drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47 #include <linux/reservation.h>
  48 #include <linux/dma-buf.h>
  49
  50 /* Primary plane formats for gen <= 3 */
  51 static const uint32_t i8xx_primary_formats[] = {
  52         DRM_FORMAT_C8,
  53         DRM_FORMAT_RGB565,
  54         DRM_FORMAT_XRGB1555,
  55         DRM_FORMAT_XRGB8888,
  56 };
  57
  58 /* Primary plane formats for gen >= 4 */
  59 static const uint32_t i965_primary_formats[] = {
  60         DRM_FORMAT_C8,
  61         DRM_FORMAT_RGB565,
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_XRGB2101010,
  65         DRM_FORMAT_XBGR2101010,
  66 };
  67
  68 static const uint32_t skl_primary_formats[] = {
  69         DRM_FORMAT_C8,
  70         DRM_FORMAT_RGB565,
  71         DRM_FORMAT_XRGB8888,
  72         DRM_FORMAT_XBGR8888,
  73         DRM_FORMAT_ARGB8888,
  74         DRM_FORMAT_ABGR8888,
  75         DRM_FORMAT_XRGB2101010,
  76         DRM_FORMAT_XBGR2101010,
  77         DRM_FORMAT_YUYV,
  78         DRM_FORMAT_YVYU,
  79         DRM_FORMAT_UYVY,
  80         DRM_FORMAT_VYUY,
  81 };
  82
  83 /* Cursor formats */
  84 static const uint32_t intel_cursor_formats[] = {
  85         DRM_FORMAT_ARGB8888,
  86 };
  87
  88 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  89
  90 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  91                                 struct intel_crtc_state *pipe_config);
  92 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  93                                    struct intel_crtc_state *pipe_config);
  94
  95 static int intel_framebuffer_init(struct drm_device *dev,
  96                                   struct intel_framebuffer *ifb,
  97                                   struct drm_mode_fb_cmd2 *mode_cmd,
  98                                   struct drm_i915_gem_object *obj);
  99 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 100 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 102                                          struct intel_link_m_n *m_n,
 103                                          struct intel_link_m_n *m2_n2);
 104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 106 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 107 static void vlv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void chv_prepare_pll(struct intel_crtc *crtc,
 110                             const struct intel_crtc_state *pipe_config);
 111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 114         struct intel_crtc_state *crtc_state);
 115 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 116                            int num_connectors);
 117 static void skylake_pfit_enable(struct intel_crtc *crtc);
 118 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 119 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 120 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 121
 122 typedef struct {
 123         int     min, max;
 124 } intel_range_t;
 125
 126 typedef struct {
 127         int     dot_limit;
 128         int     p2_slow, p2_fast;
 129 } intel_p2_t;
 130
 131 typedef struct intel_limit intel_limit_t;
 132 struct intel_limit {
 133         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 134         intel_p2_t          p2;
 135 };
 136
 137 /* returns HPLL frequency in kHz */
 138 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 139 {
 140         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 141
 142         /* Obtain SKU information */
 143         mutex_lock(&dev_priv->sb_lock);
 144         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 145                 CCK_FUSE_HPLL_FREQ_MASK;
 146         mutex_unlock(&dev_priv->sb_lock);
 147
 148         return vco_freq[hpll_freq] * 1000;
 149 }
 150
 151 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 152                                   const char *name, u32 reg)
 153 {
 154         u32 val;
 155         int divider;
 156
 157         if (dev_priv->hpll_freq == 0)
 158                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 171 }
 172
 173 int
 174 intel_pch_rawclk(struct drm_device *dev)
 175 {
 176         struct drm_i915_private *dev_priv = dev->dev_private;
 177
 178         WARN_ON(!HAS_PCH_SPLIT(dev));
 179
 180         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 181 }
 182
 183 /* hrawclock is 1/4 the FSB frequency */
 184 int intel_hrawclk(struct drm_device *dev)
 185 {
 186         struct drm_i915_private *dev_priv = dev->dev_private;
 187         uint32_t clkcfg;
 188
 189         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 190         if (IS_VALLEYVIEW(dev))
 191                 return 200;
 192
 193         clkcfg = I915_READ(CLKCFG);
 194         switch (clkcfg & CLKCFG_FSB_MASK) {
 195         case CLKCFG_FSB_400:
 196                 return 100;
 197         case CLKCFG_FSB_533:
 198                 return 133;
 199         case CLKCFG_FSB_667:
 200                 return 166;
 201         case CLKCFG_FSB_800:
 202                 return 200;
 203         case CLKCFG_FSB_1067:
 204                 return 266;
 205         case CLKCFG_FSB_1333:
 206                 return 333;
 207         /* these two are just a guess; one of them might be right */
 208         case CLKCFG_FSB_1600:
 209         case CLKCFG_FSB_1600_ALT:
 210                 return 400;
 211         default:
 212                 return 133;
 213         }
 214 }
 215
 216 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 217 {
 218         if (!IS_VALLEYVIEW(dev_priv))
 219                 return;
 220
 221         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 222                                                       CCK_CZ_CLOCK_CONTROL);
 223
 224         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 225 }
 226
 227 static inline u32 /* units of 100MHz */
 228 intel_fdi_link_freq(struct drm_device *dev)
 229 {
 230         if (IS_GEN5(dev)) {
 231                 struct drm_i915_private *dev_priv = dev->dev_private;
 232                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 233         } else
 234                 return 27;
 235 }
 236
 237 static const intel_limit_t intel_limits_i8xx_dac = {
 238         .dot = { .min = 25000, .max = 350000 },
 239         .vco = { .min = 908000, .max = 1512000 },
 240         .n = { .min = 2, .max = 16 },
 241         .m = { .min = 96, .max = 140 },
 242         .m1 = { .min = 18, .max = 26 },
 243         .m2 = { .min = 6, .max = 16 },
 244         .p = { .min = 4, .max = 128 },
 245         .p1 = { .min = 2, .max = 33 },
 246         .p2 = { .dot_limit = 165000,
 247                 .p2_slow = 4, .p2_fast = 2 },
 248 };
 249
 250 static const intel_limit_t intel_limits_i8xx_dvo = {
 251         .dot = { .min = 25000, .max = 350000 },
 252         .vco = { .min = 908000, .max = 1512000 },
 253         .n = { .min = 2, .max = 16 },
 254         .m = { .min = 96, .max = 140 },
 255         .m1 = { .min = 18, .max = 26 },
 256         .m2 = { .min = 6, .max = 16 },
 257         .p = { .min = 4, .max = 128 },
 258         .p1 = { .min = 2, .max = 33 },
 259         .p2 = { .dot_limit = 165000,
 260                 .p2_slow = 4, .p2_fast = 4 },
 261 };
 262
 263 static const intel_limit_t intel_limits_i8xx_lvds = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 1, .max = 6 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 14, .p2_fast = 7 },
 274 };
 275
 276 static const intel_limit_t intel_limits_i9xx_sdvo = {
 277         .dot = { .min = 20000, .max = 400000 },
 278         .vco = { .min = 1400000, .max = 2800000 },
 279         .n = { .min = 1, .max = 6 },
 280         .m = { .min = 70, .max = 120 },
 281         .m1 = { .min = 8, .max = 18 },
 282         .m2 = { .min = 3, .max = 7 },
 283         .p = { .min = 5, .max = 80 },
 284         .p1 = { .min = 1, .max = 8 },
 285         .p2 = { .dot_limit = 200000,
 286                 .p2_slow = 10, .p2_fast = 5 },
 287 };
 288
 289 static const intel_limit_t intel_limits_i9xx_lvds = {
 290         .dot = { .min = 20000, .max = 400000 },
 291         .vco = { .min = 1400000, .max = 2800000 },
 292         .n = { .min = 1, .max = 6 },
 293         .m = { .min = 70, .max = 120 },
 294         .m1 = { .min = 8, .max = 18 },
 295         .m2 = { .min = 3, .max = 7 },
 296         .p = { .min = 7, .max = 98 },
 297         .p1 = { .min = 1, .max = 8 },
 298         .p2 = { .dot_limit = 112000,
 299                 .p2_slow = 14, .p2_fast = 7 },
 300 };
 301
 302
 303 static const intel_limit_t intel_limits_g4x_sdvo = {
 304         .dot = { .min = 25000, .max = 270000 },
 305         .vco = { .min = 1750000, .max = 3500000},
 306         .n = { .min = 1, .max = 4 },
 307         .m = { .min = 104, .max = 138 },
 308         .m1 = { .min = 17, .max = 23 },
 309         .m2 = { .min = 5, .max = 11 },
 310         .p = { .min = 10, .max = 30 },
 311         .p1 = { .min = 1, .max = 3},
 312         .p2 = { .dot_limit = 270000,
 313                 .p2_slow = 10,
 314                 .p2_fast = 10
 315         },
 316 };
 317
 318 static const intel_limit_t intel_limits_g4x_hdmi = {
 319         .dot = { .min = 22000, .max = 400000 },
 320         .vco = { .min = 1750000, .max = 3500000},
 321         .n = { .min = 1, .max = 4 },
 322         .m = { .min = 104, .max = 138 },
 323         .m1 = { .min = 16, .max = 23 },
 324         .m2 = { .min = 5, .max = 11 },
 325         .p = { .min = 5, .max = 80 },
 326         .p1 = { .min = 1, .max = 8},
 327         .p2 = { .dot_limit = 165000,
 328                 .p2_slow = 10, .p2_fast = 5 },
 329 };
 330
 331 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 332         .dot = { .min = 20000, .max = 115000 },
 333         .vco = { .min = 1750000, .max = 3500000 },
 334         .n = { .min = 1, .max = 3 },
 335         .m = { .min = 104, .max = 138 },
 336         .m1 = { .min = 17, .max = 23 },
 337         .m2 = { .min = 5, .max = 11 },
 338         .p = { .min = 28, .max = 112 },
 339         .p1 = { .min = 2, .max = 8 },
 340         .p2 = { .dot_limit = 0,
 341                 .p2_slow = 14, .p2_fast = 14
 342         },
 343 };
 344
 345 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 346         .dot = { .min = 80000, .max = 224000 },
 347         .vco = { .min = 1750000, .max = 3500000 },
 348         .n = { .min = 1, .max = 3 },
 349         .m = { .min = 104, .max = 138 },
 350         .m1 = { .min = 17, .max = 23 },
 351         .m2 = { .min = 5, .max = 11 },
 352         .p = { .min = 14, .max = 42 },
 353         .p1 = { .min = 2, .max = 6 },
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 7, .p2_fast = 7
 356         },
 357 };
 358
 359 static const intel_limit_t intel_limits_pineview_sdvo = {
 360         .dot = { .min = 20000, .max = 400000},
 361         .vco = { .min = 1700000, .max = 3500000 },
 362         /* Pineview's Ncounter is a ring counter */
 363         .n = { .min = 3, .max = 6 },
 364         .m = { .min = 2, .max = 256 },
 365         /* Pineview only has one combined m divider, which we treat as m2. */
 366         .m1 = { .min = 0, .max = 0 },
 367         .m2 = { .min = 0, .max = 254 },
 368         .p = { .min = 5, .max = 80 },
 369         .p1 = { .min = 1, .max = 8 },
 370         .p2 = { .dot_limit = 200000,
 371                 .p2_slow = 10, .p2_fast = 5 },
 372 };
 373
 374 static const intel_limit_t intel_limits_pineview_lvds = {
 375         .dot = { .min = 20000, .max = 400000 },
 376         .vco = { .min = 1700000, .max = 3500000 },
 377         .n = { .min = 3, .max = 6 },
 378         .m = { .min = 2, .max = 256 },
 379         .m1 = { .min = 0, .max = 0 },
 380         .m2 = { .min = 0, .max = 254 },
 381         .p = { .min = 7, .max = 112 },
 382         .p1 = { .min = 1, .max = 8 },
 383         .p2 = { .dot_limit = 112000,
 384                 .p2_slow = 14, .p2_fast = 14 },
 385 };
 386
 387 /* Ironlake / Sandybridge
 388  *
 389  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 390  * the range value for them is (actual_value - 2).
 391  */
 392 static const intel_limit_t intel_limits_ironlake_dac = {
 393         .dot = { .min = 25000, .max = 350000 },
 394         .vco = { .min = 1760000, .max = 3510000 },
 395         .n = { .min = 1, .max = 5 },
 396         .m = { .min = 79, .max = 127 },
 397         .m1 = { .min = 12, .max = 22 },
 398         .m2 = { .min = 5, .max = 9 },
 399         .p = { .min = 5, .max = 80 },
 400         .p1 = { .min = 1, .max = 8 },
 401         .p2 = { .dot_limit = 225000,
 402                 .p2_slow = 10, .p2_fast = 5 },
 403 };
 404
 405 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 406         .dot = { .min = 25000, .max = 350000 },
 407         .vco = { .min = 1760000, .max = 3510000 },
 408         .n = { .min = 1, .max = 3 },
 409         .m = { .min = 79, .max = 118 },
 410         .m1 = { .min = 12, .max = 22 },
 411         .m2 = { .min = 5, .max = 9 },
 412         .p = { .min = 28, .max = 112 },
 413         .p1 = { .min = 2, .max = 8 },
 414         .p2 = { .dot_limit = 225000,
 415                 .p2_slow = 14, .p2_fast = 14 },
 416 };
 417
 418 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 3 },
 422         .m = { .min = 79, .max = 127 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 14, .max = 56 },
 426         .p1 = { .min = 2, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 7, .p2_fast = 7 },
 429 };
 430
 431 /* LVDS 100mhz refclk limits. */
 432 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 433         .dot = { .min = 25000, .max = 350000 },
 434         .vco = { .min = 1760000, .max = 3510000 },
 435         .n = { .min = 1, .max = 2 },
 436         .m = { .min = 79, .max = 126 },
 437         .m1 = { .min = 12, .max = 22 },
 438         .m2 = { .min = 5, .max = 9 },
 439         .p = { .min = 28, .max = 112 },
 440         .p1 = { .min = 2, .max = 8 },
 441         .p2 = { .dot_limit = 225000,
 442                 .p2_slow = 14, .p2_fast = 14 },
 443 };
 444
 445 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 446         .dot = { .min = 25000, .max = 350000 },
 447         .vco = { .min = 1760000, .max = 3510000 },
 448         .n = { .min = 1, .max = 3 },
 449         .m = { .min = 79, .max = 126 },
 450         .m1 = { .min = 12, .max = 22 },
 451         .m2 = { .min = 5, .max = 9 },
 452         .p = { .min = 14, .max = 42 },
 453         .p1 = { .min = 2, .max = 6 },
 454         .p2 = { .dot_limit = 225000,
 455                 .p2_slow = 7, .p2_fast = 7 },
 456 };
 457
 458 static const intel_limit_t intel_limits_vlv = {
 459          /*
 460           * These are the data rate limits (measured in fast clocks)
 461           * since those are the strictest limits we have. The fast
 462           * clock and actual rate limits are more relaxed, so checking
 463           * them would make no difference.
 464           */
 465         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 466         .vco = { .min = 4000000, .max = 6000000 },
 467         .n = { .min = 1, .max = 7 },
 468         .m1 = { .min = 2, .max = 3 },
 469         .m2 = { .min = 11, .max = 156 },
 470         .p1 = { .min = 2, .max = 3 },
 471         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 472 };
 473
 474 static const intel_limit_t intel_limits_chv = {
 475         /*
 476          * These are the data rate limits (measured in fast clocks)
 477          * since those are the strictest limits we have.  The fast
 478          * clock and actual rate limits are more relaxed, so checking
 479          * them would make no difference.
 480          */
 481         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 482         .vco = { .min = 4800000, .max = 6480000 },
 483         .n = { .min = 1, .max = 1 },
 484         .m1 = { .min = 2, .max = 2 },
 485         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 486         .p1 = { .min = 2, .max = 4 },
 487         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 488 };
 489
 490 static const intel_limit_t intel_limits_bxt = {
 491         /* FIXME: find real dot limits */
 492         .dot = { .min = 0, .max = INT_MAX },
 493         .vco = { .min = 4800000, .max = 6700000 },
 494         .n = { .min = 1, .max = 1 },
 495         .m1 = { .min = 2, .max = 2 },
 496         /* FIXME: find real m2 limits */
 497         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 498         .p1 = { .min = 2, .max = 4 },
 499         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 500 };
 501
 502 static bool
 503 needs_modeset(struct drm_crtc_state *state)
 504 {
 505         return drm_atomic_crtc_needs_modeset(state);
 506 }
 507
 508 /**
 509  * Returns whether any output on the specified pipe is of the specified type
 510  */
 511 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 512 {
 513         struct drm_device *dev = crtc->base.dev;
 514         struct intel_encoder *encoder;
 515
 516         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 517                 if (encoder->type == type)
 518                         return true;
 519
 520         return false;
 521 }
 522
 523 /**
 524  * Returns whether any output on the specified pipe will have the specified
 525  * type after a staged modeset is complete, i.e., the same as
 526  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 527  * encoder->crtc.
 528  */
 529 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 530                                       int type)
 531 {
 532         struct drm_atomic_state *state = crtc_state->base.state;
 533         struct drm_connector *connector;
 534         struct drm_connector_state *connector_state;
 535         struct intel_encoder *encoder;
 536         int i, num_connectors = 0;
 537
 538         for_each_connector_in_state(state, connector, connector_state, i) {
 539                 if (connector_state->crtc != crtc_state->base.crtc)
 540                         continue;
 541
 542                 num_connectors++;
 543
 544                 encoder = to_intel_encoder(connector_state->best_encoder);
 545                 if (encoder->type == type)
 546                         return true;
 547         }
 548
 549         WARN_ON(num_connectors == 0);
 550
 551         return false;
 552 }
 553
 554 static const intel_limit_t *
 555 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 556 {
 557         struct drm_device *dev = crtc_state->base.crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 561                 if (intel_is_dual_link_lvds(dev)) {
 562                         if (refclk == 100000)
 563                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 564                         else
 565                                 limit = &intel_limits_ironlake_dual_lvds;
 566                 } else {
 567                         if (refclk == 100000)
 568                                 limit = &intel_limits_ironlake_single_lvds_100m;
 569                         else
 570                                 limit = &intel_limits_ironlake_single_lvds;
 571                 }
 572         } else
 573                 limit = &intel_limits_ironlake_dac;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *
 579 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 580 {
 581         struct drm_device *dev = crtc_state->base.crtc->dev;
 582         const intel_limit_t *limit;
 583
 584         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 585                 if (intel_is_dual_link_lvds(dev))
 586                         limit = &intel_limits_g4x_dual_channel_lvds;
 587                 else
 588                         limit = &intel_limits_g4x_single_channel_lvds;
 589         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 590                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 591                 limit = &intel_limits_g4x_hdmi;
 592         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 593                 limit = &intel_limits_g4x_sdvo;
 594         } else /* The option is for other outputs */
 595                 limit = &intel_limits_i9xx_sdvo;
 596
 597         return limit;
 598 }
 599
 600 static const intel_limit_t *
 601 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 602 {
 603         struct drm_device *dev = crtc_state->base.crtc->dev;
 604         const intel_limit_t *limit;
 605
 606         if (IS_BROXTON(dev))
 607                 limit = &intel_limits_bxt;
 608         else if (HAS_PCH_SPLIT(dev))
 609                 limit = intel_ironlake_limit(crtc_state, refclk);
 610         else if (IS_G4X(dev)) {
 611                 limit = intel_g4x_limit(crtc_state);
 612         } else if (IS_PINEVIEW(dev)) {
 613                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 614                         limit = &intel_limits_pineview_lvds;
 615                 else
 616                         limit = &intel_limits_pineview_sdvo;
 617         } else if (IS_CHERRYVIEW(dev)) {
 618                 limit = &intel_limits_chv;
 619         } else if (IS_VALLEYVIEW(dev)) {
 620                 limit = &intel_limits_vlv;
 621         } else if (!IS_GEN2(dev)) {
 622                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 623                         limit = &intel_limits_i9xx_lvds;
 624                 else
 625                         limit = &intel_limits_i9xx_sdvo;
 626         } else {
 627                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 628                         limit = &intel_limits_i8xx_lvds;
 629                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 630                         limit = &intel_limits_i8xx_dvo;
 631                 else
 632                         limit = &intel_limits_i8xx_dac;
 633         }
 634         return limit;
 635 }
 636
 637 /*
 638  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 639  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 640  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 641  * The helpers' return value is the rate of the clock that is fed to the
 642  * display engine's pipe which can be the above fast dot clock rate or a
 643  * divided-down version of it.
 644  */
 645 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 646 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 647 {
 648         clock->m = clock->m2 + 2;
 649         clock->p = clock->p1 * clock->p2;
 650         if (WARN_ON(clock->n == 0 || clock->p == 0))
 651                 return 0;
 652         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 653         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 654
 655         return clock->dot;
 656 }
 657
 658 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 659 {
 660         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 661 }
 662
 663 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 664 {
 665         clock->m = i9xx_dpll_compute_m(clock);
 666         clock->p = clock->p1 * clock->p2;
 667         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 668                 return 0;
 669         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 670         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 671
 672         return clock->dot;
 673 }
 674
 675 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 676 {
 677         clock->m = clock->m1 * clock->m2;
 678         clock->p = clock->p1 * clock->p2;
 679         if (WARN_ON(clock->n == 0 || clock->p == 0))
 680                 return 0;
 681         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 682         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 683
 684         return clock->dot / 5;
 685 }
 686
 687 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 688 {
 689         clock->m = clock->m1 * clock->m2;
 690         clock->p = clock->p1 * clock->p2;
 691         if (WARN_ON(clock->n == 0 || clock->p == 0))
 692                 return 0;
 693         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 694                         clock->n << 22);
 695         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 696
 697         return clock->dot / 5;
 698 }
 699
 700 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 701 /**
 702  * Returns whether the given set of divisors are valid for a given refclk with
 703  * the given connectors.
 704  */
 705
 706 static bool intel_PLL_is_valid(struct drm_device *dev,
 707                                const intel_limit_t *limit,
 708                                const intel_clock_t *clock)
 709 {
 710         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 711                 INTELPllInvalid("n out of range\n");
 712         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 713                 INTELPllInvalid("p1 out of range\n");
 714         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 715                 INTELPllInvalid("m2 out of range\n");
 716         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 717                 INTELPllInvalid("m1 out of range\n");
 718
 719         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 720                 if (clock->m1 <= clock->m2)
 721                         INTELPllInvalid("m1 <= m2\n");
 722
 723         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 724                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 725                         INTELPllInvalid("p out of range\n");
 726                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 727                         INTELPllInvalid("m out of range\n");
 728         }
 729
 730         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 731                 INTELPllInvalid("vco out of range\n");
 732         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 733          * connector, etc., rather than just a single range.
 734          */
 735         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 736                 INTELPllInvalid("dot out of range\n");
 737
 738         return true;
 739 }
 740
 741 static int
 742 i9xx_select_p2_div(const intel_limit_t *limit,
 743                    const struct intel_crtc_state *crtc_state,
 744                    int target)
 745 {
 746         struct drm_device *dev = crtc_state->base.crtc->dev;
 747
 748         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 749                 /*
 750                  * For LVDS just rely on its current settings for dual-channel.
 751                  * We haven't figured out how to reliably set up different
 752                  * single/dual channel state, if we even can.
 753                  */
 754                 if (intel_is_dual_link_lvds(dev))
 755                         return limit->p2.p2_fast;
 756                 else
 757                         return limit->p2.p2_slow;
 758         } else {
 759                 if (target < limit->p2.dot_limit)
 760                         return limit->p2.p2_slow;
 761                 else
 762                         return limit->p2.p2_fast;
 763         }
 764 }
 765
 766 static bool
 767 i9xx_find_best_dpll(const intel_limit_t *limit,
 768                     struct intel_crtc_state *crtc_state,
 769                     int target, int refclk, intel_clock_t *match_clock,
 770                     intel_clock_t *best_clock)
 771 {
 772         struct drm_device *dev = crtc_state->base.crtc->dev;
 773         intel_clock_t clock;
 774         int err = target;
 775
 776         memset(best_clock, 0, sizeof(*best_clock));
 777
 778         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 779
 780         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 781              clock.m1++) {
 782                 for (clock.m2 = limit->m2.min;
 783                      clock.m2 <= limit->m2.max; clock.m2++) {
 784                         if (clock.m2 >= clock.m1)
 785                                 break;
 786                         for (clock.n = limit->n.min;
 787                              clock.n <= limit->n.max; clock.n++) {
 788                                 for (clock.p1 = limit->p1.min;
 789                                         clock.p1 <= limit->p1.max; clock.p1++) {
 790                                         int this_err;
 791
 792                                         i9xx_calc_dpll_params(refclk, &clock);
 793                                         if (!intel_PLL_is_valid(dev, limit,
 794                                                                 &clock))
 795                                                 continue;
 796                                         if (match_clock &&
 797                                             clock.p != match_clock->p)
 798                                                 continue;
 799
 800                                         this_err = abs(clock.dot - target);
 801                                         if (this_err < err) {
 802                                                 *best_clock = clock;
 803                                                 err = this_err;
 804                                         }
 805                                 }
 806                         }
 807                 }
 808         }
 809
 810         return (err != target);
 811 }
 812
 813 static bool
 814 pnv_find_best_dpll(const intel_limit_t *limit,
 815                    struct intel_crtc_state *crtc_state,
 816                    int target, int refclk, intel_clock_t *match_clock,
 817                    intel_clock_t *best_clock)
 818 {
 819         struct drm_device *dev = crtc_state->base.crtc->dev;
 820         intel_clock_t clock;
 821         int err = target;
 822
 823         memset(best_clock, 0, sizeof(*best_clock));
 824
 825         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 826
 827         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 828              clock.m1++) {
 829                 for (clock.m2 = limit->m2.min;
 830                      clock.m2 <= limit->m2.max; clock.m2++) {
 831                         for (clock.n = limit->n.min;
 832                              clock.n <= limit->n.max; clock.n++) {
 833                                 for (clock.p1 = limit->p1.min;
 834                                         clock.p1 <= limit->p1.max; clock.p1++) {
 835                                         int this_err;
 836
 837                                         pnv_calc_dpll_params(refclk, &clock);
 838                                         if (!intel_PLL_is_valid(dev, limit,
 839                                                                 &clock))
 840                                                 continue;
 841                                         if (match_clock &&
 842                                             clock.p != match_clock->p)
 843                                                 continue;
 844
 845                                         this_err = abs(clock.dot - target);
 846                                         if (this_err < err) {
 847                                                 *best_clock = clock;
 848                                                 err = this_err;
 849                                         }
 850                                 }
 851                         }
 852                 }
 853         }
 854
 855         return (err != target);
 856 }
 857
 858 static bool
 859 g4x_find_best_dpll(const intel_limit_t *limit,
 860                    struct intel_crtc_state *crtc_state,
 861                    int target, int refclk, intel_clock_t *match_clock,
 862                    intel_clock_t *best_clock)
 863 {
 864         struct drm_device *dev = crtc_state->base.crtc->dev;
 865         intel_clock_t clock;
 866         int max_n;
 867         bool found = false;
 868         /* approximately equals target * 0.00585 */
 869         int err_most = (target >> 8) + (target >> 9);
 870
 871         memset(best_clock, 0, sizeof(*best_clock));
 872
 873         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 874
 875         max_n = limit->n.max;
 876         /* based on hardware requirement, prefer smaller n to precision */
 877         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 878                 /* based on hardware requirement, prefere larger m1,m2 */
 879                 for (clock.m1 = limit->m1.max;
 880                      clock.m1 >= limit->m1.min; clock.m1--) {
 881                         for (clock.m2 = limit->m2.max;
 882                              clock.m2 >= limit->m2.min; clock.m2--) {
 883                                 for (clock.p1 = limit->p1.max;
 884                                      clock.p1 >= limit->p1.min; clock.p1--) {
 885                                         int this_err;
 886
 887                                         i9xx_calc_dpll_params(refclk, &clock);
 888                                         if (!intel_PLL_is_valid(dev, limit,
 889                                                                 &clock))
 890                                                 continue;
 891
 892                                         this_err = abs(clock.dot - target);
 893                                         if (this_err < err_most) {
 894                                                 *best_clock = clock;
 895                                                 err_most = this_err;
 896                                                 max_n = clock.n;
 897                                                 found = true;
 898                                         }
 899                                 }
 900                         }
 901                 }
 902         }
 903         return found;
 904 }
 905
 906 /*
 907  * Check if the calculated PLL configuration is more optimal compared to the
 908  * best configuration and error found so far. Return the calculated error.
 909  */
 910 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 911                                const intel_clock_t *calculated_clock,
 912                                const intel_clock_t *best_clock,
 913                                unsigned int best_error_ppm,
 914                                unsigned int *error_ppm)
 915 {
 916         /*
 917          * For CHV ignore the error and consider only the P value.
 918          * Prefer a bigger P value based on HW requirements.
 919          */
 920         if (IS_CHERRYVIEW(dev)) {
 921                 *error_ppm = 0;
 922
 923                 return calculated_clock->p > best_clock->p;
 924         }
 925
 926         if (WARN_ON_ONCE(!target_freq))
 927                 return false;
 928
 929         *error_ppm = div_u64(1000000ULL *
 930                                 abs(target_freq - calculated_clock->dot),
 931                              target_freq);
 932         /*
 933          * Prefer a better P value over a better (smaller) error if the error
 934          * is small. Ensure this preference for future configurations too by
 935          * setting the error to 0.
 936          */
 937         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 938                 *error_ppm = 0;
 939
 940                 return true;
 941         }
 942
 943         return *error_ppm + 10 < best_error_ppm;
 944 }
 945
 946 static bool
 947 vlv_find_best_dpll(const intel_limit_t *limit,
 948                    struct intel_crtc_state *crtc_state,
 949                    int target, int refclk, intel_clock_t *match_clock,
 950                    intel_clock_t *best_clock)
 951 {
 952         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 953         struct drm_device *dev = crtc->base.dev;
 954         intel_clock_t clock;
 955         unsigned int bestppm = 1000000;
 956         /* min update 19.2 MHz */
 957         int max_n = min(limit->n.max, refclk / 19200);
 958         bool found = false;
 959
 960         target *= 5; /* fast clock */
 961
 962         memset(best_clock, 0, sizeof(*best_clock));
 963
 964         /* based on hardware requirement, prefer smaller n to precision */
 965         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 966                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 967                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 968                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 969                                 clock.p = clock.p1 * clock.p2;
 970                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 971                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 972                                         unsigned int ppm;
 973
 974                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 975                                                                      refclk * clock.m1);
 976
 977                                         vlv_calc_dpll_params(refclk, &clock);
 978
 979                                         if (!intel_PLL_is_valid(dev, limit,
 980                                                                 &clock))
 981                                                 continue;
 982
 983                                         if (!vlv_PLL_is_optimal(dev, target,
 984                                                                 &clock,
 985                                                                 best_clock,
 986                                                                 bestppm, &ppm))
 987                                                 continue;
 988
 989                                         *best_clock = clock;
 990                                         bestppm = ppm;
 991                                         found = true;
 992                                 }
 993                         }
 994                 }
 995         }
 996
 997         return found;
 998 }
 999
1000 static bool
1001 chv_find_best_dpll(const intel_limit_t *limit,
1002                    struct intel_crtc_state *crtc_state,
1003                    int target, int refclk, intel_clock_t *match_clock,
1004                    intel_clock_t *best_clock)
1005 {
1006         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1007         struct drm_device *dev = crtc->base.dev;
1008         unsigned int best_error_ppm;
1009         intel_clock_t clock;
1010         uint64_t m2;
1011         int found = false;
1012
1013         memset(best_clock, 0, sizeof(*best_clock));
1014         best_error_ppm = 1000000;
1015
1016         /*
1017          * Based on hardware doc, the n always set to 1, and m1 always
1018          * set to 2.  If requires to support 200Mhz refclk, we need to
1019          * revisit this because n may not 1 anymore.
1020          */
1021         clock.n = 1, clock.m1 = 2;
1022         target *= 5;    /* fast clock */
1023
1024         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1025                 for (clock.p2 = limit->p2.p2_fast;
1026                                 clock.p2 >= limit->p2.p2_slow;
1027                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1028                         unsigned int error_ppm;
1029
1030                         clock.p = clock.p1 * clock.p2;
1031
1032                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1033                                         clock.n) << 22, refclk * clock.m1);
1034
1035                         if (m2 > INT_MAX/clock.m1)
1036                                 continue;
1037
1038                         clock.m2 = m2;
1039
1040                         chv_calc_dpll_params(refclk, &clock);
1041
1042                         if (!intel_PLL_is_valid(dev, limit, &clock))
1043                                 continue;
1044
1045                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1046                                                 best_error_ppm, &error_ppm))
1047                                 continue;
1048
1049                         *best_clock = clock;
1050                         best_error_ppm = error_ppm;
1051                         found = true;
1052                 }
1053         }
1054
1055         return found;
1056 }
1057
1058 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1059                         intel_clock_t *best_clock)
1060 {
1061         int refclk = i9xx_get_refclk(crtc_state, 0);
1062
1063         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1064                                   target_clock, refclk, NULL, best_clock);
1065 }
1066
1067 bool intel_crtc_active(struct drm_crtc *crtc)
1068 {
1069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1070
1071         /* Be paranoid as we can arrive here with only partial
1072          * state retrieved from the hardware during setup.
1073          *
1074          * We can ditch the adjusted_mode.crtc_clock check as soon
1075          * as Haswell has gained clock readout/fastboot support.
1076          *
1077          * We can ditch the crtc->primary->fb check as soon as we can
1078          * properly reconstruct framebuffers.
1079          *
1080          * FIXME: The intel_crtc->active here should be switched to
1081          * crtc->state->active once we have proper CRTC states wired up
1082          * for atomic.
1083          */
1084         return intel_crtc->active && crtc->primary->state->fb &&
1085                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1086 }
1087
1088 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1089                                              enum pipe pipe)
1090 {
1091         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1093
1094         return intel_crtc->config->cpu_transcoder;
1095 }
1096
1097 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1098 {
1099         struct drm_i915_private *dev_priv = dev->dev_private;
1100         i915_reg_t reg = PIPEDSL(pipe);
1101         u32 line1, line2;
1102         u32 line_mask;
1103
1104         if (IS_GEN2(dev))
1105                 line_mask = DSL_LINEMASK_GEN2;
1106         else
1107                 line_mask = DSL_LINEMASK_GEN3;
1108
1109         line1 = I915_READ(reg) & line_mask;
1110         msleep(5);
1111         line2 = I915_READ(reg) & line_mask;
1112
1113         return line1 == line2;
1114 }
1115
1116 /*
1117  * intel_wait_for_pipe_off - wait for pipe to turn off
1118  * @crtc: crtc whose pipe to wait for
1119  *
1120  * After disabling a pipe, we can't wait for vblank in the usual way,
1121  * spinning on the vblank interrupt status bit, since we won't actually
1122  * see an interrupt when the pipe is disabled.
1123  *
1124  * On Gen4 and above:
1125  *   wait for the pipe register state bit to turn off
1126  *
1127  * Otherwise:
1128  *   wait for the display line value to settle (it usually
1129  *   ends up stopping at the start of the next frame).
1130  *
1131  */
1132 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1133 {
1134         struct drm_device *dev = crtc->base.dev;
1135         struct drm_i915_private *dev_priv = dev->dev_private;
1136         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1137         enum pipe pipe = crtc->pipe;
1138
1139         if (INTEL_INFO(dev)->gen >= 4) {
1140                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1141
1142                 /* Wait for the Pipe State to go off */
1143                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1144                              100))
1145                         WARN(1, "pipe_off wait timed out\n");
1146         } else {
1147                 /* Wait for the display line to settle */
1148                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1149                         WARN(1, "pipe_off wait timed out\n");
1150         }
1151 }
1152
1153 static const char *state_string(bool enabled)
1154 {
1155         return enabled ? "on" : "off";
1156 }
1157
1158 /* Only for pre-ILK configs */
1159 void assert_pll(struct drm_i915_private *dev_priv,
1160                 enum pipe pipe, bool state)
1161 {
1162         u32 val;
1163         bool cur_state;
1164
1165         val = I915_READ(DPLL(pipe));
1166         cur_state = !!(val & DPLL_VCO_ENABLE);
1167         I915_STATE_WARN(cur_state != state,
1168              "PLL state assertion failure (expected %s, current %s)\n",
1169              state_string(state), state_string(cur_state));
1170 }
1171
1172 /* XXX: the dsi pll is shared between MIPI DSI ports */
1173 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1174 {
1175         u32 val;
1176         bool cur_state;
1177
1178         mutex_lock(&dev_priv->sb_lock);
1179         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1180         mutex_unlock(&dev_priv->sb_lock);
1181
1182         cur_state = val & DSI_PLL_VCO_EN;
1183         I915_STATE_WARN(cur_state != state,
1184              "DSI PLL state assertion failure (expected %s, current %s)\n",
1185              state_string(state), state_string(cur_state));
1186 }
1187 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1188 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1189
1190 struct intel_shared_dpll *
1191 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1192 {
1193         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1194
1195         if (crtc->config->shared_dpll < 0)
1196                 return NULL;
1197
1198         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1199 }
1200
1201 /* For ILK+ */
1202 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1203                         struct intel_shared_dpll *pll,
1204                         bool state)
1205 {
1206         bool cur_state;
1207         struct intel_dpll_hw_state hw_state;
1208
1209         if (WARN (!pll,
1210                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1211                 return;
1212
1213         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1214         I915_STATE_WARN(cur_state != state,
1215              "%s assertion failure (expected %s, current %s)\n",
1216              pll->name, state_string(state), state_string(cur_state));
1217 }
1218
1219 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1220                           enum pipe pipe, bool state)
1221 {
1222         bool cur_state;
1223         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224                                                                       pipe);
1225
1226         if (HAS_DDI(dev_priv->dev)) {
1227                 /* DDI does not have a specific FDI_TX register */
1228                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1229                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1230         } else {
1231                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1232                 cur_state = !!(val & FDI_TX_ENABLE);
1233         }
1234         I915_STATE_WARN(cur_state != state,
1235              "FDI TX state assertion failure (expected %s, current %s)\n",
1236              state_string(state), state_string(cur_state));
1237 }
1238 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1239 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1240
1241 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1242                           enum pipe pipe, bool state)
1243 {
1244         u32 val;
1245         bool cur_state;
1246
1247         val = I915_READ(FDI_RX_CTL(pipe));
1248         cur_state = !!(val & FDI_RX_ENABLE);
1249         I915_STATE_WARN(cur_state != state,
1250              "FDI RX state assertion failure (expected %s, current %s)\n",
1251              state_string(state), state_string(cur_state));
1252 }
1253 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1254 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1255
1256 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1257                                       enum pipe pipe)
1258 {
1259         u32 val;
1260
1261         /* ILK FDI PLL is always enabled */
1262         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1263                 return;
1264
1265         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1266         if (HAS_DDI(dev_priv->dev))
1267                 return;
1268
1269         val = I915_READ(FDI_TX_CTL(pipe));
1270         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1271 }
1272
1273 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1274                        enum pipe pipe, bool state)
1275 {
1276         u32 val;
1277         bool cur_state;
1278
1279         val = I915_READ(FDI_RX_CTL(pipe));
1280         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1281         I915_STATE_WARN(cur_state != state,
1282              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1283              state_string(state), state_string(cur_state));
1284 }
1285
1286 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1287                            enum pipe pipe)
1288 {
1289         struct drm_device *dev = dev_priv->dev;
1290         i915_reg_t pp_reg;
1291         u32 val;
1292         enum pipe panel_pipe = PIPE_A;
1293         bool locked = true;
1294
1295         if (WARN_ON(HAS_DDI(dev)))
1296                 return;
1297
1298         if (HAS_PCH_SPLIT(dev)) {
1299                 u32 port_sel;
1300
1301                 pp_reg = PCH_PP_CONTROL;
1302                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1303
1304                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1305                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1306                         panel_pipe = PIPE_B;
1307                 /* XXX: else fix for eDP */
1308         } else if (IS_VALLEYVIEW(dev)) {
1309                 /* presumably write lock depends on pipe, not port select */
1310                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1311                 panel_pipe = pipe;
1312         } else {
1313                 pp_reg = PP_CONTROL;
1314                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1315                         panel_pipe = PIPE_B;
1316         }
1317
1318         val = I915_READ(pp_reg);
1319         if (!(val & PANEL_POWER_ON) ||
1320             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1321                 locked = false;
1322
1323         I915_STATE_WARN(panel_pipe == pipe && locked,
1324              "panel assertion failure, pipe %c regs locked\n",
1325              pipe_name(pipe));
1326 }
1327
1328 static void assert_cursor(struct drm_i915_private *dev_priv,
1329                           enum pipe pipe, bool state)
1330 {
1331         struct drm_device *dev = dev_priv->dev;
1332         bool cur_state;
1333
1334         if (IS_845G(dev) || IS_I865G(dev))
1335                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1336         else
1337                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1338
1339         I915_STATE_WARN(cur_state != state,
1340              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1341              pipe_name(pipe), state_string(state), state_string(cur_state));
1342 }
1343 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1344 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1345
1346 void assert_pipe(struct drm_i915_private *dev_priv,
1347                  enum pipe pipe, bool state)
1348 {
1349         bool cur_state;
1350         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1351                                                                       pipe);
1352
1353         /* if we need the pipe quirk it must be always on */
1354         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1355             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1356                 state = true;
1357
1358         if (!intel_display_power_is_enabled(dev_priv,
1359                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1360                 cur_state = false;
1361         } else {
1362                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1363                 cur_state = !!(val & PIPECONF_ENABLE);
1364         }
1365
1366         I915_STATE_WARN(cur_state != state,
1367              "pipe %c assertion failure (expected %s, current %s)\n",
1368              pipe_name(pipe), state_string(state), state_string(cur_state));
1369 }
1370
1371 static void assert_plane(struct drm_i915_private *dev_priv,
1372                          enum plane plane, bool state)
1373 {
1374         u32 val;
1375         bool cur_state;
1376
1377         val = I915_READ(DSPCNTR(plane));
1378         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1379         I915_STATE_WARN(cur_state != state,
1380              "plane %c assertion failure (expected %s, current %s)\n",
1381              plane_name(plane), state_string(state), state_string(cur_state));
1382 }
1383
1384 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1385 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1386
1387 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1388                                    enum pipe pipe)
1389 {
1390         struct drm_device *dev = dev_priv->dev;
1391         int i;
1392
1393         /* Primary planes are fixed to pipes on gen4+ */
1394         if (INTEL_INFO(dev)->gen >= 4) {
1395                 u32 val = I915_READ(DSPCNTR(pipe));
1396                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1397                      "plane %c assertion failure, should be disabled but not\n",
1398                      plane_name(pipe));
1399                 return;
1400         }
1401
1402         /* Need to check both planes against the pipe */
1403         for_each_pipe(dev_priv, i) {
1404                 u32 val = I915_READ(DSPCNTR(i));
1405                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1406                         DISPPLANE_SEL_PIPE_SHIFT;
1407                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1408                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1409                      plane_name(i), pipe_name(pipe));
1410         }
1411 }
1412
1413 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1414                                     enum pipe pipe)
1415 {
1416         struct drm_device *dev = dev_priv->dev;
1417         int sprite;
1418
1419         if (INTEL_INFO(dev)->gen >= 9) {
1420                 for_each_sprite(dev_priv, pipe, sprite) {
1421                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1422                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1423                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1424                              sprite, pipe_name(pipe));
1425                 }
1426         } else if (IS_VALLEYVIEW(dev)) {
1427                 for_each_sprite(dev_priv, pipe, sprite) {
1428                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1429                         I915_STATE_WARN(val & SP_ENABLE,
1430                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431                              sprite_name(pipe, sprite), pipe_name(pipe));
1432                 }
1433         } else if (INTEL_INFO(dev)->gen >= 7) {
1434                 u32 val = I915_READ(SPRCTL(pipe));
1435                 I915_STATE_WARN(val & SPRITE_ENABLE,
1436                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1437                      plane_name(pipe), pipe_name(pipe));
1438         } else if (INTEL_INFO(dev)->gen >= 5) {
1439                 u32 val = I915_READ(DVSCNTR(pipe));
1440                 I915_STATE_WARN(val & DVS_ENABLE,
1441                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1442                      plane_name(pipe), pipe_name(pipe));
1443         }
1444 }
1445
1446 static void assert_vblank_disabled(struct drm_crtc *crtc)
1447 {
1448         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1449                 drm_crtc_vblank_put(crtc);
1450 }
1451
1452 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1453 {
1454         u32 val;
1455         bool enabled;
1456
1457         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1458
1459         val = I915_READ(PCH_DREF_CONTROL);
1460         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1461                             DREF_SUPERSPREAD_SOURCE_MASK));
1462         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1463 }
1464
1465 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1466                                            enum pipe pipe)
1467 {
1468         u32 val;
1469         bool enabled;
1470
1471         val = I915_READ(PCH_TRANSCONF(pipe));
1472         enabled = !!(val & TRANS_ENABLE);
1473         I915_STATE_WARN(enabled,
1474              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1475              pipe_name(pipe));
1476 }
1477
1478 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1479                             enum pipe pipe, u32 port_sel, u32 val)
1480 {
1481         if ((val & DP_PORT_EN) == 0)
1482                 return false;
1483
1484         if (HAS_PCH_CPT(dev_priv->dev)) {
1485                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1486                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1487                         return false;
1488         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1489                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1490                         return false;
1491         } else {
1492                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1493                         return false;
1494         }
1495         return true;
1496 }
1497
1498 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1499                               enum pipe pipe, u32 val)
1500 {
1501         if ((val & SDVO_ENABLE) == 0)
1502                 return false;
1503
1504         if (HAS_PCH_CPT(dev_priv->dev)) {
1505                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1506                         return false;
1507         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1508                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1509                         return false;
1510         } else {
1511                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1512                         return false;
1513         }
1514         return true;
1515 }
1516
1517 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1518                               enum pipe pipe, u32 val)
1519 {
1520         if ((val & LVDS_PORT_EN) == 0)
1521                 return false;
1522
1523         if (HAS_PCH_CPT(dev_priv->dev)) {
1524                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1525                         return false;
1526         } else {
1527                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1528                         return false;
1529         }
1530         return true;
1531 }
1532
1533 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1534                               enum pipe pipe, u32 val)
1535 {
1536         if ((val & ADPA_DAC_ENABLE) == 0)
1537                 return false;
1538         if (HAS_PCH_CPT(dev_priv->dev)) {
1539                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1540                         return false;
1541         } else {
1542                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1543                         return false;
1544         }
1545         return true;
1546 }
1547
1548 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1549                                    enum pipe pipe, i915_reg_t reg,
1550                                    u32 port_sel)
1551 {
1552         u32 val = I915_READ(reg);
1553         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1554              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1555              i915_mmio_reg_offset(reg), pipe_name(pipe));
1556
1557         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1558              && (val & DP_PIPEB_SELECT),
1559              "IBX PCH dp port still using transcoder B\n");
1560 }
1561
1562 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1563                                      enum pipe pipe, i915_reg_t reg)
1564 {
1565         u32 val = I915_READ(reg);
1566         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1567              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1568              i915_mmio_reg_offset(reg), pipe_name(pipe));
1569
1570         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1571              && (val & SDVO_PIPE_B_SELECT),
1572              "IBX PCH hdmi port still using transcoder B\n");
1573 }
1574
1575 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1576                                       enum pipe pipe)
1577 {
1578         u32 val;
1579
1580         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1581         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1582         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1583
1584         val = I915_READ(PCH_ADPA);
1585         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1586              "PCH VGA enabled on transcoder %c, should be disabled\n",
1587              pipe_name(pipe));
1588
1589         val = I915_READ(PCH_LVDS);
1590         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1591              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1592              pipe_name(pipe));
1593
1594         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1595         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1596         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1597 }
1598
1599 static void vlv_enable_pll(struct intel_crtc *crtc,
1600                            const struct intel_crtc_state *pipe_config)
1601 {
1602         struct drm_device *dev = crtc->base.dev;
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604         i915_reg_t reg = DPLL(crtc->pipe);
1605         u32 dpll = pipe_config->dpll_hw_state.dpll;
1606
1607         assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609         /* No really, not for ILK+ */
1610         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1611
1612         /* PLL is protected by panel, make sure we can write it */
1613         if (IS_MOBILE(dev_priv->dev))
1614                 assert_panel_unlocked(dev_priv, crtc->pipe);
1615
1616         I915_WRITE(reg, dpll);
1617         POSTING_READ(reg);
1618         udelay(150);
1619
1620         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1621                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1622
1623         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1624         POSTING_READ(DPLL_MD(crtc->pipe));
1625
1626         /* We do this three times for luck */
1627         I915_WRITE(reg, dpll);
1628         POSTING_READ(reg);
1629         udelay(150); /* wait for warmup */
1630         I915_WRITE(reg, dpll);
1631         POSTING_READ(reg);
1632         udelay(150); /* wait for warmup */
1633         I915_WRITE(reg, dpll);
1634         POSTING_READ(reg);
1635         udelay(150); /* wait for warmup */
1636 }
1637
1638 static void chv_enable_pll(struct intel_crtc *crtc,
1639                            const struct intel_crtc_state *pipe_config)
1640 {
1641         struct drm_device *dev = crtc->base.dev;
1642         struct drm_i915_private *dev_priv = dev->dev_private;
1643         int pipe = crtc->pipe;
1644         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1645         u32 tmp;
1646
1647         assert_pipe_disabled(dev_priv, crtc->pipe);
1648
1649         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1650
1651         mutex_lock(&dev_priv->sb_lock);
1652
1653         /* Enable back the 10bit clock to display controller */
1654         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1655         tmp |= DPIO_DCLKP_EN;
1656         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1657
1658         mutex_unlock(&dev_priv->sb_lock);
1659
1660         /*
1661          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1662          */
1663         udelay(1);
1664
1665         /* Enable PLL */
1666         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1667
1668         /* Check PLL is locked */
1669         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1670                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1671
1672         /* not sure when this should be written */
1673         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1674         POSTING_READ(DPLL_MD(pipe));
1675 }
1676
1677 static int intel_num_dvo_pipes(struct drm_device *dev)
1678 {
1679         struct intel_crtc *crtc;
1680         int count = 0;
1681
1682         for_each_intel_crtc(dev, crtc)
1683                 count += crtc->base.state->active &&
1684                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1685
1686         return count;
1687 }
1688
1689 static void i9xx_enable_pll(struct intel_crtc *crtc)
1690 {
1691         struct drm_device *dev = crtc->base.dev;
1692         struct drm_i915_private *dev_priv = dev->dev_private;
1693         i915_reg_t reg = DPLL(crtc->pipe);
1694         u32 dpll = crtc->config->dpll_hw_state.dpll;
1695
1696         assert_pipe_disabled(dev_priv, crtc->pipe);
1697
1698         /* No really, not for ILK+ */
1699         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1700
1701         /* PLL is protected by panel, make sure we can write it */
1702         if (IS_MOBILE(dev) && !IS_I830(dev))
1703                 assert_panel_unlocked(dev_priv, crtc->pipe);
1704
1705         /* Enable DVO 2x clock on both PLLs if necessary */
1706         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1707                 /*
1708                  * It appears to be important that we don't enable this
1709                  * for the current pipe before otherwise configuring the
1710                  * PLL. No idea how this should be handled if multiple
1711                  * DVO outputs are enabled simultaneosly.
1712                  */
1713                 dpll |= DPLL_DVO_2X_MODE;
1714                 I915_WRITE(DPLL(!crtc->pipe),
1715                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1716         }
1717
1718         /*
1719          * Apparently we need to have VGA mode enabled prior to changing
1720          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1721          * dividers, even though the register value does change.
1722          */
1723         I915_WRITE(reg, 0);
1724
1725         I915_WRITE(reg, dpll);
1726
1727         /* Wait for the clocks to stabilize. */
1728         POSTING_READ(reg);
1729         udelay(150);
1730
1731         if (INTEL_INFO(dev)->gen >= 4) {
1732                 I915_WRITE(DPLL_MD(crtc->pipe),
1733                            crtc->config->dpll_hw_state.dpll_md);
1734         } else {
1735                 /* The pixel multiplier can only be updated once the
1736                  * DPLL is enabled and the clocks are stable.
1737                  *
1738                  * So write it again.
1739                  */
1740                 I915_WRITE(reg, dpll);
1741         }
1742
1743         /* We do this three times for luck */
1744         I915_WRITE(reg, dpll);
1745         POSTING_READ(reg);
1746         udelay(150); /* wait for warmup */
1747         I915_WRITE(reg, dpll);
1748         POSTING_READ(reg);
1749         udelay(150); /* wait for warmup */
1750         I915_WRITE(reg, dpll);
1751         POSTING_READ(reg);
1752         udelay(150); /* wait for warmup */
1753 }
1754
1755 /**
1756  * i9xx_disable_pll - disable a PLL
1757  * @dev_priv: i915 private structure
1758  * @pipe: pipe PLL to disable
1759  *
1760  * Disable the PLL for @pipe, making sure the pipe is off first.
1761  *
1762  * Note!  This is for pre-ILK only.
1763  */
1764 static void i9xx_disable_pll(struct intel_crtc *crtc)
1765 {
1766         struct drm_device *dev = crtc->base.dev;
1767         struct drm_i915_private *dev_priv = dev->dev_private;
1768         enum pipe pipe = crtc->pipe;
1769
1770         /* Disable DVO 2x clock on both PLLs if necessary */
1771         if (IS_I830(dev) &&
1772             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1773             !intel_num_dvo_pipes(dev)) {
1774                 I915_WRITE(DPLL(PIPE_B),
1775                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1776                 I915_WRITE(DPLL(PIPE_A),
1777                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1778         }
1779
1780         /* Don't disable pipe or pipe PLLs if needed */
1781         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1782             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1783                 return;
1784
1785         /* Make sure the pipe isn't still relying on us */
1786         assert_pipe_disabled(dev_priv, pipe);
1787
1788         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1789         POSTING_READ(DPLL(pipe));
1790 }
1791
1792 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793 {
1794         u32 val;
1795
1796         /* Make sure the pipe isn't still relying on us */
1797         assert_pipe_disabled(dev_priv, pipe);
1798
1799         /*
1800          * Leave integrated clock source and reference clock enabled for pipe B.
1801          * The latter is needed for VGA hotplug / manual detection.
1802          */
1803         val = DPLL_VGA_MODE_DIS;
1804         if (pipe == PIPE_B)
1805                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1806         I915_WRITE(DPLL(pipe), val);
1807         POSTING_READ(DPLL(pipe));
1808
1809 }
1810
1811 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1812 {
1813         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1814         u32 val;
1815
1816         /* Make sure the pipe isn't still relying on us */
1817         assert_pipe_disabled(dev_priv, pipe);
1818
1819         /* Set PLL en = 0 */
1820         val = DPLL_SSC_REF_CLK_CHV |
1821                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1822         if (pipe != PIPE_A)
1823                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1824         I915_WRITE(DPLL(pipe), val);
1825         POSTING_READ(DPLL(pipe));
1826
1827         mutex_lock(&dev_priv->sb_lock);
1828
1829         /* Disable 10bit clock to display controller */
1830         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1831         val &= ~DPIO_DCLKP_EN;
1832         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1833
1834         mutex_unlock(&dev_priv->sb_lock);
1835 }
1836
1837 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1838                          struct intel_digital_port *dport,
1839                          unsigned int expected_mask)
1840 {
1841         u32 port_mask;
1842         i915_reg_t dpll_reg;
1843
1844         switch (dport->port) {
1845         case PORT_B:
1846                 port_mask = DPLL_PORTB_READY_MASK;
1847                 dpll_reg = DPLL(0);
1848                 break;
1849         case PORT_C:
1850                 port_mask = DPLL_PORTC_READY_MASK;
1851                 dpll_reg = DPLL(0);
1852                 expected_mask <<= 4;
1853                 break;
1854         case PORT_D:
1855                 port_mask = DPLL_PORTD_READY_MASK;
1856                 dpll_reg = DPIO_PHY_STATUS;
1857                 break;
1858         default:
1859                 BUG();
1860         }
1861
1862         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1863                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1864                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1865 }
1866
1867 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1868 {
1869         struct drm_device *dev = crtc->base.dev;
1870         struct drm_i915_private *dev_priv = dev->dev_private;
1871         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1872
1873         if (WARN_ON(pll == NULL))
1874                 return;
1875
1876         WARN_ON(!pll->config.crtc_mask);
1877         if (pll->active == 0) {
1878                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1879                 WARN_ON(pll->on);
1880                 assert_shared_dpll_disabled(dev_priv, pll);
1881
1882                 pll->mode_set(dev_priv, pll);
1883         }
1884 }
1885
1886 /**
1887  * intel_enable_shared_dpll - enable PCH PLL
1888  * @dev_priv: i915 private structure
1889  * @pipe: pipe PLL to enable
1890  *
1891  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1892  * drives the transcoder clock.
1893  */
1894 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1895 {
1896         struct drm_device *dev = crtc->base.dev;
1897         struct drm_i915_private *dev_priv = dev->dev_private;
1898         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1899
1900         if (WARN_ON(pll == NULL))
1901                 return;
1902
1903         if (WARN_ON(pll->config.crtc_mask == 0))
1904                 return;
1905
1906         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1907                       pll->name, pll->active, pll->on,
1908                       crtc->base.base.id);
1909
1910         if (pll->active++) {
1911                 WARN_ON(!pll->on);
1912                 assert_shared_dpll_enabled(dev_priv, pll);
1913                 return;
1914         }
1915         WARN_ON(pll->on);
1916
1917         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1918
1919         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1920         pll->enable(dev_priv, pll);
1921         pll->on = true;
1922 }
1923
1924 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1925 {
1926         struct drm_device *dev = crtc->base.dev;
1927         struct drm_i915_private *dev_priv = dev->dev_private;
1928         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1929
1930         /* PCH only available on ILK+ */
1931         if (INTEL_INFO(dev)->gen < 5)
1932                 return;
1933
1934         if (pll == NULL)
1935                 return;
1936
1937         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1938                 return;
1939
1940         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1941                       pll->name, pll->active, pll->on,
1942                       crtc->base.base.id);
1943
1944         if (WARN_ON(pll->active == 0)) {
1945                 assert_shared_dpll_disabled(dev_priv, pll);
1946                 return;
1947         }
1948
1949         assert_shared_dpll_enabled(dev_priv, pll);
1950         WARN_ON(!pll->on);
1951         if (--pll->active)
1952                 return;
1953
1954         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1955         pll->disable(dev_priv, pll);
1956         pll->on = false;
1957
1958         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1959 }
1960
1961 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1962                                            enum pipe pipe)
1963 {
1964         struct drm_device *dev = dev_priv->dev;
1965         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1967         i915_reg_t reg;
1968         uint32_t val, pipeconf_val;
1969
1970         /* PCH only available on ILK+ */
1971         BUG_ON(!HAS_PCH_SPLIT(dev));
1972
1973         /* Make sure PCH DPLL is enabled */
1974         assert_shared_dpll_enabled(dev_priv,
1975                                    intel_crtc_to_shared_dpll(intel_crtc));
1976
1977         /* FDI must be feeding us bits for PCH ports */
1978         assert_fdi_tx_enabled(dev_priv, pipe);
1979         assert_fdi_rx_enabled(dev_priv, pipe);
1980
1981         if (HAS_PCH_CPT(dev)) {
1982                 /* Workaround: Set the timing override bit before enabling the
1983                  * pch transcoder. */
1984                 reg = TRANS_CHICKEN2(pipe);
1985                 val = I915_READ(reg);
1986                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1987                 I915_WRITE(reg, val);
1988         }
1989
1990         reg = PCH_TRANSCONF(pipe);
1991         val = I915_READ(reg);
1992         pipeconf_val = I915_READ(PIPECONF(pipe));
1993
1994         if (HAS_PCH_IBX(dev_priv->dev)) {
1995                 /*
1996                  * Make the BPC in transcoder be consistent with
1997                  * that in pipeconf reg. For HDMI we must use 8bpc
1998                  * here for both 8bpc and 12bpc.
1999                  */
2000                 val &= ~PIPECONF_BPC_MASK;
2001                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2002                         val |= PIPECONF_8BPC;
2003                 else
2004                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2005         }
2006
2007         val &= ~TRANS_INTERLACE_MASK;
2008         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2009                 if (HAS_PCH_IBX(dev_priv->dev) &&
2010                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2011                         val |= TRANS_LEGACY_INTERLACED_ILK;
2012                 else
2013                         val |= TRANS_INTERLACED;
2014         else
2015                 val |= TRANS_PROGRESSIVE;
2016
2017         I915_WRITE(reg, val | TRANS_ENABLE);
2018         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2019                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2020 }
2021
2022 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2023                                       enum transcoder cpu_transcoder)
2024 {
2025         u32 val, pipeconf_val;
2026
2027         /* PCH only available on ILK+ */
2028         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2029
2030         /* FDI must be feeding us bits for PCH ports */
2031         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2032         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2033
2034         /* Workaround: set timing override bit. */
2035         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2036         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2037         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2038
2039         val = TRANS_ENABLE;
2040         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2041
2042         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2043             PIPECONF_INTERLACED_ILK)
2044                 val |= TRANS_INTERLACED;
2045         else
2046                 val |= TRANS_PROGRESSIVE;
2047
2048         I915_WRITE(LPT_TRANSCONF, val);
2049         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2050                 DRM_ERROR("Failed to enable PCH transcoder\n");
2051 }
2052
2053 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2054                                             enum pipe pipe)
2055 {
2056         struct drm_device *dev = dev_priv->dev;
2057         i915_reg_t reg;
2058         uint32_t val;
2059
2060         /* FDI relies on the transcoder */
2061         assert_fdi_tx_disabled(dev_priv, pipe);
2062         assert_fdi_rx_disabled(dev_priv, pipe);
2063
2064         /* Ports must be off as well */
2065         assert_pch_ports_disabled(dev_priv, pipe);
2066
2067         reg = PCH_TRANSCONF(pipe);
2068         val = I915_READ(reg);
2069         val &= ~TRANS_ENABLE;
2070         I915_WRITE(reg, val);
2071         /* wait for PCH transcoder off, transcoder state */
2072         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2073                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2074
2075         if (HAS_PCH_CPT(dev)) {
2076                 /* Workaround: Clear the timing override chicken bit again. */
2077                 reg = TRANS_CHICKEN2(pipe);
2078                 val = I915_READ(reg);
2079                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2080                 I915_WRITE(reg, val);
2081         }
2082 }
2083
2084 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2085 {
2086         u32 val;
2087
2088         val = I915_READ(LPT_TRANSCONF);
2089         val &= ~TRANS_ENABLE;
2090         I915_WRITE(LPT_TRANSCONF, val);
2091         /* wait for PCH transcoder off, transcoder state */
2092         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2093                 DRM_ERROR("Failed to disable PCH transcoder\n");
2094
2095         /* Workaround: clear timing override bit. */
2096         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2097         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2098         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2099 }
2100
2101 /**
2102  * intel_enable_pipe - enable a pipe, asserting requirements
2103  * @crtc: crtc responsible for the pipe
2104  *
2105  * Enable @crtc's pipe, making sure that various hardware specific requirements
2106  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2107  */
2108 static void intel_enable_pipe(struct intel_crtc *crtc)
2109 {
2110         struct drm_device *dev = crtc->base.dev;
2111         struct drm_i915_private *dev_priv = dev->dev_private;
2112         enum pipe pipe = crtc->pipe;
2113         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2114         enum pipe pch_transcoder;
2115         i915_reg_t reg;
2116         u32 val;
2117
2118         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2119
2120         assert_planes_disabled(dev_priv, pipe);
2121         assert_cursor_disabled(dev_priv, pipe);
2122         assert_sprites_disabled(dev_priv, pipe);
2123
2124         if (HAS_PCH_LPT(dev_priv->dev))
2125                 pch_transcoder = TRANSCODER_A;
2126         else
2127                 pch_transcoder = pipe;
2128
2129         /*
2130          * A pipe without a PLL won't actually be able to drive bits from
2131          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2132          * need the check.
2133          */
2134         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2135                 if (crtc->config->has_dsi_encoder)
2136                         assert_dsi_pll_enabled(dev_priv);
2137                 else
2138                         assert_pll_enabled(dev_priv, pipe);
2139         else {
2140                 if (crtc->config->has_pch_encoder) {
2141                         /* if driving the PCH, we need FDI enabled */
2142                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2143                         assert_fdi_tx_pll_enabled(dev_priv,
2144                                                   (enum pipe) cpu_transcoder);
2145                 }
2146                 /* FIXME: assert CPU port conditions for SNB+ */
2147         }
2148
2149         reg = PIPECONF(cpu_transcoder);
2150         val = I915_READ(reg);
2151         if (val & PIPECONF_ENABLE) {
2152                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2153                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2154                 return;
2155         }
2156
2157         I915_WRITE(reg, val | PIPECONF_ENABLE);
2158         POSTING_READ(reg);
2159 }
2160
2161 /**
2162  * intel_disable_pipe - disable a pipe, asserting requirements
2163  * @crtc: crtc whose pipes is to be disabled
2164  *
2165  * Disable the pipe of @crtc, making sure that various hardware
2166  * specific requirements are met, if applicable, e.g. plane
2167  * disabled, panel fitter off, etc.
2168  *
2169  * Will wait until the pipe has shut down before returning.
2170  */
2171 static void intel_disable_pipe(struct intel_crtc *crtc)
2172 {
2173         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2174         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2175         enum pipe pipe = crtc->pipe;
2176         i915_reg_t reg;
2177         u32 val;
2178
2179         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2180
2181         /*
2182          * Make sure planes won't keep trying to pump pixels to us,
2183          * or we might hang the display.
2184          */
2185         assert_planes_disabled(dev_priv, pipe);
2186         assert_cursor_disabled(dev_priv, pipe);
2187         assert_sprites_disabled(dev_priv, pipe);
2188
2189         reg = PIPECONF(cpu_transcoder);
2190         val = I915_READ(reg);
2191         if ((val & PIPECONF_ENABLE) == 0)
2192                 return;
2193
2194         /*
2195          * Double wide has implications for planes
2196          * so best keep it disabled when not needed.
2197          */
2198         if (crtc->config->double_wide)
2199                 val &= ~PIPECONF_DOUBLE_WIDE;
2200
2201         /* Don't disable pipe or pipe PLLs if needed */
2202         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2203             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2204                 val &= ~PIPECONF_ENABLE;
2205
2206         I915_WRITE(reg, val);
2207         if ((val & PIPECONF_ENABLE) == 0)
2208                 intel_wait_for_pipe_off(crtc);
2209 }
2210
2211 static bool need_vtd_wa(struct drm_device *dev)
2212 {
2213 #ifdef CONFIG_INTEL_IOMMU
2214         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2215                 return true;
2216 #endif
2217         return false;
2218 }
2219
2220 unsigned int
2221 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2222                   uint64_t fb_format_modifier, unsigned int plane)
2223 {
2224         unsigned int tile_height;
2225         uint32_t pixel_bytes;
2226
2227         switch (fb_format_modifier) {
2228         case DRM_FORMAT_MOD_NONE:
2229                 tile_height = 1;
2230                 break;
2231         case I915_FORMAT_MOD_X_TILED:
2232                 tile_height = IS_GEN2(dev) ? 16 : 8;
2233                 break;
2234         case I915_FORMAT_MOD_Y_TILED:
2235                 tile_height = 32;
2236                 break;
2237         case I915_FORMAT_MOD_Yf_TILED:
2238                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2239                 switch (pixel_bytes) {
2240                 default:
2241                 case 1:
2242                         tile_height = 64;
2243                         break;
2244                 case 2:
2245                 case 4:
2246                         tile_height = 32;
2247                         break;
2248                 case 8:
2249                         tile_height = 16;
2250                         break;
2251                 case 16:
2252                         WARN_ONCE(1,
2253                                   "128-bit pixels are not supported for display!");
2254                         tile_height = 16;
2255                         break;
2256                 }
2257                 break;
2258         default:
2259                 MISSING_CASE(fb_format_modifier);
2260                 tile_height = 1;
2261                 break;
2262         }
2263
2264         return tile_height;
2265 }
2266
2267 unsigned int
2268 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2269                       uint32_t pixel_format, uint64_t fb_format_modifier)
2270 {
2271         return ALIGN(height, intel_tile_height(dev, pixel_format,
2272                                                fb_format_modifier, 0));
2273 }
2274
2275 static void
2276 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2277                         const struct drm_plane_state *plane_state)
2278 {
2279         struct intel_rotation_info *info = &view->params.rotation_info;
2280         unsigned int tile_height, tile_pitch;
2281
2282         *view = i915_ggtt_view_normal;
2283
2284         if (!plane_state)
2285                 return;
2286
2287         if (!intel_rotation_90_or_270(plane_state->rotation))
2288                 return;
2289
2290         *view = i915_ggtt_view_rotated;
2291
2292         info->height = fb->height;
2293         info->pixel_format = fb->pixel_format;
2294         info->pitch = fb->pitches[0];
2295         info->uv_offset = fb->offsets[1];
2296         info->fb_modifier = fb->modifier[0];
2297
2298         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2299                                         fb->modifier[0], 0);
2300         tile_pitch = PAGE_SIZE / tile_height;
2301         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2302         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2303         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2304
2305         if (info->pixel_format == DRM_FORMAT_NV12) {
2306                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2307                                                 fb->modifier[0], 1);
2308                 tile_pitch = PAGE_SIZE / tile_height;
2309                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2310                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2311                                                      tile_height);
2312                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2313                                 PAGE_SIZE;
2314         }
2315 }
2316
2317 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2318 {
2319         if (INTEL_INFO(dev_priv)->gen >= 9)
2320                 return 256 * 1024;
2321         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2322                  IS_VALLEYVIEW(dev_priv))
2323                 return 128 * 1024;
2324         else if (INTEL_INFO(dev_priv)->gen >= 4)
2325                 return 4 * 1024;
2326         else
2327                 return 0;
2328 }
2329
2330 int
2331 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2332                            struct drm_framebuffer *fb,
2333                            const struct drm_plane_state *plane_state)
2334 {
2335         struct drm_device *dev = fb->dev;
2336         struct drm_i915_private *dev_priv = dev->dev_private;
2337         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2338         struct i915_ggtt_view view;
2339         u32 alignment;
2340         int ret;
2341
2342         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2343
2344         switch (fb->modifier[0]) {
2345         case DRM_FORMAT_MOD_NONE:
2346                 alignment = intel_linear_alignment(dev_priv);
2347                 break;
2348         case I915_FORMAT_MOD_X_TILED:
2349                 if (INTEL_INFO(dev)->gen >= 9)
2350                         alignment = 256 * 1024;
2351                 else {
2352                         /* pin() will align the object as required by fence */
2353                         alignment = 0;
2354                 }
2355                 break;
2356         case I915_FORMAT_MOD_Y_TILED:
2357         case I915_FORMAT_MOD_Yf_TILED:
2358                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2359                           "Y tiling bo slipped through, driver bug!\n"))
2360                         return -EINVAL;
2361                 alignment = 1 * 1024 * 1024;
2362                 break;
2363         default:
2364                 MISSING_CASE(fb->modifier[0]);
2365                 return -EINVAL;
2366         }
2367
2368         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2369
2370         /* Note that the w/a also requires 64 PTE of padding following the
2371          * bo. We currently fill all unused PTE with the shadow page and so
2372          * we should always have valid PTE following the scanout preventing
2373          * the VT-d warning.
2374          */
2375         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2376                 alignment = 256 * 1024;
2377
2378         /*
2379          * Global gtt pte registers are special registers which actually forward
2380          * writes to a chunk of system memory. Which means that there is no risk
2381          * that the register values disappear as soon as we call
2382          * intel_runtime_pm_put(), so it is correct to wrap only the
2383          * pin/unpin/fence and not more.
2384          */
2385         intel_runtime_pm_get(dev_priv);
2386
2387         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2388                                                    &view);
2389         if (ret)
2390                 goto err_pm;
2391
2392         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2393          * fence, whereas 965+ only requires a fence if using
2394          * framebuffer compression.  For simplicity, we always install
2395          * a fence as the cost is not that onerous.
2396          */
2397         if (view.type == I915_GGTT_VIEW_NORMAL) {
2398                 ret = i915_gem_object_get_fence(obj);
2399                 if (ret == -EDEADLK) {
2400                         /*
2401                          * -EDEADLK means there are no free fences
2402                          * no pending flips.
2403                          *
2404                          * This is propagated to atomic, but it uses
2405                          * -EDEADLK to force a locking recovery, so
2406                          * change the returned error to -EBUSY.
2407                          */
2408                         ret = -EBUSY;
2409                         goto err_unpin;
2410                 } else if (ret)
2411                         goto err_unpin;
2412
2413                 i915_gem_object_pin_fence(obj);
2414         }
2415
2416         intel_runtime_pm_put(dev_priv);
2417         return 0;
2418
2419 err_unpin:
2420         i915_gem_object_unpin_from_display_plane(obj, &view);
2421 err_pm:
2422         intel_runtime_pm_put(dev_priv);
2423         return ret;
2424 }
2425
2426 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2427                                const struct drm_plane_state *plane_state)
2428 {
2429         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2430         struct i915_ggtt_view view;
2431
2432         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2433
2434         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2435
2436         if (view.type == I915_GGTT_VIEW_NORMAL)
2437                 i915_gem_object_unpin_fence(obj);
2438
2439         i915_gem_object_unpin_from_display_plane(obj, &view);
2440 }
2441
2442 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2443  * is assumed to be a power-of-two. */
2444 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2445                                              int *x, int *y,
2446                                              unsigned int tiling_mode,
2447                                              unsigned int cpp,
2448                                              unsigned int pitch)
2449 {
2450         if (tiling_mode != I915_TILING_NONE) {
2451                 unsigned int tile_rows, tiles;
2452
2453                 tile_rows = *y / 8;
2454                 *y %= 8;
2455
2456                 tiles = *x / (512/cpp);
2457                 *x %= 512/cpp;
2458
2459                 return tile_rows * pitch * 8 + tiles * 4096;
2460         } else {
2461                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2462                 unsigned int offset;
2463
2464                 offset = *y * pitch + *x * cpp;
2465                 *y = (offset & alignment) / pitch;
2466                 *x = ((offset & alignment) - *y * pitch) / cpp;
2467                 return offset & ~alignment;
2468         }
2469 }
2470
2471 static int i9xx_format_to_fourcc(int format)
2472 {
2473         switch (format) {
2474         case DISPPLANE_8BPP:
2475                 return DRM_FORMAT_C8;
2476         case DISPPLANE_BGRX555:
2477                 return DRM_FORMAT_XRGB1555;
2478         case DISPPLANE_BGRX565:
2479                 return DRM_FORMAT_RGB565;
2480         default:
2481         case DISPPLANE_BGRX888:
2482                 return DRM_FORMAT_XRGB8888;
2483         case DISPPLANE_RGBX888:
2484                 return DRM_FORMAT_XBGR8888;
2485         case DISPPLANE_BGRX101010:
2486                 return DRM_FORMAT_XRGB2101010;
2487         case DISPPLANE_RGBX101010:
2488                 return DRM_FORMAT_XBGR2101010;
2489         }
2490 }
2491
2492 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2493 {
2494         switch (format) {
2495         case PLANE_CTL_FORMAT_RGB_565:
2496                 return DRM_FORMAT_RGB565;
2497         default:
2498         case PLANE_CTL_FORMAT_XRGB_8888:
2499                 if (rgb_order) {
2500                         if (alpha)
2501                                 return DRM_FORMAT_ABGR8888;
2502                         else
2503                                 return DRM_FORMAT_XBGR8888;
2504                 } else {
2505                         if (alpha)
2506                                 return DRM_FORMAT_ARGB8888;
2507                         else
2508                                 return DRM_FORMAT_XRGB8888;
2509                 }
2510         case PLANE_CTL_FORMAT_XRGB_2101010:
2511                 if (rgb_order)
2512                         return DRM_FORMAT_XBGR2101010;
2513                 else
2514                         return DRM_FORMAT_XRGB2101010;
2515         }
2516 }
2517
2518 static bool
2519 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2520                               struct intel_initial_plane_config *plane_config)
2521 {
2522         struct drm_device *dev = crtc->base.dev;
2523         struct drm_i915_private *dev_priv = to_i915(dev);
2524         struct drm_i915_gem_object *obj = NULL;
2525         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2526         struct drm_framebuffer *fb = &plane_config->fb->base;
2527         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2528         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2529                                     PAGE_SIZE);
2530
2531         size_aligned -= base_aligned;
2532
2533         if (plane_config->size == 0)
2534                 return false;
2535
2536         /* If the FB is too big, just don't use it since fbdev is not very
2537          * important and we should probably use that space with FBC or other
2538          * features. */
2539         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2540                 return false;
2541
2542         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2543                                                              base_aligned,
2544                                                              base_aligned,
2545                                                              size_aligned);
2546         if (!obj)
2547                 return false;
2548
2549         obj->tiling_mode = plane_config->tiling;
2550         if (obj->tiling_mode == I915_TILING_X)
2551                 obj->stride = fb->pitches[0];
2552
2553         mode_cmd.pixel_format = fb->pixel_format;
2554         mode_cmd.width = fb->width;
2555         mode_cmd.height = fb->height;
2556         mode_cmd.pitches[0] = fb->pitches[0];
2557         mode_cmd.modifier[0] = fb->modifier[0];
2558         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2559
2560         mutex_lock(&dev->struct_mutex);
2561         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2562                                    &mode_cmd, obj)) {
2563                 DRM_DEBUG_KMS("intel fb init failed\n");
2564                 goto out_unref_obj;
2565         }
2566         mutex_unlock(&dev->struct_mutex);
2567
2568         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2569         return true;
2570
2571 out_unref_obj:
2572         drm_gem_object_unreference(&obj->base);
2573         mutex_unlock(&dev->struct_mutex);
2574         return false;
2575 }
2576
2577 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2578 static void
2579 update_state_fb(struct drm_plane *plane)
2580 {
2581         if (plane->fb == plane->state->fb)
2582                 return;
2583
2584         if (plane->state->fb)
2585                 drm_framebuffer_unreference(plane->state->fb);
2586         plane->state->fb = plane->fb;
2587         if (plane->state->fb)
2588                 drm_framebuffer_reference(plane->state->fb);
2589 }
2590
2591 static void
2592 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2593                              struct intel_initial_plane_config *plane_config)
2594 {
2595         struct drm_device *dev = intel_crtc->base.dev;
2596         struct drm_i915_private *dev_priv = dev->dev_private;
2597         struct drm_crtc *c;
2598         struct intel_crtc *i;
2599         struct drm_i915_gem_object *obj;
2600         struct drm_plane *primary = intel_crtc->base.primary;
2601         struct drm_plane_state *plane_state = primary->state;
2602         struct drm_framebuffer *fb;
2603
2604         if (!plane_config->fb)
2605                 return;
2606
2607         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2608                 fb = &plane_config->fb->base;
2609                 goto valid_fb;
2610         }
2611
2612         kfree(plane_config->fb);
2613
2614         /*
2615          * Failed to alloc the obj, check to see if we should share
2616          * an fb with another CRTC instead
2617          */
2618         for_each_crtc(dev, c) {
2619                 i = to_intel_crtc(c);
2620
2621                 if (c == &intel_crtc->base)
2622                         continue;
2623
2624                 if (!i->active)
2625                         continue;
2626
2627                 fb = c->primary->fb;
2628                 if (!fb)
2629                         continue;
2630
2631                 obj = intel_fb_obj(fb);
2632                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2633                         drm_framebuffer_reference(fb);
2634                         goto valid_fb;
2635                 }
2636         }
2637
2638         return;
2639
2640 valid_fb:
2641         plane_state->src_x = 0;
2642         plane_state->src_y = 0;
2643         plane_state->src_w = fb->width << 16;
2644         plane_state->src_h = fb->height << 16;
2645
2646         plane_state->crtc_x = 0;
2647         plane_state->crtc_y = 0;
2648         plane_state->crtc_w = fb->width;
2649         plane_state->crtc_h = fb->height;
2650
2651         obj = intel_fb_obj(fb);
2652         if (obj->tiling_mode != I915_TILING_NONE)
2653                 dev_priv->preserve_bios_swizzle = true;
2654
2655         drm_framebuffer_reference(fb);
2656         primary->fb = primary->state->fb = fb;
2657         primary->crtc = primary->state->crtc = &intel_crtc->base;
2658         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2659         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2660 }
2661
2662 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2663                                       struct drm_framebuffer *fb,
2664                                       int x, int y)
2665 {
2666         struct drm_device *dev = crtc->dev;
2667         struct drm_i915_private *dev_priv = dev->dev_private;
2668         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2669         struct drm_plane *primary = crtc->primary;
2670         bool visible = to_intel_plane_state(primary->state)->visible;
2671         struct drm_i915_gem_object *obj;
2672         int plane = intel_crtc->plane;
2673         unsigned long linear_offset;
2674         u32 dspcntr;
2675         i915_reg_t reg = DSPCNTR(plane);
2676         int pixel_size;
2677
2678         if (!visible || !fb) {
2679                 I915_WRITE(reg, 0);
2680                 if (INTEL_INFO(dev)->gen >= 4)
2681                         I915_WRITE(DSPSURF(plane), 0);
2682                 else
2683                         I915_WRITE(DSPADDR(plane), 0);
2684                 POSTING_READ(reg);
2685                 return;
2686         }
2687
2688         obj = intel_fb_obj(fb);
2689         if (WARN_ON(obj == NULL))
2690                 return;
2691
2692         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2693
2694         dspcntr = DISPPLANE_GAMMA_ENABLE;
2695
2696         dspcntr |= DISPLAY_PLANE_ENABLE;
2697
2698         if (INTEL_INFO(dev)->gen < 4) {
2699                 if (intel_crtc->pipe == PIPE_B)
2700                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2701
2702                 /* pipesrc and dspsize control the size that is scaled from,
2703                  * which should always be the user's requested size.
2704                  */
2705                 I915_WRITE(DSPSIZE(plane),
2706                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2707                            (intel_crtc->config->pipe_src_w - 1));
2708                 I915_WRITE(DSPPOS(plane), 0);
2709         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2710                 I915_WRITE(PRIMSIZE(plane),
2711                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2712                            (intel_crtc->config->pipe_src_w - 1));
2713                 I915_WRITE(PRIMPOS(plane), 0);
2714                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2715         }
2716
2717         switch (fb->pixel_format) {
2718         case DRM_FORMAT_C8:
2719                 dspcntr |= DISPPLANE_8BPP;
2720                 break;
2721         case DRM_FORMAT_XRGB1555:
2722                 dspcntr |= DISPPLANE_BGRX555;
2723                 break;
2724         case DRM_FORMAT_RGB565:
2725                 dspcntr |= DISPPLANE_BGRX565;
2726                 break;
2727         case DRM_FORMAT_XRGB8888:
2728                 dspcntr |= DISPPLANE_BGRX888;
2729                 break;
2730         case DRM_FORMAT_XBGR8888:
2731                 dspcntr |= DISPPLANE_RGBX888;
2732                 break;
2733         case DRM_FORMAT_XRGB2101010:
2734                 dspcntr |= DISPPLANE_BGRX101010;
2735                 break;
2736         case DRM_FORMAT_XBGR2101010:
2737                 dspcntr |= DISPPLANE_RGBX101010;
2738                 break;
2739         default:
2740                 BUG();
2741         }
2742
2743         if (INTEL_INFO(dev)->gen >= 4 &&
2744             obj->tiling_mode != I915_TILING_NONE)
2745                 dspcntr |= DISPPLANE_TILED;
2746
2747         if (IS_G4X(dev))
2748                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2749
2750         linear_offset = y * fb->pitches[0] + x * pixel_size;
2751
2752         if (INTEL_INFO(dev)->gen >= 4) {
2753                 intel_crtc->dspaddr_offset =
2754                         intel_gen4_compute_page_offset(dev_priv,
2755                                                        &x, &y, obj->tiling_mode,
2756                                                        pixel_size,
2757                                                        fb->pitches[0]);
2758                 linear_offset -= intel_crtc->dspaddr_offset;
2759         } else {
2760                 intel_crtc->dspaddr_offset = linear_offset;
2761         }
2762
2763         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2764                 dspcntr |= DISPPLANE_ROTATE_180;
2765
2766                 x += (intel_crtc->config->pipe_src_w - 1);
2767                 y += (intel_crtc->config->pipe_src_h - 1);
2768
2769                 /* Finding the last pixel of the last line of the display
2770                 data and adding to linear_offset*/
2771                 linear_offset +=
2772                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2773                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2774         }
2775
2776         intel_crtc->adjusted_x = x;
2777         intel_crtc->adjusted_y = y;
2778
2779         I915_WRITE(reg, dspcntr);
2780
2781         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2782         if (INTEL_INFO(dev)->gen >= 4) {
2783                 I915_WRITE(DSPSURF(plane),
2784                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2785                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2786                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2787         } else
2788                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2789         POSTING_READ(reg);
2790 }
2791
2792 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2793                                           struct drm_framebuffer *fb,
2794                                           int x, int y)
2795 {
2796         struct drm_device *dev = crtc->dev;
2797         struct drm_i915_private *dev_priv = dev->dev_private;
2798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2799         struct drm_plane *primary = crtc->primary;
2800         bool visible = to_intel_plane_state(primary->state)->visible;
2801         struct drm_i915_gem_object *obj;
2802         int plane = intel_crtc->plane;
2803         unsigned long linear_offset;
2804         u32 dspcntr;
2805         i915_reg_t reg = DSPCNTR(plane);
2806         int pixel_size;
2807
2808         if (!visible || !fb) {
2809                 I915_WRITE(reg, 0);
2810                 I915_WRITE(DSPSURF(plane), 0);
2811                 POSTING_READ(reg);
2812                 return;
2813         }
2814
2815         obj = intel_fb_obj(fb);
2816         if (WARN_ON(obj == NULL))
2817                 return;
2818
2819         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2820
2821         dspcntr = DISPPLANE_GAMMA_ENABLE;
2822
2823         dspcntr |= DISPLAY_PLANE_ENABLE;
2824
2825         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2826                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2827
2828         switch (fb->pixel_format) {
2829         case DRM_FORMAT_C8:
2830                 dspcntr |= DISPPLANE_8BPP;
2831                 break;
2832         case DRM_FORMAT_RGB565:
2833                 dspcntr |= DISPPLANE_BGRX565;
2834                 break;
2835         case DRM_FORMAT_XRGB8888:
2836                 dspcntr |= DISPPLANE_BGRX888;
2837                 break;
2838         case DRM_FORMAT_XBGR8888:
2839                 dspcntr |= DISPPLANE_RGBX888;
2840                 break;
2841         case DRM_FORMAT_XRGB2101010:
2842                 dspcntr |= DISPPLANE_BGRX101010;
2843                 break;
2844         case DRM_FORMAT_XBGR2101010:
2845                 dspcntr |= DISPPLANE_RGBX101010;
2846                 break;
2847         default:
2848                 BUG();
2849         }
2850
2851         if (obj->tiling_mode != I915_TILING_NONE)
2852                 dspcntr |= DISPPLANE_TILED;
2853
2854         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2855                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2856
2857         linear_offset = y * fb->pitches[0] + x * pixel_size;
2858         intel_crtc->dspaddr_offset =
2859                 intel_gen4_compute_page_offset(dev_priv,
2860                                                &x, &y, obj->tiling_mode,
2861                                                pixel_size,
2862                                                fb->pitches[0]);
2863         linear_offset -= intel_crtc->dspaddr_offset;
2864         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2865                 dspcntr |= DISPPLANE_ROTATE_180;
2866
2867                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2868                         x += (intel_crtc->config->pipe_src_w - 1);
2869                         y += (intel_crtc->config->pipe_src_h - 1);
2870
2871                         /* Finding the last pixel of the last line of the display
2872                         data and adding to linear_offset*/
2873                         linear_offset +=
2874                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2875                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2876                 }
2877         }
2878
2879         intel_crtc->adjusted_x = x;
2880         intel_crtc->adjusted_y = y;
2881
2882         I915_WRITE(reg, dspcntr);
2883
2884         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2885         I915_WRITE(DSPSURF(plane),
2886                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2887         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2888                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2889         } else {
2890                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2891                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2892         }
2893         POSTING_READ(reg);
2894 }
2895
2896 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2897                               uint32_t pixel_format)
2898 {
2899         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2900
2901         /*
2902          * The stride is either expressed as a multiple of 64 bytes
2903          * chunks for linear buffers or in number of tiles for tiled
2904          * buffers.
2905          */
2906         switch (fb_modifier) {
2907         case DRM_FORMAT_MOD_NONE:
2908                 return 64;
2909         case I915_FORMAT_MOD_X_TILED:
2910                 if (INTEL_INFO(dev)->gen == 2)
2911                         return 128;
2912                 return 512;
2913         case I915_FORMAT_MOD_Y_TILED:
2914                 /* No need to check for old gens and Y tiling since this is
2915                  * about the display engine and those will be blocked before
2916                  * we get here.
2917                  */
2918                 return 128;
2919         case I915_FORMAT_MOD_Yf_TILED:
2920                 if (bits_per_pixel == 8)
2921                         return 64;
2922                 else
2923                         return 128;
2924         default:
2925                 MISSING_CASE(fb_modifier);
2926                 return 64;
2927         }
2928 }
2929
2930 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2931                            struct drm_i915_gem_object *obj,
2932                            unsigned int plane)
2933 {
2934         struct i915_ggtt_view view;
2935         struct i915_vma *vma;
2936         u64 offset;
2937
2938         intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
2939                                 intel_plane->base.state);
2940
2941         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2942         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2943                 view.type))
2944                 return -1;
2945
2946         offset = vma->node.start;
2947
2948         if (plane == 1) {
2949                 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2950                           PAGE_SIZE;
2951         }
2952
2953         WARN_ON(upper_32_bits(offset));
2954
2955         return lower_32_bits(offset);
2956 }
2957
2958 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2959 {
2960         struct drm_device *dev = intel_crtc->base.dev;
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962
2963         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2964         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2965         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2966 }
2967
2968 /*
2969  * This function detaches (aka. unbinds) unused scalers in hardware
2970  */
2971 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2972 {
2973         struct intel_crtc_scaler_state *scaler_state;
2974         int i;
2975
2976         scaler_state = &intel_crtc->config->scaler_state;
2977
2978         /* loop through and disable scalers that aren't in use */
2979         for (i = 0; i < intel_crtc->num_scalers; i++) {
2980                 if (!scaler_state->scalers[i].in_use)
2981                         skl_detach_scaler(intel_crtc, i);
2982         }
2983 }
2984
2985 u32 skl_plane_ctl_format(uint32_t pixel_format)
2986 {
2987         switch (pixel_format) {
2988         case DRM_FORMAT_C8:
2989                 return PLANE_CTL_FORMAT_INDEXED;
2990         case DRM_FORMAT_RGB565:
2991                 return PLANE_CTL_FORMAT_RGB_565;
2992         case DRM_FORMAT_XBGR8888:
2993                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2994         case DRM_FORMAT_XRGB8888:
2995                 return PLANE_CTL_FORMAT_XRGB_8888;
2996         /*
2997          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2998          * to be already pre-multiplied. We need to add a knob (or a different
2999          * DRM_FORMAT) for user-space to configure that.
3000          */
3001         case DRM_FORMAT_ABGR8888:
3002                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3003                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3004         case DRM_FORMAT_ARGB8888:
3005                 return PLANE_CTL_FORMAT_XRGB_8888 |
3006                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3007         case DRM_FORMAT_XRGB2101010:
3008                 return PLANE_CTL_FORMAT_XRGB_2101010;
3009         case DRM_FORMAT_XBGR2101010:
3010                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3011         case DRM_FORMAT_YUYV:
3012                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3013         case DRM_FORMAT_YVYU:
3014                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3015         case DRM_FORMAT_UYVY:
3016                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3017         case DRM_FORMAT_VYUY:
3018                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3019         default:
3020                 MISSING_CASE(pixel_format);
3021         }
3022
3023         return 0;
3024 }
3025
3026 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3027 {
3028         switch (fb_modifier) {
3029         case DRM_FORMAT_MOD_NONE:
3030                 break;
3031         case I915_FORMAT_MOD_X_TILED:
3032                 return PLANE_CTL_TILED_X;
3033         case I915_FORMAT_MOD_Y_TILED:
3034                 return PLANE_CTL_TILED_Y;
3035         case I915_FORMAT_MOD_Yf_TILED:
3036                 return PLANE_CTL_TILED_YF;
3037         default:
3038                 MISSING_CASE(fb_modifier);
3039         }
3040
3041         return 0;
3042 }
3043
3044 u32 skl_plane_ctl_rotation(unsigned int rotation)
3045 {
3046         switch (rotation) {
3047         case BIT(DRM_ROTATE_0):
3048                 break;
3049         /*
3050          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3051          * while i915 HW rotation is clockwise, thats why this swapping.
3052          */
3053         case BIT(DRM_ROTATE_90):
3054                 return PLANE_CTL_ROTATE_270;
3055         case BIT(DRM_ROTATE_180):
3056                 return PLANE_CTL_ROTATE_180;
3057         case BIT(DRM_ROTATE_270):
3058                 return PLANE_CTL_ROTATE_90;
3059         default:
3060                 MISSING_CASE(rotation);
3061         }
3062
3063         return 0;
3064 }
3065
3066 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3067                                          struct drm_framebuffer *fb,
3068                                          int x, int y)
3069 {
3070         struct drm_device *dev = crtc->dev;
3071         struct drm_i915_private *dev_priv = dev->dev_private;
3072         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3073         struct drm_plane *plane = crtc->primary;
3074         bool visible = to_intel_plane_state(plane->state)->visible;
3075         struct drm_i915_gem_object *obj;
3076         int pipe = intel_crtc->pipe;
3077         u32 plane_ctl, stride_div, stride;
3078         u32 tile_height, plane_offset, plane_size;
3079         unsigned int rotation;
3080         int x_offset, y_offset;
3081         u32 surf_addr;
3082         struct intel_crtc_state *crtc_state = intel_crtc->config;
3083         struct intel_plane_state *plane_state;
3084         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3085         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3086         int scaler_id = -1;
3087
3088         plane_state = to_intel_plane_state(plane->state);
3089
3090         if (!visible || !fb) {
3091                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3092                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3093                 POSTING_READ(PLANE_CTL(pipe, 0));
3094                 return;
3095         }
3096
3097         plane_ctl = PLANE_CTL_ENABLE |
3098                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3099                     PLANE_CTL_PIPE_CSC_ENABLE;
3100
3101         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3102         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3103         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3104
3105         rotation = plane->state->rotation;
3106         plane_ctl |= skl_plane_ctl_rotation(rotation);
3107
3108         obj = intel_fb_obj(fb);
3109         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3110                                                fb->pixel_format);
3111         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3112
3113         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3114
3115         scaler_id = plane_state->scaler_id;
3116         src_x = plane_state->src.x1 >> 16;
3117         src_y = plane_state->src.y1 >> 16;
3118         src_w = drm_rect_width(&plane_state->src) >> 16;
3119         src_h = drm_rect_height(&plane_state->src) >> 16;
3120         dst_x = plane_state->dst.x1;
3121         dst_y = plane_state->dst.y1;
3122         dst_w = drm_rect_width(&plane_state->dst);
3123         dst_h = drm_rect_height(&plane_state->dst);
3124
3125         WARN_ON(x != src_x || y != src_y);
3126
3127         if (intel_rotation_90_or_270(rotation)) {
3128                 /* stride = Surface height in tiles */
3129                 tile_height = intel_tile_height(dev, fb->pixel_format,
3130                                                 fb->modifier[0], 0);
3131                 stride = DIV_ROUND_UP(fb->height, tile_height);
3132                 x_offset = stride * tile_height - y - src_h;
3133                 y_offset = x;
3134                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3135         } else {
3136                 stride = fb->pitches[0] / stride_div;
3137                 x_offset = x;
3138                 y_offset = y;
3139                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3140         }
3141         plane_offset = y_offset << 16 | x_offset;
3142
3143         intel_crtc->adjusted_x = x_offset;
3144         intel_crtc->adjusted_y = y_offset;
3145
3146         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3147         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3148         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3149         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3150
3151         if (scaler_id >= 0) {
3152                 uint32_t ps_ctrl = 0;
3153
3154                 WARN_ON(!dst_w || !dst_h);
3155                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3156                         crtc_state->scaler_state.scalers[scaler_id].mode;
3157                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3158                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3159                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3160                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3161                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3162         } else {
3163                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3164         }
3165
3166         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3167
3168         POSTING_READ(PLANE_SURF(pipe, 0));
3169 }
3170
3171 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3172 static int
3173 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3174                            int x, int y, enum mode_set_atomic state)
3175 {
3176         struct drm_device *dev = crtc->dev;
3177         struct drm_i915_private *dev_priv = dev->dev_private;
3178
3179         if (dev_priv->fbc.deactivate)
3180                 dev_priv->fbc.deactivate(dev_priv);
3181
3182         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3183
3184         return 0;
3185 }
3186
3187 static void intel_complete_page_flips(struct drm_device *dev)
3188 {
3189         struct drm_crtc *crtc;
3190
3191         for_each_crtc(dev, crtc) {
3192                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3193                 enum plane plane = intel_crtc->plane;
3194
3195                 intel_prepare_page_flip(dev, plane);
3196                 intel_finish_page_flip_plane(dev, plane);
3197         }
3198 }
3199
3200 static void intel_update_primary_planes(struct drm_device *dev)
3201 {
3202         struct drm_crtc *crtc;
3203
3204         for_each_crtc(dev, crtc) {
3205                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3206                 struct intel_plane_state *plane_state;
3207
3208                 drm_modeset_lock_crtc(crtc, &plane->base);
3209                 plane_state = to_intel_plane_state(plane->base.state);
3210
3211                 if (crtc->state->active && plane_state->base.fb)
3212                         plane->commit_plane(&plane->base, plane_state);
3213
3214                 drm_modeset_unlock_crtc(crtc);
3215         }
3216 }
3217
3218 void intel_prepare_reset(struct drm_device *dev)
3219 {
3220         /* no reset support for gen2 */
3221         if (IS_GEN2(dev))
3222                 return;
3223
3224         /* reset doesn't touch the display */
3225         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3226                 return;
3227
3228         drm_modeset_lock_all(dev);
3229         /*
3230          * Disabling the crtcs gracefully seems nicer. Also the
3231          * g33 docs say we should at least disable all the planes.
3232          */
3233         intel_display_suspend(dev);
3234 }
3235
3236 void intel_finish_reset(struct drm_device *dev)
3237 {
3238         struct drm_i915_private *dev_priv = to_i915(dev);
3239
3240         /*
3241          * Flips in the rings will be nuked by the reset,
3242          * so complete all pending flips so that user space
3243          * will get its events and not get stuck.
3244          */
3245         intel_complete_page_flips(dev);
3246
3247         /* no reset support for gen2 */
3248         if (IS_GEN2(dev))
3249                 return;
3250
3251         /* reset doesn't touch the display */
3252         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3253                 /*
3254                  * Flips in the rings have been nuked by the reset,
3255                  * so update the base address of all primary
3256                  * planes to the the last fb to make sure we're
3257                  * showing the correct fb after a reset.
3258                  *
3259                  * FIXME: Atomic will make this obsolete since we won't schedule
3260                  * CS-based flips (which might get lost in gpu resets) any more.
3261                  */
3262                 intel_update_primary_planes(dev);
3263                 return;
3264         }
3265
3266         /*
3267          * The display has been reset as well,
3268          * so need a full re-initialization.
3269          */
3270         intel_runtime_pm_disable_interrupts(dev_priv);
3271         intel_runtime_pm_enable_interrupts(dev_priv);
3272
3273         intel_modeset_init_hw(dev);
3274
3275         spin_lock_irq(&dev_priv->irq_lock);
3276         if (dev_priv->display.hpd_irq_setup)
3277                 dev_priv->display.hpd_irq_setup(dev);
3278         spin_unlock_irq(&dev_priv->irq_lock);
3279
3280         intel_display_resume(dev);
3281
3282         intel_hpd_init(dev_priv);
3283
3284         drm_modeset_unlock_all(dev);
3285 }
3286
3287 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3288 {
3289         struct drm_device *dev = crtc->dev;
3290         struct drm_i915_private *dev_priv = dev->dev_private;
3291         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3292         bool pending;
3293
3294         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3295             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3296                 return false;
3297
3298         spin_lock_irq(&dev->event_lock);
3299         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3300         spin_unlock_irq(&dev->event_lock);
3301
3302         return pending;
3303 }
3304
3305 static void intel_update_pipe_config(struct intel_crtc *crtc,
3306                                      struct intel_crtc_state *old_crtc_state)
3307 {
3308         struct drm_device *dev = crtc->base.dev;
3309         struct drm_i915_private *dev_priv = dev->dev_private;
3310         struct intel_crtc_state *pipe_config =
3311                 to_intel_crtc_state(crtc->base.state);
3312
3313         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3314         crtc->base.mode = crtc->base.state->mode;
3315
3316         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3317                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3318                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3319
3320         if (HAS_DDI(dev))
3321                 intel_set_pipe_csc(&crtc->base);
3322
3323         /*
3324          * Update pipe size and adjust fitter if needed: the reason for this is
3325          * that in compute_mode_changes we check the native mode (not the pfit
3326          * mode) to see if we can flip rather than do a full mode set. In the
3327          * fastboot case, we'll flip, but if we don't update the pipesrc and
3328          * pfit state, we'll end up with a big fb scanned out into the wrong
3329          * sized surface.
3330          */
3331
3332         I915_WRITE(PIPESRC(crtc->pipe),
3333                    ((pipe_config->pipe_src_w - 1) << 16) |
3334                    (pipe_config->pipe_src_h - 1));
3335
3336         /* on skylake this is done by detaching scalers */
3337         if (INTEL_INFO(dev)->gen >= 9) {
3338                 skl_detach_scalers(crtc);
3339
3340                 if (pipe_config->pch_pfit.enabled)
3341                         skylake_pfit_enable(crtc);
3342         } else if (HAS_PCH_SPLIT(dev)) {
3343                 if (pipe_config->pch_pfit.enabled)
3344                         ironlake_pfit_enable(crtc);
3345                 else if (old_crtc_state->pch_pfit.enabled)
3346                         ironlake_pfit_disable(crtc, true);
3347         }
3348 }
3349
3350 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3351 {
3352         struct drm_device *dev = crtc->dev;
3353         struct drm_i915_private *dev_priv = dev->dev_private;
3354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355         int pipe = intel_crtc->pipe;
3356         i915_reg_t reg;
3357         u32 temp;
3358
3359         /* enable normal train */
3360         reg = FDI_TX_CTL(pipe);
3361         temp = I915_READ(reg);
3362         if (IS_IVYBRIDGE(dev)) {
3363                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3364                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3365         } else {
3366                 temp &= ~FDI_LINK_TRAIN_NONE;
3367                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3368         }
3369         I915_WRITE(reg, temp);
3370
3371         reg = FDI_RX_CTL(pipe);
3372         temp = I915_READ(reg);
3373         if (HAS_PCH_CPT(dev)) {
3374                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3375                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3376         } else {
3377                 temp &= ~FDI_LINK_TRAIN_NONE;
3378                 temp |= FDI_LINK_TRAIN_NONE;
3379         }
3380         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3381
3382         /* wait one idle pattern time */
3383         POSTING_READ(reg);
3384         udelay(1000);
3385
3386         /* IVB wants error correction enabled */
3387         if (IS_IVYBRIDGE(dev))
3388                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3389                            FDI_FE_ERRC_ENABLE);
3390 }
3391
3392 /* The FDI link training functions for ILK/Ibexpeak. */
3393 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3394 {
3395         struct drm_device *dev = crtc->dev;
3396         struct drm_i915_private *dev_priv = dev->dev_private;
3397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3398         int pipe = intel_crtc->pipe;
3399         i915_reg_t reg;
3400         u32 temp, tries;
3401
3402         /* FDI needs bits from pipe first */
3403         assert_pipe_enabled(dev_priv, pipe);
3404
3405         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3406            for train result */
3407         reg = FDI_RX_IMR(pipe);
3408         temp = I915_READ(reg);
3409         temp &= ~FDI_RX_SYMBOL_LOCK;
3410         temp &= ~FDI_RX_BIT_LOCK;
3411         I915_WRITE(reg, temp);
3412         I915_READ(reg);
3413         udelay(150);
3414
3415         /* enable CPU FDI TX and PCH FDI RX */
3416         reg = FDI_TX_CTL(pipe);
3417         temp = I915_READ(reg);
3418         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3419         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3420         temp &= ~FDI_LINK_TRAIN_NONE;
3421         temp |= FDI_LINK_TRAIN_PATTERN_1;
3422         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3423
3424         reg = FDI_RX_CTL(pipe);
3425         temp = I915_READ(reg);
3426         temp &= ~FDI_LINK_TRAIN_NONE;
3427         temp |= FDI_LINK_TRAIN_PATTERN_1;
3428         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3429
3430         POSTING_READ(reg);
3431         udelay(150);
3432
3433         /* Ironlake workaround, enable clock pointer after FDI enable*/
3434         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3435         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3436                    FDI_RX_PHASE_SYNC_POINTER_EN);
3437
3438         reg = FDI_RX_IIR(pipe);
3439         for (tries = 0; tries < 5; tries++) {
3440                 temp = I915_READ(reg);
3441                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3442
3443                 if ((temp & FDI_RX_BIT_LOCK)) {
3444                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3445                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3446                         break;
3447                 }
3448         }
3449         if (tries == 5)
3450                 DRM_ERROR("FDI train 1 fail!\n");
3451
3452         /* Train 2 */
3453         reg = FDI_TX_CTL(pipe);
3454         temp = I915_READ(reg);
3455         temp &= ~FDI_LINK_TRAIN_NONE;
3456         temp |= FDI_LINK_TRAIN_PATTERN_2;
3457         I915_WRITE(reg, temp);
3458
3459         reg = FDI_RX_CTL(pipe);
3460         temp = I915_READ(reg);
3461         temp &= ~FDI_LINK_TRAIN_NONE;
3462         temp |= FDI_LINK_TRAIN_PATTERN_2;
3463         I915_WRITE(reg, temp);
3464
3465         POSTING_READ(reg);
3466         udelay(150);
3467
3468         reg = FDI_RX_IIR(pipe);
3469         for (tries = 0; tries < 5; tries++) {
3470                 temp = I915_READ(reg);
3471                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3472
3473                 if (temp & FDI_RX_SYMBOL_LOCK) {
3474                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3475                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3476                         break;
3477                 }
3478         }
3479         if (tries == 5)
3480                 DRM_ERROR("FDI train 2 fail!\n");
3481
3482         DRM_DEBUG_KMS("FDI train done\n");
3483
3484 }
3485
3486 static const int snb_b_fdi_train_param[] = {
3487         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3488         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3489         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3490         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3491 };
3492
3493 /* The FDI link training functions for SNB/Cougarpoint. */
3494 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3495 {
3496         struct drm_device *dev = crtc->dev;
3497         struct drm_i915_private *dev_priv = dev->dev_private;
3498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3499         int pipe = intel_crtc->pipe;
3500         i915_reg_t reg;
3501         u32 temp, i, retry;
3502
3503         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3504            for train result */
3505         reg = FDI_RX_IMR(pipe);
3506         temp = I915_READ(reg);
3507         temp &= ~FDI_RX_SYMBOL_LOCK;
3508         temp &= ~FDI_RX_BIT_LOCK;
3509         I915_WRITE(reg, temp);
3510
3511         POSTING_READ(reg);
3512         udelay(150);
3513
3514         /* enable CPU FDI TX and PCH FDI RX */
3515         reg = FDI_TX_CTL(pipe);
3516         temp = I915_READ(reg);
3517         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3518         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3519         temp &= ~FDI_LINK_TRAIN_NONE;
3520         temp |= FDI_LINK_TRAIN_PATTERN_1;
3521         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3522         /* SNB-B */
3523         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3524         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3525
3526         I915_WRITE(FDI_RX_MISC(pipe),
3527                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3528
3529         reg = FDI_RX_CTL(pipe);
3530         temp = I915_READ(reg);
3531         if (HAS_PCH_CPT(dev)) {
3532                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3533                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3534         } else {
3535                 temp &= ~FDI_LINK_TRAIN_NONE;
3536                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3537         }
3538         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3539
3540         POSTING_READ(reg);
3541         udelay(150);
3542
3543         for (i = 0; i < 4; i++) {
3544                 reg = FDI_TX_CTL(pipe);
3545                 temp = I915_READ(reg);
3546                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3547                 temp |= snb_b_fdi_train_param[i];
3548                 I915_WRITE(reg, temp);
3549
3550                 POSTING_READ(reg);
3551                 udelay(500);
3552
3553                 for (retry = 0; retry < 5; retry++) {
3554                         reg = FDI_RX_IIR(pipe);
3555                         temp = I915_READ(reg);
3556                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3557                         if (temp & FDI_RX_BIT_LOCK) {
3558                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3559                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3560                                 break;
3561                         }
3562                         udelay(50);
3563                 }
3564                 if (retry < 5)
3565                         break;
3566         }
3567         if (i == 4)
3568                 DRM_ERROR("FDI train 1 fail!\n");
3569
3570         /* Train 2 */
3571         reg = FDI_TX_CTL(pipe);
3572         temp = I915_READ(reg);
3573         temp &= ~FDI_LINK_TRAIN_NONE;
3574         temp |= FDI_LINK_TRAIN_PATTERN_2;
3575         if (IS_GEN6(dev)) {
3576                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3577                 /* SNB-B */
3578                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3579         }
3580         I915_WRITE(reg, temp);
3581
3582         reg = FDI_RX_CTL(pipe);
3583         temp = I915_READ(reg);
3584         if (HAS_PCH_CPT(dev)) {
3585                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3586                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3587         } else {
3588                 temp &= ~FDI_LINK_TRAIN_NONE;
3589                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3590         }
3591         I915_WRITE(reg, temp);
3592
3593         POSTING_READ(reg);
3594         udelay(150);
3595
3596         for (i = 0; i < 4; i++) {
3597                 reg = FDI_TX_CTL(pipe);
3598                 temp = I915_READ(reg);
3599                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3600                 temp |= snb_b_fdi_train_param[i];
3601                 I915_WRITE(reg, temp);
3602
3603                 POSTING_READ(reg);
3604                 udelay(500);
3605
3606                 for (retry = 0; retry < 5; retry++) {
3607                         reg = FDI_RX_IIR(pipe);
3608                         temp = I915_READ(reg);
3609                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3610                         if (temp & FDI_RX_SYMBOL_LOCK) {
3611                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3612                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3613                                 break;
3614                         }
3615                         udelay(50);
3616                 }
3617                 if (retry < 5)
3618                         break;
3619         }
3620         if (i == 4)
3621                 DRM_ERROR("FDI train 2 fail!\n");
3622
3623         DRM_DEBUG_KMS("FDI train done.\n");
3624 }
3625
3626 /* Manual link training for Ivy Bridge A0 parts */
3627 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3628 {
3629         struct drm_device *dev = crtc->dev;
3630         struct drm_i915_private *dev_priv = dev->dev_private;
3631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3632         int pipe = intel_crtc->pipe;
3633         i915_reg_t reg;
3634         u32 temp, i, j;
3635
3636         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3637            for train result */
3638         reg = FDI_RX_IMR(pipe);
3639         temp = I915_READ(reg);
3640         temp &= ~FDI_RX_SYMBOL_LOCK;
3641         temp &= ~FDI_RX_BIT_LOCK;
3642         I915_WRITE(reg, temp);
3643
3644         POSTING_READ(reg);
3645         udelay(150);
3646
3647         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3648                       I915_READ(FDI_RX_IIR(pipe)));
3649
3650         /* Try each vswing and preemphasis setting twice before moving on */
3651         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3652                 /* disable first in case we need to retry */
3653                 reg = FDI_TX_CTL(pipe);
3654                 temp = I915_READ(reg);
3655                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3656                 temp &= ~FDI_TX_ENABLE;
3657                 I915_WRITE(reg, temp);
3658
3659                 reg = FDI_RX_CTL(pipe);
3660                 temp = I915_READ(reg);
3661                 temp &= ~FDI_LINK_TRAIN_AUTO;
3662                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3663                 temp &= ~FDI_RX_ENABLE;
3664                 I915_WRITE(reg, temp);
3665
3666                 /* enable CPU FDI TX and PCH FDI RX */
3667                 reg = FDI_TX_CTL(pipe);
3668                 temp = I915_READ(reg);
3669                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3670                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3671                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3672                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3673                 temp |= snb_b_fdi_train_param[j/2];
3674                 temp |= FDI_COMPOSITE_SYNC;
3675                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3676
3677                 I915_WRITE(FDI_RX_MISC(pipe),
3678                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3679
3680                 reg = FDI_RX_CTL(pipe);
3681                 temp = I915_READ(reg);
3682                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3683                 temp |= FDI_COMPOSITE_SYNC;
3684                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3685
3686                 POSTING_READ(reg);
3687                 udelay(1); /* should be 0.5us */
3688
3689                 for (i = 0; i < 4; i++) {
3690                         reg = FDI_RX_IIR(pipe);
3691                         temp = I915_READ(reg);
3692                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3693
3694                         if (temp & FDI_RX_BIT_LOCK ||
3695                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3696                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3697                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3698                                               i);
3699                                 break;
3700                         }
3701                         udelay(1); /* should be 0.5us */
3702                 }
3703                 if (i == 4) {
3704                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3705                         continue;
3706                 }
3707
3708                 /* Train 2 */
3709                 reg = FDI_TX_CTL(pipe);
3710                 temp = I915_READ(reg);
3711                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3712                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3713                 I915_WRITE(reg, temp);
3714
3715                 reg = FDI_RX_CTL(pipe);
3716                 temp = I915_READ(reg);
3717                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3718                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3719                 I915_WRITE(reg, temp);
3720
3721                 POSTING_READ(reg);
3722                 udelay(2); /* should be 1.5us */
3723
3724                 for (i = 0; i < 4; i++) {
3725                         reg = FDI_RX_IIR(pipe);
3726                         temp = I915_READ(reg);
3727                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3728
3729                         if (temp & FDI_RX_SYMBOL_LOCK ||
3730                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3731                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3732                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3733                                               i);
3734                                 goto train_done;
3735                         }
3736                         udelay(2); /* should be 1.5us */
3737                 }
3738                 if (i == 4)
3739                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3740         }
3741
3742 train_done:
3743         DRM_DEBUG_KMS("FDI train done.\n");
3744 }
3745
3746 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3747 {
3748         struct drm_device *dev = intel_crtc->base.dev;
3749         struct drm_i915_private *dev_priv = dev->dev_private;
3750         int pipe = intel_crtc->pipe;
3751         i915_reg_t reg;
3752         u32 temp;
3753
3754         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3755         reg = FDI_RX_CTL(pipe);
3756         temp = I915_READ(reg);
3757         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3758         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3759         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3760         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3761
3762         POSTING_READ(reg);
3763         udelay(200);
3764
3765         /* Switch from Rawclk to PCDclk */
3766         temp = I915_READ(reg);
3767         I915_WRITE(reg, temp | FDI_PCDCLK);
3768
3769         POSTING_READ(reg);
3770         udelay(200);
3771
3772         /* Enable CPU FDI TX PLL, always on for Ironlake */
3773         reg = FDI_TX_CTL(pipe);
3774         temp = I915_READ(reg);
3775         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3776                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3777
3778                 POSTING_READ(reg);
3779                 udelay(100);
3780         }
3781 }
3782
3783 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3784 {
3785         struct drm_device *dev = intel_crtc->base.dev;
3786         struct drm_i915_private *dev_priv = dev->dev_private;
3787         int pipe = intel_crtc->pipe;
3788         i915_reg_t reg;
3789         u32 temp;
3790
3791         /* Switch from PCDclk to Rawclk */
3792         reg = FDI_RX_CTL(pipe);
3793         temp = I915_READ(reg);
3794         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3795
3796         /* Disable CPU FDI TX PLL */
3797         reg = FDI_TX_CTL(pipe);
3798         temp = I915_READ(reg);
3799         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3800
3801         POSTING_READ(reg);
3802         udelay(100);
3803
3804         reg = FDI_RX_CTL(pipe);
3805         temp = I915_READ(reg);
3806         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3807
3808         /* Wait for the clocks to turn off. */
3809         POSTING_READ(reg);
3810         udelay(100);
3811 }
3812
3813 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3814 {
3815         struct drm_device *dev = crtc->dev;
3816         struct drm_i915_private *dev_priv = dev->dev_private;
3817         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3818         int pipe = intel_crtc->pipe;
3819         i915_reg_t reg;
3820         u32 temp;
3821
3822         /* disable CPU FDI tx and PCH FDI rx */
3823         reg = FDI_TX_CTL(pipe);
3824         temp = I915_READ(reg);
3825         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3826         POSTING_READ(reg);
3827
3828         reg = FDI_RX_CTL(pipe);
3829         temp = I915_READ(reg);
3830         temp &= ~(0x7 << 16);
3831         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3832         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3833
3834         POSTING_READ(reg);
3835         udelay(100);
3836
3837         /* Ironlake workaround, disable clock pointer after downing FDI */
3838         if (HAS_PCH_IBX(dev))
3839                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3840
3841         /* still set train pattern 1 */
3842         reg = FDI_TX_CTL(pipe);
3843         temp = I915_READ(reg);
3844         temp &= ~FDI_LINK_TRAIN_NONE;
3845         temp |= FDI_LINK_TRAIN_PATTERN_1;
3846         I915_WRITE(reg, temp);
3847
3848         reg = FDI_RX_CTL(pipe);
3849         temp = I915_READ(reg);
3850         if (HAS_PCH_CPT(dev)) {
3851                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3852                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3853         } else {
3854                 temp &= ~FDI_LINK_TRAIN_NONE;
3855                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3856         }
3857         /* BPC in FDI rx is consistent with that in PIPECONF */
3858         temp &= ~(0x07 << 16);
3859         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3860         I915_WRITE(reg, temp);
3861
3862         POSTING_READ(reg);
3863         udelay(100);
3864 }
3865
3866 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3867 {
3868         struct intel_crtc *crtc;
3869
3870         /* Note that we don't need to be called with mode_config.lock here
3871          * as our list of CRTC objects is static for the lifetime of the
3872          * device and so cannot disappear as we iterate. Similarly, we can
3873          * happily treat the predicates as racy, atomic checks as userspace
3874          * cannot claim and pin a new fb without at least acquring the
3875          * struct_mutex and so serialising with us.
3876          */
3877         for_each_intel_crtc(dev, crtc) {
3878                 if (atomic_read(&crtc->unpin_work_count) == 0)
3879                         continue;
3880
3881                 if (crtc->unpin_work)
3882                         intel_wait_for_vblank(dev, crtc->pipe);
3883
3884                 return true;
3885         }
3886
3887         return false;
3888 }
3889
3890 static void page_flip_completed(struct intel_crtc *intel_crtc)
3891 {
3892         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3893         struct intel_unpin_work *work = intel_crtc->unpin_work;
3894
3895         /* ensure that the unpin work is consistent wrt ->pending. */
3896         smp_rmb();
3897         intel_crtc->unpin_work = NULL;
3898
3899         if (work->event)
3900                 drm_send_vblank_event(intel_crtc->base.dev,
3901                                       intel_crtc->pipe,
3902                                       work->event);
3903
3904         drm_crtc_vblank_put(&intel_crtc->base);
3905
3906         wake_up_all(&dev_priv->pending_flip_queue);
3907         queue_work(dev_priv->wq, &work->work);
3908
3909         trace_i915_flip_complete(intel_crtc->plane,
3910                                  work->pending_flip_obj);
3911 }
3912
3913 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3914 {
3915         struct drm_device *dev = crtc->dev;
3916         struct drm_i915_private *dev_priv = dev->dev_private;
3917         long ret;
3918
3919         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3920
3921         ret = wait_event_interruptible_timeout(
3922                                         dev_priv->pending_flip_queue,
3923                                         !intel_crtc_has_pending_flip(crtc),
3924                                         60*HZ);
3925
3926         if (ret < 0)
3927                 return ret;
3928
3929         if (ret == 0) {
3930                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3931
3932                 spin_lock_irq(&dev->event_lock);
3933                 if (intel_crtc->unpin_work) {
3934                         WARN_ONCE(1, "Removing stuck page flip\n");
3935                         page_flip_completed(intel_crtc);
3936                 }
3937                 spin_unlock_irq(&dev->event_lock);
3938         }
3939
3940         return 0;
3941 }
3942
3943 /* Program iCLKIP clock to the desired frequency */
3944 static void lpt_program_iclkip(struct drm_crtc *crtc)
3945 {
3946         struct drm_device *dev = crtc->dev;
3947         struct drm_i915_private *dev_priv = dev->dev_private;
3948         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3949         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3950         u32 temp;
3951
3952         mutex_lock(&dev_priv->sb_lock);
3953
3954         /* It is necessary to ungate the pixclk gate prior to programming
3955          * the divisors, and gate it back when it is done.
3956          */
3957         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3958
3959         /* Disable SSCCTL */
3960         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3961                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3962                                 SBI_SSCCTL_DISABLE,
3963                         SBI_ICLK);
3964
3965         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3966         if (clock == 20000) {
3967                 auxdiv = 1;
3968                 divsel = 0x41;
3969                 phaseinc = 0x20;
3970         } else {
3971                 /* The iCLK virtual clock root frequency is in MHz,
3972                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3973                  * divisors, it is necessary to divide one by another, so we
3974                  * convert the virtual clock precision to KHz here for higher
3975                  * precision.
3976                  */
3977                 u32 iclk_virtual_root_freq = 172800 * 1000;
3978                 u32 iclk_pi_range = 64;
3979                 u32 desired_divisor, msb_divisor_value, pi_value;
3980
3981                 desired_divisor = (iclk_virtual_root_freq / clock);
3982                 msb_divisor_value = desired_divisor / iclk_pi_range;
3983                 pi_value = desired_divisor % iclk_pi_range;
3984
3985                 auxdiv = 0;
3986                 divsel = msb_divisor_value - 2;
3987                 phaseinc = pi_value;
3988         }
3989
3990         /* This should not happen with any sane values */
3991         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3992                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3993         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3994                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3995
3996         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3997                         clock,
3998                         auxdiv,
3999                         divsel,
4000                         phasedir,
4001                         phaseinc);
4002
4003         /* Program SSCDIVINTPHASE6 */
4004         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4005         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4006         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4007         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4008         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4009         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4010         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4011         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4012
4013         /* Program SSCAUXDIV */
4014         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4015         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4016         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4017         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4018
4019         /* Enable modulator and associated divider */
4020         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4021         temp &= ~SBI_SSCCTL_DISABLE;
4022         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4023
4024         /* Wait for initialization time */
4025         udelay(24);
4026
4027         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4028
4029         mutex_unlock(&dev_priv->sb_lock);
4030 }
4031
4032 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4033                                                 enum pipe pch_transcoder)
4034 {
4035         struct drm_device *dev = crtc->base.dev;
4036         struct drm_i915_private *dev_priv = dev->dev_private;
4037         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4038
4039         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4040                    I915_READ(HTOTAL(cpu_transcoder)));
4041         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4042                    I915_READ(HBLANK(cpu_transcoder)));
4043         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4044                    I915_READ(HSYNC(cpu_transcoder)));
4045
4046         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4047                    I915_READ(VTOTAL(cpu_transcoder)));
4048         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4049                    I915_READ(VBLANK(cpu_transcoder)));
4050         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4051                    I915_READ(VSYNC(cpu_transcoder)));
4052         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4053                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4054 }
4055
4056 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4057 {
4058         struct drm_i915_private *dev_priv = dev->dev_private;
4059         uint32_t temp;
4060
4061         temp = I915_READ(SOUTH_CHICKEN1);
4062         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4063                 return;
4064
4065         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4066         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4067
4068         temp &= ~FDI_BC_BIFURCATION_SELECT;
4069         if (enable)
4070                 temp |= FDI_BC_BIFURCATION_SELECT;
4071
4072         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4073         I915_WRITE(SOUTH_CHICKEN1, temp);
4074         POSTING_READ(SOUTH_CHICKEN1);
4075 }
4076
4077 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4078 {
4079         struct drm_device *dev = intel_crtc->base.dev;
4080
4081         switch (intel_crtc->pipe) {
4082         case PIPE_A:
4083                 break;
4084         case PIPE_B:
4085                 if (intel_crtc->config->fdi_lanes > 2)
4086                         cpt_set_fdi_bc_bifurcation(dev, false);
4087                 else
4088                         cpt_set_fdi_bc_bifurcation(dev, true);
4089
4090                 break;
4091         case PIPE_C:
4092                 cpt_set_fdi_bc_bifurcation(dev, true);
4093
4094                 break;
4095         default:
4096                 BUG();
4097         }
4098 }
4099
4100 /* Return which DP Port should be selected for Transcoder DP control */
4101 static enum port
4102 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4103 {
4104         struct drm_device *dev = crtc->dev;
4105         struct intel_encoder *encoder;
4106
4107         for_each_encoder_on_crtc(dev, crtc, encoder) {
4108                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4109                     encoder->type == INTEL_OUTPUT_EDP)
4110                         return enc_to_dig_port(&encoder->base)->port;
4111         }
4112
4113         return -1;
4114 }
4115
4116 /*
4117  * Enable PCH resources required for PCH ports:
4118  *   - PCH PLLs
4119  *   - FDI training & RX/TX
4120  *   - update transcoder timings
4121  *   - DP transcoding bits
4122  *   - transcoder
4123  */
4124 static void ironlake_pch_enable(struct drm_crtc *crtc)
4125 {
4126         struct drm_device *dev = crtc->dev;
4127         struct drm_i915_private *dev_priv = dev->dev_private;
4128         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4129         int pipe = intel_crtc->pipe;
4130         u32 temp;
4131
4132         assert_pch_transcoder_disabled(dev_priv, pipe);
4133
4134         if (IS_IVYBRIDGE(dev))
4135                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4136
4137         /* Write the TU size bits before fdi link training, so that error
4138          * detection works. */
4139         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4140                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4141
4142         /*
4143          * Sometimes spurious CPU pipe underruns happen during FDI
4144          * training, at least with VGA+HDMI cloning. Suppress them.
4145          */
4146         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4147
4148         /* For PCH output, training FDI link */
4149         dev_priv->display.fdi_link_train(crtc);
4150
4151         /* We need to program the right clock selection before writing the pixel
4152          * mutliplier into the DPLL. */
4153         if (HAS_PCH_CPT(dev)) {
4154                 u32 sel;
4155
4156                 temp = I915_READ(PCH_DPLL_SEL);
4157                 temp |= TRANS_DPLL_ENABLE(pipe);
4158                 sel = TRANS_DPLLB_SEL(pipe);
4159                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4160                         temp |= sel;
4161                 else
4162                         temp &= ~sel;
4163                 I915_WRITE(PCH_DPLL_SEL, temp);
4164         }
4165
4166         /* XXX: pch pll's can be enabled any time before we enable the PCH
4167          * transcoder, and we actually should do this to not upset any PCH
4168          * transcoder that already use the clock when we share it.
4169          *
4170          * Note that enable_shared_dpll tries to do the right thing, but
4171          * get_shared_dpll unconditionally resets the pll - we need that to have
4172          * the right LVDS enable sequence. */
4173         intel_enable_shared_dpll(intel_crtc);
4174
4175         /* set transcoder timing, panel must allow it */
4176         assert_panel_unlocked(dev_priv, pipe);
4177         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4178
4179         intel_fdi_normal_train(crtc);
4180
4181         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4182
4183         /* For PCH DP, enable TRANS_DP_CTL */
4184         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4185                 const struct drm_display_mode *adjusted_mode =
4186                         &intel_crtc->config->base.adjusted_mode;
4187                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4188                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4189                 temp = I915_READ(reg);
4190                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4191                           TRANS_DP_SYNC_MASK |
4192                           TRANS_DP_BPC_MASK);
4193                 temp |= TRANS_DP_OUTPUT_ENABLE;
4194                 temp |= bpc << 9; /* same format but at 11:9 */
4195
4196                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4197                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4198                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4199                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4200
4201                 switch (intel_trans_dp_port_sel(crtc)) {
4202                 case PORT_B:
4203                         temp |= TRANS_DP_PORT_SEL_B;
4204                         break;
4205                 case PORT_C:
4206                         temp |= TRANS_DP_PORT_SEL_C;
4207                         break;
4208                 case PORT_D:
4209                         temp |= TRANS_DP_PORT_SEL_D;
4210                         break;
4211                 default:
4212                         BUG();
4213                 }
4214
4215                 I915_WRITE(reg, temp);
4216         }
4217
4218         ironlake_enable_pch_transcoder(dev_priv, pipe);
4219 }
4220
4221 static void lpt_pch_enable(struct drm_crtc *crtc)
4222 {
4223         struct drm_device *dev = crtc->dev;
4224         struct drm_i915_private *dev_priv = dev->dev_private;
4225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4226         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4227
4228         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4229
4230         lpt_program_iclkip(crtc);
4231
4232         /* Set transcoder timing. */
4233         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4234
4235         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4236 }
4237
4238 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4239                                                 struct intel_crtc_state *crtc_state)
4240 {
4241         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4242         struct intel_shared_dpll *pll;
4243         struct intel_shared_dpll_config *shared_dpll;
4244         enum intel_dpll_id i;
4245         int max = dev_priv->num_shared_dpll;
4246
4247         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4248
4249         if (HAS_PCH_IBX(dev_priv->dev)) {
4250                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4251                 i = (enum intel_dpll_id) crtc->pipe;
4252                 pll = &dev_priv->shared_dplls[i];
4253
4254                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4255                               crtc->base.base.id, pll->name);
4256
4257                 WARN_ON(shared_dpll[i].crtc_mask);
4258
4259                 goto found;
4260         }
4261
4262         if (IS_BROXTON(dev_priv->dev)) {
4263                 /* PLL is attached to port in bxt */
4264                 struct intel_encoder *encoder;
4265                 struct intel_digital_port *intel_dig_port;
4266
4267                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4268                 if (WARN_ON(!encoder))
4269                         return NULL;
4270
4271                 intel_dig_port = enc_to_dig_port(&encoder->base);
4272                 /* 1:1 mapping between ports and PLLs */
4273                 i = (enum intel_dpll_id)intel_dig_port->port;
4274                 pll = &dev_priv->shared_dplls[i];
4275                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4276                         crtc->base.base.id, pll->name);
4277                 WARN_ON(shared_dpll[i].crtc_mask);
4278
4279                 goto found;
4280         } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4281                 /* Do not consider SPLL */
4282                 max = 2;
4283
4284         for (i = 0; i < max; i++) {
4285                 pll = &dev_priv->shared_dplls[i];
4286
4287                 /* Only want to check enabled timings first */
4288                 if (shared_dpll[i].crtc_mask == 0)
4289                         continue;
4290
4291                 if (memcmp(&crtc_state->dpll_hw_state,
4292                            &shared_dpll[i].hw_state,
4293                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4294                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4295                                       crtc->base.base.id, pll->name,
4296                                       shared_dpll[i].crtc_mask,
4297                                       pll->active);
4298                         goto found;
4299                 }
4300         }
4301
4302         /* Ok no matching timings, maybe there's a free one? */
4303         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4304                 pll = &dev_priv->shared_dplls[i];
4305                 if (shared_dpll[i].crtc_mask == 0) {
4306                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4307                                       crtc->base.base.id, pll->name);
4308                         goto found;
4309                 }
4310         }
4311
4312         return NULL;
4313
4314 found:
4315         if (shared_dpll[i].crtc_mask == 0)
4316                 shared_dpll[i].hw_state =
4317                         crtc_state->dpll_hw_state;
4318
4319         crtc_state->shared_dpll = i;
4320         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4321                          pipe_name(crtc->pipe));
4322
4323         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4324
4325         return pll;
4326 }
4327
4328 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4329 {
4330         struct drm_i915_private *dev_priv = to_i915(state->dev);
4331         struct intel_shared_dpll_config *shared_dpll;
4332         struct intel_shared_dpll *pll;
4333         enum intel_dpll_id i;
4334
4335         if (!to_intel_atomic_state(state)->dpll_set)
4336                 return;
4337
4338         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4339         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4340                 pll = &dev_priv->shared_dplls[i];
4341                 pll->config = shared_dpll[i];
4342         }
4343 }
4344
4345 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4346 {
4347         struct drm_i915_private *dev_priv = dev->dev_private;
4348         i915_reg_t dslreg = PIPEDSL(pipe);
4349         u32 temp;
4350
4351         temp = I915_READ(dslreg);
4352         udelay(500);
4353         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4354                 if (wait_for(I915_READ(dslreg) != temp, 5))
4355                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4356         }
4357 }
4358
4359 static int
4360 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4361                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4362                   int src_w, int src_h, int dst_w, int dst_h)
4363 {
4364         struct intel_crtc_scaler_state *scaler_state =
4365                 &crtc_state->scaler_state;
4366         struct intel_crtc *intel_crtc =
4367                 to_intel_crtc(crtc_state->base.crtc);
4368         int need_scaling;
4369
4370         need_scaling = intel_rotation_90_or_270(rotation) ?
4371                 (src_h != dst_w || src_w != dst_h):
4372                 (src_w != dst_w || src_h != dst_h);
4373
4374         /*
4375          * if plane is being disabled or scaler is no more required or force detach
4376          *  - free scaler binded to this plane/crtc
4377          *  - in order to do this, update crtc->scaler_usage
4378          *
4379          * Here scaler state in crtc_state is set free so that
4380          * scaler can be assigned to other user. Actual register
4381          * update to free the scaler is done in plane/panel-fit programming.
4382          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4383          */
4384         if (force_detach || !need_scaling) {
4385                 if (*scaler_id >= 0) {
4386                         scaler_state->scaler_users &= ~(1 << scaler_user);
4387                         scaler_state->scalers[*scaler_id].in_use = 0;
4388
4389                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4390                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4391                                 intel_crtc->pipe, scaler_user, *scaler_id,
4392                                 scaler_state->scaler_users);
4393                         *scaler_id = -1;
4394                 }
4395                 return 0;
4396         }
4397
4398         /* range checks */
4399         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4400                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4401
4402                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4403                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4404                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4405                         "size is out of scaler range\n",
4406                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4407                 return -EINVAL;
4408         }
4409
4410         /* mark this plane as a scaler user in crtc_state */
4411         scaler_state->scaler_users |= (1 << scaler_user);
4412         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4413                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4414                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4415                 scaler_state->scaler_users);
4416
4417         return 0;
4418 }
4419
4420 /**
4421  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4422  *
4423  * @state: crtc's scaler state
4424  *
4425  * Return
4426  *     0 - scaler_usage updated successfully
4427  *    error - requested scaling cannot be supported or other error condition
4428  */
4429 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4430 {
4431         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4432         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4433
4434         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4435                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4436
4437         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4438                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4439                 state->pipe_src_w, state->pipe_src_h,
4440                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4441 }
4442
4443 /**
4444  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4445  *
4446  * @state: crtc's scaler state
4447  * @plane_state: atomic plane state to update
4448  *
4449  * Return
4450  *     0 - scaler_usage updated successfully
4451  *    error - requested scaling cannot be supported or other error condition
4452  */
4453 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4454                                    struct intel_plane_state *plane_state)
4455 {
4456
4457         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4458         struct intel_plane *intel_plane =
4459                 to_intel_plane(plane_state->base.plane);
4460         struct drm_framebuffer *fb = plane_state->base.fb;
4461         int ret;
4462
4463         bool force_detach = !fb || !plane_state->visible;
4464
4465         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4466                       intel_plane->base.base.id, intel_crtc->pipe,
4467                       drm_plane_index(&intel_plane->base));
4468
4469         ret = skl_update_scaler(crtc_state, force_detach,
4470                                 drm_plane_index(&intel_plane->base),
4471                                 &plane_state->scaler_id,
4472                                 plane_state->base.rotation,
4473                                 drm_rect_width(&plane_state->src) >> 16,
4474                                 drm_rect_height(&plane_state->src) >> 16,
4475                                 drm_rect_width(&plane_state->dst),
4476                                 drm_rect_height(&plane_state->dst));
4477
4478         if (ret || plane_state->scaler_id < 0)
4479                 return ret;
4480
4481         /* check colorkey */
4482         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4483                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4484                               intel_plane->base.base.id);
4485                 return -EINVAL;
4486         }
4487
4488         /* Check src format */
4489         switch (fb->pixel_format) {
4490         case DRM_FORMAT_RGB565:
4491         case DRM_FORMAT_XBGR8888:
4492         case DRM_FORMAT_XRGB8888:
4493         case DRM_FORMAT_ABGR8888:
4494         case DRM_FORMAT_ARGB8888:
4495         case DRM_FORMAT_XRGB2101010:
4496         case DRM_FORMAT_XBGR2101010:
4497         case DRM_FORMAT_YUYV:
4498         case DRM_FORMAT_YVYU:
4499         case DRM_FORMAT_UYVY:
4500         case DRM_FORMAT_VYUY:
4501                 break;
4502         default:
4503                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4504                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4505                 return -EINVAL;
4506         }
4507
4508         return 0;
4509 }
4510
4511 static void skylake_scaler_disable(struct intel_crtc *crtc)
4512 {
4513         int i;
4514
4515         for (i = 0; i < crtc->num_scalers; i++)
4516                 skl_detach_scaler(crtc, i);
4517 }
4518
4519 static void skylake_pfit_enable(struct intel_crtc *crtc)
4520 {
4521         struct drm_device *dev = crtc->base.dev;
4522         struct drm_i915_private *dev_priv = dev->dev_private;
4523         int pipe = crtc->pipe;
4524         struct intel_crtc_scaler_state *scaler_state =
4525                 &crtc->config->scaler_state;
4526
4527         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4528
4529         if (crtc->config->pch_pfit.enabled) {
4530                 int id;
4531
4532                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4533                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4534                         return;
4535                 }
4536
4537                 id = scaler_state->scaler_id;
4538                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4539                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4540                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4541                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4542
4543                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4544         }
4545 }
4546
4547 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4548 {
4549         struct drm_device *dev = crtc->base.dev;
4550         struct drm_i915_private *dev_priv = dev->dev_private;
4551         int pipe = crtc->pipe;
4552
4553         if (crtc->config->pch_pfit.enabled) {
4554                 /* Force use of hard-coded filter coefficients
4555                  * as some pre-programmed values are broken,
4556                  * e.g. x201.
4557                  */
4558                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4559                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4560                                                  PF_PIPE_SEL_IVB(pipe));
4561                 else
4562                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4563                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4564                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4565         }
4566 }
4567
4568 void hsw_enable_ips(struct intel_crtc *crtc)
4569 {
4570         struct drm_device *dev = crtc->base.dev;
4571         struct drm_i915_private *dev_priv = dev->dev_private;
4572
4573         if (!crtc->config->ips_enabled)
4574                 return;
4575
4576         /* We can only enable IPS after we enable a plane and wait for a vblank */
4577         intel_wait_for_vblank(dev, crtc->pipe);
4578
4579         assert_plane_enabled(dev_priv, crtc->plane);
4580         if (IS_BROADWELL(dev)) {
4581                 mutex_lock(&dev_priv->rps.hw_lock);
4582                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4583                 mutex_unlock(&dev_priv->rps.hw_lock);
4584                 /* Quoting Art Runyan: "its not safe to expect any particular
4585                  * value in IPS_CTL bit 31 after enabling IPS through the
4586                  * mailbox." Moreover, the mailbox may return a bogus state,
4587                  * so we need to just enable it and continue on.
4588                  */
4589         } else {
4590                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4591                 /* The bit only becomes 1 in the next vblank, so this wait here
4592                  * is essentially intel_wait_for_vblank. If we don't have this
4593                  * and don't wait for vblanks until the end of crtc_enable, then
4594                  * the HW state readout code will complain that the expected
4595                  * IPS_CTL value is not the one we read. */
4596                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4597                         DRM_ERROR("Timed out waiting for IPS enable\n");
4598         }
4599 }
4600
4601 void hsw_disable_ips(struct intel_crtc *crtc)
4602 {
4603         struct drm_device *dev = crtc->base.dev;
4604         struct drm_i915_private *dev_priv = dev->dev_private;
4605
4606         if (!crtc->config->ips_enabled)
4607                 return;
4608
4609         assert_plane_enabled(dev_priv, crtc->plane);
4610         if (IS_BROADWELL(dev)) {
4611                 mutex_lock(&dev_priv->rps.hw_lock);
4612                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4613                 mutex_unlock(&dev_priv->rps.hw_lock);
4614                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4615                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4616                         DRM_ERROR("Timed out waiting for IPS disable\n");
4617         } else {
4618                 I915_WRITE(IPS_CTL, 0);
4619                 POSTING_READ(IPS_CTL);
4620         }
4621
4622         /* We need to wait for a vblank before we can disable the plane. */
4623         intel_wait_for_vblank(dev, crtc->pipe);
4624 }
4625
4626 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4627 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4628 {
4629         struct drm_device *dev = crtc->dev;
4630         struct drm_i915_private *dev_priv = dev->dev_private;
4631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4632         enum pipe pipe = intel_crtc->pipe;
4633         int i;
4634         bool reenable_ips = false;
4635
4636         /* The clocks have to be on to load the palette. */
4637         if (!crtc->state->active)
4638                 return;
4639
4640         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4641                 if (intel_crtc->config->has_dsi_encoder)
4642                         assert_dsi_pll_enabled(dev_priv);
4643                 else
4644                         assert_pll_enabled(dev_priv, pipe);
4645         }
4646
4647         /* Workaround : Do not read or write the pipe palette/gamma data while
4648          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4649          */
4650         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4651             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4652              GAMMA_MODE_MODE_SPLIT)) {
4653                 hsw_disable_ips(intel_crtc);
4654                 reenable_ips = true;
4655         }
4656
4657         for (i = 0; i < 256; i++) {
4658                 i915_reg_t palreg;
4659
4660                 if (HAS_GMCH_DISPLAY(dev))
4661                         palreg = PALETTE(pipe, i);
4662                 else
4663                         palreg = LGC_PALETTE(pipe, i);
4664
4665                 I915_WRITE(palreg,
4666                            (intel_crtc->lut_r[i] << 16) |
4667                            (intel_crtc->lut_g[i] << 8) |
4668                            intel_crtc->lut_b[i]);
4669         }
4670
4671         if (reenable_ips)
4672                 hsw_enable_ips(intel_crtc);
4673 }
4674
4675 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4676 {
4677         if (intel_crtc->overlay) {
4678                 struct drm_device *dev = intel_crtc->base.dev;
4679                 struct drm_i915_private *dev_priv = dev->dev_private;
4680
4681                 mutex_lock(&dev->struct_mutex);
4682                 dev_priv->mm.interruptible = false;
4683                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4684                 dev_priv->mm.interruptible = true;
4685                 mutex_unlock(&dev->struct_mutex);
4686         }
4687
4688         /* Let userspace switch the overlay on again. In most cases userspace
4689          * has to recompute where to put it anyway.
4690          */
4691 }
4692
4693 /**
4694  * intel_post_enable_primary - Perform operations after enabling primary plane
4695  * @crtc: the CRTC whose primary plane was just enabled
4696  *
4697  * Performs potentially sleeping operations that must be done after the primary
4698  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4699  * called due to an explicit primary plane update, or due to an implicit
4700  * re-enable that is caused when a sprite plane is updated to no longer
4701  * completely hide the primary plane.
4702  */
4703 static void
4704 intel_post_enable_primary(struct drm_crtc *crtc)
4705 {
4706         struct drm_device *dev = crtc->dev;
4707         struct drm_i915_private *dev_priv = dev->dev_private;
4708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709         int pipe = intel_crtc->pipe;
4710
4711         /*
4712          * BDW signals flip done immediately if the plane
4713          * is disabled, even if the plane enable is already
4714          * armed to occur at the next vblank :(
4715          */
4716         if (IS_BROADWELL(dev))
4717                 intel_wait_for_vblank(dev, pipe);
4718
4719         /*
4720          * FIXME IPS should be fine as long as one plane is
4721          * enabled, but in practice it seems to have problems
4722          * when going from primary only to sprite only and vice
4723          * versa.
4724          */
4725         hsw_enable_ips(intel_crtc);
4726
4727         /*
4728          * Gen2 reports pipe underruns whenever all planes are disabled.
4729          * So don't enable underrun reporting before at least some planes
4730          * are enabled.
4731          * FIXME: Need to fix the logic to work when we turn off all planes
4732          * but leave the pipe running.
4733          */
4734         if (IS_GEN2(dev))
4735                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4736
4737         /* Underruns don't always raise interrupts, so check manually. */
4738         intel_check_cpu_fifo_underruns(dev_priv);
4739         intel_check_pch_fifo_underruns(dev_priv);
4740 }
4741
4742 /**
4743  * intel_pre_disable_primary - Perform operations before disabling primary plane
4744  * @crtc: the CRTC whose primary plane is to be disabled
4745  *
4746  * Performs potentially sleeping operations that must be done before the
4747  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4748  * be called due to an explicit primary plane update, or due to an implicit
4749  * disable that is caused when a sprite plane completely hides the primary
4750  * plane.
4751  */
4752 static void
4753 intel_pre_disable_primary(struct drm_crtc *crtc)
4754 {
4755         struct drm_device *dev = crtc->dev;
4756         struct drm_i915_private *dev_priv = dev->dev_private;
4757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4758         int pipe = intel_crtc->pipe;
4759
4760         /*
4761          * Gen2 reports pipe underruns whenever all planes are disabled.
4762          * So diasble underrun reporting before all the planes get disabled.
4763          * FIXME: Need to fix the logic to work when we turn off all planes
4764          * but leave the pipe running.
4765          */
4766         if (IS_GEN2(dev))
4767                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4768
4769         /*
4770          * Vblank time updates from the shadow to live plane control register
4771          * are blocked if the memory self-refresh mode is active at that
4772          * moment. So to make sure the plane gets truly disabled, disable
4773          * first the self-refresh mode. The self-refresh enable bit in turn
4774          * will be checked/applied by the HW only at the next frame start
4775          * event which is after the vblank start event, so we need to have a
4776          * wait-for-vblank between disabling the plane and the pipe.
4777          */
4778         if (HAS_GMCH_DISPLAY(dev)) {
4779                 intel_set_memory_cxsr(dev_priv, false);
4780                 dev_priv->wm.vlv.cxsr = false;
4781                 intel_wait_for_vblank(dev, pipe);
4782         }
4783
4784         /*
4785          * FIXME IPS should be fine as long as one plane is
4786          * enabled, but in practice it seems to have problems
4787          * when going from primary only to sprite only and vice
4788          * versa.
4789          */
4790         hsw_disable_ips(intel_crtc);
4791 }
4792
4793 static void intel_post_plane_update(struct intel_crtc *crtc)
4794 {
4795         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4796         struct drm_device *dev = crtc->base.dev;
4797
4798         if (atomic->wait_vblank)
4799                 intel_wait_for_vblank(dev, crtc->pipe);
4800
4801         intel_frontbuffer_flip(dev, atomic->fb_bits);
4802
4803         if (atomic->disable_cxsr)
4804                 crtc->wm.cxsr_allowed = true;
4805
4806         if (crtc->atomic.update_wm_post)
4807                 intel_update_watermarks(&crtc->base);
4808
4809         if (atomic->update_fbc)
4810                 intel_fbc_update(crtc);
4811
4812         if (atomic->post_enable_primary)
4813                 intel_post_enable_primary(&crtc->base);
4814
4815         memset(atomic, 0, sizeof(*atomic));
4816 }
4817
4818 static void intel_pre_plane_update(struct intel_crtc *crtc)
4819 {
4820         struct drm_device *dev = crtc->base.dev;
4821         struct drm_i915_private *dev_priv = dev->dev_private;
4822         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4823
4824         if (atomic->disable_fbc)
4825                 intel_fbc_deactivate(crtc);
4826
4827         if (crtc->atomic.disable_ips)
4828                 hsw_disable_ips(crtc);
4829
4830         if (atomic->pre_disable_primary)
4831                 intel_pre_disable_primary(&crtc->base);
4832
4833         if (atomic->disable_cxsr) {
4834                 crtc->wm.cxsr_allowed = false;
4835                 intel_set_memory_cxsr(dev_priv, false);
4836         }
4837 }
4838
4839 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4840 {
4841         struct drm_device *dev = crtc->dev;
4842         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4843         struct drm_plane *p;
4844         int pipe = intel_crtc->pipe;
4845
4846         intel_crtc_dpms_overlay_disable(intel_crtc);
4847
4848         drm_for_each_plane_mask(p, dev, plane_mask)
4849                 to_intel_plane(p)->disable_plane(p, crtc);
4850
4851         /*
4852          * FIXME: Once we grow proper nuclear flip support out of this we need
4853          * to compute the mask of flip planes precisely. For the time being
4854          * consider this a flip to a NULL plane.
4855          */
4856         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4857 }
4858
4859 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4860 {
4861         struct drm_device *dev = crtc->dev;
4862         struct drm_i915_private *dev_priv = dev->dev_private;
4863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4864         struct intel_encoder *encoder;
4865         int pipe = intel_crtc->pipe;
4866
4867         if (WARN_ON(intel_crtc->active))
4868                 return;
4869
4870         if (intel_crtc->config->has_pch_encoder)
4871                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4872
4873         if (intel_crtc->config->has_pch_encoder)
4874                 intel_prepare_shared_dpll(intel_crtc);
4875
4876         if (intel_crtc->config->has_dp_encoder)
4877                 intel_dp_set_m_n(intel_crtc, M1_N1);
4878
4879         intel_set_pipe_timings(intel_crtc);
4880
4881         if (intel_crtc->config->has_pch_encoder) {
4882                 intel_cpu_transcoder_set_m_n(intel_crtc,
4883                                      &intel_crtc->config->fdi_m_n, NULL);
4884         }
4885
4886         ironlake_set_pipeconf(crtc);
4887
4888         intel_crtc->active = true;
4889
4890         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4891
4892         for_each_encoder_on_crtc(dev, crtc, encoder)
4893                 if (encoder->pre_enable)
4894                         encoder->pre_enable(encoder);
4895
4896         if (intel_crtc->config->has_pch_encoder) {
4897                 /* Note: FDI PLL enabling _must_ be done before we enable the
4898                  * cpu pipes, hence this is separate from all the other fdi/pch
4899                  * enabling. */
4900                 ironlake_fdi_pll_enable(intel_crtc);
4901         } else {
4902                 assert_fdi_tx_disabled(dev_priv, pipe);
4903                 assert_fdi_rx_disabled(dev_priv, pipe);
4904         }
4905
4906         ironlake_pfit_enable(intel_crtc);
4907
4908         /*
4909          * On ILK+ LUT must be loaded before the pipe is running but with
4910          * clocks enabled
4911          */
4912         intel_crtc_load_lut(crtc);
4913
4914         intel_update_watermarks(crtc);
4915         intel_enable_pipe(intel_crtc);
4916
4917         if (intel_crtc->config->has_pch_encoder)
4918                 ironlake_pch_enable(crtc);
4919
4920         assert_vblank_disabled(crtc);
4921         drm_crtc_vblank_on(crtc);
4922
4923         for_each_encoder_on_crtc(dev, crtc, encoder)
4924                 encoder->enable(encoder);
4925
4926         if (HAS_PCH_CPT(dev))
4927                 cpt_verify_modeset(dev, intel_crtc->pipe);
4928
4929         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4930         if (intel_crtc->config->has_pch_encoder)
4931                 intel_wait_for_vblank(dev, pipe);
4932         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4933
4934         intel_fbc_enable(intel_crtc);
4935 }
4936
4937 /* IPS only exists on ULT machines and is tied to pipe A. */
4938 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4939 {
4940         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4941 }
4942
4943 static void haswell_crtc_enable(struct drm_crtc *crtc)
4944 {
4945         struct drm_device *dev = crtc->dev;
4946         struct drm_i915_private *dev_priv = dev->dev_private;
4947         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4948         struct intel_encoder *encoder;
4949         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4950         struct intel_crtc_state *pipe_config =
4951                 to_intel_crtc_state(crtc->state);
4952
4953         if (WARN_ON(intel_crtc->active))
4954                 return;
4955
4956         if (intel_crtc->config->has_pch_encoder)
4957                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4958                                                       false);
4959
4960         if (intel_crtc_to_shared_dpll(intel_crtc))
4961                 intel_enable_shared_dpll(intel_crtc);
4962
4963         if (intel_crtc->config->has_dp_encoder)
4964                 intel_dp_set_m_n(intel_crtc, M1_N1);
4965
4966         intel_set_pipe_timings(intel_crtc);
4967
4968         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4969                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4970                            intel_crtc->config->pixel_multiplier - 1);
4971         }
4972
4973         if (intel_crtc->config->has_pch_encoder) {
4974                 intel_cpu_transcoder_set_m_n(intel_crtc,
4975                                      &intel_crtc->config->fdi_m_n, NULL);
4976         }
4977
4978         haswell_set_pipeconf(crtc);
4979
4980         intel_set_pipe_csc(crtc);
4981
4982         intel_crtc->active = true;
4983
4984         if (intel_crtc->config->has_pch_encoder)
4985                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4986         else
4987                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4988
4989         for_each_encoder_on_crtc(dev, crtc, encoder) {
4990                 if (encoder->pre_enable)
4991                         encoder->pre_enable(encoder);
4992         }
4993
4994         if (intel_crtc->config->has_pch_encoder)
4995                 dev_priv->display.fdi_link_train(crtc);
4996
4997         if (!intel_crtc->config->has_dsi_encoder)
4998                 intel_ddi_enable_pipe_clock(intel_crtc);
4999
5000         if (INTEL_INFO(dev)->gen >= 9)
5001                 skylake_pfit_enable(intel_crtc);
5002         else
5003                 ironlake_pfit_enable(intel_crtc);
5004
5005         /*
5006          * On ILK+ LUT must be loaded before the pipe is running but with
5007          * clocks enabled
5008          */
5009         intel_crtc_load_lut(crtc);
5010
5011         intel_ddi_set_pipe_settings(crtc);
5012         if (!intel_crtc->config->has_dsi_encoder)
5013                 intel_ddi_enable_transcoder_func(crtc);
5014
5015         intel_update_watermarks(crtc);
5016         intel_enable_pipe(intel_crtc);
5017
5018         if (intel_crtc->config->has_pch_encoder)
5019                 lpt_pch_enable(crtc);
5020
5021         if (intel_crtc->config->dp_encoder_is_mst)
5022                 intel_ddi_set_vc_payload_alloc(crtc, true);
5023
5024         assert_vblank_disabled(crtc);
5025         drm_crtc_vblank_on(crtc);
5026
5027         for_each_encoder_on_crtc(dev, crtc, encoder) {
5028                 encoder->enable(encoder);
5029                 intel_opregion_notify_encoder(encoder, true);
5030         }
5031
5032         if (intel_crtc->config->has_pch_encoder) {
5033                 intel_wait_for_vblank(dev, pipe);
5034                 intel_wait_for_vblank(dev, pipe);
5035                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5036                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5037                                                       true);
5038         }
5039
5040         /* If we change the relative order between pipe/planes enabling, we need
5041          * to change the workaround. */
5042         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5043         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5044                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5045                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5046         }
5047
5048         intel_fbc_enable(intel_crtc);
5049 }
5050
5051 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5052 {
5053         struct drm_device *dev = crtc->base.dev;
5054         struct drm_i915_private *dev_priv = dev->dev_private;
5055         int pipe = crtc->pipe;
5056
5057         /* To avoid upsetting the power well on haswell only disable the pfit if
5058          * it's in use. The hw state code will make sure we get this right. */
5059         if (force || crtc->config->pch_pfit.enabled) {
5060                 I915_WRITE(PF_CTL(pipe), 0);
5061                 I915_WRITE(PF_WIN_POS(pipe), 0);
5062                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5063         }
5064 }
5065
5066 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5067 {
5068         struct drm_device *dev = crtc->dev;
5069         struct drm_i915_private *dev_priv = dev->dev_private;
5070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5071         struct intel_encoder *encoder;
5072         int pipe = intel_crtc->pipe;
5073
5074         if (intel_crtc->config->has_pch_encoder)
5075                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5076
5077         for_each_encoder_on_crtc(dev, crtc, encoder)
5078                 encoder->disable(encoder);
5079
5080         drm_crtc_vblank_off(crtc);
5081         assert_vblank_disabled(crtc);
5082
5083         /*
5084          * Sometimes spurious CPU pipe underruns happen when the
5085          * pipe is already disabled, but FDI RX/TX is still enabled.
5086          * Happens at least with VGA+HDMI cloning. Suppress them.
5087          */
5088         if (intel_crtc->config->has_pch_encoder)
5089                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5090
5091         intel_disable_pipe(intel_crtc);
5092
5093         ironlake_pfit_disable(intel_crtc, false);
5094
5095         if (intel_crtc->config->has_pch_encoder) {
5096                 ironlake_fdi_disable(crtc);
5097                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5098         }
5099
5100         for_each_encoder_on_crtc(dev, crtc, encoder)
5101                 if (encoder->post_disable)
5102                         encoder->post_disable(encoder);
5103
5104         if (intel_crtc->config->has_pch_encoder) {
5105                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5106
5107                 if (HAS_PCH_CPT(dev)) {
5108                         i915_reg_t reg;
5109                         u32 temp;
5110
5111                         /* disable TRANS_DP_CTL */
5112                         reg = TRANS_DP_CTL(pipe);
5113                         temp = I915_READ(reg);
5114                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5115                                   TRANS_DP_PORT_SEL_MASK);
5116                         temp |= TRANS_DP_PORT_SEL_NONE;
5117                         I915_WRITE(reg, temp);
5118
5119                         /* disable DPLL_SEL */
5120                         temp = I915_READ(PCH_DPLL_SEL);
5121                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5122                         I915_WRITE(PCH_DPLL_SEL, temp);
5123                 }
5124
5125                 ironlake_fdi_pll_disable(intel_crtc);
5126         }
5127
5128         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5129
5130         intel_fbc_disable_crtc(intel_crtc);
5131 }
5132
5133 static void haswell_crtc_disable(struct drm_crtc *crtc)
5134 {
5135         struct drm_device *dev = crtc->dev;
5136         struct drm_i915_private *dev_priv = dev->dev_private;
5137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5138         struct intel_encoder *encoder;
5139         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5140
5141         if (intel_crtc->config->has_pch_encoder)
5142                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5143                                                       false);
5144
5145         for_each_encoder_on_crtc(dev, crtc, encoder) {
5146                 intel_opregion_notify_encoder(encoder, false);
5147                 encoder->disable(encoder);
5148         }
5149
5150         drm_crtc_vblank_off(crtc);
5151         assert_vblank_disabled(crtc);
5152
5153         intel_disable_pipe(intel_crtc);
5154
5155         if (intel_crtc->config->dp_encoder_is_mst)
5156                 intel_ddi_set_vc_payload_alloc(crtc, false);
5157
5158         if (!intel_crtc->config->has_dsi_encoder)
5159                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5160
5161         if (INTEL_INFO(dev)->gen >= 9)
5162                 skylake_scaler_disable(intel_crtc);
5163         else
5164                 ironlake_pfit_disable(intel_crtc, false);
5165
5166         if (!intel_crtc->config->has_dsi_encoder)
5167                 intel_ddi_disable_pipe_clock(intel_crtc);
5168
5169         if (intel_crtc->config->has_pch_encoder) {
5170                 lpt_disable_pch_transcoder(dev_priv);
5171                 intel_ddi_fdi_disable(crtc);
5172         }
5173
5174         for_each_encoder_on_crtc(dev, crtc, encoder)
5175                 if (encoder->post_disable)
5176                         encoder->post_disable(encoder);
5177
5178         if (intel_crtc->config->has_pch_encoder)
5179                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5180                                                       true);
5181
5182         intel_fbc_disable_crtc(intel_crtc);
5183 }
5184
5185 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5186 {
5187         struct drm_device *dev = crtc->base.dev;
5188         struct drm_i915_private *dev_priv = dev->dev_private;
5189         struct intel_crtc_state *pipe_config = crtc->config;
5190
5191         if (!pipe_config->gmch_pfit.control)
5192                 return;
5193
5194         /*
5195          * The panel fitter should only be adjusted whilst the pipe is disabled,
5196          * according to register description and PRM.
5197          */
5198         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5199         assert_pipe_disabled(dev_priv, crtc->pipe);
5200
5201         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5202         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5203
5204         /* Border color in case we don't scale up to the full screen. Black by
5205          * default, change to something else for debugging. */
5206         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5207 }
5208
5209 static enum intel_display_power_domain port_to_power_domain(enum port port)
5210 {
5211         switch (port) {
5212         case PORT_A:
5213                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5214         case PORT_B:
5215                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5216         case PORT_C:
5217                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5218         case PORT_D:
5219                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5220         case PORT_E:
5221                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5222         default:
5223                 MISSING_CASE(port);
5224                 return POWER_DOMAIN_PORT_OTHER;
5225         }
5226 }
5227
5228 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5229 {
5230         switch (port) {
5231         case PORT_A:
5232                 return POWER_DOMAIN_AUX_A;
5233         case PORT_B:
5234                 return POWER_DOMAIN_AUX_B;
5235         case PORT_C:
5236                 return POWER_DOMAIN_AUX_C;
5237         case PORT_D:
5238                 return POWER_DOMAIN_AUX_D;
5239         case PORT_E:
5240                 /* FIXME: Check VBT for actual wiring of PORT E */
5241                 return POWER_DOMAIN_AUX_D;
5242         default:
5243                 MISSING_CASE(port);
5244                 return POWER_DOMAIN_AUX_A;
5245         }
5246 }
5247
5248 enum intel_display_power_domain
5249 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5250 {
5251         struct drm_device *dev = intel_encoder->base.dev;
5252         struct intel_digital_port *intel_dig_port;
5253
5254         switch (intel_encoder->type) {
5255         case INTEL_OUTPUT_UNKNOWN:
5256                 /* Only DDI platforms should ever use this output type */
5257                 WARN_ON_ONCE(!HAS_DDI(dev));
5258         case INTEL_OUTPUT_DISPLAYPORT:
5259         case INTEL_OUTPUT_HDMI:
5260         case INTEL_OUTPUT_EDP:
5261                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5262                 return port_to_power_domain(intel_dig_port->port);
5263         case INTEL_OUTPUT_DP_MST:
5264                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5265                 return port_to_power_domain(intel_dig_port->port);
5266         case INTEL_OUTPUT_ANALOG:
5267                 return POWER_DOMAIN_PORT_CRT;
5268         case INTEL_OUTPUT_DSI:
5269                 return POWER_DOMAIN_PORT_DSI;
5270         default:
5271                 return POWER_DOMAIN_PORT_OTHER;
5272         }
5273 }
5274
5275 enum intel_display_power_domain
5276 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5277 {
5278         struct drm_device *dev = intel_encoder->base.dev;
5279         struct intel_digital_port *intel_dig_port;
5280
5281         switch (intel_encoder->type) {
5282         case INTEL_OUTPUT_UNKNOWN:
5283         case INTEL_OUTPUT_HDMI:
5284                 /*
5285                  * Only DDI platforms should ever use these output types.
5286                  * We can get here after the HDMI detect code has already set
5287                  * the type of the shared encoder. Since we can't be sure
5288                  * what's the status of the given connectors, play safe and
5289                  * run the DP detection too.
5290                  */
5291                 WARN_ON_ONCE(!HAS_DDI(dev));
5292         case INTEL_OUTPUT_DISPLAYPORT:
5293         case INTEL_OUTPUT_EDP:
5294                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5295                 return port_to_aux_power_domain(intel_dig_port->port);
5296         case INTEL_OUTPUT_DP_MST:
5297                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5298                 return port_to_aux_power_domain(intel_dig_port->port);
5299         default:
5300                 MISSING_CASE(intel_encoder->type);
5301                 return POWER_DOMAIN_AUX_A;
5302         }
5303 }
5304
5305 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5306 {
5307         struct drm_device *dev = crtc->dev;
5308         struct intel_encoder *intel_encoder;
5309         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5310         enum pipe pipe = intel_crtc->pipe;
5311         unsigned long mask;
5312         enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5313
5314         if (!crtc->state->active)
5315                 return 0;
5316
5317         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5318         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5319         if (intel_crtc->config->pch_pfit.enabled ||
5320             intel_crtc->config->pch_pfit.force_thru)
5321                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5322
5323         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5324                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5325
5326         return mask;
5327 }
5328
5329 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5330 {
5331         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5333         enum intel_display_power_domain domain;
5334         unsigned long domains, new_domains, old_domains;
5335
5336         old_domains = intel_crtc->enabled_power_domains;
5337         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5338
5339         domains = new_domains & ~old_domains;
5340
5341         for_each_power_domain(domain, domains)
5342                 intel_display_power_get(dev_priv, domain);
5343
5344         return old_domains & ~new_domains;
5345 }
5346
5347 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5348                                       unsigned long domains)
5349 {
5350         enum intel_display_power_domain domain;
5351
5352         for_each_power_domain(domain, domains)
5353                 intel_display_power_put(dev_priv, domain);
5354 }
5355
5356 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5357 {
5358         struct drm_device *dev = state->dev;
5359         struct drm_i915_private *dev_priv = dev->dev_private;
5360         unsigned long put_domains[I915_MAX_PIPES] = {};
5361         struct drm_crtc_state *crtc_state;
5362         struct drm_crtc *crtc;
5363         int i;
5364
5365         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5366                 if (needs_modeset(crtc->state))
5367                         put_domains[to_intel_crtc(crtc)->pipe] =
5368                                 modeset_get_crtc_power_domains(crtc);
5369         }
5370
5371         if (dev_priv->display.modeset_commit_cdclk) {
5372                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5373
5374                 if (cdclk != dev_priv->cdclk_freq &&
5375                     !WARN_ON(!state->allow_modeset))
5376                         dev_priv->display.modeset_commit_cdclk(state);
5377         }
5378
5379         for (i = 0; i < I915_MAX_PIPES; i++)
5380                 if (put_domains[i])
5381                         modeset_put_power_domains(dev_priv, put_domains[i]);
5382 }
5383
5384 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5385 {
5386         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5387
5388         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5389             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5390                 return max_cdclk_freq;
5391         else if (IS_CHERRYVIEW(dev_priv))
5392                 return max_cdclk_freq*95/100;
5393         else if (INTEL_INFO(dev_priv)->gen < 4)
5394                 return 2*max_cdclk_freq*90/100;
5395         else
5396                 return max_cdclk_freq*90/100;
5397 }
5398
5399 static void intel_update_max_cdclk(struct drm_device *dev)
5400 {
5401         struct drm_i915_private *dev_priv = dev->dev_private;
5402
5403         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5404                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5405
5406                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5407                         dev_priv->max_cdclk_freq = 675000;
5408                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5409                         dev_priv->max_cdclk_freq = 540000;
5410                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5411                         dev_priv->max_cdclk_freq = 450000;
5412                 else
5413                         dev_priv->max_cdclk_freq = 337500;
5414         } else if (IS_BROADWELL(dev))  {
5415                 /*
5416                  * FIXME with extra cooling we can allow
5417                  * 540 MHz for ULX and 675 Mhz for ULT.
5418                  * How can we know if extra cooling is
5419                  * available? PCI ID, VTB, something else?
5420                  */
5421                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5422                         dev_priv->max_cdclk_freq = 450000;
5423                 else if (IS_BDW_ULX(dev))
5424                         dev_priv->max_cdclk_freq = 450000;
5425                 else if (IS_BDW_ULT(dev))
5426                         dev_priv->max_cdclk_freq = 540000;
5427                 else
5428                         dev_priv->max_cdclk_freq = 675000;
5429         } else if (IS_CHERRYVIEW(dev)) {
5430                 dev_priv->max_cdclk_freq = 320000;
5431         } else if (IS_VALLEYVIEW(dev)) {
5432                 dev_priv->max_cdclk_freq = 400000;
5433         } else {
5434                 /* otherwise assume cdclk is fixed */
5435                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5436         }
5437
5438         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5439
5440         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5441                          dev_priv->max_cdclk_freq);
5442
5443         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5444                          dev_priv->max_dotclk_freq);
5445 }
5446
5447 static void intel_update_cdclk(struct drm_device *dev)
5448 {
5449         struct drm_i915_private *dev_priv = dev->dev_private;
5450
5451         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5452         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5453                          dev_priv->cdclk_freq);
5454
5455         /*
5456          * Program the gmbus_freq based on the cdclk frequency.
5457          * BSpec erroneously claims we should aim for 4MHz, but
5458          * in fact 1MHz is the correct frequency.
5459          */
5460         if (IS_VALLEYVIEW(dev)) {
5461                 /*
5462                  * Program the gmbus_freq based on the cdclk frequency.
5463                  * BSpec erroneously claims we should aim for 4MHz, but
5464                  * in fact 1MHz is the correct frequency.
5465                  */
5466                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5467         }
5468
5469         if (dev_priv->max_cdclk_freq == 0)
5470                 intel_update_max_cdclk(dev);
5471 }
5472
5473 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5474 {
5475         struct drm_i915_private *dev_priv = dev->dev_private;
5476         uint32_t divider;
5477         uint32_t ratio;
5478         uint32_t current_freq;
5479         int ret;
5480
5481         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5482         switch (frequency) {
5483         case 144000:
5484                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5485                 ratio = BXT_DE_PLL_RATIO(60);
5486                 break;
5487         case 288000:
5488                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5489                 ratio = BXT_DE_PLL_RATIO(60);
5490                 break;
5491         case 384000:
5492                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5493                 ratio = BXT_DE_PLL_RATIO(60);
5494                 break;
5495         case 576000:
5496                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5497                 ratio = BXT_DE_PLL_RATIO(60);
5498                 break;
5499         case 624000:
5500                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5501                 ratio = BXT_DE_PLL_RATIO(65);
5502                 break;
5503         case 19200:
5504                 /*
5505                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5506                  * to suppress GCC warning.
5507                  */
5508                 ratio = 0;
5509                 divider = 0;
5510                 break;
5511         default:
5512                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5513
5514                 return;
5515         }
5516
5517         mutex_lock(&dev_priv->rps.hw_lock);
5518         /* Inform power controller of upcoming frequency change */
5519         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5520                                       0x80000000);
5521         mutex_unlock(&dev_priv->rps.hw_lock);
5522
5523         if (ret) {
5524                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5525                           ret, frequency);
5526                 return;
5527         }
5528
5529         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5530         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5531         current_freq = current_freq * 500 + 1000;
5532
5533         /*
5534          * DE PLL has to be disabled when
5535          * - setting to 19.2MHz (bypass, PLL isn't used)
5536          * - before setting to 624MHz (PLL needs toggling)
5537          * - before setting to any frequency from 624MHz (PLL needs toggling)
5538          */
5539         if (frequency == 19200 || frequency == 624000 ||
5540             current_freq == 624000) {
5541                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5542                 /* Timeout 200us */
5543                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5544                              1))
5545                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5546         }
5547
5548         if (frequency != 19200) {
5549                 uint32_t val;
5550
5551                 val = I915_READ(BXT_DE_PLL_CTL);
5552                 val &= ~BXT_DE_PLL_RATIO_MASK;
5553                 val |= ratio;
5554                 I915_WRITE(BXT_DE_PLL_CTL, val);
5555
5556                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5557                 /* Timeout 200us */
5558                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5559                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5560
5561                 val = I915_READ(CDCLK_CTL);
5562                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5563                 val |= divider;
5564                 /*
5565                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5566                  * enable otherwise.
5567                  */
5568                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5569                 if (frequency >= 500000)
5570                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5571
5572                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5573                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5574                 val |= (frequency - 1000) / 500;
5575                 I915_WRITE(CDCLK_CTL, val);
5576         }
5577
5578         mutex_lock(&dev_priv->rps.hw_lock);
5579         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5580                                       DIV_ROUND_UP(frequency, 25000));
5581         mutex_unlock(&dev_priv->rps.hw_lock);
5582
5583         if (ret) {
5584                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5585                           ret, frequency);
5586                 return;
5587         }
5588
5589         intel_update_cdclk(dev);
5590 }
5591
5592 void broxton_init_cdclk(struct drm_device *dev)
5593 {
5594         struct drm_i915_private *dev_priv = dev->dev_private;
5595         uint32_t val;
5596
5597         /*
5598          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5599          * or else the reset will hang because there is no PCH to respond.
5600          * Move the handshake programming to initialization sequence.
5601          * Previously was left up to BIOS.
5602          */
5603         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5604         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5605         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5606
5607         /* Enable PG1 for cdclk */
5608         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5609
5610         /* check if cd clock is enabled */
5611         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5612                 DRM_DEBUG_KMS("Display already initialized\n");
5613                 return;
5614         }
5615
5616         /*
5617          * FIXME:
5618          * - The initial CDCLK needs to be read from VBT.
5619          *   Need to make this change after VBT has changes for BXT.
5620          * - check if setting the max (or any) cdclk freq is really necessary
5621          *   here, it belongs to modeset time
5622          */
5623         broxton_set_cdclk(dev, 624000);
5624
5625         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5626         POSTING_READ(DBUF_CTL);
5627
5628         udelay(10);
5629
5630         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5631                 DRM_ERROR("DBuf power enable timeout!\n");
5632 }
5633
5634 void broxton_uninit_cdclk(struct drm_device *dev)
5635 {
5636         struct drm_i915_private *dev_priv = dev->dev_private;
5637
5638         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5639         POSTING_READ(DBUF_CTL);
5640
5641         udelay(10);
5642
5643         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5644                 DRM_ERROR("DBuf power disable timeout!\n");
5645
5646         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5647         broxton_set_cdclk(dev, 19200);
5648
5649         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5650 }
5651
5652 static const struct skl_cdclk_entry {
5653         unsigned int freq;
5654         unsigned int vco;
5655 } skl_cdclk_frequencies[] = {
5656         { .freq = 308570, .vco = 8640 },
5657         { .freq = 337500, .vco = 8100 },
5658         { .freq = 432000, .vco = 8640 },
5659         { .freq = 450000, .vco = 8100 },
5660         { .freq = 540000, .vco = 8100 },
5661         { .freq = 617140, .vco = 8640 },
5662         { .freq = 675000, .vco = 8100 },
5663 };
5664
5665 static unsigned int skl_cdclk_decimal(unsigned int freq)
5666 {
5667         return (freq - 1000) / 500;
5668 }
5669
5670 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5671 {
5672         unsigned int i;
5673
5674         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5675                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5676
5677                 if (e->freq == freq)
5678                         return e->vco;
5679         }
5680
5681         return 8100;
5682 }
5683
5684 static void
5685 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5686 {
5687         unsigned int min_freq;
5688         u32 val;
5689
5690         /* select the minimum CDCLK before enabling DPLL 0 */
5691         val = I915_READ(CDCLK_CTL);
5692         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5693         val |= CDCLK_FREQ_337_308;
5694
5695         if (required_vco == 8640)
5696                 min_freq = 308570;
5697         else
5698                 min_freq = 337500;
5699
5700         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5701
5702         I915_WRITE(CDCLK_CTL, val);
5703         POSTING_READ(CDCLK_CTL);
5704
5705         /*
5706          * We always enable DPLL0 with the lowest link rate possible, but still
5707          * taking into account the VCO required to operate the eDP panel at the
5708          * desired frequency. The usual DP link rates operate with a VCO of
5709          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5710          * The modeset code is responsible for the selection of the exact link
5711          * rate later on, with the constraint of choosing a frequency that
5712          * works with required_vco.
5713          */
5714         val = I915_READ(DPLL_CTRL1);
5715
5716         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5717                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5718         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5719         if (required_vco == 8640)
5720                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5721                                             SKL_DPLL0);
5722         else
5723                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5724                                             SKL_DPLL0);
5725
5726         I915_WRITE(DPLL_CTRL1, val);
5727         POSTING_READ(DPLL_CTRL1);
5728
5729         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5730
5731         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5732                 DRM_ERROR("DPLL0 not locked\n");
5733 }
5734
5735 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5736 {
5737         int ret;
5738         u32 val;
5739
5740         /* inform PCU we want to change CDCLK */
5741         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5742         mutex_lock(&dev_priv->rps.hw_lock);
5743         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5744         mutex_unlock(&dev_priv->rps.hw_lock);
5745
5746         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5747 }
5748
5749 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5750 {
5751         unsigned int i;
5752
5753         for (i = 0; i < 15; i++) {
5754                 if (skl_cdclk_pcu_ready(dev_priv))
5755                         return true;
5756                 udelay(10);
5757         }
5758
5759         return false;
5760 }
5761
5762 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5763 {
5764         struct drm_device *dev = dev_priv->dev;
5765         u32 freq_select, pcu_ack;
5766
5767         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5768
5769         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5770                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5771                 return;
5772         }
5773
5774         /* set CDCLK_CTL */
5775         switch(freq) {
5776         case 450000:
5777         case 432000:
5778                 freq_select = CDCLK_FREQ_450_432;
5779                 pcu_ack = 1;
5780                 break;
5781         case 540000:
5782                 freq_select = CDCLK_FREQ_540;
5783                 pcu_ack = 2;
5784                 break;
5785         case 308570:
5786         case 337500:
5787         default:
5788                 freq_select = CDCLK_FREQ_337_308;
5789                 pcu_ack = 0;
5790                 break;
5791         case 617140:
5792         case 675000:
5793                 freq_select = CDCLK_FREQ_675_617;
5794                 pcu_ack = 3;
5795                 break;
5796         }
5797
5798         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5799         POSTING_READ(CDCLK_CTL);
5800
5801         /* inform PCU of the change */
5802         mutex_lock(&dev_priv->rps.hw_lock);
5803         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5804         mutex_unlock(&dev_priv->rps.hw_lock);
5805
5806         intel_update_cdclk(dev);
5807 }
5808
5809 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5810 {
5811         /* disable DBUF power */
5812         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5813         POSTING_READ(DBUF_CTL);
5814
5815         udelay(10);
5816
5817         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5818                 DRM_ERROR("DBuf power disable timeout\n");
5819
5820         /* disable DPLL0 */
5821         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5822         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5823                 DRM_ERROR("Couldn't disable DPLL0\n");
5824 }
5825
5826 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5827 {
5828         unsigned int required_vco;
5829
5830         /* DPLL0 not enabled (happens on early BIOS versions) */
5831         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5832                 /* enable DPLL0 */
5833                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5834                 skl_dpll0_enable(dev_priv, required_vco);
5835         }
5836
5837         /* set CDCLK to the frequency the BIOS chose */
5838         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5839
5840         /* enable DBUF power */
5841         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5842         POSTING_READ(DBUF_CTL);
5843
5844         udelay(10);
5845
5846         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5847                 DRM_ERROR("DBuf power enable timeout\n");
5848 }
5849
5850 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5851 {
5852         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5853         uint32_t cdctl = I915_READ(CDCLK_CTL);
5854         int freq = dev_priv->skl_boot_cdclk;
5855
5856         /*
5857          * check if the pre-os intialized the display
5858          * There is SWF18 scratchpad register defined which is set by the
5859          * pre-os which can be used by the OS drivers to check the status
5860          */
5861         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5862                 goto sanitize;
5863
5864         /* Is PLL enabled and locked ? */
5865         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5866                 goto sanitize;
5867
5868         /* DPLL okay; verify the cdclock
5869          *
5870          * Noticed in some instances that the freq selection is correct but
5871          * decimal part is programmed wrong from BIOS where pre-os does not
5872          * enable display. Verify the same as well.
5873          */
5874         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5875                 /* All well; nothing to sanitize */
5876                 return false;
5877 sanitize:
5878         /*
5879          * As of now initialize with max cdclk till
5880          * we get dynamic cdclk support
5881          * */
5882         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5883         skl_init_cdclk(dev_priv);
5884
5885         /* we did have to sanitize */
5886         return true;
5887 }
5888
5889 /* Adjust CDclk dividers to allow high res or save power if possible */
5890 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5891 {
5892         struct drm_i915_private *dev_priv = dev->dev_private;
5893         u32 val, cmd;
5894
5895         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5896                                         != dev_priv->cdclk_freq);
5897
5898         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5899                 cmd = 2;
5900         else if (cdclk == 266667)
5901                 cmd = 1;
5902         else
5903                 cmd = 0;
5904
5905         mutex_lock(&dev_priv->rps.hw_lock);
5906         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5907         val &= ~DSPFREQGUAR_MASK;
5908         val |= (cmd << DSPFREQGUAR_SHIFT);
5909         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5910         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5911                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5912                      50)) {
5913                 DRM_ERROR("timed out waiting for CDclk change\n");
5914         }
5915         mutex_unlock(&dev_priv->rps.hw_lock);
5916
5917         mutex_lock(&dev_priv->sb_lock);
5918
5919         if (cdclk == 400000) {
5920                 u32 divider;
5921
5922                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5923
5924                 /* adjust cdclk divider */
5925                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5926                 val &= ~CCK_FREQUENCY_VALUES;
5927                 val |= divider;
5928                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5929
5930                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5931                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5932                              50))
5933                         DRM_ERROR("timed out waiting for CDclk change\n");
5934         }
5935
5936         /* adjust self-refresh exit latency value */
5937         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5938         val &= ~0x7f;
5939
5940         /*
5941          * For high bandwidth configs, we set a higher latency in the bunit
5942          * so that the core display fetch happens in time to avoid underruns.
5943          */
5944         if (cdclk == 400000)
5945                 val |= 4500 / 250; /* 4.5 usec */
5946         else
5947                 val |= 3000 / 250; /* 3.0 usec */
5948         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5949
5950         mutex_unlock(&dev_priv->sb_lock);
5951
5952         intel_update_cdclk(dev);
5953 }
5954
5955 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5956 {
5957         struct drm_i915_private *dev_priv = dev->dev_private;
5958         u32 val, cmd;
5959
5960         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5961                                                 != dev_priv->cdclk_freq);
5962
5963         switch (cdclk) {
5964         case 333333:
5965         case 320000:
5966         case 266667:
5967         case 200000:
5968                 break;
5969         default:
5970                 MISSING_CASE(cdclk);
5971                 return;
5972         }
5973
5974         /*
5975          * Specs are full of misinformation, but testing on actual
5976          * hardware has shown that we just need to write the desired
5977          * CCK divider into the Punit register.
5978          */
5979         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5980
5981         mutex_lock(&dev_priv->rps.hw_lock);
5982         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5983         val &= ~DSPFREQGUAR_MASK_CHV;
5984         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5985         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5986         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5987                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5988                      50)) {
5989                 DRM_ERROR("timed out waiting for CDclk change\n");
5990         }
5991         mutex_unlock(&dev_priv->rps.hw_lock);
5992
5993         intel_update_cdclk(dev);
5994 }
5995
5996 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5997                                  int max_pixclk)
5998 {
5999         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6000         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6001
6002         /*
6003          * Really only a few cases to deal with, as only 4 CDclks are supported:
6004          *   200MHz
6005          *   267MHz
6006          *   320/333MHz (depends on HPLL freq)
6007          *   400MHz (VLV only)
6008          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6009          * of the lower bin and adjust if needed.
6010          *
6011          * We seem to get an unstable or solid color picture at 200MHz.
6012          * Not sure what's wrong. For now use 200MHz only when all pipes
6013          * are off.
6014          */
6015         if (!IS_CHERRYVIEW(dev_priv) &&
6016             max_pixclk > freq_320*limit/100)
6017                 return 400000;
6018         else if (max_pixclk > 266667*limit/100)
6019                 return freq_320;
6020         else if (max_pixclk > 0)
6021                 return 266667;
6022         else
6023                 return 200000;
6024 }
6025
6026 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6027                               int max_pixclk)
6028 {
6029         /*
6030          * FIXME:
6031          * - remove the guardband, it's not needed on BXT
6032          * - set 19.2MHz bypass frequency if there are no active pipes
6033          */
6034         if (max_pixclk > 576000*9/10)
6035                 return 624000;
6036         else if (max_pixclk > 384000*9/10)
6037                 return 576000;
6038         else if (max_pixclk > 288000*9/10)
6039                 return 384000;
6040         else if (max_pixclk > 144000*9/10)
6041                 return 288000;
6042         else
6043                 return 144000;
6044 }
6045
6046 /* Compute the max pixel clock for new configuration. Uses atomic state if
6047  * that's non-NULL, look at current state otherwise. */
6048 static int intel_mode_max_pixclk(struct drm_device *dev,
6049                                  struct drm_atomic_state *state)
6050 {
6051         struct intel_crtc *intel_crtc;
6052         struct intel_crtc_state *crtc_state;
6053         int max_pixclk = 0;
6054
6055         for_each_intel_crtc(dev, intel_crtc) {
6056                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6057                 if (IS_ERR(crtc_state))
6058                         return PTR_ERR(crtc_state);
6059
6060                 if (!crtc_state->base.enable)
6061                         continue;
6062
6063                 max_pixclk = max(max_pixclk,
6064                                  crtc_state->base.adjusted_mode.crtc_clock);
6065         }
6066
6067         return max_pixclk;
6068 }
6069
6070 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6071 {
6072         struct drm_device *dev = state->dev;
6073         struct drm_i915_private *dev_priv = dev->dev_private;
6074         int max_pixclk = intel_mode_max_pixclk(dev, state);
6075
6076         if (max_pixclk < 0)
6077                 return max_pixclk;
6078
6079         to_intel_atomic_state(state)->cdclk =
6080                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6081
6082         return 0;
6083 }
6084
6085 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6086 {
6087         struct drm_device *dev = state->dev;
6088         struct drm_i915_private *dev_priv = dev->dev_private;
6089         int max_pixclk = intel_mode_max_pixclk(dev, state);
6090
6091         if (max_pixclk < 0)
6092                 return max_pixclk;
6093
6094         to_intel_atomic_state(state)->cdclk =
6095                 broxton_calc_cdclk(dev_priv, max_pixclk);
6096
6097         return 0;
6098 }
6099
6100 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6101 {
6102         unsigned int credits, default_credits;
6103
6104         if (IS_CHERRYVIEW(dev_priv))
6105                 default_credits = PFI_CREDIT(12);
6106         else
6107                 default_credits = PFI_CREDIT(8);
6108
6109         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6110                 /* CHV suggested value is 31 or 63 */
6111                 if (IS_CHERRYVIEW(dev_priv))
6112                         credits = PFI_CREDIT_63;
6113                 else
6114                         credits = PFI_CREDIT(15);
6115         } else {
6116                 credits = default_credits;
6117         }
6118
6119         /*
6120          * WA - write default credits before re-programming
6121          * FIXME: should we also set the resend bit here?
6122          */
6123         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6124                    default_credits);
6125
6126         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6127                    credits | PFI_CREDIT_RESEND);
6128
6129         /*
6130          * FIXME is this guaranteed to clear
6131          * immediately or should we poll for it?
6132          */
6133         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6134 }
6135
6136 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6137 {
6138         struct drm_device *dev = old_state->dev;
6139         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6140         struct drm_i915_private *dev_priv = dev->dev_private;
6141
6142         /*
6143          * FIXME: We can end up here with all power domains off, yet
6144          * with a CDCLK frequency other than the minimum. To account
6145          * for this take the PIPE-A power domain, which covers the HW
6146          * blocks needed for the following programming. This can be
6147          * removed once it's guaranteed that we get here either with
6148          * the minimum CDCLK set, or the required power domains
6149          * enabled.
6150          */
6151         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6152
6153         if (IS_CHERRYVIEW(dev))
6154                 cherryview_set_cdclk(dev, req_cdclk);
6155         else
6156                 valleyview_set_cdclk(dev, req_cdclk);
6157
6158         vlv_program_pfi_credits(dev_priv);
6159
6160         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6161 }
6162
6163 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6164 {
6165         struct drm_device *dev = crtc->dev;
6166         struct drm_i915_private *dev_priv = to_i915(dev);
6167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6168         struct intel_encoder *encoder;
6169         int pipe = intel_crtc->pipe;
6170
6171         if (WARN_ON(intel_crtc->active))
6172                 return;
6173
6174         if (intel_crtc->config->has_dp_encoder)
6175                 intel_dp_set_m_n(intel_crtc, M1_N1);
6176
6177         intel_set_pipe_timings(intel_crtc);
6178
6179         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6180                 struct drm_i915_private *dev_priv = dev->dev_private;
6181
6182                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6183                 I915_WRITE(CHV_CANVAS(pipe), 0);
6184         }
6185
6186         i9xx_set_pipeconf(intel_crtc);
6187
6188         intel_crtc->active = true;
6189
6190         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6191
6192         for_each_encoder_on_crtc(dev, crtc, encoder)
6193                 if (encoder->pre_pll_enable)
6194                         encoder->pre_pll_enable(encoder);
6195
6196         if (!intel_crtc->config->has_dsi_encoder) {
6197                 if (IS_CHERRYVIEW(dev)) {
6198                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6199                         chv_enable_pll(intel_crtc, intel_crtc->config);
6200                 } else {
6201                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6202                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6203                 }
6204         }
6205
6206         for_each_encoder_on_crtc(dev, crtc, encoder)
6207                 if (encoder->pre_enable)
6208                         encoder->pre_enable(encoder);
6209
6210         i9xx_pfit_enable(intel_crtc);
6211
6212         intel_crtc_load_lut(crtc);
6213
6214         intel_enable_pipe(intel_crtc);
6215
6216         assert_vblank_disabled(crtc);
6217         drm_crtc_vblank_on(crtc);
6218
6219         for_each_encoder_on_crtc(dev, crtc, encoder)
6220                 encoder->enable(encoder);
6221 }
6222
6223 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6224 {
6225         struct drm_device *dev = crtc->base.dev;
6226         struct drm_i915_private *dev_priv = dev->dev_private;
6227
6228         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6229         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6230 }
6231
6232 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6233 {
6234         struct drm_device *dev = crtc->dev;
6235         struct drm_i915_private *dev_priv = to_i915(dev);
6236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6237         struct intel_encoder *encoder;
6238         int pipe = intel_crtc->pipe;
6239
6240         if (WARN_ON(intel_crtc->active))
6241                 return;
6242
6243         i9xx_set_pll_dividers(intel_crtc);
6244
6245         if (intel_crtc->config->has_dp_encoder)
6246                 intel_dp_set_m_n(intel_crtc, M1_N1);
6247
6248         intel_set_pipe_timings(intel_crtc);
6249
6250         i9xx_set_pipeconf(intel_crtc);
6251
6252         intel_crtc->active = true;
6253
6254         if (!IS_GEN2(dev))
6255                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6256
6257         for_each_encoder_on_crtc(dev, crtc, encoder)
6258                 if (encoder->pre_enable)
6259                         encoder->pre_enable(encoder);
6260
6261         i9xx_enable_pll(intel_crtc);
6262
6263         i9xx_pfit_enable(intel_crtc);
6264
6265         intel_crtc_load_lut(crtc);
6266
6267         intel_update_watermarks(crtc);
6268         intel_enable_pipe(intel_crtc);
6269
6270         assert_vblank_disabled(crtc);
6271         drm_crtc_vblank_on(crtc);
6272
6273         for_each_encoder_on_crtc(dev, crtc, encoder)
6274                 encoder->enable(encoder);
6275
6276         intel_fbc_enable(intel_crtc);
6277 }
6278
6279 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6280 {
6281         struct drm_device *dev = crtc->base.dev;
6282         struct drm_i915_private *dev_priv = dev->dev_private;
6283
6284         if (!crtc->config->gmch_pfit.control)
6285                 return;
6286
6287         assert_pipe_disabled(dev_priv, crtc->pipe);
6288
6289         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6290                          I915_READ(PFIT_CONTROL));
6291         I915_WRITE(PFIT_CONTROL, 0);
6292 }
6293
6294 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6295 {
6296         struct drm_device *dev = crtc->dev;
6297         struct drm_i915_private *dev_priv = dev->dev_private;
6298         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6299         struct intel_encoder *encoder;
6300         int pipe = intel_crtc->pipe;
6301
6302         /*
6303          * On gen2 planes are double buffered but the pipe isn't, so we must
6304          * wait for planes to fully turn off before disabling the pipe.
6305          * We also need to wait on all gmch platforms because of the
6306          * self-refresh mode constraint explained above.
6307          */
6308         intel_wait_for_vblank(dev, pipe);
6309
6310         for_each_encoder_on_crtc(dev, crtc, encoder)
6311                 encoder->disable(encoder);
6312
6313         drm_crtc_vblank_off(crtc);
6314         assert_vblank_disabled(crtc);
6315
6316         intel_disable_pipe(intel_crtc);
6317
6318         i9xx_pfit_disable(intel_crtc);
6319
6320         for_each_encoder_on_crtc(dev, crtc, encoder)
6321                 if (encoder->post_disable)
6322                         encoder->post_disable(encoder);
6323
6324         if (!intel_crtc->config->has_dsi_encoder) {
6325                 if (IS_CHERRYVIEW(dev))
6326                         chv_disable_pll(dev_priv, pipe);
6327                 else if (IS_VALLEYVIEW(dev))
6328                         vlv_disable_pll(dev_priv, pipe);
6329                 else
6330                         i9xx_disable_pll(intel_crtc);
6331         }
6332
6333         for_each_encoder_on_crtc(dev, crtc, encoder)
6334                 if (encoder->post_pll_disable)
6335                         encoder->post_pll_disable(encoder);
6336
6337         if (!IS_GEN2(dev))
6338                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6339
6340         intel_fbc_disable_crtc(intel_crtc);
6341 }
6342
6343 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6344 {
6345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6346         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6347         enum intel_display_power_domain domain;
6348         unsigned long domains;
6349
6350         if (!intel_crtc->active)
6351                 return;
6352
6353         if (to_intel_plane_state(crtc->primary->state)->visible) {
6354                 WARN_ON(intel_crtc->unpin_work);
6355
6356                 intel_pre_disable_primary(crtc);
6357         }
6358
6359         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6360         dev_priv->display.crtc_disable(crtc);
6361         intel_crtc->active = false;
6362         intel_update_watermarks(crtc);
6363         intel_disable_shared_dpll(intel_crtc);
6364
6365         domains = intel_crtc->enabled_power_domains;
6366         for_each_power_domain(domain, domains)
6367                 intel_display_power_put(dev_priv, domain);
6368         intel_crtc->enabled_power_domains = 0;
6369 }
6370
6371 /*
6372  * turn all crtc's off, but do not adjust state
6373  * This has to be paired with a call to intel_modeset_setup_hw_state.
6374  */
6375 int intel_display_suspend(struct drm_device *dev)
6376 {
6377         struct drm_mode_config *config = &dev->mode_config;
6378         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6379         struct drm_atomic_state *state;
6380         struct drm_crtc *crtc;
6381         unsigned crtc_mask = 0;
6382         int ret = 0;
6383
6384         if (WARN_ON(!ctx))
6385                 return 0;
6386
6387         lockdep_assert_held(&ctx->ww_ctx);
6388         state = drm_atomic_state_alloc(dev);
6389         if (WARN_ON(!state))
6390                 return -ENOMEM;
6391
6392         state->acquire_ctx = ctx;
6393         state->allow_modeset = true;
6394
6395         for_each_crtc(dev, crtc) {
6396                 struct drm_crtc_state *crtc_state =
6397                         drm_atomic_get_crtc_state(state, crtc);
6398
6399                 ret = PTR_ERR_OR_ZERO(crtc_state);
6400                 if (ret)
6401                         goto free;
6402
6403                 if (!crtc_state->active)
6404                         continue;
6405
6406                 crtc_state->active = false;
6407                 crtc_mask |= 1 << drm_crtc_index(crtc);
6408         }
6409
6410         if (crtc_mask) {
6411                 ret = drm_atomic_commit(state);
6412
6413                 if (!ret) {
6414                         for_each_crtc(dev, crtc)
6415                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6416                                         crtc->state->active = true;
6417
6418                         return ret;
6419                 }
6420         }
6421
6422 free:
6423         if (ret)
6424                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6425         drm_atomic_state_free(state);
6426         return ret;
6427 }
6428
6429 void intel_encoder_destroy(struct drm_encoder *encoder)
6430 {
6431         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6432
6433         drm_encoder_cleanup(encoder);
6434         kfree(intel_encoder);
6435 }
6436
6437 /* Cross check the actual hw state with our own modeset state tracking (and it's
6438  * internal consistency). */
6439 static void intel_connector_check_state(struct intel_connector *connector)
6440 {
6441         struct drm_crtc *crtc = connector->base.state->crtc;
6442
6443         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6444                       connector->base.base.id,
6445                       connector->base.name);
6446
6447         if (connector->get_hw_state(connector)) {
6448                 struct intel_encoder *encoder = connector->encoder;
6449                 struct drm_connector_state *conn_state = connector->base.state;
6450
6451                 I915_STATE_WARN(!crtc,
6452                          "connector enabled without attached crtc\n");
6453
6454                 if (!crtc)
6455                         return;
6456
6457                 I915_STATE_WARN(!crtc->state->active,
6458                       "connector is active, but attached crtc isn't\n");
6459
6460                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6461                         return;
6462
6463                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6464                         "atomic encoder doesn't match attached encoder\n");
6465
6466                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6467                         "attached encoder crtc differs from connector crtc\n");
6468         } else {
6469                 I915_STATE_WARN(crtc && crtc->state->active,
6470                         "attached crtc is active, but connector isn't\n");
6471                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6472                         "best encoder set without crtc!\n");
6473         }
6474 }
6475
6476 int intel_connector_init(struct intel_connector *connector)
6477 {
6478         drm_atomic_helper_connector_reset(&connector->base);
6479
6480         if (!connector->base.state)
6481                 return -ENOMEM;
6482
6483         return 0;
6484 }
6485
6486 struct intel_connector *intel_connector_alloc(void)
6487 {
6488         struct intel_connector *connector;
6489
6490         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6491         if (!connector)
6492                 return NULL;
6493
6494         if (intel_connector_init(connector) < 0) {
6495                 kfree(connector);
6496                 return NULL;
6497         }
6498
6499         return connector;
6500 }
6501
6502 /* Simple connector->get_hw_state implementation for encoders that support only
6503  * one connector and no cloning and hence the encoder state determines the state
6504  * of the connector. */
6505 bool intel_connector_get_hw_state(struct intel_connector *connector)
6506 {
6507         enum pipe pipe = 0;
6508         struct intel_encoder *encoder = connector->encoder;
6509
6510         return encoder->get_hw_state(encoder, &pipe);
6511 }
6512
6513 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6514 {
6515         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6516                 return crtc_state->fdi_lanes;
6517
6518         return 0;
6519 }
6520
6521 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6522                                      struct intel_crtc_state *pipe_config)
6523 {
6524         struct drm_atomic_state *state = pipe_config->base.state;
6525         struct intel_crtc *other_crtc;
6526         struct intel_crtc_state *other_crtc_state;
6527
6528         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6529                       pipe_name(pipe), pipe_config->fdi_lanes);
6530         if (pipe_config->fdi_lanes > 4) {
6531                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6532                               pipe_name(pipe), pipe_config->fdi_lanes);
6533                 return -EINVAL;
6534         }
6535
6536         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6537                 if (pipe_config->fdi_lanes > 2) {
6538                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6539                                       pipe_config->fdi_lanes);
6540                         return -EINVAL;
6541                 } else {
6542                         return 0;
6543                 }
6544         }
6545
6546         if (INTEL_INFO(dev)->num_pipes == 2)
6547                 return 0;
6548
6549         /* Ivybridge 3 pipe is really complicated */
6550         switch (pipe) {
6551         case PIPE_A:
6552                 return 0;
6553         case PIPE_B:
6554                 if (pipe_config->fdi_lanes <= 2)
6555                         return 0;
6556
6557                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6558                 other_crtc_state =
6559                         intel_atomic_get_crtc_state(state, other_crtc);
6560                 if (IS_ERR(other_crtc_state))
6561                         return PTR_ERR(other_crtc_state);
6562
6563                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6564                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6565                                       pipe_name(pipe), pipe_config->fdi_lanes);
6566                         return -EINVAL;
6567                 }
6568                 return 0;
6569         case PIPE_C:
6570                 if (pipe_config->fdi_lanes > 2) {
6571                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6572                                       pipe_name(pipe), pipe_config->fdi_lanes);
6573                         return -EINVAL;
6574                 }
6575
6576                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6577                 other_crtc_state =
6578                         intel_atomic_get_crtc_state(state, other_crtc);
6579                 if (IS_ERR(other_crtc_state))
6580                         return PTR_ERR(other_crtc_state);
6581
6582                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6583                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6584                         return -EINVAL;
6585                 }
6586                 return 0;
6587         default:
6588                 BUG();
6589         }
6590 }
6591
6592 #define RETRY 1
6593 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6594                                        struct intel_crtc_state *pipe_config)
6595 {
6596         struct drm_device *dev = intel_crtc->base.dev;
6597         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6598         int lane, link_bw, fdi_dotclock, ret;
6599         bool needs_recompute = false;
6600
6601 retry:
6602         /* FDI is a binary signal running at ~2.7GHz, encoding
6603          * each output octet as 10 bits. The actual frequency
6604          * is stored as a divider into a 100MHz clock, and the
6605          * mode pixel clock is stored in units of 1KHz.
6606          * Hence the bw of each lane in terms of the mode signal
6607          * is:
6608          */
6609         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6610
6611         fdi_dotclock = adjusted_mode->crtc_clock;
6612
6613         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6614                                            pipe_config->pipe_bpp);
6615
6616         pipe_config->fdi_lanes = lane;
6617
6618         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6619                                link_bw, &pipe_config->fdi_m_n);
6620
6621         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6622                                        intel_crtc->pipe, pipe_config);
6623         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6624                 pipe_config->pipe_bpp -= 2*3;
6625                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6626                               pipe_config->pipe_bpp);
6627                 needs_recompute = true;
6628                 pipe_config->bw_constrained = true;
6629
6630                 goto retry;
6631         }
6632
6633         if (needs_recompute)
6634                 return RETRY;
6635
6636         return ret;
6637 }
6638
6639 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6640                                      struct intel_crtc_state *pipe_config)
6641 {
6642         if (pipe_config->pipe_bpp > 24)
6643                 return false;
6644
6645         /* HSW can handle pixel rate up to cdclk? */
6646         if (IS_HASWELL(dev_priv->dev))
6647                 return true;
6648
6649         /*
6650          * We compare against max which means we must take
6651          * the increased cdclk requirement into account when
6652          * calculating the new cdclk.
6653          *
6654          * Should measure whether using a lower cdclk w/o IPS
6655          */
6656         return ilk_pipe_pixel_rate(pipe_config) <=
6657                 dev_priv->max_cdclk_freq * 95 / 100;
6658 }
6659
6660 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6661                                    struct intel_crtc_state *pipe_config)
6662 {
6663         struct drm_device *dev = crtc->base.dev;
6664         struct drm_i915_private *dev_priv = dev->dev_private;
6665
6666         pipe_config->ips_enabled = i915.enable_ips &&
6667                 hsw_crtc_supports_ips(crtc) &&
6668                 pipe_config_supports_ips(dev_priv, pipe_config);
6669 }
6670
6671 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6672 {
6673         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6674
6675         /* GDG double wide on either pipe, otherwise pipe A only */
6676         return INTEL_INFO(dev_priv)->gen < 4 &&
6677                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6678 }
6679
6680 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6681                                      struct intel_crtc_state *pipe_config)
6682 {
6683         struct drm_device *dev = crtc->base.dev;
6684         struct drm_i915_private *dev_priv = dev->dev_private;
6685         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6686
6687         /* FIXME should check pixel clock limits on all platforms */
6688         if (INTEL_INFO(dev)->gen < 4) {
6689                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6690
6691                 /*
6692                  * Enable double wide mode when the dot clock
6693                  * is > 90% of the (display) core speed.
6694                  */
6695                 if (intel_crtc_supports_double_wide(crtc) &&
6696                     adjusted_mode->crtc_clock > clock_limit) {
6697                         clock_limit *= 2;
6698                         pipe_config->double_wide = true;
6699                 }
6700
6701                 if (adjusted_mode->crtc_clock > clock_limit) {
6702                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6703                                       adjusted_mode->crtc_clock, clock_limit,
6704                                       yesno(pipe_config->double_wide));
6705                         return -EINVAL;
6706                 }
6707         }
6708
6709         /*
6710          * Pipe horizontal size must be even in:
6711          * - DVO ganged mode
6712          * - LVDS dual channel mode
6713          * - Double wide pipe
6714          */
6715         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6716              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6717                 pipe_config->pipe_src_w &= ~1;
6718
6719         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6720          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6721          */
6722         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6723                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6724                 return -EINVAL;
6725
6726         if (HAS_IPS(dev))
6727                 hsw_compute_ips_config(crtc, pipe_config);
6728
6729         if (pipe_config->has_pch_encoder)
6730                 return ironlake_fdi_compute_config(crtc, pipe_config);
6731
6732         return 0;
6733 }
6734
6735 static int skylake_get_display_clock_speed(struct drm_device *dev)
6736 {
6737         struct drm_i915_private *dev_priv = to_i915(dev);
6738         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6739         uint32_t cdctl = I915_READ(CDCLK_CTL);
6740         uint32_t linkrate;
6741
6742         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6743                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6744
6745         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6746                 return 540000;
6747
6748         linkrate = (I915_READ(DPLL_CTRL1) &
6749                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6750
6751         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6752             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6753                 /* vco 8640 */
6754                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6755                 case CDCLK_FREQ_450_432:
6756                         return 432000;
6757                 case CDCLK_FREQ_337_308:
6758                         return 308570;
6759                 case CDCLK_FREQ_675_617:
6760                         return 617140;
6761                 default:
6762                         WARN(1, "Unknown cd freq selection\n");
6763                 }
6764         } else {
6765                 /* vco 8100 */
6766                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6767                 case CDCLK_FREQ_450_432:
6768                         return 450000;
6769                 case CDCLK_FREQ_337_308:
6770                         return 337500;
6771                 case CDCLK_FREQ_675_617:
6772                         return 675000;
6773                 default:
6774                         WARN(1, "Unknown cd freq selection\n");
6775                 }
6776         }
6777
6778         /* error case, do as if DPLL0 isn't enabled */
6779         return 24000;
6780 }
6781
6782 static int broxton_get_display_clock_speed(struct drm_device *dev)
6783 {
6784         struct drm_i915_private *dev_priv = to_i915(dev);
6785         uint32_t cdctl = I915_READ(CDCLK_CTL);
6786         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6787         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6788         int cdclk;
6789
6790         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6791                 return 19200;
6792
6793         cdclk = 19200 * pll_ratio / 2;
6794
6795         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6796         case BXT_CDCLK_CD2X_DIV_SEL_1:
6797                 return cdclk;  /* 576MHz or 624MHz */
6798         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6799                 return cdclk * 2 / 3; /* 384MHz */
6800         case BXT_CDCLK_CD2X_DIV_SEL_2:
6801                 return cdclk / 2; /* 288MHz */
6802         case BXT_CDCLK_CD2X_DIV_SEL_4:
6803                 return cdclk / 4; /* 144MHz */
6804         }
6805
6806         /* error case, do as if DE PLL isn't enabled */
6807         return 19200;
6808 }
6809
6810 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6811 {
6812         struct drm_i915_private *dev_priv = dev->dev_private;
6813         uint32_t lcpll = I915_READ(LCPLL_CTL);
6814         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6815
6816         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6817                 return 800000;
6818         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6819                 return 450000;
6820         else if (freq == LCPLL_CLK_FREQ_450)
6821                 return 450000;
6822         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6823                 return 540000;
6824         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6825                 return 337500;
6826         else
6827                 return 675000;
6828 }
6829
6830 static int haswell_get_display_clock_speed(struct drm_device *dev)
6831 {
6832         struct drm_i915_private *dev_priv = dev->dev_private;
6833         uint32_t lcpll = I915_READ(LCPLL_CTL);
6834         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6835
6836         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6837                 return 800000;
6838         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6839                 return 450000;
6840         else if (freq == LCPLL_CLK_FREQ_450)
6841                 return 450000;
6842         else if (IS_HSW_ULT(dev))
6843                 return 337500;
6844         else
6845                 return 540000;
6846 }
6847
6848 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6849 {
6850         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6851                                       CCK_DISPLAY_CLOCK_CONTROL);
6852 }
6853
6854 static int ilk_get_display_clock_speed(struct drm_device *dev)
6855 {
6856         return 450000;
6857 }
6858
6859 static int i945_get_display_clock_speed(struct drm_device *dev)
6860 {
6861         return 400000;
6862 }
6863
6864 static int i915_get_display_clock_speed(struct drm_device *dev)
6865 {
6866         return 333333;
6867 }
6868
6869 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6870 {
6871         return 200000;
6872 }
6873
6874 static int pnv_get_display_clock_speed(struct drm_device *dev)
6875 {
6876         u16 gcfgc = 0;
6877
6878         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6879
6880         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6881         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6882                 return 266667;
6883         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6884                 return 333333;
6885         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6886                 return 444444;
6887         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6888                 return 200000;
6889         default:
6890                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6891         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6892                 return 133333;
6893         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6894                 return 166667;
6895         }
6896 }
6897
6898 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6899 {
6900         u16 gcfgc = 0;
6901
6902         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6903
6904         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6905                 return 133333;
6906         else {
6907                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6908                 case GC_DISPLAY_CLOCK_333_MHZ:
6909                         return 333333;
6910                 default:
6911                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6912                         return 190000;
6913                 }
6914         }
6915 }
6916
6917 static int i865_get_display_clock_speed(struct drm_device *dev)
6918 {
6919         return 266667;
6920 }
6921
6922 static int i85x_get_display_clock_speed(struct drm_device *dev)
6923 {
6924         u16 hpllcc = 0;
6925
6926         /*
6927          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6928          * encoding is different :(
6929          * FIXME is this the right way to detect 852GM/852GMV?
6930          */
6931         if (dev->pdev->revision == 0x1)
6932                 return 133333;
6933
6934         pci_bus_read_config_word(dev->pdev->bus,
6935                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6936
6937         /* Assume that the hardware is in the high speed state.  This
6938          * should be the default.
6939          */
6940         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6941         case GC_CLOCK_133_200:
6942         case GC_CLOCK_133_200_2:
6943         case GC_CLOCK_100_200:
6944                 return 200000;
6945         case GC_CLOCK_166_250:
6946                 return 250000;
6947         case GC_CLOCK_100_133:
6948                 return 133333;
6949         case GC_CLOCK_133_266:
6950         case GC_CLOCK_133_266_2:
6951         case GC_CLOCK_166_266:
6952                 return 266667;
6953         }
6954
6955         /* Shouldn't happen */
6956         return 0;
6957 }
6958
6959 static int i830_get_display_clock_speed(struct drm_device *dev)
6960 {
6961         return 133333;
6962 }
6963
6964 static unsigned int intel_hpll_vco(struct drm_device *dev)
6965 {
6966         struct drm_i915_private *dev_priv = dev->dev_private;
6967         static const unsigned int blb_vco[8] = {
6968                 [0] = 3200000,
6969                 [1] = 4000000,
6970                 [2] = 5333333,
6971                 [3] = 4800000,
6972                 [4] = 6400000,
6973         };
6974         static const unsigned int pnv_vco[8] = {
6975                 [0] = 3200000,
6976                 [1] = 4000000,
6977                 [2] = 5333333,
6978                 [3] = 4800000,
6979                 [4] = 2666667,
6980         };
6981         static const unsigned int cl_vco[8] = {
6982                 [0] = 3200000,
6983                 [1] = 4000000,
6984                 [2] = 5333333,
6985                 [3] = 6400000,
6986                 [4] = 3333333,
6987                 [5] = 3566667,
6988                 [6] = 4266667,
6989         };
6990         static const unsigned int elk_vco[8] = {
6991                 [0] = 3200000,
6992                 [1] = 4000000,
6993                 [2] = 5333333,
6994                 [3] = 4800000,
6995         };
6996         static const unsigned int ctg_vco[8] = {
6997                 [0] = 3200000,
6998                 [1] = 4000000,
6999                 [2] = 5333333,
7000                 [3] = 6400000,
7001                 [4] = 2666667,
7002                 [5] = 4266667,
7003         };
7004         const unsigned int *vco_table;
7005         unsigned int vco;
7006         uint8_t tmp = 0;
7007
7008         /* FIXME other chipsets? */
7009         if (IS_GM45(dev))
7010                 vco_table = ctg_vco;
7011         else if (IS_G4X(dev))
7012                 vco_table = elk_vco;
7013         else if (IS_CRESTLINE(dev))
7014                 vco_table = cl_vco;
7015         else if (IS_PINEVIEW(dev))
7016                 vco_table = pnv_vco;
7017         else if (IS_G33(dev))
7018                 vco_table = blb_vco;
7019         else
7020                 return 0;
7021
7022         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7023
7024         vco = vco_table[tmp & 0x7];
7025         if (vco == 0)
7026                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7027         else
7028                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7029
7030         return vco;
7031 }
7032
7033 static int gm45_get_display_clock_speed(struct drm_device *dev)
7034 {
7035         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7036         uint16_t tmp = 0;
7037
7038         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7039
7040         cdclk_sel = (tmp >> 12) & 0x1;
7041
7042         switch (vco) {
7043         case 2666667:
7044         case 4000000:
7045         case 5333333:
7046                 return cdclk_sel ? 333333 : 222222;
7047         case 3200000:
7048                 return cdclk_sel ? 320000 : 228571;
7049         default:
7050                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7051                 return 222222;
7052         }
7053 }
7054
7055 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7056 {
7057         static const uint8_t div_3200[] = { 16, 10,  8 };
7058         static const uint8_t div_4000[] = { 20, 12, 10 };
7059         static const uint8_t div_5333[] = { 24, 16, 14 };
7060         const uint8_t *div_table;
7061         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7062         uint16_t tmp = 0;
7063
7064         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7065
7066         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7067
7068         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7069                 goto fail;
7070
7071         switch (vco) {
7072         case 3200000:
7073                 div_table = div_3200;
7074                 break;
7075         case 4000000:
7076                 div_table = div_4000;
7077                 break;
7078         case 5333333:
7079                 div_table = div_5333;
7080                 break;
7081         default:
7082                 goto fail;
7083         }
7084
7085         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7086
7087 fail:
7088         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7089         return 200000;
7090 }
7091
7092 static int g33_get_display_clock_speed(struct drm_device *dev)
7093 {
7094         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7095         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7096         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7097         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7098         const uint8_t *div_table;
7099         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7100         uint16_t tmp = 0;
7101
7102         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7103
7104         cdclk_sel = (tmp >> 4) & 0x7;
7105
7106         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7107                 goto fail;
7108
7109         switch (vco) {
7110         case 3200000:
7111                 div_table = div_3200;
7112                 break;
7113         case 4000000:
7114                 div_table = div_4000;
7115                 break;
7116         case 4800000:
7117                 div_table = div_4800;
7118                 break;
7119         case 5333333:
7120                 div_table = div_5333;
7121                 break;
7122         default:
7123                 goto fail;
7124         }
7125
7126         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7127
7128 fail:
7129         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7130         return 190476;
7131 }
7132
7133 static void
7134 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7135 {
7136         while (*num > DATA_LINK_M_N_MASK ||
7137                *den > DATA_LINK_M_N_MASK) {
7138                 *num >>= 1;
7139                 *den >>= 1;
7140         }
7141 }
7142
7143 static void compute_m_n(unsigned int m, unsigned int n,
7144                         uint32_t *ret_m, uint32_t *ret_n)
7145 {
7146         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7147         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7148         intel_reduce_m_n_ratio(ret_m, ret_n);
7149 }
7150
7151 void
7152 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7153                        int pixel_clock, int link_clock,
7154                        struct intel_link_m_n *m_n)
7155 {
7156         m_n->tu = 64;
7157
7158         compute_m_n(bits_per_pixel * pixel_clock,
7159                     link_clock * nlanes * 8,
7160                     &m_n->gmch_m, &m_n->gmch_n);
7161
7162         compute_m_n(pixel_clock, link_clock,
7163                     &m_n->link_m, &m_n->link_n);
7164 }
7165
7166 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7167 {
7168         if (i915.panel_use_ssc >= 0)
7169                 return i915.panel_use_ssc != 0;
7170         return dev_priv->vbt.lvds_use_ssc
7171                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7172 }
7173
7174 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7175                            int num_connectors)
7176 {
7177         struct drm_device *dev = crtc_state->base.crtc->dev;
7178         struct drm_i915_private *dev_priv = dev->dev_private;
7179         int refclk;
7180
7181         WARN_ON(!crtc_state->base.state);
7182
7183         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7184                 refclk = 100000;
7185         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7186             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7187                 refclk = dev_priv->vbt.lvds_ssc_freq;
7188                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7189         } else if (!IS_GEN2(dev)) {
7190                 refclk = 96000;
7191         } else {
7192                 refclk = 48000;
7193         }
7194
7195         return refclk;
7196 }
7197
7198 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7199 {
7200         return (1 << dpll->n) << 16 | dpll->m2;
7201 }
7202
7203 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7204 {
7205         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7206 }
7207
7208 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7209                                      struct intel_crtc_state *crtc_state,
7210                                      intel_clock_t *reduced_clock)
7211 {
7212         struct drm_device *dev = crtc->base.dev;
7213         u32 fp, fp2 = 0;
7214
7215         if (IS_PINEVIEW(dev)) {
7216                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7217                 if (reduced_clock)
7218                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7219         } else {
7220                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7221                 if (reduced_clock)
7222                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7223         }
7224
7225         crtc_state->dpll_hw_state.fp0 = fp;
7226
7227         crtc->lowfreq_avail = false;
7228         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7229             reduced_clock) {
7230                 crtc_state->dpll_hw_state.fp1 = fp2;
7231                 crtc->lowfreq_avail = true;
7232         } else {
7233                 crtc_state->dpll_hw_state.fp1 = fp;
7234         }
7235 }
7236
7237 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7238                 pipe)
7239 {
7240         u32 reg_val;
7241
7242         /*
7243          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7244          * and set it to a reasonable value instead.
7245          */
7246         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7247         reg_val &= 0xffffff00;
7248         reg_val |= 0x00000030;
7249         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7250
7251         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7252         reg_val &= 0x8cffffff;
7253         reg_val = 0x8c000000;
7254         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7255
7256         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7257         reg_val &= 0xffffff00;
7258         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7259
7260         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7261         reg_val &= 0x00ffffff;
7262         reg_val |= 0xb0000000;
7263         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7264 }
7265
7266 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7267                                          struct intel_link_m_n *m_n)
7268 {
7269         struct drm_device *dev = crtc->base.dev;
7270         struct drm_i915_private *dev_priv = dev->dev_private;
7271         int pipe = crtc->pipe;
7272
7273         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7274         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7275         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7276         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7277 }
7278
7279 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7280                                          struct intel_link_m_n *m_n,
7281                                          struct intel_link_m_n *m2_n2)
7282 {
7283         struct drm_device *dev = crtc->base.dev;
7284         struct drm_i915_private *dev_priv = dev->dev_private;
7285         int pipe = crtc->pipe;
7286         enum transcoder transcoder = crtc->config->cpu_transcoder;
7287
7288         if (INTEL_INFO(dev)->gen >= 5) {
7289                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7290                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7291                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7292                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7293                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7294                  * for gen < 8) and if DRRS is supported (to make sure the
7295                  * registers are not unnecessarily accessed).
7296                  */
7297                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7298                         crtc->config->has_drrs) {
7299                         I915_WRITE(PIPE_DATA_M2(transcoder),
7300                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7301                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7302                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7303                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7304                 }
7305         } else {
7306                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7307                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7308                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7309                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7310         }
7311 }
7312
7313 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7314 {
7315         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7316
7317         if (m_n == M1_N1) {
7318                 dp_m_n = &crtc->config->dp_m_n;
7319                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7320         } else if (m_n == M2_N2) {
7321
7322                 /*
7323                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7324                  * needs to be programmed into M1_N1.
7325                  */
7326                 dp_m_n = &crtc->config->dp_m2_n2;
7327         } else {
7328                 DRM_ERROR("Unsupported divider value\n");
7329                 return;
7330         }
7331
7332         if (crtc->config->has_pch_encoder)
7333                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7334         else
7335                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7336 }
7337
7338 static void vlv_compute_dpll(struct intel_crtc *crtc,
7339                              struct intel_crtc_state *pipe_config)
7340 {
7341         u32 dpll, dpll_md;
7342
7343         /*
7344          * Enable DPIO clock input. We should never disable the reference
7345          * clock for pipe B, since VGA hotplug / manual detection depends
7346          * on it.
7347          */
7348         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7349                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7350         /* We should never disable this, set it here for state tracking */
7351         if (crtc->pipe == PIPE_B)
7352                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7353         dpll |= DPLL_VCO_ENABLE;
7354         pipe_config->dpll_hw_state.dpll = dpll;
7355
7356         dpll_md = (pipe_config->pixel_multiplier - 1)
7357                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7358         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7359 }
7360
7361 static void vlv_prepare_pll(struct intel_crtc *crtc,
7362                             const struct intel_crtc_state *pipe_config)
7363 {
7364         struct drm_device *dev = crtc->base.dev;
7365         struct drm_i915_private *dev_priv = dev->dev_private;
7366         int pipe = crtc->pipe;
7367         u32 mdiv;
7368         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7369         u32 coreclk, reg_val;
7370
7371         mutex_lock(&dev_priv->sb_lock);
7372
7373         bestn = pipe_config->dpll.n;
7374         bestm1 = pipe_config->dpll.m1;
7375         bestm2 = pipe_config->dpll.m2;
7376         bestp1 = pipe_config->dpll.p1;
7377         bestp2 = pipe_config->dpll.p2;
7378
7379         /* See eDP HDMI DPIO driver vbios notes doc */
7380
7381         /* PLL B needs special handling */
7382         if (pipe == PIPE_B)
7383                 vlv_pllb_recal_opamp(dev_priv, pipe);
7384
7385         /* Set up Tx target for periodic Rcomp update */
7386         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7387
7388         /* Disable target IRef on PLL */
7389         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7390         reg_val &= 0x00ffffff;
7391         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7392
7393         /* Disable fast lock */
7394         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7395
7396         /* Set idtafcrecal before PLL is enabled */
7397         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7398         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7399         mdiv |= ((bestn << DPIO_N_SHIFT));
7400         mdiv |= (1 << DPIO_K_SHIFT);
7401
7402         /*
7403          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7404          * but we don't support that).
7405          * Note: don't use the DAC post divider as it seems unstable.
7406          */
7407         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7408         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7409
7410         mdiv |= DPIO_ENABLE_CALIBRATION;
7411         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7412
7413         /* Set HBR and RBR LPF coefficients */
7414         if (pipe_config->port_clock == 162000 ||
7415             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7416             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7417                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7418                                  0x009f0003);
7419         else
7420                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7421                                  0x00d0000f);
7422
7423         if (pipe_config->has_dp_encoder) {
7424                 /* Use SSC source */
7425                 if (pipe == PIPE_A)
7426                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7427                                          0x0df40000);
7428                 else
7429                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7430                                          0x0df70000);
7431         } else { /* HDMI or VGA */
7432                 /* Use bend source */
7433                 if (pipe == PIPE_A)
7434                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7435                                          0x0df70000);
7436                 else
7437                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7438                                          0x0df40000);
7439         }
7440
7441         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7442         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7443         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7444             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7445                 coreclk |= 0x01000000;
7446         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7447
7448         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7449         mutex_unlock(&dev_priv->sb_lock);
7450 }
7451
7452 static void chv_compute_dpll(struct intel_crtc *crtc,
7453                              struct intel_crtc_state *pipe_config)
7454 {
7455         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7456                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7457                 DPLL_VCO_ENABLE;
7458         if (crtc->pipe != PIPE_A)
7459                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7460
7461         pipe_config->dpll_hw_state.dpll_md =
7462                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7463 }
7464
7465 static void chv_prepare_pll(struct intel_crtc *crtc,
7466                             const struct intel_crtc_state *pipe_config)
7467 {
7468         struct drm_device *dev = crtc->base.dev;
7469         struct drm_i915_private *dev_priv = dev->dev_private;
7470         int pipe = crtc->pipe;
7471         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7472         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7473         u32 loopfilter, tribuf_calcntr;
7474         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7475         u32 dpio_val;
7476         int vco;
7477
7478         bestn = pipe_config->dpll.n;
7479         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7480         bestm1 = pipe_config->dpll.m1;
7481         bestm2 = pipe_config->dpll.m2 >> 22;
7482         bestp1 = pipe_config->dpll.p1;
7483         bestp2 = pipe_config->dpll.p2;
7484         vco = pipe_config->dpll.vco;
7485         dpio_val = 0;
7486         loopfilter = 0;
7487
7488         /*
7489          * Enable Refclk and SSC
7490          */
7491         I915_WRITE(dpll_reg,
7492                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7493
7494         mutex_lock(&dev_priv->sb_lock);
7495
7496         /* p1 and p2 divider */
7497         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7498                         5 << DPIO_CHV_S1_DIV_SHIFT |
7499                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7500                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7501                         1 << DPIO_CHV_K_DIV_SHIFT);
7502
7503         /* Feedback post-divider - m2 */
7504         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7505
7506         /* Feedback refclk divider - n and m1 */
7507         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7508                         DPIO_CHV_M1_DIV_BY_2 |
7509                         1 << DPIO_CHV_N_DIV_SHIFT);
7510
7511         /* M2 fraction division */
7512         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7513
7514         /* M2 fraction division enable */
7515         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7516         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7517         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7518         if (bestm2_frac)
7519                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7520         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7521
7522         /* Program digital lock detect threshold */
7523         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7524         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7525                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7526         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7527         if (!bestm2_frac)
7528                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7529         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7530
7531         /* Loop filter */
7532         if (vco == 5400000) {
7533                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7534                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7535                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7536                 tribuf_calcntr = 0x9;
7537         } else if (vco <= 6200000) {
7538                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7539                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7540                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7541                 tribuf_calcntr = 0x9;
7542         } else if (vco <= 6480000) {
7543                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7544                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7545                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7546                 tribuf_calcntr = 0x8;
7547         } else {
7548                 /* Not supported. Apply the same limits as in the max case */
7549                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7550                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7551                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7552                 tribuf_calcntr = 0;
7553         }
7554         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7555
7556         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7557         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7558         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7559         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7560
7561         /* AFC Recal */
7562         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7563                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7564                         DPIO_AFC_RECAL);
7565
7566         mutex_unlock(&dev_priv->sb_lock);
7567 }
7568
7569 /**
7570  * vlv_force_pll_on - forcibly enable just the PLL
7571  * @dev_priv: i915 private structure
7572  * @pipe: pipe PLL to enable
7573  * @dpll: PLL configuration
7574  *
7575  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7576  * in cases where we need the PLL enabled even when @pipe is not going to
7577  * be enabled.
7578  */
7579 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7580                       const struct dpll *dpll)
7581 {
7582         struct intel_crtc *crtc =
7583                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7584         struct intel_crtc_state pipe_config = {
7585                 .base.crtc = &crtc->base,
7586                 .pixel_multiplier = 1,
7587                 .dpll = *dpll,
7588         };
7589
7590         if (IS_CHERRYVIEW(dev)) {
7591                 chv_compute_dpll(crtc, &pipe_config);
7592                 chv_prepare_pll(crtc, &pipe_config);
7593                 chv_enable_pll(crtc, &pipe_config);
7594         } else {
7595                 vlv_compute_dpll(crtc, &pipe_config);
7596                 vlv_prepare_pll(crtc, &pipe_config);
7597                 vlv_enable_pll(crtc, &pipe_config);
7598         }
7599 }
7600
7601 /**
7602  * vlv_force_pll_off - forcibly disable just the PLL
7603  * @dev_priv: i915 private structure
7604  * @pipe: pipe PLL to disable
7605  *
7606  * Disable the PLL for @pipe. To be used in cases where we need
7607  * the PLL enabled even when @pipe is not going to be enabled.
7608  */
7609 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7610 {
7611         if (IS_CHERRYVIEW(dev))
7612                 chv_disable_pll(to_i915(dev), pipe);
7613         else
7614                 vlv_disable_pll(to_i915(dev), pipe);
7615 }
7616
7617 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7618                               struct intel_crtc_state *crtc_state,
7619                               intel_clock_t *reduced_clock,
7620                               int num_connectors)
7621 {
7622         struct drm_device *dev = crtc->base.dev;
7623         struct drm_i915_private *dev_priv = dev->dev_private;
7624         u32 dpll;
7625         bool is_sdvo;
7626         struct dpll *clock = &crtc_state->dpll;
7627
7628         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7629
7630         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7631                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7632
7633         dpll = DPLL_VGA_MODE_DIS;
7634
7635         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7636                 dpll |= DPLLB_MODE_LVDS;
7637         else
7638                 dpll |= DPLLB_MODE_DAC_SERIAL;
7639
7640         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7641                 dpll |= (crtc_state->pixel_multiplier - 1)
7642                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7643         }
7644
7645         if (is_sdvo)
7646                 dpll |= DPLL_SDVO_HIGH_SPEED;
7647
7648         if (crtc_state->has_dp_encoder)
7649                 dpll |= DPLL_SDVO_HIGH_SPEED;
7650
7651         /* compute bitmask from p1 value */
7652         if (IS_PINEVIEW(dev))
7653                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7654         else {
7655                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7656                 if (IS_G4X(dev) && reduced_clock)
7657                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7658         }
7659         switch (clock->p2) {
7660         case 5:
7661                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7662                 break;
7663         case 7:
7664                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7665                 break;
7666         case 10:
7667                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7668                 break;
7669         case 14:
7670                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7671                 break;
7672         }
7673         if (INTEL_INFO(dev)->gen >= 4)
7674                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7675
7676         if (crtc_state->sdvo_tv_clock)
7677                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7678         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7679                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7680                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7681         else
7682                 dpll |= PLL_REF_INPUT_DREFCLK;
7683
7684         dpll |= DPLL_VCO_ENABLE;
7685         crtc_state->dpll_hw_state.dpll = dpll;
7686
7687         if (INTEL_INFO(dev)->gen >= 4) {
7688                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7689                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7690                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7691         }
7692 }
7693
7694 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7695                               struct intel_crtc_state *crtc_state,
7696                               intel_clock_t *reduced_clock,
7697                               int num_connectors)
7698 {
7699         struct drm_device *dev = crtc->base.dev;
7700         struct drm_i915_private *dev_priv = dev->dev_private;
7701         u32 dpll;
7702         struct dpll *clock = &crtc_state->dpll;
7703
7704         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7705
7706         dpll = DPLL_VGA_MODE_DIS;
7707
7708         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7709                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7710         } else {
7711                 if (clock->p1 == 2)
7712                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7713                 else
7714                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7715                 if (clock->p2 == 4)
7716                         dpll |= PLL_P2_DIVIDE_BY_4;
7717         }
7718
7719         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7720                 dpll |= DPLL_DVO_2X_MODE;
7721
7722         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7723                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7724                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7725         else
7726                 dpll |= PLL_REF_INPUT_DREFCLK;
7727
7728         dpll |= DPLL_VCO_ENABLE;
7729         crtc_state->dpll_hw_state.dpll = dpll;
7730 }
7731
7732 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7733 {
7734         struct drm_device *dev = intel_crtc->base.dev;
7735         struct drm_i915_private *dev_priv = dev->dev_private;
7736         enum pipe pipe = intel_crtc->pipe;
7737         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7738         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7739         uint32_t crtc_vtotal, crtc_vblank_end;
7740         int vsyncshift = 0;
7741
7742         /* We need to be careful not to changed the adjusted mode, for otherwise
7743          * the hw state checker will get angry at the mismatch. */
7744         crtc_vtotal = adjusted_mode->crtc_vtotal;
7745         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7746
7747         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7748                 /* the chip adds 2 halflines automatically */
7749                 crtc_vtotal -= 1;
7750                 crtc_vblank_end -= 1;
7751
7752                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7753                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7754                 else
7755                         vsyncshift = adjusted_mode->crtc_hsync_start -
7756                                 adjusted_mode->crtc_htotal / 2;
7757                 if (vsyncshift < 0)
7758                         vsyncshift += adjusted_mode->crtc_htotal;
7759         }
7760
7761         if (INTEL_INFO(dev)->gen > 3)
7762                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7763
7764         I915_WRITE(HTOTAL(cpu_transcoder),
7765                    (adjusted_mode->crtc_hdisplay - 1) |
7766                    ((adjusted_mode->crtc_htotal - 1) << 16));
7767         I915_WRITE(HBLANK(cpu_transcoder),
7768                    (adjusted_mode->crtc_hblank_start - 1) |
7769                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7770         I915_WRITE(HSYNC(cpu_transcoder),
7771                    (adjusted_mode->crtc_hsync_start - 1) |
7772                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7773
7774         I915_WRITE(VTOTAL(cpu_transcoder),
7775                    (adjusted_mode->crtc_vdisplay - 1) |
7776                    ((crtc_vtotal - 1) << 16));
7777         I915_WRITE(VBLANK(cpu_transcoder),
7778                    (adjusted_mode->crtc_vblank_start - 1) |
7779                    ((crtc_vblank_end - 1) << 16));
7780         I915_WRITE(VSYNC(cpu_transcoder),
7781                    (adjusted_mode->crtc_vsync_start - 1) |
7782                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7783
7784         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7785          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7786          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7787          * bits. */
7788         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7789             (pipe == PIPE_B || pipe == PIPE_C))
7790                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7791
7792         /* pipesrc controls the size that is scaled from, which should
7793          * always be the user's requested size.
7794          */
7795         I915_WRITE(PIPESRC(pipe),
7796                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7797                    (intel_crtc->config->pipe_src_h - 1));
7798 }
7799
7800 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7801                                    struct intel_crtc_state *pipe_config)
7802 {
7803         struct drm_device *dev = crtc->base.dev;
7804         struct drm_i915_private *dev_priv = dev->dev_private;
7805         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7806         uint32_t tmp;
7807
7808         tmp = I915_READ(HTOTAL(cpu_transcoder));
7809         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7810         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7811         tmp = I915_READ(HBLANK(cpu_transcoder));
7812         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7813         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7814         tmp = I915_READ(HSYNC(cpu_transcoder));
7815         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7816         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7817
7818         tmp = I915_READ(VTOTAL(cpu_transcoder));
7819         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7820         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7821         tmp = I915_READ(VBLANK(cpu_transcoder));
7822         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7823         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7824         tmp = I915_READ(VSYNC(cpu_transcoder));
7825         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7826         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7827
7828         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7829                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7830                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7831                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7832         }
7833
7834         tmp = I915_READ(PIPESRC(crtc->pipe));
7835         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7836         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7837
7838         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7839         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7840 }
7841
7842 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7843                                  struct intel_crtc_state *pipe_config)
7844 {
7845         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7846         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7847         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7848         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7849
7850         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7851         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7852         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7853         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7854
7855         mode->flags = pipe_config->base.adjusted_mode.flags;
7856         mode->type = DRM_MODE_TYPE_DRIVER;
7857
7858         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7859         mode->flags |= pipe_config->base.adjusted_mode.flags;
7860
7861         mode->hsync = drm_mode_hsync(mode);
7862         mode->vrefresh = drm_mode_vrefresh(mode);
7863         drm_mode_set_name(mode);
7864 }
7865
7866 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7867 {
7868         struct drm_device *dev = intel_crtc->base.dev;
7869         struct drm_i915_private *dev_priv = dev->dev_private;
7870         uint32_t pipeconf;
7871
7872         pipeconf = 0;
7873
7874         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7875             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7876                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7877
7878         if (intel_crtc->config->double_wide)
7879                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7880
7881         /* only g4x and later have fancy bpc/dither controls */
7882         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7883                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7884                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7885                         pipeconf |= PIPECONF_DITHER_EN |
7886                                     PIPECONF_DITHER_TYPE_SP;
7887
7888                 switch (intel_crtc->config->pipe_bpp) {
7889                 case 18:
7890                         pipeconf |= PIPECONF_6BPC;
7891                         break;
7892                 case 24:
7893                         pipeconf |= PIPECONF_8BPC;
7894                         break;
7895                 case 30:
7896                         pipeconf |= PIPECONF_10BPC;
7897                         break;
7898                 default:
7899                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7900                         BUG();
7901                 }
7902         }
7903
7904         if (HAS_PIPE_CXSR(dev)) {
7905                 if (intel_crtc->lowfreq_avail) {
7906                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7907                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7908                 } else {
7909                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7910                 }
7911         }
7912
7913         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7914                 if (INTEL_INFO(dev)->gen < 4 ||
7915                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7916                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7917                 else
7918                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7919         } else
7920                 pipeconf |= PIPECONF_PROGRESSIVE;
7921
7922         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7923                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7924
7925         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7926         POSTING_READ(PIPECONF(intel_crtc->pipe));
7927 }
7928
7929 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7930                                    struct intel_crtc_state *crtc_state)
7931 {
7932         struct drm_device *dev = crtc->base.dev;
7933         struct drm_i915_private *dev_priv = dev->dev_private;
7934         int refclk, num_connectors = 0;
7935         intel_clock_t clock;
7936         bool ok;
7937         const intel_limit_t *limit;
7938         struct drm_atomic_state *state = crtc_state->base.state;
7939         struct drm_connector *connector;
7940         struct drm_connector_state *connector_state;
7941         int i;
7942
7943         memset(&crtc_state->dpll_hw_state, 0,
7944                sizeof(crtc_state->dpll_hw_state));
7945
7946         if (crtc_state->has_dsi_encoder)
7947                 return 0;
7948
7949         for_each_connector_in_state(state, connector, connector_state, i) {
7950                 if (connector_state->crtc == &crtc->base)
7951                         num_connectors++;
7952         }
7953
7954         if (!crtc_state->clock_set) {
7955                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7956
7957                 /*
7958                  * Returns a set of divisors for the desired target clock with
7959                  * the given refclk, or FALSE.  The returned values represent
7960                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7961                  * 2) / p1 / p2.
7962                  */
7963                 limit = intel_limit(crtc_state, refclk);
7964                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7965                                                  crtc_state->port_clock,
7966                                                  refclk, NULL, &clock);
7967                 if (!ok) {
7968                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7969                         return -EINVAL;
7970                 }
7971
7972                 /* Compat-code for transition, will disappear. */
7973                 crtc_state->dpll.n = clock.n;
7974                 crtc_state->dpll.m1 = clock.m1;
7975                 crtc_state->dpll.m2 = clock.m2;
7976                 crtc_state->dpll.p1 = clock.p1;
7977                 crtc_state->dpll.p2 = clock.p2;
7978         }
7979
7980         if (IS_GEN2(dev)) {
7981                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7982                                   num_connectors);
7983         } else if (IS_CHERRYVIEW(dev)) {
7984                 chv_compute_dpll(crtc, crtc_state);
7985         } else if (IS_VALLEYVIEW(dev)) {
7986                 vlv_compute_dpll(crtc, crtc_state);
7987         } else {
7988                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7989                                   num_connectors);
7990         }
7991
7992         return 0;
7993 }
7994
7995 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7996                                  struct intel_crtc_state *pipe_config)
7997 {
7998         struct drm_device *dev = crtc->base.dev;
7999         struct drm_i915_private *dev_priv = dev->dev_private;
8000         uint32_t tmp;
8001
8002         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8003                 return;
8004
8005         tmp = I915_READ(PFIT_CONTROL);
8006         if (!(tmp & PFIT_ENABLE))
8007                 return;
8008
8009         /* Check whether the pfit is attached to our pipe. */
8010         if (INTEL_INFO(dev)->gen < 4) {
8011                 if (crtc->pipe != PIPE_B)
8012                         return;
8013         } else {
8014                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8015                         return;
8016         }
8017
8018         pipe_config->gmch_pfit.control = tmp;
8019         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8020         if (INTEL_INFO(dev)->gen < 5)
8021                 pipe_config->gmch_pfit.lvds_border_bits =
8022                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8023 }
8024
8025 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8026                                struct intel_crtc_state *pipe_config)
8027 {
8028         struct drm_device *dev = crtc->base.dev;
8029         struct drm_i915_private *dev_priv = dev->dev_private;
8030         int pipe = pipe_config->cpu_transcoder;
8031         intel_clock_t clock;
8032         u32 mdiv;
8033         int refclk = 100000;
8034
8035         /* In case of MIPI DPLL will not even be used */
8036         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8037                 return;
8038
8039         mutex_lock(&dev_priv->sb_lock);
8040         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8041         mutex_unlock(&dev_priv->sb_lock);
8042
8043         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8044         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8045         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8046         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8047         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8048
8049         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8050 }
8051
8052 static void
8053 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8054                               struct intel_initial_plane_config *plane_config)
8055 {
8056         struct drm_device *dev = crtc->base.dev;
8057         struct drm_i915_private *dev_priv = dev->dev_private;
8058         u32 val, base, offset;
8059         int pipe = crtc->pipe, plane = crtc->plane;
8060         int fourcc, pixel_format;
8061         unsigned int aligned_height;
8062         struct drm_framebuffer *fb;
8063         struct intel_framebuffer *intel_fb;
8064
8065         val = I915_READ(DSPCNTR(plane));
8066         if (!(val & DISPLAY_PLANE_ENABLE))
8067                 return;
8068
8069         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8070         if (!intel_fb) {
8071                 DRM_DEBUG_KMS("failed to alloc fb\n");
8072                 return;
8073         }
8074
8075         fb = &intel_fb->base;
8076
8077         if (INTEL_INFO(dev)->gen >= 4) {
8078                 if (val & DISPPLANE_TILED) {
8079                         plane_config->tiling = I915_TILING_X;
8080                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8081                 }
8082         }
8083
8084         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8085         fourcc = i9xx_format_to_fourcc(pixel_format);
8086         fb->pixel_format = fourcc;
8087         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8088
8089         if (INTEL_INFO(dev)->gen >= 4) {
8090                 if (plane_config->tiling)
8091                         offset = I915_READ(DSPTILEOFF(plane));
8092                 else
8093                         offset = I915_READ(DSPLINOFF(plane));
8094                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8095         } else {
8096                 base = I915_READ(DSPADDR(plane));
8097         }
8098         plane_config->base = base;
8099
8100         val = I915_READ(PIPESRC(pipe));
8101         fb->width = ((val >> 16) & 0xfff) + 1;
8102         fb->height = ((val >> 0) & 0xfff) + 1;
8103
8104         val = I915_READ(DSPSTRIDE(pipe));
8105         fb->pitches[0] = val & 0xffffffc0;
8106
8107         aligned_height = intel_fb_align_height(dev, fb->height,
8108                                                fb->pixel_format,
8109                                                fb->modifier[0]);
8110
8111         plane_config->size = fb->pitches[0] * aligned_height;
8112
8113         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8114                       pipe_name(pipe), plane, fb->width, fb->height,
8115                       fb->bits_per_pixel, base, fb->pitches[0],
8116                       plane_config->size);
8117
8118         plane_config->fb = intel_fb;
8119 }
8120
8121 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8122                                struct intel_crtc_state *pipe_config)
8123 {
8124         struct drm_device *dev = crtc->base.dev;
8125         struct drm_i915_private *dev_priv = dev->dev_private;
8126         int pipe = pipe_config->cpu_transcoder;
8127         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8128         intel_clock_t clock;
8129         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8130         int refclk = 100000;
8131
8132         mutex_lock(&dev_priv->sb_lock);
8133         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8134         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8135         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8136         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8137         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8138         mutex_unlock(&dev_priv->sb_lock);
8139
8140         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8141         clock.m2 = (pll_dw0 & 0xff) << 22;
8142         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8143                 clock.m2 |= pll_dw2 & 0x3fffff;
8144         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8145         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8146         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8147
8148         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8149 }
8150
8151 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8152                                  struct intel_crtc_state *pipe_config)
8153 {
8154         struct drm_device *dev = crtc->base.dev;
8155         struct drm_i915_private *dev_priv = dev->dev_private;
8156         uint32_t tmp;
8157
8158         if (!intel_display_power_is_enabled(dev_priv,
8159                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8160                 return false;
8161
8162         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8163         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8164
8165         tmp = I915_READ(PIPECONF(crtc->pipe));
8166         if (!(tmp & PIPECONF_ENABLE))
8167                 return false;
8168
8169         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8170                 switch (tmp & PIPECONF_BPC_MASK) {
8171                 case PIPECONF_6BPC:
8172                         pipe_config->pipe_bpp = 18;
8173                         break;
8174                 case PIPECONF_8BPC:
8175                         pipe_config->pipe_bpp = 24;
8176                         break;
8177                 case PIPECONF_10BPC:
8178                         pipe_config->pipe_bpp = 30;
8179                         break;
8180                 default:
8181                         break;
8182                 }
8183         }
8184
8185         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8186                 pipe_config->limited_color_range = true;
8187
8188         if (INTEL_INFO(dev)->gen < 4)
8189                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8190
8191         intel_get_pipe_timings(crtc, pipe_config);
8192
8193         i9xx_get_pfit_config(crtc, pipe_config);
8194
8195         if (INTEL_INFO(dev)->gen >= 4) {
8196                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8197                 pipe_config->pixel_multiplier =
8198                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8199                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8200                 pipe_config->dpll_hw_state.dpll_md = tmp;
8201         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8202                 tmp = I915_READ(DPLL(crtc->pipe));
8203                 pipe_config->pixel_multiplier =
8204                         ((tmp & SDVO_MULTIPLIER_MASK)
8205                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8206         } else {
8207                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8208                  * port and will be fixed up in the encoder->get_config
8209                  * function. */
8210                 pipe_config->pixel_multiplier = 1;
8211         }
8212         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8213         if (!IS_VALLEYVIEW(dev)) {
8214                 /*
8215                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8216                  * on 830. Filter it out here so that we don't
8217                  * report errors due to that.
8218                  */
8219                 if (IS_I830(dev))
8220                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8221
8222                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8223                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8224         } else {
8225                 /* Mask out read-only status bits. */
8226                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8227                                                      DPLL_PORTC_READY_MASK |
8228                                                      DPLL_PORTB_READY_MASK);
8229         }
8230
8231         if (IS_CHERRYVIEW(dev))
8232                 chv_crtc_clock_get(crtc, pipe_config);
8233         else if (IS_VALLEYVIEW(dev))
8234                 vlv_crtc_clock_get(crtc, pipe_config);
8235         else
8236                 i9xx_crtc_clock_get(crtc, pipe_config);
8237
8238         /*
8239          * Normally the dotclock is filled in by the encoder .get_config()
8240          * but in case the pipe is enabled w/o any ports we need a sane
8241          * default.
8242          */
8243         pipe_config->base.adjusted_mode.crtc_clock =
8244                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8245
8246         return true;
8247 }
8248
8249 static void ironlake_init_pch_refclk(struct drm_device *dev)
8250 {
8251         struct drm_i915_private *dev_priv = dev->dev_private;
8252         struct intel_encoder *encoder;
8253         u32 val, final;
8254         bool has_lvds = false;
8255         bool has_cpu_edp = false;
8256         bool has_panel = false;
8257         bool has_ck505 = false;
8258         bool can_ssc = false;
8259
8260         /* We need to take the global config into account */
8261         for_each_intel_encoder(dev, encoder) {
8262                 switch (encoder->type) {
8263                 case INTEL_OUTPUT_LVDS:
8264                         has_panel = true;
8265                         has_lvds = true;
8266                         break;
8267                 case INTEL_OUTPUT_EDP:
8268                         has_panel = true;
8269                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8270                                 has_cpu_edp = true;
8271                         break;
8272                 default:
8273                         break;
8274                 }
8275         }
8276
8277         if (HAS_PCH_IBX(dev)) {
8278                 has_ck505 = dev_priv->vbt.display_clock_mode;
8279                 can_ssc = has_ck505;
8280         } else {
8281                 has_ck505 = false;
8282                 can_ssc = true;
8283         }
8284
8285         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8286                       has_panel, has_lvds, has_ck505);
8287
8288         /* Ironlake: try to setup display ref clock before DPLL
8289          * enabling. This is only under driver's control after
8290          * PCH B stepping, previous chipset stepping should be
8291          * ignoring this setting.
8292          */
8293         val = I915_READ(PCH_DREF_CONTROL);
8294
8295         /* As we must carefully and slowly disable/enable each source in turn,
8296          * compute the final state we want first and check if we need to
8297          * make any changes at all.
8298          */
8299         final = val;
8300         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8301         if (has_ck505)
8302                 final |= DREF_NONSPREAD_CK505_ENABLE;
8303         else
8304                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8305
8306         final &= ~DREF_SSC_SOURCE_MASK;
8307         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8308         final &= ~DREF_SSC1_ENABLE;
8309
8310         if (has_panel) {
8311                 final |= DREF_SSC_SOURCE_ENABLE;
8312
8313                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8314                         final |= DREF_SSC1_ENABLE;
8315
8316                 if (has_cpu_edp) {
8317                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8318                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8319                         else
8320                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8321                 } else
8322                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8323         } else {
8324                 final |= DREF_SSC_SOURCE_DISABLE;
8325                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8326         }
8327
8328         if (final == val)
8329                 return;
8330
8331         /* Always enable nonspread source */
8332         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8333
8334         if (has_ck505)
8335                 val |= DREF_NONSPREAD_CK505_ENABLE;
8336         else
8337                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8338
8339         if (has_panel) {
8340                 val &= ~DREF_SSC_SOURCE_MASK;
8341                 val |= DREF_SSC_SOURCE_ENABLE;
8342
8343                 /* SSC must be turned on before enabling the CPU output  */
8344                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8345                         DRM_DEBUG_KMS("Using SSC on panel\n");
8346                         val |= DREF_SSC1_ENABLE;
8347                 } else
8348                         val &= ~DREF_SSC1_ENABLE;
8349
8350                 /* Get SSC going before enabling the outputs */
8351                 I915_WRITE(PCH_DREF_CONTROL, val);
8352                 POSTING_READ(PCH_DREF_CONTROL);
8353                 udelay(200);
8354
8355                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8356
8357                 /* Enable CPU source on CPU attached eDP */
8358                 if (has_cpu_edp) {
8359                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8360                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8361                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8362                         } else
8363                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8364                 } else
8365                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8366
8367                 I915_WRITE(PCH_DREF_CONTROL, val);
8368                 POSTING_READ(PCH_DREF_CONTROL);
8369                 udelay(200);
8370         } else {
8371                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8372
8373                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8374
8375                 /* Turn off CPU output */
8376                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8377
8378                 I915_WRITE(PCH_DREF_CONTROL, val);
8379                 POSTING_READ(PCH_DREF_CONTROL);
8380                 udelay(200);
8381
8382                 /* Turn off the SSC source */
8383                 val &= ~DREF_SSC_SOURCE_MASK;
8384                 val |= DREF_SSC_SOURCE_DISABLE;
8385
8386                 /* Turn off SSC1 */
8387                 val &= ~DREF_SSC1_ENABLE;
8388
8389                 I915_WRITE(PCH_DREF_CONTROL, val);
8390                 POSTING_READ(PCH_DREF_CONTROL);
8391                 udelay(200);
8392         }
8393
8394         BUG_ON(val != final);
8395 }
8396
8397 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8398 {
8399         uint32_t tmp;
8400
8401         tmp = I915_READ(SOUTH_CHICKEN2);
8402         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8403         I915_WRITE(SOUTH_CHICKEN2, tmp);
8404
8405         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8406                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8407                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8408
8409         tmp = I915_READ(SOUTH_CHICKEN2);
8410         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8411         I915_WRITE(SOUTH_CHICKEN2, tmp);
8412
8413         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8414                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8415                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8416 }
8417
8418 /* WaMPhyProgramming:hsw */
8419 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8420 {
8421         uint32_t tmp;
8422
8423         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8424         tmp &= ~(0xFF << 24);
8425         tmp |= (0x12 << 24);
8426         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8427
8428         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8429         tmp |= (1 << 11);
8430         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8431
8432         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8433         tmp |= (1 << 11);
8434         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8435
8436         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8437         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8438         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8439
8440         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8441         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8442         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8443
8444         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8445         tmp &= ~(7 << 13);
8446         tmp |= (5 << 13);
8447         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8448
8449         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8450         tmp &= ~(7 << 13);
8451         tmp |= (5 << 13);
8452         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8453
8454         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8455         tmp &= ~0xFF;
8456         tmp |= 0x1C;
8457         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8458
8459         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8460         tmp &= ~0xFF;
8461         tmp |= 0x1C;
8462         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8463
8464         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8465         tmp &= ~(0xFF << 16);
8466         tmp |= (0x1C << 16);
8467         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8468
8469         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8470         tmp &= ~(0xFF << 16);
8471         tmp |= (0x1C << 16);
8472         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8473
8474         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8475         tmp |= (1 << 27);
8476         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8477
8478         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8479         tmp |= (1 << 27);
8480         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8481
8482         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8483         tmp &= ~(0xF << 28);
8484         tmp |= (4 << 28);
8485         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8486
8487         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8488         tmp &= ~(0xF << 28);
8489         tmp |= (4 << 28);
8490         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8491 }
8492
8493 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8494  * Programming" based on the parameters passed:
8495  * - Sequence to enable CLKOUT_DP
8496  * - Sequence to enable CLKOUT_DP without spread
8497  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8498  */
8499 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8500                                  bool with_fdi)
8501 {
8502         struct drm_i915_private *dev_priv = dev->dev_private;
8503         uint32_t reg, tmp;
8504
8505         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8506                 with_spread = true;
8507         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8508                 with_fdi = false;
8509
8510         mutex_lock(&dev_priv->sb_lock);
8511
8512         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8513         tmp &= ~SBI_SSCCTL_DISABLE;
8514         tmp |= SBI_SSCCTL_PATHALT;
8515         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8516
8517         udelay(24);
8518
8519         if (with_spread) {
8520                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8521                 tmp &= ~SBI_SSCCTL_PATHALT;
8522                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8523
8524                 if (with_fdi) {
8525                         lpt_reset_fdi_mphy(dev_priv);
8526                         lpt_program_fdi_mphy(dev_priv);
8527                 }
8528         }
8529
8530         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8531         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8532         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8533         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8534
8535         mutex_unlock(&dev_priv->sb_lock);
8536 }
8537
8538 /* Sequence to disable CLKOUT_DP */
8539 static void lpt_disable_clkout_dp(struct drm_device *dev)
8540 {
8541         struct drm_i915_private *dev_priv = dev->dev_private;
8542         uint32_t reg, tmp;
8543
8544         mutex_lock(&dev_priv->sb_lock);
8545
8546         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8547         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8548         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8549         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8550
8551         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8552         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8553                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8554                         tmp |= SBI_SSCCTL_PATHALT;
8555                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8556                         udelay(32);
8557                 }
8558                 tmp |= SBI_SSCCTL_DISABLE;
8559                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8560         }
8561
8562         mutex_unlock(&dev_priv->sb_lock);
8563 }
8564
8565 static void lpt_init_pch_refclk(struct drm_device *dev)
8566 {
8567         struct intel_encoder *encoder;
8568         bool has_vga = false;
8569
8570         for_each_intel_encoder(dev, encoder) {
8571                 switch (encoder->type) {
8572                 case INTEL_OUTPUT_ANALOG:
8573                         has_vga = true;
8574                         break;
8575                 default:
8576                         break;
8577                 }
8578         }
8579
8580         if (has_vga)
8581                 lpt_enable_clkout_dp(dev, true, true);
8582         else
8583                 lpt_disable_clkout_dp(dev);
8584 }
8585
8586 /*
8587  * Initialize reference clocks when the driver loads
8588  */
8589 void intel_init_pch_refclk(struct drm_device *dev)
8590 {
8591         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8592                 ironlake_init_pch_refclk(dev);
8593         else if (HAS_PCH_LPT(dev))
8594                 lpt_init_pch_refclk(dev);
8595 }
8596
8597 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8598 {
8599         struct drm_device *dev = crtc_state->base.crtc->dev;
8600         struct drm_i915_private *dev_priv = dev->dev_private;
8601         struct drm_atomic_state *state = crtc_state->base.state;
8602         struct drm_connector *connector;
8603         struct drm_connector_state *connector_state;
8604         struct intel_encoder *encoder;
8605         int num_connectors = 0, i;
8606         bool is_lvds = false;
8607
8608         for_each_connector_in_state(state, connector, connector_state, i) {
8609                 if (connector_state->crtc != crtc_state->base.crtc)
8610                         continue;
8611
8612                 encoder = to_intel_encoder(connector_state->best_encoder);
8613
8614                 switch (encoder->type) {
8615                 case INTEL_OUTPUT_LVDS:
8616                         is_lvds = true;
8617                         break;
8618                 default:
8619                         break;
8620                 }
8621                 num_connectors++;
8622         }
8623
8624         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8625                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8626                               dev_priv->vbt.lvds_ssc_freq);
8627                 return dev_priv->vbt.lvds_ssc_freq;
8628         }
8629
8630         return 120000;
8631 }
8632
8633 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8634 {
8635         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8637         int pipe = intel_crtc->pipe;
8638         uint32_t val;
8639
8640         val = 0;
8641
8642         switch (intel_crtc->config->pipe_bpp) {
8643         case 18:
8644                 val |= PIPECONF_6BPC;
8645                 break;
8646         case 24:
8647                 val |= PIPECONF_8BPC;
8648                 break;
8649         case 30:
8650                 val |= PIPECONF_10BPC;
8651                 break;
8652         case 36:
8653                 val |= PIPECONF_12BPC;
8654                 break;
8655         default:
8656                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8657                 BUG();
8658         }
8659
8660         if (intel_crtc->config->dither)
8661                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8662
8663         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8664                 val |= PIPECONF_INTERLACED_ILK;
8665         else
8666                 val |= PIPECONF_PROGRESSIVE;
8667
8668         if (intel_crtc->config->limited_color_range)
8669                 val |= PIPECONF_COLOR_RANGE_SELECT;
8670
8671         I915_WRITE(PIPECONF(pipe), val);
8672         POSTING_READ(PIPECONF(pipe));
8673 }
8674
8675 /*
8676  * Set up the pipe CSC unit.
8677  *
8678  * Currently only full range RGB to limited range RGB conversion
8679  * is supported, but eventually this should handle various
8680  * RGB<->YCbCr scenarios as well.
8681  */
8682 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8683 {
8684         struct drm_device *dev = crtc->dev;
8685         struct drm_i915_private *dev_priv = dev->dev_private;
8686         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8687         int pipe = intel_crtc->pipe;
8688         uint16_t coeff = 0x7800; /* 1.0 */
8689
8690         /*
8691          * TODO: Check what kind of values actually come out of the pipe
8692          * with these coeff/postoff values and adjust to get the best
8693          * accuracy. Perhaps we even need to take the bpc value into
8694          * consideration.
8695          */
8696
8697         if (intel_crtc->config->limited_color_range)
8698                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8699
8700         /*
8701          * GY/GU and RY/RU should be the other way around according
8702          * to BSpec, but reality doesn't agree. Just set them up in
8703          * a way that results in the correct picture.
8704          */
8705         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8706         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8707
8708         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8709         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8710
8711         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8712         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8713
8714         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8715         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8716         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8717
8718         if (INTEL_INFO(dev)->gen > 6) {
8719                 uint16_t postoff = 0;
8720
8721                 if (intel_crtc->config->limited_color_range)
8722                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8723
8724                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8725                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8726                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8727
8728                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8729         } else {
8730                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8731
8732                 if (intel_crtc->config->limited_color_range)
8733                         mode |= CSC_BLACK_SCREEN_OFFSET;
8734
8735                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8736         }
8737 }
8738
8739 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8740 {
8741         struct drm_device *dev = crtc->dev;
8742         struct drm_i915_private *dev_priv = dev->dev_private;
8743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8744         enum pipe pipe = intel_crtc->pipe;
8745         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8746         uint32_t val;
8747
8748         val = 0;
8749
8750         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8751                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8752
8753         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8754                 val |= PIPECONF_INTERLACED_ILK;
8755         else
8756                 val |= PIPECONF_PROGRESSIVE;
8757
8758         I915_WRITE(PIPECONF(cpu_transcoder), val);
8759         POSTING_READ(PIPECONF(cpu_transcoder));
8760
8761         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8762         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8763
8764         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8765                 val = 0;
8766
8767                 switch (intel_crtc->config->pipe_bpp) {
8768                 case 18:
8769                         val |= PIPEMISC_DITHER_6_BPC;
8770                         break;
8771                 case 24:
8772                         val |= PIPEMISC_DITHER_8_BPC;
8773                         break;
8774                 case 30:
8775                         val |= PIPEMISC_DITHER_10_BPC;
8776                         break;
8777                 case 36:
8778                         val |= PIPEMISC_DITHER_12_BPC;
8779                         break;
8780                 default:
8781                         /* Case prevented by pipe_config_set_bpp. */
8782                         BUG();
8783                 }
8784
8785                 if (intel_crtc->config->dither)
8786                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8787
8788                 I915_WRITE(PIPEMISC(pipe), val);
8789         }
8790 }
8791
8792 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8793                                     struct intel_crtc_state *crtc_state,
8794                                     intel_clock_t *clock,
8795                                     bool *has_reduced_clock,
8796                                     intel_clock_t *reduced_clock)
8797 {
8798         struct drm_device *dev = crtc->dev;
8799         struct drm_i915_private *dev_priv = dev->dev_private;
8800         int refclk;
8801         const intel_limit_t *limit;
8802         bool ret;
8803
8804         refclk = ironlake_get_refclk(crtc_state);
8805
8806         /*
8807          * Returns a set of divisors for the desired target clock with the given
8808          * refclk, or FALSE.  The returned values represent the clock equation:
8809          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8810          */
8811         limit = intel_limit(crtc_state, refclk);
8812         ret = dev_priv->display.find_dpll(limit, crtc_state,
8813                                           crtc_state->port_clock,
8814                                           refclk, NULL, clock);
8815         if (!ret)
8816                 return false;
8817
8818         return true;
8819 }
8820
8821 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8822 {
8823         /*
8824          * Account for spread spectrum to avoid
8825          * oversubscribing the link. Max center spread
8826          * is 2.5%; use 5% for safety's sake.
8827          */
8828         u32 bps = target_clock * bpp * 21 / 20;
8829         return DIV_ROUND_UP(bps, link_bw * 8);
8830 }
8831
8832 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8833 {
8834         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8835 }
8836
8837 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8838                                       struct intel_crtc_state *crtc_state,
8839                                       u32 *fp,
8840                                       intel_clock_t *reduced_clock, u32 *fp2)
8841 {
8842         struct drm_crtc *crtc = &intel_crtc->base;
8843         struct drm_device *dev = crtc->dev;
8844         struct drm_i915_private *dev_priv = dev->dev_private;
8845         struct drm_atomic_state *state = crtc_state->base.state;
8846         struct drm_connector *connector;
8847         struct drm_connector_state *connector_state;
8848         struct intel_encoder *encoder;
8849         uint32_t dpll;
8850         int factor, num_connectors = 0, i;
8851         bool is_lvds = false, is_sdvo = false;
8852
8853         for_each_connector_in_state(state, connector, connector_state, i) {
8854                 if (connector_state->crtc != crtc_state->base.crtc)
8855                         continue;
8856
8857                 encoder = to_intel_encoder(connector_state->best_encoder);
8858
8859                 switch (encoder->type) {
8860                 case INTEL_OUTPUT_LVDS:
8861                         is_lvds = true;
8862                         break;
8863                 case INTEL_OUTPUT_SDVO:
8864                 case INTEL_OUTPUT_HDMI:
8865                         is_sdvo = true;
8866                         break;
8867                 default:
8868                         break;
8869                 }
8870
8871                 num_connectors++;
8872         }
8873
8874         /* Enable autotuning of the PLL clock (if permissible) */
8875         factor = 21;
8876         if (is_lvds) {
8877                 if ((intel_panel_use_ssc(dev_priv) &&
8878                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8879                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8880                         factor = 25;
8881         } else if (crtc_state->sdvo_tv_clock)
8882                 factor = 20;
8883
8884         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8885                 *fp |= FP_CB_TUNE;
8886
8887         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8888                 *fp2 |= FP_CB_TUNE;
8889
8890         dpll = 0;
8891
8892         if (is_lvds)
8893                 dpll |= DPLLB_MODE_LVDS;
8894         else
8895                 dpll |= DPLLB_MODE_DAC_SERIAL;
8896
8897         dpll |= (crtc_state->pixel_multiplier - 1)
8898                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8899
8900         if (is_sdvo)
8901                 dpll |= DPLL_SDVO_HIGH_SPEED;
8902         if (crtc_state->has_dp_encoder)
8903                 dpll |= DPLL_SDVO_HIGH_SPEED;
8904
8905         /* compute bitmask from p1 value */
8906         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8907         /* also FPA1 */
8908         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8909
8910         switch (crtc_state->dpll.p2) {
8911         case 5:
8912                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8913                 break;
8914         case 7:
8915                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8916                 break;
8917         case 10:
8918                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8919                 break;
8920         case 14:
8921                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8922                 break;
8923         }
8924
8925         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8926                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8927         else
8928                 dpll |= PLL_REF_INPUT_DREFCLK;
8929
8930         return dpll | DPLL_VCO_ENABLE;
8931 }
8932
8933 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8934                                        struct intel_crtc_state *crtc_state)
8935 {
8936         struct drm_device *dev = crtc->base.dev;
8937         intel_clock_t clock, reduced_clock;
8938         u32 dpll = 0, fp = 0, fp2 = 0;
8939         bool ok, has_reduced_clock = false;
8940         bool is_lvds = false;
8941         struct intel_shared_dpll *pll;
8942
8943         memset(&crtc_state->dpll_hw_state, 0,
8944                sizeof(crtc_state->dpll_hw_state));
8945
8946         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8947
8948         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8949              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8950
8951         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8952                                      &has_reduced_clock, &reduced_clock);
8953         if (!ok && !crtc_state->clock_set) {
8954                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8955                 return -EINVAL;
8956         }
8957         /* Compat-code for transition, will disappear. */
8958         if (!crtc_state->clock_set) {
8959                 crtc_state->dpll.n = clock.n;
8960                 crtc_state->dpll.m1 = clock.m1;
8961                 crtc_state->dpll.m2 = clock.m2;
8962                 crtc_state->dpll.p1 = clock.p1;
8963                 crtc_state->dpll.p2 = clock.p2;
8964         }
8965
8966         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8967         if (crtc_state->has_pch_encoder) {
8968                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8969                 if (has_reduced_clock)
8970                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8971
8972                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8973                                              &fp, &reduced_clock,
8974                                              has_reduced_clock ? &fp2 : NULL);
8975
8976                 crtc_state->dpll_hw_state.dpll = dpll;
8977                 crtc_state->dpll_hw_state.fp0 = fp;
8978                 if (has_reduced_clock)
8979                         crtc_state->dpll_hw_state.fp1 = fp2;
8980                 else
8981                         crtc_state->dpll_hw_state.fp1 = fp;
8982
8983                 pll = intel_get_shared_dpll(crtc, crtc_state);
8984                 if (pll == NULL) {
8985                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8986                                          pipe_name(crtc->pipe));
8987                         return -EINVAL;
8988                 }
8989         }
8990
8991         if (is_lvds && has_reduced_clock)
8992                 crtc->lowfreq_avail = true;
8993         else
8994                 crtc->lowfreq_avail = false;
8995
8996         return 0;
8997 }
8998
8999 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9000                                          struct intel_link_m_n *m_n)
9001 {
9002         struct drm_device *dev = crtc->base.dev;
9003         struct drm_i915_private *dev_priv = dev->dev_private;
9004         enum pipe pipe = crtc->pipe;
9005
9006         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9007         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9008         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9009                 & ~TU_SIZE_MASK;
9010         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9011         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9012                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9013 }
9014
9015 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9016                                          enum transcoder transcoder,
9017                                          struct intel_link_m_n *m_n,
9018                                          struct intel_link_m_n *m2_n2)
9019 {
9020         struct drm_device *dev = crtc->base.dev;
9021         struct drm_i915_private *dev_priv = dev->dev_private;
9022         enum pipe pipe = crtc->pipe;
9023
9024         if (INTEL_INFO(dev)->gen >= 5) {
9025                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9026                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9027                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9028                         & ~TU_SIZE_MASK;
9029                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9030                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9031                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9032                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9033                  * gen < 8) and if DRRS is supported (to make sure the
9034                  * registers are not unnecessarily read).
9035                  */
9036                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9037                         crtc->config->has_drrs) {
9038                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9039                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9040                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9041                                         & ~TU_SIZE_MASK;
9042                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9043                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9044                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9045                 }
9046         } else {
9047                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9048                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9049                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9050                         & ~TU_SIZE_MASK;
9051                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9052                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9053                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9054         }
9055 }
9056
9057 void intel_dp_get_m_n(struct intel_crtc *crtc,
9058                       struct intel_crtc_state *pipe_config)
9059 {
9060         if (pipe_config->has_pch_encoder)
9061                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9062         else
9063                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9064                                              &pipe_config->dp_m_n,
9065                                              &pipe_config->dp_m2_n2);
9066 }
9067
9068 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9069                                         struct intel_crtc_state *pipe_config)
9070 {
9071         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9072                                      &pipe_config->fdi_m_n, NULL);
9073 }
9074
9075 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9076                                     struct intel_crtc_state *pipe_config)
9077 {
9078         struct drm_device *dev = crtc->base.dev;
9079         struct drm_i915_private *dev_priv = dev->dev_private;
9080         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9081         uint32_t ps_ctrl = 0;
9082         int id = -1;
9083         int i;
9084
9085         /* find scaler attached to this pipe */
9086         for (i = 0; i < crtc->num_scalers; i++) {
9087                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9088                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9089                         id = i;
9090                         pipe_config->pch_pfit.enabled = true;
9091                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9092                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9093                         break;
9094                 }
9095         }
9096
9097         scaler_state->scaler_id = id;
9098         if (id >= 0) {
9099                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9100         } else {
9101                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9102         }
9103 }
9104
9105 static void
9106 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9107                                  struct intel_initial_plane_config *plane_config)
9108 {
9109         struct drm_device *dev = crtc->base.dev;
9110         struct drm_i915_private *dev_priv = dev->dev_private;
9111         u32 val, base, offset, stride_mult, tiling;
9112         int pipe = crtc->pipe;
9113         int fourcc, pixel_format;
9114         unsigned int aligned_height;
9115         struct drm_framebuffer *fb;
9116         struct intel_framebuffer *intel_fb;
9117
9118         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9119         if (!intel_fb) {
9120                 DRM_DEBUG_KMS("failed to alloc fb\n");
9121                 return;
9122         }
9123
9124         fb = &intel_fb->base;
9125
9126         val = I915_READ(PLANE_CTL(pipe, 0));
9127         if (!(val & PLANE_CTL_ENABLE))
9128                 goto error;
9129
9130         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9131         fourcc = skl_format_to_fourcc(pixel_format,
9132                                       val & PLANE_CTL_ORDER_RGBX,
9133                                       val & PLANE_CTL_ALPHA_MASK);
9134         fb->pixel_format = fourcc;
9135         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9136
9137         tiling = val & PLANE_CTL_TILED_MASK;
9138         switch (tiling) {
9139         case PLANE_CTL_TILED_LINEAR:
9140                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9141                 break;
9142         case PLANE_CTL_TILED_X:
9143                 plane_config->tiling = I915_TILING_X;
9144                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9145                 break;
9146         case PLANE_CTL_TILED_Y:
9147                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9148                 break;
9149         case PLANE_CTL_TILED_YF:
9150                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9151                 break;
9152         default:
9153                 MISSING_CASE(tiling);
9154                 goto error;
9155         }
9156
9157         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9158         plane_config->base = base;
9159
9160         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9161
9162         val = I915_READ(PLANE_SIZE(pipe, 0));
9163         fb->height = ((val >> 16) & 0xfff) + 1;
9164         fb->width = ((val >> 0) & 0x1fff) + 1;
9165
9166         val = I915_READ(PLANE_STRIDE(pipe, 0));
9167         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9168                                                 fb->pixel_format);
9169         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9170
9171         aligned_height = intel_fb_align_height(dev, fb->height,
9172                                                fb->pixel_format,
9173                                                fb->modifier[0]);
9174
9175         plane_config->size = fb->pitches[0] * aligned_height;
9176
9177         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9178                       pipe_name(pipe), fb->width, fb->height,
9179                       fb->bits_per_pixel, base, fb->pitches[0],
9180                       plane_config->size);
9181
9182         plane_config->fb = intel_fb;
9183         return;
9184
9185 error:
9186         kfree(fb);
9187 }
9188
9189 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9190                                      struct intel_crtc_state *pipe_config)
9191 {
9192         struct drm_device *dev = crtc->base.dev;
9193         struct drm_i915_private *dev_priv = dev->dev_private;
9194         uint32_t tmp;
9195
9196         tmp = I915_READ(PF_CTL(crtc->pipe));
9197
9198         if (tmp & PF_ENABLE) {
9199                 pipe_config->pch_pfit.enabled = true;
9200                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9201                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9202
9203                 /* We currently do not free assignements of panel fitters on
9204                  * ivb/hsw (since we don't use the higher upscaling modes which
9205                  * differentiates them) so just WARN about this case for now. */
9206                 if (IS_GEN7(dev)) {
9207                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9208                                 PF_PIPE_SEL_IVB(crtc->pipe));
9209                 }
9210         }
9211 }
9212
9213 static void
9214 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9215                                   struct intel_initial_plane_config *plane_config)
9216 {
9217         struct drm_device *dev = crtc->base.dev;
9218         struct drm_i915_private *dev_priv = dev->dev_private;
9219         u32 val, base, offset;
9220         int pipe = crtc->pipe;
9221         int fourcc, pixel_format;
9222         unsigned int aligned_height;
9223         struct drm_framebuffer *fb;
9224         struct intel_framebuffer *intel_fb;
9225
9226         val = I915_READ(DSPCNTR(pipe));
9227         if (!(val & DISPLAY_PLANE_ENABLE))
9228                 return;
9229
9230         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9231         if (!intel_fb) {
9232                 DRM_DEBUG_KMS("failed to alloc fb\n");
9233                 return;
9234         }
9235
9236         fb = &intel_fb->base;
9237
9238         if (INTEL_INFO(dev)->gen >= 4) {
9239                 if (val & DISPPLANE_TILED) {
9240                         plane_config->tiling = I915_TILING_X;
9241                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9242                 }
9243         }
9244
9245         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9246         fourcc = i9xx_format_to_fourcc(pixel_format);
9247         fb->pixel_format = fourcc;
9248         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9249
9250         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9251         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9252                 offset = I915_READ(DSPOFFSET(pipe));
9253         } else {
9254                 if (plane_config->tiling)
9255                         offset = I915_READ(DSPTILEOFF(pipe));
9256                 else
9257                         offset = I915_READ(DSPLINOFF(pipe));
9258         }
9259         plane_config->base = base;
9260
9261         val = I915_READ(PIPESRC(pipe));
9262         fb->width = ((val >> 16) & 0xfff) + 1;
9263         fb->height = ((val >> 0) & 0xfff) + 1;
9264
9265         val = I915_READ(DSPSTRIDE(pipe));
9266         fb->pitches[0] = val & 0xffffffc0;
9267
9268         aligned_height = intel_fb_align_height(dev, fb->height,
9269                                                fb->pixel_format,
9270                                                fb->modifier[0]);
9271
9272         plane_config->size = fb->pitches[0] * aligned_height;
9273
9274         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9275                       pipe_name(pipe), fb->width, fb->height,
9276                       fb->bits_per_pixel, base, fb->pitches[0],
9277                       plane_config->size);
9278
9279         plane_config->fb = intel_fb;
9280 }
9281
9282 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9283                                      struct intel_crtc_state *pipe_config)
9284 {
9285         struct drm_device *dev = crtc->base.dev;
9286         struct drm_i915_private *dev_priv = dev->dev_private;
9287         uint32_t tmp;
9288
9289         if (!intel_display_power_is_enabled(dev_priv,
9290                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9291                 return false;
9292
9293         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9294         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9295
9296         tmp = I915_READ(PIPECONF(crtc->pipe));
9297         if (!(tmp & PIPECONF_ENABLE))
9298                 return false;
9299
9300         switch (tmp & PIPECONF_BPC_MASK) {
9301         case PIPECONF_6BPC:
9302                 pipe_config->pipe_bpp = 18;
9303                 break;
9304         case PIPECONF_8BPC:
9305                 pipe_config->pipe_bpp = 24;
9306                 break;
9307         case PIPECONF_10BPC:
9308                 pipe_config->pipe_bpp = 30;
9309                 break;
9310         case PIPECONF_12BPC:
9311                 pipe_config->pipe_bpp = 36;
9312                 break;
9313         default:
9314                 break;
9315         }
9316
9317         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9318                 pipe_config->limited_color_range = true;
9319
9320         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9321                 struct intel_shared_dpll *pll;
9322
9323                 pipe_config->has_pch_encoder = true;
9324
9325                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9326                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9327                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9328
9329                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9330
9331                 if (HAS_PCH_IBX(dev_priv->dev)) {
9332                         pipe_config->shared_dpll =
9333                                 (enum intel_dpll_id) crtc->pipe;
9334                 } else {
9335                         tmp = I915_READ(PCH_DPLL_SEL);
9336                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9337                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9338                         else
9339                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9340                 }
9341
9342                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9343
9344                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9345                                            &pipe_config->dpll_hw_state));
9346
9347                 tmp = pipe_config->dpll_hw_state.dpll;
9348                 pipe_config->pixel_multiplier =
9349                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9350                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9351
9352                 ironlake_pch_clock_get(crtc, pipe_config);
9353         } else {
9354                 pipe_config->pixel_multiplier = 1;
9355         }
9356
9357         intel_get_pipe_timings(crtc, pipe_config);
9358
9359         ironlake_get_pfit_config(crtc, pipe_config);
9360
9361         return true;
9362 }
9363
9364 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9365 {
9366         struct drm_device *dev = dev_priv->dev;
9367         struct intel_crtc *crtc;
9368
9369         for_each_intel_crtc(dev, crtc)
9370                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9371                      pipe_name(crtc->pipe));
9372
9373         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9374         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9375         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9376         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9377         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9378         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9379              "CPU PWM1 enabled\n");
9380         if (IS_HASWELL(dev))
9381                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9382                      "CPU PWM2 enabled\n");
9383         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9384              "PCH PWM1 enabled\n");
9385         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9386              "Utility pin enabled\n");
9387         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9388
9389         /*
9390          * In theory we can still leave IRQs enabled, as long as only the HPD
9391          * interrupts remain enabled. We used to check for that, but since it's
9392          * gen-specific and since we only disable LCPLL after we fully disable
9393          * the interrupts, the check below should be enough.
9394          */
9395         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9396 }
9397
9398 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9399 {
9400         struct drm_device *dev = dev_priv->dev;
9401
9402         if (IS_HASWELL(dev))
9403                 return I915_READ(D_COMP_HSW);
9404         else
9405                 return I915_READ(D_COMP_BDW);
9406 }
9407
9408 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9409 {
9410         struct drm_device *dev = dev_priv->dev;
9411
9412         if (IS_HASWELL(dev)) {
9413                 mutex_lock(&dev_priv->rps.hw_lock);
9414                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9415                                             val))
9416                         DRM_ERROR("Failed to write to D_COMP\n");
9417                 mutex_unlock(&dev_priv->rps.hw_lock);
9418         } else {
9419                 I915_WRITE(D_COMP_BDW, val);
9420                 POSTING_READ(D_COMP_BDW);
9421         }
9422 }
9423
9424 /*
9425  * This function implements pieces of two sequences from BSpec:
9426  * - Sequence for display software to disable LCPLL
9427  * - Sequence for display software to allow package C8+
9428  * The steps implemented here are just the steps that actually touch the LCPLL
9429  * register. Callers should take care of disabling all the display engine
9430  * functions, doing the mode unset, fixing interrupts, etc.
9431  */
9432 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9433                               bool switch_to_fclk, bool allow_power_down)
9434 {
9435         uint32_t val;
9436
9437         assert_can_disable_lcpll(dev_priv);
9438
9439         val = I915_READ(LCPLL_CTL);
9440
9441         if (switch_to_fclk) {
9442                 val |= LCPLL_CD_SOURCE_FCLK;
9443                 I915_WRITE(LCPLL_CTL, val);
9444
9445                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9446                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9447                         DRM_ERROR("Switching to FCLK failed\n");
9448
9449                 val = I915_READ(LCPLL_CTL);
9450         }
9451
9452         val |= LCPLL_PLL_DISABLE;
9453         I915_WRITE(LCPLL_CTL, val);
9454         POSTING_READ(LCPLL_CTL);
9455
9456         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9457                 DRM_ERROR("LCPLL still locked\n");
9458
9459         val = hsw_read_dcomp(dev_priv);
9460         val |= D_COMP_COMP_DISABLE;
9461         hsw_write_dcomp(dev_priv, val);
9462         ndelay(100);
9463
9464         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9465                      1))
9466                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9467
9468         if (allow_power_down) {
9469                 val = I915_READ(LCPLL_CTL);
9470                 val |= LCPLL_POWER_DOWN_ALLOW;
9471                 I915_WRITE(LCPLL_CTL, val);
9472                 POSTING_READ(LCPLL_CTL);
9473         }
9474 }
9475
9476 /*
9477  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9478  * source.
9479  */
9480 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9481 {
9482         uint32_t val;
9483
9484         val = I915_READ(LCPLL_CTL);
9485
9486         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9487                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9488                 return;
9489
9490         /*
9491          * Make sure we're not on PC8 state before disabling PC8, otherwise
9492          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9493          */
9494         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9495
9496         if (val & LCPLL_POWER_DOWN_ALLOW) {
9497                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9498                 I915_WRITE(LCPLL_CTL, val);
9499                 POSTING_READ(LCPLL_CTL);
9500         }
9501
9502         val = hsw_read_dcomp(dev_priv);
9503         val |= D_COMP_COMP_FORCE;
9504         val &= ~D_COMP_COMP_DISABLE;
9505         hsw_write_dcomp(dev_priv, val);
9506
9507         val = I915_READ(LCPLL_CTL);
9508         val &= ~LCPLL_PLL_DISABLE;
9509         I915_WRITE(LCPLL_CTL, val);
9510
9511         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9512                 DRM_ERROR("LCPLL not locked yet\n");
9513
9514         if (val & LCPLL_CD_SOURCE_FCLK) {
9515                 val = I915_READ(LCPLL_CTL);
9516                 val &= ~LCPLL_CD_SOURCE_FCLK;
9517                 I915_WRITE(LCPLL_CTL, val);
9518
9519                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9520                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9521                         DRM_ERROR("Switching back to LCPLL failed\n");
9522         }
9523
9524         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9525         intel_update_cdclk(dev_priv->dev);
9526 }
9527
9528 /*
9529  * Package states C8 and deeper are really deep PC states that can only be
9530  * reached when all the devices on the system allow it, so even if the graphics
9531  * device allows PC8+, it doesn't mean the system will actually get to these
9532  * states. Our driver only allows PC8+ when going into runtime PM.
9533  *
9534  * The requirements for PC8+ are that all the outputs are disabled, the power
9535  * well is disabled and most interrupts are disabled, and these are also
9536  * requirements for runtime PM. When these conditions are met, we manually do
9537  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9538  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9539  * hang the machine.
9540  *
9541  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9542  * the state of some registers, so when we come back from PC8+ we need to
9543  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9544  * need to take care of the registers kept by RC6. Notice that this happens even
9545  * if we don't put the device in PCI D3 state (which is what currently happens
9546  * because of the runtime PM support).
9547  *
9548  * For more, read "Display Sequences for Package C8" on the hardware
9549  * documentation.
9550  */
9551 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9552 {
9553         struct drm_device *dev = dev_priv->dev;
9554         uint32_t val;
9555
9556         DRM_DEBUG_KMS("Enabling package C8+\n");
9557
9558         if (HAS_PCH_LPT_LP(dev)) {
9559                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9560                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9561                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9562         }
9563
9564         lpt_disable_clkout_dp(dev);
9565         hsw_disable_lcpll(dev_priv, true, true);
9566 }
9567
9568 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9569 {
9570         struct drm_device *dev = dev_priv->dev;
9571         uint32_t val;
9572
9573         DRM_DEBUG_KMS("Disabling package C8+\n");
9574
9575         hsw_restore_lcpll(dev_priv);
9576         lpt_init_pch_refclk(dev);
9577
9578         if (HAS_PCH_LPT_LP(dev)) {
9579                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9580                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9581                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9582         }
9583
9584         intel_prepare_ddi(dev);
9585 }
9586
9587 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9588 {
9589         struct drm_device *dev = old_state->dev;
9590         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9591
9592         broxton_set_cdclk(dev, req_cdclk);
9593 }
9594
9595 /* compute the max rate for new configuration */
9596 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9597 {
9598         struct intel_crtc *intel_crtc;
9599         struct intel_crtc_state *crtc_state;
9600         int max_pixel_rate = 0;
9601
9602         for_each_intel_crtc(state->dev, intel_crtc) {
9603                 int pixel_rate;
9604
9605                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9606                 if (IS_ERR(crtc_state))
9607                         return PTR_ERR(crtc_state);
9608
9609                 if (!crtc_state->base.enable)
9610                         continue;
9611
9612                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9613
9614                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9615                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9616                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9617
9618                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9619         }
9620
9621         return max_pixel_rate;
9622 }
9623
9624 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9625 {
9626         struct drm_i915_private *dev_priv = dev->dev_private;
9627         uint32_t val, data;
9628         int ret;
9629
9630         if (WARN((I915_READ(LCPLL_CTL) &
9631                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9632                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9633                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9634                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9635                  "trying to change cdclk frequency with cdclk not enabled\n"))
9636                 return;
9637
9638         mutex_lock(&dev_priv->rps.hw_lock);
9639         ret = sandybridge_pcode_write(dev_priv,
9640                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9641         mutex_unlock(&dev_priv->rps.hw_lock);
9642         if (ret) {
9643                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9644                 return;
9645         }
9646
9647         val = I915_READ(LCPLL_CTL);
9648         val |= LCPLL_CD_SOURCE_FCLK;
9649         I915_WRITE(LCPLL_CTL, val);
9650
9651         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9652                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9653                 DRM_ERROR("Switching to FCLK failed\n");
9654
9655         val = I915_READ(LCPLL_CTL);
9656         val &= ~LCPLL_CLK_FREQ_MASK;
9657
9658         switch (cdclk) {
9659         case 450000:
9660                 val |= LCPLL_CLK_FREQ_450;
9661                 data = 0;
9662                 break;
9663         case 540000:
9664                 val |= LCPLL_CLK_FREQ_54O_BDW;
9665                 data = 1;
9666                 break;
9667         case 337500:
9668                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9669                 data = 2;
9670                 break;
9671         case 675000:
9672                 val |= LCPLL_CLK_FREQ_675_BDW;
9673                 data = 3;
9674                 break;
9675         default:
9676                 WARN(1, "invalid cdclk frequency\n");
9677                 return;
9678         }
9679
9680         I915_WRITE(LCPLL_CTL, val);
9681
9682         val = I915_READ(LCPLL_CTL);
9683         val &= ~LCPLL_CD_SOURCE_FCLK;
9684         I915_WRITE(LCPLL_CTL, val);
9685
9686         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9687                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9688                 DRM_ERROR("Switching back to LCPLL failed\n");
9689
9690         mutex_lock(&dev_priv->rps.hw_lock);
9691         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9692         mutex_unlock(&dev_priv->rps.hw_lock);
9693
9694         intel_update_cdclk(dev);
9695
9696         WARN(cdclk != dev_priv->cdclk_freq,
9697              "cdclk requested %d kHz but got %d kHz\n",
9698              cdclk, dev_priv->cdclk_freq);
9699 }
9700
9701 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9702 {
9703         struct drm_i915_private *dev_priv = to_i915(state->dev);
9704         int max_pixclk = ilk_max_pixel_rate(state);
9705         int cdclk;
9706
9707         /*
9708          * FIXME should also account for plane ratio
9709          * once 64bpp pixel formats are supported.
9710          */
9711         if (max_pixclk > 540000)
9712                 cdclk = 675000;
9713         else if (max_pixclk > 450000)
9714                 cdclk = 540000;
9715         else if (max_pixclk > 337500)
9716                 cdclk = 450000;
9717         else
9718                 cdclk = 337500;
9719
9720         if (cdclk > dev_priv->max_cdclk_freq) {
9721                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9722                               cdclk, dev_priv->max_cdclk_freq);
9723                 return -EINVAL;
9724         }
9725
9726         to_intel_atomic_state(state)->cdclk = cdclk;
9727
9728         return 0;
9729 }
9730
9731 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9732 {
9733         struct drm_device *dev = old_state->dev;
9734         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9735
9736         broadwell_set_cdclk(dev, req_cdclk);
9737 }
9738
9739 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9740                                       struct intel_crtc_state *crtc_state)
9741 {
9742         if (!intel_ddi_pll_select(crtc, crtc_state))
9743                 return -EINVAL;
9744
9745         crtc->lowfreq_avail = false;
9746
9747         return 0;
9748 }
9749
9750 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9751                                 enum port port,
9752                                 struct intel_crtc_state *pipe_config)
9753 {
9754         switch (port) {
9755         case PORT_A:
9756                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9757                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9758                 break;
9759         case PORT_B:
9760                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9761                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9762                 break;
9763         case PORT_C:
9764                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9765                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9766                 break;
9767         default:
9768                 DRM_ERROR("Incorrect port type\n");
9769         }
9770 }
9771
9772 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9773                                 enum port port,
9774                                 struct intel_crtc_state *pipe_config)
9775 {
9776         u32 temp, dpll_ctl1;
9777
9778         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9779         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9780
9781         switch (pipe_config->ddi_pll_sel) {
9782         case SKL_DPLL0:
9783                 /*
9784                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9785                  * of the shared DPLL framework and thus needs to be read out
9786                  * separately
9787                  */
9788                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9789                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9790                 break;
9791         case SKL_DPLL1:
9792                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9793                 break;
9794         case SKL_DPLL2:
9795                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9796                 break;
9797         case SKL_DPLL3:
9798                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9799                 break;
9800         }
9801 }
9802
9803 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9804                                 enum port port,
9805                                 struct intel_crtc_state *pipe_config)
9806 {
9807         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9808
9809         switch (pipe_config->ddi_pll_sel) {
9810         case PORT_CLK_SEL_WRPLL1:
9811                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9812                 break;
9813         case PORT_CLK_SEL_WRPLL2:
9814                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9815                 break;
9816         case PORT_CLK_SEL_SPLL:
9817                 pipe_config->shared_dpll = DPLL_ID_SPLL;
9818                 break;
9819         }
9820 }
9821
9822 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9823                                        struct intel_crtc_state *pipe_config)
9824 {
9825         struct drm_device *dev = crtc->base.dev;
9826         struct drm_i915_private *dev_priv = dev->dev_private;
9827         struct intel_shared_dpll *pll;
9828         enum port port;
9829         uint32_t tmp;
9830
9831         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9832
9833         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9834
9835         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9836                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9837         else if (IS_BROXTON(dev))
9838                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9839         else
9840                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9841
9842         if (pipe_config->shared_dpll >= 0) {
9843                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9844
9845                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9846                                            &pipe_config->dpll_hw_state));
9847         }
9848
9849         /*
9850          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9851          * DDI E. So just check whether this pipe is wired to DDI E and whether
9852          * the PCH transcoder is on.
9853          */
9854         if (INTEL_INFO(dev)->gen < 9 &&
9855             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9856                 pipe_config->has_pch_encoder = true;
9857
9858                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9859                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9860                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9861
9862                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9863         }
9864 }
9865
9866 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9867                                     struct intel_crtc_state *pipe_config)
9868 {
9869         struct drm_device *dev = crtc->base.dev;
9870         struct drm_i915_private *dev_priv = dev->dev_private;
9871         enum intel_display_power_domain pfit_domain;
9872         uint32_t tmp;
9873
9874         if (!intel_display_power_is_enabled(dev_priv,
9875                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9876                 return false;
9877
9878         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9879         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9880
9881         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9882         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9883                 enum pipe trans_edp_pipe;
9884                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9885                 default:
9886                         WARN(1, "unknown pipe linked to edp transcoder\n");
9887                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9888                 case TRANS_DDI_EDP_INPUT_A_ON:
9889                         trans_edp_pipe = PIPE_A;
9890                         break;
9891                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9892                         trans_edp_pipe = PIPE_B;
9893                         break;
9894                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9895                         trans_edp_pipe = PIPE_C;
9896                         break;
9897                 }
9898
9899                 if (trans_edp_pipe == crtc->pipe)
9900                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9901         }
9902
9903         if (!intel_display_power_is_enabled(dev_priv,
9904                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9905                 return false;
9906
9907         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9908         if (!(tmp & PIPECONF_ENABLE))
9909                 return false;
9910
9911         haswell_get_ddi_port_state(crtc, pipe_config);
9912
9913         intel_get_pipe_timings(crtc, pipe_config);
9914
9915         if (INTEL_INFO(dev)->gen >= 9) {
9916                 skl_init_scalers(dev, crtc, pipe_config);
9917         }
9918
9919         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9920
9921         if (INTEL_INFO(dev)->gen >= 9) {
9922                 pipe_config->scaler_state.scaler_id = -1;
9923                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9924         }
9925
9926         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9927                 if (INTEL_INFO(dev)->gen >= 9)
9928                         skylake_get_pfit_config(crtc, pipe_config);
9929                 else
9930                         ironlake_get_pfit_config(crtc, pipe_config);
9931         }
9932
9933         if (IS_HASWELL(dev))
9934                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9935                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9936
9937         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9938                 pipe_config->pixel_multiplier =
9939                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9940         } else {
9941                 pipe_config->pixel_multiplier = 1;
9942         }
9943
9944         return true;
9945 }
9946
9947 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9948 {
9949         struct drm_device *dev = crtc->dev;
9950         struct drm_i915_private *dev_priv = dev->dev_private;
9951         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9952         uint32_t cntl = 0, size = 0;
9953
9954         if (base) {
9955                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9956                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9957                 unsigned int stride = roundup_pow_of_two(width) * 4;
9958
9959                 switch (stride) {
9960                 default:
9961                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9962                                   width, stride);
9963                         stride = 256;
9964                         /* fallthrough */
9965                 case 256:
9966                 case 512:
9967                 case 1024:
9968                 case 2048:
9969                         break;
9970                 }
9971
9972                 cntl |= CURSOR_ENABLE |
9973                         CURSOR_GAMMA_ENABLE |
9974                         CURSOR_FORMAT_ARGB |
9975                         CURSOR_STRIDE(stride);
9976
9977                 size = (height << 12) | width;
9978         }
9979
9980         if (intel_crtc->cursor_cntl != 0 &&
9981             (intel_crtc->cursor_base != base ||
9982              intel_crtc->cursor_size != size ||
9983              intel_crtc->cursor_cntl != cntl)) {
9984                 /* On these chipsets we can only modify the base/size/stride
9985                  * whilst the cursor is disabled.
9986                  */
9987                 I915_WRITE(CURCNTR(PIPE_A), 0);
9988                 POSTING_READ(CURCNTR(PIPE_A));
9989                 intel_crtc->cursor_cntl = 0;
9990         }
9991
9992         if (intel_crtc->cursor_base != base) {
9993                 I915_WRITE(CURBASE(PIPE_A), base);
9994                 intel_crtc->cursor_base = base;
9995         }
9996
9997         if (intel_crtc->cursor_size != size) {
9998                 I915_WRITE(CURSIZE, size);
9999                 intel_crtc->cursor_size = size;
10000         }
10001
10002         if (intel_crtc->cursor_cntl != cntl) {
10003                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10004                 POSTING_READ(CURCNTR(PIPE_A));
10005                 intel_crtc->cursor_cntl = cntl;
10006         }
10007 }
10008
10009 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
10010 {
10011         struct drm_device *dev = crtc->dev;
10012         struct drm_i915_private *dev_priv = dev->dev_private;
10013         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10014         int pipe = intel_crtc->pipe;
10015         uint32_t cntl;
10016
10017         cntl = 0;
10018         if (base) {
10019                 cntl = MCURSOR_GAMMA_ENABLE;
10020                 switch (intel_crtc->base.cursor->state->crtc_w) {
10021                         case 64:
10022                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10023                                 break;
10024                         case 128:
10025                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10026                                 break;
10027                         case 256:
10028                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10029                                 break;
10030                         default:
10031                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10032                                 return;
10033                 }
10034                 cntl |= pipe << 28; /* Connect to correct pipe */
10035
10036                 if (HAS_DDI(dev))
10037                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10038         }
10039
10040         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10041                 cntl |= CURSOR_ROTATE_180;
10042
10043         if (intel_crtc->cursor_cntl != cntl) {
10044                 I915_WRITE(CURCNTR(pipe), cntl);
10045                 POSTING_READ(CURCNTR(pipe));
10046                 intel_crtc->cursor_cntl = cntl;
10047         }
10048
10049         /* and commit changes on next vblank */
10050         I915_WRITE(CURBASE(pipe), base);
10051         POSTING_READ(CURBASE(pipe));
10052
10053         intel_crtc->cursor_base = base;
10054 }
10055
10056 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10057 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10058                                      bool on)
10059 {
10060         struct drm_device *dev = crtc->dev;
10061         struct drm_i915_private *dev_priv = dev->dev_private;
10062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10063         int pipe = intel_crtc->pipe;
10064         struct drm_plane_state *cursor_state = crtc->cursor->state;
10065         int x = cursor_state->crtc_x;
10066         int y = cursor_state->crtc_y;
10067         u32 base = 0, pos = 0;
10068
10069         if (on)
10070                 base = intel_crtc->cursor_addr;
10071
10072         if (x >= intel_crtc->config->pipe_src_w)
10073                 base = 0;
10074
10075         if (y >= intel_crtc->config->pipe_src_h)
10076                 base = 0;
10077
10078         if (x < 0) {
10079                 if (x + cursor_state->crtc_w <= 0)
10080                         base = 0;
10081
10082                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10083                 x = -x;
10084         }
10085         pos |= x << CURSOR_X_SHIFT;
10086
10087         if (y < 0) {
10088                 if (y + cursor_state->crtc_h <= 0)
10089                         base = 0;
10090
10091                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10092                 y = -y;
10093         }
10094         pos |= y << CURSOR_Y_SHIFT;
10095
10096         if (base == 0 && intel_crtc->cursor_base == 0)
10097                 return;
10098
10099         I915_WRITE(CURPOS(pipe), pos);
10100
10101         /* ILK+ do this automagically */
10102         if (HAS_GMCH_DISPLAY(dev) &&
10103             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10104                 base += (cursor_state->crtc_h *
10105                          cursor_state->crtc_w - 1) * 4;
10106         }
10107
10108         if (IS_845G(dev) || IS_I865G(dev))
10109                 i845_update_cursor(crtc, base);
10110         else
10111                 i9xx_update_cursor(crtc, base);
10112 }
10113
10114 static bool cursor_size_ok(struct drm_device *dev,
10115                            uint32_t width, uint32_t height)
10116 {
10117         if (width == 0 || height == 0)
10118                 return false;
10119
10120         /*
10121          * 845g/865g are special in that they are only limited by
10122          * the width of their cursors, the height is arbitrary up to
10123          * the precision of the register. Everything else requires
10124          * square cursors, limited to a few power-of-two sizes.
10125          */
10126         if (IS_845G(dev) || IS_I865G(dev)) {
10127                 if ((width & 63) != 0)
10128                         return false;
10129
10130                 if (width > (IS_845G(dev) ? 64 : 512))
10131                         return false;
10132
10133                 if (height > 1023)
10134                         return false;
10135         } else {
10136                 switch (width | height) {
10137                 case 256:
10138                 case 128:
10139                         if (IS_GEN2(dev))
10140                                 return false;
10141                 case 64:
10142                         break;
10143                 default:
10144                         return false;
10145                 }
10146         }
10147
10148         return true;
10149 }
10150
10151 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10152                                  u16 *blue, uint32_t start, uint32_t size)
10153 {
10154         int end = (start + size > 256) ? 256 : start + size, i;
10155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10156
10157         for (i = start; i < end; i++) {
10158                 intel_crtc->lut_r[i] = red[i] >> 8;
10159                 intel_crtc->lut_g[i] = green[i] >> 8;
10160                 intel_crtc->lut_b[i] = blue[i] >> 8;
10161         }
10162
10163         intel_crtc_load_lut(crtc);
10164 }
10165
10166 /* VESA 640x480x72Hz mode to set on the pipe */
10167 static struct drm_display_mode load_detect_mode = {
10168         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10169                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10170 };
10171
10172 struct drm_framebuffer *
10173 __intel_framebuffer_create(struct drm_device *dev,
10174                            struct drm_mode_fb_cmd2 *mode_cmd,
10175                            struct drm_i915_gem_object *obj)
10176 {
10177         struct intel_framebuffer *intel_fb;
10178         int ret;
10179
10180         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10181         if (!intel_fb)
10182                 return ERR_PTR(-ENOMEM);
10183
10184         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10185         if (ret)
10186                 goto err;
10187
10188         return &intel_fb->base;
10189
10190 err:
10191         kfree(intel_fb);
10192         return ERR_PTR(ret);
10193 }
10194
10195 static struct drm_framebuffer *
10196 intel_framebuffer_create(struct drm_device *dev,
10197                          struct drm_mode_fb_cmd2 *mode_cmd,
10198                          struct drm_i915_gem_object *obj)
10199 {
10200         struct drm_framebuffer *fb;
10201         int ret;
10202
10203         ret = i915_mutex_lock_interruptible(dev);
10204         if (ret)
10205                 return ERR_PTR(ret);
10206         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10207         mutex_unlock(&dev->struct_mutex);
10208
10209         return fb;
10210 }
10211
10212 static u32
10213 intel_framebuffer_pitch_for_width(int width, int bpp)
10214 {
10215         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10216         return ALIGN(pitch, 64);
10217 }
10218
10219 static u32
10220 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10221 {
10222         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10223         return PAGE_ALIGN(pitch * mode->vdisplay);
10224 }
10225
10226 static struct drm_framebuffer *
10227 intel_framebuffer_create_for_mode(struct drm_device *dev,
10228                                   struct drm_display_mode *mode,
10229                                   int depth, int bpp)
10230 {
10231         struct drm_framebuffer *fb;
10232         struct drm_i915_gem_object *obj;
10233         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10234
10235         obj = i915_gem_alloc_object(dev,
10236                                     intel_framebuffer_size_for_mode(mode, bpp));
10237         if (obj == NULL)
10238                 return ERR_PTR(-ENOMEM);
10239
10240         mode_cmd.width = mode->hdisplay;
10241         mode_cmd.height = mode->vdisplay;
10242         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10243                                                                 bpp);
10244         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10245
10246         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10247         if (IS_ERR(fb))
10248                 drm_gem_object_unreference_unlocked(&obj->base);
10249
10250         return fb;
10251 }
10252
10253 static struct drm_framebuffer *
10254 mode_fits_in_fbdev(struct drm_device *dev,
10255                    struct drm_display_mode *mode)
10256 {
10257 #ifdef CONFIG_DRM_FBDEV_EMULATION
10258         struct drm_i915_private *dev_priv = dev->dev_private;
10259         struct drm_i915_gem_object *obj;
10260         struct drm_framebuffer *fb;
10261
10262         if (!dev_priv->fbdev)
10263                 return NULL;
10264
10265         if (!dev_priv->fbdev->fb)
10266                 return NULL;
10267
10268         obj = dev_priv->fbdev->fb->obj;
10269         BUG_ON(!obj);
10270
10271         fb = &dev_priv->fbdev->fb->base;
10272         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10273                                                                fb->bits_per_pixel))
10274                 return NULL;
10275
10276         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10277                 return NULL;
10278
10279         return fb;
10280 #else
10281         return NULL;
10282 #endif
10283 }
10284
10285 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10286                                            struct drm_crtc *crtc,
10287                                            struct drm_display_mode *mode,
10288                                            struct drm_framebuffer *fb,
10289                                            int x, int y)
10290 {
10291         struct drm_plane_state *plane_state;
10292         int hdisplay, vdisplay;
10293         int ret;
10294
10295         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10296         if (IS_ERR(plane_state))
10297                 return PTR_ERR(plane_state);
10298
10299         if (mode)
10300                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10301         else
10302                 hdisplay = vdisplay = 0;
10303
10304         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10305         if (ret)
10306                 return ret;
10307         drm_atomic_set_fb_for_plane(plane_state, fb);
10308         plane_state->crtc_x = 0;
10309         plane_state->crtc_y = 0;
10310         plane_state->crtc_w = hdisplay;
10311         plane_state->crtc_h = vdisplay;
10312         plane_state->src_x = x << 16;
10313         plane_state->src_y = y << 16;
10314         plane_state->src_w = hdisplay << 16;
10315         plane_state->src_h = vdisplay << 16;
10316
10317         return 0;
10318 }
10319
10320 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10321                                 struct drm_display_mode *mode,
10322                                 struct intel_load_detect_pipe *old,
10323                                 struct drm_modeset_acquire_ctx *ctx)
10324 {
10325         struct intel_crtc *intel_crtc;
10326         struct intel_encoder *intel_encoder =
10327                 intel_attached_encoder(connector);
10328         struct drm_crtc *possible_crtc;
10329         struct drm_encoder *encoder = &intel_encoder->base;
10330         struct drm_crtc *crtc = NULL;
10331         struct drm_device *dev = encoder->dev;
10332         struct drm_framebuffer *fb;
10333         struct drm_mode_config *config = &dev->mode_config;
10334         struct drm_atomic_state *state = NULL;
10335         struct drm_connector_state *connector_state;
10336         struct intel_crtc_state *crtc_state;
10337         int ret, i = -1;
10338
10339         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10340                       connector->base.id, connector->name,
10341                       encoder->base.id, encoder->name);
10342
10343 retry:
10344         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10345         if (ret)
10346                 goto fail;
10347
10348         /*
10349          * Algorithm gets a little messy:
10350          *
10351          *   - if the connector already has an assigned crtc, use it (but make
10352          *     sure it's on first)
10353          *
10354          *   - try to find the first unused crtc that can drive this connector,
10355          *     and use that if we find one
10356          */
10357
10358         /* See if we already have a CRTC for this connector */
10359         if (encoder->crtc) {
10360                 crtc = encoder->crtc;
10361
10362                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10363                 if (ret)
10364                         goto fail;
10365                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10366                 if (ret)
10367                         goto fail;
10368
10369                 old->dpms_mode = connector->dpms;
10370                 old->load_detect_temp = false;
10371
10372                 /* Make sure the crtc and connector are running */
10373                 if (connector->dpms != DRM_MODE_DPMS_ON)
10374                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10375
10376                 return true;
10377         }
10378
10379         /* Find an unused one (if possible) */
10380         for_each_crtc(dev, possible_crtc) {
10381                 i++;
10382                 if (!(encoder->possible_crtcs & (1 << i)))
10383                         continue;
10384                 if (possible_crtc->state->enable)
10385                         continue;
10386
10387                 crtc = possible_crtc;
10388                 break;
10389         }
10390
10391         /*
10392          * If we didn't find an unused CRTC, don't use any.
10393          */
10394         if (!crtc) {
10395                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10396                 goto fail;
10397         }
10398
10399         ret = drm_modeset_lock(&crtc->mutex, ctx);
10400         if (ret)
10401                 goto fail;
10402         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10403         if (ret)
10404                 goto fail;
10405
10406         intel_crtc = to_intel_crtc(crtc);
10407         old->dpms_mode = connector->dpms;
10408         old->load_detect_temp = true;
10409         old->release_fb = NULL;
10410
10411         state = drm_atomic_state_alloc(dev);
10412         if (!state)
10413                 return false;
10414
10415         state->acquire_ctx = ctx;
10416
10417         connector_state = drm_atomic_get_connector_state(state, connector);
10418         if (IS_ERR(connector_state)) {
10419                 ret = PTR_ERR(connector_state);
10420                 goto fail;
10421         }
10422
10423         connector_state->crtc = crtc;
10424         connector_state->best_encoder = &intel_encoder->base;
10425
10426         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10427         if (IS_ERR(crtc_state)) {
10428                 ret = PTR_ERR(crtc_state);
10429                 goto fail;
10430         }
10431
10432         crtc_state->base.active = crtc_state->base.enable = true;
10433
10434         if (!mode)
10435                 mode = &load_detect_mode;
10436
10437         /* We need a framebuffer large enough to accommodate all accesses
10438          * that the plane may generate whilst we perform load detection.
10439          * We can not rely on the fbcon either being present (we get called
10440          * during its initialisation to detect all boot displays, or it may
10441          * not even exist) or that it is large enough to satisfy the
10442          * requested mode.
10443          */
10444         fb = mode_fits_in_fbdev(dev, mode);
10445         if (fb == NULL) {
10446                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10447                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10448                 old->release_fb = fb;
10449         } else
10450                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10451         if (IS_ERR(fb)) {
10452                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10453                 goto fail;
10454         }
10455
10456         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10457         if (ret)
10458                 goto fail;
10459
10460         drm_mode_copy(&crtc_state->base.mode, mode);
10461
10462         if (drm_atomic_commit(state)) {
10463                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10464                 if (old->release_fb)
10465                         old->release_fb->funcs->destroy(old->release_fb);
10466                 goto fail;
10467         }
10468         crtc->primary->crtc = crtc;
10469
10470         /* let the connector get through one full cycle before testing */
10471         intel_wait_for_vblank(dev, intel_crtc->pipe);
10472         return true;
10473
10474 fail:
10475         drm_atomic_state_free(state);
10476         state = NULL;
10477
10478         if (ret == -EDEADLK) {
10479                 drm_modeset_backoff(ctx);
10480                 goto retry;
10481         }
10482
10483         return false;
10484 }
10485
10486 void intel_release_load_detect_pipe(struct drm_connector *connector,
10487                                     struct intel_load_detect_pipe *old,
10488                                     struct drm_modeset_acquire_ctx *ctx)
10489 {
10490         struct drm_device *dev = connector->dev;
10491         struct intel_encoder *intel_encoder =
10492                 intel_attached_encoder(connector);
10493         struct drm_encoder *encoder = &intel_encoder->base;
10494         struct drm_crtc *crtc = encoder->crtc;
10495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10496         struct drm_atomic_state *state;
10497         struct drm_connector_state *connector_state;
10498         struct intel_crtc_state *crtc_state;
10499         int ret;
10500
10501         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10502                       connector->base.id, connector->name,
10503                       encoder->base.id, encoder->name);
10504
10505         if (old->load_detect_temp) {
10506                 state = drm_atomic_state_alloc(dev);
10507                 if (!state)
10508                         goto fail;
10509
10510                 state->acquire_ctx = ctx;
10511
10512                 connector_state = drm_atomic_get_connector_state(state, connector);
10513                 if (IS_ERR(connector_state))
10514                         goto fail;
10515
10516                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10517                 if (IS_ERR(crtc_state))
10518                         goto fail;
10519
10520                 connector_state->best_encoder = NULL;
10521                 connector_state->crtc = NULL;
10522
10523                 crtc_state->base.enable = crtc_state->base.active = false;
10524
10525                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10526                                                       0, 0);
10527                 if (ret)
10528                         goto fail;
10529
10530                 ret = drm_atomic_commit(state);
10531                 if (ret)
10532                         goto fail;
10533
10534                 if (old->release_fb) {
10535                         drm_framebuffer_unregister_private(old->release_fb);
10536                         drm_framebuffer_unreference(old->release_fb);
10537                 }
10538
10539                 return;
10540         }
10541
10542         /* Switch crtc and encoder back off if necessary */
10543         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10544                 connector->funcs->dpms(connector, old->dpms_mode);
10545
10546         return;
10547 fail:
10548         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10549         drm_atomic_state_free(state);
10550 }
10551
10552 static int i9xx_pll_refclk(struct drm_device *dev,
10553                            const struct intel_crtc_state *pipe_config)
10554 {
10555         struct drm_i915_private *dev_priv = dev->dev_private;
10556         u32 dpll = pipe_config->dpll_hw_state.dpll;
10557
10558         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10559                 return dev_priv->vbt.lvds_ssc_freq;
10560         else if (HAS_PCH_SPLIT(dev))
10561                 return 120000;
10562         else if (!IS_GEN2(dev))
10563                 return 96000;
10564         else
10565                 return 48000;
10566 }
10567
10568 /* Returns the clock of the currently programmed mode of the given pipe. */
10569 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10570                                 struct intel_crtc_state *pipe_config)
10571 {
10572         struct drm_device *dev = crtc->base.dev;
10573         struct drm_i915_private *dev_priv = dev->dev_private;
10574         int pipe = pipe_config->cpu_transcoder;
10575         u32 dpll = pipe_config->dpll_hw_state.dpll;
10576         u32 fp;
10577         intel_clock_t clock;
10578         int port_clock;
10579         int refclk = i9xx_pll_refclk(dev, pipe_config);
10580
10581         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10582                 fp = pipe_config->dpll_hw_state.fp0;
10583         else
10584                 fp = pipe_config->dpll_hw_state.fp1;
10585
10586         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10587         if (IS_PINEVIEW(dev)) {
10588                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10589                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10590         } else {
10591                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10592                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10593         }
10594
10595         if (!IS_GEN2(dev)) {
10596                 if (IS_PINEVIEW(dev))
10597                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10598                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10599                 else
10600                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10601                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10602
10603                 switch (dpll & DPLL_MODE_MASK) {
10604                 case DPLLB_MODE_DAC_SERIAL:
10605                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10606                                 5 : 10;
10607                         break;
10608                 case DPLLB_MODE_LVDS:
10609                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10610                                 7 : 14;
10611                         break;
10612                 default:
10613                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10614                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10615                         return;
10616                 }
10617
10618                 if (IS_PINEVIEW(dev))
10619                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10620                 else
10621                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10622         } else {
10623                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10624                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10625
10626                 if (is_lvds) {
10627                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10628                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10629
10630                         if (lvds & LVDS_CLKB_POWER_UP)
10631                                 clock.p2 = 7;
10632                         else
10633                                 clock.p2 = 14;
10634                 } else {
10635                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10636                                 clock.p1 = 2;
10637                         else {
10638                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10639                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10640                         }
10641                         if (dpll & PLL_P2_DIVIDE_BY_4)
10642                                 clock.p2 = 4;
10643                         else
10644                                 clock.p2 = 2;
10645                 }
10646
10647                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10648         }
10649
10650         /*
10651          * This value includes pixel_multiplier. We will use
10652          * port_clock to compute adjusted_mode.crtc_clock in the
10653          * encoder's get_config() function.
10654          */
10655         pipe_config->port_clock = port_clock;
10656 }
10657
10658 int intel_dotclock_calculate(int link_freq,
10659                              const struct intel_link_m_n *m_n)
10660 {
10661         /*
10662          * The calculation for the data clock is:
10663          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10664          * But we want to avoid losing precison if possible, so:
10665          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10666          *
10667          * and the link clock is simpler:
10668          * link_clock = (m * link_clock) / n
10669          */
10670
10671         if (!m_n->link_n)
10672                 return 0;
10673
10674         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10675 }
10676
10677 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10678                                    struct intel_crtc_state *pipe_config)
10679 {
10680         struct drm_device *dev = crtc->base.dev;
10681
10682         /* read out port_clock from the DPLL */
10683         i9xx_crtc_clock_get(crtc, pipe_config);
10684
10685         /*
10686          * This value does not include pixel_multiplier.
10687          * We will check that port_clock and adjusted_mode.crtc_clock
10688          * agree once we know their relationship in the encoder's
10689          * get_config() function.
10690          */
10691         pipe_config->base.adjusted_mode.crtc_clock =
10692                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10693                                          &pipe_config->fdi_m_n);
10694 }
10695
10696 /** Returns the currently programmed mode of the given pipe. */
10697 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10698                                              struct drm_crtc *crtc)
10699 {
10700         struct drm_i915_private *dev_priv = dev->dev_private;
10701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10702         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10703         struct drm_display_mode *mode;
10704         struct intel_crtc_state pipe_config;
10705         int htot = I915_READ(HTOTAL(cpu_transcoder));
10706         int hsync = I915_READ(HSYNC(cpu_transcoder));
10707         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10708         int vsync = I915_READ(VSYNC(cpu_transcoder));
10709         enum pipe pipe = intel_crtc->pipe;
10710
10711         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10712         if (!mode)
10713                 return NULL;
10714
10715         /*
10716          * Construct a pipe_config sufficient for getting the clock info
10717          * back out of crtc_clock_get.
10718          *
10719          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10720          * to use a real value here instead.
10721          */
10722         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10723         pipe_config.pixel_multiplier = 1;
10724         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10725         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10726         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10727         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10728
10729         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10730         mode->hdisplay = (htot & 0xffff) + 1;
10731         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10732         mode->hsync_start = (hsync & 0xffff) + 1;
10733         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10734         mode->vdisplay = (vtot & 0xffff) + 1;
10735         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10736         mode->vsync_start = (vsync & 0xffff) + 1;
10737         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10738
10739         drm_mode_set_name(mode);
10740
10741         return mode;
10742 }
10743
10744 void intel_mark_busy(struct drm_device *dev)
10745 {
10746         struct drm_i915_private *dev_priv = dev->dev_private;
10747
10748         if (dev_priv->mm.busy)
10749                 return;
10750
10751         intel_runtime_pm_get(dev_priv);
10752         i915_update_gfx_val(dev_priv);
10753         if (INTEL_INFO(dev)->gen >= 6)
10754                 gen6_rps_busy(dev_priv);
10755         dev_priv->mm.busy = true;
10756 }
10757
10758 void intel_mark_idle(struct drm_device *dev)
10759 {
10760         struct drm_i915_private *dev_priv = dev->dev_private;
10761
10762         if (!dev_priv->mm.busy)
10763                 return;
10764
10765         dev_priv->mm.busy = false;
10766
10767         if (INTEL_INFO(dev)->gen >= 6)
10768                 gen6_rps_idle(dev->dev_private);
10769
10770         intel_runtime_pm_put(dev_priv);
10771 }
10772
10773 static void intel_crtc_destroy(struct drm_crtc *crtc)
10774 {
10775         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10776         struct drm_device *dev = crtc->dev;
10777         struct intel_unpin_work *work;
10778
10779         spin_lock_irq(&dev->event_lock);
10780         work = intel_crtc->unpin_work;
10781         intel_crtc->unpin_work = NULL;
10782         spin_unlock_irq(&dev->event_lock);
10783
10784         if (work) {
10785                 cancel_work_sync(&work->work);
10786                 kfree(work);
10787         }
10788
10789         drm_crtc_cleanup(crtc);
10790
10791         kfree(intel_crtc);
10792 }
10793
10794 static void intel_unpin_work_fn(struct work_struct *__work)
10795 {
10796         struct intel_unpin_work *work =
10797                 container_of(__work, struct intel_unpin_work, work);
10798         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10799         struct drm_device *dev = crtc->base.dev;
10800         struct drm_plane *primary = crtc->base.primary;
10801
10802         mutex_lock(&dev->struct_mutex);
10803         intel_unpin_fb_obj(work->old_fb, primary->state);
10804         drm_gem_object_unreference(&work->pending_flip_obj->base);
10805
10806         if (work->flip_queued_req)
10807                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10808         mutex_unlock(&dev->struct_mutex);
10809
10810         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10811         drm_framebuffer_unreference(work->old_fb);
10812
10813         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10814         atomic_dec(&crtc->unpin_work_count);
10815
10816         kfree(work);
10817 }
10818
10819 static void do_intel_finish_page_flip(struct drm_device *dev,
10820                                       struct drm_crtc *crtc)
10821 {
10822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10823         struct intel_unpin_work *work;
10824         unsigned long flags;
10825
10826         /* Ignore early vblank irqs */
10827         if (intel_crtc == NULL)
10828                 return;
10829
10830         /*
10831          * This is called both by irq handlers and the reset code (to complete
10832          * lost pageflips) so needs the full irqsave spinlocks.
10833          */
10834         spin_lock_irqsave(&dev->event_lock, flags);
10835         work = intel_crtc->unpin_work;
10836
10837         /* Ensure we don't miss a work->pending update ... */
10838         smp_rmb();
10839
10840         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10841                 spin_unlock_irqrestore(&dev->event_lock, flags);
10842                 return;
10843         }
10844
10845         page_flip_completed(intel_crtc);
10846
10847         spin_unlock_irqrestore(&dev->event_lock, flags);
10848 }
10849
10850 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10851 {
10852         struct drm_i915_private *dev_priv = dev->dev_private;
10853         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10854
10855         do_intel_finish_page_flip(dev, crtc);
10856 }
10857
10858 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10859 {
10860         struct drm_i915_private *dev_priv = dev->dev_private;
10861         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10862
10863         do_intel_finish_page_flip(dev, crtc);
10864 }
10865
10866 /* Is 'a' after or equal to 'b'? */
10867 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10868 {
10869         return !((a - b) & 0x80000000);
10870 }
10871
10872 static bool page_flip_finished(struct intel_crtc *crtc)
10873 {
10874         struct drm_device *dev = crtc->base.dev;
10875         struct drm_i915_private *dev_priv = dev->dev_private;
10876
10877         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10878             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10879                 return true;
10880
10881         /*
10882          * The relevant registers doen't exist on pre-ctg.
10883          * As the flip done interrupt doesn't trigger for mmio
10884          * flips on gmch platforms, a flip count check isn't
10885          * really needed there. But since ctg has the registers,
10886          * include it in the check anyway.
10887          */
10888         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10889                 return true;
10890
10891         /*
10892          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10893          * used the same base address. In that case the mmio flip might
10894          * have completed, but the CS hasn't even executed the flip yet.
10895          *
10896          * A flip count check isn't enough as the CS might have updated
10897          * the base address just after start of vblank, but before we
10898          * managed to process the interrupt. This means we'd complete the
10899          * CS flip too soon.
10900          *
10901          * Combining both checks should get us a good enough result. It may
10902          * still happen that the CS flip has been executed, but has not
10903          * yet actually completed. But in case the base address is the same
10904          * anyway, we don't really care.
10905          */
10906         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10907                 crtc->unpin_work->gtt_offset &&
10908                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10909                                     crtc->unpin_work->flip_count);
10910 }
10911
10912 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10913 {
10914         struct drm_i915_private *dev_priv = dev->dev_private;
10915         struct intel_crtc *intel_crtc =
10916                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10917         unsigned long flags;
10918
10919
10920         /*
10921          * This is called both by irq handlers and the reset code (to complete
10922          * lost pageflips) so needs the full irqsave spinlocks.
10923          *
10924          * NB: An MMIO update of the plane base pointer will also
10925          * generate a page-flip completion irq, i.e. every modeset
10926          * is also accompanied by a spurious intel_prepare_page_flip().
10927          */
10928         spin_lock_irqsave(&dev->event_lock, flags);
10929         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10930                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10931         spin_unlock_irqrestore(&dev->event_lock, flags);
10932 }
10933
10934 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10935 {
10936         /* Ensure that the work item is consistent when activating it ... */
10937         smp_wmb();
10938         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10939         /* and that it is marked active as soon as the irq could fire. */
10940         smp_wmb();
10941 }
10942
10943 static int intel_gen2_queue_flip(struct drm_device *dev,
10944                                  struct drm_crtc *crtc,
10945                                  struct drm_framebuffer *fb,
10946                                  struct drm_i915_gem_object *obj,
10947                                  struct drm_i915_gem_request *req,
10948                                  uint32_t flags)
10949 {
10950         struct intel_engine_cs *ring = req->ring;
10951         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10952         u32 flip_mask;
10953         int ret;
10954
10955         ret = intel_ring_begin(req, 6);
10956         if (ret)
10957                 return ret;
10958
10959         /* Can't queue multiple flips, so wait for the previous
10960          * one to finish before executing the next.
10961          */
10962         if (intel_crtc->plane)
10963                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10964         else
10965                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10966         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10967         intel_ring_emit(ring, MI_NOOP);
10968         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10969                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10970         intel_ring_emit(ring, fb->pitches[0]);
10971         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10972         intel_ring_emit(ring, 0); /* aux display base address, unused */
10973
10974         intel_mark_page_flip_active(intel_crtc->unpin_work);
10975         return 0;
10976 }
10977
10978 static int intel_gen3_queue_flip(struct drm_device *dev,
10979                                  struct drm_crtc *crtc,
10980                                  struct drm_framebuffer *fb,
10981                                  struct drm_i915_gem_object *obj,
10982                                  struct drm_i915_gem_request *req,
10983                                  uint32_t flags)
10984 {
10985         struct intel_engine_cs *ring = req->ring;
10986         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10987         u32 flip_mask;
10988         int ret;
10989
10990         ret = intel_ring_begin(req, 6);
10991         if (ret)
10992                 return ret;
10993
10994         if (intel_crtc->plane)
10995                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10996         else
10997                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10998         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10999         intel_ring_emit(ring, MI_NOOP);
11000         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11001                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11002         intel_ring_emit(ring, fb->pitches[0]);
11003         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11004         intel_ring_emit(ring, MI_NOOP);
11005
11006         intel_mark_page_flip_active(intel_crtc->unpin_work);
11007         return 0;
11008 }
11009
11010 static int intel_gen4_queue_flip(struct drm_device *dev,
11011                                  struct drm_crtc *crtc,
11012                                  struct drm_framebuffer *fb,
11013                                  struct drm_i915_gem_object *obj,
11014                                  struct drm_i915_gem_request *req,
11015                                  uint32_t flags)
11016 {
11017         struct intel_engine_cs *ring = req->ring;
11018         struct drm_i915_private *dev_priv = dev->dev_private;
11019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11020         uint32_t pf, pipesrc;
11021         int ret;
11022
11023         ret = intel_ring_begin(req, 4);
11024         if (ret)
11025                 return ret;
11026
11027         /* i965+ uses the linear or tiled offsets from the
11028          * Display Registers (which do not change across a page-flip)
11029          * so we need only reprogram the base address.
11030          */
11031         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11032                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11033         intel_ring_emit(ring, fb->pitches[0]);
11034         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11035                         obj->tiling_mode);
11036
11037         /* XXX Enabling the panel-fitter across page-flip is so far
11038          * untested on non-native modes, so ignore it for now.
11039          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11040          */
11041         pf = 0;
11042         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11043         intel_ring_emit(ring, pf | pipesrc);
11044
11045         intel_mark_page_flip_active(intel_crtc->unpin_work);
11046         return 0;
11047 }
11048
11049 static int intel_gen6_queue_flip(struct drm_device *dev,
11050                                  struct drm_crtc *crtc,
11051                                  struct drm_framebuffer *fb,
11052                                  struct drm_i915_gem_object *obj,
11053                                  struct drm_i915_gem_request *req,
11054                                  uint32_t flags)
11055 {
11056         struct intel_engine_cs *ring = req->ring;
11057         struct drm_i915_private *dev_priv = dev->dev_private;
11058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11059         uint32_t pf, pipesrc;
11060         int ret;
11061
11062         ret = intel_ring_begin(req, 4);
11063         if (ret)
11064                 return ret;
11065
11066         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11067                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11068         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11069         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11070
11071         /* Contrary to the suggestions in the documentation,
11072          * "Enable Panel Fitter" does not seem to be required when page
11073          * flipping with a non-native mode, and worse causes a normal
11074          * modeset to fail.
11075          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11076          */
11077         pf = 0;
11078         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11079         intel_ring_emit(ring, pf | pipesrc);
11080
11081         intel_mark_page_flip_active(intel_crtc->unpin_work);
11082         return 0;
11083 }
11084
11085 static int intel_gen7_queue_flip(struct drm_device *dev,
11086                                  struct drm_crtc *crtc,
11087                                  struct drm_framebuffer *fb,
11088                                  struct drm_i915_gem_object *obj,
11089                                  struct drm_i915_gem_request *req,
11090                                  uint32_t flags)
11091 {
11092         struct intel_engine_cs *ring = req->ring;
11093         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11094         uint32_t plane_bit = 0;
11095         int len, ret;
11096
11097         switch (intel_crtc->plane) {
11098         case PLANE_A:
11099                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11100                 break;
11101         case PLANE_B:
11102                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11103                 break;
11104         case PLANE_C:
11105                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11106                 break;
11107         default:
11108                 WARN_ONCE(1, "unknown plane in flip command\n");
11109                 return -ENODEV;
11110         }
11111
11112         len = 4;
11113         if (ring->id == RCS) {
11114                 len += 6;
11115                 /*
11116                  * On Gen 8, SRM is now taking an extra dword to accommodate
11117                  * 48bits addresses, and we need a NOOP for the batch size to
11118                  * stay even.
11119                  */
11120                 if (IS_GEN8(dev))
11121                         len += 2;
11122         }
11123
11124         /*
11125          * BSpec MI_DISPLAY_FLIP for IVB:
11126          * "The full packet must be contained within the same cache line."
11127          *
11128          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11129          * cacheline, if we ever start emitting more commands before
11130          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11131          * then do the cacheline alignment, and finally emit the
11132          * MI_DISPLAY_FLIP.
11133          */
11134         ret = intel_ring_cacheline_align(req);
11135         if (ret)
11136                 return ret;
11137
11138         ret = intel_ring_begin(req, len);
11139         if (ret)
11140                 return ret;
11141
11142         /* Unmask the flip-done completion message. Note that the bspec says that
11143          * we should do this for both the BCS and RCS, and that we must not unmask
11144          * more than one flip event at any time (or ensure that one flip message
11145          * can be sent by waiting for flip-done prior to queueing new flips).
11146          * Experimentation says that BCS works despite DERRMR masking all
11147          * flip-done completion events and that unmasking all planes at once
11148          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11149          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11150          */
11151         if (ring->id == RCS) {
11152                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11153                 intel_ring_emit_reg(ring, DERRMR);
11154                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11155                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11156                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11157                 if (IS_GEN8(dev))
11158                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11159                                               MI_SRM_LRM_GLOBAL_GTT);
11160                 else
11161                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11162                                               MI_SRM_LRM_GLOBAL_GTT);
11163                 intel_ring_emit_reg(ring, DERRMR);
11164                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11165                 if (IS_GEN8(dev)) {
11166                         intel_ring_emit(ring, 0);
11167                         intel_ring_emit(ring, MI_NOOP);
11168                 }
11169         }
11170
11171         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11172         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11173         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11174         intel_ring_emit(ring, (MI_NOOP));
11175
11176         intel_mark_page_flip_active(intel_crtc->unpin_work);
11177         return 0;
11178 }
11179
11180 static bool use_mmio_flip(struct intel_engine_cs *ring,
11181                           struct drm_i915_gem_object *obj)
11182 {
11183         /*
11184          * This is not being used for older platforms, because
11185          * non-availability of flip done interrupt forces us to use
11186          * CS flips. Older platforms derive flip done using some clever
11187          * tricks involving the flip_pending status bits and vblank irqs.
11188          * So using MMIO flips there would disrupt this mechanism.
11189          */
11190
11191         if (ring == NULL)
11192                 return true;
11193
11194         if (INTEL_INFO(ring->dev)->gen < 5)
11195                 return false;
11196
11197         if (i915.use_mmio_flip < 0)
11198                 return false;
11199         else if (i915.use_mmio_flip > 0)
11200                 return true;
11201         else if (i915.enable_execlists)
11202                 return true;
11203         else if (obj->base.dma_buf &&
11204                  !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11205                                                        false))
11206                 return true;
11207         else
11208                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11209 }
11210
11211 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11212                              unsigned int rotation,
11213                              struct intel_unpin_work *work)
11214 {
11215         struct drm_device *dev = intel_crtc->base.dev;
11216         struct drm_i915_private *dev_priv = dev->dev_private;
11217         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11218         const enum pipe pipe = intel_crtc->pipe;
11219         u32 ctl, stride, tile_height;
11220
11221         ctl = I915_READ(PLANE_CTL(pipe, 0));
11222         ctl &= ~PLANE_CTL_TILED_MASK;
11223         switch (fb->modifier[0]) {
11224         case DRM_FORMAT_MOD_NONE:
11225                 break;
11226         case I915_FORMAT_MOD_X_TILED:
11227                 ctl |= PLANE_CTL_TILED_X;
11228                 break;
11229         case I915_FORMAT_MOD_Y_TILED:
11230                 ctl |= PLANE_CTL_TILED_Y;
11231                 break;
11232         case I915_FORMAT_MOD_Yf_TILED:
11233                 ctl |= PLANE_CTL_TILED_YF;
11234                 break;
11235         default:
11236                 MISSING_CASE(fb->modifier[0]);
11237         }
11238
11239         /*
11240          * The stride is either expressed as a multiple of 64 bytes chunks for
11241          * linear buffers or in number of tiles for tiled buffers.
11242          */
11243         if (intel_rotation_90_or_270(rotation)) {
11244                 /* stride = Surface height in tiles */
11245                 tile_height = intel_tile_height(dev, fb->pixel_format,
11246                                                 fb->modifier[0], 0);
11247                 stride = DIV_ROUND_UP(fb->height, tile_height);
11248         } else {
11249                 stride = fb->pitches[0] /
11250                                 intel_fb_stride_alignment(dev, fb->modifier[0],
11251                                                           fb->pixel_format);
11252         }
11253
11254         /*
11255          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11256          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11257          */
11258         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11259         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11260
11261         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11262         POSTING_READ(PLANE_SURF(pipe, 0));
11263 }
11264
11265 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11266                              struct intel_unpin_work *work)
11267 {
11268         struct drm_device *dev = intel_crtc->base.dev;
11269         struct drm_i915_private *dev_priv = dev->dev_private;
11270         struct intel_framebuffer *intel_fb =
11271                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11272         struct drm_i915_gem_object *obj = intel_fb->obj;
11273         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11274         u32 dspcntr;
11275
11276         dspcntr = I915_READ(reg);
11277
11278         if (obj->tiling_mode != I915_TILING_NONE)
11279                 dspcntr |= DISPPLANE_TILED;
11280         else
11281                 dspcntr &= ~DISPPLANE_TILED;
11282
11283         I915_WRITE(reg, dspcntr);
11284
11285         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11286         POSTING_READ(DSPSURF(intel_crtc->plane));
11287 }
11288
11289 /*
11290  * XXX: This is the temporary way to update the plane registers until we get
11291  * around to using the usual plane update functions for MMIO flips
11292  */
11293 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11294 {
11295         struct intel_crtc *crtc = mmio_flip->crtc;
11296         struct intel_unpin_work *work;
11297
11298         spin_lock_irq(&crtc->base.dev->event_lock);
11299         work = crtc->unpin_work;
11300         spin_unlock_irq(&crtc->base.dev->event_lock);
11301         if (work == NULL)
11302                 return;
11303
11304         intel_mark_page_flip_active(work);
11305
11306         intel_pipe_update_start(crtc);
11307
11308         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11309                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11310         else
11311                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11312                 ilk_do_mmio_flip(crtc, work);
11313
11314         intel_pipe_update_end(crtc);
11315 }
11316
11317 static void intel_mmio_flip_work_func(struct work_struct *work)
11318 {
11319         struct intel_mmio_flip *mmio_flip =
11320                 container_of(work, struct intel_mmio_flip, work);
11321         struct intel_framebuffer *intel_fb =
11322                 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11323         struct drm_i915_gem_object *obj = intel_fb->obj;
11324
11325         if (mmio_flip->req) {
11326                 WARN_ON(__i915_wait_request(mmio_flip->req,
11327                                             mmio_flip->crtc->reset_counter,
11328                                             false, NULL,
11329                                             &mmio_flip->i915->rps.mmioflips));
11330                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11331         }
11332
11333         /* For framebuffer backed by dmabuf, wait for fence */
11334         if (obj->base.dma_buf)
11335                 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11336                                                             false, false,
11337                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11338
11339         intel_do_mmio_flip(mmio_flip);
11340         kfree(mmio_flip);
11341 }
11342
11343 static int intel_queue_mmio_flip(struct drm_device *dev,
11344                                  struct drm_crtc *crtc,
11345                                  struct drm_i915_gem_object *obj)
11346 {
11347         struct intel_mmio_flip *mmio_flip;
11348
11349         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11350         if (mmio_flip == NULL)
11351                 return -ENOMEM;
11352
11353         mmio_flip->i915 = to_i915(dev);
11354         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11355         mmio_flip->crtc = to_intel_crtc(crtc);
11356         mmio_flip->rotation = crtc->primary->state->rotation;
11357
11358         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11359         schedule_work(&mmio_flip->work);
11360
11361         return 0;
11362 }
11363
11364 static int intel_default_queue_flip(struct drm_device *dev,
11365                                     struct drm_crtc *crtc,
11366                                     struct drm_framebuffer *fb,
11367                                     struct drm_i915_gem_object *obj,
11368                                     struct drm_i915_gem_request *req,
11369                                     uint32_t flags)
11370 {
11371         return -ENODEV;
11372 }
11373
11374 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11375                                          struct drm_crtc *crtc)
11376 {
11377         struct drm_i915_private *dev_priv = dev->dev_private;
11378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11379         struct intel_unpin_work *work = intel_crtc->unpin_work;
11380         u32 addr;
11381
11382         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11383                 return true;
11384
11385         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11386                 return false;
11387
11388         if (!work->enable_stall_check)
11389                 return false;
11390
11391         if (work->flip_ready_vblank == 0) {
11392                 if (work->flip_queued_req &&
11393                     !i915_gem_request_completed(work->flip_queued_req, true))
11394                         return false;
11395
11396                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11397         }
11398
11399         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11400                 return false;
11401
11402         /* Potential stall - if we see that the flip has happened,
11403          * assume a missed interrupt. */
11404         if (INTEL_INFO(dev)->gen >= 4)
11405                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11406         else
11407                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11408
11409         /* There is a potential issue here with a false positive after a flip
11410          * to the same address. We could address this by checking for a
11411          * non-incrementing frame counter.
11412          */
11413         return addr == work->gtt_offset;
11414 }
11415
11416 void intel_check_page_flip(struct drm_device *dev, int pipe)
11417 {
11418         struct drm_i915_private *dev_priv = dev->dev_private;
11419         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11421         struct intel_unpin_work *work;
11422
11423         WARN_ON(!in_interrupt());
11424
11425         if (crtc == NULL)
11426                 return;
11427
11428         spin_lock(&dev->event_lock);
11429         work = intel_crtc->unpin_work;
11430         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11431                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11432                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11433                 page_flip_completed(intel_crtc);
11434                 work = NULL;
11435         }
11436         if (work != NULL &&
11437             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11438                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11439         spin_unlock(&dev->event_lock);
11440 }
11441
11442 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11443                                 struct drm_framebuffer *fb,
11444                                 struct drm_pending_vblank_event *event,
11445                                 uint32_t page_flip_flags)
11446 {
11447         struct drm_device *dev = crtc->dev;
11448         struct drm_i915_private *dev_priv = dev->dev_private;
11449         struct drm_framebuffer *old_fb = crtc->primary->fb;
11450         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11452         struct drm_plane *primary = crtc->primary;
11453         enum pipe pipe = intel_crtc->pipe;
11454         struct intel_unpin_work *work;
11455         struct intel_engine_cs *ring;
11456         bool mmio_flip;
11457         struct drm_i915_gem_request *request = NULL;
11458         int ret;
11459
11460         /*
11461          * drm_mode_page_flip_ioctl() should already catch this, but double
11462          * check to be safe.  In the future we may enable pageflipping from
11463          * a disabled primary plane.
11464          */
11465         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11466                 return -EBUSY;
11467
11468         /* Can't change pixel format via MI display flips. */
11469         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11470                 return -EINVAL;
11471
11472         /*
11473          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11474          * Note that pitch changes could also affect these register.
11475          */
11476         if (INTEL_INFO(dev)->gen > 3 &&
11477             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11478              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11479                 return -EINVAL;
11480
11481         if (i915_terminally_wedged(&dev_priv->gpu_error))
11482                 goto out_hang;
11483
11484         work = kzalloc(sizeof(*work), GFP_KERNEL);
11485         if (work == NULL)
11486                 return -ENOMEM;
11487
11488         work->event = event;
11489         work->crtc = crtc;
11490         work->old_fb = old_fb;
11491         INIT_WORK(&work->work, intel_unpin_work_fn);
11492
11493         ret = drm_crtc_vblank_get(crtc);
11494         if (ret)
11495                 goto free_work;
11496
11497         /* We borrow the event spin lock for protecting unpin_work */
11498         spin_lock_irq(&dev->event_lock);
11499         if (intel_crtc->unpin_work) {
11500                 /* Before declaring the flip queue wedged, check if
11501                  * the hardware completed the operation behind our backs.
11502                  */
11503                 if (__intel_pageflip_stall_check(dev, crtc)) {
11504                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11505                         page_flip_completed(intel_crtc);
11506                 } else {
11507                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11508                         spin_unlock_irq(&dev->event_lock);
11509
11510                         drm_crtc_vblank_put(crtc);
11511                         kfree(work);
11512                         return -EBUSY;
11513                 }
11514         }
11515         intel_crtc->unpin_work = work;
11516         spin_unlock_irq(&dev->event_lock);
11517
11518         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11519                 flush_workqueue(dev_priv->wq);
11520
11521         /* Reference the objects for the scheduled work. */
11522         drm_framebuffer_reference(work->old_fb);
11523         drm_gem_object_reference(&obj->base);
11524
11525         crtc->primary->fb = fb;
11526         update_state_fb(crtc->primary);
11527
11528         work->pending_flip_obj = obj;
11529
11530         ret = i915_mutex_lock_interruptible(dev);
11531         if (ret)
11532                 goto cleanup;
11533
11534         atomic_inc(&intel_crtc->unpin_work_count);
11535         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11536
11537         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11538                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11539
11540         if (IS_VALLEYVIEW(dev)) {
11541                 ring = &dev_priv->ring[BCS];
11542                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11543                         /* vlv: DISPLAY_FLIP fails to change tiling */
11544                         ring = NULL;
11545         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11546                 ring = &dev_priv->ring[BCS];
11547         } else if (INTEL_INFO(dev)->gen >= 7) {
11548                 ring = i915_gem_request_get_ring(obj->last_write_req);
11549                 if (ring == NULL || ring->id != RCS)
11550                         ring = &dev_priv->ring[BCS];
11551         } else {
11552                 ring = &dev_priv->ring[RCS];
11553         }
11554
11555         mmio_flip = use_mmio_flip(ring, obj);
11556
11557         /* When using CS flips, we want to emit semaphores between rings.
11558          * However, when using mmio flips we will create a task to do the
11559          * synchronisation, so all we want here is to pin the framebuffer
11560          * into the display plane and skip any waits.
11561          */
11562         if (!mmio_flip) {
11563                 ret = i915_gem_object_sync(obj, ring, &request);
11564                 if (ret)
11565                         goto cleanup_pending;
11566         }
11567
11568         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11569                                          crtc->primary->state);
11570         if (ret)
11571                 goto cleanup_pending;
11572
11573         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11574                                                   obj, 0);
11575         work->gtt_offset += intel_crtc->dspaddr_offset;
11576
11577         if (mmio_flip) {
11578                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11579                 if (ret)
11580                         goto cleanup_unpin;
11581
11582                 i915_gem_request_assign(&work->flip_queued_req,
11583                                         obj->last_write_req);
11584         } else {
11585                 if (!request) {
11586                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11587                         if (ret)
11588                                 goto cleanup_unpin;
11589                 }
11590
11591                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11592                                                    page_flip_flags);
11593                 if (ret)
11594                         goto cleanup_unpin;
11595
11596                 i915_gem_request_assign(&work->flip_queued_req, request);
11597         }
11598
11599         if (request)
11600                 i915_add_request_no_flush(request);
11601
11602         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11603         work->enable_stall_check = true;
11604
11605         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11606                           to_intel_plane(primary)->frontbuffer_bit);
11607         mutex_unlock(&dev->struct_mutex);
11608
11609         intel_fbc_deactivate(intel_crtc);
11610         intel_frontbuffer_flip_prepare(dev,
11611                                        to_intel_plane(primary)->frontbuffer_bit);
11612
11613         trace_i915_flip_request(intel_crtc->plane, obj);
11614
11615         return 0;
11616
11617 cleanup_unpin:
11618         intel_unpin_fb_obj(fb, crtc->primary->state);
11619 cleanup_pending:
11620         if (request)
11621                 i915_gem_request_cancel(request);
11622         atomic_dec(&intel_crtc->unpin_work_count);
11623         mutex_unlock(&dev->struct_mutex);
11624 cleanup:
11625         crtc->primary->fb = old_fb;
11626         update_state_fb(crtc->primary);
11627
11628         drm_gem_object_unreference_unlocked(&obj->base);
11629         drm_framebuffer_unreference(work->old_fb);
11630
11631         spin_lock_irq(&dev->event_lock);
11632         intel_crtc->unpin_work = NULL;
11633         spin_unlock_irq(&dev->event_lock);
11634
11635         drm_crtc_vblank_put(crtc);
11636 free_work:
11637         kfree(work);
11638
11639         if (ret == -EIO) {
11640                 struct drm_atomic_state *state;
11641                 struct drm_plane_state *plane_state;
11642
11643 out_hang:
11644                 state = drm_atomic_state_alloc(dev);
11645                 if (!state)
11646                         return -ENOMEM;
11647                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11648
11649 retry:
11650                 plane_state = drm_atomic_get_plane_state(state, primary);
11651                 ret = PTR_ERR_OR_ZERO(plane_state);
11652                 if (!ret) {
11653                         drm_atomic_set_fb_for_plane(plane_state, fb);
11654
11655                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11656                         if (!ret)
11657                                 ret = drm_atomic_commit(state);
11658                 }
11659
11660                 if (ret == -EDEADLK) {
11661                         drm_modeset_backoff(state->acquire_ctx);
11662                         drm_atomic_state_clear(state);
11663                         goto retry;
11664                 }
11665
11666                 if (ret)
11667                         drm_atomic_state_free(state);
11668
11669                 if (ret == 0 && event) {
11670                         spin_lock_irq(&dev->event_lock);
11671                         drm_send_vblank_event(dev, pipe, event);
11672                         spin_unlock_irq(&dev->event_lock);
11673                 }
11674         }
11675         return ret;
11676 }
11677
11678
11679 /**
11680  * intel_wm_need_update - Check whether watermarks need updating
11681  * @plane: drm plane
11682  * @state: new plane state
11683  *
11684  * Check current plane state versus the new one to determine whether
11685  * watermarks need to be recalculated.
11686  *
11687  * Returns true or false.
11688  */
11689 static bool intel_wm_need_update(struct drm_plane *plane,
11690                                  struct drm_plane_state *state)
11691 {
11692         struct intel_plane_state *new = to_intel_plane_state(state);
11693         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11694
11695         /* Update watermarks on tiling or size changes. */
11696         if (!plane->state->fb || !state->fb ||
11697             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11698             plane->state->rotation != state->rotation ||
11699             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11700             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11701             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11702             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11703                 return true;
11704
11705         return false;
11706 }
11707
11708 static bool needs_scaling(struct intel_plane_state *state)
11709 {
11710         int src_w = drm_rect_width(&state->src) >> 16;
11711         int src_h = drm_rect_height(&state->src) >> 16;
11712         int dst_w = drm_rect_width(&state->dst);
11713         int dst_h = drm_rect_height(&state->dst);
11714
11715         return (src_w != dst_w || src_h != dst_h);
11716 }
11717
11718 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11719                                     struct drm_plane_state *plane_state)
11720 {
11721         struct drm_crtc *crtc = crtc_state->crtc;
11722         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11723         struct drm_plane *plane = plane_state->plane;
11724         struct drm_device *dev = crtc->dev;
11725         struct drm_i915_private *dev_priv = dev->dev_private;
11726         struct intel_plane_state *old_plane_state =
11727                 to_intel_plane_state(plane->state);
11728         int idx = intel_crtc->base.base.id, ret;
11729         int i = drm_plane_index(plane);
11730         bool mode_changed = needs_modeset(crtc_state);
11731         bool was_crtc_enabled = crtc->state->active;
11732         bool is_crtc_enabled = crtc_state->active;
11733         bool turn_off, turn_on, visible, was_visible;
11734         struct drm_framebuffer *fb = plane_state->fb;
11735
11736         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11737             plane->type != DRM_PLANE_TYPE_CURSOR) {
11738                 ret = skl_update_scaler_plane(
11739                         to_intel_crtc_state(crtc_state),
11740                         to_intel_plane_state(plane_state));
11741                 if (ret)
11742                         return ret;
11743         }
11744
11745         was_visible = old_plane_state->visible;
11746         visible = to_intel_plane_state(plane_state)->visible;
11747
11748         if (!was_crtc_enabled && WARN_ON(was_visible))
11749                 was_visible = false;
11750
11751         if (!is_crtc_enabled && WARN_ON(visible))
11752                 visible = false;
11753
11754         if (!was_visible && !visible)
11755                 return 0;
11756
11757         turn_off = was_visible && (!visible || mode_changed);
11758         turn_on = visible && (!was_visible || mode_changed);
11759
11760         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11761                          plane->base.id, fb ? fb->base.id : -1);
11762
11763         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11764                          plane->base.id, was_visible, visible,
11765                          turn_off, turn_on, mode_changed);
11766
11767         if (turn_on) {
11768                 intel_crtc->atomic.update_wm_pre = true;
11769                 /* must disable cxsr around plane enable/disable */
11770                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11771                         intel_crtc->atomic.disable_cxsr = true;
11772                         /* to potentially re-enable cxsr */
11773                         intel_crtc->atomic.wait_vblank = true;
11774                         intel_crtc->atomic.update_wm_post = true;
11775                 }
11776         } else if (turn_off) {
11777                 intel_crtc->atomic.update_wm_post = true;
11778                 /* must disable cxsr around plane enable/disable */
11779                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11780                         if (is_crtc_enabled)
11781                                 intel_crtc->atomic.wait_vblank = true;
11782                         intel_crtc->atomic.disable_cxsr = true;
11783                 }
11784         } else if (intel_wm_need_update(plane, plane_state)) {
11785                 intel_crtc->atomic.update_wm_pre = true;
11786         }
11787
11788         if (visible || was_visible)
11789                 intel_crtc->atomic.fb_bits |=
11790                         to_intel_plane(plane)->frontbuffer_bit;
11791
11792         switch (plane->type) {
11793         case DRM_PLANE_TYPE_PRIMARY:
11794                 intel_crtc->atomic.pre_disable_primary = turn_off;
11795                 intel_crtc->atomic.post_enable_primary = turn_on;
11796
11797                 if (turn_off) {
11798                         /*
11799                          * FIXME: Actually if we will still have any other
11800                          * plane enabled on the pipe we could let IPS enabled
11801                          * still, but for now lets consider that when we make
11802                          * primary invisible by setting DSPCNTR to 0 on
11803                          * update_primary_plane function IPS needs to be
11804                          * disable.
11805                          */
11806                         intel_crtc->atomic.disable_ips = true;
11807
11808                         intel_crtc->atomic.disable_fbc = true;
11809                 }
11810
11811                 /*
11812                  * FBC does not work on some platforms for rotated
11813                  * planes, so disable it when rotation is not 0 and
11814                  * update it when rotation is set back to 0.
11815                  *
11816                  * FIXME: This is redundant with the fbc update done in
11817                  * the primary plane enable function except that that
11818                  * one is done too late. We eventually need to unify
11819                  * this.
11820                  */
11821
11822                 if (visible &&
11823                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11824                     dev_priv->fbc.crtc == intel_crtc &&
11825                     plane_state->rotation != BIT(DRM_ROTATE_0))
11826                         intel_crtc->atomic.disable_fbc = true;
11827
11828                 /*
11829                  * BDW signals flip done immediately if the plane
11830                  * is disabled, even if the plane enable is already
11831                  * armed to occur at the next vblank :(
11832                  */
11833                 if (turn_on && IS_BROADWELL(dev))
11834                         intel_crtc->atomic.wait_vblank = true;
11835
11836                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11837                 break;
11838         case DRM_PLANE_TYPE_CURSOR:
11839                 break;
11840         case DRM_PLANE_TYPE_OVERLAY:
11841                 /*
11842                  * WaCxSRDisabledForSpriteScaling:ivb
11843                  *
11844                  * cstate->update_wm was already set above, so this flag will
11845                  * take effect when we commit and program watermarks.
11846                  */
11847                 if (IS_IVYBRIDGE(dev) &&
11848                     needs_scaling(to_intel_plane_state(plane_state)) &&
11849                     !needs_scaling(old_plane_state)) {
11850                         to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11851                 } else if (turn_off && !mode_changed) {
11852                         intel_crtc->atomic.wait_vblank = true;
11853                         intel_crtc->atomic.update_sprite_watermarks |=
11854                                 1 << i;
11855                 }
11856
11857                 break;
11858         }
11859         return 0;
11860 }
11861
11862 static bool encoders_cloneable(const struct intel_encoder *a,
11863                                const struct intel_encoder *b)
11864 {
11865         /* masks could be asymmetric, so check both ways */
11866         return a == b || (a->cloneable & (1 << b->type) &&
11867                           b->cloneable & (1 << a->type));
11868 }
11869
11870 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11871                                          struct intel_crtc *crtc,
11872                                          struct intel_encoder *encoder)
11873 {
11874         struct intel_encoder *source_encoder;
11875         struct drm_connector *connector;
11876         struct drm_connector_state *connector_state;
11877         int i;
11878
11879         for_each_connector_in_state(state, connector, connector_state, i) {
11880                 if (connector_state->crtc != &crtc->base)
11881                         continue;
11882
11883                 source_encoder =
11884                         to_intel_encoder(connector_state->best_encoder);
11885                 if (!encoders_cloneable(encoder, source_encoder))
11886                         return false;
11887         }
11888
11889         return true;
11890 }
11891
11892 static bool check_encoder_cloning(struct drm_atomic_state *state,
11893                                   struct intel_crtc *crtc)
11894 {
11895         struct intel_encoder *encoder;
11896         struct drm_connector *connector;
11897         struct drm_connector_state *connector_state;
11898         int i;
11899
11900         for_each_connector_in_state(state, connector, connector_state, i) {
11901                 if (connector_state->crtc != &crtc->base)
11902                         continue;
11903
11904                 encoder = to_intel_encoder(connector_state->best_encoder);
11905                 if (!check_single_encoder_cloning(state, crtc, encoder))
11906                         return false;
11907         }
11908
11909         return true;
11910 }
11911
11912 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11913                                    struct drm_crtc_state *crtc_state)
11914 {
11915         struct drm_device *dev = crtc->dev;
11916         struct drm_i915_private *dev_priv = dev->dev_private;
11917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11918         struct intel_crtc_state *pipe_config =
11919                 to_intel_crtc_state(crtc_state);
11920         struct drm_atomic_state *state = crtc_state->state;
11921         int ret;
11922         bool mode_changed = needs_modeset(crtc_state);
11923
11924         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11925                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11926                 return -EINVAL;
11927         }
11928
11929         if (mode_changed && !crtc_state->active)
11930                 intel_crtc->atomic.update_wm_post = true;
11931
11932         if (mode_changed && crtc_state->enable &&
11933             dev_priv->display.crtc_compute_clock &&
11934             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11935                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11936                                                            pipe_config);
11937                 if (ret)
11938                         return ret;
11939         }
11940
11941         ret = 0;
11942         if (dev_priv->display.compute_pipe_wm) {
11943                 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
11944                 if (ret)
11945                         return ret;
11946         }
11947
11948         if (INTEL_INFO(dev)->gen >= 9) {
11949                 if (mode_changed)
11950                         ret = skl_update_scaler_crtc(pipe_config);
11951
11952                 if (!ret)
11953                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11954                                                          pipe_config);
11955         }
11956
11957         return ret;
11958 }
11959
11960 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11961         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11962         .load_lut = intel_crtc_load_lut,
11963         .atomic_begin = intel_begin_crtc_commit,
11964         .atomic_flush = intel_finish_crtc_commit,
11965         .atomic_check = intel_crtc_atomic_check,
11966 };
11967
11968 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11969 {
11970         struct intel_connector *connector;
11971
11972         for_each_intel_connector(dev, connector) {
11973                 if (connector->base.encoder) {
11974                         connector->base.state->best_encoder =
11975                                 connector->base.encoder;
11976                         connector->base.state->crtc =
11977                                 connector->base.encoder->crtc;
11978                 } else {
11979                         connector->base.state->best_encoder = NULL;
11980                         connector->base.state->crtc = NULL;
11981                 }
11982         }
11983 }
11984
11985 static void
11986 connected_sink_compute_bpp(struct intel_connector *connector,
11987                            struct intel_crtc_state *pipe_config)
11988 {
11989         int bpp = pipe_config->pipe_bpp;
11990
11991         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11992                 connector->base.base.id,
11993                 connector->base.name);
11994
11995         /* Don't use an invalid EDID bpc value */
11996         if (connector->base.display_info.bpc &&
11997             connector->base.display_info.bpc * 3 < bpp) {
11998                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11999                               bpp, connector->base.display_info.bpc*3);
12000                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12001         }
12002
12003         /* Clamp bpp to 8 on screens without EDID 1.4 */
12004         if (connector->base.display_info.bpc == 0 && bpp > 24) {
12005                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12006                               bpp);
12007                 pipe_config->pipe_bpp = 24;
12008         }
12009 }
12010
12011 static int
12012 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12013                           struct intel_crtc_state *pipe_config)
12014 {
12015         struct drm_device *dev = crtc->base.dev;
12016         struct drm_atomic_state *state;
12017         struct drm_connector *connector;
12018         struct drm_connector_state *connector_state;
12019         int bpp, i;
12020
12021         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
12022                 bpp = 10*3;
12023         else if (INTEL_INFO(dev)->gen >= 5)
12024                 bpp = 12*3;
12025         else
12026                 bpp = 8*3;
12027
12028
12029         pipe_config->pipe_bpp = bpp;
12030
12031         state = pipe_config->base.state;
12032
12033         /* Clamp display bpp to EDID value */
12034         for_each_connector_in_state(state, connector, connector_state, i) {
12035                 if (connector_state->crtc != &crtc->base)
12036                         continue;
12037
12038                 connected_sink_compute_bpp(to_intel_connector(connector),
12039                                            pipe_config);
12040         }
12041
12042         return bpp;
12043 }
12044
12045 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12046 {
12047         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12048                         "type: 0x%x flags: 0x%x\n",
12049                 mode->crtc_clock,
12050                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12051                 mode->crtc_hsync_end, mode->crtc_htotal,
12052                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12053                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12054 }
12055
12056 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12057                                    struct intel_crtc_state *pipe_config,
12058                                    const char *context)
12059 {
12060         struct drm_device *dev = crtc->base.dev;
12061         struct drm_plane *plane;
12062         struct intel_plane *intel_plane;
12063         struct intel_plane_state *state;
12064         struct drm_framebuffer *fb;
12065
12066         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12067                       context, pipe_config, pipe_name(crtc->pipe));
12068
12069         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12070         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12071                       pipe_config->pipe_bpp, pipe_config->dither);
12072         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12073                       pipe_config->has_pch_encoder,
12074                       pipe_config->fdi_lanes,
12075                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12076                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12077                       pipe_config->fdi_m_n.tu);
12078         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12079                       pipe_config->has_dp_encoder,
12080                       pipe_config->lane_count,
12081                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12082                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12083                       pipe_config->dp_m_n.tu);
12084
12085         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12086                       pipe_config->has_dp_encoder,
12087                       pipe_config->lane_count,
12088                       pipe_config->dp_m2_n2.gmch_m,
12089                       pipe_config->dp_m2_n2.gmch_n,
12090                       pipe_config->dp_m2_n2.link_m,
12091                       pipe_config->dp_m2_n2.link_n,
12092                       pipe_config->dp_m2_n2.tu);
12093
12094         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12095                       pipe_config->has_audio,
12096                       pipe_config->has_infoframe);
12097
12098         DRM_DEBUG_KMS("requested mode:\n");
12099         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12100         DRM_DEBUG_KMS("adjusted mode:\n");
12101         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12102         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12103         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12104         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12105                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12106         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12107                       crtc->num_scalers,
12108                       pipe_config->scaler_state.scaler_users,
12109                       pipe_config->scaler_state.scaler_id);
12110         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12111                       pipe_config->gmch_pfit.control,
12112                       pipe_config->gmch_pfit.pgm_ratios,
12113                       pipe_config->gmch_pfit.lvds_border_bits);
12114         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12115                       pipe_config->pch_pfit.pos,
12116                       pipe_config->pch_pfit.size,
12117                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12118         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12119         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12120
12121         if (IS_BROXTON(dev)) {
12122                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12123                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12124                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12125                               pipe_config->ddi_pll_sel,
12126                               pipe_config->dpll_hw_state.ebb0,
12127                               pipe_config->dpll_hw_state.ebb4,
12128                               pipe_config->dpll_hw_state.pll0,
12129                               pipe_config->dpll_hw_state.pll1,
12130                               pipe_config->dpll_hw_state.pll2,
12131                               pipe_config->dpll_hw_state.pll3,
12132                               pipe_config->dpll_hw_state.pll6,
12133                               pipe_config->dpll_hw_state.pll8,
12134                               pipe_config->dpll_hw_state.pll9,
12135                               pipe_config->dpll_hw_state.pll10,
12136                               pipe_config->dpll_hw_state.pcsdw12);
12137         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12138                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12139                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12140                               pipe_config->ddi_pll_sel,
12141                               pipe_config->dpll_hw_state.ctrl1,
12142                               pipe_config->dpll_hw_state.cfgcr1,
12143                               pipe_config->dpll_hw_state.cfgcr2);
12144         } else if (HAS_DDI(dev)) {
12145                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12146                               pipe_config->ddi_pll_sel,
12147                               pipe_config->dpll_hw_state.wrpll,
12148                               pipe_config->dpll_hw_state.spll);
12149         } else {
12150                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12151                               "fp0: 0x%x, fp1: 0x%x\n",
12152                               pipe_config->dpll_hw_state.dpll,
12153                               pipe_config->dpll_hw_state.dpll_md,
12154                               pipe_config->dpll_hw_state.fp0,
12155                               pipe_config->dpll_hw_state.fp1);
12156         }
12157
12158         DRM_DEBUG_KMS("planes on this crtc\n");
12159         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12160                 intel_plane = to_intel_plane(plane);
12161                 if (intel_plane->pipe != crtc->pipe)
12162                         continue;
12163
12164                 state = to_intel_plane_state(plane->state);
12165                 fb = state->base.fb;
12166                 if (!fb) {
12167                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12168                                 "disabled, scaler_id = %d\n",
12169                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12170                                 plane->base.id, intel_plane->pipe,
12171                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12172                                 drm_plane_index(plane), state->scaler_id);
12173                         continue;
12174                 }
12175
12176                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12177                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12178                         plane->base.id, intel_plane->pipe,
12179                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12180                         drm_plane_index(plane));
12181                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12182                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12183                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12184                         state->scaler_id,
12185                         state->src.x1 >> 16, state->src.y1 >> 16,
12186                         drm_rect_width(&state->src) >> 16,
12187                         drm_rect_height(&state->src) >> 16,
12188                         state->dst.x1, state->dst.y1,
12189                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12190         }
12191 }
12192
12193 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12194 {
12195         struct drm_device *dev = state->dev;
12196         struct intel_encoder *encoder;
12197         struct drm_connector *connector;
12198         struct drm_connector_state *connector_state;
12199         unsigned int used_ports = 0;
12200         int i;
12201
12202         /*
12203          * Walk the connector list instead of the encoder
12204          * list to detect the problem on ddi platforms
12205          * where there's just one encoder per digital port.
12206          */
12207         for_each_connector_in_state(state, connector, connector_state, i) {
12208                 if (!connector_state->best_encoder)
12209                         continue;
12210
12211                 encoder = to_intel_encoder(connector_state->best_encoder);
12212
12213                 WARN_ON(!connector_state->crtc);
12214
12215                 switch (encoder->type) {
12216                         unsigned int port_mask;
12217                 case INTEL_OUTPUT_UNKNOWN:
12218                         if (WARN_ON(!HAS_DDI(dev)))
12219                                 break;
12220                 case INTEL_OUTPUT_DISPLAYPORT:
12221                 case INTEL_OUTPUT_HDMI:
12222                 case INTEL_OUTPUT_EDP:
12223                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12224
12225                         /* the same port mustn't appear more than once */
12226                         if (used_ports & port_mask)
12227                                 return false;
12228
12229                         used_ports |= port_mask;
12230                 default:
12231                         break;
12232                 }
12233         }
12234
12235         return true;
12236 }
12237
12238 static void
12239 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12240 {
12241         struct drm_crtc_state tmp_state;
12242         struct intel_crtc_scaler_state scaler_state;
12243         struct intel_dpll_hw_state dpll_hw_state;
12244         enum intel_dpll_id shared_dpll;
12245         uint32_t ddi_pll_sel;
12246         bool force_thru;
12247
12248         /* FIXME: before the switch to atomic started, a new pipe_config was
12249          * kzalloc'd. Code that depends on any field being zero should be
12250          * fixed, so that the crtc_state can be safely duplicated. For now,
12251          * only fields that are know to not cause problems are preserved. */
12252
12253         tmp_state = crtc_state->base;
12254         scaler_state = crtc_state->scaler_state;
12255         shared_dpll = crtc_state->shared_dpll;
12256         dpll_hw_state = crtc_state->dpll_hw_state;
12257         ddi_pll_sel = crtc_state->ddi_pll_sel;
12258         force_thru = crtc_state->pch_pfit.force_thru;
12259
12260         memset(crtc_state, 0, sizeof *crtc_state);
12261
12262         crtc_state->base = tmp_state;
12263         crtc_state->scaler_state = scaler_state;
12264         crtc_state->shared_dpll = shared_dpll;
12265         crtc_state->dpll_hw_state = dpll_hw_state;
12266         crtc_state->ddi_pll_sel = ddi_pll_sel;
12267         crtc_state->pch_pfit.force_thru = force_thru;
12268 }
12269
12270 static int
12271 intel_modeset_pipe_config(struct drm_crtc *crtc,
12272                           struct intel_crtc_state *pipe_config)
12273 {
12274         struct drm_atomic_state *state = pipe_config->base.state;
12275         struct intel_encoder *encoder;
12276         struct drm_connector *connector;
12277         struct drm_connector_state *connector_state;
12278         int base_bpp, ret = -EINVAL;
12279         int i;
12280         bool retry = true;
12281
12282         clear_intel_crtc_state(pipe_config);
12283
12284         pipe_config->cpu_transcoder =
12285                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12286
12287         /*
12288          * Sanitize sync polarity flags based on requested ones. If neither
12289          * positive or negative polarity is requested, treat this as meaning
12290          * negative polarity.
12291          */
12292         if (!(pipe_config->base.adjusted_mode.flags &
12293               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12294                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12295
12296         if (!(pipe_config->base.adjusted_mode.flags &
12297               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12298                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12299
12300         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12301                                              pipe_config);
12302         if (base_bpp < 0)
12303                 goto fail;
12304
12305         /*
12306          * Determine the real pipe dimensions. Note that stereo modes can
12307          * increase the actual pipe size due to the frame doubling and
12308          * insertion of additional space for blanks between the frame. This
12309          * is stored in the crtc timings. We use the requested mode to do this
12310          * computation to clearly distinguish it from the adjusted mode, which
12311          * can be changed by the connectors in the below retry loop.
12312          */
12313         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12314                                &pipe_config->pipe_src_w,
12315                                &pipe_config->pipe_src_h);
12316
12317 encoder_retry:
12318         /* Ensure the port clock defaults are reset when retrying. */
12319         pipe_config->port_clock = 0;
12320         pipe_config->pixel_multiplier = 1;
12321
12322         /* Fill in default crtc timings, allow encoders to overwrite them. */
12323         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12324                               CRTC_STEREO_DOUBLE);
12325
12326         /* Pass our mode to the connectors and the CRTC to give them a chance to
12327          * adjust it according to limitations or connector properties, and also
12328          * a chance to reject the mode entirely.
12329          */
12330         for_each_connector_in_state(state, connector, connector_state, i) {
12331                 if (connector_state->crtc != crtc)
12332                         continue;
12333
12334                 encoder = to_intel_encoder(connector_state->best_encoder);
12335
12336                 if (!(encoder->compute_config(encoder, pipe_config))) {
12337                         DRM_DEBUG_KMS("Encoder config failure\n");
12338                         goto fail;
12339                 }
12340         }
12341
12342         /* Set default port clock if not overwritten by the encoder. Needs to be
12343          * done afterwards in case the encoder adjusts the mode. */
12344         if (!pipe_config->port_clock)
12345                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12346                         * pipe_config->pixel_multiplier;
12347
12348         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12349         if (ret < 0) {
12350                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12351                 goto fail;
12352         }
12353
12354         if (ret == RETRY) {
12355                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12356                         ret = -EINVAL;
12357                         goto fail;
12358                 }
12359
12360                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12361                 retry = false;
12362                 goto encoder_retry;
12363         }
12364
12365         /* Dithering seems to not pass-through bits correctly when it should, so
12366          * only enable it on 6bpc panels. */
12367         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12368         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12369                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12370
12371 fail:
12372         return ret;
12373 }
12374
12375 static void
12376 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12377 {
12378         struct drm_crtc *crtc;
12379         struct drm_crtc_state *crtc_state;
12380         int i;
12381
12382         /* Double check state. */
12383         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12384                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12385
12386                 /* Update hwmode for vblank functions */
12387                 if (crtc->state->active)
12388                         crtc->hwmode = crtc->state->adjusted_mode;
12389                 else
12390                         crtc->hwmode.crtc_clock = 0;
12391
12392                 /*
12393                  * Update legacy state to satisfy fbc code. This can
12394                  * be removed when fbc uses the atomic state.
12395                  */
12396                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12397                         struct drm_plane_state *plane_state = crtc->primary->state;
12398
12399                         crtc->primary->fb = plane_state->fb;
12400                         crtc->x = plane_state->src_x >> 16;
12401                         crtc->y = plane_state->src_y >> 16;
12402                 }
12403         }
12404 }
12405
12406 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12407 {
12408         int diff;
12409
12410         if (clock1 == clock2)
12411                 return true;
12412
12413         if (!clock1 || !clock2)
12414                 return false;
12415
12416         diff = abs(clock1 - clock2);
12417
12418         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12419                 return true;
12420
12421         return false;
12422 }
12423
12424 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12425         list_for_each_entry((intel_crtc), \
12426                             &(dev)->mode_config.crtc_list, \
12427                             base.head) \
12428                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12429
12430 static bool
12431 intel_compare_m_n(unsigned int m, unsigned int n,
12432                   unsigned int m2, unsigned int n2,
12433                   bool exact)
12434 {
12435         if (m == m2 && n == n2)
12436                 return true;
12437
12438         if (exact || !m || !n || !m2 || !n2)
12439                 return false;
12440
12441         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12442
12443         if (m > m2) {
12444                 while (m > m2) {
12445                         m2 <<= 1;
12446                         n2 <<= 1;
12447                 }
12448         } else if (m < m2) {
12449                 while (m < m2) {
12450                         m <<= 1;
12451                         n <<= 1;
12452                 }
12453         }
12454
12455         return m == m2 && n == n2;
12456 }
12457
12458 static bool
12459 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12460                        struct intel_link_m_n *m2_n2,
12461                        bool adjust)
12462 {
12463         if (m_n->tu == m2_n2->tu &&
12464             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12465                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12466             intel_compare_m_n(m_n->link_m, m_n->link_n,
12467                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12468                 if (adjust)
12469                         *m2_n2 = *m_n;
12470
12471                 return true;
12472         }
12473
12474         return false;
12475 }
12476
12477 static bool
12478 intel_pipe_config_compare(struct drm_device *dev,
12479                           struct intel_crtc_state *current_config,
12480                           struct intel_crtc_state *pipe_config,
12481                           bool adjust)
12482 {
12483         bool ret = true;
12484
12485 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12486         do { \
12487                 if (!adjust) \
12488                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12489                 else \
12490                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12491         } while (0)
12492
12493 #define PIPE_CONF_CHECK_X(name) \
12494         if (current_config->name != pipe_config->name) { \
12495                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12496                           "(expected 0x%08x, found 0x%08x)\n", \
12497                           current_config->name, \
12498                           pipe_config->name); \
12499                 ret = false; \
12500         }
12501
12502 #define PIPE_CONF_CHECK_I(name) \
12503         if (current_config->name != pipe_config->name) { \
12504                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12505                           "(expected %i, found %i)\n", \
12506                           current_config->name, \
12507                           pipe_config->name); \
12508                 ret = false; \
12509         }
12510
12511 #define PIPE_CONF_CHECK_M_N(name) \
12512         if (!intel_compare_link_m_n(&current_config->name, \
12513                                     &pipe_config->name,\
12514                                     adjust)) { \
12515                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12516                           "(expected tu %i gmch %i/%i link %i/%i, " \
12517                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12518                           current_config->name.tu, \
12519                           current_config->name.gmch_m, \
12520                           current_config->name.gmch_n, \
12521                           current_config->name.link_m, \
12522                           current_config->name.link_n, \
12523                           pipe_config->name.tu, \
12524                           pipe_config->name.gmch_m, \
12525                           pipe_config->name.gmch_n, \
12526                           pipe_config->name.link_m, \
12527                           pipe_config->name.link_n); \
12528                 ret = false; \
12529         }
12530
12531 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12532         if (!intel_compare_link_m_n(&current_config->name, \
12533                                     &pipe_config->name, adjust) && \
12534             !intel_compare_link_m_n(&current_config->alt_name, \
12535                                     &pipe_config->name, adjust)) { \
12536                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12537                           "(expected tu %i gmch %i/%i link %i/%i, " \
12538                           "or tu %i gmch %i/%i link %i/%i, " \
12539                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12540                           current_config->name.tu, \
12541                           current_config->name.gmch_m, \
12542                           current_config->name.gmch_n, \
12543                           current_config->name.link_m, \
12544                           current_config->name.link_n, \
12545                           current_config->alt_name.tu, \
12546                           current_config->alt_name.gmch_m, \
12547                           current_config->alt_name.gmch_n, \
12548                           current_config->alt_name.link_m, \
12549                           current_config->alt_name.link_n, \
12550                           pipe_config->name.tu, \
12551                           pipe_config->name.gmch_m, \
12552                           pipe_config->name.gmch_n, \
12553                           pipe_config->name.link_m, \
12554                           pipe_config->name.link_n); \
12555                 ret = false; \
12556         }
12557
12558 /* This is required for BDW+ where there is only one set of registers for
12559  * switching between high and low RR.
12560  * This macro can be used whenever a comparison has to be made between one
12561  * hw state and multiple sw state variables.
12562  */
12563 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12564         if ((current_config->name != pipe_config->name) && \
12565                 (current_config->alt_name != pipe_config->name)) { \
12566                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12567                                   "(expected %i or %i, found %i)\n", \
12568                                   current_config->name, \
12569                                   current_config->alt_name, \
12570                                   pipe_config->name); \
12571                         ret = false; \
12572         }
12573
12574 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12575         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12576                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12577                           "(expected %i, found %i)\n", \
12578                           current_config->name & (mask), \
12579                           pipe_config->name & (mask)); \
12580                 ret = false; \
12581         }
12582
12583 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12584         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12585                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12586                           "(expected %i, found %i)\n", \
12587                           current_config->name, \
12588                           pipe_config->name); \
12589                 ret = false; \
12590         }
12591
12592 #define PIPE_CONF_QUIRK(quirk)  \
12593         ((current_config->quirks | pipe_config->quirks) & (quirk))
12594
12595         PIPE_CONF_CHECK_I(cpu_transcoder);
12596
12597         PIPE_CONF_CHECK_I(has_pch_encoder);
12598         PIPE_CONF_CHECK_I(fdi_lanes);
12599         PIPE_CONF_CHECK_M_N(fdi_m_n);
12600
12601         PIPE_CONF_CHECK_I(has_dp_encoder);
12602         PIPE_CONF_CHECK_I(lane_count);
12603
12604         if (INTEL_INFO(dev)->gen < 8) {
12605                 PIPE_CONF_CHECK_M_N(dp_m_n);
12606
12607                 if (current_config->has_drrs)
12608                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12609         } else
12610                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12611
12612         PIPE_CONF_CHECK_I(has_dsi_encoder);
12613
12614         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12615         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12616         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12617         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12618         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12619         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12620
12621         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12622         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12623         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12624         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12625         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12626         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12627
12628         PIPE_CONF_CHECK_I(pixel_multiplier);
12629         PIPE_CONF_CHECK_I(has_hdmi_sink);
12630         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12631             IS_VALLEYVIEW(dev))
12632                 PIPE_CONF_CHECK_I(limited_color_range);
12633         PIPE_CONF_CHECK_I(has_infoframe);
12634
12635         PIPE_CONF_CHECK_I(has_audio);
12636
12637         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12638                               DRM_MODE_FLAG_INTERLACE);
12639
12640         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12641                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12642                                       DRM_MODE_FLAG_PHSYNC);
12643                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12644                                       DRM_MODE_FLAG_NHSYNC);
12645                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12646                                       DRM_MODE_FLAG_PVSYNC);
12647                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12648                                       DRM_MODE_FLAG_NVSYNC);
12649         }
12650
12651         PIPE_CONF_CHECK_X(gmch_pfit.control);
12652         /* pfit ratios are autocomputed by the hw on gen4+ */
12653         if (INTEL_INFO(dev)->gen < 4)
12654                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12655         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12656
12657         if (!adjust) {
12658                 PIPE_CONF_CHECK_I(pipe_src_w);
12659                 PIPE_CONF_CHECK_I(pipe_src_h);
12660
12661                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12662                 if (current_config->pch_pfit.enabled) {
12663                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12664                         PIPE_CONF_CHECK_X(pch_pfit.size);
12665                 }
12666
12667                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12668         }
12669
12670         /* BDW+ don't expose a synchronous way to read the state */
12671         if (IS_HASWELL(dev))
12672                 PIPE_CONF_CHECK_I(ips_enabled);
12673
12674         PIPE_CONF_CHECK_I(double_wide);
12675
12676         PIPE_CONF_CHECK_X(ddi_pll_sel);
12677
12678         PIPE_CONF_CHECK_I(shared_dpll);
12679         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12680         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12681         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12682         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12683         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12684         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12685         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12686         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12687         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12688
12689         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12690                 PIPE_CONF_CHECK_I(pipe_bpp);
12691
12692         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12693         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12694
12695 #undef PIPE_CONF_CHECK_X
12696 #undef PIPE_CONF_CHECK_I
12697 #undef PIPE_CONF_CHECK_I_ALT
12698 #undef PIPE_CONF_CHECK_FLAGS
12699 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12700 #undef PIPE_CONF_QUIRK
12701 #undef INTEL_ERR_OR_DBG_KMS
12702
12703         return ret;
12704 }
12705
12706 static void check_wm_state(struct drm_device *dev)
12707 {
12708         struct drm_i915_private *dev_priv = dev->dev_private;
12709         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12710         struct intel_crtc *intel_crtc;
12711         int plane;
12712
12713         if (INTEL_INFO(dev)->gen < 9)
12714                 return;
12715
12716         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12717         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12718
12719         for_each_intel_crtc(dev, intel_crtc) {
12720                 struct skl_ddb_entry *hw_entry, *sw_entry;
12721                 const enum pipe pipe = intel_crtc->pipe;
12722
12723                 if (!intel_crtc->active)
12724                         continue;
12725
12726                 /* planes */
12727                 for_each_plane(dev_priv, pipe, plane) {
12728                         hw_entry = &hw_ddb.plane[pipe][plane];
12729                         sw_entry = &sw_ddb->plane[pipe][plane];
12730
12731                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12732                                 continue;
12733
12734                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12735                                   "(expected (%u,%u), found (%u,%u))\n",
12736                                   pipe_name(pipe), plane + 1,
12737                                   sw_entry->start, sw_entry->end,
12738                                   hw_entry->start, hw_entry->end);
12739                 }
12740
12741                 /* cursor */
12742                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12743                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12744
12745                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12746                         continue;
12747
12748                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12749                           "(expected (%u,%u), found (%u,%u))\n",
12750                           pipe_name(pipe),
12751                           sw_entry->start, sw_entry->end,
12752                           hw_entry->start, hw_entry->end);
12753         }
12754 }
12755
12756 static void
12757 check_connector_state(struct drm_device *dev,
12758                       struct drm_atomic_state *old_state)
12759 {
12760         struct drm_connector_state *old_conn_state;
12761         struct drm_connector *connector;
12762         int i;
12763
12764         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12765                 struct drm_encoder *encoder = connector->encoder;
12766                 struct drm_connector_state *state = connector->state;
12767
12768                 /* This also checks the encoder/connector hw state with the
12769                  * ->get_hw_state callbacks. */
12770                 intel_connector_check_state(to_intel_connector(connector));
12771
12772                 I915_STATE_WARN(state->best_encoder != encoder,
12773                      "connector's atomic encoder doesn't match legacy encoder\n");
12774         }
12775 }
12776
12777 static void
12778 check_encoder_state(struct drm_device *dev)
12779 {
12780         struct intel_encoder *encoder;
12781         struct intel_connector *connector;
12782
12783         for_each_intel_encoder(dev, encoder) {
12784                 bool enabled = false;
12785                 enum pipe pipe;
12786
12787                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12788                               encoder->base.base.id,
12789                               encoder->base.name);
12790
12791                 for_each_intel_connector(dev, connector) {
12792                         if (connector->base.state->best_encoder != &encoder->base)
12793                                 continue;
12794                         enabled = true;
12795
12796                         I915_STATE_WARN(connector->base.state->crtc !=
12797                                         encoder->base.crtc,
12798                              "connector's crtc doesn't match encoder crtc\n");
12799                 }
12800
12801                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12802                      "encoder's enabled state mismatch "
12803                      "(expected %i, found %i)\n",
12804                      !!encoder->base.crtc, enabled);
12805
12806                 if (!encoder->base.crtc) {
12807                         bool active;
12808
12809                         active = encoder->get_hw_state(encoder, &pipe);
12810                         I915_STATE_WARN(active,
12811                              "encoder detached but still enabled on pipe %c.\n",
12812                              pipe_name(pipe));
12813                 }
12814         }
12815 }
12816
12817 static void
12818 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12819 {
12820         struct drm_i915_private *dev_priv = dev->dev_private;
12821         struct intel_encoder *encoder;
12822         struct drm_crtc_state *old_crtc_state;
12823         struct drm_crtc *crtc;
12824         int i;
12825
12826         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12827                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12828                 struct intel_crtc_state *pipe_config, *sw_config;
12829                 bool active;
12830
12831                 if (!needs_modeset(crtc->state) &&
12832                     !to_intel_crtc_state(crtc->state)->update_pipe)
12833                         continue;
12834
12835                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12836                 pipe_config = to_intel_crtc_state(old_crtc_state);
12837                 memset(pipe_config, 0, sizeof(*pipe_config));
12838                 pipe_config->base.crtc = crtc;
12839                 pipe_config->base.state = old_state;
12840
12841                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12842                               crtc->base.id);
12843
12844                 active = dev_priv->display.get_pipe_config(intel_crtc,
12845                                                            pipe_config);
12846
12847                 /* hw state is inconsistent with the pipe quirk */
12848                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12849                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12850                         active = crtc->state->active;
12851
12852                 I915_STATE_WARN(crtc->state->active != active,
12853                      "crtc active state doesn't match with hw state "
12854                      "(expected %i, found %i)\n", crtc->state->active, active);
12855
12856                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12857                      "transitional active state does not match atomic hw state "
12858                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12859
12860                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12861                         enum pipe pipe;
12862
12863                         active = encoder->get_hw_state(encoder, &pipe);
12864                         I915_STATE_WARN(active != crtc->state->active,
12865                                 "[ENCODER:%i] active %i with crtc active %i\n",
12866                                 encoder->base.base.id, active, crtc->state->active);
12867
12868                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12869                                         "Encoder connected to wrong pipe %c\n",
12870                                         pipe_name(pipe));
12871
12872                         if (active)
12873                                 encoder->get_config(encoder, pipe_config);
12874                 }
12875
12876                 if (!crtc->state->active)
12877                         continue;
12878
12879                 sw_config = to_intel_crtc_state(crtc->state);
12880                 if (!intel_pipe_config_compare(dev, sw_config,
12881                                                pipe_config, false)) {
12882                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12883                         intel_dump_pipe_config(intel_crtc, pipe_config,
12884                                                "[hw state]");
12885                         intel_dump_pipe_config(intel_crtc, sw_config,
12886                                                "[sw state]");
12887                 }
12888         }
12889 }
12890
12891 static void
12892 check_shared_dpll_state(struct drm_device *dev)
12893 {
12894         struct drm_i915_private *dev_priv = dev->dev_private;
12895         struct intel_crtc *crtc;
12896         struct intel_dpll_hw_state dpll_hw_state;
12897         int i;
12898
12899         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12900                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12901                 int enabled_crtcs = 0, active_crtcs = 0;
12902                 bool active;
12903
12904                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12905
12906                 DRM_DEBUG_KMS("%s\n", pll->name);
12907
12908                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12909
12910                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12911                      "more active pll users than references: %i vs %i\n",
12912                      pll->active, hweight32(pll->config.crtc_mask));
12913                 I915_STATE_WARN(pll->active && !pll->on,
12914                      "pll in active use but not on in sw tracking\n");
12915                 I915_STATE_WARN(pll->on && !pll->active,
12916                      "pll in on but not on in use in sw tracking\n");
12917                 I915_STATE_WARN(pll->on != active,
12918                      "pll on state mismatch (expected %i, found %i)\n",
12919                      pll->on, active);
12920
12921                 for_each_intel_crtc(dev, crtc) {
12922                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12923                                 enabled_crtcs++;
12924                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12925                                 active_crtcs++;
12926                 }
12927                 I915_STATE_WARN(pll->active != active_crtcs,
12928                      "pll active crtcs mismatch (expected %i, found %i)\n",
12929                      pll->active, active_crtcs);
12930                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12931                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12932                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12933
12934                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12935                                        sizeof(dpll_hw_state)),
12936                      "pll hw state mismatch\n");
12937         }
12938 }
12939
12940 static void
12941 intel_modeset_check_state(struct drm_device *dev,
12942                           struct drm_atomic_state *old_state)
12943 {
12944         check_wm_state(dev);
12945         check_connector_state(dev, old_state);
12946         check_encoder_state(dev);
12947         check_crtc_state(dev, old_state);
12948         check_shared_dpll_state(dev);
12949 }
12950
12951 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12952                                      int dotclock)
12953 {
12954         /*
12955          * FDI already provided one idea for the dotclock.
12956          * Yell if the encoder disagrees.
12957          */
12958         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12959              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12960              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12961 }
12962
12963 static void update_scanline_offset(struct intel_crtc *crtc)
12964 {
12965         struct drm_device *dev = crtc->base.dev;
12966
12967         /*
12968          * The scanline counter increments at the leading edge of hsync.
12969          *
12970          * On most platforms it starts counting from vtotal-1 on the
12971          * first active line. That means the scanline counter value is
12972          * always one less than what we would expect. Ie. just after
12973          * start of vblank, which also occurs at start of hsync (on the
12974          * last active line), the scanline counter will read vblank_start-1.
12975          *
12976          * On gen2 the scanline counter starts counting from 1 instead
12977          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12978          * to keep the value positive), instead of adding one.
12979          *
12980          * On HSW+ the behaviour of the scanline counter depends on the output
12981          * type. For DP ports it behaves like most other platforms, but on HDMI
12982          * there's an extra 1 line difference. So we need to add two instead of
12983          * one to the value.
12984          */
12985         if (IS_GEN2(dev)) {
12986                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12987                 int vtotal;
12988
12989                 vtotal = adjusted_mode->crtc_vtotal;
12990                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12991                         vtotal /= 2;
12992
12993                 crtc->scanline_offset = vtotal - 1;
12994         } else if (HAS_DDI(dev) &&
12995                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12996                 crtc->scanline_offset = 2;
12997         } else
12998                 crtc->scanline_offset = 1;
12999 }
13000
13001 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13002 {
13003         struct drm_device *dev = state->dev;
13004         struct drm_i915_private *dev_priv = to_i915(dev);
13005         struct intel_shared_dpll_config *shared_dpll = NULL;
13006         struct intel_crtc *intel_crtc;
13007         struct intel_crtc_state *intel_crtc_state;
13008         struct drm_crtc *crtc;
13009         struct drm_crtc_state *crtc_state;
13010         int i;
13011
13012         if (!dev_priv->display.crtc_compute_clock)
13013                 return;
13014
13015         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13016                 int dpll;
13017
13018                 intel_crtc = to_intel_crtc(crtc);
13019                 intel_crtc_state = to_intel_crtc_state(crtc_state);
13020                 dpll = intel_crtc_state->shared_dpll;
13021
13022                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13023                         continue;
13024
13025                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13026
13027                 if (!shared_dpll)
13028                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13029
13030                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13031         }
13032 }
13033
13034 /*
13035  * This implements the workaround described in the "notes" section of the mode
13036  * set sequence documentation. When going from no pipes or single pipe to
13037  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13038  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13039  */
13040 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13041 {
13042         struct drm_crtc_state *crtc_state;
13043         struct intel_crtc *intel_crtc;
13044         struct drm_crtc *crtc;
13045         struct intel_crtc_state *first_crtc_state = NULL;
13046         struct intel_crtc_state *other_crtc_state = NULL;
13047         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13048         int i;
13049
13050         /* look at all crtc's that are going to be enabled in during modeset */
13051         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13052                 intel_crtc = to_intel_crtc(crtc);
13053
13054                 if (!crtc_state->active || !needs_modeset(crtc_state))
13055                         continue;
13056
13057                 if (first_crtc_state) {
13058                         other_crtc_state = to_intel_crtc_state(crtc_state);
13059                         break;
13060                 } else {
13061                         first_crtc_state = to_intel_crtc_state(crtc_state);
13062                         first_pipe = intel_crtc->pipe;
13063                 }
13064         }
13065
13066         /* No workaround needed? */
13067         if (!first_crtc_state)
13068                 return 0;
13069
13070         /* w/a possibly needed, check how many crtc's are already enabled. */
13071         for_each_intel_crtc(state->dev, intel_crtc) {
13072                 struct intel_crtc_state *pipe_config;
13073
13074                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13075                 if (IS_ERR(pipe_config))
13076                         return PTR_ERR(pipe_config);
13077
13078                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13079
13080                 if (!pipe_config->base.active ||
13081                     needs_modeset(&pipe_config->base))
13082                         continue;
13083
13084                 /* 2 or more enabled crtcs means no need for w/a */
13085                 if (enabled_pipe != INVALID_PIPE)
13086                         return 0;
13087
13088                 enabled_pipe = intel_crtc->pipe;
13089         }
13090
13091         if (enabled_pipe != INVALID_PIPE)
13092                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13093         else if (other_crtc_state)
13094                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13095
13096         return 0;
13097 }
13098
13099 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13100 {
13101         struct drm_crtc *crtc;
13102         struct drm_crtc_state *crtc_state;
13103         int ret = 0;
13104
13105         /* add all active pipes to the state */
13106         for_each_crtc(state->dev, crtc) {
13107                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13108                 if (IS_ERR(crtc_state))
13109                         return PTR_ERR(crtc_state);
13110
13111                 if (!crtc_state->active || needs_modeset(crtc_state))
13112                         continue;
13113
13114                 crtc_state->mode_changed = true;
13115
13116                 ret = drm_atomic_add_affected_connectors(state, crtc);
13117                 if (ret)
13118                         break;
13119
13120                 ret = drm_atomic_add_affected_planes(state, crtc);
13121                 if (ret)
13122                         break;
13123         }
13124
13125         return ret;
13126 }
13127
13128 static int intel_modeset_checks(struct drm_atomic_state *state)
13129 {
13130         struct drm_device *dev = state->dev;
13131         struct drm_i915_private *dev_priv = dev->dev_private;
13132         int ret;
13133
13134         if (!check_digital_port_conflicts(state)) {
13135                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13136                 return -EINVAL;
13137         }
13138
13139         /*
13140          * See if the config requires any additional preparation, e.g.
13141          * to adjust global state with pipes off.  We need to do this
13142          * here so we can get the modeset_pipe updated config for the new
13143          * mode set on this crtc.  For other crtcs we need to use the
13144          * adjusted_mode bits in the crtc directly.
13145          */
13146         if (dev_priv->display.modeset_calc_cdclk) {
13147                 unsigned int cdclk;
13148
13149                 ret = dev_priv->display.modeset_calc_cdclk(state);
13150
13151                 cdclk = to_intel_atomic_state(state)->cdclk;
13152                 if (!ret && cdclk != dev_priv->cdclk_freq)
13153                         ret = intel_modeset_all_pipes(state);
13154
13155                 if (ret < 0)
13156                         return ret;
13157         } else
13158                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13159
13160         intel_modeset_clear_plls(state);
13161
13162         if (IS_HASWELL(dev))
13163                 return haswell_mode_set_planes_workaround(state);
13164
13165         return 0;
13166 }
13167
13168 /*
13169  * Handle calculation of various watermark data at the end of the atomic check
13170  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13171  * handlers to ensure that all derived state has been updated.
13172  */
13173 static void calc_watermark_data(struct drm_atomic_state *state)
13174 {
13175         struct drm_device *dev = state->dev;
13176         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13177         struct drm_crtc *crtc;
13178         struct drm_crtc_state *cstate;
13179         struct drm_plane *plane;
13180         struct drm_plane_state *pstate;
13181
13182         /*
13183          * Calculate watermark configuration details now that derived
13184          * plane/crtc state is all properly updated.
13185          */
13186         drm_for_each_crtc(crtc, dev) {
13187                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13188                         crtc->state;
13189
13190                 if (cstate->active)
13191                         intel_state->wm_config.num_pipes_active++;
13192         }
13193         drm_for_each_legacy_plane(plane, dev) {
13194                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13195                         plane->state;
13196
13197                 if (!to_intel_plane_state(pstate)->visible)
13198                         continue;
13199
13200                 intel_state->wm_config.sprites_enabled = true;
13201                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13202                     pstate->crtc_h != pstate->src_h >> 16)
13203                         intel_state->wm_config.sprites_scaled = true;
13204         }
13205 }
13206
13207 /**
13208  * intel_atomic_check - validate state object
13209  * @dev: drm device
13210  * @state: state to validate
13211  */
13212 static int intel_atomic_check(struct drm_device *dev,
13213                               struct drm_atomic_state *state)
13214 {
13215         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13216         struct drm_crtc *crtc;
13217         struct drm_crtc_state *crtc_state;
13218         int ret, i;
13219         bool any_ms = false;
13220
13221         ret = drm_atomic_helper_check_modeset(dev, state);
13222         if (ret)
13223                 return ret;
13224
13225         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13226                 struct intel_crtc_state *pipe_config =
13227                         to_intel_crtc_state(crtc_state);
13228
13229                 memset(&to_intel_crtc(crtc)->atomic, 0,
13230                        sizeof(struct intel_crtc_atomic_commit));
13231
13232                 /* Catch I915_MODE_FLAG_INHERITED */
13233                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13234                         crtc_state->mode_changed = true;
13235
13236                 if (!crtc_state->enable) {
13237                         if (needs_modeset(crtc_state))
13238                                 any_ms = true;
13239                         continue;
13240                 }
13241
13242                 if (!needs_modeset(crtc_state))
13243                         continue;
13244
13245                 /* FIXME: For only active_changed we shouldn't need to do any
13246                  * state recomputation at all. */
13247
13248                 ret = drm_atomic_add_affected_connectors(state, crtc);
13249                 if (ret)
13250                         return ret;
13251
13252                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13253                 if (ret)
13254                         return ret;
13255
13256                 if (i915.fastboot &&
13257                     intel_pipe_config_compare(state->dev,
13258                                         to_intel_crtc_state(crtc->state),
13259                                         pipe_config, true)) {
13260                         crtc_state->mode_changed = false;
13261                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13262                 }
13263
13264                 if (needs_modeset(crtc_state)) {
13265                         any_ms = true;
13266
13267                         ret = drm_atomic_add_affected_planes(state, crtc);
13268                         if (ret)
13269                                 return ret;
13270                 }
13271
13272                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13273                                        needs_modeset(crtc_state) ?
13274                                        "[modeset]" : "[fastset]");
13275         }
13276
13277         if (any_ms) {
13278                 ret = intel_modeset_checks(state);
13279
13280                 if (ret)
13281                         return ret;
13282         } else
13283                 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13284
13285         ret = drm_atomic_helper_check_planes(state->dev, state);
13286         if (ret)
13287                 return ret;
13288
13289         calc_watermark_data(state);
13290
13291         return 0;
13292 }
13293
13294 static int intel_atomic_prepare_commit(struct drm_device *dev,
13295                                        struct drm_atomic_state *state,
13296                                        bool async)
13297 {
13298         struct drm_i915_private *dev_priv = dev->dev_private;
13299         struct drm_plane_state *plane_state;
13300         struct drm_crtc_state *crtc_state;
13301         struct drm_plane *plane;
13302         struct drm_crtc *crtc;
13303         int i, ret;
13304
13305         if (async) {
13306                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13307                 return -EINVAL;
13308         }
13309
13310         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13311                 ret = intel_crtc_wait_for_pending_flips(crtc);
13312                 if (ret)
13313                         return ret;
13314
13315                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13316                         flush_workqueue(dev_priv->wq);
13317         }
13318
13319         ret = mutex_lock_interruptible(&dev->struct_mutex);
13320         if (ret)
13321                 return ret;
13322
13323         ret = drm_atomic_helper_prepare_planes(dev, state);
13324         if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13325                 u32 reset_counter;
13326
13327                 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13328                 mutex_unlock(&dev->struct_mutex);
13329
13330                 for_each_plane_in_state(state, plane, plane_state, i) {
13331                         struct intel_plane_state *intel_plane_state =
13332                                 to_intel_plane_state(plane_state);
13333
13334                         if (!intel_plane_state->wait_req)
13335                                 continue;
13336
13337                         ret = __i915_wait_request(intel_plane_state->wait_req,
13338                                                   reset_counter, true,
13339                                                   NULL, NULL);
13340
13341                         /* Swallow -EIO errors to allow updates during hw lockup. */
13342                         if (ret == -EIO)
13343                                 ret = 0;
13344
13345                         if (ret)
13346                                 break;
13347                 }
13348
13349                 if (!ret)
13350                         return 0;
13351
13352                 mutex_lock(&dev->struct_mutex);
13353                 drm_atomic_helper_cleanup_planes(dev, state);
13354         }
13355
13356         mutex_unlock(&dev->struct_mutex);
13357         return ret;
13358 }
13359
13360 /**
13361  * intel_atomic_commit - commit validated state object
13362  * @dev: DRM device
13363  * @state: the top-level driver state object
13364  * @async: asynchronous commit
13365  *
13366  * This function commits a top-level state object that has been validated
13367  * with drm_atomic_helper_check().
13368  *
13369  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13370  * we can only handle plane-related operations and do not yet support
13371  * asynchronous commit.
13372  *
13373  * RETURNS
13374  * Zero for success or -errno.
13375  */
13376 static int intel_atomic_commit(struct drm_device *dev,
13377                                struct drm_atomic_state *state,
13378                                bool async)
13379 {
13380         struct drm_i915_private *dev_priv = dev->dev_private;
13381         struct drm_crtc_state *crtc_state;
13382         struct drm_crtc *crtc;
13383         int ret = 0;
13384         int i;
13385         bool any_ms = false;
13386
13387         ret = intel_atomic_prepare_commit(dev, state, async);
13388         if (ret) {
13389                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13390                 return ret;
13391         }
13392
13393         drm_atomic_helper_swap_state(dev, state);
13394         dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13395
13396         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13397                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13398
13399                 if (!needs_modeset(crtc->state))
13400                         continue;
13401
13402                 any_ms = true;
13403                 intel_pre_plane_update(intel_crtc);
13404
13405                 if (crtc_state->active) {
13406                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13407                         dev_priv->display.crtc_disable(crtc);
13408                         intel_crtc->active = false;
13409                         intel_disable_shared_dpll(intel_crtc);
13410
13411                         /*
13412                          * Underruns don't always raise
13413                          * interrupts, so check manually.
13414                          */
13415                         intel_check_cpu_fifo_underruns(dev_priv);
13416                         intel_check_pch_fifo_underruns(dev_priv);
13417                 }
13418         }
13419
13420         /* Only after disabling all output pipelines that will be changed can we
13421          * update the the output configuration. */
13422         intel_modeset_update_crtc_state(state);
13423
13424         if (any_ms) {
13425                 intel_shared_dpll_commit(state);
13426
13427                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13428                 modeset_update_crtc_power_domains(state);
13429         }
13430
13431         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13432         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13433                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13434                 bool modeset = needs_modeset(crtc->state);
13435                 bool update_pipe = !modeset &&
13436                         to_intel_crtc_state(crtc->state)->update_pipe;
13437                 unsigned long put_domains = 0;
13438
13439                 if (modeset)
13440                         intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13441
13442                 if (modeset && crtc->state->active) {
13443                         update_scanline_offset(to_intel_crtc(crtc));
13444                         dev_priv->display.crtc_enable(crtc);
13445                 }
13446
13447                 if (update_pipe) {
13448                         put_domains = modeset_get_crtc_power_domains(crtc);
13449
13450                         /* make sure intel_modeset_check_state runs */
13451                         any_ms = true;
13452                 }
13453
13454                 if (!modeset)
13455                         intel_pre_plane_update(intel_crtc);
13456
13457                 if (crtc->state->active &&
13458                     (crtc->state->planes_changed || update_pipe))
13459                         drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13460
13461                 if (put_domains)
13462                         modeset_put_power_domains(dev_priv, put_domains);
13463
13464                 intel_post_plane_update(intel_crtc);
13465
13466                 if (modeset)
13467                         intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13468         }
13469
13470         /* FIXME: add subpixel order */
13471
13472         drm_atomic_helper_wait_for_vblanks(dev, state);
13473
13474         mutex_lock(&dev->struct_mutex);
13475         drm_atomic_helper_cleanup_planes(dev, state);
13476         mutex_unlock(&dev->struct_mutex);
13477
13478         if (any_ms)
13479                 intel_modeset_check_state(dev, state);
13480
13481         drm_atomic_state_free(state);
13482
13483         return 0;
13484 }
13485
13486 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13487 {
13488         struct drm_device *dev = crtc->dev;
13489         struct drm_atomic_state *state;
13490         struct drm_crtc_state *crtc_state;
13491         int ret;
13492
13493         state = drm_atomic_state_alloc(dev);
13494         if (!state) {
13495                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13496                               crtc->base.id);
13497                 return;
13498         }
13499
13500         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13501
13502 retry:
13503         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13504         ret = PTR_ERR_OR_ZERO(crtc_state);
13505         if (!ret) {
13506                 if (!crtc_state->active)
13507                         goto out;
13508
13509                 crtc_state->mode_changed = true;
13510                 ret = drm_atomic_commit(state);
13511         }
13512
13513         if (ret == -EDEADLK) {
13514                 drm_atomic_state_clear(state);
13515                 drm_modeset_backoff(state->acquire_ctx);
13516                 goto retry;
13517         }
13518
13519         if (ret)
13520 out:
13521                 drm_atomic_state_free(state);
13522 }
13523
13524 #undef for_each_intel_crtc_masked
13525
13526 static const struct drm_crtc_funcs intel_crtc_funcs = {
13527         .gamma_set = intel_crtc_gamma_set,
13528         .set_config = drm_atomic_helper_set_config,
13529         .destroy = intel_crtc_destroy,
13530         .page_flip = intel_crtc_page_flip,
13531         .atomic_duplicate_state = intel_crtc_duplicate_state,
13532         .atomic_destroy_state = intel_crtc_destroy_state,
13533 };
13534
13535 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13536                                       struct intel_shared_dpll *pll,
13537                                       struct intel_dpll_hw_state *hw_state)
13538 {
13539         uint32_t val;
13540
13541         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13542                 return false;
13543
13544         val = I915_READ(PCH_DPLL(pll->id));
13545         hw_state->dpll = val;
13546         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13547         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13548
13549         return val & DPLL_VCO_ENABLE;
13550 }
13551
13552 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13553                                   struct intel_shared_dpll *pll)
13554 {
13555         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13556         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13557 }
13558
13559 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13560                                 struct intel_shared_dpll *pll)
13561 {
13562         /* PCH refclock must be enabled first */
13563         ibx_assert_pch_refclk_enabled(dev_priv);
13564
13565         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13566
13567         /* Wait for the clocks to stabilize. */
13568         POSTING_READ(PCH_DPLL(pll->id));
13569         udelay(150);
13570
13571         /* The pixel multiplier can only be updated once the
13572          * DPLL is enabled and the clocks are stable.
13573          *
13574          * So write it again.
13575          */
13576         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13577         POSTING_READ(PCH_DPLL(pll->id));
13578         udelay(200);
13579 }
13580
13581 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13582                                  struct intel_shared_dpll *pll)
13583 {
13584         struct drm_device *dev = dev_priv->dev;
13585         struct intel_crtc *crtc;
13586
13587         /* Make sure no transcoder isn't still depending on us. */
13588         for_each_intel_crtc(dev, crtc) {
13589                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13590                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13591         }
13592
13593         I915_WRITE(PCH_DPLL(pll->id), 0);
13594         POSTING_READ(PCH_DPLL(pll->id));
13595         udelay(200);
13596 }
13597
13598 static char *ibx_pch_dpll_names[] = {
13599         "PCH DPLL A",
13600         "PCH DPLL B",
13601 };
13602
13603 static void ibx_pch_dpll_init(struct drm_device *dev)
13604 {
13605         struct drm_i915_private *dev_priv = dev->dev_private;
13606         int i;
13607
13608         dev_priv->num_shared_dpll = 2;
13609
13610         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13611                 dev_priv->shared_dplls[i].id = i;
13612                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13613                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13614                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13615                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13616                 dev_priv->shared_dplls[i].get_hw_state =
13617                         ibx_pch_dpll_get_hw_state;
13618         }
13619 }
13620
13621 static void intel_shared_dpll_init(struct drm_device *dev)
13622 {
13623         struct drm_i915_private *dev_priv = dev->dev_private;
13624
13625         if (HAS_DDI(dev))
13626                 intel_ddi_pll_init(dev);
13627         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13628                 ibx_pch_dpll_init(dev);
13629         else
13630                 dev_priv->num_shared_dpll = 0;
13631
13632         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13633 }
13634
13635 /**
13636  * intel_prepare_plane_fb - Prepare fb for usage on plane
13637  * @plane: drm plane to prepare for
13638  * @fb: framebuffer to prepare for presentation
13639  *
13640  * Prepares a framebuffer for usage on a display plane.  Generally this
13641  * involves pinning the underlying object and updating the frontbuffer tracking
13642  * bits.  Some older platforms need special physical address handling for
13643  * cursor planes.
13644  *
13645  * Must be called with struct_mutex held.
13646  *
13647  * Returns 0 on success, negative error code on failure.
13648  */
13649 int
13650 intel_prepare_plane_fb(struct drm_plane *plane,
13651                        const struct drm_plane_state *new_state)
13652 {
13653         struct drm_device *dev = plane->dev;
13654         struct drm_framebuffer *fb = new_state->fb;
13655         struct intel_plane *intel_plane = to_intel_plane(plane);
13656         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13657         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13658         int ret = 0;
13659
13660         if (!obj && !old_obj)
13661                 return 0;
13662
13663         if (old_obj) {
13664                 struct drm_crtc_state *crtc_state =
13665                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13666
13667                 /* Big Hammer, we also need to ensure that any pending
13668                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13669                  * current scanout is retired before unpinning the old
13670                  * framebuffer. Note that we rely on userspace rendering
13671                  * into the buffer attached to the pipe they are waiting
13672                  * on. If not, userspace generates a GPU hang with IPEHR
13673                  * point to the MI_WAIT_FOR_EVENT.
13674                  *
13675                  * This should only fail upon a hung GPU, in which case we
13676                  * can safely continue.
13677                  */
13678                 if (needs_modeset(crtc_state))
13679                         ret = i915_gem_object_wait_rendering(old_obj, true);
13680
13681                 /* Swallow -EIO errors to allow updates during hw lockup. */
13682                 if (ret && ret != -EIO)
13683                         return ret;
13684         }
13685
13686         /* For framebuffer backed by dmabuf, wait for fence */
13687         if (obj && obj->base.dma_buf) {
13688                 ret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13689                                                           false, true,
13690                                                           MAX_SCHEDULE_TIMEOUT);
13691                 if (ret == -ERESTARTSYS)
13692                         return ret;
13693
13694                 WARN_ON(ret < 0);
13695         }
13696
13697         if (!obj) {
13698                 ret = 0;
13699         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13700             INTEL_INFO(dev)->cursor_needs_physical) {
13701                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13702                 ret = i915_gem_object_attach_phys(obj, align);
13703                 if (ret)
13704                         DRM_DEBUG_KMS("failed to attach phys object\n");
13705         } else {
13706                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13707         }
13708
13709         if (ret == 0) {
13710                 if (obj) {
13711                         struct intel_plane_state *plane_state =
13712                                 to_intel_plane_state(new_state);
13713
13714                         i915_gem_request_assign(&plane_state->wait_req,
13715                                                 obj->last_write_req);
13716                 }
13717
13718                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13719         }
13720
13721         return ret;
13722 }
13723
13724 /**
13725  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13726  * @plane: drm plane to clean up for
13727  * @fb: old framebuffer that was on plane
13728  *
13729  * Cleans up a framebuffer that has just been removed from a plane.
13730  *
13731  * Must be called with struct_mutex held.
13732  */
13733 void
13734 intel_cleanup_plane_fb(struct drm_plane *plane,
13735                        const struct drm_plane_state *old_state)
13736 {
13737         struct drm_device *dev = plane->dev;
13738         struct intel_plane *intel_plane = to_intel_plane(plane);
13739         struct intel_plane_state *old_intel_state;
13740         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13741         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13742
13743         old_intel_state = to_intel_plane_state(old_state);
13744
13745         if (!obj && !old_obj)
13746                 return;
13747
13748         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13749             !INTEL_INFO(dev)->cursor_needs_physical))
13750                 intel_unpin_fb_obj(old_state->fb, old_state);
13751
13752         /* prepare_fb aborted? */
13753         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13754             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13755                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13756
13757         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13758
13759 }
13760
13761 int
13762 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13763 {
13764         int max_scale;
13765         struct drm_device *dev;
13766         struct drm_i915_private *dev_priv;
13767         int crtc_clock, cdclk;
13768
13769         if (!intel_crtc || !crtc_state)
13770                 return DRM_PLANE_HELPER_NO_SCALING;
13771
13772         dev = intel_crtc->base.dev;
13773         dev_priv = dev->dev_private;
13774         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13775         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13776
13777         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13778                 return DRM_PLANE_HELPER_NO_SCALING;
13779
13780         /*
13781          * skl max scale is lower of:
13782          *    close to 3 but not 3, -1 is for that purpose
13783          *            or
13784          *    cdclk/crtc_clock
13785          */
13786         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13787
13788         return max_scale;
13789 }
13790
13791 static int
13792 intel_check_primary_plane(struct drm_plane *plane,
13793                           struct intel_crtc_state *crtc_state,
13794                           struct intel_plane_state *state)
13795 {
13796         struct drm_crtc *crtc = state->base.crtc;
13797         struct drm_framebuffer *fb = state->base.fb;
13798         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13799         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13800         bool can_position = false;
13801
13802         /* use scaler when colorkey is not required */
13803         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13804             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13805                 min_scale = 1;
13806                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13807                 can_position = true;
13808         }
13809
13810         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13811                                              &state->dst, &state->clip,
13812                                              min_scale, max_scale,
13813                                              can_position, true,
13814                                              &state->visible);
13815 }
13816
13817 static void
13818 intel_commit_primary_plane(struct drm_plane *plane,
13819                            struct intel_plane_state *state)
13820 {
13821         struct drm_crtc *crtc = state->base.crtc;
13822         struct drm_framebuffer *fb = state->base.fb;
13823         struct drm_device *dev = plane->dev;
13824         struct drm_i915_private *dev_priv = dev->dev_private;
13825
13826         crtc = crtc ? crtc : plane->crtc;
13827
13828         dev_priv->display.update_primary_plane(crtc, fb,
13829                                                state->src.x1 >> 16,
13830                                                state->src.y1 >> 16);
13831 }
13832
13833 static void
13834 intel_disable_primary_plane(struct drm_plane *plane,
13835                             struct drm_crtc *crtc)
13836 {
13837         struct drm_device *dev = plane->dev;
13838         struct drm_i915_private *dev_priv = dev->dev_private;
13839
13840         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13841 }
13842
13843 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13844                                     struct drm_crtc_state *old_crtc_state)
13845 {
13846         struct drm_device *dev = crtc->dev;
13847         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13848         struct intel_crtc_state *old_intel_state =
13849                 to_intel_crtc_state(old_crtc_state);
13850         bool modeset = needs_modeset(crtc->state);
13851
13852         if (intel_crtc->atomic.update_wm_pre)
13853                 intel_update_watermarks(crtc);
13854
13855         /* Perform vblank evasion around commit operation */
13856         intel_pipe_update_start(intel_crtc);
13857
13858         if (modeset)
13859                 return;
13860
13861         if (to_intel_crtc_state(crtc->state)->update_pipe)
13862                 intel_update_pipe_config(intel_crtc, old_intel_state);
13863         else if (INTEL_INFO(dev)->gen >= 9)
13864                 skl_detach_scalers(intel_crtc);
13865 }
13866
13867 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13868                                      struct drm_crtc_state *old_crtc_state)
13869 {
13870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13871
13872         intel_pipe_update_end(intel_crtc);
13873 }
13874
13875 /**
13876  * intel_plane_destroy - destroy a plane
13877  * @plane: plane to destroy
13878  *
13879  * Common destruction function for all types of planes (primary, cursor,
13880  * sprite).
13881  */
13882 void intel_plane_destroy(struct drm_plane *plane)
13883 {
13884         struct intel_plane *intel_plane = to_intel_plane(plane);
13885         drm_plane_cleanup(plane);
13886         kfree(intel_plane);
13887 }
13888
13889 const struct drm_plane_funcs intel_plane_funcs = {
13890         .update_plane = drm_atomic_helper_update_plane,
13891         .disable_plane = drm_atomic_helper_disable_plane,
13892         .destroy = intel_plane_destroy,
13893         .set_property = drm_atomic_helper_plane_set_property,
13894         .atomic_get_property = intel_plane_atomic_get_property,
13895         .atomic_set_property = intel_plane_atomic_set_property,
13896         .atomic_duplicate_state = intel_plane_duplicate_state,
13897         .atomic_destroy_state = intel_plane_destroy_state,
13898
13899 };
13900
13901 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13902                                                     int pipe)
13903 {
13904         struct intel_plane *primary;
13905         struct intel_plane_state *state;
13906         const uint32_t *intel_primary_formats;
13907         unsigned int num_formats;
13908
13909         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13910         if (primary == NULL)
13911                 return NULL;
13912
13913         state = intel_create_plane_state(&primary->base);
13914         if (!state) {
13915                 kfree(primary);
13916                 return NULL;
13917         }
13918         primary->base.state = &state->base;
13919
13920         primary->can_scale = false;
13921         primary->max_downscale = 1;
13922         if (INTEL_INFO(dev)->gen >= 9) {
13923                 primary->can_scale = true;
13924                 state->scaler_id = -1;
13925         }
13926         primary->pipe = pipe;
13927         primary->plane = pipe;
13928         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13929         primary->check_plane = intel_check_primary_plane;
13930         primary->commit_plane = intel_commit_primary_plane;
13931         primary->disable_plane = intel_disable_primary_plane;
13932         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13933                 primary->plane = !pipe;
13934
13935         if (INTEL_INFO(dev)->gen >= 9) {
13936                 intel_primary_formats = skl_primary_formats;
13937                 num_formats = ARRAY_SIZE(skl_primary_formats);
13938         } else if (INTEL_INFO(dev)->gen >= 4) {
13939                 intel_primary_formats = i965_primary_formats;
13940                 num_formats = ARRAY_SIZE(i965_primary_formats);
13941         } else {
13942                 intel_primary_formats = i8xx_primary_formats;
13943                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13944         }
13945
13946         drm_universal_plane_init(dev, &primary->base, 0,
13947                                  &intel_plane_funcs,
13948                                  intel_primary_formats, num_formats,
13949                                  DRM_PLANE_TYPE_PRIMARY, NULL);
13950
13951         if (INTEL_INFO(dev)->gen >= 4)
13952                 intel_create_rotation_property(dev, primary);
13953
13954         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13955
13956         return &primary->base;
13957 }
13958
13959 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13960 {
13961         if (!dev->mode_config.rotation_property) {
13962                 unsigned long flags = BIT(DRM_ROTATE_0) |
13963                         BIT(DRM_ROTATE_180);
13964
13965                 if (INTEL_INFO(dev)->gen >= 9)
13966                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13967
13968                 dev->mode_config.rotation_property =
13969                         drm_mode_create_rotation_property(dev, flags);
13970         }
13971         if (dev->mode_config.rotation_property)
13972                 drm_object_attach_property(&plane->base.base,
13973                                 dev->mode_config.rotation_property,
13974                                 plane->base.state->rotation);
13975 }
13976
13977 static int
13978 intel_check_cursor_plane(struct drm_plane *plane,
13979                          struct intel_crtc_state *crtc_state,
13980                          struct intel_plane_state *state)
13981 {
13982         struct drm_crtc *crtc = crtc_state->base.crtc;
13983         struct drm_framebuffer *fb = state->base.fb;
13984         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13985         unsigned stride;
13986         int ret;
13987
13988         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13989                                             &state->dst, &state->clip,
13990                                             DRM_PLANE_HELPER_NO_SCALING,
13991                                             DRM_PLANE_HELPER_NO_SCALING,
13992                                             true, true, &state->visible);
13993         if (ret)
13994                 return ret;
13995
13996         /* if we want to turn off the cursor ignore width and height */
13997         if (!obj)
13998                 return 0;
13999
14000         /* Check for which cursor types we support */
14001         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14002                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14003                           state->base.crtc_w, state->base.crtc_h);
14004                 return -EINVAL;
14005         }
14006
14007         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14008         if (obj->base.size < stride * state->base.crtc_h) {
14009                 DRM_DEBUG_KMS("buffer is too small\n");
14010                 return -ENOMEM;
14011         }
14012
14013         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14014                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14015                 return -EINVAL;
14016         }
14017
14018         return 0;
14019 }
14020
14021 static void
14022 intel_disable_cursor_plane(struct drm_plane *plane,
14023                            struct drm_crtc *crtc)
14024 {
14025         intel_crtc_update_cursor(crtc, false);
14026 }
14027
14028 static void
14029 intel_commit_cursor_plane(struct drm_plane *plane,
14030                           struct intel_plane_state *state)
14031 {
14032         struct drm_crtc *crtc = state->base.crtc;
14033         struct drm_device *dev = plane->dev;
14034         struct intel_crtc *intel_crtc;
14035         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14036         uint32_t addr;
14037
14038         crtc = crtc ? crtc : plane->crtc;
14039         intel_crtc = to_intel_crtc(crtc);
14040
14041         if (intel_crtc->cursor_bo == obj)
14042                 goto update;
14043
14044         if (!obj)
14045                 addr = 0;
14046         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14047                 addr = i915_gem_obj_ggtt_offset(obj);
14048         else
14049                 addr = obj->phys_handle->busaddr;
14050
14051         intel_crtc->cursor_addr = addr;
14052         intel_crtc->cursor_bo = obj;
14053
14054 update:
14055         intel_crtc_update_cursor(crtc, state->visible);
14056 }
14057
14058 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14059                                                    int pipe)
14060 {
14061         struct intel_plane *cursor;
14062         struct intel_plane_state *state;
14063
14064         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14065         if (cursor == NULL)
14066                 return NULL;
14067
14068         state = intel_create_plane_state(&cursor->base);
14069         if (!state) {
14070                 kfree(cursor);
14071                 return NULL;
14072         }
14073         cursor->base.state = &state->base;
14074
14075         cursor->can_scale = false;
14076         cursor->max_downscale = 1;
14077         cursor->pipe = pipe;
14078         cursor->plane = pipe;
14079         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14080         cursor->check_plane = intel_check_cursor_plane;
14081         cursor->commit_plane = intel_commit_cursor_plane;
14082         cursor->disable_plane = intel_disable_cursor_plane;
14083
14084         drm_universal_plane_init(dev, &cursor->base, 0,
14085                                  &intel_plane_funcs,
14086                                  intel_cursor_formats,
14087                                  ARRAY_SIZE(intel_cursor_formats),
14088                                  DRM_PLANE_TYPE_CURSOR, NULL);
14089
14090         if (INTEL_INFO(dev)->gen >= 4) {
14091                 if (!dev->mode_config.rotation_property)
14092                         dev->mode_config.rotation_property =
14093                                 drm_mode_create_rotation_property(dev,
14094                                                         BIT(DRM_ROTATE_0) |
14095                                                         BIT(DRM_ROTATE_180));
14096                 if (dev->mode_config.rotation_property)
14097                         drm_object_attach_property(&cursor->base.base,
14098                                 dev->mode_config.rotation_property,
14099                                 state->base.rotation);
14100         }
14101
14102         if (INTEL_INFO(dev)->gen >=9)
14103                 state->scaler_id = -1;
14104
14105         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14106
14107         return &cursor->base;
14108 }
14109
14110 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14111         struct intel_crtc_state *crtc_state)
14112 {
14113         int i;
14114         struct intel_scaler *intel_scaler;
14115         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14116
14117         for (i = 0; i < intel_crtc->num_scalers; i++) {
14118                 intel_scaler = &scaler_state->scalers[i];
14119                 intel_scaler->in_use = 0;
14120                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14121         }
14122
14123         scaler_state->scaler_id = -1;
14124 }
14125
14126 static void intel_crtc_init(struct drm_device *dev, int pipe)
14127 {
14128         struct drm_i915_private *dev_priv = dev->dev_private;
14129         struct intel_crtc *intel_crtc;
14130         struct intel_crtc_state *crtc_state = NULL;
14131         struct drm_plane *primary = NULL;
14132         struct drm_plane *cursor = NULL;
14133         int i, ret;
14134
14135         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14136         if (intel_crtc == NULL)
14137                 return;
14138
14139         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14140         if (!crtc_state)
14141                 goto fail;
14142         intel_crtc->config = crtc_state;
14143         intel_crtc->base.state = &crtc_state->base;
14144         crtc_state->base.crtc = &intel_crtc->base;
14145
14146         /* initialize shared scalers */
14147         if (INTEL_INFO(dev)->gen >= 9) {
14148                 if (pipe == PIPE_C)
14149                         intel_crtc->num_scalers = 1;
14150                 else
14151                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14152
14153                 skl_init_scalers(dev, intel_crtc, crtc_state);
14154         }
14155
14156         primary = intel_primary_plane_create(dev, pipe);
14157         if (!primary)
14158                 goto fail;
14159
14160         cursor = intel_cursor_plane_create(dev, pipe);
14161         if (!cursor)
14162                 goto fail;
14163
14164         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14165                                         cursor, &intel_crtc_funcs, NULL);
14166         if (ret)
14167                 goto fail;
14168
14169         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14170         for (i = 0; i < 256; i++) {
14171                 intel_crtc->lut_r[i] = i;
14172                 intel_crtc->lut_g[i] = i;
14173                 intel_crtc->lut_b[i] = i;
14174         }
14175
14176         /*
14177          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14178          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14179          */
14180         intel_crtc->pipe = pipe;
14181         intel_crtc->plane = pipe;
14182         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14183                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14184                 intel_crtc->plane = !pipe;
14185         }
14186
14187         intel_crtc->cursor_base = ~0;
14188         intel_crtc->cursor_cntl = ~0;
14189         intel_crtc->cursor_size = ~0;
14190
14191         intel_crtc->wm.cxsr_allowed = true;
14192
14193         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14194                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14195         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14196         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14197
14198         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14199
14200         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14201         return;
14202
14203 fail:
14204         if (primary)
14205                 drm_plane_cleanup(primary);
14206         if (cursor)
14207                 drm_plane_cleanup(cursor);
14208         kfree(crtc_state);
14209         kfree(intel_crtc);
14210 }
14211
14212 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14213 {
14214         struct drm_encoder *encoder = connector->base.encoder;
14215         struct drm_device *dev = connector->base.dev;
14216
14217         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14218
14219         if (!encoder || WARN_ON(!encoder->crtc))
14220                 return INVALID_PIPE;
14221
14222         return to_intel_crtc(encoder->crtc)->pipe;
14223 }
14224
14225 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14226                                 struct drm_file *file)
14227 {
14228         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14229         struct drm_crtc *drmmode_crtc;
14230         struct intel_crtc *crtc;
14231
14232         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14233
14234         if (!drmmode_crtc) {
14235                 DRM_ERROR("no such CRTC id\n");
14236                 return -ENOENT;
14237         }
14238
14239         crtc = to_intel_crtc(drmmode_crtc);
14240         pipe_from_crtc_id->pipe = crtc->pipe;
14241
14242         return 0;
14243 }
14244
14245 static int intel_encoder_clones(struct intel_encoder *encoder)
14246 {
14247         struct drm_device *dev = encoder->base.dev;
14248         struct intel_encoder *source_encoder;
14249         int index_mask = 0;
14250         int entry = 0;
14251
14252         for_each_intel_encoder(dev, source_encoder) {
14253                 if (encoders_cloneable(encoder, source_encoder))
14254                         index_mask |= (1 << entry);
14255
14256                 entry++;
14257         }
14258
14259         return index_mask;
14260 }
14261
14262 static bool has_edp_a(struct drm_device *dev)
14263 {
14264         struct drm_i915_private *dev_priv = dev->dev_private;
14265
14266         if (!IS_MOBILE(dev))
14267                 return false;
14268
14269         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14270                 return false;
14271
14272         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14273                 return false;
14274
14275         return true;
14276 }
14277
14278 static bool intel_crt_present(struct drm_device *dev)
14279 {
14280         struct drm_i915_private *dev_priv = dev->dev_private;
14281
14282         if (INTEL_INFO(dev)->gen >= 9)
14283                 return false;
14284
14285         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14286                 return false;
14287
14288         if (IS_CHERRYVIEW(dev))
14289                 return false;
14290
14291         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14292                 return false;
14293
14294         /* DDI E can't be used if DDI A requires 4 lanes */
14295         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14296                 return false;
14297
14298         if (!dev_priv->vbt.int_crt_support)
14299                 return false;
14300
14301         return true;
14302 }
14303
14304 static void intel_setup_outputs(struct drm_device *dev)
14305 {
14306         struct drm_i915_private *dev_priv = dev->dev_private;
14307         struct intel_encoder *encoder;
14308         bool dpd_is_edp = false;
14309
14310         intel_lvds_init(dev);
14311
14312         if (intel_crt_present(dev))
14313                 intel_crt_init(dev);
14314
14315         if (IS_BROXTON(dev)) {
14316                 /*
14317                  * FIXME: Broxton doesn't support port detection via the
14318                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14319                  * detect the ports.
14320                  */
14321                 intel_ddi_init(dev, PORT_A);
14322                 intel_ddi_init(dev, PORT_B);
14323                 intel_ddi_init(dev, PORT_C);
14324         } else if (HAS_DDI(dev)) {
14325                 int found;
14326
14327                 /*
14328                  * Haswell uses DDI functions to detect digital outputs.
14329                  * On SKL pre-D0 the strap isn't connected, so we assume
14330                  * it's there.
14331                  */
14332                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14333                 /* WaIgnoreDDIAStrap: skl */
14334                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14335                         intel_ddi_init(dev, PORT_A);
14336
14337                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14338                  * register */
14339                 found = I915_READ(SFUSE_STRAP);
14340
14341                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14342                         intel_ddi_init(dev, PORT_B);
14343                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14344                         intel_ddi_init(dev, PORT_C);
14345                 if (found & SFUSE_STRAP_DDID_DETECTED)
14346                         intel_ddi_init(dev, PORT_D);
14347                 /*
14348                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14349                  */
14350                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14351                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14352                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14353                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14354                         intel_ddi_init(dev, PORT_E);
14355
14356         } else if (HAS_PCH_SPLIT(dev)) {
14357                 int found;
14358                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14359
14360                 if (has_edp_a(dev))
14361                         intel_dp_init(dev, DP_A, PORT_A);
14362
14363                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14364                         /* PCH SDVOB multiplex with HDMIB */
14365                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14366                         if (!found)
14367                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14368                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14369                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14370                 }
14371
14372                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14373                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14374
14375                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14376                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14377
14378                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14379                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14380
14381                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14382                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14383         } else if (IS_VALLEYVIEW(dev)) {
14384                 /*
14385                  * The DP_DETECTED bit is the latched state of the DDC
14386                  * SDA pin at boot. However since eDP doesn't require DDC
14387                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14388                  * eDP ports may have been muxed to an alternate function.
14389                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14390                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14391                  * detect eDP ports.
14392                  */
14393                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14394                     !intel_dp_is_edp(dev, PORT_B))
14395                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14396                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14397                     intel_dp_is_edp(dev, PORT_B))
14398                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14399
14400                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14401                     !intel_dp_is_edp(dev, PORT_C))
14402                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14403                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14404                     intel_dp_is_edp(dev, PORT_C))
14405                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14406
14407                 if (IS_CHERRYVIEW(dev)) {
14408                         /* eDP not supported on port D, so don't check VBT */
14409                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14410                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14411                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14412                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14413                 }
14414
14415                 intel_dsi_init(dev);
14416         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14417                 bool found = false;
14418
14419                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14420                         DRM_DEBUG_KMS("probing SDVOB\n");
14421                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14422                         if (!found && IS_G4X(dev)) {
14423                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14424                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14425                         }
14426
14427                         if (!found && IS_G4X(dev))
14428                                 intel_dp_init(dev, DP_B, PORT_B);
14429                 }
14430
14431                 /* Before G4X SDVOC doesn't have its own detect register */
14432
14433                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14434                         DRM_DEBUG_KMS("probing SDVOC\n");
14435                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14436                 }
14437
14438                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14439
14440                         if (IS_G4X(dev)) {
14441                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14442                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14443                         }
14444                         if (IS_G4X(dev))
14445                                 intel_dp_init(dev, DP_C, PORT_C);
14446                 }
14447
14448                 if (IS_G4X(dev) &&
14449                     (I915_READ(DP_D) & DP_DETECTED))
14450                         intel_dp_init(dev, DP_D, PORT_D);
14451         } else if (IS_GEN2(dev))
14452                 intel_dvo_init(dev);
14453
14454         if (SUPPORTS_TV(dev))
14455                 intel_tv_init(dev);
14456
14457         intel_psr_init(dev);
14458
14459         for_each_intel_encoder(dev, encoder) {
14460                 encoder->base.possible_crtcs = encoder->crtc_mask;
14461                 encoder->base.possible_clones =
14462                         intel_encoder_clones(encoder);
14463         }
14464
14465         intel_init_pch_refclk(dev);
14466
14467         drm_helper_move_panel_connectors_to_head(dev);
14468 }
14469
14470 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14471 {
14472         struct drm_device *dev = fb->dev;
14473         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14474
14475         drm_framebuffer_cleanup(fb);
14476         mutex_lock(&dev->struct_mutex);
14477         WARN_ON(!intel_fb->obj->framebuffer_references--);
14478         drm_gem_object_unreference(&intel_fb->obj->base);
14479         mutex_unlock(&dev->struct_mutex);
14480         kfree(intel_fb);
14481 }
14482
14483 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14484                                                 struct drm_file *file,
14485                                                 unsigned int *handle)
14486 {
14487         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14488         struct drm_i915_gem_object *obj = intel_fb->obj;
14489
14490         if (obj->userptr.mm) {
14491                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14492                 return -EINVAL;
14493         }
14494
14495         return drm_gem_handle_create(file, &obj->base, handle);
14496 }
14497
14498 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14499                                         struct drm_file *file,
14500                                         unsigned flags, unsigned color,
14501                                         struct drm_clip_rect *clips,
14502                                         unsigned num_clips)
14503 {
14504         struct drm_device *dev = fb->dev;
14505         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14506         struct drm_i915_gem_object *obj = intel_fb->obj;
14507
14508         mutex_lock(&dev->struct_mutex);
14509         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14510         mutex_unlock(&dev->struct_mutex);
14511
14512         return 0;
14513 }
14514
14515 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14516         .destroy = intel_user_framebuffer_destroy,
14517         .create_handle = intel_user_framebuffer_create_handle,
14518         .dirty = intel_user_framebuffer_dirty,
14519 };
14520
14521 static
14522 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14523                          uint32_t pixel_format)
14524 {
14525         u32 gen = INTEL_INFO(dev)->gen;
14526
14527         if (gen >= 9) {
14528                 /* "The stride in bytes must not exceed the of the size of 8K
14529                  *  pixels and 32K bytes."
14530                  */
14531                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14532         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14533                 return 32*1024;
14534         } else if (gen >= 4) {
14535                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14536                         return 16*1024;
14537                 else
14538                         return 32*1024;
14539         } else if (gen >= 3) {
14540                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14541                         return 8*1024;
14542                 else
14543                         return 16*1024;
14544         } else {
14545                 /* XXX DSPC is limited to 4k tiled */
14546                 return 8*1024;
14547         }
14548 }
14549
14550 static int intel_framebuffer_init(struct drm_device *dev,
14551                                   struct intel_framebuffer *intel_fb,
14552                                   struct drm_mode_fb_cmd2 *mode_cmd,
14553                                   struct drm_i915_gem_object *obj)
14554 {
14555         unsigned int aligned_height;
14556         int ret;
14557         u32 pitch_limit, stride_alignment;
14558
14559         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14560
14561         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14562                 /* Enforce that fb modifier and tiling mode match, but only for
14563                  * X-tiled. This is needed for FBC. */
14564                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14565                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14566                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14567                         return -EINVAL;
14568                 }
14569         } else {
14570                 if (obj->tiling_mode == I915_TILING_X)
14571                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14572                 else if (obj->tiling_mode == I915_TILING_Y) {
14573                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14574                         return -EINVAL;
14575                 }
14576         }
14577
14578         /* Passed in modifier sanity checking. */
14579         switch (mode_cmd->modifier[0]) {
14580         case I915_FORMAT_MOD_Y_TILED:
14581         case I915_FORMAT_MOD_Yf_TILED:
14582                 if (INTEL_INFO(dev)->gen < 9) {
14583                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14584                                   mode_cmd->modifier[0]);
14585                         return -EINVAL;
14586                 }
14587         case DRM_FORMAT_MOD_NONE:
14588         case I915_FORMAT_MOD_X_TILED:
14589                 break;
14590         default:
14591                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14592                           mode_cmd->modifier[0]);
14593                 return -EINVAL;
14594         }
14595
14596         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14597                                                      mode_cmd->pixel_format);
14598         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14599                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14600                           mode_cmd->pitches[0], stride_alignment);
14601                 return -EINVAL;
14602         }
14603
14604         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14605                                            mode_cmd->pixel_format);
14606         if (mode_cmd->pitches[0] > pitch_limit) {
14607                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14608                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14609                           "tiled" : "linear",
14610                           mode_cmd->pitches[0], pitch_limit);
14611                 return -EINVAL;
14612         }
14613
14614         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14615             mode_cmd->pitches[0] != obj->stride) {
14616                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14617                           mode_cmd->pitches[0], obj->stride);
14618                 return -EINVAL;
14619         }
14620
14621         /* Reject formats not supported by any plane early. */
14622         switch (mode_cmd->pixel_format) {
14623         case DRM_FORMAT_C8:
14624         case DRM_FORMAT_RGB565:
14625         case DRM_FORMAT_XRGB8888:
14626         case DRM_FORMAT_ARGB8888:
14627                 break;
14628         case DRM_FORMAT_XRGB1555:
14629                 if (INTEL_INFO(dev)->gen > 3) {
14630                         DRM_DEBUG("unsupported pixel format: %s\n",
14631                                   drm_get_format_name(mode_cmd->pixel_format));
14632                         return -EINVAL;
14633                 }
14634                 break;
14635         case DRM_FORMAT_ABGR8888:
14636                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14637                         DRM_DEBUG("unsupported pixel format: %s\n",
14638                                   drm_get_format_name(mode_cmd->pixel_format));
14639                         return -EINVAL;
14640                 }
14641                 break;
14642         case DRM_FORMAT_XBGR8888:
14643         case DRM_FORMAT_XRGB2101010:
14644         case DRM_FORMAT_XBGR2101010:
14645                 if (INTEL_INFO(dev)->gen < 4) {
14646                         DRM_DEBUG("unsupported pixel format: %s\n",
14647                                   drm_get_format_name(mode_cmd->pixel_format));
14648                         return -EINVAL;
14649                 }
14650                 break;
14651         case DRM_FORMAT_ABGR2101010:
14652                 if (!IS_VALLEYVIEW(dev)) {
14653                         DRM_DEBUG("unsupported pixel format: %s\n",
14654                                   drm_get_format_name(mode_cmd->pixel_format));
14655                         return -EINVAL;
14656                 }
14657                 break;
14658         case DRM_FORMAT_YUYV:
14659         case DRM_FORMAT_UYVY:
14660         case DRM_FORMAT_YVYU:
14661         case DRM_FORMAT_VYUY:
14662                 if (INTEL_INFO(dev)->gen < 5) {
14663                         DRM_DEBUG("unsupported pixel format: %s\n",
14664                                   drm_get_format_name(mode_cmd->pixel_format));
14665                         return -EINVAL;
14666                 }
14667                 break;
14668         default:
14669                 DRM_DEBUG("unsupported pixel format: %s\n",
14670                           drm_get_format_name(mode_cmd->pixel_format));
14671                 return -EINVAL;
14672         }
14673
14674         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14675         if (mode_cmd->offsets[0] != 0)
14676                 return -EINVAL;
14677
14678         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14679                                                mode_cmd->pixel_format,
14680                                                mode_cmd->modifier[0]);
14681         /* FIXME drm helper for size checks (especially planar formats)? */
14682         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14683                 return -EINVAL;
14684
14685         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14686         intel_fb->obj = obj;
14687         intel_fb->obj->framebuffer_references++;
14688
14689         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14690         if (ret) {
14691                 DRM_ERROR("framebuffer init failed %d\n", ret);
14692                 return ret;
14693         }
14694
14695         return 0;
14696 }
14697
14698 static struct drm_framebuffer *
14699 intel_user_framebuffer_create(struct drm_device *dev,
14700                               struct drm_file *filp,
14701                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14702 {
14703         struct drm_framebuffer *fb;
14704         struct drm_i915_gem_object *obj;
14705         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14706
14707         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14708                                                 mode_cmd.handles[0]));
14709         if (&obj->base == NULL)
14710                 return ERR_PTR(-ENOENT);
14711
14712         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14713         if (IS_ERR(fb))
14714                 drm_gem_object_unreference_unlocked(&obj->base);
14715
14716         return fb;
14717 }
14718
14719 #ifndef CONFIG_DRM_FBDEV_EMULATION
14720 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14721 {
14722 }
14723 #endif
14724
14725 static const struct drm_mode_config_funcs intel_mode_funcs = {
14726         .fb_create = intel_user_framebuffer_create,
14727         .output_poll_changed = intel_fbdev_output_poll_changed,
14728         .atomic_check = intel_atomic_check,
14729         .atomic_commit = intel_atomic_commit,
14730         .atomic_state_alloc = intel_atomic_state_alloc,
14731         .atomic_state_clear = intel_atomic_state_clear,
14732 };
14733
14734 /* Set up chip specific display functions */
14735 static void intel_init_display(struct drm_device *dev)
14736 {
14737         struct drm_i915_private *dev_priv = dev->dev_private;
14738
14739         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14740                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14741         else if (IS_CHERRYVIEW(dev))
14742                 dev_priv->display.find_dpll = chv_find_best_dpll;
14743         else if (IS_VALLEYVIEW(dev))
14744                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14745         else if (IS_PINEVIEW(dev))
14746                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14747         else
14748                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14749
14750         if (INTEL_INFO(dev)->gen >= 9) {
14751                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14752                 dev_priv->display.get_initial_plane_config =
14753                         skylake_get_initial_plane_config;
14754                 dev_priv->display.crtc_compute_clock =
14755                         haswell_crtc_compute_clock;
14756                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14757                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14758                 dev_priv->display.update_primary_plane =
14759                         skylake_update_primary_plane;
14760         } else if (HAS_DDI(dev)) {
14761                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14762                 dev_priv->display.get_initial_plane_config =
14763                         ironlake_get_initial_plane_config;
14764                 dev_priv->display.crtc_compute_clock =
14765                         haswell_crtc_compute_clock;
14766                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14767                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14768                 dev_priv->display.update_primary_plane =
14769                         ironlake_update_primary_plane;
14770         } else if (HAS_PCH_SPLIT(dev)) {
14771                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14772                 dev_priv->display.get_initial_plane_config =
14773                         ironlake_get_initial_plane_config;
14774                 dev_priv->display.crtc_compute_clock =
14775                         ironlake_crtc_compute_clock;
14776                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14777                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14778                 dev_priv->display.update_primary_plane =
14779                         ironlake_update_primary_plane;
14780         } else if (IS_VALLEYVIEW(dev)) {
14781                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14782                 dev_priv->display.get_initial_plane_config =
14783                         i9xx_get_initial_plane_config;
14784                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14785                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14786                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14787                 dev_priv->display.update_primary_plane =
14788                         i9xx_update_primary_plane;
14789         } else {
14790                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14791                 dev_priv->display.get_initial_plane_config =
14792                         i9xx_get_initial_plane_config;
14793                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14794                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14795                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14796                 dev_priv->display.update_primary_plane =
14797                         i9xx_update_primary_plane;
14798         }
14799
14800         /* Returns the core display clock speed */
14801         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14802                 dev_priv->display.get_display_clock_speed =
14803                         skylake_get_display_clock_speed;
14804         else if (IS_BROXTON(dev))
14805                 dev_priv->display.get_display_clock_speed =
14806                         broxton_get_display_clock_speed;
14807         else if (IS_BROADWELL(dev))
14808                 dev_priv->display.get_display_clock_speed =
14809                         broadwell_get_display_clock_speed;
14810         else if (IS_HASWELL(dev))
14811                 dev_priv->display.get_display_clock_speed =
14812                         haswell_get_display_clock_speed;
14813         else if (IS_VALLEYVIEW(dev))
14814                 dev_priv->display.get_display_clock_speed =
14815                         valleyview_get_display_clock_speed;
14816         else if (IS_GEN5(dev))
14817                 dev_priv->display.get_display_clock_speed =
14818                         ilk_get_display_clock_speed;
14819         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14820                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14821                 dev_priv->display.get_display_clock_speed =
14822                         i945_get_display_clock_speed;
14823         else if (IS_GM45(dev))
14824                 dev_priv->display.get_display_clock_speed =
14825                         gm45_get_display_clock_speed;
14826         else if (IS_CRESTLINE(dev))
14827                 dev_priv->display.get_display_clock_speed =
14828                         i965gm_get_display_clock_speed;
14829         else if (IS_PINEVIEW(dev))
14830                 dev_priv->display.get_display_clock_speed =
14831                         pnv_get_display_clock_speed;
14832         else if (IS_G33(dev) || IS_G4X(dev))
14833                 dev_priv->display.get_display_clock_speed =
14834                         g33_get_display_clock_speed;
14835         else if (IS_I915G(dev))
14836                 dev_priv->display.get_display_clock_speed =
14837                         i915_get_display_clock_speed;
14838         else if (IS_I945GM(dev) || IS_845G(dev))
14839                 dev_priv->display.get_display_clock_speed =
14840                         i9xx_misc_get_display_clock_speed;
14841         else if (IS_I915GM(dev))
14842                 dev_priv->display.get_display_clock_speed =
14843                         i915gm_get_display_clock_speed;
14844         else if (IS_I865G(dev))
14845                 dev_priv->display.get_display_clock_speed =
14846                         i865_get_display_clock_speed;
14847         else if (IS_I85X(dev))
14848                 dev_priv->display.get_display_clock_speed =
14849                         i85x_get_display_clock_speed;
14850         else { /* 830 */
14851                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14852                 dev_priv->display.get_display_clock_speed =
14853                         i830_get_display_clock_speed;
14854         }
14855
14856         if (IS_GEN5(dev)) {
14857                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14858         } else if (IS_GEN6(dev)) {
14859                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14860         } else if (IS_IVYBRIDGE(dev)) {
14861                 /* FIXME: detect B0+ stepping and use auto training */
14862                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14863         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14864                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14865                 if (IS_BROADWELL(dev)) {
14866                         dev_priv->display.modeset_commit_cdclk =
14867                                 broadwell_modeset_commit_cdclk;
14868                         dev_priv->display.modeset_calc_cdclk =
14869                                 broadwell_modeset_calc_cdclk;
14870                 }
14871         } else if (IS_VALLEYVIEW(dev)) {
14872                 dev_priv->display.modeset_commit_cdclk =
14873                         valleyview_modeset_commit_cdclk;
14874                 dev_priv->display.modeset_calc_cdclk =
14875                         valleyview_modeset_calc_cdclk;
14876         } else if (IS_BROXTON(dev)) {
14877                 dev_priv->display.modeset_commit_cdclk =
14878                         broxton_modeset_commit_cdclk;
14879                 dev_priv->display.modeset_calc_cdclk =
14880                         broxton_modeset_calc_cdclk;
14881         }
14882
14883         switch (INTEL_INFO(dev)->gen) {
14884         case 2:
14885                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14886                 break;
14887
14888         case 3:
14889                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14890                 break;
14891
14892         case 4:
14893         case 5:
14894                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14895                 break;
14896
14897         case 6:
14898                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14899                 break;
14900         case 7:
14901         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14902                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14903                 break;
14904         case 9:
14905                 /* Drop through - unsupported since execlist only. */
14906         default:
14907                 /* Default just returns -ENODEV to indicate unsupported */
14908                 dev_priv->display.queue_flip = intel_default_queue_flip;
14909         }
14910
14911         mutex_init(&dev_priv->pps_mutex);
14912 }
14913
14914 /*
14915  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14916  * resume, or other times.  This quirk makes sure that's the case for
14917  * affected systems.
14918  */
14919 static void quirk_pipea_force(struct drm_device *dev)
14920 {
14921         struct drm_i915_private *dev_priv = dev->dev_private;
14922
14923         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14924         DRM_INFO("applying pipe a force quirk\n");
14925 }
14926
14927 static void quirk_pipeb_force(struct drm_device *dev)
14928 {
14929         struct drm_i915_private *dev_priv = dev->dev_private;
14930
14931         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14932         DRM_INFO("applying pipe b force quirk\n");
14933 }
14934
14935 /*
14936  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14937  */
14938 static void quirk_ssc_force_disable(struct drm_device *dev)
14939 {
14940         struct drm_i915_private *dev_priv = dev->dev_private;
14941         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14942         DRM_INFO("applying lvds SSC disable quirk\n");
14943 }
14944
14945 /*
14946  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14947  * brightness value
14948  */
14949 static void quirk_invert_brightness(struct drm_device *dev)
14950 {
14951         struct drm_i915_private *dev_priv = dev->dev_private;
14952         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14953         DRM_INFO("applying inverted panel brightness quirk\n");
14954 }
14955
14956 /* Some VBT's incorrectly indicate no backlight is present */
14957 static void quirk_backlight_present(struct drm_device *dev)
14958 {
14959         struct drm_i915_private *dev_priv = dev->dev_private;
14960         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14961         DRM_INFO("applying backlight present quirk\n");
14962 }
14963
14964 struct intel_quirk {
14965         int device;
14966         int subsystem_vendor;
14967         int subsystem_device;
14968         void (*hook)(struct drm_device *dev);
14969 };
14970
14971 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14972 struct intel_dmi_quirk {
14973         void (*hook)(struct drm_device *dev);
14974         const struct dmi_system_id (*dmi_id_list)[];
14975 };
14976
14977 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14978 {
14979         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14980         return 1;
14981 }
14982
14983 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14984         {
14985                 .dmi_id_list = &(const struct dmi_system_id[]) {
14986                         {
14987                                 .callback = intel_dmi_reverse_brightness,
14988                                 .ident = "NCR Corporation",
14989                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14990                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14991                                 },
14992                         },
14993                         { }  /* terminating entry */
14994                 },
14995                 .hook = quirk_invert_brightness,
14996         },
14997 };
14998
14999 static struct intel_quirk intel_quirks[] = {
15000         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15001         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15002
15003         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15004         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15005
15006         /* 830 needs to leave pipe A & dpll A up */
15007         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15008
15009         /* 830 needs to leave pipe B & dpll B up */
15010         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15011
15012         /* Lenovo U160 cannot use SSC on LVDS */
15013         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15014
15015         /* Sony Vaio Y cannot use SSC on LVDS */
15016         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15017
15018         /* Acer Aspire 5734Z must invert backlight brightness */
15019         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15020
15021         /* Acer/eMachines G725 */
15022         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15023
15024         /* Acer/eMachines e725 */
15025         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15026
15027         /* Acer/Packard Bell NCL20 */
15028         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15029
15030         /* Acer Aspire 4736Z */
15031         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15032
15033         /* Acer Aspire 5336 */
15034         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15035
15036         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15037         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15038
15039         /* Acer C720 Chromebook (Core i3 4005U) */
15040         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15041
15042         /* Apple Macbook 2,1 (Core 2 T7400) */
15043         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15044
15045         /* Apple Macbook 4,1 */
15046         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15047
15048         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15049         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15050
15051         /* HP Chromebook 14 (Celeron 2955U) */
15052         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15053
15054         /* Dell Chromebook 11 */
15055         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15056
15057         /* Dell Chromebook 11 (2015 version) */
15058         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15059 };
15060
15061 static void intel_init_quirks(struct drm_device *dev)
15062 {
15063         struct pci_dev *d = dev->pdev;
15064         int i;
15065
15066         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15067                 struct intel_quirk *q = &intel_quirks[i];
15068
15069                 if (d->device == q->device &&
15070                     (d->subsystem_vendor == q->subsystem_vendor ||
15071                      q->subsystem_vendor == PCI_ANY_ID) &&
15072                     (d->subsystem_device == q->subsystem_device ||
15073                      q->subsystem_device == PCI_ANY_ID))
15074                         q->hook(dev);
15075         }
15076         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15077                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15078                         intel_dmi_quirks[i].hook(dev);
15079         }
15080 }
15081
15082 /* Disable the VGA plane that we never use */
15083 static void i915_disable_vga(struct drm_device *dev)
15084 {
15085         struct drm_i915_private *dev_priv = dev->dev_private;
15086         u8 sr1;
15087         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15088
15089         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15090         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15091         outb(SR01, VGA_SR_INDEX);
15092         sr1 = inb(VGA_SR_DATA);
15093         outb(sr1 | 1<<5, VGA_SR_DATA);
15094         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15095         udelay(300);
15096
15097         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15098         POSTING_READ(vga_reg);
15099 }
15100
15101 void intel_modeset_init_hw(struct drm_device *dev)
15102 {
15103         intel_update_cdclk(dev);
15104         intel_prepare_ddi(dev);
15105         intel_init_clock_gating(dev);
15106         intel_enable_gt_powersave(dev);
15107 }
15108
15109 void intel_modeset_init(struct drm_device *dev)
15110 {
15111         struct drm_i915_private *dev_priv = dev->dev_private;
15112         int sprite, ret;
15113         enum pipe pipe;
15114         struct intel_crtc *crtc;
15115
15116         drm_mode_config_init(dev);
15117
15118         dev->mode_config.min_width = 0;
15119         dev->mode_config.min_height = 0;
15120
15121         dev->mode_config.preferred_depth = 24;
15122         dev->mode_config.prefer_shadow = 1;
15123
15124         dev->mode_config.allow_fb_modifiers = true;
15125
15126         dev->mode_config.funcs = &intel_mode_funcs;
15127
15128         intel_init_quirks(dev);
15129
15130         intel_init_pm(dev);
15131
15132         if (INTEL_INFO(dev)->num_pipes == 0)
15133                 return;
15134
15135         /*
15136          * There may be no VBT; and if the BIOS enabled SSC we can
15137          * just keep using it to avoid unnecessary flicker.  Whereas if the
15138          * BIOS isn't using it, don't assume it will work even if the VBT
15139          * indicates as much.
15140          */
15141         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15142                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15143                                             DREF_SSC1_ENABLE);
15144
15145                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15146                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15147                                      bios_lvds_use_ssc ? "en" : "dis",
15148                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15149                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15150                 }
15151         }
15152
15153         intel_init_display(dev);
15154         intel_init_audio(dev);
15155
15156         if (IS_GEN2(dev)) {
15157                 dev->mode_config.max_width = 2048;
15158                 dev->mode_config.max_height = 2048;
15159         } else if (IS_GEN3(dev)) {
15160                 dev->mode_config.max_width = 4096;
15161                 dev->mode_config.max_height = 4096;
15162         } else {
15163                 dev->mode_config.max_width = 8192;
15164                 dev->mode_config.max_height = 8192;
15165         }
15166
15167         if (IS_845G(dev) || IS_I865G(dev)) {
15168                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15169                 dev->mode_config.cursor_height = 1023;
15170         } else if (IS_GEN2(dev)) {
15171                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15172                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15173         } else {
15174                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15175                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15176         }
15177
15178         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15179
15180         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15181                       INTEL_INFO(dev)->num_pipes,
15182                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15183
15184         for_each_pipe(dev_priv, pipe) {
15185                 intel_crtc_init(dev, pipe);
15186                 for_each_sprite(dev_priv, pipe, sprite) {
15187                         ret = intel_plane_init(dev, pipe, sprite);
15188                         if (ret)
15189                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15190                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15191                 }
15192         }
15193
15194         intel_update_czclk(dev_priv);
15195         intel_update_cdclk(dev);
15196
15197         intel_shared_dpll_init(dev);
15198
15199         /* Just disable it once at startup */
15200         i915_disable_vga(dev);
15201         intel_setup_outputs(dev);
15202
15203         drm_modeset_lock_all(dev);
15204         intel_modeset_setup_hw_state(dev);
15205         drm_modeset_unlock_all(dev);
15206
15207         for_each_intel_crtc(dev, crtc) {
15208                 struct intel_initial_plane_config plane_config = {};
15209
15210                 if (!crtc->active)
15211                         continue;
15212
15213                 /*
15214                  * Note that reserving the BIOS fb up front prevents us
15215                  * from stuffing other stolen allocations like the ring
15216                  * on top.  This prevents some ugliness at boot time, and
15217                  * can even allow for smooth boot transitions if the BIOS
15218                  * fb is large enough for the active pipe configuration.
15219                  */
15220                 dev_priv->display.get_initial_plane_config(crtc,
15221                                                            &plane_config);
15222
15223                 /*
15224                  * If the fb is shared between multiple heads, we'll
15225                  * just get the first one.
15226                  */
15227                 intel_find_initial_plane_obj(crtc, &plane_config);
15228         }
15229 }
15230
15231 static void intel_enable_pipe_a(struct drm_device *dev)
15232 {
15233         struct intel_connector *connector;
15234         struct drm_connector *crt = NULL;
15235         struct intel_load_detect_pipe load_detect_temp;
15236         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15237
15238         /* We can't just switch on the pipe A, we need to set things up with a
15239          * proper mode and output configuration. As a gross hack, enable pipe A
15240          * by enabling the load detect pipe once. */
15241         for_each_intel_connector(dev, connector) {
15242                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15243                         crt = &connector->base;
15244                         break;
15245                 }
15246         }
15247
15248         if (!crt)
15249                 return;
15250
15251         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15252                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15253 }
15254
15255 static bool
15256 intel_check_plane_mapping(struct intel_crtc *crtc)
15257 {
15258         struct drm_device *dev = crtc->base.dev;
15259         struct drm_i915_private *dev_priv = dev->dev_private;
15260         u32 val;
15261
15262         if (INTEL_INFO(dev)->num_pipes == 1)
15263                 return true;
15264
15265         val = I915_READ(DSPCNTR(!crtc->plane));
15266
15267         if ((val & DISPLAY_PLANE_ENABLE) &&
15268             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15269                 return false;
15270
15271         return true;
15272 }
15273
15274 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15275 {
15276         struct drm_device *dev = crtc->base.dev;
15277         struct intel_encoder *encoder;
15278
15279         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15280                 return true;
15281
15282         return false;
15283 }
15284
15285 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15286 {
15287         struct drm_device *dev = crtc->base.dev;
15288         struct drm_i915_private *dev_priv = dev->dev_private;
15289         i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15290
15291         /* Clear any frame start delays used for debugging left by the BIOS */
15292         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15293
15294         /* restore vblank interrupts to correct state */
15295         drm_crtc_vblank_reset(&crtc->base);
15296         if (crtc->active) {
15297                 struct intel_plane *plane;
15298
15299                 drm_crtc_vblank_on(&crtc->base);
15300
15301                 /* Disable everything but the primary plane */
15302                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15303                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15304                                 continue;
15305
15306                         plane->disable_plane(&plane->base, &crtc->base);
15307                 }
15308         }
15309
15310         /* We need to sanitize the plane -> pipe mapping first because this will
15311          * disable the crtc (and hence change the state) if it is wrong. Note
15312          * that gen4+ has a fixed plane -> pipe mapping.  */
15313         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15314                 bool plane;
15315
15316                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15317                               crtc->base.base.id);
15318
15319                 /* Pipe has the wrong plane attached and the plane is active.
15320                  * Temporarily change the plane mapping and disable everything
15321                  * ...  */
15322                 plane = crtc->plane;
15323                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15324                 crtc->plane = !plane;
15325                 intel_crtc_disable_noatomic(&crtc->base);
15326                 crtc->plane = plane;
15327         }
15328
15329         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15330             crtc->pipe == PIPE_A && !crtc->active) {
15331                 /* BIOS forgot to enable pipe A, this mostly happens after
15332                  * resume. Force-enable the pipe to fix this, the update_dpms
15333                  * call below we restore the pipe to the right state, but leave
15334                  * the required bits on. */
15335                 intel_enable_pipe_a(dev);
15336         }
15337
15338         /* Adjust the state of the output pipe according to whether we
15339          * have active connectors/encoders. */
15340         if (!intel_crtc_has_encoders(crtc))
15341                 intel_crtc_disable_noatomic(&crtc->base);
15342
15343         if (crtc->active != crtc->base.state->active) {
15344                 struct intel_encoder *encoder;
15345
15346                 /* This can happen either due to bugs in the get_hw_state
15347                  * functions or because of calls to intel_crtc_disable_noatomic,
15348                  * or because the pipe is force-enabled due to the
15349                  * pipe A quirk. */
15350                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15351                               crtc->base.base.id,
15352                               crtc->base.state->enable ? "enabled" : "disabled",
15353                               crtc->active ? "enabled" : "disabled");
15354
15355                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15356                 crtc->base.state->active = crtc->active;
15357                 crtc->base.enabled = crtc->active;
15358
15359                 /* Because we only establish the connector -> encoder ->
15360                  * crtc links if something is active, this means the
15361                  * crtc is now deactivated. Break the links. connector
15362                  * -> encoder links are only establish when things are
15363                  *  actually up, hence no need to break them. */
15364                 WARN_ON(crtc->active);
15365
15366                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15367                         encoder->base.crtc = NULL;
15368         }
15369
15370         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15371                 /*
15372                  * We start out with underrun reporting disabled to avoid races.
15373                  * For correct bookkeeping mark this on active crtcs.
15374                  *
15375                  * Also on gmch platforms we dont have any hardware bits to
15376                  * disable the underrun reporting. Which means we need to start
15377                  * out with underrun reporting disabled also on inactive pipes,
15378                  * since otherwise we'll complain about the garbage we read when
15379                  * e.g. coming up after runtime pm.
15380                  *
15381                  * No protection against concurrent access is required - at
15382                  * worst a fifo underrun happens which also sets this to false.
15383                  */
15384                 crtc->cpu_fifo_underrun_disabled = true;
15385                 crtc->pch_fifo_underrun_disabled = true;
15386         }
15387 }
15388
15389 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15390 {
15391         struct intel_connector *connector;
15392         struct drm_device *dev = encoder->base.dev;
15393         bool active = false;
15394
15395         /* We need to check both for a crtc link (meaning that the
15396          * encoder is active and trying to read from a pipe) and the
15397          * pipe itself being active. */
15398         bool has_active_crtc = encoder->base.crtc &&
15399                 to_intel_crtc(encoder->base.crtc)->active;
15400
15401         for_each_intel_connector(dev, connector) {
15402                 if (connector->base.encoder != &encoder->base)
15403                         continue;
15404
15405                 active = true;
15406                 break;
15407         }
15408
15409         if (active && !has_active_crtc) {
15410                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15411                               encoder->base.base.id,
15412                               encoder->base.name);
15413
15414                 /* Connector is active, but has no active pipe. This is
15415                  * fallout from our resume register restoring. Disable
15416                  * the encoder manually again. */
15417                 if (encoder->base.crtc) {
15418                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15419                                       encoder->base.base.id,
15420                                       encoder->base.name);
15421                         encoder->disable(encoder);
15422                         if (encoder->post_disable)
15423                                 encoder->post_disable(encoder);
15424                 }
15425                 encoder->base.crtc = NULL;
15426
15427                 /* Inconsistent output/port/pipe state happens presumably due to
15428                  * a bug in one of the get_hw_state functions. Or someplace else
15429                  * in our code, like the register restore mess on resume. Clamp
15430                  * things to off as a safer default. */
15431                 for_each_intel_connector(dev, connector) {
15432                         if (connector->encoder != encoder)
15433                                 continue;
15434                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15435                         connector->base.encoder = NULL;
15436                 }
15437         }
15438         /* Enabled encoders without active connectors will be fixed in
15439          * the crtc fixup. */
15440 }
15441
15442 void i915_redisable_vga_power_on(struct drm_device *dev)
15443 {
15444         struct drm_i915_private *dev_priv = dev->dev_private;
15445         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15446
15447         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15448                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15449                 i915_disable_vga(dev);
15450         }
15451 }
15452
15453 void i915_redisable_vga(struct drm_device *dev)
15454 {
15455         struct drm_i915_private *dev_priv = dev->dev_private;
15456
15457         /* This function can be called both from intel_modeset_setup_hw_state or
15458          * at a very early point in our resume sequence, where the power well
15459          * structures are not yet restored. Since this function is at a very
15460          * paranoid "someone might have enabled VGA while we were not looking"
15461          * level, just check if the power well is enabled instead of trying to
15462          * follow the "don't touch the power well if we don't need it" policy
15463          * the rest of the driver uses. */
15464         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15465                 return;
15466
15467         i915_redisable_vga_power_on(dev);
15468 }
15469
15470 static bool primary_get_hw_state(struct intel_plane *plane)
15471 {
15472         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15473
15474         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15475 }
15476
15477 /* FIXME read out full plane state for all planes */
15478 static void readout_plane_state(struct intel_crtc *crtc)
15479 {
15480         struct drm_plane *primary = crtc->base.primary;
15481         struct intel_plane_state *plane_state =
15482                 to_intel_plane_state(primary->state);
15483
15484         plane_state->visible = crtc->active &&
15485                 primary_get_hw_state(to_intel_plane(primary));
15486
15487         if (plane_state->visible)
15488                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15489 }
15490
15491 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15492 {
15493         struct drm_i915_private *dev_priv = dev->dev_private;
15494         enum pipe pipe;
15495         struct intel_crtc *crtc;
15496         struct intel_encoder *encoder;
15497         struct intel_connector *connector;
15498         int i;
15499
15500         for_each_intel_crtc(dev, crtc) {
15501                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15502                 memset(crtc->config, 0, sizeof(*crtc->config));
15503                 crtc->config->base.crtc = &crtc->base;
15504
15505                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15506                                                                  crtc->config);
15507
15508                 crtc->base.state->active = crtc->active;
15509                 crtc->base.enabled = crtc->active;
15510
15511                 readout_plane_state(crtc);
15512
15513                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15514                               crtc->base.base.id,
15515                               crtc->active ? "enabled" : "disabled");
15516         }
15517
15518         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15519                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15520
15521                 pll->on = pll->get_hw_state(dev_priv, pll,
15522                                             &pll->config.hw_state);
15523                 pll->active = 0;
15524                 pll->config.crtc_mask = 0;
15525                 for_each_intel_crtc(dev, crtc) {
15526                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15527                                 pll->active++;
15528                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15529                         }
15530                 }
15531
15532                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15533                               pll->name, pll->config.crtc_mask, pll->on);
15534
15535                 if (pll->config.crtc_mask)
15536                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15537         }
15538
15539         for_each_intel_encoder(dev, encoder) {
15540                 pipe = 0;
15541
15542                 if (encoder->get_hw_state(encoder, &pipe)) {
15543                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15544                         encoder->base.crtc = &crtc->base;
15545                         encoder->get_config(encoder, crtc->config);
15546                 } else {
15547                         encoder->base.crtc = NULL;
15548                 }
15549
15550                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15551                               encoder->base.base.id,
15552                               encoder->base.name,
15553                               encoder->base.crtc ? "enabled" : "disabled",
15554                               pipe_name(pipe));
15555         }
15556
15557         for_each_intel_connector(dev, connector) {
15558                 if (connector->get_hw_state(connector)) {
15559                         connector->base.dpms = DRM_MODE_DPMS_ON;
15560                         connector->base.encoder = &connector->encoder->base;
15561                 } else {
15562                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15563                         connector->base.encoder = NULL;
15564                 }
15565                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15566                               connector->base.base.id,
15567                               connector->base.name,
15568                               connector->base.encoder ? "enabled" : "disabled");
15569         }
15570
15571         for_each_intel_crtc(dev, crtc) {
15572                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15573
15574                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15575                 if (crtc->base.state->active) {
15576                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15577                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15578                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15579
15580                         /*
15581                          * The initial mode needs to be set in order to keep
15582                          * the atomic core happy. It wants a valid mode if the
15583                          * crtc's enabled, so we do the above call.
15584                          *
15585                          * At this point some state updated by the connectors
15586                          * in their ->detect() callback has not run yet, so
15587                          * no recalculation can be done yet.
15588                          *
15589                          * Even if we could do a recalculation and modeset
15590                          * right now it would cause a double modeset if
15591                          * fbdev or userspace chooses a different initial mode.
15592                          *
15593                          * If that happens, someone indicated they wanted a
15594                          * mode change, which means it's safe to do a full
15595                          * recalculation.
15596                          */
15597                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15598
15599                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15600                         update_scanline_offset(crtc);
15601                 }
15602         }
15603 }
15604
15605 /* Scan out the current hw modeset state,
15606  * and sanitizes it to the current state
15607  */
15608 static void
15609 intel_modeset_setup_hw_state(struct drm_device *dev)
15610 {
15611         struct drm_i915_private *dev_priv = dev->dev_private;
15612         enum pipe pipe;
15613         struct intel_crtc *crtc;
15614         struct intel_encoder *encoder;
15615         int i;
15616
15617         intel_modeset_readout_hw_state(dev);
15618
15619         /* HW state is read out, now we need to sanitize this mess. */
15620         for_each_intel_encoder(dev, encoder) {
15621                 intel_sanitize_encoder(encoder);
15622         }
15623
15624         for_each_pipe(dev_priv, pipe) {
15625                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15626                 intel_sanitize_crtc(crtc);
15627                 intel_dump_pipe_config(crtc, crtc->config,
15628                                        "[setup_hw_state]");
15629         }
15630
15631         intel_modeset_update_connector_atomic_state(dev);
15632
15633         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15634                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15635
15636                 if (!pll->on || pll->active)
15637                         continue;
15638
15639                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15640
15641                 pll->disable(dev_priv, pll);
15642                 pll->on = false;
15643         }
15644
15645         if (IS_VALLEYVIEW(dev))
15646                 vlv_wm_get_hw_state(dev);
15647         else if (IS_GEN9(dev))
15648                 skl_wm_get_hw_state(dev);
15649         else if (HAS_PCH_SPLIT(dev))
15650                 ilk_wm_get_hw_state(dev);
15651
15652         for_each_intel_crtc(dev, crtc) {
15653                 unsigned long put_domains;
15654
15655                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15656                 if (WARN_ON(put_domains))
15657                         modeset_put_power_domains(dev_priv, put_domains);
15658         }
15659         intel_display_set_init_power(dev_priv, false);
15660 }
15661
15662 void intel_display_resume(struct drm_device *dev)
15663 {
15664         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15665         struct intel_connector *conn;
15666         struct intel_plane *plane;
15667         struct drm_crtc *crtc;
15668         int ret;
15669
15670         if (!state)
15671                 return;
15672
15673         state->acquire_ctx = dev->mode_config.acquire_ctx;
15674
15675         /* preserve complete old state, including dpll */
15676         intel_atomic_get_shared_dpll_state(state);
15677
15678         for_each_crtc(dev, crtc) {
15679                 struct drm_crtc_state *crtc_state =
15680                         drm_atomic_get_crtc_state(state, crtc);
15681
15682                 ret = PTR_ERR_OR_ZERO(crtc_state);
15683                 if (ret)
15684                         goto err;
15685
15686                 /* force a restore */
15687                 crtc_state->mode_changed = true;
15688         }
15689
15690         for_each_intel_plane(dev, plane) {
15691                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15692                 if (ret)
15693                         goto err;
15694         }
15695
15696         for_each_intel_connector(dev, conn) {
15697                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15698                 if (ret)
15699                         goto err;
15700         }
15701
15702         intel_modeset_setup_hw_state(dev);
15703
15704         i915_redisable_vga(dev);
15705         ret = drm_atomic_commit(state);
15706         if (!ret)
15707                 return;
15708
15709 err:
15710         DRM_ERROR("Restoring old state failed with %i\n", ret);
15711         drm_atomic_state_free(state);
15712 }
15713
15714 void intel_modeset_gem_init(struct drm_device *dev)
15715 {
15716         struct drm_crtc *c;
15717         struct drm_i915_gem_object *obj;
15718         int ret;
15719
15720         mutex_lock(&dev->struct_mutex);
15721         intel_init_gt_powersave(dev);
15722         mutex_unlock(&dev->struct_mutex);
15723
15724         intel_modeset_init_hw(dev);
15725
15726         intel_setup_overlay(dev);
15727
15728         /*
15729          * Make sure any fbs we allocated at startup are properly
15730          * pinned & fenced.  When we do the allocation it's too early
15731          * for this.
15732          */
15733         for_each_crtc(dev, c) {
15734                 obj = intel_fb_obj(c->primary->fb);
15735                 if (obj == NULL)
15736                         continue;
15737
15738                 mutex_lock(&dev->struct_mutex);
15739                 ret = intel_pin_and_fence_fb_obj(c->primary,
15740                                                  c->primary->fb,
15741                                                  c->primary->state);
15742                 mutex_unlock(&dev->struct_mutex);
15743                 if (ret) {
15744                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15745                                   to_intel_crtc(c)->pipe);
15746                         drm_framebuffer_unreference(c->primary->fb);
15747                         c->primary->fb = NULL;
15748                         c->primary->crtc = c->primary->state->crtc = NULL;
15749                         update_state_fb(c->primary);
15750                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15751                 }
15752         }
15753
15754         intel_backlight_register(dev);
15755 }
15756
15757 void intel_connector_unregister(struct intel_connector *intel_connector)
15758 {
15759         struct drm_connector *connector = &intel_connector->base;
15760
15761         intel_panel_destroy_backlight(connector);
15762         drm_connector_unregister(connector);
15763 }
15764
15765 void intel_modeset_cleanup(struct drm_device *dev)
15766 {
15767         struct drm_i915_private *dev_priv = dev->dev_private;
15768         struct drm_connector *connector;
15769
15770         intel_disable_gt_powersave(dev);
15771
15772         intel_backlight_unregister(dev);
15773
15774         /*
15775          * Interrupts and polling as the first thing to avoid creating havoc.
15776          * Too much stuff here (turning of connectors, ...) would
15777          * experience fancy races otherwise.
15778          */
15779         intel_irq_uninstall(dev_priv);
15780
15781         /*
15782          * Due to the hpd irq storm handling the hotplug work can re-arm the
15783          * poll handlers. Hence disable polling after hpd handling is shut down.
15784          */
15785         drm_kms_helper_poll_fini(dev);
15786
15787         intel_unregister_dsm_handler();
15788
15789         intel_fbc_disable(dev_priv);
15790
15791         /* flush any delayed tasks or pending work */
15792         flush_scheduled_work();
15793
15794         /* destroy the backlight and sysfs files before encoders/connectors */
15795         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15796                 struct intel_connector *intel_connector;
15797
15798                 intel_connector = to_intel_connector(connector);
15799                 intel_connector->unregister(intel_connector);
15800         }
15801
15802         drm_mode_config_cleanup(dev);
15803
15804         intel_cleanup_overlay(dev);
15805
15806         mutex_lock(&dev->struct_mutex);
15807         intel_cleanup_gt_powersave(dev);
15808         mutex_unlock(&dev->struct_mutex);
15809 }
15810
15811 /*
15812  * Return which encoder is currently attached for connector.
15813  */
15814 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15815 {
15816         return &intel_attached_encoder(connector)->base;
15817 }
15818
15819 void intel_connector_attach_encoder(struct intel_connector *connector,
15820                                     struct intel_encoder *encoder)
15821 {
15822         connector->encoder = encoder;
15823         drm_mode_connector_attach_encoder(&connector->base,
15824                                           &encoder->base);
15825 }
15826
15827 /*
15828  * set vga decode state - true == enable VGA decode
15829  */
15830 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15831 {
15832         struct drm_i915_private *dev_priv = dev->dev_private;
15833         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15834         u16 gmch_ctrl;
15835
15836         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15837                 DRM_ERROR("failed to read control word\n");
15838                 return -EIO;
15839         }
15840
15841         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15842                 return 0;
15843
15844         if (state)
15845                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15846         else
15847                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15848
15849         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15850                 DRM_ERROR("failed to write control word\n");
15851                 return -EIO;
15852         }
15853
15854         return 0;
15855 }
15856
15857 struct intel_display_error_state {
15858
15859         u32 power_well_driver;
15860
15861         int num_transcoders;
15862
15863         struct intel_cursor_error_state {
15864                 u32 control;
15865                 u32 position;
15866                 u32 base;
15867                 u32 size;
15868         } cursor[I915_MAX_PIPES];
15869
15870         struct intel_pipe_error_state {
15871                 bool power_domain_on;
15872                 u32 source;
15873                 u32 stat;
15874         } pipe[I915_MAX_PIPES];
15875
15876         struct intel_plane_error_state {
15877                 u32 control;
15878                 u32 stride;
15879                 u32 size;
15880                 u32 pos;
15881                 u32 addr;
15882                 u32 surface;
15883                 u32 tile_offset;
15884         } plane[I915_MAX_PIPES];
15885
15886         struct intel_transcoder_error_state {
15887                 bool power_domain_on;
15888                 enum transcoder cpu_transcoder;
15889
15890                 u32 conf;
15891
15892                 u32 htotal;
15893                 u32 hblank;
15894                 u32 hsync;
15895                 u32 vtotal;
15896                 u32 vblank;
15897                 u32 vsync;
15898         } transcoder[4];
15899 };
15900
15901 struct intel_display_error_state *
15902 intel_display_capture_error_state(struct drm_device *dev)
15903 {
15904         struct drm_i915_private *dev_priv = dev->dev_private;
15905         struct intel_display_error_state *error;
15906         int transcoders[] = {
15907                 TRANSCODER_A,
15908                 TRANSCODER_B,
15909                 TRANSCODER_C,
15910                 TRANSCODER_EDP,
15911         };
15912         int i;
15913
15914         if (INTEL_INFO(dev)->num_pipes == 0)
15915                 return NULL;
15916
15917         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15918         if (error == NULL)
15919                 return NULL;
15920
15921         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15922                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15923
15924         for_each_pipe(dev_priv, i) {
15925                 error->pipe[i].power_domain_on =
15926                         __intel_display_power_is_enabled(dev_priv,
15927                                                          POWER_DOMAIN_PIPE(i));
15928                 if (!error->pipe[i].power_domain_on)
15929                         continue;
15930
15931                 error->cursor[i].control = I915_READ(CURCNTR(i));
15932                 error->cursor[i].position = I915_READ(CURPOS(i));
15933                 error->cursor[i].base = I915_READ(CURBASE(i));
15934
15935                 error->plane[i].control = I915_READ(DSPCNTR(i));
15936                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15937                 if (INTEL_INFO(dev)->gen <= 3) {
15938                         error->plane[i].size = I915_READ(DSPSIZE(i));
15939                         error->plane[i].pos = I915_READ(DSPPOS(i));
15940                 }
15941                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15942                         error->plane[i].addr = I915_READ(DSPADDR(i));
15943                 if (INTEL_INFO(dev)->gen >= 4) {
15944                         error->plane[i].surface = I915_READ(DSPSURF(i));
15945                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15946                 }
15947
15948                 error->pipe[i].source = I915_READ(PIPESRC(i));
15949
15950                 if (HAS_GMCH_DISPLAY(dev))
15951                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15952         }
15953
15954         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15955         if (HAS_DDI(dev_priv->dev))
15956                 error->num_transcoders++; /* Account for eDP. */
15957
15958         for (i = 0; i < error->num_transcoders; i++) {
15959                 enum transcoder cpu_transcoder = transcoders[i];
15960
15961                 error->transcoder[i].power_domain_on =
15962                         __intel_display_power_is_enabled(dev_priv,
15963                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15964                 if (!error->transcoder[i].power_domain_on)
15965                         continue;
15966
15967                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15968
15969                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15970                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15971                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15972                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15973                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15974                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15975                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15976         }
15977
15978         return error;
15979 }
15980
15981 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15982
15983 void
15984 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15985                                 struct drm_device *dev,
15986                                 struct intel_display_error_state *error)
15987 {
15988         struct drm_i915_private *dev_priv = dev->dev_private;
15989         int i;
15990
15991         if (!error)
15992                 return;
15993
15994         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15995         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15996                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15997                            error->power_well_driver);
15998         for_each_pipe(dev_priv, i) {
15999                 err_printf(m, "Pipe [%d]:\n", i);
16000                 err_printf(m, "  Power: %s\n",
16001                            error->pipe[i].power_domain_on ? "on" : "off");
16002                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16003                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16004
16005                 err_printf(m, "Plane [%d]:\n", i);
16006                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16007                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16008                 if (INTEL_INFO(dev)->gen <= 3) {
16009                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16010                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16011                 }
16012                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16013                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16014                 if (INTEL_INFO(dev)->gen >= 4) {
16015                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16016                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16017                 }
16018
16019                 err_printf(m, "Cursor [%d]:\n", i);
16020                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16021                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16022                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16023         }
16024
16025         for (i = 0; i < error->num_transcoders; i++) {
16026                 err_printf(m, "CPU transcoder: %c\n",
16027                            transcoder_name(error->transcoder[i].cpu_transcoder));
16028                 err_printf(m, "  Power: %s\n",
16029                            error->transcoder[i].power_domain_on ? "on" : "off");
16030                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16031                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16032                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16033                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16034                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16035                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16036                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16037         }
16038 }
16039
16040 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
16041 {
16042         struct intel_crtc *crtc;
16043
16044         for_each_intel_crtc(dev, crtc) {
16045                 struct intel_unpin_work *work;
16046
16047                 spin_lock_irq(&dev->event_lock);
16048
16049                 work = crtc->unpin_work;
16050
16051                 if (work && work->event &&
16052                     work->event->base.file_priv == file) {
16053                         kfree(work->event);
16054                         work->event = NULL;
16055                 }
16056
16057                 spin_unlock_irq(&dev->event_lock);
16058         }
16059 }