drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54
  55
  56 typedef struct {
  57         int     min, max;
  58 } intel_range_t;
  59
  60 typedef struct {
  61         int     dot_limit;
  62         int     p2_slow, p2_fast;
  63 } intel_p2_t;
  64
  65 typedef struct intel_limit intel_limit_t;
  66 struct intel_limit {
  67         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  68         intel_p2_t          p2;
  69 };
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 930000, .max = 1400000 },
  94         .n = { .min = 3, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 930000, .max = 1400000 },
 107         .n = { .min = 3, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 930000, .max = 1400000 },
 120         .n = { .min = 3, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv = {
 313          /*
 314           * These are the data rate limits (measured in fast clocks)
 315           * since those are the strictest limits we have. The fast
 316           * clock and actual rate limits are more relaxed, so checking
 317           * them would make no difference.
 318           */
 319         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 320         .vco = { .min = 4000000, .max = 6000000 },
 321         .n = { .min = 1, .max = 7 },
 322         .m1 = { .min = 2, .max = 3 },
 323         .m2 = { .min = 11, .max = 156 },
 324         .p1 = { .min = 2, .max = 3 },
 325         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 326 };
 327
 328 static void vlv_clock(int refclk, intel_clock_t *clock)
 329 {
 330         clock->m = clock->m1 * clock->m2;
 331         clock->p = clock->p1 * clock->p2;
 332         clock->vco = refclk * clock->m / clock->n;
 333         clock->dot = clock->vco / clock->p;
 334 }
 335
 336 /**
 337  * Returns whether any output on the specified pipe is of the specified type
 338  */
 339 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 340 {
 341         struct drm_device *dev = crtc->dev;
 342         struct intel_encoder *encoder;
 343
 344         for_each_encoder_on_crtc(dev, crtc, encoder)
 345                 if (encoder->type == type)
 346                         return true;
 347
 348         return false;
 349 }
 350
 351 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 352                                                 int refclk)
 353 {
 354         struct drm_device *dev = crtc->dev;
 355         const intel_limit_t *limit;
 356
 357         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 358                 if (intel_is_dual_link_lvds(dev)) {
 359                         if (refclk == 100000)
 360                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 361                         else
 362                                 limit = &intel_limits_ironlake_dual_lvds;
 363                 } else {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_single_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_single_lvds;
 368                 }
 369         } else
 370                 limit = &intel_limits_ironlake_dac;
 371
 372         return limit;
 373 }
 374
 375 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 376 {
 377         struct drm_device *dev = crtc->dev;
 378         const intel_limit_t *limit;
 379
 380         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 381                 if (intel_is_dual_link_lvds(dev))
 382                         limit = &intel_limits_g4x_dual_channel_lvds;
 383                 else
 384                         limit = &intel_limits_g4x_single_channel_lvds;
 385         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 386                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 387                 limit = &intel_limits_g4x_hdmi;
 388         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 389                 limit = &intel_limits_g4x_sdvo;
 390         } else /* The option is for other outputs */
 391                 limit = &intel_limits_i9xx_sdvo;
 392
 393         return limit;
 394 }
 395
 396 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 397 {
 398         struct drm_device *dev = crtc->dev;
 399         const intel_limit_t *limit;
 400
 401         if (HAS_PCH_SPLIT(dev))
 402                 limit = intel_ironlake_limit(crtc, refclk);
 403         else if (IS_G4X(dev)) {
 404                 limit = intel_g4x_limit(crtc);
 405         } else if (IS_PINEVIEW(dev)) {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_pineview_lvds;
 408                 else
 409                         limit = &intel_limits_pineview_sdvo;
 410         } else if (IS_VALLEYVIEW(dev)) {
 411                 limit = &intel_limits_vlv;
 412         } else if (!IS_GEN2(dev)) {
 413                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 414                         limit = &intel_limits_i9xx_lvds;
 415                 else
 416                         limit = &intel_limits_i9xx_sdvo;
 417         } else {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i8xx_lvds;
 420                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 421                         limit = &intel_limits_i8xx_dvo;
 422                 else
 423                         limit = &intel_limits_i8xx_dac;
 424         }
 425         return limit;
 426 }
 427
 428 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 429 static void pineview_clock(int refclk, intel_clock_t *clock)
 430 {
 431         clock->m = clock->m2 + 2;
 432         clock->p = clock->p1 * clock->p2;
 433         clock->vco = refclk * clock->m / clock->n;
 434         clock->dot = clock->vco / clock->p;
 435 }
 436
 437 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 438 {
 439         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 440 }
 441
 442 static void i9xx_clock(int refclk, intel_clock_t *clock)
 443 {
 444         clock->m = i9xx_dpll_compute_m(clock);
 445         clock->p = clock->p1 * clock->p2;
 446         clock->vco = refclk * clock->m / (clock->n + 2);
 447         clock->dot = clock->vco / clock->p;
 448 }
 449
 450 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 451 /**
 452  * Returns whether the given set of divisors are valid for a given refclk with
 453  * the given connectors.
 454  */
 455
 456 static bool intel_PLL_is_valid(struct drm_device *dev,
 457                                const intel_limit_t *limit,
 458                                const intel_clock_t *clock)
 459 {
 460         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 461                 INTELPllInvalid("n out of range\n");
 462         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 463                 INTELPllInvalid("p1 out of range\n");
 464         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 465                 INTELPllInvalid("m2 out of range\n");
 466         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 467                 INTELPllInvalid("m1 out of range\n");
 468
 469         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 470                 if (clock->m1 <= clock->m2)
 471                         INTELPllInvalid("m1 <= m2\n");
 472
 473         if (!IS_VALLEYVIEW(dev)) {
 474                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 475                         INTELPllInvalid("p out of range\n");
 476                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 477                         INTELPllInvalid("m out of range\n");
 478         }
 479
 480         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 481                 INTELPllInvalid("vco out of range\n");
 482         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 483          * connector, etc., rather than just a single range.
 484          */
 485         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 486                 INTELPllInvalid("dot out of range\n");
 487
 488         return true;
 489 }
 490
 491 static bool
 492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 493                     int target, int refclk, intel_clock_t *match_clock,
 494                     intel_clock_t *best_clock)
 495 {
 496         struct drm_device *dev = crtc->dev;
 497         intel_clock_t clock;
 498         int err = target;
 499
 500         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 501                 /*
 502                  * For LVDS just rely on its current settings for dual-channel.
 503                  * We haven't figured out how to reliably set up different
 504                  * single/dual channel state, if we even can.
 505                  */
 506                 if (intel_is_dual_link_lvds(dev))
 507                         clock.p2 = limit->p2.p2_fast;
 508                 else
 509                         clock.p2 = limit->p2.p2_slow;
 510         } else {
 511                 if (target < limit->p2.dot_limit)
 512                         clock.p2 = limit->p2.p2_slow;
 513                 else
 514                         clock.p2 = limit->p2.p2_fast;
 515         }
 516
 517         memset(best_clock, 0, sizeof(*best_clock));
 518
 519         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 520              clock.m1++) {
 521                 for (clock.m2 = limit->m2.min;
 522                      clock.m2 <= limit->m2.max; clock.m2++) {
 523                         if (clock.m2 >= clock.m1)
 524                                 break;
 525                         for (clock.n = limit->n.min;
 526                              clock.n <= limit->n.max; clock.n++) {
 527                                 for (clock.p1 = limit->p1.min;
 528                                         clock.p1 <= limit->p1.max; clock.p1++) {
 529                                         int this_err;
 530
 531                                         i9xx_clock(refclk, &clock);
 532                                         if (!intel_PLL_is_valid(dev, limit,
 533                                                                 &clock))
 534                                                 continue;
 535                                         if (match_clock &&
 536                                             clock.p != match_clock->p)
 537                                                 continue;
 538
 539                                         this_err = abs(clock.dot - target);
 540                                         if (this_err < err) {
 541                                                 *best_clock = clock;
 542                                                 err = this_err;
 543                                         }
 544                                 }
 545                         }
 546                 }
 547         }
 548
 549         return (err != target);
 550 }
 551
 552 static bool
 553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 554                    int target, int refclk, intel_clock_t *match_clock,
 555                    intel_clock_t *best_clock)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         intel_clock_t clock;
 559         int err = target;
 560
 561         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 562                 /*
 563                  * For LVDS just rely on its current settings for dual-channel.
 564                  * We haven't figured out how to reliably set up different
 565                  * single/dual channel state, if we even can.
 566                  */
 567                 if (intel_is_dual_link_lvds(dev))
 568                         clock.p2 = limit->p2.p2_fast;
 569                 else
 570                         clock.p2 = limit->p2.p2_slow;
 571         } else {
 572                 if (target < limit->p2.dot_limit)
 573                         clock.p2 = limit->p2.p2_slow;
 574                 else
 575                         clock.p2 = limit->p2.p2_fast;
 576         }
 577
 578         memset(best_clock, 0, sizeof(*best_clock));
 579
 580         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 581              clock.m1++) {
 582                 for (clock.m2 = limit->m2.min;
 583                      clock.m2 <= limit->m2.max; clock.m2++) {
 584                         for (clock.n = limit->n.min;
 585                              clock.n <= limit->n.max; clock.n++) {
 586                                 for (clock.p1 = limit->p1.min;
 587                                         clock.p1 <= limit->p1.max; clock.p1++) {
 588                                         int this_err;
 589
 590                                         pineview_clock(refclk, &clock);
 591                                         if (!intel_PLL_is_valid(dev, limit,
 592                                                                 &clock))
 593                                                 continue;
 594                                         if (match_clock &&
 595                                             clock.p != match_clock->p)
 596                                                 continue;
 597
 598                                         this_err = abs(clock.dot - target);
 599                                         if (this_err < err) {
 600                                                 *best_clock = clock;
 601                                                 err = this_err;
 602                                         }
 603                                 }
 604                         }
 605                 }
 606         }
 607
 608         return (err != target);
 609 }
 610
 611 static bool
 612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 613                    int target, int refclk, intel_clock_t *match_clock,
 614                    intel_clock_t *best_clock)
 615 {
 616         struct drm_device *dev = crtc->dev;
 617         intel_clock_t clock;
 618         int max_n;
 619         bool found;
 620         /* approximately equals target * 0.00585 */
 621         int err_most = (target >> 8) + (target >> 9);
 622         found = false;
 623
 624         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 625                 if (intel_is_dual_link_lvds(dev))
 626                         clock.p2 = limit->p2.p2_fast;
 627                 else
 628                         clock.p2 = limit->p2.p2_slow;
 629         } else {
 630                 if (target < limit->p2.dot_limit)
 631                         clock.p2 = limit->p2.p2_slow;
 632                 else
 633                         clock.p2 = limit->p2.p2_fast;
 634         }
 635
 636         memset(best_clock, 0, sizeof(*best_clock));
 637         max_n = limit->n.max;
 638         /* based on hardware requirement, prefer smaller n to precision */
 639         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 640                 /* based on hardware requirement, prefere larger m1,m2 */
 641                 for (clock.m1 = limit->m1.max;
 642                      clock.m1 >= limit->m1.min; clock.m1--) {
 643                         for (clock.m2 = limit->m2.max;
 644                              clock.m2 >= limit->m2.min; clock.m2--) {
 645                                 for (clock.p1 = limit->p1.max;
 646                                      clock.p1 >= limit->p1.min; clock.p1--) {
 647                                         int this_err;
 648
 649                                         i9xx_clock(refclk, &clock);
 650                                         if (!intel_PLL_is_valid(dev, limit,
 651                                                                 &clock))
 652                                                 continue;
 653
 654                                         this_err = abs(clock.dot - target);
 655                                         if (this_err < err_most) {
 656                                                 *best_clock = clock;
 657                                                 err_most = this_err;
 658                                                 max_n = clock.n;
 659                                                 found = true;
 660                                         }
 661                                 }
 662                         }
 663                 }
 664         }
 665         return found;
 666 }
 667
 668 static bool
 669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                    int target, int refclk, intel_clock_t *match_clock,
 671                    intel_clock_t *best_clock)
 672 {
 673         struct drm_device *dev = crtc->dev;
 674         intel_clock_t clock;
 675         unsigned int bestppm = 1000000;
 676         /* min update 19.2 MHz */
 677         int max_n = min(limit->n.max, refclk / 19200);
 678         bool found = false;
 679
 680         target *= 5; /* fast clock */
 681
 682         memset(best_clock, 0, sizeof(*best_clock));
 683
 684         /* based on hardware requirement, prefer smaller n to precision */
 685         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 686                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 687                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 688                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 689                                 clock.p = clock.p1 * clock.p2;
 690                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 691                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 692                                         unsigned int ppm, diff;
 693
 694                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 695                                                                      refclk * clock.m1);
 696
 697                                         vlv_clock(refclk, &clock);
 698
 699                                         if (!intel_PLL_is_valid(dev, limit,
 700                                                                 &clock))
 701                                                 continue;
 702
 703                                         diff = abs(clock.dot - target);
 704                                         ppm = div_u64(1000000ULL * diff, target);
 705
 706                                         if (ppm < 100 && clock.p > best_clock->p) {
 707                                                 bestppm = 0;
 708                                                 *best_clock = clock;
 709                                                 found = true;
 710                                         }
 711
 712                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 713                                                 bestppm = ppm;
 714                                                 *best_clock = clock;
 715                                                 found = true;
 716                                         }
 717                                 }
 718                         }
 719                 }
 720         }
 721
 722         return found;
 723 }
 724
 725 bool intel_crtc_active(struct drm_crtc *crtc)
 726 {
 727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 728
 729         /* Be paranoid as we can arrive here with only partial
 730          * state retrieved from the hardware during setup.
 731          *
 732          * We can ditch the adjusted_mode.crtc_clock check as soon
 733          * as Haswell has gained clock readout/fastboot support.
 734          *
 735          * We can ditch the crtc->fb check as soon as we can
 736          * properly reconstruct framebuffers.
 737          */
 738         return intel_crtc->active && crtc->fb &&
 739                 intel_crtc->config.adjusted_mode.crtc_clock;
 740 }
 741
 742 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 743                                              enum pipe pipe)
 744 {
 745         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 747
 748         return intel_crtc->config.cpu_transcoder;
 749 }
 750
 751 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 752 {
 753         struct drm_i915_private *dev_priv = dev->dev_private;
 754         u32 frame, frame_reg = PIPEFRAME(pipe);
 755
 756         frame = I915_READ(frame_reg);
 757
 758         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 759                 DRM_DEBUG_KMS("vblank wait timed out\n");
 760 }
 761
 762 /**
 763  * intel_wait_for_vblank - wait for vblank on a given pipe
 764  * @dev: drm device
 765  * @pipe: pipe to wait for
 766  *
 767  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 768  * mode setting code.
 769  */
 770 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 771 {
 772         struct drm_i915_private *dev_priv = dev->dev_private;
 773         int pipestat_reg = PIPESTAT(pipe);
 774
 775         if (INTEL_INFO(dev)->gen >= 5) {
 776                 ironlake_wait_for_vblank(dev, pipe);
 777                 return;
 778         }
 779
 780         /* Clear existing vblank status. Note this will clear any other
 781          * sticky status fields as well.
 782          *
 783          * This races with i915_driver_irq_handler() with the result
 784          * that either function could miss a vblank event.  Here it is not
 785          * fatal, as we will either wait upon the next vblank interrupt or
 786          * timeout.  Generally speaking intel_wait_for_vblank() is only
 787          * called during modeset at which time the GPU should be idle and
 788          * should *not* be performing page flips and thus not waiting on
 789          * vblanks...
 790          * Currently, the result of us stealing a vblank from the irq
 791          * handler is that a single frame will be skipped during swapbuffers.
 792          */
 793         I915_WRITE(pipestat_reg,
 794                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 795
 796         /* Wait for vblank interrupt bit to set */
 797         if (wait_for(I915_READ(pipestat_reg) &
 798                      PIPE_VBLANK_INTERRUPT_STATUS,
 799                      50))
 800                 DRM_DEBUG_KMS("vblank wait timed out\n");
 801 }
 802
 803 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 804 {
 805         struct drm_i915_private *dev_priv = dev->dev_private;
 806         u32 reg = PIPEDSL(pipe);
 807         u32 line1, line2;
 808         u32 line_mask;
 809
 810         if (IS_GEN2(dev))
 811                 line_mask = DSL_LINEMASK_GEN2;
 812         else
 813                 line_mask = DSL_LINEMASK_GEN3;
 814
 815         line1 = I915_READ(reg) & line_mask;
 816         mdelay(5);
 817         line2 = I915_READ(reg) & line_mask;
 818
 819         return line1 == line2;
 820 }
 821
 822 /*
 823  * intel_wait_for_pipe_off - wait for pipe to turn off
 824  * @dev: drm device
 825  * @pipe: pipe to wait for
 826  *
 827  * After disabling a pipe, we can't wait for vblank in the usual way,
 828  * spinning on the vblank interrupt status bit, since we won't actually
 829  * see an interrupt when the pipe is disabled.
 830  *
 831  * On Gen4 and above:
 832  *   wait for the pipe register state bit to turn off
 833  *
 834  * Otherwise:
 835  *   wait for the display line value to settle (it usually
 836  *   ends up stopping at the start of the next frame).
 837  *
 838  */
 839 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 840 {
 841         struct drm_i915_private *dev_priv = dev->dev_private;
 842         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 843                                                                       pipe);
 844
 845         if (INTEL_INFO(dev)->gen >= 4) {
 846                 int reg = PIPECONF(cpu_transcoder);
 847
 848                 /* Wait for the Pipe State to go off */
 849                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 850                              100))
 851                         WARN(1, "pipe_off wait timed out\n");
 852         } else {
 853                 /* Wait for the display line to settle */
 854                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 855                         WARN(1, "pipe_off wait timed out\n");
 856         }
 857 }
 858
 859 /*
 860  * ibx_digital_port_connected - is the specified port connected?
 861  * @dev_priv: i915 private structure
 862  * @port: the port to test
 863  *
 864  * Returns true if @port is connected, false otherwise.
 865  */
 866 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 867                                 struct intel_digital_port *port)
 868 {
 869         u32 bit;
 870
 871         if (HAS_PCH_IBX(dev_priv->dev)) {
 872                 switch(port->port) {
 873                 case PORT_B:
 874                         bit = SDE_PORTB_HOTPLUG;
 875                         break;
 876                 case PORT_C:
 877                         bit = SDE_PORTC_HOTPLUG;
 878                         break;
 879                 case PORT_D:
 880                         bit = SDE_PORTD_HOTPLUG;
 881                         break;
 882                 default:
 883                         return true;
 884                 }
 885         } else {
 886                 switch(port->port) {
 887                 case PORT_B:
 888                         bit = SDE_PORTB_HOTPLUG_CPT;
 889                         break;
 890                 case PORT_C:
 891                         bit = SDE_PORTC_HOTPLUG_CPT;
 892                         break;
 893                 case PORT_D:
 894                         bit = SDE_PORTD_HOTPLUG_CPT;
 895                         break;
 896                 default:
 897                         return true;
 898                 }
 899         }
 900
 901         return I915_READ(SDEISR) & bit;
 902 }
 903
 904 static const char *state_string(bool enabled)
 905 {
 906         return enabled ? "on" : "off";
 907 }
 908
 909 /* Only for pre-ILK configs */
 910 void assert_pll(struct drm_i915_private *dev_priv,
 911                 enum pipe pipe, bool state)
 912 {
 913         int reg;
 914         u32 val;
 915         bool cur_state;
 916
 917         reg = DPLL(pipe);
 918         val = I915_READ(reg);
 919         cur_state = !!(val & DPLL_VCO_ENABLE);
 920         WARN(cur_state != state,
 921              "PLL state assertion failure (expected %s, current %s)\n",
 922              state_string(state), state_string(cur_state));
 923 }
 924
 925 /* XXX: the dsi pll is shared between MIPI DSI ports */
 926 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 927 {
 928         u32 val;
 929         bool cur_state;
 930
 931         mutex_lock(&dev_priv->dpio_lock);
 932         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 933         mutex_unlock(&dev_priv->dpio_lock);
 934
 935         cur_state = val & DSI_PLL_VCO_EN;
 936         WARN(cur_state != state,
 937              "DSI PLL state assertion failure (expected %s, current %s)\n",
 938              state_string(state), state_string(cur_state));
 939 }
 940 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 941 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 942
 943 struct intel_shared_dpll *
 944 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 945 {
 946         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 947
 948         if (crtc->config.shared_dpll < 0)
 949                 return NULL;
 950
 951         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 952 }
 953
 954 /* For ILK+ */
 955 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 956                         struct intel_shared_dpll *pll,
 957                         bool state)
 958 {
 959         bool cur_state;
 960         struct intel_dpll_hw_state hw_state;
 961
 962         if (HAS_PCH_LPT(dev_priv->dev)) {
 963                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 964                 return;
 965         }
 966
 967         if (WARN (!pll,
 968                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 969                 return;
 970
 971         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 972         WARN(cur_state != state,
 973              "%s assertion failure (expected %s, current %s)\n",
 974              pll->name, state_string(state), state_string(cur_state));
 975 }
 976
 977 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 978                           enum pipe pipe, bool state)
 979 {
 980         int reg;
 981         u32 val;
 982         bool cur_state;
 983         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 984                                                                       pipe);
 985
 986         if (HAS_DDI(dev_priv->dev)) {
 987                 /* DDI does not have a specific FDI_TX register */
 988                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 989                 val = I915_READ(reg);
 990                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 991         } else {
 992                 reg = FDI_TX_CTL(pipe);
 993                 val = I915_READ(reg);
 994                 cur_state = !!(val & FDI_TX_ENABLE);
 995         }
 996         WARN(cur_state != state,
 997              "FDI TX state assertion failure (expected %s, current %s)\n",
 998              state_string(state), state_string(cur_state));
 999 }
1000 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1001 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1002
1003 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1004                           enum pipe pipe, bool state)
1005 {
1006         int reg;
1007         u32 val;
1008         bool cur_state;
1009
1010         reg = FDI_RX_CTL(pipe);
1011         val = I915_READ(reg);
1012         cur_state = !!(val & FDI_RX_ENABLE);
1013         WARN(cur_state != state,
1014              "FDI RX state assertion failure (expected %s, current %s)\n",
1015              state_string(state), state_string(cur_state));
1016 }
1017 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1018 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1019
1020 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1021                                       enum pipe pipe)
1022 {
1023         int reg;
1024         u32 val;
1025
1026         /* ILK FDI PLL is always enabled */
1027         if (dev_priv->info->gen == 5)
1028                 return;
1029
1030         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1031         if (HAS_DDI(dev_priv->dev))
1032                 return;
1033
1034         reg = FDI_TX_CTL(pipe);
1035         val = I915_READ(reg);
1036         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1037 }
1038
1039 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1040                        enum pipe pipe, bool state)
1041 {
1042         int reg;
1043         u32 val;
1044         bool cur_state;
1045
1046         reg = FDI_RX_CTL(pipe);
1047         val = I915_READ(reg);
1048         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1049         WARN(cur_state != state,
1050              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1051              state_string(state), state_string(cur_state));
1052 }
1053
1054 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1055                                   enum pipe pipe)
1056 {
1057         int pp_reg, lvds_reg;
1058         u32 val;
1059         enum pipe panel_pipe = PIPE_A;
1060         bool locked = true;
1061
1062         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1063                 pp_reg = PCH_PP_CONTROL;
1064                 lvds_reg = PCH_LVDS;
1065         } else {
1066                 pp_reg = PP_CONTROL;
1067                 lvds_reg = LVDS;
1068         }
1069
1070         val = I915_READ(pp_reg);
1071         if (!(val & PANEL_POWER_ON) ||
1072             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1073                 locked = false;
1074
1075         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1076                 panel_pipe = PIPE_B;
1077
1078         WARN(panel_pipe == pipe && locked,
1079              "panel assertion failure, pipe %c regs locked\n",
1080              pipe_name(pipe));
1081 }
1082
1083 static void assert_cursor(struct drm_i915_private *dev_priv,
1084                           enum pipe pipe, bool state)
1085 {
1086         struct drm_device *dev = dev_priv->dev;
1087         bool cur_state;
1088
1089         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1090                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1091         else if (IS_845G(dev) || IS_I865G(dev))
1092                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1093         else
1094                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1095
1096         WARN(cur_state != state,
1097              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1098              pipe_name(pipe), state_string(state), state_string(cur_state));
1099 }
1100 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1101 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1102
1103 void assert_pipe(struct drm_i915_private *dev_priv,
1104                  enum pipe pipe, bool state)
1105 {
1106         int reg;
1107         u32 val;
1108         bool cur_state;
1109         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1110                                                                       pipe);
1111
1112         /* if we need the pipe A quirk it must be always on */
1113         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1114                 state = true;
1115
1116         if (!intel_display_power_enabled(dev_priv->dev,
1117                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1118                 cur_state = false;
1119         } else {
1120                 reg = PIPECONF(cpu_transcoder);
1121                 val = I915_READ(reg);
1122                 cur_state = !!(val & PIPECONF_ENABLE);
1123         }
1124
1125         WARN(cur_state != state,
1126              "pipe %c assertion failure (expected %s, current %s)\n",
1127              pipe_name(pipe), state_string(state), state_string(cur_state));
1128 }
1129
1130 static void assert_plane(struct drm_i915_private *dev_priv,
1131                          enum plane plane, bool state)
1132 {
1133         int reg;
1134         u32 val;
1135         bool cur_state;
1136
1137         reg = DSPCNTR(plane);
1138         val = I915_READ(reg);
1139         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1140         WARN(cur_state != state,
1141              "plane %c assertion failure (expected %s, current %s)\n",
1142              plane_name(plane), state_string(state), state_string(cur_state));
1143 }
1144
1145 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1146 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1147
1148 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1149                                    enum pipe pipe)
1150 {
1151         struct drm_device *dev = dev_priv->dev;
1152         int reg, i;
1153         u32 val;
1154         int cur_pipe;
1155
1156         /* Primary planes are fixed to pipes on gen4+ */
1157         if (INTEL_INFO(dev)->gen >= 4) {
1158                 reg = DSPCNTR(pipe);
1159                 val = I915_READ(reg);
1160                 WARN((val & DISPLAY_PLANE_ENABLE),
1161                      "plane %c assertion failure, should be disabled but not\n",
1162                      plane_name(pipe));
1163                 return;
1164         }
1165
1166         /* Need to check both planes against the pipe */
1167         for_each_pipe(i) {
1168                 reg = DSPCNTR(i);
1169                 val = I915_READ(reg);
1170                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1171                         DISPPLANE_SEL_PIPE_SHIFT;
1172                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1173                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1174                      plane_name(i), pipe_name(pipe));
1175         }
1176 }
1177
1178 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1179                                     enum pipe pipe)
1180 {
1181         struct drm_device *dev = dev_priv->dev;
1182         int reg, i;
1183         u32 val;
1184
1185         if (IS_VALLEYVIEW(dev)) {
1186                 for (i = 0; i < dev_priv->num_plane; i++) {
1187                         reg = SPCNTR(pipe, i);
1188                         val = I915_READ(reg);
1189                         WARN((val & SP_ENABLE),
1190                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1191                              sprite_name(pipe, i), pipe_name(pipe));
1192                 }
1193         } else if (INTEL_INFO(dev)->gen >= 7) {
1194                 reg = SPRCTL(pipe);
1195                 val = I915_READ(reg);
1196                 WARN((val & SPRITE_ENABLE),
1197                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1198                      plane_name(pipe), pipe_name(pipe));
1199         } else if (INTEL_INFO(dev)->gen >= 5) {
1200                 reg = DVSCNTR(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & DVS_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         }
1206 }
1207
1208 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1209 {
1210         u32 val;
1211         bool enabled;
1212
1213         if (HAS_PCH_LPT(dev_priv->dev)) {
1214                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1215                 return;
1216         }
1217
1218         val = I915_READ(PCH_DREF_CONTROL);
1219         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1220                             DREF_SUPERSPREAD_SOURCE_MASK));
1221         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1222 }
1223
1224 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1225                                            enum pipe pipe)
1226 {
1227         int reg;
1228         u32 val;
1229         bool enabled;
1230
1231         reg = PCH_TRANSCONF(pipe);
1232         val = I915_READ(reg);
1233         enabled = !!(val & TRANS_ENABLE);
1234         WARN(enabled,
1235              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1236              pipe_name(pipe));
1237 }
1238
1239 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1240                             enum pipe pipe, u32 port_sel, u32 val)
1241 {
1242         if ((val & DP_PORT_EN) == 0)
1243                 return false;
1244
1245         if (HAS_PCH_CPT(dev_priv->dev)) {
1246                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1247                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1248                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1249                         return false;
1250         } else {
1251                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1252                         return false;
1253         }
1254         return true;
1255 }
1256
1257 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1258                               enum pipe pipe, u32 val)
1259 {
1260         if ((val & SDVO_ENABLE) == 0)
1261                 return false;
1262
1263         if (HAS_PCH_CPT(dev_priv->dev)) {
1264                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1265                         return false;
1266         } else {
1267                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1268                         return false;
1269         }
1270         return true;
1271 }
1272
1273 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1274                               enum pipe pipe, u32 val)
1275 {
1276         if ((val & LVDS_PORT_EN) == 0)
1277                 return false;
1278
1279         if (HAS_PCH_CPT(dev_priv->dev)) {
1280                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281                         return false;
1282         } else {
1283                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1284                         return false;
1285         }
1286         return true;
1287 }
1288
1289 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1290                               enum pipe pipe, u32 val)
1291 {
1292         if ((val & ADPA_DAC_ENABLE) == 0)
1293                 return false;
1294         if (HAS_PCH_CPT(dev_priv->dev)) {
1295                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1296                         return false;
1297         } else {
1298                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1299                         return false;
1300         }
1301         return true;
1302 }
1303
1304 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1305                                    enum pipe pipe, int reg, u32 port_sel)
1306 {
1307         u32 val = I915_READ(reg);
1308         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1309              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1310              reg, pipe_name(pipe));
1311
1312         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1313              && (val & DP_PIPEB_SELECT),
1314              "IBX PCH dp port still using transcoder B\n");
1315 }
1316
1317 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1318                                      enum pipe pipe, int reg)
1319 {
1320         u32 val = I915_READ(reg);
1321         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1322              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1323              reg, pipe_name(pipe));
1324
1325         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1326              && (val & SDVO_PIPE_B_SELECT),
1327              "IBX PCH hdmi port still using transcoder B\n");
1328 }
1329
1330 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1331                                       enum pipe pipe)
1332 {
1333         int reg;
1334         u32 val;
1335
1336         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1337         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1338         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1339
1340         reg = PCH_ADPA;
1341         val = I915_READ(reg);
1342         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1343              "PCH VGA enabled on transcoder %c, should be disabled\n",
1344              pipe_name(pipe));
1345
1346         reg = PCH_LVDS;
1347         val = I915_READ(reg);
1348         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1349              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1353         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1354         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1355 }
1356
1357 static void intel_init_dpio(struct drm_device *dev)
1358 {
1359         struct drm_i915_private *dev_priv = dev->dev_private;
1360
1361         if (!IS_VALLEYVIEW(dev))
1362                 return;
1363
1364         /*
1365          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1366          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1367          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1368          *   b. The other bits such as sfr settings / modesel may all be set
1369          *      to 0.
1370          *
1371          * This should only be done on init and resume from S3 with both
1372          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1373          */
1374         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1375 }
1376
1377 static void vlv_enable_pll(struct intel_crtc *crtc)
1378 {
1379         struct drm_device *dev = crtc->base.dev;
1380         struct drm_i915_private *dev_priv = dev->dev_private;
1381         int reg = DPLL(crtc->pipe);
1382         u32 dpll = crtc->config.dpll_hw_state.dpll;
1383
1384         assert_pipe_disabled(dev_priv, crtc->pipe);
1385
1386         /* No really, not for ILK+ */
1387         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1388
1389         /* PLL is protected by panel, make sure we can write it */
1390         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1391                 assert_panel_unlocked(dev_priv, crtc->pipe);
1392
1393         I915_WRITE(reg, dpll);
1394         POSTING_READ(reg);
1395         udelay(150);
1396
1397         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1398                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1399
1400         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1401         POSTING_READ(DPLL_MD(crtc->pipe));
1402
1403         /* We do this three times for luck */
1404         I915_WRITE(reg, dpll);
1405         POSTING_READ(reg);
1406         udelay(150); /* wait for warmup */
1407         I915_WRITE(reg, dpll);
1408         POSTING_READ(reg);
1409         udelay(150); /* wait for warmup */
1410         I915_WRITE(reg, dpll);
1411         POSTING_READ(reg);
1412         udelay(150); /* wait for warmup */
1413 }
1414
1415 static void i9xx_enable_pll(struct intel_crtc *crtc)
1416 {
1417         struct drm_device *dev = crtc->base.dev;
1418         struct drm_i915_private *dev_priv = dev->dev_private;
1419         int reg = DPLL(crtc->pipe);
1420         u32 dpll = crtc->config.dpll_hw_state.dpll;
1421
1422         assert_pipe_disabled(dev_priv, crtc->pipe);
1423
1424         /* No really, not for ILK+ */
1425         BUG_ON(dev_priv->info->gen >= 5);
1426
1427         /* PLL is protected by panel, make sure we can write it */
1428         if (IS_MOBILE(dev) && !IS_I830(dev))
1429                 assert_panel_unlocked(dev_priv, crtc->pipe);
1430
1431         I915_WRITE(reg, dpll);
1432
1433         /* Wait for the clocks to stabilize. */
1434         POSTING_READ(reg);
1435         udelay(150);
1436
1437         if (INTEL_INFO(dev)->gen >= 4) {
1438                 I915_WRITE(DPLL_MD(crtc->pipe),
1439                            crtc->config.dpll_hw_state.dpll_md);
1440         } else {
1441                 /* The pixel multiplier can only be updated once the
1442                  * DPLL is enabled and the clocks are stable.
1443                  *
1444                  * So write it again.
1445                  */
1446                 I915_WRITE(reg, dpll);
1447         }
1448
1449         /* We do this three times for luck */
1450         I915_WRITE(reg, dpll);
1451         POSTING_READ(reg);
1452         udelay(150); /* wait for warmup */
1453         I915_WRITE(reg, dpll);
1454         POSTING_READ(reg);
1455         udelay(150); /* wait for warmup */
1456         I915_WRITE(reg, dpll);
1457         POSTING_READ(reg);
1458         udelay(150); /* wait for warmup */
1459 }
1460
1461 /**
1462  * i9xx_disable_pll - disable a PLL
1463  * @dev_priv: i915 private structure
1464  * @pipe: pipe PLL to disable
1465  *
1466  * Disable the PLL for @pipe, making sure the pipe is off first.
1467  *
1468  * Note!  This is for pre-ILK only.
1469  */
1470 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1471 {
1472         /* Don't disable pipe A or pipe A PLLs if needed */
1473         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1474                 return;
1475
1476         /* Make sure the pipe isn't still relying on us */
1477         assert_pipe_disabled(dev_priv, pipe);
1478
1479         I915_WRITE(DPLL(pipe), 0);
1480         POSTING_READ(DPLL(pipe));
1481 }
1482
1483 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1484 {
1485         u32 val = 0;
1486
1487         /* Make sure the pipe isn't still relying on us */
1488         assert_pipe_disabled(dev_priv, pipe);
1489
1490         /* Leave integrated clock source enabled */
1491         if (pipe == PIPE_B)
1492                 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1493         I915_WRITE(DPLL(pipe), val);
1494         POSTING_READ(DPLL(pipe));
1495 }
1496
1497 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1498 {
1499         u32 port_mask;
1500
1501         if (!port)
1502                 port_mask = DPLL_PORTB_READY_MASK;
1503         else
1504                 port_mask = DPLL_PORTC_READY_MASK;
1505
1506         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1507                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1508                      'B' + port, I915_READ(DPLL(0)));
1509 }
1510
1511 /**
1512  * ironlake_enable_shared_dpll - enable PCH PLL
1513  * @dev_priv: i915 private structure
1514  * @pipe: pipe PLL to enable
1515  *
1516  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1517  * drives the transcoder clock.
1518  */
1519 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1520 {
1521         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1522         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1523
1524         /* PCH PLLs only available on ILK, SNB and IVB */
1525         BUG_ON(dev_priv->info->gen < 5);
1526         if (WARN_ON(pll == NULL))
1527                 return;
1528
1529         if (WARN_ON(pll->refcount == 0))
1530                 return;
1531
1532         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1533                       pll->name, pll->active, pll->on,
1534                       crtc->base.base.id);
1535
1536         if (pll->active++) {
1537                 WARN_ON(!pll->on);
1538                 assert_shared_dpll_enabled(dev_priv, pll);
1539                 return;
1540         }
1541         WARN_ON(pll->on);
1542
1543         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1544         pll->enable(dev_priv, pll);
1545         pll->on = true;
1546 }
1547
1548 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1549 {
1550         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1551         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1552
1553         /* PCH only available on ILK+ */
1554         BUG_ON(dev_priv->info->gen < 5);
1555         if (WARN_ON(pll == NULL))
1556                return;
1557
1558         if (WARN_ON(pll->refcount == 0))
1559                 return;
1560
1561         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1562                       pll->name, pll->active, pll->on,
1563                       crtc->base.base.id);
1564
1565         if (WARN_ON(pll->active == 0)) {
1566                 assert_shared_dpll_disabled(dev_priv, pll);
1567                 return;
1568         }
1569
1570         assert_shared_dpll_enabled(dev_priv, pll);
1571         WARN_ON(!pll->on);
1572         if (--pll->active)
1573                 return;
1574
1575         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1576         pll->disable(dev_priv, pll);
1577         pll->on = false;
1578 }
1579
1580 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581                                            enum pipe pipe)
1582 {
1583         struct drm_device *dev = dev_priv->dev;
1584         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1586         uint32_t reg, val, pipeconf_val;
1587
1588         /* PCH only available on ILK+ */
1589         BUG_ON(dev_priv->info->gen < 5);
1590
1591         /* Make sure PCH DPLL is enabled */
1592         assert_shared_dpll_enabled(dev_priv,
1593                                    intel_crtc_to_shared_dpll(intel_crtc));
1594
1595         /* FDI must be feeding us bits for PCH ports */
1596         assert_fdi_tx_enabled(dev_priv, pipe);
1597         assert_fdi_rx_enabled(dev_priv, pipe);
1598
1599         if (HAS_PCH_CPT(dev)) {
1600                 /* Workaround: Set the timing override bit before enabling the
1601                  * pch transcoder. */
1602                 reg = TRANS_CHICKEN2(pipe);
1603                 val = I915_READ(reg);
1604                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605                 I915_WRITE(reg, val);
1606         }
1607
1608         reg = PCH_TRANSCONF(pipe);
1609         val = I915_READ(reg);
1610         pipeconf_val = I915_READ(PIPECONF(pipe));
1611
1612         if (HAS_PCH_IBX(dev_priv->dev)) {
1613                 /*
1614                  * make the BPC in transcoder be consistent with
1615                  * that in pipeconf reg.
1616                  */
1617                 val &= ~PIPECONF_BPC_MASK;
1618                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1619         }
1620
1621         val &= ~TRANS_INTERLACE_MASK;
1622         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1623                 if (HAS_PCH_IBX(dev_priv->dev) &&
1624                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625                         val |= TRANS_LEGACY_INTERLACED_ILK;
1626                 else
1627                         val |= TRANS_INTERLACED;
1628         else
1629                 val |= TRANS_PROGRESSIVE;
1630
1631         I915_WRITE(reg, val | TRANS_ENABLE);
1632         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1633                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1634 }
1635
1636 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1637                                       enum transcoder cpu_transcoder)
1638 {
1639         u32 val, pipeconf_val;
1640
1641         /* PCH only available on ILK+ */
1642         BUG_ON(dev_priv->info->gen < 5);
1643
1644         /* FDI must be feeding us bits for PCH ports */
1645         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1646         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1647
1648         /* Workaround: set timing override bit. */
1649         val = I915_READ(_TRANSA_CHICKEN2);
1650         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1651         I915_WRITE(_TRANSA_CHICKEN2, val);
1652
1653         val = TRANS_ENABLE;
1654         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1655
1656         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657             PIPECONF_INTERLACED_ILK)
1658                 val |= TRANS_INTERLACED;
1659         else
1660                 val |= TRANS_PROGRESSIVE;
1661
1662         I915_WRITE(LPT_TRANSCONF, val);
1663         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1664                 DRM_ERROR("Failed to enable PCH transcoder\n");
1665 }
1666
1667 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668                                             enum pipe pipe)
1669 {
1670         struct drm_device *dev = dev_priv->dev;
1671         uint32_t reg, val;
1672
1673         /* FDI relies on the transcoder */
1674         assert_fdi_tx_disabled(dev_priv, pipe);
1675         assert_fdi_rx_disabled(dev_priv, pipe);
1676
1677         /* Ports must be off as well */
1678         assert_pch_ports_disabled(dev_priv, pipe);
1679
1680         reg = PCH_TRANSCONF(pipe);
1681         val = I915_READ(reg);
1682         val &= ~TRANS_ENABLE;
1683         I915_WRITE(reg, val);
1684         /* wait for PCH transcoder off, transcoder state */
1685         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1686                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1687
1688         if (!HAS_PCH_IBX(dev)) {
1689                 /* Workaround: Clear the timing override chicken bit again. */
1690                 reg = TRANS_CHICKEN2(pipe);
1691                 val = I915_READ(reg);
1692                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693                 I915_WRITE(reg, val);
1694         }
1695 }
1696
1697 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1698 {
1699         u32 val;
1700
1701         val = I915_READ(LPT_TRANSCONF);
1702         val &= ~TRANS_ENABLE;
1703         I915_WRITE(LPT_TRANSCONF, val);
1704         /* wait for PCH transcoder off, transcoder state */
1705         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1706                 DRM_ERROR("Failed to disable PCH transcoder\n");
1707
1708         /* Workaround: clear timing override bit. */
1709         val = I915_READ(_TRANSA_CHICKEN2);
1710         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1711         I915_WRITE(_TRANSA_CHICKEN2, val);
1712 }
1713
1714 /**
1715  * intel_enable_pipe - enable a pipe, asserting requirements
1716  * @dev_priv: i915 private structure
1717  * @pipe: pipe to enable
1718  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1719  *
1720  * Enable @pipe, making sure that various hardware specific requirements
1721  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722  *
1723  * @pipe should be %PIPE_A or %PIPE_B.
1724  *
1725  * Will wait until the pipe is actually running (i.e. first vblank) before
1726  * returning.
1727  */
1728 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729                               bool pch_port, bool dsi)
1730 {
1731         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732                                                                       pipe);
1733         enum pipe pch_transcoder;
1734         int reg;
1735         u32 val;
1736
1737         assert_planes_disabled(dev_priv, pipe);
1738         assert_cursor_disabled(dev_priv, pipe);
1739         assert_sprites_disabled(dev_priv, pipe);
1740
1741         if (HAS_PCH_LPT(dev_priv->dev))
1742                 pch_transcoder = TRANSCODER_A;
1743         else
1744                 pch_transcoder = pipe;
1745
1746         /*
1747          * A pipe without a PLL won't actually be able to drive bits from
1748          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1749          * need the check.
1750          */
1751         if (!HAS_PCH_SPLIT(dev_priv->dev))
1752                 if (dsi)
1753                         assert_dsi_pll_enabled(dev_priv);
1754                 else
1755                         assert_pll_enabled(dev_priv, pipe);
1756         else {
1757                 if (pch_port) {
1758                         /* if driving the PCH, we need FDI enabled */
1759                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1760                         assert_fdi_tx_pll_enabled(dev_priv,
1761                                                   (enum pipe) cpu_transcoder);
1762                 }
1763                 /* FIXME: assert CPU port conditions for SNB+ */
1764         }
1765
1766         reg = PIPECONF(cpu_transcoder);
1767         val = I915_READ(reg);
1768         if (val & PIPECONF_ENABLE)
1769                 return;
1770
1771         I915_WRITE(reg, val | PIPECONF_ENABLE);
1772         intel_wait_for_vblank(dev_priv->dev, pipe);
1773 }
1774
1775 /**
1776  * intel_disable_pipe - disable a pipe, asserting requirements
1777  * @dev_priv: i915 private structure
1778  * @pipe: pipe to disable
1779  *
1780  * Disable @pipe, making sure that various hardware specific requirements
1781  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1782  *
1783  * @pipe should be %PIPE_A or %PIPE_B.
1784  *
1785  * Will wait until the pipe has shut down before returning.
1786  */
1787 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1788                                enum pipe pipe)
1789 {
1790         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1791                                                                       pipe);
1792         int reg;
1793         u32 val;
1794
1795         /*
1796          * Make sure planes won't keep trying to pump pixels to us,
1797          * or we might hang the display.
1798          */
1799         assert_planes_disabled(dev_priv, pipe);
1800         assert_cursor_disabled(dev_priv, pipe);
1801         assert_sprites_disabled(dev_priv, pipe);
1802
1803         /* Don't disable pipe A or pipe A PLLs if needed */
1804         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1805                 return;
1806
1807         reg = PIPECONF(cpu_transcoder);
1808         val = I915_READ(reg);
1809         if ((val & PIPECONF_ENABLE) == 0)
1810                 return;
1811
1812         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1813         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1814 }
1815
1816 /*
1817  * Plane regs are double buffered, going from enabled->disabled needs a
1818  * trigger in order to latch.  The display address reg provides this.
1819  */
1820 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1821                                enum plane plane)
1822 {
1823         u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1824
1825         I915_WRITE(reg, I915_READ(reg));
1826         POSTING_READ(reg);
1827 }
1828
1829 /**
1830  * intel_enable_primary_plane - enable the primary plane on a given pipe
1831  * @dev_priv: i915 private structure
1832  * @plane: plane to enable
1833  * @pipe: pipe being fed
1834  *
1835  * Enable @plane on @pipe, making sure that @pipe is running first.
1836  */
1837 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1838                                        enum plane plane, enum pipe pipe)
1839 {
1840         struct intel_crtc *intel_crtc =
1841                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1842         int reg;
1843         u32 val;
1844
1845         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1846         assert_pipe_enabled(dev_priv, pipe);
1847
1848         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1849
1850         intel_crtc->primary_enabled = true;
1851
1852         reg = DSPCNTR(plane);
1853         val = I915_READ(reg);
1854         if (val & DISPLAY_PLANE_ENABLE)
1855                 return;
1856
1857         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1858         intel_flush_primary_plane(dev_priv, plane);
1859         intel_wait_for_vblank(dev_priv->dev, pipe);
1860 }
1861
1862 /**
1863  * intel_disable_primary_plane - disable the primary plane
1864  * @dev_priv: i915 private structure
1865  * @plane: plane to disable
1866  * @pipe: pipe consuming the data
1867  *
1868  * Disable @plane; should be an independent operation.
1869  */
1870 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1871                                         enum plane plane, enum pipe pipe)
1872 {
1873         struct intel_crtc *intel_crtc =
1874                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1875         int reg;
1876         u32 val;
1877
1878         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1879
1880         intel_crtc->primary_enabled = false;
1881
1882         reg = DSPCNTR(plane);
1883         val = I915_READ(reg);
1884         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1885                 return;
1886
1887         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1888         intel_flush_primary_plane(dev_priv, plane);
1889         intel_wait_for_vblank(dev_priv->dev, pipe);
1890 }
1891
1892 static bool need_vtd_wa(struct drm_device *dev)
1893 {
1894 #ifdef CONFIG_INTEL_IOMMU
1895         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1896                 return true;
1897 #endif
1898         return false;
1899 }
1900
1901 int
1902 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1903                            struct drm_i915_gem_object *obj,
1904                            struct intel_ring_buffer *pipelined)
1905 {
1906         struct drm_i915_private *dev_priv = dev->dev_private;
1907         u32 alignment;
1908         int ret;
1909
1910         switch (obj->tiling_mode) {
1911         case I915_TILING_NONE:
1912                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1913                         alignment = 128 * 1024;
1914                 else if (INTEL_INFO(dev)->gen >= 4)
1915                         alignment = 4 * 1024;
1916                 else
1917                         alignment = 64 * 1024;
1918                 break;
1919         case I915_TILING_X:
1920                 /* pin() will align the object as required by fence */
1921                 alignment = 0;
1922                 break;
1923         case I915_TILING_Y:
1924                 /* Despite that we check this in framebuffer_init userspace can
1925                  * screw us over and change the tiling after the fact. Only
1926                  * pinned buffers can't change their tiling. */
1927                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1928                 return -EINVAL;
1929         default:
1930                 BUG();
1931         }
1932
1933         /* Note that the w/a also requires 64 PTE of padding following the
1934          * bo. We currently fill all unused PTE with the shadow page and so
1935          * we should always have valid PTE following the scanout preventing
1936          * the VT-d warning.
1937          */
1938         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1939                 alignment = 256 * 1024;
1940
1941         dev_priv->mm.interruptible = false;
1942         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1943         if (ret)
1944                 goto err_interruptible;
1945
1946         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1947          * fence, whereas 965+ only requires a fence if using
1948          * framebuffer compression.  For simplicity, we always install
1949          * a fence as the cost is not that onerous.
1950          */
1951         ret = i915_gem_object_get_fence(obj);
1952         if (ret)
1953                 goto err_unpin;
1954
1955         i915_gem_object_pin_fence(obj);
1956
1957         dev_priv->mm.interruptible = true;
1958         return 0;
1959
1960 err_unpin:
1961         i915_gem_object_unpin_from_display_plane(obj);
1962 err_interruptible:
1963         dev_priv->mm.interruptible = true;
1964         return ret;
1965 }
1966
1967 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1968 {
1969         i915_gem_object_unpin_fence(obj);
1970         i915_gem_object_unpin_from_display_plane(obj);
1971 }
1972
1973 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1974  * is assumed to be a power-of-two. */
1975 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1976                                              unsigned int tiling_mode,
1977                                              unsigned int cpp,
1978                                              unsigned int pitch)
1979 {
1980         if (tiling_mode != I915_TILING_NONE) {
1981                 unsigned int tile_rows, tiles;
1982
1983                 tile_rows = *y / 8;
1984                 *y %= 8;
1985
1986                 tiles = *x / (512/cpp);
1987                 *x %= 512/cpp;
1988
1989                 return tile_rows * pitch * 8 + tiles * 4096;
1990         } else {
1991                 unsigned int offset;
1992
1993                 offset = *y * pitch + *x * cpp;
1994                 *y = 0;
1995                 *x = (offset & 4095) / cpp;
1996                 return offset & -4096;
1997         }
1998 }
1999
2000 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2001                              int x, int y)
2002 {
2003         struct drm_device *dev = crtc->dev;
2004         struct drm_i915_private *dev_priv = dev->dev_private;
2005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2006         struct intel_framebuffer *intel_fb;
2007         struct drm_i915_gem_object *obj;
2008         int plane = intel_crtc->plane;
2009         unsigned long linear_offset;
2010         u32 dspcntr;
2011         u32 reg;
2012
2013         switch (plane) {
2014         case 0:
2015         case 1:
2016                 break;
2017         default:
2018                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2019                 return -EINVAL;
2020         }
2021
2022         intel_fb = to_intel_framebuffer(fb);
2023         obj = intel_fb->obj;
2024
2025         reg = DSPCNTR(plane);
2026         dspcntr = I915_READ(reg);
2027         /* Mask out pixel format bits in case we change it */
2028         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2029         switch (fb->pixel_format) {
2030         case DRM_FORMAT_C8:
2031                 dspcntr |= DISPPLANE_8BPP;
2032                 break;
2033         case DRM_FORMAT_XRGB1555:
2034         case DRM_FORMAT_ARGB1555:
2035                 dspcntr |= DISPPLANE_BGRX555;
2036                 break;
2037         case DRM_FORMAT_RGB565:
2038                 dspcntr |= DISPPLANE_BGRX565;
2039                 break;
2040         case DRM_FORMAT_XRGB8888:
2041         case DRM_FORMAT_ARGB8888:
2042                 dspcntr |= DISPPLANE_BGRX888;
2043                 break;
2044         case DRM_FORMAT_XBGR8888:
2045         case DRM_FORMAT_ABGR8888:
2046                 dspcntr |= DISPPLANE_RGBX888;
2047                 break;
2048         case DRM_FORMAT_XRGB2101010:
2049         case DRM_FORMAT_ARGB2101010:
2050                 dspcntr |= DISPPLANE_BGRX101010;
2051                 break;
2052         case DRM_FORMAT_XBGR2101010:
2053         case DRM_FORMAT_ABGR2101010:
2054                 dspcntr |= DISPPLANE_RGBX101010;
2055                 break;
2056         default:
2057                 BUG();
2058         }
2059
2060         if (INTEL_INFO(dev)->gen >= 4) {
2061                 if (obj->tiling_mode != I915_TILING_NONE)
2062                         dspcntr |= DISPPLANE_TILED;
2063                 else
2064                         dspcntr &= ~DISPPLANE_TILED;
2065         }
2066
2067         if (IS_G4X(dev))
2068                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2069
2070         I915_WRITE(reg, dspcntr);
2071
2072         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2073
2074         if (INTEL_INFO(dev)->gen >= 4) {
2075                 intel_crtc->dspaddr_offset =
2076                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2077                                                        fb->bits_per_pixel / 8,
2078                                                        fb->pitches[0]);
2079                 linear_offset -= intel_crtc->dspaddr_offset;
2080         } else {
2081                 intel_crtc->dspaddr_offset = linear_offset;
2082         }
2083
2084         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2085                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2086                       fb->pitches[0]);
2087         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2088         if (INTEL_INFO(dev)->gen >= 4) {
2089                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2090                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2091                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2092                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2093         } else
2094                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2095         POSTING_READ(reg);
2096
2097         return 0;
2098 }
2099
2100 static int ironlake_update_plane(struct drm_crtc *crtc,
2101                                  struct drm_framebuffer *fb, int x, int y)
2102 {
2103         struct drm_device *dev = crtc->dev;
2104         struct drm_i915_private *dev_priv = dev->dev_private;
2105         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2106         struct intel_framebuffer *intel_fb;
2107         struct drm_i915_gem_object *obj;
2108         int plane = intel_crtc->plane;
2109         unsigned long linear_offset;
2110         u32 dspcntr;
2111         u32 reg;
2112
2113         switch (plane) {
2114         case 0:
2115         case 1:
2116         case 2:
2117                 break;
2118         default:
2119                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2120                 return -EINVAL;
2121         }
2122
2123         intel_fb = to_intel_framebuffer(fb);
2124         obj = intel_fb->obj;
2125
2126         reg = DSPCNTR(plane);
2127         dspcntr = I915_READ(reg);
2128         /* Mask out pixel format bits in case we change it */
2129         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2130         switch (fb->pixel_format) {
2131         case DRM_FORMAT_C8:
2132                 dspcntr |= DISPPLANE_8BPP;
2133                 break;
2134         case DRM_FORMAT_RGB565:
2135                 dspcntr |= DISPPLANE_BGRX565;
2136                 break;
2137         case DRM_FORMAT_XRGB8888:
2138         case DRM_FORMAT_ARGB8888:
2139                 dspcntr |= DISPPLANE_BGRX888;
2140                 break;
2141         case DRM_FORMAT_XBGR8888:
2142         case DRM_FORMAT_ABGR8888:
2143                 dspcntr |= DISPPLANE_RGBX888;
2144                 break;
2145         case DRM_FORMAT_XRGB2101010:
2146         case DRM_FORMAT_ARGB2101010:
2147                 dspcntr |= DISPPLANE_BGRX101010;
2148                 break;
2149         case DRM_FORMAT_XBGR2101010:
2150         case DRM_FORMAT_ABGR2101010:
2151                 dspcntr |= DISPPLANE_RGBX101010;
2152                 break;
2153         default:
2154                 BUG();
2155         }
2156
2157         if (obj->tiling_mode != I915_TILING_NONE)
2158                 dspcntr |= DISPPLANE_TILED;
2159         else
2160                 dspcntr &= ~DISPPLANE_TILED;
2161
2162         if (IS_HASWELL(dev))
2163                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2164         else
2165                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2166
2167         I915_WRITE(reg, dspcntr);
2168
2169         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2170         intel_crtc->dspaddr_offset =
2171                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2172                                                fb->bits_per_pixel / 8,
2173                                                fb->pitches[0]);
2174         linear_offset -= intel_crtc->dspaddr_offset;
2175
2176         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2177                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2178                       fb->pitches[0]);
2179         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2180         I915_MODIFY_DISPBASE(DSPSURF(plane),
2181                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2182         if (IS_HASWELL(dev)) {
2183                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2184         } else {
2185                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2186                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2187         }
2188         POSTING_READ(reg);
2189
2190         return 0;
2191 }
2192
2193 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2194 static int
2195 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2196                            int x, int y, enum mode_set_atomic state)
2197 {
2198         struct drm_device *dev = crtc->dev;
2199         struct drm_i915_private *dev_priv = dev->dev_private;
2200
2201         if (dev_priv->display.disable_fbc)
2202                 dev_priv->display.disable_fbc(dev);
2203         intel_increase_pllclock(crtc);
2204
2205         return dev_priv->display.update_plane(crtc, fb, x, y);
2206 }
2207
2208 void intel_display_handle_reset(struct drm_device *dev)
2209 {
2210         struct drm_i915_private *dev_priv = dev->dev_private;
2211         struct drm_crtc *crtc;
2212
2213         /*
2214          * Flips in the rings have been nuked by the reset,
2215          * so complete all pending flips so that user space
2216          * will get its events and not get stuck.
2217          *
2218          * Also update the base address of all primary
2219          * planes to the the last fb to make sure we're
2220          * showing the correct fb after a reset.
2221          *
2222          * Need to make two loops over the crtcs so that we
2223          * don't try to grab a crtc mutex before the
2224          * pending_flip_queue really got woken up.
2225          */
2226
2227         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2228                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2229                 enum plane plane = intel_crtc->plane;
2230
2231                 intel_prepare_page_flip(dev, plane);
2232                 intel_finish_page_flip_plane(dev, plane);
2233         }
2234
2235         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2236                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2237
2238                 mutex_lock(&crtc->mutex);
2239                 if (intel_crtc->active)
2240                         dev_priv->display.update_plane(crtc, crtc->fb,
2241                                                        crtc->x, crtc->y);
2242                 mutex_unlock(&crtc->mutex);
2243         }
2244 }
2245
2246 static int
2247 intel_finish_fb(struct drm_framebuffer *old_fb)
2248 {
2249         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2250         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2251         bool was_interruptible = dev_priv->mm.interruptible;
2252         int ret;
2253
2254         /* Big Hammer, we also need to ensure that any pending
2255          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2256          * current scanout is retired before unpinning the old
2257          * framebuffer.
2258          *
2259          * This should only fail upon a hung GPU, in which case we
2260          * can safely continue.
2261          */
2262         dev_priv->mm.interruptible = false;
2263         ret = i915_gem_object_finish_gpu(obj);
2264         dev_priv->mm.interruptible = was_interruptible;
2265
2266         return ret;
2267 }
2268
2269 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2270 {
2271         struct drm_device *dev = crtc->dev;
2272         struct drm_i915_master_private *master_priv;
2273         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2274
2275         if (!dev->primary->master)
2276                 return;
2277
2278         master_priv = dev->primary->master->driver_priv;
2279         if (!master_priv->sarea_priv)
2280                 return;
2281
2282         switch (intel_crtc->pipe) {
2283         case 0:
2284                 master_priv->sarea_priv->pipeA_x = x;
2285                 master_priv->sarea_priv->pipeA_y = y;
2286                 break;
2287         case 1:
2288                 master_priv->sarea_priv->pipeB_x = x;
2289                 master_priv->sarea_priv->pipeB_y = y;
2290                 break;
2291         default:
2292                 break;
2293         }
2294 }
2295
2296 static int
2297 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2298                     struct drm_framebuffer *fb)
2299 {
2300         struct drm_device *dev = crtc->dev;
2301         struct drm_i915_private *dev_priv = dev->dev_private;
2302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2303         struct drm_framebuffer *old_fb;
2304         int ret;
2305
2306         /* no fb bound */
2307         if (!fb) {
2308                 DRM_ERROR("No FB bound\n");
2309                 return 0;
2310         }
2311
2312         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2313                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2314                           plane_name(intel_crtc->plane),
2315                           INTEL_INFO(dev)->num_pipes);
2316                 return -EINVAL;
2317         }
2318
2319         mutex_lock(&dev->struct_mutex);
2320         ret = intel_pin_and_fence_fb_obj(dev,
2321                                          to_intel_framebuffer(fb)->obj,
2322                                          NULL);
2323         if (ret != 0) {
2324                 mutex_unlock(&dev->struct_mutex);
2325                 DRM_ERROR("pin & fence failed\n");
2326                 return ret;
2327         }
2328
2329         /*
2330          * Update pipe size and adjust fitter if needed: the reason for this is
2331          * that in compute_mode_changes we check the native mode (not the pfit
2332          * mode) to see if we can flip rather than do a full mode set. In the
2333          * fastboot case, we'll flip, but if we don't update the pipesrc and
2334          * pfit state, we'll end up with a big fb scanned out into the wrong
2335          * sized surface.
2336          *
2337          * To fix this properly, we need to hoist the checks up into
2338          * compute_mode_changes (or above), check the actual pfit state and
2339          * whether the platform allows pfit disable with pipe active, and only
2340          * then update the pipesrc and pfit state, even on the flip path.
2341          */
2342         if (i915_fastboot) {
2343                 const struct drm_display_mode *adjusted_mode =
2344                         &intel_crtc->config.adjusted_mode;
2345
2346                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2347                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2348                            (adjusted_mode->crtc_vdisplay - 1));
2349                 if (!intel_crtc->config.pch_pfit.enabled &&
2350                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2351                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2352                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2353                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2354                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2355                 }
2356         }
2357
2358         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2359         if (ret) {
2360                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2361                 mutex_unlock(&dev->struct_mutex);
2362                 DRM_ERROR("failed to update base address\n");
2363                 return ret;
2364         }
2365
2366         old_fb = crtc->fb;
2367         crtc->fb = fb;
2368         crtc->x = x;
2369         crtc->y = y;
2370
2371         if (old_fb) {
2372                 if (intel_crtc->active && old_fb != fb)
2373                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2374                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2375         }
2376
2377         intel_update_fbc(dev);
2378         intel_edp_psr_update(dev);
2379         mutex_unlock(&dev->struct_mutex);
2380
2381         intel_crtc_update_sarea_pos(crtc, x, y);
2382
2383         return 0;
2384 }
2385
2386 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2387 {
2388         struct drm_device *dev = crtc->dev;
2389         struct drm_i915_private *dev_priv = dev->dev_private;
2390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2391         int pipe = intel_crtc->pipe;
2392         u32 reg, temp;
2393
2394         /* enable normal train */
2395         reg = FDI_TX_CTL(pipe);
2396         temp = I915_READ(reg);
2397         if (IS_IVYBRIDGE(dev)) {
2398                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2399                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2400         } else {
2401                 temp &= ~FDI_LINK_TRAIN_NONE;
2402                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2403         }
2404         I915_WRITE(reg, temp);
2405
2406         reg = FDI_RX_CTL(pipe);
2407         temp = I915_READ(reg);
2408         if (HAS_PCH_CPT(dev)) {
2409                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2410                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2411         } else {
2412                 temp &= ~FDI_LINK_TRAIN_NONE;
2413                 temp |= FDI_LINK_TRAIN_NONE;
2414         }
2415         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2416
2417         /* wait one idle pattern time */
2418         POSTING_READ(reg);
2419         udelay(1000);
2420
2421         /* IVB wants error correction enabled */
2422         if (IS_IVYBRIDGE(dev))
2423                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2424                            FDI_FE_ERRC_ENABLE);
2425 }
2426
2427 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2428 {
2429         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2430 }
2431
2432 static void ivb_modeset_global_resources(struct drm_device *dev)
2433 {
2434         struct drm_i915_private *dev_priv = dev->dev_private;
2435         struct intel_crtc *pipe_B_crtc =
2436                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2437         struct intel_crtc *pipe_C_crtc =
2438                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2439         uint32_t temp;
2440
2441         /*
2442          * When everything is off disable fdi C so that we could enable fdi B
2443          * with all lanes. Note that we don't care about enabled pipes without
2444          * an enabled pch encoder.
2445          */
2446         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2447             !pipe_has_enabled_pch(pipe_C_crtc)) {
2448                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2449                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2450
2451                 temp = I915_READ(SOUTH_CHICKEN1);
2452                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2453                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2454                 I915_WRITE(SOUTH_CHICKEN1, temp);
2455         }
2456 }
2457
2458 /* The FDI link training functions for ILK/Ibexpeak. */
2459 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2460 {
2461         struct drm_device *dev = crtc->dev;
2462         struct drm_i915_private *dev_priv = dev->dev_private;
2463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2464         int pipe = intel_crtc->pipe;
2465         int plane = intel_crtc->plane;
2466         u32 reg, temp, tries;
2467
2468         /* FDI needs bits from pipe & plane first */
2469         assert_pipe_enabled(dev_priv, pipe);
2470         assert_plane_enabled(dev_priv, plane);
2471
2472         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2473            for train result */
2474         reg = FDI_RX_IMR(pipe);
2475         temp = I915_READ(reg);
2476         temp &= ~FDI_RX_SYMBOL_LOCK;
2477         temp &= ~FDI_RX_BIT_LOCK;
2478         I915_WRITE(reg, temp);
2479         I915_READ(reg);
2480         udelay(150);
2481
2482         /* enable CPU FDI TX and PCH FDI RX */
2483         reg = FDI_TX_CTL(pipe);
2484         temp = I915_READ(reg);
2485         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2486         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2487         temp &= ~FDI_LINK_TRAIN_NONE;
2488         temp |= FDI_LINK_TRAIN_PATTERN_1;
2489         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2490
2491         reg = FDI_RX_CTL(pipe);
2492         temp = I915_READ(reg);
2493         temp &= ~FDI_LINK_TRAIN_NONE;
2494         temp |= FDI_LINK_TRAIN_PATTERN_1;
2495         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2496
2497         POSTING_READ(reg);
2498         udelay(150);
2499
2500         /* Ironlake workaround, enable clock pointer after FDI enable*/
2501         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2502         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2503                    FDI_RX_PHASE_SYNC_POINTER_EN);
2504
2505         reg = FDI_RX_IIR(pipe);
2506         for (tries = 0; tries < 5; tries++) {
2507                 temp = I915_READ(reg);
2508                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2509
2510                 if ((temp & FDI_RX_BIT_LOCK)) {
2511                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2512                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2513                         break;
2514                 }
2515         }
2516         if (tries == 5)
2517                 DRM_ERROR("FDI train 1 fail!\n");
2518
2519         /* Train 2 */
2520         reg = FDI_TX_CTL(pipe);
2521         temp = I915_READ(reg);
2522         temp &= ~FDI_LINK_TRAIN_NONE;
2523         temp |= FDI_LINK_TRAIN_PATTERN_2;
2524         I915_WRITE(reg, temp);
2525
2526         reg = FDI_RX_CTL(pipe);
2527         temp = I915_READ(reg);
2528         temp &= ~FDI_LINK_TRAIN_NONE;
2529         temp |= FDI_LINK_TRAIN_PATTERN_2;
2530         I915_WRITE(reg, temp);
2531
2532         POSTING_READ(reg);
2533         udelay(150);
2534
2535         reg = FDI_RX_IIR(pipe);
2536         for (tries = 0; tries < 5; tries++) {
2537                 temp = I915_READ(reg);
2538                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2539
2540                 if (temp & FDI_RX_SYMBOL_LOCK) {
2541                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2542                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2543                         break;
2544                 }
2545         }
2546         if (tries == 5)
2547                 DRM_ERROR("FDI train 2 fail!\n");
2548
2549         DRM_DEBUG_KMS("FDI train done\n");
2550
2551 }
2552
2553 static const int snb_b_fdi_train_param[] = {
2554         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2555         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2556         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2557         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2558 };
2559
2560 /* The FDI link training functions for SNB/Cougarpoint. */
2561 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2562 {
2563         struct drm_device *dev = crtc->dev;
2564         struct drm_i915_private *dev_priv = dev->dev_private;
2565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2566         int pipe = intel_crtc->pipe;
2567         u32 reg, temp, i, retry;
2568
2569         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2570            for train result */
2571         reg = FDI_RX_IMR(pipe);
2572         temp = I915_READ(reg);
2573         temp &= ~FDI_RX_SYMBOL_LOCK;
2574         temp &= ~FDI_RX_BIT_LOCK;
2575         I915_WRITE(reg, temp);
2576
2577         POSTING_READ(reg);
2578         udelay(150);
2579
2580         /* enable CPU FDI TX and PCH FDI RX */
2581         reg = FDI_TX_CTL(pipe);
2582         temp = I915_READ(reg);
2583         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2584         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2585         temp &= ~FDI_LINK_TRAIN_NONE;
2586         temp |= FDI_LINK_TRAIN_PATTERN_1;
2587         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588         /* SNB-B */
2589         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2591
2592         I915_WRITE(FDI_RX_MISC(pipe),
2593                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2594
2595         reg = FDI_RX_CTL(pipe);
2596         temp = I915_READ(reg);
2597         if (HAS_PCH_CPT(dev)) {
2598                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2599                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2600         } else {
2601                 temp &= ~FDI_LINK_TRAIN_NONE;
2602                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2603         }
2604         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2605
2606         POSTING_READ(reg);
2607         udelay(150);
2608
2609         for (i = 0; i < 4; i++) {
2610                 reg = FDI_TX_CTL(pipe);
2611                 temp = I915_READ(reg);
2612                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2613                 temp |= snb_b_fdi_train_param[i];
2614                 I915_WRITE(reg, temp);
2615
2616                 POSTING_READ(reg);
2617                 udelay(500);
2618
2619                 for (retry = 0; retry < 5; retry++) {
2620                         reg = FDI_RX_IIR(pipe);
2621                         temp = I915_READ(reg);
2622                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2623                         if (temp & FDI_RX_BIT_LOCK) {
2624                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2625                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2626                                 break;
2627                         }
2628                         udelay(50);
2629                 }
2630                 if (retry < 5)
2631                         break;
2632         }
2633         if (i == 4)
2634                 DRM_ERROR("FDI train 1 fail!\n");
2635
2636         /* Train 2 */
2637         reg = FDI_TX_CTL(pipe);
2638         temp = I915_READ(reg);
2639         temp &= ~FDI_LINK_TRAIN_NONE;
2640         temp |= FDI_LINK_TRAIN_PATTERN_2;
2641         if (IS_GEN6(dev)) {
2642                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2643                 /* SNB-B */
2644                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2645         }
2646         I915_WRITE(reg, temp);
2647
2648         reg = FDI_RX_CTL(pipe);
2649         temp = I915_READ(reg);
2650         if (HAS_PCH_CPT(dev)) {
2651                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2652                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2653         } else {
2654                 temp &= ~FDI_LINK_TRAIN_NONE;
2655                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2656         }
2657         I915_WRITE(reg, temp);
2658
2659         POSTING_READ(reg);
2660         udelay(150);
2661
2662         for (i = 0; i < 4; i++) {
2663                 reg = FDI_TX_CTL(pipe);
2664                 temp = I915_READ(reg);
2665                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2666                 temp |= snb_b_fdi_train_param[i];
2667                 I915_WRITE(reg, temp);
2668
2669                 POSTING_READ(reg);
2670                 udelay(500);
2671
2672                 for (retry = 0; retry < 5; retry++) {
2673                         reg = FDI_RX_IIR(pipe);
2674                         temp = I915_READ(reg);
2675                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2676                         if (temp & FDI_RX_SYMBOL_LOCK) {
2677                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2678                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2679                                 break;
2680                         }
2681                         udelay(50);
2682                 }
2683                 if (retry < 5)
2684                         break;
2685         }
2686         if (i == 4)
2687                 DRM_ERROR("FDI train 2 fail!\n");
2688
2689         DRM_DEBUG_KMS("FDI train done.\n");
2690 }
2691
2692 /* Manual link training for Ivy Bridge A0 parts */
2693 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2694 {
2695         struct drm_device *dev = crtc->dev;
2696         struct drm_i915_private *dev_priv = dev->dev_private;
2697         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2698         int pipe = intel_crtc->pipe;
2699         u32 reg, temp, i, j;
2700
2701         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2702            for train result */
2703         reg = FDI_RX_IMR(pipe);
2704         temp = I915_READ(reg);
2705         temp &= ~FDI_RX_SYMBOL_LOCK;
2706         temp &= ~FDI_RX_BIT_LOCK;
2707         I915_WRITE(reg, temp);
2708
2709         POSTING_READ(reg);
2710         udelay(150);
2711
2712         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2713                       I915_READ(FDI_RX_IIR(pipe)));
2714
2715         /* Try each vswing and preemphasis setting twice before moving on */
2716         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2717                 /* disable first in case we need to retry */
2718                 reg = FDI_TX_CTL(pipe);
2719                 temp = I915_READ(reg);
2720                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2721                 temp &= ~FDI_TX_ENABLE;
2722                 I915_WRITE(reg, temp);
2723
2724                 reg = FDI_RX_CTL(pipe);
2725                 temp = I915_READ(reg);
2726                 temp &= ~FDI_LINK_TRAIN_AUTO;
2727                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2728                 temp &= ~FDI_RX_ENABLE;
2729                 I915_WRITE(reg, temp);
2730
2731                 /* enable CPU FDI TX and PCH FDI RX */
2732                 reg = FDI_TX_CTL(pipe);
2733                 temp = I915_READ(reg);
2734                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2735                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2736                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2737                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2738                 temp |= snb_b_fdi_train_param[j/2];
2739                 temp |= FDI_COMPOSITE_SYNC;
2740                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2741
2742                 I915_WRITE(FDI_RX_MISC(pipe),
2743                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2744
2745                 reg = FDI_RX_CTL(pipe);
2746                 temp = I915_READ(reg);
2747                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2748                 temp |= FDI_COMPOSITE_SYNC;
2749                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2750
2751                 POSTING_READ(reg);
2752                 udelay(1); /* should be 0.5us */
2753
2754                 for (i = 0; i < 4; i++) {
2755                         reg = FDI_RX_IIR(pipe);
2756                         temp = I915_READ(reg);
2757                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2758
2759                         if (temp & FDI_RX_BIT_LOCK ||
2760                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2761                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2762                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2763                                               i);
2764                                 break;
2765                         }
2766                         udelay(1); /* should be 0.5us */
2767                 }
2768                 if (i == 4) {
2769                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2770                         continue;
2771                 }
2772
2773                 /* Train 2 */
2774                 reg = FDI_TX_CTL(pipe);
2775                 temp = I915_READ(reg);
2776                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2777                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2778                 I915_WRITE(reg, temp);
2779
2780                 reg = FDI_RX_CTL(pipe);
2781                 temp = I915_READ(reg);
2782                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2783                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2784                 I915_WRITE(reg, temp);
2785
2786                 POSTING_READ(reg);
2787                 udelay(2); /* should be 1.5us */
2788
2789                 for (i = 0; i < 4; i++) {
2790                         reg = FDI_RX_IIR(pipe);
2791                         temp = I915_READ(reg);
2792                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2793
2794                         if (temp & FDI_RX_SYMBOL_LOCK ||
2795                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2796                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2797                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2798                                               i);
2799                                 goto train_done;
2800                         }
2801                         udelay(2); /* should be 1.5us */
2802                 }
2803                 if (i == 4)
2804                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2805         }
2806
2807 train_done:
2808         DRM_DEBUG_KMS("FDI train done.\n");
2809 }
2810
2811 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2812 {
2813         struct drm_device *dev = intel_crtc->base.dev;
2814         struct drm_i915_private *dev_priv = dev->dev_private;
2815         int pipe = intel_crtc->pipe;
2816         u32 reg, temp;
2817
2818
2819         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2820         reg = FDI_RX_CTL(pipe);
2821         temp = I915_READ(reg);
2822         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2823         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2824         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2825         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2826
2827         POSTING_READ(reg);
2828         udelay(200);
2829
2830         /* Switch from Rawclk to PCDclk */
2831         temp = I915_READ(reg);
2832         I915_WRITE(reg, temp | FDI_PCDCLK);
2833
2834         POSTING_READ(reg);
2835         udelay(200);
2836
2837         /* Enable CPU FDI TX PLL, always on for Ironlake */
2838         reg = FDI_TX_CTL(pipe);
2839         temp = I915_READ(reg);
2840         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2841                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2842
2843                 POSTING_READ(reg);
2844                 udelay(100);
2845         }
2846 }
2847
2848 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2849 {
2850         struct drm_device *dev = intel_crtc->base.dev;
2851         struct drm_i915_private *dev_priv = dev->dev_private;
2852         int pipe = intel_crtc->pipe;
2853         u32 reg, temp;
2854
2855         /* Switch from PCDclk to Rawclk */
2856         reg = FDI_RX_CTL(pipe);
2857         temp = I915_READ(reg);
2858         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2859
2860         /* Disable CPU FDI TX PLL */
2861         reg = FDI_TX_CTL(pipe);
2862         temp = I915_READ(reg);
2863         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2864
2865         POSTING_READ(reg);
2866         udelay(100);
2867
2868         reg = FDI_RX_CTL(pipe);
2869         temp = I915_READ(reg);
2870         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2871
2872         /* Wait for the clocks to turn off. */
2873         POSTING_READ(reg);
2874         udelay(100);
2875 }
2876
2877 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2878 {
2879         struct drm_device *dev = crtc->dev;
2880         struct drm_i915_private *dev_priv = dev->dev_private;
2881         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2882         int pipe = intel_crtc->pipe;
2883         u32 reg, temp;
2884
2885         /* disable CPU FDI tx and PCH FDI rx */
2886         reg = FDI_TX_CTL(pipe);
2887         temp = I915_READ(reg);
2888         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2889         POSTING_READ(reg);
2890
2891         reg = FDI_RX_CTL(pipe);
2892         temp = I915_READ(reg);
2893         temp &= ~(0x7 << 16);
2894         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2895         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2896
2897         POSTING_READ(reg);
2898         udelay(100);
2899
2900         /* Ironlake workaround, disable clock pointer after downing FDI */
2901         if (HAS_PCH_IBX(dev)) {
2902                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2903         }
2904
2905         /* still set train pattern 1 */
2906         reg = FDI_TX_CTL(pipe);
2907         temp = I915_READ(reg);
2908         temp &= ~FDI_LINK_TRAIN_NONE;
2909         temp |= FDI_LINK_TRAIN_PATTERN_1;
2910         I915_WRITE(reg, temp);
2911
2912         reg = FDI_RX_CTL(pipe);
2913         temp = I915_READ(reg);
2914         if (HAS_PCH_CPT(dev)) {
2915                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2916                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2917         } else {
2918                 temp &= ~FDI_LINK_TRAIN_NONE;
2919                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2920         }
2921         /* BPC in FDI rx is consistent with that in PIPECONF */
2922         temp &= ~(0x07 << 16);
2923         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2924         I915_WRITE(reg, temp);
2925
2926         POSTING_READ(reg);
2927         udelay(100);
2928 }
2929
2930 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2931 {
2932         struct drm_device *dev = crtc->dev;
2933         struct drm_i915_private *dev_priv = dev->dev_private;
2934         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2935         unsigned long flags;
2936         bool pending;
2937
2938         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2939             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2940                 return false;
2941
2942         spin_lock_irqsave(&dev->event_lock, flags);
2943         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2944         spin_unlock_irqrestore(&dev->event_lock, flags);
2945
2946         return pending;
2947 }
2948
2949 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2950 {
2951         struct drm_device *dev = crtc->dev;
2952         struct drm_i915_private *dev_priv = dev->dev_private;
2953
2954         if (crtc->fb == NULL)
2955                 return;
2956
2957         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2958
2959         wait_event(dev_priv->pending_flip_queue,
2960                    !intel_crtc_has_pending_flip(crtc));
2961
2962         mutex_lock(&dev->struct_mutex);
2963         intel_finish_fb(crtc->fb);
2964         mutex_unlock(&dev->struct_mutex);
2965 }
2966
2967 /* Program iCLKIP clock to the desired frequency */
2968 static void lpt_program_iclkip(struct drm_crtc *crtc)
2969 {
2970         struct drm_device *dev = crtc->dev;
2971         struct drm_i915_private *dev_priv = dev->dev_private;
2972         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2973         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2974         u32 temp;
2975
2976         mutex_lock(&dev_priv->dpio_lock);
2977
2978         /* It is necessary to ungate the pixclk gate prior to programming
2979          * the divisors, and gate it back when it is done.
2980          */
2981         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2982
2983         /* Disable SSCCTL */
2984         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2985                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2986                                 SBI_SSCCTL_DISABLE,
2987                         SBI_ICLK);
2988
2989         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2990         if (clock == 20000) {
2991                 auxdiv = 1;
2992                 divsel = 0x41;
2993                 phaseinc = 0x20;
2994         } else {
2995                 /* The iCLK virtual clock root frequency is in MHz,
2996                  * but the adjusted_mode->crtc_clock in in KHz. To get the
2997                  * divisors, it is necessary to divide one by another, so we
2998                  * convert the virtual clock precision to KHz here for higher
2999                  * precision.
3000                  */
3001                 u32 iclk_virtual_root_freq = 172800 * 1000;
3002                 u32 iclk_pi_range = 64;
3003                 u32 desired_divisor, msb_divisor_value, pi_value;
3004
3005                 desired_divisor = (iclk_virtual_root_freq / clock);
3006                 msb_divisor_value = desired_divisor / iclk_pi_range;
3007                 pi_value = desired_divisor % iclk_pi_range;
3008
3009                 auxdiv = 0;
3010                 divsel = msb_divisor_value - 2;
3011                 phaseinc = pi_value;
3012         }
3013
3014         /* This should not happen with any sane values */
3015         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3016                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3017         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3018                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3019
3020         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3021                         clock,
3022                         auxdiv,
3023                         divsel,
3024                         phasedir,
3025                         phaseinc);
3026
3027         /* Program SSCDIVINTPHASE6 */
3028         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3029         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3030         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3031         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3032         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3033         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3034         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3035         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3036
3037         /* Program SSCAUXDIV */
3038         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3039         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3040         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3041         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3042
3043         /* Enable modulator and associated divider */
3044         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3045         temp &= ~SBI_SSCCTL_DISABLE;
3046         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3047
3048         /* Wait for initialization time */
3049         udelay(24);
3050
3051         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3052
3053         mutex_unlock(&dev_priv->dpio_lock);
3054 }
3055
3056 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3057                                                 enum pipe pch_transcoder)
3058 {
3059         struct drm_device *dev = crtc->base.dev;
3060         struct drm_i915_private *dev_priv = dev->dev_private;
3061         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3062
3063         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3064                    I915_READ(HTOTAL(cpu_transcoder)));
3065         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3066                    I915_READ(HBLANK(cpu_transcoder)));
3067         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3068                    I915_READ(HSYNC(cpu_transcoder)));
3069
3070         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3071                    I915_READ(VTOTAL(cpu_transcoder)));
3072         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3073                    I915_READ(VBLANK(cpu_transcoder)));
3074         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3075                    I915_READ(VSYNC(cpu_transcoder)));
3076         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3077                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3078 }
3079
3080 /*
3081  * Enable PCH resources required for PCH ports:
3082  *   - PCH PLLs
3083  *   - FDI training & RX/TX
3084  *   - update transcoder timings
3085  *   - DP transcoding bits
3086  *   - transcoder
3087  */
3088 static void ironlake_pch_enable(struct drm_crtc *crtc)
3089 {
3090         struct drm_device *dev = crtc->dev;
3091         struct drm_i915_private *dev_priv = dev->dev_private;
3092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3093         int pipe = intel_crtc->pipe;
3094         u32 reg, temp;
3095
3096         assert_pch_transcoder_disabled(dev_priv, pipe);
3097
3098         /* Write the TU size bits before fdi link training, so that error
3099          * detection works. */
3100         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3101                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3102
3103         /* For PCH output, training FDI link */
3104         dev_priv->display.fdi_link_train(crtc);
3105
3106         /* We need to program the right clock selection before writing the pixel
3107          * mutliplier into the DPLL. */
3108         if (HAS_PCH_CPT(dev)) {
3109                 u32 sel;
3110
3111                 temp = I915_READ(PCH_DPLL_SEL);
3112                 temp |= TRANS_DPLL_ENABLE(pipe);
3113                 sel = TRANS_DPLLB_SEL(pipe);
3114                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3115                         temp |= sel;
3116                 else
3117                         temp &= ~sel;
3118                 I915_WRITE(PCH_DPLL_SEL, temp);
3119         }
3120
3121         /* XXX: pch pll's can be enabled any time before we enable the PCH
3122          * transcoder, and we actually should do this to not upset any PCH
3123          * transcoder that already use the clock when we share it.
3124          *
3125          * Note that enable_shared_dpll tries to do the right thing, but
3126          * get_shared_dpll unconditionally resets the pll - we need that to have
3127          * the right LVDS enable sequence. */
3128         ironlake_enable_shared_dpll(intel_crtc);
3129
3130         /* set transcoder timing, panel must allow it */
3131         assert_panel_unlocked(dev_priv, pipe);
3132         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3133
3134         intel_fdi_normal_train(crtc);
3135
3136         /* For PCH DP, enable TRANS_DP_CTL */
3137         if (HAS_PCH_CPT(dev) &&
3138             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3139              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3140                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3141                 reg = TRANS_DP_CTL(pipe);
3142                 temp = I915_READ(reg);
3143                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3144                           TRANS_DP_SYNC_MASK |
3145                           TRANS_DP_BPC_MASK);
3146                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3147                          TRANS_DP_ENH_FRAMING);
3148                 temp |= bpc << 9; /* same format but at 11:9 */
3149
3150                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3151                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3152                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3153                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3154
3155                 switch (intel_trans_dp_port_sel(crtc)) {
3156                 case PCH_DP_B:
3157                         temp |= TRANS_DP_PORT_SEL_B;
3158                         break;
3159                 case PCH_DP_C:
3160                         temp |= TRANS_DP_PORT_SEL_C;
3161                         break;
3162                 case PCH_DP_D:
3163                         temp |= TRANS_DP_PORT_SEL_D;
3164                         break;
3165                 default:
3166                         BUG();
3167                 }
3168
3169                 I915_WRITE(reg, temp);
3170         }
3171
3172         ironlake_enable_pch_transcoder(dev_priv, pipe);
3173 }
3174
3175 static void lpt_pch_enable(struct drm_crtc *crtc)
3176 {
3177         struct drm_device *dev = crtc->dev;
3178         struct drm_i915_private *dev_priv = dev->dev_private;
3179         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3180         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3181
3182         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3183
3184         lpt_program_iclkip(crtc);
3185
3186         /* Set transcoder timing. */
3187         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3188
3189         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3190 }
3191
3192 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3193 {
3194         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3195
3196         if (pll == NULL)
3197                 return;
3198
3199         if (pll->refcount == 0) {
3200                 WARN(1, "bad %s refcount\n", pll->name);
3201                 return;
3202         }
3203
3204         if (--pll->refcount == 0) {
3205                 WARN_ON(pll->on);
3206                 WARN_ON(pll->active);
3207         }
3208
3209         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3210 }
3211
3212 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3213 {
3214         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3215         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3216         enum intel_dpll_id i;
3217
3218         if (pll) {
3219                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3220                               crtc->base.base.id, pll->name);
3221                 intel_put_shared_dpll(crtc);
3222         }
3223
3224         if (HAS_PCH_IBX(dev_priv->dev)) {
3225                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3226                 i = (enum intel_dpll_id) crtc->pipe;
3227                 pll = &dev_priv->shared_dplls[i];
3228
3229                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3230                               crtc->base.base.id, pll->name);
3231
3232                 goto found;
3233         }
3234
3235         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3236                 pll = &dev_priv->shared_dplls[i];
3237
3238                 /* Only want to check enabled timings first */
3239                 if (pll->refcount == 0)
3240                         continue;
3241
3242                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3243                            sizeof(pll->hw_state)) == 0) {
3244                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3245                                       crtc->base.base.id,
3246                                       pll->name, pll->refcount, pll->active);
3247
3248                         goto found;
3249                 }
3250         }
3251
3252         /* Ok no matching timings, maybe there's a free one? */
3253         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3254                 pll = &dev_priv->shared_dplls[i];
3255                 if (pll->refcount == 0) {
3256                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3257                                       crtc->base.base.id, pll->name);
3258                         goto found;
3259                 }
3260         }
3261
3262         return NULL;
3263
3264 found:
3265         crtc->config.shared_dpll = i;
3266         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3267                          pipe_name(crtc->pipe));
3268
3269         if (pll->active == 0) {
3270                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3271                        sizeof(pll->hw_state));
3272
3273                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3274                 WARN_ON(pll->on);
3275                 assert_shared_dpll_disabled(dev_priv, pll);
3276
3277                 pll->mode_set(dev_priv, pll);
3278         }
3279         pll->refcount++;
3280
3281         return pll;
3282 }
3283
3284 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3285 {
3286         struct drm_i915_private *dev_priv = dev->dev_private;
3287         int dslreg = PIPEDSL(pipe);
3288         u32 temp;
3289
3290         temp = I915_READ(dslreg);
3291         udelay(500);
3292         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3293                 if (wait_for(I915_READ(dslreg) != temp, 5))
3294                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3295         }
3296 }
3297
3298 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3299 {
3300         struct drm_device *dev = crtc->base.dev;
3301         struct drm_i915_private *dev_priv = dev->dev_private;
3302         int pipe = crtc->pipe;
3303
3304         if (crtc->config.pch_pfit.enabled) {
3305                 /* Force use of hard-coded filter coefficients
3306                  * as some pre-programmed values are broken,
3307                  * e.g. x201.
3308                  */
3309                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3310                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3311                                                  PF_PIPE_SEL_IVB(pipe));
3312                 else
3313                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3314                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3315                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3316         }
3317 }
3318
3319 static void intel_enable_planes(struct drm_crtc *crtc)
3320 {
3321         struct drm_device *dev = crtc->dev;
3322         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3323         struct intel_plane *intel_plane;
3324
3325         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3326                 if (intel_plane->pipe == pipe)
3327                         intel_plane_restore(&intel_plane->base);
3328 }
3329
3330 static void intel_disable_planes(struct drm_crtc *crtc)
3331 {
3332         struct drm_device *dev = crtc->dev;
3333         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3334         struct intel_plane *intel_plane;
3335
3336         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3337                 if (intel_plane->pipe == pipe)
3338                         intel_plane_disable(&intel_plane->base);
3339 }
3340
3341 void hsw_enable_ips(struct intel_crtc *crtc)
3342 {
3343         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3344
3345         if (!crtc->config.ips_enabled)
3346                 return;
3347
3348         /* We can only enable IPS after we enable a plane and wait for a vblank.
3349          * We guarantee that the plane is enabled by calling intel_enable_ips
3350          * only after intel_enable_plane. And intel_enable_plane already waits
3351          * for a vblank, so all we need to do here is to enable the IPS bit. */
3352         assert_plane_enabled(dev_priv, crtc->plane);
3353         I915_WRITE(IPS_CTL, IPS_ENABLE);
3354
3355         /* The bit only becomes 1 in the next vblank, so this wait here is
3356          * essentially intel_wait_for_vblank. If we don't have this and don't
3357          * wait for vblanks until the end of crtc_enable, then the HW state
3358          * readout code will complain that the expected IPS_CTL value is not the
3359          * one we read. */
3360         if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3361                 DRM_ERROR("Timed out waiting for IPS enable\n");
3362 }
3363
3364 void hsw_disable_ips(struct intel_crtc *crtc)
3365 {
3366         struct drm_device *dev = crtc->base.dev;
3367         struct drm_i915_private *dev_priv = dev->dev_private;
3368
3369         if (!crtc->config.ips_enabled)
3370                 return;
3371
3372         assert_plane_enabled(dev_priv, crtc->plane);
3373         I915_WRITE(IPS_CTL, 0);
3374         POSTING_READ(IPS_CTL);
3375
3376         /* We need to wait for a vblank before we can disable the plane. */
3377         intel_wait_for_vblank(dev, crtc->pipe);
3378 }
3379
3380 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3381 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3382 {
3383         struct drm_device *dev = crtc->dev;
3384         struct drm_i915_private *dev_priv = dev->dev_private;
3385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3386         enum pipe pipe = intel_crtc->pipe;
3387         int palreg = PALETTE(pipe);
3388         int i;
3389         bool reenable_ips = false;
3390
3391         /* The clocks have to be on to load the palette. */
3392         if (!crtc->enabled || !intel_crtc->active)
3393                 return;
3394
3395         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3396                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3397                         assert_dsi_pll_enabled(dev_priv);
3398                 else
3399                         assert_pll_enabled(dev_priv, pipe);
3400         }
3401
3402         /* use legacy palette for Ironlake */
3403         if (HAS_PCH_SPLIT(dev))
3404                 palreg = LGC_PALETTE(pipe);
3405
3406         /* Workaround : Do not read or write the pipe palette/gamma data while
3407          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3408          */
3409         if (intel_crtc->config.ips_enabled &&
3410             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3411              GAMMA_MODE_MODE_SPLIT)) {
3412                 hsw_disable_ips(intel_crtc);
3413                 reenable_ips = true;
3414         }
3415
3416         for (i = 0; i < 256; i++) {
3417                 I915_WRITE(palreg + 4 * i,
3418                            (intel_crtc->lut_r[i] << 16) |
3419                            (intel_crtc->lut_g[i] << 8) |
3420                            intel_crtc->lut_b[i]);
3421         }
3422
3423         if (reenable_ips)
3424                 hsw_enable_ips(intel_crtc);
3425 }
3426
3427 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3428 {
3429         struct drm_device *dev = crtc->dev;
3430         struct drm_i915_private *dev_priv = dev->dev_private;
3431         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3432         struct intel_encoder *encoder;
3433         int pipe = intel_crtc->pipe;
3434         int plane = intel_crtc->plane;
3435
3436         WARN_ON(!crtc->enabled);
3437
3438         if (intel_crtc->active)
3439                 return;
3440
3441         intel_crtc->active = true;
3442
3443         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3444         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3445
3446         for_each_encoder_on_crtc(dev, crtc, encoder)
3447                 if (encoder->pre_enable)
3448                         encoder->pre_enable(encoder);
3449
3450         if (intel_crtc->config.has_pch_encoder) {
3451                 /* Note: FDI PLL enabling _must_ be done before we enable the
3452                  * cpu pipes, hence this is separate from all the other fdi/pch
3453                  * enabling. */
3454                 ironlake_fdi_pll_enable(intel_crtc);
3455         } else {
3456                 assert_fdi_tx_disabled(dev_priv, pipe);
3457                 assert_fdi_rx_disabled(dev_priv, pipe);
3458         }
3459
3460         ironlake_pfit_enable(intel_crtc);
3461
3462         /*
3463          * On ILK+ LUT must be loaded before the pipe is running but with
3464          * clocks enabled
3465          */
3466         intel_crtc_load_lut(crtc);
3467
3468         intel_update_watermarks(crtc);
3469         intel_enable_pipe(dev_priv, pipe,
3470                           intel_crtc->config.has_pch_encoder, false);
3471         intel_enable_primary_plane(dev_priv, plane, pipe);
3472         intel_enable_planes(crtc);
3473         intel_crtc_update_cursor(crtc, true);
3474
3475         if (intel_crtc->config.has_pch_encoder)
3476                 ironlake_pch_enable(crtc);
3477
3478         mutex_lock(&dev->struct_mutex);
3479         intel_update_fbc(dev);
3480         mutex_unlock(&dev->struct_mutex);
3481
3482         for_each_encoder_on_crtc(dev, crtc, encoder)
3483                 encoder->enable(encoder);
3484
3485         if (HAS_PCH_CPT(dev))
3486                 cpt_verify_modeset(dev, intel_crtc->pipe);
3487
3488         /*
3489          * There seems to be a race in PCH platform hw (at least on some
3490          * outputs) where an enabled pipe still completes any pageflip right
3491          * away (as if the pipe is off) instead of waiting for vblank. As soon
3492          * as the first vblank happend, everything works as expected. Hence just
3493          * wait for one vblank before returning to avoid strange things
3494          * happening.
3495          */
3496         intel_wait_for_vblank(dev, intel_crtc->pipe);
3497 }
3498
3499 /* IPS only exists on ULT machines and is tied to pipe A. */
3500 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3501 {
3502         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3503 }
3504
3505 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3506 {
3507         struct drm_device *dev = crtc->dev;
3508         struct drm_i915_private *dev_priv = dev->dev_private;
3509         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3510         int pipe = intel_crtc->pipe;
3511         int plane = intel_crtc->plane;
3512
3513         intel_enable_primary_plane(dev_priv, plane, pipe);
3514         intel_enable_planes(crtc);
3515         intel_crtc_update_cursor(crtc, true);
3516
3517         hsw_enable_ips(intel_crtc);
3518
3519         mutex_lock(&dev->struct_mutex);
3520         intel_update_fbc(dev);
3521         mutex_unlock(&dev->struct_mutex);
3522 }
3523
3524 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3525 {
3526         struct drm_device *dev = crtc->dev;
3527         struct drm_i915_private *dev_priv = dev->dev_private;
3528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3529         int pipe = intel_crtc->pipe;
3530         int plane = intel_crtc->plane;
3531
3532         intel_crtc_wait_for_pending_flips(crtc);
3533         drm_vblank_off(dev, pipe);
3534
3535         /* FBC must be disabled before disabling the plane on HSW. */
3536         if (dev_priv->fbc.plane == plane)
3537                 intel_disable_fbc(dev);
3538
3539         hsw_disable_ips(intel_crtc);
3540
3541         intel_crtc_update_cursor(crtc, false);
3542         intel_disable_planes(crtc);
3543         intel_disable_primary_plane(dev_priv, plane, pipe);
3544 }
3545
3546 /*
3547  * This implements the workaround described in the "notes" section of the mode
3548  * set sequence documentation. When going from no pipes or single pipe to
3549  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3550  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3551  */
3552 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3553 {
3554         struct drm_device *dev = crtc->base.dev;
3555         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3556
3557         /* We want to get the other_active_crtc only if there's only 1 other
3558          * active crtc. */
3559         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3560                 if (!crtc_it->active || crtc_it == crtc)
3561                         continue;
3562
3563                 if (other_active_crtc)
3564                         return;
3565
3566                 other_active_crtc = crtc_it;
3567         }
3568         if (!other_active_crtc)
3569                 return;
3570
3571         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3572         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3573 }
3574
3575 static void haswell_crtc_enable(struct drm_crtc *crtc)
3576 {
3577         struct drm_device *dev = crtc->dev;
3578         struct drm_i915_private *dev_priv = dev->dev_private;
3579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3580         struct intel_encoder *encoder;
3581         int pipe = intel_crtc->pipe;
3582
3583         WARN_ON(!crtc->enabled);
3584
3585         if (intel_crtc->active)
3586                 return;
3587
3588         intel_crtc->active = true;
3589
3590         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3591         if (intel_crtc->config.has_pch_encoder)
3592                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3593
3594         if (intel_crtc->config.has_pch_encoder)
3595                 dev_priv->display.fdi_link_train(crtc);
3596
3597         for_each_encoder_on_crtc(dev, crtc, encoder)
3598                 if (encoder->pre_enable)
3599                         encoder->pre_enable(encoder);
3600
3601         intel_ddi_enable_pipe_clock(intel_crtc);
3602
3603         ironlake_pfit_enable(intel_crtc);
3604
3605         /*
3606          * On ILK+ LUT must be loaded before the pipe is running but with
3607          * clocks enabled
3608          */
3609         intel_crtc_load_lut(crtc);
3610
3611         intel_ddi_set_pipe_settings(crtc);
3612         intel_ddi_enable_transcoder_func(crtc);
3613
3614         intel_update_watermarks(crtc);
3615         intel_enable_pipe(dev_priv, pipe,
3616                           intel_crtc->config.has_pch_encoder, false);
3617
3618         if (intel_crtc->config.has_pch_encoder)
3619                 lpt_pch_enable(crtc);
3620
3621         for_each_encoder_on_crtc(dev, crtc, encoder) {
3622                 encoder->enable(encoder);
3623                 intel_opregion_notify_encoder(encoder, true);
3624         }
3625
3626         /* If we change the relative order between pipe/planes enabling, we need
3627          * to change the workaround. */
3628         haswell_mode_set_planes_workaround(intel_crtc);
3629         haswell_crtc_enable_planes(crtc);
3630
3631         /*
3632          * There seems to be a race in PCH platform hw (at least on some
3633          * outputs) where an enabled pipe still completes any pageflip right
3634          * away (as if the pipe is off) instead of waiting for vblank. As soon
3635          * as the first vblank happend, everything works as expected. Hence just
3636          * wait for one vblank before returning to avoid strange things
3637          * happening.
3638          */
3639         intel_wait_for_vblank(dev, intel_crtc->pipe);
3640 }
3641
3642 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3643 {
3644         struct drm_device *dev = crtc->base.dev;
3645         struct drm_i915_private *dev_priv = dev->dev_private;
3646         int pipe = crtc->pipe;
3647
3648         /* To avoid upsetting the power well on haswell only disable the pfit if
3649          * it's in use. The hw state code will make sure we get this right. */
3650         if (crtc->config.pch_pfit.enabled) {
3651                 I915_WRITE(PF_CTL(pipe), 0);
3652                 I915_WRITE(PF_WIN_POS(pipe), 0);
3653                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3654         }
3655 }
3656
3657 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3658 {
3659         struct drm_device *dev = crtc->dev;
3660         struct drm_i915_private *dev_priv = dev->dev_private;
3661         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3662         struct intel_encoder *encoder;
3663         int pipe = intel_crtc->pipe;
3664         int plane = intel_crtc->plane;
3665         u32 reg, temp;
3666
3667
3668         if (!intel_crtc->active)
3669                 return;
3670
3671         for_each_encoder_on_crtc(dev, crtc, encoder)
3672                 encoder->disable(encoder);
3673
3674         intel_crtc_wait_for_pending_flips(crtc);
3675         drm_vblank_off(dev, pipe);
3676
3677         if (dev_priv->fbc.plane == plane)
3678                 intel_disable_fbc(dev);
3679
3680         intel_crtc_update_cursor(crtc, false);
3681         intel_disable_planes(crtc);
3682         intel_disable_primary_plane(dev_priv, plane, pipe);
3683
3684         if (intel_crtc->config.has_pch_encoder)
3685                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3686
3687         intel_disable_pipe(dev_priv, pipe);
3688
3689         ironlake_pfit_disable(intel_crtc);
3690
3691         for_each_encoder_on_crtc(dev, crtc, encoder)
3692                 if (encoder->post_disable)
3693                         encoder->post_disable(encoder);
3694
3695         if (intel_crtc->config.has_pch_encoder) {
3696                 ironlake_fdi_disable(crtc);
3697
3698                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3699                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3700
3701                 if (HAS_PCH_CPT(dev)) {
3702                         /* disable TRANS_DP_CTL */
3703                         reg = TRANS_DP_CTL(pipe);
3704                         temp = I915_READ(reg);
3705                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3706                                   TRANS_DP_PORT_SEL_MASK);
3707                         temp |= TRANS_DP_PORT_SEL_NONE;
3708                         I915_WRITE(reg, temp);
3709
3710                         /* disable DPLL_SEL */
3711                         temp = I915_READ(PCH_DPLL_SEL);
3712                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3713                         I915_WRITE(PCH_DPLL_SEL, temp);
3714                 }
3715
3716                 /* disable PCH DPLL */
3717                 intel_disable_shared_dpll(intel_crtc);
3718
3719                 ironlake_fdi_pll_disable(intel_crtc);
3720         }
3721
3722         intel_crtc->active = false;
3723         intel_update_watermarks(crtc);
3724
3725         mutex_lock(&dev->struct_mutex);
3726         intel_update_fbc(dev);
3727         mutex_unlock(&dev->struct_mutex);
3728 }
3729
3730 static void haswell_crtc_disable(struct drm_crtc *crtc)
3731 {
3732         struct drm_device *dev = crtc->dev;
3733         struct drm_i915_private *dev_priv = dev->dev_private;
3734         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3735         struct intel_encoder *encoder;
3736         int pipe = intel_crtc->pipe;
3737         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3738
3739         if (!intel_crtc->active)
3740                 return;
3741
3742         haswell_crtc_disable_planes(crtc);
3743
3744         for_each_encoder_on_crtc(dev, crtc, encoder) {
3745                 intel_opregion_notify_encoder(encoder, false);
3746                 encoder->disable(encoder);
3747         }
3748
3749         if (intel_crtc->config.has_pch_encoder)
3750                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3751         intel_disable_pipe(dev_priv, pipe);
3752
3753         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3754
3755         ironlake_pfit_disable(intel_crtc);
3756
3757         intel_ddi_disable_pipe_clock(intel_crtc);
3758
3759         for_each_encoder_on_crtc(dev, crtc, encoder)
3760                 if (encoder->post_disable)
3761                         encoder->post_disable(encoder);
3762
3763         if (intel_crtc->config.has_pch_encoder) {
3764                 lpt_disable_pch_transcoder(dev_priv);
3765                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3766                 intel_ddi_fdi_disable(crtc);
3767         }
3768
3769         intel_crtc->active = false;
3770         intel_update_watermarks(crtc);
3771
3772         mutex_lock(&dev->struct_mutex);
3773         intel_update_fbc(dev);
3774         mutex_unlock(&dev->struct_mutex);
3775 }
3776
3777 static void ironlake_crtc_off(struct drm_crtc *crtc)
3778 {
3779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3780         intel_put_shared_dpll(intel_crtc);
3781 }
3782
3783 static void haswell_crtc_off(struct drm_crtc *crtc)
3784 {
3785         intel_ddi_put_crtc_pll(crtc);
3786 }
3787
3788 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3789 {
3790         if (!enable && intel_crtc->overlay) {
3791                 struct drm_device *dev = intel_crtc->base.dev;
3792                 struct drm_i915_private *dev_priv = dev->dev_private;
3793
3794                 mutex_lock(&dev->struct_mutex);
3795                 dev_priv->mm.interruptible = false;
3796                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3797                 dev_priv->mm.interruptible = true;
3798                 mutex_unlock(&dev->struct_mutex);
3799         }
3800
3801         /* Let userspace switch the overlay on again. In most cases userspace
3802          * has to recompute where to put it anyway.
3803          */
3804 }
3805
3806 /**
3807  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3808  * cursor plane briefly if not already running after enabling the display
3809  * plane.
3810  * This workaround avoids occasional blank screens when self refresh is
3811  * enabled.
3812  */
3813 static void
3814 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3815 {
3816         u32 cntl = I915_READ(CURCNTR(pipe));
3817
3818         if ((cntl & CURSOR_MODE) == 0) {
3819                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3820
3821                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3822                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3823                 intel_wait_for_vblank(dev_priv->dev, pipe);
3824                 I915_WRITE(CURCNTR(pipe), cntl);
3825                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3826                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3827         }
3828 }
3829
3830 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3831 {
3832         struct drm_device *dev = crtc->base.dev;
3833         struct drm_i915_private *dev_priv = dev->dev_private;
3834         struct intel_crtc_config *pipe_config = &crtc->config;
3835
3836         if (!crtc->config.gmch_pfit.control)
3837                 return;
3838
3839         /*
3840          * The panel fitter should only be adjusted whilst the pipe is disabled,
3841          * according to register description and PRM.
3842          */
3843         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3844         assert_pipe_disabled(dev_priv, crtc->pipe);
3845
3846         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3847         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3848
3849         /* Border color in case we don't scale up to the full screen. Black by
3850          * default, change to something else for debugging. */
3851         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3852 }
3853
3854 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3855 {
3856         struct drm_device *dev = crtc->dev;
3857         struct drm_i915_private *dev_priv = dev->dev_private;
3858         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3859         struct intel_encoder *encoder;
3860         int pipe = intel_crtc->pipe;
3861         int plane = intel_crtc->plane;
3862         bool is_dsi;
3863
3864         WARN_ON(!crtc->enabled);
3865
3866         if (intel_crtc->active)
3867                 return;
3868
3869         intel_crtc->active = true;
3870
3871         for_each_encoder_on_crtc(dev, crtc, encoder)
3872                 if (encoder->pre_pll_enable)
3873                         encoder->pre_pll_enable(encoder);
3874
3875         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3876
3877         if (!is_dsi)
3878                 vlv_enable_pll(intel_crtc);
3879
3880         for_each_encoder_on_crtc(dev, crtc, encoder)
3881                 if (encoder->pre_enable)
3882                         encoder->pre_enable(encoder);
3883
3884         i9xx_pfit_enable(intel_crtc);
3885
3886         intel_crtc_load_lut(crtc);
3887
3888         intel_update_watermarks(crtc);
3889         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3890         intel_enable_primary_plane(dev_priv, plane, pipe);
3891         intel_enable_planes(crtc);
3892         intel_crtc_update_cursor(crtc, true);
3893
3894         intel_update_fbc(dev);
3895
3896         for_each_encoder_on_crtc(dev, crtc, encoder)
3897                 encoder->enable(encoder);
3898 }
3899
3900 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3901 {
3902         struct drm_device *dev = crtc->dev;
3903         struct drm_i915_private *dev_priv = dev->dev_private;
3904         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3905         struct intel_encoder *encoder;
3906         int pipe = intel_crtc->pipe;
3907         int plane = intel_crtc->plane;
3908
3909         WARN_ON(!crtc->enabled);
3910
3911         if (intel_crtc->active)
3912                 return;
3913
3914         intel_crtc->active = true;
3915
3916         for_each_encoder_on_crtc(dev, crtc, encoder)
3917                 if (encoder->pre_enable)
3918                         encoder->pre_enable(encoder);
3919
3920         i9xx_enable_pll(intel_crtc);
3921
3922         i9xx_pfit_enable(intel_crtc);
3923
3924         intel_crtc_load_lut(crtc);
3925
3926         intel_update_watermarks(crtc);
3927         intel_enable_pipe(dev_priv, pipe, false, false);
3928         intel_enable_primary_plane(dev_priv, plane, pipe);
3929         intel_enable_planes(crtc);
3930         /* The fixup needs to happen before cursor is enabled */
3931         if (IS_G4X(dev))
3932                 g4x_fixup_plane(dev_priv, pipe);
3933         intel_crtc_update_cursor(crtc, true);
3934
3935         /* Give the overlay scaler a chance to enable if it's on this pipe */
3936         intel_crtc_dpms_overlay(intel_crtc, true);
3937
3938         intel_update_fbc(dev);
3939
3940         for_each_encoder_on_crtc(dev, crtc, encoder)
3941                 encoder->enable(encoder);
3942 }
3943
3944 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3945 {
3946         struct drm_device *dev = crtc->base.dev;
3947         struct drm_i915_private *dev_priv = dev->dev_private;
3948
3949         if (!crtc->config.gmch_pfit.control)
3950                 return;
3951
3952         assert_pipe_disabled(dev_priv, crtc->pipe);
3953
3954         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3955                          I915_READ(PFIT_CONTROL));
3956         I915_WRITE(PFIT_CONTROL, 0);
3957 }
3958
3959 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3960 {
3961         struct drm_device *dev = crtc->dev;
3962         struct drm_i915_private *dev_priv = dev->dev_private;
3963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3964         struct intel_encoder *encoder;
3965         int pipe = intel_crtc->pipe;
3966         int plane = intel_crtc->plane;
3967
3968         if (!intel_crtc->active)
3969                 return;
3970
3971         for_each_encoder_on_crtc(dev, crtc, encoder)
3972                 encoder->disable(encoder);
3973
3974         /* Give the overlay scaler a chance to disable if it's on this pipe */
3975         intel_crtc_wait_for_pending_flips(crtc);
3976         drm_vblank_off(dev, pipe);
3977
3978         if (dev_priv->fbc.plane == plane)
3979                 intel_disable_fbc(dev);
3980
3981         intel_crtc_dpms_overlay(intel_crtc, false);
3982         intel_crtc_update_cursor(crtc, false);
3983         intel_disable_planes(crtc);
3984         intel_disable_primary_plane(dev_priv, plane, pipe);
3985
3986         intel_disable_pipe(dev_priv, pipe);
3987
3988         i9xx_pfit_disable(intel_crtc);
3989
3990         for_each_encoder_on_crtc(dev, crtc, encoder)
3991                 if (encoder->post_disable)
3992                         encoder->post_disable(encoder);
3993
3994         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3995                 vlv_disable_pll(dev_priv, pipe);
3996         else if (!IS_VALLEYVIEW(dev))
3997                 i9xx_disable_pll(dev_priv, pipe);
3998
3999         intel_crtc->active = false;
4000         intel_update_watermarks(crtc);
4001
4002         intel_update_fbc(dev);
4003 }
4004
4005 static void i9xx_crtc_off(struct drm_crtc *crtc)
4006 {
4007 }
4008
4009 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4010                                     bool enabled)
4011 {
4012         struct drm_device *dev = crtc->dev;
4013         struct drm_i915_master_private *master_priv;
4014         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4015         int pipe = intel_crtc->pipe;
4016
4017         if (!dev->primary->master)
4018                 return;
4019
4020         master_priv = dev->primary->master->driver_priv;
4021         if (!master_priv->sarea_priv)
4022                 return;
4023
4024         switch (pipe) {
4025         case 0:
4026                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4027                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4028                 break;
4029         case 1:
4030                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4031                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4032                 break;
4033         default:
4034                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4035                 break;
4036         }
4037 }
4038
4039 /**
4040  * Sets the power management mode of the pipe and plane.
4041  */
4042 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4043 {
4044         struct drm_device *dev = crtc->dev;
4045         struct drm_i915_private *dev_priv = dev->dev_private;
4046         struct intel_encoder *intel_encoder;
4047         bool enable = false;
4048
4049         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4050                 enable |= intel_encoder->connectors_active;
4051
4052         if (enable)
4053                 dev_priv->display.crtc_enable(crtc);
4054         else
4055                 dev_priv->display.crtc_disable(crtc);
4056
4057         intel_crtc_update_sarea(crtc, enable);
4058 }
4059
4060 static void intel_crtc_disable(struct drm_crtc *crtc)
4061 {
4062         struct drm_device *dev = crtc->dev;
4063         struct drm_connector *connector;
4064         struct drm_i915_private *dev_priv = dev->dev_private;
4065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4066
4067         /* crtc should still be enabled when we disable it. */
4068         WARN_ON(!crtc->enabled);
4069
4070         dev_priv->display.crtc_disable(crtc);
4071         intel_crtc->eld_vld = false;
4072         intel_crtc_update_sarea(crtc, false);
4073         dev_priv->display.off(crtc);
4074
4075         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4076         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4077         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4078
4079         if (crtc->fb) {
4080                 mutex_lock(&dev->struct_mutex);
4081                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4082                 mutex_unlock(&dev->struct_mutex);
4083                 crtc->fb = NULL;
4084         }
4085
4086         /* Update computed state. */
4087         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4088                 if (!connector->encoder || !connector->encoder->crtc)
4089                         continue;
4090
4091                 if (connector->encoder->crtc != crtc)
4092                         continue;
4093
4094                 connector->dpms = DRM_MODE_DPMS_OFF;
4095                 to_intel_encoder(connector->encoder)->connectors_active = false;
4096         }
4097 }
4098
4099 void intel_encoder_destroy(struct drm_encoder *encoder)
4100 {
4101         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4102
4103         drm_encoder_cleanup(encoder);
4104         kfree(intel_encoder);
4105 }
4106
4107 /* Simple dpms helper for encoders with just one connector, no cloning and only
4108  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4109  * state of the entire output pipe. */
4110 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4111 {
4112         if (mode == DRM_MODE_DPMS_ON) {
4113                 encoder->connectors_active = true;
4114
4115                 intel_crtc_update_dpms(encoder->base.crtc);
4116         } else {
4117                 encoder->connectors_active = false;
4118
4119                 intel_crtc_update_dpms(encoder->base.crtc);
4120         }
4121 }
4122
4123 /* Cross check the actual hw state with our own modeset state tracking (and it's
4124  * internal consistency). */
4125 static void intel_connector_check_state(struct intel_connector *connector)
4126 {
4127         if (connector->get_hw_state(connector)) {
4128                 struct intel_encoder *encoder = connector->encoder;
4129                 struct drm_crtc *crtc;
4130                 bool encoder_enabled;
4131                 enum pipe pipe;
4132
4133                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4134                               connector->base.base.id,
4135                               drm_get_connector_name(&connector->base));
4136
4137                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4138                      "wrong connector dpms state\n");
4139                 WARN(connector->base.encoder != &encoder->base,
4140                      "active connector not linked to encoder\n");
4141                 WARN(!encoder->connectors_active,
4142                      "encoder->connectors_active not set\n");
4143
4144                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4145                 WARN(!encoder_enabled, "encoder not enabled\n");
4146                 if (WARN_ON(!encoder->base.crtc))
4147                         return;
4148
4149                 crtc = encoder->base.crtc;
4150
4151                 WARN(!crtc->enabled, "crtc not enabled\n");
4152                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4153                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4154                      "encoder active on the wrong pipe\n");
4155         }
4156 }
4157
4158 /* Even simpler default implementation, if there's really no special case to
4159  * consider. */
4160 void intel_connector_dpms(struct drm_connector *connector, int mode)
4161 {
4162         struct intel_encoder *encoder = intel_attached_encoder(connector);
4163
4164         /* All the simple cases only support two dpms states. */
4165         if (mode != DRM_MODE_DPMS_ON)
4166                 mode = DRM_MODE_DPMS_OFF;
4167
4168         if (mode == connector->dpms)
4169                 return;
4170
4171         connector->dpms = mode;
4172
4173         /* Only need to change hw state when actually enabled */
4174         if (encoder->base.crtc)
4175                 intel_encoder_dpms(encoder, mode);
4176         else
4177                 WARN_ON(encoder->connectors_active != false);
4178
4179         intel_modeset_check_state(connector->dev);
4180 }
4181
4182 /* Simple connector->get_hw_state implementation for encoders that support only
4183  * one connector and no cloning and hence the encoder state determines the state
4184  * of the connector. */
4185 bool intel_connector_get_hw_state(struct intel_connector *connector)
4186 {
4187         enum pipe pipe = 0;
4188         struct intel_encoder *encoder = connector->encoder;
4189
4190         return encoder->get_hw_state(encoder, &pipe);
4191 }
4192
4193 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4194                                      struct intel_crtc_config *pipe_config)
4195 {
4196         struct drm_i915_private *dev_priv = dev->dev_private;
4197         struct intel_crtc *pipe_B_crtc =
4198                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4199
4200         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4201                       pipe_name(pipe), pipe_config->fdi_lanes);
4202         if (pipe_config->fdi_lanes > 4) {
4203                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4204                               pipe_name(pipe), pipe_config->fdi_lanes);
4205                 return false;
4206         }
4207
4208         if (IS_HASWELL(dev)) {
4209                 if (pipe_config->fdi_lanes > 2) {
4210                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4211                                       pipe_config->fdi_lanes);
4212                         return false;
4213                 } else {
4214                         return true;
4215                 }
4216         }
4217
4218         if (INTEL_INFO(dev)->num_pipes == 2)
4219                 return true;
4220
4221         /* Ivybridge 3 pipe is really complicated */
4222         switch (pipe) {
4223         case PIPE_A:
4224                 return true;
4225         case PIPE_B:
4226                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4227                     pipe_config->fdi_lanes > 2) {
4228                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4229                                       pipe_name(pipe), pipe_config->fdi_lanes);
4230                         return false;
4231                 }
4232                 return true;
4233         case PIPE_C:
4234                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4235                     pipe_B_crtc->config.fdi_lanes <= 2) {
4236                         if (pipe_config->fdi_lanes > 2) {
4237                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4238                                               pipe_name(pipe), pipe_config->fdi_lanes);
4239                                 return false;
4240                         }
4241                 } else {
4242                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4243                         return false;
4244                 }
4245                 return true;
4246         default:
4247                 BUG();
4248         }
4249 }
4250
4251 #define RETRY 1
4252 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4253                                        struct intel_crtc_config *pipe_config)
4254 {
4255         struct drm_device *dev = intel_crtc->base.dev;
4256         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4257         int lane, link_bw, fdi_dotclock;
4258         bool setup_ok, needs_recompute = false;
4259
4260 retry:
4261         /* FDI is a binary signal running at ~2.7GHz, encoding
4262          * each output octet as 10 bits. The actual frequency
4263          * is stored as a divider into a 100MHz clock, and the
4264          * mode pixel clock is stored in units of 1KHz.
4265          * Hence the bw of each lane in terms of the mode signal
4266          * is:
4267          */
4268         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4269
4270         fdi_dotclock = adjusted_mode->crtc_clock;
4271
4272         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4273                                            pipe_config->pipe_bpp);
4274
4275         pipe_config->fdi_lanes = lane;
4276
4277         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4278                                link_bw, &pipe_config->fdi_m_n);
4279
4280         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4281                                             intel_crtc->pipe, pipe_config);
4282         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4283                 pipe_config->pipe_bpp -= 2*3;
4284                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4285                               pipe_config->pipe_bpp);
4286                 needs_recompute = true;
4287                 pipe_config->bw_constrained = true;
4288
4289                 goto retry;
4290         }
4291
4292         if (needs_recompute)
4293                 return RETRY;
4294
4295         return setup_ok ? 0 : -EINVAL;
4296 }
4297
4298 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4299                                    struct intel_crtc_config *pipe_config)
4300 {
4301         pipe_config->ips_enabled = i915_enable_ips &&
4302                                    hsw_crtc_supports_ips(crtc) &&
4303                                    pipe_config->pipe_bpp <= 24;
4304 }
4305
4306 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4307                                      struct intel_crtc_config *pipe_config)
4308 {
4309         struct drm_device *dev = crtc->base.dev;
4310         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4311
4312         /* FIXME should check pixel clock limits on all platforms */
4313         if (INTEL_INFO(dev)->gen < 4) {
4314                 struct drm_i915_private *dev_priv = dev->dev_private;
4315                 int clock_limit =
4316                         dev_priv->display.get_display_clock_speed(dev);
4317
4318                 /*
4319                  * Enable pixel doubling when the dot clock
4320                  * is > 90% of the (display) core speed.
4321                  *
4322                  * GDG double wide on either pipe,
4323                  * otherwise pipe A only.
4324                  */
4325                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4326                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4327                         clock_limit *= 2;
4328                         pipe_config->double_wide = true;
4329                 }
4330
4331                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4332                         return -EINVAL;
4333         }
4334
4335         /*
4336          * Pipe horizontal size must be even in:
4337          * - DVO ganged mode
4338          * - LVDS dual channel mode
4339          * - Double wide pipe
4340          */
4341         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4342              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4343                 pipe_config->pipe_src_w &= ~1;
4344
4345         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4346          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4347          */
4348         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4349                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4350                 return -EINVAL;
4351
4352         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4353                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4354         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4355                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4356                  * for lvds. */
4357                 pipe_config->pipe_bpp = 8*3;
4358         }
4359
4360         if (HAS_IPS(dev))
4361                 hsw_compute_ips_config(crtc, pipe_config);
4362
4363         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4364          * clock survives for now. */
4365         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4366                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4367
4368         if (pipe_config->has_pch_encoder)
4369                 return ironlake_fdi_compute_config(crtc, pipe_config);
4370
4371         return 0;
4372 }
4373
4374 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4375 {
4376         return 400000; /* FIXME */
4377 }
4378
4379 static int i945_get_display_clock_speed(struct drm_device *dev)
4380 {
4381         return 400000;
4382 }
4383
4384 static int i915_get_display_clock_speed(struct drm_device *dev)
4385 {
4386         return 333000;
4387 }
4388
4389 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4390 {
4391         return 200000;
4392 }
4393
4394 static int pnv_get_display_clock_speed(struct drm_device *dev)
4395 {
4396         u16 gcfgc = 0;
4397
4398         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4399
4400         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4401         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4402                 return 267000;
4403         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4404                 return 333000;
4405         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4406                 return 444000;
4407         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4408                 return 200000;
4409         default:
4410                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4411         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4412                 return 133000;
4413         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4414                 return 167000;
4415         }
4416 }
4417
4418 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4419 {
4420         u16 gcfgc = 0;
4421
4422         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4423
4424         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4425                 return 133000;
4426         else {
4427                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4428                 case GC_DISPLAY_CLOCK_333_MHZ:
4429                         return 333000;
4430                 default:
4431                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4432                         return 190000;
4433                 }
4434         }
4435 }
4436
4437 static int i865_get_display_clock_speed(struct drm_device *dev)
4438 {
4439         return 266000;
4440 }
4441
4442 static int i855_get_display_clock_speed(struct drm_device *dev)
4443 {
4444         u16 hpllcc = 0;
4445         /* Assume that the hardware is in the high speed state.  This
4446          * should be the default.
4447          */
4448         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4449         case GC_CLOCK_133_200:
4450         case GC_CLOCK_100_200:
4451                 return 200000;
4452         case GC_CLOCK_166_250:
4453                 return 250000;
4454         case GC_CLOCK_100_133:
4455                 return 133000;
4456         }
4457
4458         /* Shouldn't happen */
4459         return 0;
4460 }
4461
4462 static int i830_get_display_clock_speed(struct drm_device *dev)
4463 {
4464         return 133000;
4465 }
4466
4467 static void
4468 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4469 {
4470         while (*num > DATA_LINK_M_N_MASK ||
4471                *den > DATA_LINK_M_N_MASK) {
4472                 *num >>= 1;
4473                 *den >>= 1;
4474         }
4475 }
4476
4477 static void compute_m_n(unsigned int m, unsigned int n,
4478                         uint32_t *ret_m, uint32_t *ret_n)
4479 {
4480         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4481         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4482         intel_reduce_m_n_ratio(ret_m, ret_n);
4483 }
4484
4485 void
4486 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4487                        int pixel_clock, int link_clock,
4488                        struct intel_link_m_n *m_n)
4489 {
4490         m_n->tu = 64;
4491
4492         compute_m_n(bits_per_pixel * pixel_clock,
4493                     link_clock * nlanes * 8,
4494                     &m_n->gmch_m, &m_n->gmch_n);
4495
4496         compute_m_n(pixel_clock, link_clock,
4497                     &m_n->link_m, &m_n->link_n);
4498 }
4499
4500 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4501 {
4502         if (i915_panel_use_ssc >= 0)
4503                 return i915_panel_use_ssc != 0;
4504         return dev_priv->vbt.lvds_use_ssc
4505                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4506 }
4507
4508 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4509 {
4510         struct drm_device *dev = crtc->dev;
4511         struct drm_i915_private *dev_priv = dev->dev_private;
4512         int refclk;
4513
4514         if (IS_VALLEYVIEW(dev)) {
4515                 refclk = 100000;
4516         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4517             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4518                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4519                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4520                               refclk / 1000);
4521         } else if (!IS_GEN2(dev)) {
4522                 refclk = 96000;
4523         } else {
4524                 refclk = 48000;
4525         }
4526
4527         return refclk;
4528 }
4529
4530 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4531 {
4532         return (1 << dpll->n) << 16 | dpll->m2;
4533 }
4534
4535 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4536 {
4537         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4538 }
4539
4540 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4541                                      intel_clock_t *reduced_clock)
4542 {
4543         struct drm_device *dev = crtc->base.dev;
4544         struct drm_i915_private *dev_priv = dev->dev_private;
4545         int pipe = crtc->pipe;
4546         u32 fp, fp2 = 0;
4547
4548         if (IS_PINEVIEW(dev)) {
4549                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4550                 if (reduced_clock)
4551                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4552         } else {
4553                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4554                 if (reduced_clock)
4555                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4556         }
4557
4558         I915_WRITE(FP0(pipe), fp);
4559         crtc->config.dpll_hw_state.fp0 = fp;
4560
4561         crtc->lowfreq_avail = false;
4562         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4563             reduced_clock && i915_powersave) {
4564                 I915_WRITE(FP1(pipe), fp2);
4565                 crtc->config.dpll_hw_state.fp1 = fp2;
4566                 crtc->lowfreq_avail = true;
4567         } else {
4568                 I915_WRITE(FP1(pipe), fp);
4569                 crtc->config.dpll_hw_state.fp1 = fp;
4570         }
4571 }
4572
4573 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4574                 pipe)
4575 {
4576         u32 reg_val;
4577
4578         /*
4579          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4580          * and set it to a reasonable value instead.
4581          */
4582         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4583         reg_val &= 0xffffff00;
4584         reg_val |= 0x00000030;
4585         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4586
4587         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4588         reg_val &= 0x8cffffff;
4589         reg_val = 0x8c000000;
4590         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4591
4592         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4593         reg_val &= 0xffffff00;
4594         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4595
4596         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4597         reg_val &= 0x00ffffff;
4598         reg_val |= 0xb0000000;
4599         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4600 }
4601
4602 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4603                                          struct intel_link_m_n *m_n)
4604 {
4605         struct drm_device *dev = crtc->base.dev;
4606         struct drm_i915_private *dev_priv = dev->dev_private;
4607         int pipe = crtc->pipe;
4608
4609         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4610         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4611         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4612         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4613 }
4614
4615 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4616                                          struct intel_link_m_n *m_n)
4617 {
4618         struct drm_device *dev = crtc->base.dev;
4619         struct drm_i915_private *dev_priv = dev->dev_private;
4620         int pipe = crtc->pipe;
4621         enum transcoder transcoder = crtc->config.cpu_transcoder;
4622
4623         if (INTEL_INFO(dev)->gen >= 5) {
4624                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4625                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4626                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4627                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4628         } else {
4629                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4630                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4631                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4632                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4633         }
4634 }
4635
4636 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4637 {
4638         if (crtc->config.has_pch_encoder)
4639                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4640         else
4641                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4642 }
4643
4644 static void vlv_update_pll(struct intel_crtc *crtc)
4645 {
4646         struct drm_device *dev = crtc->base.dev;
4647         struct drm_i915_private *dev_priv = dev->dev_private;
4648         int pipe = crtc->pipe;
4649         u32 dpll, mdiv;
4650         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4651         u32 coreclk, reg_val, dpll_md;
4652
4653         mutex_lock(&dev_priv->dpio_lock);
4654
4655         bestn = crtc->config.dpll.n;
4656         bestm1 = crtc->config.dpll.m1;
4657         bestm2 = crtc->config.dpll.m2;
4658         bestp1 = crtc->config.dpll.p1;
4659         bestp2 = crtc->config.dpll.p2;
4660
4661         /* See eDP HDMI DPIO driver vbios notes doc */
4662
4663         /* PLL B needs special handling */
4664         if (pipe)
4665                 vlv_pllb_recal_opamp(dev_priv, pipe);
4666
4667         /* Set up Tx target for periodic Rcomp update */
4668         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4669
4670         /* Disable target IRef on PLL */
4671         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4672         reg_val &= 0x00ffffff;
4673         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4674
4675         /* Disable fast lock */
4676         vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4677
4678         /* Set idtafcrecal before PLL is enabled */
4679         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4680         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4681         mdiv |= ((bestn << DPIO_N_SHIFT));
4682         mdiv |= (1 << DPIO_K_SHIFT);
4683
4684         /*
4685          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4686          * but we don't support that).
4687          * Note: don't use the DAC post divider as it seems unstable.
4688          */
4689         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4690         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4691
4692         mdiv |= DPIO_ENABLE_CALIBRATION;
4693         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4694
4695         /* Set HBR and RBR LPF coefficients */
4696         if (crtc->config.port_clock == 162000 ||
4697             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4698             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4699                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4700                                  0x009f0003);
4701         else
4702                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4703                                  0x00d0000f);
4704
4705         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4706             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4707                 /* Use SSC source */
4708                 if (!pipe)
4709                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4710                                          0x0df40000);
4711                 else
4712                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4713                                          0x0df70000);
4714         } else { /* HDMI or VGA */
4715                 /* Use bend source */
4716                 if (!pipe)
4717                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4718                                          0x0df70000);
4719                 else
4720                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4721                                          0x0df40000);
4722         }
4723
4724         coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4725         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4726         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4727             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4728                 coreclk |= 0x01000000;
4729         vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4730
4731         vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4732
4733         /* Enable DPIO clock input */
4734         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4735                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4736         /* We should never disable this, set it here for state tracking */
4737         if (pipe == PIPE_B)
4738                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4739         dpll |= DPLL_VCO_ENABLE;
4740         crtc->config.dpll_hw_state.dpll = dpll;
4741
4742         dpll_md = (crtc->config.pixel_multiplier - 1)
4743                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4744         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4745
4746         if (crtc->config.has_dp_encoder)
4747                 intel_dp_set_m_n(crtc);
4748
4749         mutex_unlock(&dev_priv->dpio_lock);
4750 }
4751
4752 static void i9xx_update_pll(struct intel_crtc *crtc,
4753                             intel_clock_t *reduced_clock,
4754                             int num_connectors)
4755 {
4756         struct drm_device *dev = crtc->base.dev;
4757         struct drm_i915_private *dev_priv = dev->dev_private;
4758         u32 dpll;
4759         bool is_sdvo;
4760         struct dpll *clock = &crtc->config.dpll;
4761
4762         i9xx_update_pll_dividers(crtc, reduced_clock);
4763
4764         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4765                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4766
4767         dpll = DPLL_VGA_MODE_DIS;
4768
4769         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4770                 dpll |= DPLLB_MODE_LVDS;
4771         else
4772                 dpll |= DPLLB_MODE_DAC_SERIAL;
4773
4774         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4775                 dpll |= (crtc->config.pixel_multiplier - 1)
4776                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4777         }
4778
4779         if (is_sdvo)
4780                 dpll |= DPLL_SDVO_HIGH_SPEED;
4781
4782         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4783                 dpll |= DPLL_SDVO_HIGH_SPEED;
4784
4785         /* compute bitmask from p1 value */
4786         if (IS_PINEVIEW(dev))
4787                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4788         else {
4789                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4790                 if (IS_G4X(dev) && reduced_clock)
4791                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4792         }
4793         switch (clock->p2) {
4794         case 5:
4795                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4796                 break;
4797         case 7:
4798                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4799                 break;
4800         case 10:
4801                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4802                 break;
4803         case 14:
4804                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4805                 break;
4806         }
4807         if (INTEL_INFO(dev)->gen >= 4)
4808                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4809
4810         if (crtc->config.sdvo_tv_clock)
4811                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4812         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4813                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4814                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4815         else
4816                 dpll |= PLL_REF_INPUT_DREFCLK;
4817
4818         dpll |= DPLL_VCO_ENABLE;
4819         crtc->config.dpll_hw_state.dpll = dpll;
4820
4821         if (INTEL_INFO(dev)->gen >= 4) {
4822                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4823                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4824                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4825         }
4826
4827         if (crtc->config.has_dp_encoder)
4828                 intel_dp_set_m_n(crtc);
4829 }
4830
4831 static void i8xx_update_pll(struct intel_crtc *crtc,
4832                             intel_clock_t *reduced_clock,
4833                             int num_connectors)
4834 {
4835         struct drm_device *dev = crtc->base.dev;
4836         struct drm_i915_private *dev_priv = dev->dev_private;
4837         u32 dpll;
4838         struct dpll *clock = &crtc->config.dpll;
4839
4840         i9xx_update_pll_dividers(crtc, reduced_clock);
4841
4842         dpll = DPLL_VGA_MODE_DIS;
4843
4844         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4845                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4846         } else {
4847                 if (clock->p1 == 2)
4848                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4849                 else
4850                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4851                 if (clock->p2 == 4)
4852                         dpll |= PLL_P2_DIVIDE_BY_4;
4853         }
4854
4855         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4856                 dpll |= DPLL_DVO_2X_MODE;
4857
4858         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4859                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4860                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4861         else
4862                 dpll |= PLL_REF_INPUT_DREFCLK;
4863
4864         dpll |= DPLL_VCO_ENABLE;
4865         crtc->config.dpll_hw_state.dpll = dpll;
4866 }
4867
4868 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4869 {
4870         struct drm_device *dev = intel_crtc->base.dev;
4871         struct drm_i915_private *dev_priv = dev->dev_private;
4872         enum pipe pipe = intel_crtc->pipe;
4873         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4874         struct drm_display_mode *adjusted_mode =
4875                 &intel_crtc->config.adjusted_mode;
4876         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4877
4878         /* We need to be careful not to changed the adjusted mode, for otherwise
4879          * the hw state checker will get angry at the mismatch. */
4880         crtc_vtotal = adjusted_mode->crtc_vtotal;
4881         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4882
4883         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4884                 /* the chip adds 2 halflines automatically */
4885                 crtc_vtotal -= 1;
4886                 crtc_vblank_end -= 1;
4887                 vsyncshift = adjusted_mode->crtc_hsync_start
4888                              - adjusted_mode->crtc_htotal / 2;
4889         } else {
4890                 vsyncshift = 0;
4891         }
4892
4893         if (INTEL_INFO(dev)->gen > 3)
4894                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4895
4896         I915_WRITE(HTOTAL(cpu_transcoder),
4897                    (adjusted_mode->crtc_hdisplay - 1) |
4898                    ((adjusted_mode->crtc_htotal - 1) << 16));
4899         I915_WRITE(HBLANK(cpu_transcoder),
4900                    (adjusted_mode->crtc_hblank_start - 1) |
4901                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4902         I915_WRITE(HSYNC(cpu_transcoder),
4903                    (adjusted_mode->crtc_hsync_start - 1) |
4904                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4905
4906         I915_WRITE(VTOTAL(cpu_transcoder),
4907                    (adjusted_mode->crtc_vdisplay - 1) |
4908                    ((crtc_vtotal - 1) << 16));
4909         I915_WRITE(VBLANK(cpu_transcoder),
4910                    (adjusted_mode->crtc_vblank_start - 1) |
4911                    ((crtc_vblank_end - 1) << 16));
4912         I915_WRITE(VSYNC(cpu_transcoder),
4913                    (adjusted_mode->crtc_vsync_start - 1) |
4914                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4915
4916         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4917          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4918          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4919          * bits. */
4920         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4921             (pipe == PIPE_B || pipe == PIPE_C))
4922                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4923
4924         /* pipesrc controls the size that is scaled from, which should
4925          * always be the user's requested size.
4926          */
4927         I915_WRITE(PIPESRC(pipe),
4928                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
4929                    (intel_crtc->config.pipe_src_h - 1));
4930 }
4931
4932 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4933                                    struct intel_crtc_config *pipe_config)
4934 {
4935         struct drm_device *dev = crtc->base.dev;
4936         struct drm_i915_private *dev_priv = dev->dev_private;
4937         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4938         uint32_t tmp;
4939
4940         tmp = I915_READ(HTOTAL(cpu_transcoder));
4941         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4942         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4943         tmp = I915_READ(HBLANK(cpu_transcoder));
4944         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4945         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4946         tmp = I915_READ(HSYNC(cpu_transcoder));
4947         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4948         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4949
4950         tmp = I915_READ(VTOTAL(cpu_transcoder));
4951         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4952         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4953         tmp = I915_READ(VBLANK(cpu_transcoder));
4954         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4955         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4956         tmp = I915_READ(VSYNC(cpu_transcoder));
4957         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4958         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4959
4960         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4961                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4962                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4963                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4964         }
4965
4966         tmp = I915_READ(PIPESRC(crtc->pipe));
4967         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4968         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4969
4970         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4971         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
4972 }
4973
4974 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4975                                              struct intel_crtc_config *pipe_config)
4976 {
4977         struct drm_crtc *crtc = &intel_crtc->base;
4978
4979         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4980         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4981         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4982         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4983
4984         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4985         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4986         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4987         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4988
4989         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4990
4991         crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
4992         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4993 }
4994
4995 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4996 {
4997         struct drm_device *dev = intel_crtc->base.dev;
4998         struct drm_i915_private *dev_priv = dev->dev_private;
4999         uint32_t pipeconf;
5000
5001         pipeconf = 0;
5002
5003         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5004             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5005                 pipeconf |= PIPECONF_ENABLE;
5006
5007         if (intel_crtc->config.double_wide)
5008                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5009
5010         /* only g4x and later have fancy bpc/dither controls */
5011         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5012                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5013                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5014                         pipeconf |= PIPECONF_DITHER_EN |
5015                                     PIPECONF_DITHER_TYPE_SP;
5016
5017                 switch (intel_crtc->config.pipe_bpp) {
5018                 case 18:
5019                         pipeconf |= PIPECONF_6BPC;
5020                         break;
5021                 case 24:
5022                         pipeconf |= PIPECONF_8BPC;
5023                         break;
5024                 case 30:
5025                         pipeconf |= PIPECONF_10BPC;
5026                         break;
5027                 default:
5028                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5029                         BUG();
5030                 }
5031         }
5032
5033         if (HAS_PIPE_CXSR(dev)) {
5034                 if (intel_crtc->lowfreq_avail) {
5035                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5036                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5037                 } else {
5038                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5039                 }
5040         }
5041
5042         if (!IS_GEN2(dev) &&
5043             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5044                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5045         else
5046                 pipeconf |= PIPECONF_PROGRESSIVE;
5047
5048         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5049                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5050
5051         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5052         POSTING_READ(PIPECONF(intel_crtc->pipe));
5053 }
5054
5055 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5056                               int x, int y,
5057                               struct drm_framebuffer *fb)
5058 {
5059         struct drm_device *dev = crtc->dev;
5060         struct drm_i915_private *dev_priv = dev->dev_private;
5061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5062         int pipe = intel_crtc->pipe;
5063         int plane = intel_crtc->plane;
5064         int refclk, num_connectors = 0;
5065         intel_clock_t clock, reduced_clock;
5066         u32 dspcntr;
5067         bool ok, has_reduced_clock = false;
5068         bool is_lvds = false, is_dsi = false;
5069         struct intel_encoder *encoder;
5070         const intel_limit_t *limit;
5071         int ret;
5072
5073         for_each_encoder_on_crtc(dev, crtc, encoder) {
5074                 switch (encoder->type) {
5075                 case INTEL_OUTPUT_LVDS:
5076                         is_lvds = true;
5077                         break;
5078                 case INTEL_OUTPUT_DSI:
5079                         is_dsi = true;
5080                         break;
5081                 }
5082
5083                 num_connectors++;
5084         }
5085
5086         if (is_dsi)
5087                 goto skip_dpll;
5088
5089         if (!intel_crtc->config.clock_set) {
5090                 refclk = i9xx_get_refclk(crtc, num_connectors);
5091
5092                 /*
5093                  * Returns a set of divisors for the desired target clock with
5094                  * the given refclk, or FALSE.  The returned values represent
5095                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5096                  * 2) / p1 / p2.
5097                  */
5098                 limit = intel_limit(crtc, refclk);
5099                 ok = dev_priv->display.find_dpll(limit, crtc,
5100                                                  intel_crtc->config.port_clock,
5101                                                  refclk, NULL, &clock);
5102                 if (!ok) {
5103                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5104                         return -EINVAL;
5105                 }
5106
5107                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5108                         /*
5109                          * Ensure we match the reduced clock's P to the target
5110                          * clock.  If the clocks don't match, we can't switch
5111                          * the display clock by using the FP0/FP1. In such case
5112                          * we will disable the LVDS downclock feature.
5113                          */
5114                         has_reduced_clock =
5115                                 dev_priv->display.find_dpll(limit, crtc,
5116                                                             dev_priv->lvds_downclock,
5117                                                             refclk, &clock,
5118                                                             &reduced_clock);
5119                 }
5120                 /* Compat-code for transition, will disappear. */
5121                 intel_crtc->config.dpll.n = clock.n;
5122                 intel_crtc->config.dpll.m1 = clock.m1;
5123                 intel_crtc->config.dpll.m2 = clock.m2;
5124                 intel_crtc->config.dpll.p1 = clock.p1;
5125                 intel_crtc->config.dpll.p2 = clock.p2;
5126         }
5127
5128         if (IS_GEN2(dev)) {
5129                 i8xx_update_pll(intel_crtc,
5130                                 has_reduced_clock ? &reduced_clock : NULL,
5131                                 num_connectors);
5132         } else if (IS_VALLEYVIEW(dev)) {
5133                 vlv_update_pll(intel_crtc);
5134         } else {
5135                 i9xx_update_pll(intel_crtc,
5136                                 has_reduced_clock ? &reduced_clock : NULL,
5137                                 num_connectors);
5138         }
5139
5140 skip_dpll:
5141         /* Set up the display plane register */
5142         dspcntr = DISPPLANE_GAMMA_ENABLE;
5143
5144         if (!IS_VALLEYVIEW(dev)) {
5145                 if (pipe == 0)
5146                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5147                 else
5148                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5149         }
5150
5151         intel_set_pipe_timings(intel_crtc);
5152
5153         /* pipesrc and dspsize control the size that is scaled from,
5154          * which should always be the user's requested size.
5155          */
5156         I915_WRITE(DSPSIZE(plane),
5157                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5158                    (intel_crtc->config.pipe_src_w - 1));
5159         I915_WRITE(DSPPOS(plane), 0);
5160
5161         i9xx_set_pipeconf(intel_crtc);
5162
5163         I915_WRITE(DSPCNTR(plane), dspcntr);
5164         POSTING_READ(DSPCNTR(plane));
5165
5166         ret = intel_pipe_set_base(crtc, x, y, fb);
5167
5168         return ret;
5169 }
5170
5171 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5172                                  struct intel_crtc_config *pipe_config)
5173 {
5174         struct drm_device *dev = crtc->base.dev;
5175         struct drm_i915_private *dev_priv = dev->dev_private;
5176         uint32_t tmp;
5177
5178         tmp = I915_READ(PFIT_CONTROL);
5179         if (!(tmp & PFIT_ENABLE))
5180                 return;
5181
5182         /* Check whether the pfit is attached to our pipe. */
5183         if (INTEL_INFO(dev)->gen < 4) {
5184                 if (crtc->pipe != PIPE_B)
5185                         return;
5186         } else {
5187                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5188                         return;
5189         }
5190
5191         pipe_config->gmch_pfit.control = tmp;
5192         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5193         if (INTEL_INFO(dev)->gen < 5)
5194                 pipe_config->gmch_pfit.lvds_border_bits =
5195                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5196 }
5197
5198 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5199                                struct intel_crtc_config *pipe_config)
5200 {
5201         struct drm_device *dev = crtc->base.dev;
5202         struct drm_i915_private *dev_priv = dev->dev_private;
5203         int pipe = pipe_config->cpu_transcoder;
5204         intel_clock_t clock;
5205         u32 mdiv;
5206         int refclk = 100000;
5207
5208         mutex_lock(&dev_priv->dpio_lock);
5209         mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5210         mutex_unlock(&dev_priv->dpio_lock);
5211
5212         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5213         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5214         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5215         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5216         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5217
5218         clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5219         clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
5220
5221         pipe_config->port_clock = clock.dot / 10;
5222 }
5223
5224 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5225                                  struct intel_crtc_config *pipe_config)
5226 {
5227         struct drm_device *dev = crtc->base.dev;
5228         struct drm_i915_private *dev_priv = dev->dev_private;
5229         uint32_t tmp;
5230
5231         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5232         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5233
5234         tmp = I915_READ(PIPECONF(crtc->pipe));
5235         if (!(tmp & PIPECONF_ENABLE))
5236                 return false;
5237
5238         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5239                 switch (tmp & PIPECONF_BPC_MASK) {
5240                 case PIPECONF_6BPC:
5241                         pipe_config->pipe_bpp = 18;
5242                         break;
5243                 case PIPECONF_8BPC:
5244                         pipe_config->pipe_bpp = 24;
5245                         break;
5246                 case PIPECONF_10BPC:
5247                         pipe_config->pipe_bpp = 30;
5248                         break;
5249                 default:
5250                         break;
5251                 }
5252         }
5253
5254         if (INTEL_INFO(dev)->gen < 4)
5255                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5256
5257         intel_get_pipe_timings(crtc, pipe_config);
5258
5259         i9xx_get_pfit_config(crtc, pipe_config);
5260
5261         if (INTEL_INFO(dev)->gen >= 4) {
5262                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5263                 pipe_config->pixel_multiplier =
5264                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5265                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5266                 pipe_config->dpll_hw_state.dpll_md = tmp;
5267         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5268                 tmp = I915_READ(DPLL(crtc->pipe));
5269                 pipe_config->pixel_multiplier =
5270                         ((tmp & SDVO_MULTIPLIER_MASK)
5271                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5272         } else {
5273                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5274                  * port and will be fixed up in the encoder->get_config
5275                  * function. */
5276                 pipe_config->pixel_multiplier = 1;
5277         }
5278         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5279         if (!IS_VALLEYVIEW(dev)) {
5280                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5281                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5282         } else {
5283                 /* Mask out read-only status bits. */
5284                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5285                                                      DPLL_PORTC_READY_MASK |
5286                                                      DPLL_PORTB_READY_MASK);
5287         }
5288
5289         if (IS_VALLEYVIEW(dev))
5290                 vlv_crtc_clock_get(crtc, pipe_config);
5291         else
5292                 i9xx_crtc_clock_get(crtc, pipe_config);
5293
5294         return true;
5295 }
5296
5297 static void ironlake_init_pch_refclk(struct drm_device *dev)
5298 {
5299         struct drm_i915_private *dev_priv = dev->dev_private;
5300         struct drm_mode_config *mode_config = &dev->mode_config;
5301         struct intel_encoder *encoder;
5302         u32 val, final;
5303         bool has_lvds = false;
5304         bool has_cpu_edp = false;
5305         bool has_panel = false;
5306         bool has_ck505 = false;
5307         bool can_ssc = false;
5308
5309         /* We need to take the global config into account */
5310         list_for_each_entry(encoder, &mode_config->encoder_list,
5311                             base.head) {
5312                 switch (encoder->type) {
5313                 case INTEL_OUTPUT_LVDS:
5314                         has_panel = true;
5315                         has_lvds = true;
5316                         break;
5317                 case INTEL_OUTPUT_EDP:
5318                         has_panel = true;
5319                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5320                                 has_cpu_edp = true;
5321                         break;
5322                 }
5323         }
5324
5325         if (HAS_PCH_IBX(dev)) {
5326                 has_ck505 = dev_priv->vbt.display_clock_mode;
5327                 can_ssc = has_ck505;
5328         } else {
5329                 has_ck505 = false;
5330                 can_ssc = true;
5331         }
5332
5333         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5334                       has_panel, has_lvds, has_ck505);
5335
5336         /* Ironlake: try to setup display ref clock before DPLL
5337          * enabling. This is only under driver's control after
5338          * PCH B stepping, previous chipset stepping should be
5339          * ignoring this setting.
5340          */
5341         val = I915_READ(PCH_DREF_CONTROL);
5342
5343         /* As we must carefully and slowly disable/enable each source in turn,
5344          * compute the final state we want first and check if we need to
5345          * make any changes at all.
5346          */
5347         final = val;
5348         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5349         if (has_ck505)
5350                 final |= DREF_NONSPREAD_CK505_ENABLE;
5351         else
5352                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5353
5354         final &= ~DREF_SSC_SOURCE_MASK;
5355         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5356         final &= ~DREF_SSC1_ENABLE;
5357
5358         if (has_panel) {
5359                 final |= DREF_SSC_SOURCE_ENABLE;
5360
5361                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5362                         final |= DREF_SSC1_ENABLE;
5363
5364                 if (has_cpu_edp) {
5365                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5366                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5367                         else
5368                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5369                 } else
5370                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5371         } else {
5372                 final |= DREF_SSC_SOURCE_DISABLE;
5373                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5374         }
5375
5376         if (final == val)
5377                 return;
5378
5379         /* Always enable nonspread source */
5380         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5381
5382         if (has_ck505)
5383                 val |= DREF_NONSPREAD_CK505_ENABLE;
5384         else
5385                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5386
5387         if (has_panel) {
5388                 val &= ~DREF_SSC_SOURCE_MASK;
5389                 val |= DREF_SSC_SOURCE_ENABLE;
5390
5391                 /* SSC must be turned on before enabling the CPU output  */
5392                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5393                         DRM_DEBUG_KMS("Using SSC on panel\n");
5394                         val |= DREF_SSC1_ENABLE;
5395                 } else
5396                         val &= ~DREF_SSC1_ENABLE;
5397
5398                 /* Get SSC going before enabling the outputs */
5399                 I915_WRITE(PCH_DREF_CONTROL, val);
5400                 POSTING_READ(PCH_DREF_CONTROL);
5401                 udelay(200);
5402
5403                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5404
5405                 /* Enable CPU source on CPU attached eDP */
5406                 if (has_cpu_edp) {
5407                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5408                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5409                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5410                         }
5411                         else
5412                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5413                 } else
5414                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5415
5416                 I915_WRITE(PCH_DREF_CONTROL, val);
5417                 POSTING_READ(PCH_DREF_CONTROL);
5418                 udelay(200);
5419         } else {
5420                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5421
5422                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5423
5424                 /* Turn off CPU output */
5425                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5426
5427                 I915_WRITE(PCH_DREF_CONTROL, val);
5428                 POSTING_READ(PCH_DREF_CONTROL);
5429                 udelay(200);
5430
5431                 /* Turn off the SSC source */
5432                 val &= ~DREF_SSC_SOURCE_MASK;
5433                 val |= DREF_SSC_SOURCE_DISABLE;
5434
5435                 /* Turn off SSC1 */
5436                 val &= ~DREF_SSC1_ENABLE;
5437
5438                 I915_WRITE(PCH_DREF_CONTROL, val);
5439                 POSTING_READ(PCH_DREF_CONTROL);
5440                 udelay(200);
5441         }
5442
5443         BUG_ON(val != final);
5444 }
5445
5446 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5447 {
5448         uint32_t tmp;
5449
5450         tmp = I915_READ(SOUTH_CHICKEN2);
5451         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5452         I915_WRITE(SOUTH_CHICKEN2, tmp);
5453
5454         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5455                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5456                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5457
5458         tmp = I915_READ(SOUTH_CHICKEN2);
5459         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5460         I915_WRITE(SOUTH_CHICKEN2, tmp);
5461
5462         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5463                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5464                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5465 }
5466
5467 /* WaMPhyProgramming:hsw */
5468 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5469 {
5470         uint32_t tmp;
5471
5472         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5473         tmp &= ~(0xFF << 24);
5474         tmp |= (0x12 << 24);
5475         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5476
5477         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5478         tmp |= (1 << 11);
5479         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5480
5481         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5482         tmp |= (1 << 11);
5483         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5484
5485         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5486         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5487         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5488
5489         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5490         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5491         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5492
5493         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5494         tmp &= ~(7 << 13);
5495         tmp |= (5 << 13);
5496         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5497
5498         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5499         tmp &= ~(7 << 13);
5500         tmp |= (5 << 13);
5501         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5502
5503         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5504         tmp &= ~0xFF;
5505         tmp |= 0x1C;
5506         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5507
5508         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5509         tmp &= ~0xFF;
5510         tmp |= 0x1C;
5511         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5512
5513         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5514         tmp &= ~(0xFF << 16);
5515         tmp |= (0x1C << 16);
5516         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5517
5518         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5519         tmp &= ~(0xFF << 16);
5520         tmp |= (0x1C << 16);
5521         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5522
5523         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5524         tmp |= (1 << 27);
5525         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5526
5527         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5528         tmp |= (1 << 27);
5529         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5530
5531         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5532         tmp &= ~(0xF << 28);
5533         tmp |= (4 << 28);
5534         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5535
5536         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5537         tmp &= ~(0xF << 28);
5538         tmp |= (4 << 28);
5539         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5540 }
5541
5542 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5543  * Programming" based on the parameters passed:
5544  * - Sequence to enable CLKOUT_DP
5545  * - Sequence to enable CLKOUT_DP without spread
5546  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5547  */
5548 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5549                                  bool with_fdi)
5550 {
5551         struct drm_i915_private *dev_priv = dev->dev_private;
5552         uint32_t reg, tmp;
5553
5554         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5555                 with_spread = true;
5556         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5557                  with_fdi, "LP PCH doesn't have FDI\n"))
5558                 with_fdi = false;
5559
5560         mutex_lock(&dev_priv->dpio_lock);
5561
5562         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5563         tmp &= ~SBI_SSCCTL_DISABLE;
5564         tmp |= SBI_SSCCTL_PATHALT;
5565         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5566
5567         udelay(24);
5568
5569         if (with_spread) {
5570                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5571                 tmp &= ~SBI_SSCCTL_PATHALT;
5572                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5573
5574                 if (with_fdi) {
5575                         lpt_reset_fdi_mphy(dev_priv);
5576                         lpt_program_fdi_mphy(dev_priv);
5577                 }
5578         }
5579
5580         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5581                SBI_GEN0 : SBI_DBUFF0;
5582         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5583         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5584         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5585
5586         mutex_unlock(&dev_priv->dpio_lock);
5587 }
5588
5589 /* Sequence to disable CLKOUT_DP */
5590 static void lpt_disable_clkout_dp(struct drm_device *dev)
5591 {
5592         struct drm_i915_private *dev_priv = dev->dev_private;
5593         uint32_t reg, tmp;
5594
5595         mutex_lock(&dev_priv->dpio_lock);
5596
5597         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5598                SBI_GEN0 : SBI_DBUFF0;
5599         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5600         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5601         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5602
5603         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5604         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5605                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5606                         tmp |= SBI_SSCCTL_PATHALT;
5607                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5608                         udelay(32);
5609                 }
5610                 tmp |= SBI_SSCCTL_DISABLE;
5611                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5612         }
5613
5614         mutex_unlock(&dev_priv->dpio_lock);
5615 }
5616
5617 static void lpt_init_pch_refclk(struct drm_device *dev)
5618 {
5619         struct drm_mode_config *mode_config = &dev->mode_config;
5620         struct intel_encoder *encoder;
5621         bool has_vga = false;
5622
5623         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5624                 switch (encoder->type) {
5625                 case INTEL_OUTPUT_ANALOG:
5626                         has_vga = true;
5627                         break;
5628                 }
5629         }
5630
5631         if (has_vga)
5632                 lpt_enable_clkout_dp(dev, true, true);
5633         else
5634                 lpt_disable_clkout_dp(dev);
5635 }
5636
5637 /*
5638  * Initialize reference clocks when the driver loads
5639  */
5640 void intel_init_pch_refclk(struct drm_device *dev)
5641 {
5642         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5643                 ironlake_init_pch_refclk(dev);
5644         else if (HAS_PCH_LPT(dev))
5645                 lpt_init_pch_refclk(dev);
5646 }
5647
5648 static int ironlake_get_refclk(struct drm_crtc *crtc)
5649 {
5650         struct drm_device *dev = crtc->dev;
5651         struct drm_i915_private *dev_priv = dev->dev_private;
5652         struct intel_encoder *encoder;
5653         int num_connectors = 0;
5654         bool is_lvds = false;
5655
5656         for_each_encoder_on_crtc(dev, crtc, encoder) {
5657                 switch (encoder->type) {
5658                 case INTEL_OUTPUT_LVDS:
5659                         is_lvds = true;
5660                         break;
5661                 }
5662                 num_connectors++;
5663         }
5664
5665         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5666                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5667                               dev_priv->vbt.lvds_ssc_freq);
5668                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5669         }
5670
5671         return 120000;
5672 }
5673
5674 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5675 {
5676         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5678         int pipe = intel_crtc->pipe;
5679         uint32_t val;
5680
5681         val = 0;
5682
5683         switch (intel_crtc->config.pipe_bpp) {
5684         case 18:
5685                 val |= PIPECONF_6BPC;
5686                 break;
5687         case 24:
5688                 val |= PIPECONF_8BPC;
5689                 break;
5690         case 30:
5691                 val |= PIPECONF_10BPC;
5692                 break;
5693         case 36:
5694                 val |= PIPECONF_12BPC;
5695                 break;
5696         default:
5697                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5698                 BUG();
5699         }
5700
5701         if (intel_crtc->config.dither)
5702                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5703
5704         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5705                 val |= PIPECONF_INTERLACED_ILK;
5706         else
5707                 val |= PIPECONF_PROGRESSIVE;
5708
5709         if (intel_crtc->config.limited_color_range)
5710                 val |= PIPECONF_COLOR_RANGE_SELECT;
5711
5712         I915_WRITE(PIPECONF(pipe), val);
5713         POSTING_READ(PIPECONF(pipe));
5714 }
5715
5716 /*
5717  * Set up the pipe CSC unit.
5718  *
5719  * Currently only full range RGB to limited range RGB conversion
5720  * is supported, but eventually this should handle various
5721  * RGB<->YCbCr scenarios as well.
5722  */
5723 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5724 {
5725         struct drm_device *dev = crtc->dev;
5726         struct drm_i915_private *dev_priv = dev->dev_private;
5727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5728         int pipe = intel_crtc->pipe;
5729         uint16_t coeff = 0x7800; /* 1.0 */
5730
5731         /*
5732          * TODO: Check what kind of values actually come out of the pipe
5733          * with these coeff/postoff values and adjust to get the best
5734          * accuracy. Perhaps we even need to take the bpc value into
5735          * consideration.
5736          */
5737
5738         if (intel_crtc->config.limited_color_range)
5739                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5740
5741         /*
5742          * GY/GU and RY/RU should be the other way around according
5743          * to BSpec, but reality doesn't agree. Just set them up in
5744          * a way that results in the correct picture.
5745          */
5746         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5747         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5748
5749         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5750         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5751
5752         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5753         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5754
5755         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5756         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5757         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5758
5759         if (INTEL_INFO(dev)->gen > 6) {
5760                 uint16_t postoff = 0;
5761
5762                 if (intel_crtc->config.limited_color_range)
5763                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5764
5765                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5766                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5767                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5768
5769                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5770         } else {
5771                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5772
5773                 if (intel_crtc->config.limited_color_range)
5774                         mode |= CSC_BLACK_SCREEN_OFFSET;
5775
5776                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5777         }
5778 }
5779
5780 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5781 {
5782         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5784         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5785         uint32_t val;
5786
5787         val = 0;
5788
5789         if (intel_crtc->config.dither)
5790                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5791
5792         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5793                 val |= PIPECONF_INTERLACED_ILK;
5794         else
5795                 val |= PIPECONF_PROGRESSIVE;
5796
5797         I915_WRITE(PIPECONF(cpu_transcoder), val);
5798         POSTING_READ(PIPECONF(cpu_transcoder));
5799
5800         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5801         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5802 }
5803
5804 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5805                                     intel_clock_t *clock,
5806                                     bool *has_reduced_clock,
5807                                     intel_clock_t *reduced_clock)
5808 {
5809         struct drm_device *dev = crtc->dev;
5810         struct drm_i915_private *dev_priv = dev->dev_private;
5811         struct intel_encoder *intel_encoder;
5812         int refclk;
5813         const intel_limit_t *limit;
5814         bool ret, is_lvds = false;
5815
5816         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5817                 switch (intel_encoder->type) {
5818                 case INTEL_OUTPUT_LVDS:
5819                         is_lvds = true;
5820                         break;
5821                 }
5822         }
5823
5824         refclk = ironlake_get_refclk(crtc);
5825
5826         /*
5827          * Returns a set of divisors for the desired target clock with the given
5828          * refclk, or FALSE.  The returned values represent the clock equation:
5829          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5830          */
5831         limit = intel_limit(crtc, refclk);
5832         ret = dev_priv->display.find_dpll(limit, crtc,
5833                                           to_intel_crtc(crtc)->config.port_clock,
5834                                           refclk, NULL, clock);
5835         if (!ret)
5836                 return false;
5837
5838         if (is_lvds && dev_priv->lvds_downclock_avail) {
5839                 /*
5840                  * Ensure we match the reduced clock's P to the target clock.
5841                  * If the clocks don't match, we can't switch the display clock
5842                  * by using the FP0/FP1. In such case we will disable the LVDS
5843                  * downclock feature.
5844                 */
5845                 *has_reduced_clock =
5846                         dev_priv->display.find_dpll(limit, crtc,
5847                                                     dev_priv->lvds_downclock,
5848                                                     refclk, clock,
5849                                                     reduced_clock);
5850         }
5851
5852         return true;
5853 }
5854
5855 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5856 {
5857         struct drm_i915_private *dev_priv = dev->dev_private;
5858         uint32_t temp;
5859
5860         temp = I915_READ(SOUTH_CHICKEN1);
5861         if (temp & FDI_BC_BIFURCATION_SELECT)
5862                 return;
5863
5864         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5865         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5866
5867         temp |= FDI_BC_BIFURCATION_SELECT;
5868         DRM_DEBUG_KMS("enabling fdi C rx\n");
5869         I915_WRITE(SOUTH_CHICKEN1, temp);
5870         POSTING_READ(SOUTH_CHICKEN1);
5871 }
5872
5873 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5874 {
5875         struct drm_device *dev = intel_crtc->base.dev;
5876         struct drm_i915_private *dev_priv = dev->dev_private;
5877
5878         switch (intel_crtc->pipe) {
5879         case PIPE_A:
5880                 break;
5881         case PIPE_B:
5882                 if (intel_crtc->config.fdi_lanes > 2)
5883                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5884                 else
5885                         cpt_enable_fdi_bc_bifurcation(dev);
5886
5887                 break;
5888         case PIPE_C:
5889                 cpt_enable_fdi_bc_bifurcation(dev);
5890
5891                 break;
5892         default:
5893                 BUG();
5894         }
5895 }
5896
5897 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5898 {
5899         /*
5900          * Account for spread spectrum to avoid
5901          * oversubscribing the link. Max center spread
5902          * is 2.5%; use 5% for safety's sake.
5903          */
5904         u32 bps = target_clock * bpp * 21 / 20;
5905         return bps / (link_bw * 8) + 1;
5906 }
5907
5908 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5909 {
5910         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5911 }
5912
5913 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5914                                       u32 *fp,
5915                                       intel_clock_t *reduced_clock, u32 *fp2)
5916 {
5917         struct drm_crtc *crtc = &intel_crtc->base;
5918         struct drm_device *dev = crtc->dev;
5919         struct drm_i915_private *dev_priv = dev->dev_private;
5920         struct intel_encoder *intel_encoder;
5921         uint32_t dpll;
5922         int factor, num_connectors = 0;
5923         bool is_lvds = false, is_sdvo = false;
5924
5925         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5926                 switch (intel_encoder->type) {
5927                 case INTEL_OUTPUT_LVDS:
5928                         is_lvds = true;
5929                         break;
5930                 case INTEL_OUTPUT_SDVO:
5931                 case INTEL_OUTPUT_HDMI:
5932                         is_sdvo = true;
5933                         break;
5934                 }
5935
5936                 num_connectors++;
5937         }
5938
5939         /* Enable autotuning of the PLL clock (if permissible) */
5940         factor = 21;
5941         if (is_lvds) {
5942                 if ((intel_panel_use_ssc(dev_priv) &&
5943                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5944                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5945                         factor = 25;
5946         } else if (intel_crtc->config.sdvo_tv_clock)
5947                 factor = 20;
5948
5949         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5950                 *fp |= FP_CB_TUNE;
5951
5952         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5953                 *fp2 |= FP_CB_TUNE;
5954
5955         dpll = 0;
5956
5957         if (is_lvds)
5958                 dpll |= DPLLB_MODE_LVDS;
5959         else
5960                 dpll |= DPLLB_MODE_DAC_SERIAL;
5961
5962         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5963                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5964
5965         if (is_sdvo)
5966                 dpll |= DPLL_SDVO_HIGH_SPEED;
5967         if (intel_crtc->config.has_dp_encoder)
5968                 dpll |= DPLL_SDVO_HIGH_SPEED;
5969
5970         /* compute bitmask from p1 value */
5971         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5972         /* also FPA1 */
5973         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5974
5975         switch (intel_crtc->config.dpll.p2) {
5976         case 5:
5977                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5978                 break;
5979         case 7:
5980                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5981                 break;
5982         case 10:
5983                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5984                 break;
5985         case 14:
5986                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5987                 break;
5988         }
5989
5990         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5991                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5992         else
5993                 dpll |= PLL_REF_INPUT_DREFCLK;
5994
5995         return dpll | DPLL_VCO_ENABLE;
5996 }
5997
5998 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5999                                   int x, int y,
6000                                   struct drm_framebuffer *fb)
6001 {
6002         struct drm_device *dev = crtc->dev;
6003         struct drm_i915_private *dev_priv = dev->dev_private;
6004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6005         int pipe = intel_crtc->pipe;
6006         int plane = intel_crtc->plane;
6007         int num_connectors = 0;
6008         intel_clock_t clock, reduced_clock;
6009         u32 dpll = 0, fp = 0, fp2 = 0;
6010         bool ok, has_reduced_clock = false;
6011         bool is_lvds = false;
6012         struct intel_encoder *encoder;
6013         struct intel_shared_dpll *pll;
6014         int ret;
6015
6016         for_each_encoder_on_crtc(dev, crtc, encoder) {
6017                 switch (encoder->type) {
6018                 case INTEL_OUTPUT_LVDS:
6019                         is_lvds = true;
6020                         break;
6021                 }
6022
6023                 num_connectors++;
6024         }
6025
6026         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6027              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6028
6029         ok = ironlake_compute_clocks(crtc, &clock,
6030                                      &has_reduced_clock, &reduced_clock);
6031         if (!ok && !intel_crtc->config.clock_set) {
6032                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6033                 return -EINVAL;
6034         }
6035         /* Compat-code for transition, will disappear. */
6036         if (!intel_crtc->config.clock_set) {
6037                 intel_crtc->config.dpll.n = clock.n;
6038                 intel_crtc->config.dpll.m1 = clock.m1;
6039                 intel_crtc->config.dpll.m2 = clock.m2;
6040                 intel_crtc->config.dpll.p1 = clock.p1;
6041                 intel_crtc->config.dpll.p2 = clock.p2;
6042         }
6043
6044         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6045         if (intel_crtc->config.has_pch_encoder) {
6046                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6047                 if (has_reduced_clock)
6048                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6049
6050                 dpll = ironlake_compute_dpll(intel_crtc,
6051                                              &fp, &reduced_clock,
6052                                              has_reduced_clock ? &fp2 : NULL);
6053
6054                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6055                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6056                 if (has_reduced_clock)
6057                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6058                 else
6059                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6060
6061                 pll = intel_get_shared_dpll(intel_crtc);
6062                 if (pll == NULL) {
6063                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6064                                          pipe_name(pipe));
6065                         return -EINVAL;
6066                 }
6067         } else
6068                 intel_put_shared_dpll(intel_crtc);
6069
6070         if (intel_crtc->config.has_dp_encoder)
6071                 intel_dp_set_m_n(intel_crtc);
6072
6073         if (is_lvds && has_reduced_clock && i915_powersave)
6074                 intel_crtc->lowfreq_avail = true;
6075         else
6076                 intel_crtc->lowfreq_avail = false;
6077
6078         if (intel_crtc->config.has_pch_encoder) {
6079                 pll = intel_crtc_to_shared_dpll(intel_crtc);
6080
6081         }
6082
6083         intel_set_pipe_timings(intel_crtc);
6084
6085         if (intel_crtc->config.has_pch_encoder) {
6086                 intel_cpu_transcoder_set_m_n(intel_crtc,
6087                                              &intel_crtc->config.fdi_m_n);
6088         }
6089
6090         if (IS_IVYBRIDGE(dev))
6091                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
6092
6093         ironlake_set_pipeconf(crtc);
6094
6095         /* Set up the display plane register */
6096         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6097         POSTING_READ(DSPCNTR(plane));
6098
6099         ret = intel_pipe_set_base(crtc, x, y, fb);
6100
6101         return ret;
6102 }
6103
6104 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6105                                          struct intel_link_m_n *m_n)
6106 {
6107         struct drm_device *dev = crtc->base.dev;
6108         struct drm_i915_private *dev_priv = dev->dev_private;
6109         enum pipe pipe = crtc->pipe;
6110
6111         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6112         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6113         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6114                 & ~TU_SIZE_MASK;
6115         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6116         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6117                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6118 }
6119
6120 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6121                                          enum transcoder transcoder,
6122                                          struct intel_link_m_n *m_n)
6123 {
6124         struct drm_device *dev = crtc->base.dev;
6125         struct drm_i915_private *dev_priv = dev->dev_private;
6126         enum pipe pipe = crtc->pipe;
6127
6128         if (INTEL_INFO(dev)->gen >= 5) {
6129                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6130                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6131                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6132                         & ~TU_SIZE_MASK;
6133                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6134                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6135                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6136         } else {
6137                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6138                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6139                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6140                         & ~TU_SIZE_MASK;
6141                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6142                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6143                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6144         }
6145 }
6146
6147 void intel_dp_get_m_n(struct intel_crtc *crtc,
6148                       struct intel_crtc_config *pipe_config)
6149 {
6150         if (crtc->config.has_pch_encoder)
6151                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6152         else
6153                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6154                                              &pipe_config->dp_m_n);
6155 }
6156
6157 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6158                                         struct intel_crtc_config *pipe_config)
6159 {
6160         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6161                                      &pipe_config->fdi_m_n);
6162 }
6163
6164 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6165                                      struct intel_crtc_config *pipe_config)
6166 {
6167         struct drm_device *dev = crtc->base.dev;
6168         struct drm_i915_private *dev_priv = dev->dev_private;
6169         uint32_t tmp;
6170
6171         tmp = I915_READ(PF_CTL(crtc->pipe));
6172
6173         if (tmp & PF_ENABLE) {
6174                 pipe_config->pch_pfit.enabled = true;
6175                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6176                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6177
6178                 /* We currently do not free assignements of panel fitters on
6179                  * ivb/hsw (since we don't use the higher upscaling modes which
6180                  * differentiates them) so just WARN about this case for now. */
6181                 if (IS_GEN7(dev)) {
6182                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6183                                 PF_PIPE_SEL_IVB(crtc->pipe));
6184                 }
6185         }
6186 }
6187
6188 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6189                                      struct intel_crtc_config *pipe_config)
6190 {
6191         struct drm_device *dev = crtc->base.dev;
6192         struct drm_i915_private *dev_priv = dev->dev_private;
6193         uint32_t tmp;
6194
6195         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6196         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6197
6198         tmp = I915_READ(PIPECONF(crtc->pipe));
6199         if (!(tmp & PIPECONF_ENABLE))
6200                 return false;
6201
6202         switch (tmp & PIPECONF_BPC_MASK) {
6203         case PIPECONF_6BPC:
6204                 pipe_config->pipe_bpp = 18;
6205                 break;
6206         case PIPECONF_8BPC:
6207                 pipe_config->pipe_bpp = 24;
6208                 break;
6209         case PIPECONF_10BPC:
6210                 pipe_config->pipe_bpp = 30;
6211                 break;
6212         case PIPECONF_12BPC:
6213                 pipe_config->pipe_bpp = 36;
6214                 break;
6215         default:
6216                 break;
6217         }
6218
6219         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6220                 struct intel_shared_dpll *pll;
6221
6222                 pipe_config->has_pch_encoder = true;
6223
6224                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6225                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6226                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6227
6228                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6229
6230                 if (HAS_PCH_IBX(dev_priv->dev)) {
6231                         pipe_config->shared_dpll =
6232                                 (enum intel_dpll_id) crtc->pipe;
6233                 } else {
6234                         tmp = I915_READ(PCH_DPLL_SEL);
6235                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6236                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6237                         else
6238                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6239                 }
6240
6241                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6242
6243                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6244                                            &pipe_config->dpll_hw_state));
6245
6246                 tmp = pipe_config->dpll_hw_state.dpll;
6247                 pipe_config->pixel_multiplier =
6248                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6249                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6250
6251                 ironlake_pch_clock_get(crtc, pipe_config);
6252         } else {
6253                 pipe_config->pixel_multiplier = 1;
6254         }
6255
6256         intel_get_pipe_timings(crtc, pipe_config);
6257
6258         ironlake_get_pfit_config(crtc, pipe_config);
6259
6260         return true;
6261 }
6262
6263 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6264 {
6265         struct drm_device *dev = dev_priv->dev;
6266         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6267         struct intel_crtc *crtc;
6268         unsigned long irqflags;
6269         uint32_t val;
6270
6271         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6272                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6273                      pipe_name(crtc->pipe));
6274
6275         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6276         WARN(plls->spll_refcount, "SPLL enabled\n");
6277         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6278         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6279         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6280         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6281              "CPU PWM1 enabled\n");
6282         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6283              "CPU PWM2 enabled\n");
6284         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6285              "PCH PWM1 enabled\n");
6286         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6287              "Utility pin enabled\n");
6288         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6289
6290         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6291         val = I915_READ(DEIMR);
6292         WARN((val & ~DE_PCH_EVENT_IVB) != val,
6293              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6294         val = I915_READ(SDEIMR);
6295         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6296              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6297         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6298 }
6299
6300 /*
6301  * This function implements pieces of two sequences from BSpec:
6302  * - Sequence for display software to disable LCPLL
6303  * - Sequence for display software to allow package C8+
6304  * The steps implemented here are just the steps that actually touch the LCPLL
6305  * register. Callers should take care of disabling all the display engine
6306  * functions, doing the mode unset, fixing interrupts, etc.
6307  */
6308 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6309                               bool switch_to_fclk, bool allow_power_down)
6310 {
6311         uint32_t val;
6312
6313         assert_can_disable_lcpll(dev_priv);
6314
6315         val = I915_READ(LCPLL_CTL);
6316
6317         if (switch_to_fclk) {
6318                 val |= LCPLL_CD_SOURCE_FCLK;
6319                 I915_WRITE(LCPLL_CTL, val);
6320
6321                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6322                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6323                         DRM_ERROR("Switching to FCLK failed\n");
6324
6325                 val = I915_READ(LCPLL_CTL);
6326         }
6327
6328         val |= LCPLL_PLL_DISABLE;
6329         I915_WRITE(LCPLL_CTL, val);
6330         POSTING_READ(LCPLL_CTL);
6331
6332         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6333                 DRM_ERROR("LCPLL still locked\n");
6334
6335         val = I915_READ(D_COMP);
6336         val |= D_COMP_COMP_DISABLE;
6337         mutex_lock(&dev_priv->rps.hw_lock);
6338         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6339                 DRM_ERROR("Failed to disable D_COMP\n");
6340         mutex_unlock(&dev_priv->rps.hw_lock);
6341         POSTING_READ(D_COMP);
6342         ndelay(100);
6343
6344         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6345                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6346
6347         if (allow_power_down) {
6348                 val = I915_READ(LCPLL_CTL);
6349                 val |= LCPLL_POWER_DOWN_ALLOW;
6350                 I915_WRITE(LCPLL_CTL, val);
6351                 POSTING_READ(LCPLL_CTL);
6352         }
6353 }
6354
6355 /*
6356  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6357  * source.
6358  */
6359 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6360 {
6361         uint32_t val;
6362
6363         val = I915_READ(LCPLL_CTL);
6364
6365         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6366                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6367                 return;
6368
6369         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6370          * we'll hang the machine! */
6371         dev_priv->uncore.funcs.force_wake_get(dev_priv);
6372
6373         if (val & LCPLL_POWER_DOWN_ALLOW) {
6374                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6375                 I915_WRITE(LCPLL_CTL, val);
6376                 POSTING_READ(LCPLL_CTL);
6377         }
6378
6379         val = I915_READ(D_COMP);
6380         val |= D_COMP_COMP_FORCE;
6381         val &= ~D_COMP_COMP_DISABLE;
6382         mutex_lock(&dev_priv->rps.hw_lock);
6383         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6384                 DRM_ERROR("Failed to enable D_COMP\n");
6385         mutex_unlock(&dev_priv->rps.hw_lock);
6386         POSTING_READ(D_COMP);
6387
6388         val = I915_READ(LCPLL_CTL);
6389         val &= ~LCPLL_PLL_DISABLE;
6390         I915_WRITE(LCPLL_CTL, val);
6391
6392         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6393                 DRM_ERROR("LCPLL not locked yet\n");
6394
6395         if (val & LCPLL_CD_SOURCE_FCLK) {
6396                 val = I915_READ(LCPLL_CTL);
6397                 val &= ~LCPLL_CD_SOURCE_FCLK;
6398                 I915_WRITE(LCPLL_CTL, val);
6399
6400                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6401                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6402                         DRM_ERROR("Switching back to LCPLL failed\n");
6403         }
6404
6405         dev_priv->uncore.funcs.force_wake_put(dev_priv);
6406 }
6407
6408 void hsw_enable_pc8_work(struct work_struct *__work)
6409 {
6410         struct drm_i915_private *dev_priv =
6411                 container_of(to_delayed_work(__work), struct drm_i915_private,
6412                              pc8.enable_work);
6413         struct drm_device *dev = dev_priv->dev;
6414         uint32_t val;
6415
6416         if (dev_priv->pc8.enabled)
6417                 return;
6418
6419         DRM_DEBUG_KMS("Enabling package C8+\n");
6420
6421         dev_priv->pc8.enabled = true;
6422
6423         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6424                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6425                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6426                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6427         }
6428
6429         lpt_disable_clkout_dp(dev);
6430         hsw_pc8_disable_interrupts(dev);
6431         hsw_disable_lcpll(dev_priv, true, true);
6432 }
6433
6434 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6435 {
6436         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6437         WARN(dev_priv->pc8.disable_count < 1,
6438              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6439
6440         dev_priv->pc8.disable_count--;
6441         if (dev_priv->pc8.disable_count != 0)
6442                 return;
6443
6444         schedule_delayed_work(&dev_priv->pc8.enable_work,
6445                               msecs_to_jiffies(i915_pc8_timeout));
6446 }
6447
6448 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6449 {
6450         struct drm_device *dev = dev_priv->dev;
6451         uint32_t val;
6452
6453         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6454         WARN(dev_priv->pc8.disable_count < 0,
6455              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6456
6457         dev_priv->pc8.disable_count++;
6458         if (dev_priv->pc8.disable_count != 1)
6459                 return;
6460
6461         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6462         if (!dev_priv->pc8.enabled)
6463                 return;
6464
6465         DRM_DEBUG_KMS("Disabling package C8+\n");
6466
6467         hsw_restore_lcpll(dev_priv);
6468         hsw_pc8_restore_interrupts(dev);
6469         lpt_init_pch_refclk(dev);
6470
6471         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6472                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6473                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6474                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6475         }
6476
6477         intel_prepare_ddi(dev);
6478         i915_gem_init_swizzling(dev);
6479         mutex_lock(&dev_priv->rps.hw_lock);
6480         gen6_update_ring_freq(dev);
6481         mutex_unlock(&dev_priv->rps.hw_lock);
6482         dev_priv->pc8.enabled = false;
6483 }
6484
6485 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6486 {
6487         mutex_lock(&dev_priv->pc8.lock);
6488         __hsw_enable_package_c8(dev_priv);
6489         mutex_unlock(&dev_priv->pc8.lock);
6490 }
6491
6492 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6493 {
6494         mutex_lock(&dev_priv->pc8.lock);
6495         __hsw_disable_package_c8(dev_priv);
6496         mutex_unlock(&dev_priv->pc8.lock);
6497 }
6498
6499 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6500 {
6501         struct drm_device *dev = dev_priv->dev;
6502         struct intel_crtc *crtc;
6503         uint32_t val;
6504
6505         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6506                 if (crtc->base.enabled)
6507                         return false;
6508
6509         /* This case is still possible since we have the i915.disable_power_well
6510          * parameter and also the KVMr or something else might be requesting the
6511          * power well. */
6512         val = I915_READ(HSW_PWR_WELL_DRIVER);
6513         if (val != 0) {
6514                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6515                 return false;
6516         }
6517
6518         return true;
6519 }
6520
6521 /* Since we're called from modeset_global_resources there's no way to
6522  * symmetrically increase and decrease the refcount, so we use
6523  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6524  * or not.
6525  */
6526 static void hsw_update_package_c8(struct drm_device *dev)
6527 {
6528         struct drm_i915_private *dev_priv = dev->dev_private;
6529         bool allow;
6530
6531         if (!i915_enable_pc8)
6532                 return;
6533
6534         mutex_lock(&dev_priv->pc8.lock);
6535
6536         allow = hsw_can_enable_package_c8(dev_priv);
6537
6538         if (allow == dev_priv->pc8.requirements_met)
6539                 goto done;
6540
6541         dev_priv->pc8.requirements_met = allow;
6542
6543         if (allow)
6544                 __hsw_enable_package_c8(dev_priv);
6545         else
6546                 __hsw_disable_package_c8(dev_priv);
6547
6548 done:
6549         mutex_unlock(&dev_priv->pc8.lock);
6550 }
6551
6552 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6553 {
6554         if (!dev_priv->pc8.gpu_idle) {
6555                 dev_priv->pc8.gpu_idle = true;
6556                 hsw_enable_package_c8(dev_priv);
6557         }
6558 }
6559
6560 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6561 {
6562         if (dev_priv->pc8.gpu_idle) {
6563                 dev_priv->pc8.gpu_idle = false;
6564                 hsw_disable_package_c8(dev_priv);
6565         }
6566 }
6567
6568 static void haswell_modeset_global_resources(struct drm_device *dev)
6569 {
6570         bool enable = false;
6571         struct intel_crtc *crtc;
6572
6573         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6574                 if (!crtc->base.enabled)
6575                         continue;
6576
6577                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
6578                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6579                         enable = true;
6580         }
6581
6582         intel_set_power_well(dev, enable);
6583
6584         hsw_update_package_c8(dev);
6585 }
6586
6587 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6588                                  int x, int y,
6589                                  struct drm_framebuffer *fb)
6590 {
6591         struct drm_device *dev = crtc->dev;
6592         struct drm_i915_private *dev_priv = dev->dev_private;
6593         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6594         int plane = intel_crtc->plane;
6595         int ret;
6596
6597         if (!intel_ddi_pll_mode_set(crtc))
6598                 return -EINVAL;
6599
6600         if (intel_crtc->config.has_dp_encoder)
6601                 intel_dp_set_m_n(intel_crtc);
6602
6603         intel_crtc->lowfreq_avail = false;
6604
6605         intel_set_pipe_timings(intel_crtc);
6606
6607         if (intel_crtc->config.has_pch_encoder) {
6608                 intel_cpu_transcoder_set_m_n(intel_crtc,
6609                                              &intel_crtc->config.fdi_m_n);
6610         }
6611
6612         haswell_set_pipeconf(crtc);
6613
6614         intel_set_pipe_csc(crtc);
6615
6616         /* Set up the display plane register */
6617         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6618         POSTING_READ(DSPCNTR(plane));
6619
6620         ret = intel_pipe_set_base(crtc, x, y, fb);
6621
6622         return ret;
6623 }
6624
6625 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6626                                     struct intel_crtc_config *pipe_config)
6627 {
6628         struct drm_device *dev = crtc->base.dev;
6629         struct drm_i915_private *dev_priv = dev->dev_private;
6630         enum intel_display_power_domain pfit_domain;
6631         uint32_t tmp;
6632
6633         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6634         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6635
6636         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6637         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6638                 enum pipe trans_edp_pipe;
6639                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6640                 default:
6641                         WARN(1, "unknown pipe linked to edp transcoder\n");
6642                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6643                 case TRANS_DDI_EDP_INPUT_A_ON:
6644                         trans_edp_pipe = PIPE_A;
6645                         break;
6646                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6647                         trans_edp_pipe = PIPE_B;
6648                         break;
6649                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6650                         trans_edp_pipe = PIPE_C;
6651                         break;
6652                 }
6653
6654                 if (trans_edp_pipe == crtc->pipe)
6655                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6656         }
6657
6658         if (!intel_display_power_enabled(dev,
6659                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6660                 return false;
6661
6662         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6663         if (!(tmp & PIPECONF_ENABLE))
6664                 return false;
6665
6666         /*
6667          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6668          * DDI E. So just check whether this pipe is wired to DDI E and whether
6669          * the PCH transcoder is on.
6670          */
6671         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6672         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6673             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6674                 pipe_config->has_pch_encoder = true;
6675
6676                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6677                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6678                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6679
6680                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6681         }
6682
6683         intel_get_pipe_timings(crtc, pipe_config);
6684
6685         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6686         if (intel_display_power_enabled(dev, pfit_domain))
6687                 ironlake_get_pfit_config(crtc, pipe_config);
6688
6689         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6690                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6691
6692         pipe_config->pixel_multiplier = 1;
6693
6694         return true;
6695 }
6696
6697 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6698                                int x, int y,
6699                                struct drm_framebuffer *fb)
6700 {
6701         struct drm_device *dev = crtc->dev;
6702         struct drm_i915_private *dev_priv = dev->dev_private;
6703         struct intel_encoder *encoder;
6704         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6705         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6706         int pipe = intel_crtc->pipe;
6707         int ret;
6708
6709         drm_vblank_pre_modeset(dev, pipe);
6710
6711         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6712
6713         drm_vblank_post_modeset(dev, pipe);
6714
6715         if (ret != 0)
6716                 return ret;
6717
6718         for_each_encoder_on_crtc(dev, crtc, encoder) {
6719                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6720                         encoder->base.base.id,
6721                         drm_get_encoder_name(&encoder->base),
6722                         mode->base.id, mode->name);
6723                 encoder->mode_set(encoder);
6724         }
6725
6726         return 0;
6727 }
6728
6729 static bool intel_eld_uptodate(struct drm_connector *connector,
6730                                int reg_eldv, uint32_t bits_eldv,
6731                                int reg_elda, uint32_t bits_elda,
6732                                int reg_edid)
6733 {
6734         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6735         uint8_t *eld = connector->eld;
6736         uint32_t i;
6737
6738         i = I915_READ(reg_eldv);
6739         i &= bits_eldv;
6740
6741         if (!eld[0])
6742                 return !i;
6743
6744         if (!i)
6745                 return false;
6746
6747         i = I915_READ(reg_elda);
6748         i &= ~bits_elda;
6749         I915_WRITE(reg_elda, i);
6750
6751         for (i = 0; i < eld[2]; i++)
6752                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6753                         return false;
6754
6755         return true;
6756 }
6757
6758 static void g4x_write_eld(struct drm_connector *connector,
6759                           struct drm_crtc *crtc)
6760 {
6761         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6762         uint8_t *eld = connector->eld;
6763         uint32_t eldv;
6764         uint32_t len;
6765         uint32_t i;
6766
6767         i = I915_READ(G4X_AUD_VID_DID);
6768
6769         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6770                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6771         else
6772                 eldv = G4X_ELDV_DEVCTG;
6773
6774         if (intel_eld_uptodate(connector,
6775                                G4X_AUD_CNTL_ST, eldv,
6776                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6777                                G4X_HDMIW_HDMIEDID))
6778                 return;
6779
6780         i = I915_READ(G4X_AUD_CNTL_ST);
6781         i &= ~(eldv | G4X_ELD_ADDR);
6782         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6783         I915_WRITE(G4X_AUD_CNTL_ST, i);
6784
6785         if (!eld[0])
6786                 return;
6787
6788         len = min_t(uint8_t, eld[2], len);
6789         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6790         for (i = 0; i < len; i++)
6791                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6792
6793         i = I915_READ(G4X_AUD_CNTL_ST);
6794         i |= eldv;
6795         I915_WRITE(G4X_AUD_CNTL_ST, i);
6796 }
6797
6798 static void haswell_write_eld(struct drm_connector *connector,
6799                                      struct drm_crtc *crtc)
6800 {
6801         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6802         uint8_t *eld = connector->eld;
6803         struct drm_device *dev = crtc->dev;
6804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6805         uint32_t eldv;
6806         uint32_t i;
6807         int len;
6808         int pipe = to_intel_crtc(crtc)->pipe;
6809         int tmp;
6810
6811         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6812         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6813         int aud_config = HSW_AUD_CFG(pipe);
6814         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6815
6816
6817         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6818
6819         /* Audio output enable */
6820         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6821         tmp = I915_READ(aud_cntrl_st2);
6822         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6823         I915_WRITE(aud_cntrl_st2, tmp);
6824
6825         /* Wait for 1 vertical blank */
6826         intel_wait_for_vblank(dev, pipe);
6827
6828         /* Set ELD valid state */
6829         tmp = I915_READ(aud_cntrl_st2);
6830         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6831         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6832         I915_WRITE(aud_cntrl_st2, tmp);
6833         tmp = I915_READ(aud_cntrl_st2);
6834         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6835
6836         /* Enable HDMI mode */
6837         tmp = I915_READ(aud_config);
6838         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6839         /* clear N_programing_enable and N_value_index */
6840         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6841         I915_WRITE(aud_config, tmp);
6842
6843         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6844
6845         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6846         intel_crtc->eld_vld = true;
6847
6848         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6849                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6850                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6851                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6852         } else
6853                 I915_WRITE(aud_config, 0);
6854
6855         if (intel_eld_uptodate(connector,
6856                                aud_cntrl_st2, eldv,
6857                                aud_cntl_st, IBX_ELD_ADDRESS,
6858                                hdmiw_hdmiedid))
6859                 return;
6860
6861         i = I915_READ(aud_cntrl_st2);
6862         i &= ~eldv;
6863         I915_WRITE(aud_cntrl_st2, i);
6864
6865         if (!eld[0])
6866                 return;
6867
6868         i = I915_READ(aud_cntl_st);
6869         i &= ~IBX_ELD_ADDRESS;
6870         I915_WRITE(aud_cntl_st, i);
6871         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6872         DRM_DEBUG_DRIVER("port num:%d\n", i);
6873
6874         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6875         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6876         for (i = 0; i < len; i++)
6877                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6878
6879         i = I915_READ(aud_cntrl_st2);
6880         i |= eldv;
6881         I915_WRITE(aud_cntrl_st2, i);
6882
6883 }
6884
6885 static void ironlake_write_eld(struct drm_connector *connector,
6886                                      struct drm_crtc *crtc)
6887 {
6888         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6889         uint8_t *eld = connector->eld;
6890         uint32_t eldv;
6891         uint32_t i;
6892         int len;
6893         int hdmiw_hdmiedid;
6894         int aud_config;
6895         int aud_cntl_st;
6896         int aud_cntrl_st2;
6897         int pipe = to_intel_crtc(crtc)->pipe;
6898
6899         if (HAS_PCH_IBX(connector->dev)) {
6900                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6901                 aud_config = IBX_AUD_CFG(pipe);
6902                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6903                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6904         } else {
6905                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6906                 aud_config = CPT_AUD_CFG(pipe);
6907                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6908                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6909         }
6910
6911         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6912
6913         i = I915_READ(aud_cntl_st);
6914         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6915         if (!i) {
6916                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6917                 /* operate blindly on all ports */
6918                 eldv = IBX_ELD_VALIDB;
6919                 eldv |= IBX_ELD_VALIDB << 4;
6920                 eldv |= IBX_ELD_VALIDB << 8;
6921         } else {
6922                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6923                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6924         }
6925
6926         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6927                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6928                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6929                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6930         } else
6931                 I915_WRITE(aud_config, 0);
6932
6933         if (intel_eld_uptodate(connector,
6934                                aud_cntrl_st2, eldv,
6935                                aud_cntl_st, IBX_ELD_ADDRESS,
6936                                hdmiw_hdmiedid))
6937                 return;
6938
6939         i = I915_READ(aud_cntrl_st2);
6940         i &= ~eldv;
6941         I915_WRITE(aud_cntrl_st2, i);
6942
6943         if (!eld[0])
6944                 return;
6945
6946         i = I915_READ(aud_cntl_st);
6947         i &= ~IBX_ELD_ADDRESS;
6948         I915_WRITE(aud_cntl_st, i);
6949
6950         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6951         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6952         for (i = 0; i < len; i++)
6953                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6954
6955         i = I915_READ(aud_cntrl_st2);
6956         i |= eldv;
6957         I915_WRITE(aud_cntrl_st2, i);
6958 }
6959
6960 void intel_write_eld(struct drm_encoder *encoder,
6961                      struct drm_display_mode *mode)
6962 {
6963         struct drm_crtc *crtc = encoder->crtc;
6964         struct drm_connector *connector;
6965         struct drm_device *dev = encoder->dev;
6966         struct drm_i915_private *dev_priv = dev->dev_private;
6967
6968         connector = drm_select_eld(encoder, mode);
6969         if (!connector)
6970                 return;
6971
6972         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6973                          connector->base.id,
6974                          drm_get_connector_name(connector),
6975                          connector->encoder->base.id,
6976                          drm_get_encoder_name(connector->encoder));
6977
6978         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6979
6980         if (dev_priv->display.write_eld)
6981                 dev_priv->display.write_eld(connector, crtc);
6982 }
6983
6984 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6985 {
6986         struct drm_device *dev = crtc->dev;
6987         struct drm_i915_private *dev_priv = dev->dev_private;
6988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6989         bool visible = base != 0;
6990         u32 cntl;
6991
6992         if (intel_crtc->cursor_visible == visible)
6993                 return;
6994
6995         cntl = I915_READ(_CURACNTR);
6996         if (visible) {
6997                 /* On these chipsets we can only modify the base whilst
6998                  * the cursor is disabled.
6999                  */
7000                 I915_WRITE(_CURABASE, base);
7001
7002                 cntl &= ~(CURSOR_FORMAT_MASK);
7003                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7004                 cntl |= CURSOR_ENABLE |
7005                         CURSOR_GAMMA_ENABLE |
7006                         CURSOR_FORMAT_ARGB;
7007         } else
7008                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7009         I915_WRITE(_CURACNTR, cntl);
7010
7011         intel_crtc->cursor_visible = visible;
7012 }
7013
7014 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7015 {
7016         struct drm_device *dev = crtc->dev;
7017         struct drm_i915_private *dev_priv = dev->dev_private;
7018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7019         int pipe = intel_crtc->pipe;
7020         bool visible = base != 0;
7021
7022         if (intel_crtc->cursor_visible != visible) {
7023                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7024                 if (base) {
7025                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7026                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7027                         cntl |= pipe << 28; /* Connect to correct pipe */
7028                 } else {
7029                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7030                         cntl |= CURSOR_MODE_DISABLE;
7031                 }
7032                 I915_WRITE(CURCNTR(pipe), cntl);
7033
7034                 intel_crtc->cursor_visible = visible;
7035         }
7036         /* and commit changes on next vblank */
7037         I915_WRITE(CURBASE(pipe), base);
7038 }
7039
7040 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7041 {
7042         struct drm_device *dev = crtc->dev;
7043         struct drm_i915_private *dev_priv = dev->dev_private;
7044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7045         int pipe = intel_crtc->pipe;
7046         bool visible = base != 0;
7047
7048         if (intel_crtc->cursor_visible != visible) {
7049                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7050                 if (base) {
7051                         cntl &= ~CURSOR_MODE;
7052                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7053                 } else {
7054                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7055                         cntl |= CURSOR_MODE_DISABLE;
7056                 }
7057                 if (IS_HASWELL(dev)) {
7058                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7059                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7060                 }
7061                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7062
7063                 intel_crtc->cursor_visible = visible;
7064         }
7065         /* and commit changes on next vblank */
7066         I915_WRITE(CURBASE_IVB(pipe), base);
7067 }
7068
7069 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7070 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7071                                      bool on)
7072 {
7073         struct drm_device *dev = crtc->dev;
7074         struct drm_i915_private *dev_priv = dev->dev_private;
7075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7076         int pipe = intel_crtc->pipe;
7077         int x = intel_crtc->cursor_x;
7078         int y = intel_crtc->cursor_y;
7079         u32 base = 0, pos = 0;
7080         bool visible;
7081
7082         if (on)
7083                 base = intel_crtc->cursor_addr;
7084
7085         if (x >= intel_crtc->config.pipe_src_w)
7086                 base = 0;
7087
7088         if (y >= intel_crtc->config.pipe_src_h)
7089                 base = 0;
7090
7091         if (x < 0) {
7092                 if (x + intel_crtc->cursor_width <= 0)
7093                         base = 0;
7094
7095                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7096                 x = -x;
7097         }
7098         pos |= x << CURSOR_X_SHIFT;
7099
7100         if (y < 0) {
7101                 if (y + intel_crtc->cursor_height <= 0)
7102                         base = 0;
7103
7104                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7105                 y = -y;
7106         }
7107         pos |= y << CURSOR_Y_SHIFT;
7108
7109         visible = base != 0;
7110         if (!visible && !intel_crtc->cursor_visible)
7111                 return;
7112
7113         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
7114                 I915_WRITE(CURPOS_IVB(pipe), pos);
7115                 ivb_update_cursor(crtc, base);
7116         } else {
7117                 I915_WRITE(CURPOS(pipe), pos);
7118                 if (IS_845G(dev) || IS_I865G(dev))
7119                         i845_update_cursor(crtc, base);
7120                 else
7121                         i9xx_update_cursor(crtc, base);
7122         }
7123 }
7124
7125 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7126                                  struct drm_file *file,
7127                                  uint32_t handle,
7128                                  uint32_t width, uint32_t height)
7129 {
7130         struct drm_device *dev = crtc->dev;
7131         struct drm_i915_private *dev_priv = dev->dev_private;
7132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7133         struct drm_i915_gem_object *obj;
7134         uint32_t addr;
7135         int ret;
7136
7137         /* if we want to turn off the cursor ignore width and height */
7138         if (!handle) {
7139                 DRM_DEBUG_KMS("cursor off\n");
7140                 addr = 0;
7141                 obj = NULL;
7142                 mutex_lock(&dev->struct_mutex);
7143                 goto finish;
7144         }
7145
7146         /* Currently we only support 64x64 cursors */
7147         if (width != 64 || height != 64) {
7148                 DRM_ERROR("we currently only support 64x64 cursors\n");
7149                 return -EINVAL;
7150         }
7151
7152         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7153         if (&obj->base == NULL)
7154                 return -ENOENT;
7155
7156         if (obj->base.size < width * height * 4) {
7157                 DRM_ERROR("buffer is to small\n");
7158                 ret = -ENOMEM;
7159                 goto fail;
7160         }
7161
7162         /* we only need to pin inside GTT if cursor is non-phy */
7163         mutex_lock(&dev->struct_mutex);
7164         if (!dev_priv->info->cursor_needs_physical) {
7165                 unsigned alignment;
7166
7167                 if (obj->tiling_mode) {
7168                         DRM_ERROR("cursor cannot be tiled\n");
7169                         ret = -EINVAL;
7170                         goto fail_locked;
7171                 }
7172
7173                 /* Note that the w/a also requires 2 PTE of padding following
7174                  * the bo. We currently fill all unused PTE with the shadow
7175                  * page and so we should always have valid PTE following the
7176                  * cursor preventing the VT-d warning.
7177                  */
7178                 alignment = 0;
7179                 if (need_vtd_wa(dev))
7180                         alignment = 64*1024;
7181
7182                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7183                 if (ret) {
7184                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7185                         goto fail_locked;
7186                 }
7187
7188                 ret = i915_gem_object_put_fence(obj);
7189                 if (ret) {
7190                         DRM_ERROR("failed to release fence for cursor");
7191                         goto fail_unpin;
7192                 }
7193
7194                 addr = i915_gem_obj_ggtt_offset(obj);
7195         } else {
7196                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7197                 ret = i915_gem_attach_phys_object(dev, obj,
7198                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7199                                                   align);
7200                 if (ret) {
7201                         DRM_ERROR("failed to attach phys object\n");
7202                         goto fail_locked;
7203                 }
7204                 addr = obj->phys_obj->handle->busaddr;
7205         }
7206
7207         if (IS_GEN2(dev))
7208                 I915_WRITE(CURSIZE, (height << 12) | width);
7209
7210  finish:
7211         if (intel_crtc->cursor_bo) {
7212                 if (dev_priv->info->cursor_needs_physical) {
7213                         if (intel_crtc->cursor_bo != obj)
7214                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7215                 } else
7216                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7217                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7218         }
7219
7220         mutex_unlock(&dev->struct_mutex);
7221
7222         intel_crtc->cursor_addr = addr;
7223         intel_crtc->cursor_bo = obj;
7224         intel_crtc->cursor_width = width;
7225         intel_crtc->cursor_height = height;
7226
7227         if (intel_crtc->active)
7228                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7229
7230         return 0;
7231 fail_unpin:
7232         i915_gem_object_unpin_from_display_plane(obj);
7233 fail_locked:
7234         mutex_unlock(&dev->struct_mutex);
7235 fail:
7236         drm_gem_object_unreference_unlocked(&obj->base);
7237         return ret;
7238 }
7239
7240 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7241 {
7242         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7243
7244         intel_crtc->cursor_x = x;
7245         intel_crtc->cursor_y = y;
7246
7247         if (intel_crtc->active)
7248                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7249
7250         return 0;
7251 }
7252
7253 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7254                                  u16 *blue, uint32_t start, uint32_t size)
7255 {
7256         int end = (start + size > 256) ? 256 : start + size, i;
7257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7258
7259         for (i = start; i < end; i++) {
7260                 intel_crtc->lut_r[i] = red[i] >> 8;
7261                 intel_crtc->lut_g[i] = green[i] >> 8;
7262                 intel_crtc->lut_b[i] = blue[i] >> 8;
7263         }
7264
7265         intel_crtc_load_lut(crtc);
7266 }
7267
7268 /* VESA 640x480x72Hz mode to set on the pipe */
7269 static struct drm_display_mode load_detect_mode = {
7270         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7271                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7272 };
7273
7274 static struct drm_framebuffer *
7275 intel_framebuffer_create(struct drm_device *dev,
7276                          struct drm_mode_fb_cmd2 *mode_cmd,
7277                          struct drm_i915_gem_object *obj)
7278 {
7279         struct intel_framebuffer *intel_fb;
7280         int ret;
7281
7282         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7283         if (!intel_fb) {
7284                 drm_gem_object_unreference_unlocked(&obj->base);
7285                 return ERR_PTR(-ENOMEM);
7286         }
7287
7288         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7289         if (ret) {
7290                 drm_gem_object_unreference_unlocked(&obj->base);
7291                 kfree(intel_fb);
7292                 return ERR_PTR(ret);
7293         }
7294
7295         return &intel_fb->base;
7296 }
7297
7298 static u32
7299 intel_framebuffer_pitch_for_width(int width, int bpp)
7300 {
7301         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7302         return ALIGN(pitch, 64);
7303 }
7304
7305 static u32
7306 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7307 {
7308         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7309         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7310 }
7311
7312 static struct drm_framebuffer *
7313 intel_framebuffer_create_for_mode(struct drm_device *dev,
7314                                   struct drm_display_mode *mode,
7315                                   int depth, int bpp)
7316 {
7317         struct drm_i915_gem_object *obj;
7318         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7319
7320         obj = i915_gem_alloc_object(dev,
7321                                     intel_framebuffer_size_for_mode(mode, bpp));
7322         if (obj == NULL)
7323                 return ERR_PTR(-ENOMEM);
7324
7325         mode_cmd.width = mode->hdisplay;
7326         mode_cmd.height = mode->vdisplay;
7327         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7328                                                                 bpp);
7329         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7330
7331         return intel_framebuffer_create(dev, &mode_cmd, obj);
7332 }
7333
7334 static struct drm_framebuffer *
7335 mode_fits_in_fbdev(struct drm_device *dev,
7336                    struct drm_display_mode *mode)
7337 {
7338 #ifdef CONFIG_DRM_I915_FBDEV
7339         struct drm_i915_private *dev_priv = dev->dev_private;
7340         struct drm_i915_gem_object *obj;
7341         struct drm_framebuffer *fb;
7342
7343         if (dev_priv->fbdev == NULL)
7344                 return NULL;
7345
7346         obj = dev_priv->fbdev->ifb.obj;
7347         if (obj == NULL)
7348                 return NULL;
7349
7350         fb = &dev_priv->fbdev->ifb.base;
7351         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7352                                                                fb->bits_per_pixel))
7353                 return NULL;
7354
7355         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7356                 return NULL;
7357
7358         return fb;
7359 #else
7360         return NULL;
7361 #endif
7362 }
7363
7364 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7365                                 struct drm_display_mode *mode,
7366                                 struct intel_load_detect_pipe *old)
7367 {
7368         struct intel_crtc *intel_crtc;
7369         struct intel_encoder *intel_encoder =
7370                 intel_attached_encoder(connector);
7371         struct drm_crtc *possible_crtc;
7372         struct drm_encoder *encoder = &intel_encoder->base;
7373         struct drm_crtc *crtc = NULL;
7374         struct drm_device *dev = encoder->dev;
7375         struct drm_framebuffer *fb;
7376         int i = -1;
7377
7378         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7379                       connector->base.id, drm_get_connector_name(connector),
7380                       encoder->base.id, drm_get_encoder_name(encoder));
7381
7382         /*
7383          * Algorithm gets a little messy:
7384          *
7385          *   - if the connector already has an assigned crtc, use it (but make
7386          *     sure it's on first)
7387          *
7388          *   - try to find the first unused crtc that can drive this connector,
7389          *     and use that if we find one
7390          */
7391
7392         /* See if we already have a CRTC for this connector */
7393         if (encoder->crtc) {
7394                 crtc = encoder->crtc;
7395
7396                 mutex_lock(&crtc->mutex);
7397
7398                 old->dpms_mode = connector->dpms;
7399                 old->load_detect_temp = false;
7400
7401                 /* Make sure the crtc and connector are running */
7402                 if (connector->dpms != DRM_MODE_DPMS_ON)
7403                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7404
7405                 return true;
7406         }
7407
7408         /* Find an unused one (if possible) */
7409         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7410                 i++;
7411                 if (!(encoder->possible_crtcs & (1 << i)))
7412                         continue;
7413                 if (!possible_crtc->enabled) {
7414                         crtc = possible_crtc;
7415                         break;
7416                 }
7417         }
7418
7419         /*
7420          * If we didn't find an unused CRTC, don't use any.
7421          */
7422         if (!crtc) {
7423                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7424                 return false;
7425         }
7426
7427         mutex_lock(&crtc->mutex);
7428         intel_encoder->new_crtc = to_intel_crtc(crtc);
7429         to_intel_connector(connector)->new_encoder = intel_encoder;
7430
7431         intel_crtc = to_intel_crtc(crtc);
7432         old->dpms_mode = connector->dpms;
7433         old->load_detect_temp = true;
7434         old->release_fb = NULL;
7435
7436         if (!mode)
7437                 mode = &load_detect_mode;
7438
7439         /* We need a framebuffer large enough to accommodate all accesses
7440          * that the plane may generate whilst we perform load detection.
7441          * We can not rely on the fbcon either being present (we get called
7442          * during its initialisation to detect all boot displays, or it may
7443          * not even exist) or that it is large enough to satisfy the
7444          * requested mode.
7445          */
7446         fb = mode_fits_in_fbdev(dev, mode);
7447         if (fb == NULL) {
7448                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7449                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7450                 old->release_fb = fb;
7451         } else
7452                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7453         if (IS_ERR(fb)) {
7454                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7455                 mutex_unlock(&crtc->mutex);
7456                 return false;
7457         }
7458
7459         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7460                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7461                 if (old->release_fb)
7462                         old->release_fb->funcs->destroy(old->release_fb);
7463                 mutex_unlock(&crtc->mutex);
7464                 return false;
7465         }
7466
7467         /* let the connector get through one full cycle before testing */
7468         intel_wait_for_vblank(dev, intel_crtc->pipe);
7469         return true;
7470 }
7471
7472 void intel_release_load_detect_pipe(struct drm_connector *connector,
7473                                     struct intel_load_detect_pipe *old)
7474 {
7475         struct intel_encoder *intel_encoder =
7476                 intel_attached_encoder(connector);
7477         struct drm_encoder *encoder = &intel_encoder->base;
7478         struct drm_crtc *crtc = encoder->crtc;
7479
7480         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7481                       connector->base.id, drm_get_connector_name(connector),
7482                       encoder->base.id, drm_get_encoder_name(encoder));
7483
7484         if (old->load_detect_temp) {
7485                 to_intel_connector(connector)->new_encoder = NULL;
7486                 intel_encoder->new_crtc = NULL;
7487                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7488
7489                 if (old->release_fb) {
7490                         drm_framebuffer_unregister_private(old->release_fb);
7491                         drm_framebuffer_unreference(old->release_fb);
7492                 }
7493
7494                 mutex_unlock(&crtc->mutex);
7495                 return;
7496         }
7497
7498         /* Switch crtc and encoder back off if necessary */
7499         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7500                 connector->funcs->dpms(connector, old->dpms_mode);
7501
7502         mutex_unlock(&crtc->mutex);
7503 }
7504
7505 static int i9xx_pll_refclk(struct drm_device *dev,
7506                            const struct intel_crtc_config *pipe_config)
7507 {
7508         struct drm_i915_private *dev_priv = dev->dev_private;
7509         u32 dpll = pipe_config->dpll_hw_state.dpll;
7510
7511         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7512                 return dev_priv->vbt.lvds_ssc_freq * 1000;
7513         else if (HAS_PCH_SPLIT(dev))
7514                 return 120000;
7515         else if (!IS_GEN2(dev))
7516                 return 96000;
7517         else
7518                 return 48000;
7519 }
7520
7521 /* Returns the clock of the currently programmed mode of the given pipe. */
7522 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7523                                 struct intel_crtc_config *pipe_config)
7524 {
7525         struct drm_device *dev = crtc->base.dev;
7526         struct drm_i915_private *dev_priv = dev->dev_private;
7527         int pipe = pipe_config->cpu_transcoder;
7528         u32 dpll = pipe_config->dpll_hw_state.dpll;
7529         u32 fp;
7530         intel_clock_t clock;
7531         int refclk = i9xx_pll_refclk(dev, pipe_config);
7532
7533         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7534                 fp = pipe_config->dpll_hw_state.fp0;
7535         else
7536                 fp = pipe_config->dpll_hw_state.fp1;
7537
7538         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7539         if (IS_PINEVIEW(dev)) {
7540                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7541                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7542         } else {
7543                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7544                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7545         }
7546
7547         if (!IS_GEN2(dev)) {
7548                 if (IS_PINEVIEW(dev))
7549                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7550                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7551                 else
7552                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7553                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7554
7555                 switch (dpll & DPLL_MODE_MASK) {
7556                 case DPLLB_MODE_DAC_SERIAL:
7557                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7558                                 5 : 10;
7559                         break;
7560                 case DPLLB_MODE_LVDS:
7561                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7562                                 7 : 14;
7563                         break;
7564                 default:
7565                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7566                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7567                         return;
7568                 }
7569
7570                 if (IS_PINEVIEW(dev))
7571                         pineview_clock(refclk, &clock);
7572                 else
7573                         i9xx_clock(refclk, &clock);
7574         } else {
7575                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7576
7577                 if (is_lvds) {
7578                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7579                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7580                         clock.p2 = 14;
7581                 } else {
7582                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7583                                 clock.p1 = 2;
7584                         else {
7585                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7586                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7587                         }
7588                         if (dpll & PLL_P2_DIVIDE_BY_4)
7589                                 clock.p2 = 4;
7590                         else
7591                                 clock.p2 = 2;
7592                 }
7593
7594                 i9xx_clock(refclk, &clock);
7595         }
7596
7597         /*
7598          * This value includes pixel_multiplier. We will use
7599          * port_clock to compute adjusted_mode.crtc_clock in the
7600          * encoder's get_config() function.
7601          */
7602         pipe_config->port_clock = clock.dot;
7603 }
7604
7605 int intel_dotclock_calculate(int link_freq,
7606                              const struct intel_link_m_n *m_n)
7607 {
7608         /*
7609          * The calculation for the data clock is:
7610          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7611          * But we want to avoid losing precison if possible, so:
7612          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7613          *
7614          * and the link clock is simpler:
7615          * link_clock = (m * link_clock) / n
7616          */
7617
7618         if (!m_n->link_n)
7619                 return 0;
7620
7621         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7622 }
7623
7624 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7625                                    struct intel_crtc_config *pipe_config)
7626 {
7627         struct drm_device *dev = crtc->base.dev;
7628
7629         /* read out port_clock from the DPLL */
7630         i9xx_crtc_clock_get(crtc, pipe_config);
7631
7632         /*
7633          * This value does not include pixel_multiplier.
7634          * We will check that port_clock and adjusted_mode.crtc_clock
7635          * agree once we know their relationship in the encoder's
7636          * get_config() function.
7637          */
7638         pipe_config->adjusted_mode.crtc_clock =
7639                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7640                                          &pipe_config->fdi_m_n);
7641 }
7642
7643 /** Returns the currently programmed mode of the given pipe. */
7644 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7645                                              struct drm_crtc *crtc)
7646 {
7647         struct drm_i915_private *dev_priv = dev->dev_private;
7648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7649         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7650         struct drm_display_mode *mode;
7651         struct intel_crtc_config pipe_config;
7652         int htot = I915_READ(HTOTAL(cpu_transcoder));
7653         int hsync = I915_READ(HSYNC(cpu_transcoder));
7654         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7655         int vsync = I915_READ(VSYNC(cpu_transcoder));
7656         enum pipe pipe = intel_crtc->pipe;
7657
7658         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7659         if (!mode)
7660                 return NULL;
7661
7662         /*
7663          * Construct a pipe_config sufficient for getting the clock info
7664          * back out of crtc_clock_get.
7665          *
7666          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7667          * to use a real value here instead.
7668          */
7669         pipe_config.cpu_transcoder = (enum transcoder) pipe;
7670         pipe_config.pixel_multiplier = 1;
7671         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7672         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7673         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7674         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7675
7676         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
7677         mode->hdisplay = (htot & 0xffff) + 1;
7678         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7679         mode->hsync_start = (hsync & 0xffff) + 1;
7680         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7681         mode->vdisplay = (vtot & 0xffff) + 1;
7682         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7683         mode->vsync_start = (vsync & 0xffff) + 1;
7684         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7685
7686         drm_mode_set_name(mode);
7687
7688         return mode;
7689 }
7690
7691 static void intel_increase_pllclock(struct drm_crtc *crtc)
7692 {
7693         struct drm_device *dev = crtc->dev;
7694         drm_i915_private_t *dev_priv = dev->dev_private;
7695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7696         int pipe = intel_crtc->pipe;
7697         int dpll_reg = DPLL(pipe);
7698         int dpll;
7699
7700         if (HAS_PCH_SPLIT(dev))
7701                 return;
7702
7703         if (!dev_priv->lvds_downclock_avail)
7704                 return;
7705
7706         dpll = I915_READ(dpll_reg);
7707         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7708                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7709
7710                 assert_panel_unlocked(dev_priv, pipe);
7711
7712                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7713                 I915_WRITE(dpll_reg, dpll);
7714                 intel_wait_for_vblank(dev, pipe);
7715
7716                 dpll = I915_READ(dpll_reg);
7717                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7718                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7719         }
7720 }
7721
7722 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7723 {
7724         struct drm_device *dev = crtc->dev;
7725         drm_i915_private_t *dev_priv = dev->dev_private;
7726         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7727
7728         if (HAS_PCH_SPLIT(dev))
7729                 return;
7730
7731         if (!dev_priv->lvds_downclock_avail)
7732                 return;
7733
7734         /*
7735          * Since this is called by a timer, we should never get here in
7736          * the manual case.
7737          */
7738         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7739                 int pipe = intel_crtc->pipe;
7740                 int dpll_reg = DPLL(pipe);
7741                 int dpll;
7742
7743                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7744
7745                 assert_panel_unlocked(dev_priv, pipe);
7746
7747                 dpll = I915_READ(dpll_reg);
7748                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7749                 I915_WRITE(dpll_reg, dpll);
7750                 intel_wait_for_vblank(dev, pipe);
7751                 dpll = I915_READ(dpll_reg);
7752                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7753                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7754         }
7755
7756 }
7757
7758 void intel_mark_busy(struct drm_device *dev)
7759 {
7760         struct drm_i915_private *dev_priv = dev->dev_private;
7761
7762         hsw_package_c8_gpu_busy(dev_priv);
7763         i915_update_gfx_val(dev_priv);
7764 }
7765
7766 void intel_mark_idle(struct drm_device *dev)
7767 {
7768         struct drm_i915_private *dev_priv = dev->dev_private;
7769         struct drm_crtc *crtc;
7770
7771         hsw_package_c8_gpu_idle(dev_priv);
7772
7773         if (!i915_powersave)
7774                 return;
7775
7776         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7777                 if (!crtc->fb)
7778                         continue;
7779
7780                 intel_decrease_pllclock(crtc);
7781         }
7782
7783         if (dev_priv->info->gen >= 6)
7784                 gen6_rps_idle(dev->dev_private);
7785 }
7786
7787 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7788                         struct intel_ring_buffer *ring)
7789 {
7790         struct drm_device *dev = obj->base.dev;
7791         struct drm_crtc *crtc;
7792
7793         if (!i915_powersave)
7794                 return;
7795
7796         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7797                 if (!crtc->fb)
7798                         continue;
7799
7800                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7801                         continue;
7802
7803                 intel_increase_pllclock(crtc);
7804                 if (ring && intel_fbc_enabled(dev))
7805                         ring->fbc_dirty = true;
7806         }
7807 }
7808
7809 static void intel_crtc_destroy(struct drm_crtc *crtc)
7810 {
7811         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7812         struct drm_device *dev = crtc->dev;
7813         struct intel_unpin_work *work;
7814         unsigned long flags;
7815
7816         spin_lock_irqsave(&dev->event_lock, flags);
7817         work = intel_crtc->unpin_work;
7818         intel_crtc->unpin_work = NULL;
7819         spin_unlock_irqrestore(&dev->event_lock, flags);
7820
7821         if (work) {
7822                 cancel_work_sync(&work->work);
7823                 kfree(work);
7824         }
7825
7826         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7827
7828         drm_crtc_cleanup(crtc);
7829
7830         kfree(intel_crtc);
7831 }
7832
7833 static void intel_unpin_work_fn(struct work_struct *__work)
7834 {
7835         struct intel_unpin_work *work =
7836                 container_of(__work, struct intel_unpin_work, work);
7837         struct drm_device *dev = work->crtc->dev;
7838
7839         mutex_lock(&dev->struct_mutex);
7840         intel_unpin_fb_obj(work->old_fb_obj);
7841         drm_gem_object_unreference(&work->pending_flip_obj->base);
7842         drm_gem_object_unreference(&work->old_fb_obj->base);
7843
7844         intel_update_fbc(dev);
7845         mutex_unlock(&dev->struct_mutex);
7846
7847         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7848         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7849
7850         kfree(work);
7851 }
7852
7853 static void do_intel_finish_page_flip(struct drm_device *dev,
7854                                       struct drm_crtc *crtc)
7855 {
7856         drm_i915_private_t *dev_priv = dev->dev_private;
7857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7858         struct intel_unpin_work *work;
7859         unsigned long flags;
7860
7861         /* Ignore early vblank irqs */
7862         if (intel_crtc == NULL)
7863                 return;
7864
7865         spin_lock_irqsave(&dev->event_lock, flags);
7866         work = intel_crtc->unpin_work;
7867
7868         /* Ensure we don't miss a work->pending update ... */
7869         smp_rmb();
7870
7871         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7872                 spin_unlock_irqrestore(&dev->event_lock, flags);
7873                 return;
7874         }
7875
7876         /* and that the unpin work is consistent wrt ->pending. */
7877         smp_rmb();
7878
7879         intel_crtc->unpin_work = NULL;
7880
7881         if (work->event)
7882                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7883
7884         drm_vblank_put(dev, intel_crtc->pipe);
7885
7886         spin_unlock_irqrestore(&dev->event_lock, flags);
7887
7888         wake_up_all(&dev_priv->pending_flip_queue);
7889
7890         queue_work(dev_priv->wq, &work->work);
7891
7892         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7893 }
7894
7895 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7896 {
7897         drm_i915_private_t *dev_priv = dev->dev_private;
7898         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7899
7900         do_intel_finish_page_flip(dev, crtc);
7901 }
7902
7903 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7904 {
7905         drm_i915_private_t *dev_priv = dev->dev_private;
7906         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7907
7908         do_intel_finish_page_flip(dev, crtc);
7909 }
7910
7911 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7912 {
7913         drm_i915_private_t *dev_priv = dev->dev_private;
7914         struct intel_crtc *intel_crtc =
7915                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7916         unsigned long flags;
7917
7918         /* NB: An MMIO update of the plane base pointer will also
7919          * generate a page-flip completion irq, i.e. every modeset
7920          * is also accompanied by a spurious intel_prepare_page_flip().
7921          */
7922         spin_lock_irqsave(&dev->event_lock, flags);
7923         if (intel_crtc->unpin_work)
7924                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7925         spin_unlock_irqrestore(&dev->event_lock, flags);
7926 }
7927
7928 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7929 {
7930         /* Ensure that the work item is consistent when activating it ... */
7931         smp_wmb();
7932         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7933         /* and that it is marked active as soon as the irq could fire. */
7934         smp_wmb();
7935 }
7936
7937 static int intel_gen2_queue_flip(struct drm_device *dev,
7938                                  struct drm_crtc *crtc,
7939                                  struct drm_framebuffer *fb,
7940                                  struct drm_i915_gem_object *obj,
7941                                  uint32_t flags)
7942 {
7943         struct drm_i915_private *dev_priv = dev->dev_private;
7944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7945         u32 flip_mask;
7946         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7947         int ret;
7948
7949         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7950         if (ret)
7951                 goto err;
7952
7953         ret = intel_ring_begin(ring, 6);
7954         if (ret)
7955                 goto err_unpin;
7956
7957         /* Can't queue multiple flips, so wait for the previous
7958          * one to finish before executing the next.
7959          */
7960         if (intel_crtc->plane)
7961                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7962         else
7963                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7964         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7965         intel_ring_emit(ring, MI_NOOP);
7966         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7967                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7968         intel_ring_emit(ring, fb->pitches[0]);
7969         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7970         intel_ring_emit(ring, 0); /* aux display base address, unused */
7971
7972         intel_mark_page_flip_active(intel_crtc);
7973         __intel_ring_advance(ring);
7974         return 0;
7975
7976 err_unpin:
7977         intel_unpin_fb_obj(obj);
7978 err:
7979         return ret;
7980 }
7981
7982 static int intel_gen3_queue_flip(struct drm_device *dev,
7983                                  struct drm_crtc *crtc,
7984                                  struct drm_framebuffer *fb,
7985                                  struct drm_i915_gem_object *obj,
7986                                  uint32_t flags)
7987 {
7988         struct drm_i915_private *dev_priv = dev->dev_private;
7989         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7990         u32 flip_mask;
7991         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7992         int ret;
7993
7994         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7995         if (ret)
7996                 goto err;
7997
7998         ret = intel_ring_begin(ring, 6);
7999         if (ret)
8000                 goto err_unpin;
8001
8002         if (intel_crtc->plane)
8003                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8004         else
8005                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8006         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8007         intel_ring_emit(ring, MI_NOOP);
8008         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8009                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8010         intel_ring_emit(ring, fb->pitches[0]);
8011         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8012         intel_ring_emit(ring, MI_NOOP);
8013
8014         intel_mark_page_flip_active(intel_crtc);
8015         __intel_ring_advance(ring);
8016         return 0;
8017
8018 err_unpin:
8019         intel_unpin_fb_obj(obj);
8020 err:
8021         return ret;
8022 }
8023
8024 static int intel_gen4_queue_flip(struct drm_device *dev,
8025                                  struct drm_crtc *crtc,
8026                                  struct drm_framebuffer *fb,
8027                                  struct drm_i915_gem_object *obj,
8028                                  uint32_t flags)
8029 {
8030         struct drm_i915_private *dev_priv = dev->dev_private;
8031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8032         uint32_t pf, pipesrc;
8033         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8034         int ret;
8035
8036         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8037         if (ret)
8038                 goto err;
8039
8040         ret = intel_ring_begin(ring, 4);
8041         if (ret)
8042                 goto err_unpin;
8043
8044         /* i965+ uses the linear or tiled offsets from the
8045          * Display Registers (which do not change across a page-flip)
8046          * so we need only reprogram the base address.
8047          */
8048         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8049                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8050         intel_ring_emit(ring, fb->pitches[0]);
8051         intel_ring_emit(ring,
8052                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8053                         obj->tiling_mode);
8054
8055         /* XXX Enabling the panel-fitter across page-flip is so far
8056          * untested on non-native modes, so ignore it for now.
8057          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8058          */
8059         pf = 0;
8060         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8061         intel_ring_emit(ring, pf | pipesrc);
8062
8063         intel_mark_page_flip_active(intel_crtc);
8064         __intel_ring_advance(ring);
8065         return 0;
8066
8067 err_unpin:
8068         intel_unpin_fb_obj(obj);
8069 err:
8070         return ret;
8071 }
8072
8073 static int intel_gen6_queue_flip(struct drm_device *dev,
8074                                  struct drm_crtc *crtc,
8075                                  struct drm_framebuffer *fb,
8076                                  struct drm_i915_gem_object *obj,
8077                                  uint32_t flags)
8078 {
8079         struct drm_i915_private *dev_priv = dev->dev_private;
8080         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8081         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8082         uint32_t pf, pipesrc;
8083         int ret;
8084
8085         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8086         if (ret)
8087                 goto err;
8088
8089         ret = intel_ring_begin(ring, 4);
8090         if (ret)
8091                 goto err_unpin;
8092
8093         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8094                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8095         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8096         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8097
8098         /* Contrary to the suggestions in the documentation,
8099          * "Enable Panel Fitter" does not seem to be required when page
8100          * flipping with a non-native mode, and worse causes a normal
8101          * modeset to fail.
8102          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8103          */
8104         pf = 0;
8105         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8106         intel_ring_emit(ring, pf | pipesrc);
8107
8108         intel_mark_page_flip_active(intel_crtc);
8109         __intel_ring_advance(ring);
8110         return 0;
8111
8112 err_unpin:
8113         intel_unpin_fb_obj(obj);
8114 err:
8115         return ret;
8116 }
8117
8118 static int intel_gen7_queue_flip(struct drm_device *dev,
8119                                  struct drm_crtc *crtc,
8120                                  struct drm_framebuffer *fb,
8121                                  struct drm_i915_gem_object *obj,
8122                                  uint32_t flags)
8123 {
8124         struct drm_i915_private *dev_priv = dev->dev_private;
8125         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8126         struct intel_ring_buffer *ring;
8127         uint32_t plane_bit = 0;
8128         int len, ret;
8129
8130         ring = obj->ring;
8131         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8132                 ring = &dev_priv->ring[BCS];
8133
8134         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8135         if (ret)
8136                 goto err;
8137
8138         switch(intel_crtc->plane) {
8139         case PLANE_A:
8140                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8141                 break;
8142         case PLANE_B:
8143                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8144                 break;
8145         case PLANE_C:
8146                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8147                 break;
8148         default:
8149                 WARN_ONCE(1, "unknown plane in flip command\n");
8150                 ret = -ENODEV;
8151                 goto err_unpin;
8152         }
8153
8154         len = 4;
8155         if (ring->id == RCS)
8156                 len += 6;
8157
8158         ret = intel_ring_begin(ring, len);
8159         if (ret)
8160                 goto err_unpin;
8161
8162         /* Unmask the flip-done completion message. Note that the bspec says that
8163          * we should do this for both the BCS and RCS, and that we must not unmask
8164          * more than one flip event at any time (or ensure that one flip message
8165          * can be sent by waiting for flip-done prior to queueing new flips).
8166          * Experimentation says that BCS works despite DERRMR masking all
8167          * flip-done completion events and that unmasking all planes at once
8168          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8169          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8170          */
8171         if (ring->id == RCS) {
8172                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8173                 intel_ring_emit(ring, DERRMR);
8174                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8175                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8176                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8177                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8178                 intel_ring_emit(ring, DERRMR);
8179                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8180         }
8181
8182         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8183         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8184         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8185         intel_ring_emit(ring, (MI_NOOP));
8186
8187         intel_mark_page_flip_active(intel_crtc);
8188         __intel_ring_advance(ring);
8189         return 0;
8190
8191 err_unpin:
8192         intel_unpin_fb_obj(obj);
8193 err:
8194         return ret;
8195 }
8196
8197 static int intel_default_queue_flip(struct drm_device *dev,
8198                                     struct drm_crtc *crtc,
8199                                     struct drm_framebuffer *fb,
8200                                     struct drm_i915_gem_object *obj,
8201                                     uint32_t flags)
8202 {
8203         return -ENODEV;
8204 }
8205
8206 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8207                                 struct drm_framebuffer *fb,
8208                                 struct drm_pending_vblank_event *event,
8209                                 uint32_t page_flip_flags)
8210 {
8211         struct drm_device *dev = crtc->dev;
8212         struct drm_i915_private *dev_priv = dev->dev_private;
8213         struct drm_framebuffer *old_fb = crtc->fb;
8214         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8216         struct intel_unpin_work *work;
8217         unsigned long flags;
8218         int ret;
8219
8220         /* Can't change pixel format via MI display flips. */
8221         if (fb->pixel_format != crtc->fb->pixel_format)
8222                 return -EINVAL;
8223
8224         /*
8225          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8226          * Note that pitch changes could also affect these register.
8227          */
8228         if (INTEL_INFO(dev)->gen > 3 &&
8229             (fb->offsets[0] != crtc->fb->offsets[0] ||
8230              fb->pitches[0] != crtc->fb->pitches[0]))
8231                 return -EINVAL;
8232
8233         work = kzalloc(sizeof(*work), GFP_KERNEL);
8234         if (work == NULL)
8235                 return -ENOMEM;
8236
8237         work->event = event;
8238         work->crtc = crtc;
8239         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8240         INIT_WORK(&work->work, intel_unpin_work_fn);
8241
8242         ret = drm_vblank_get(dev, intel_crtc->pipe);
8243         if (ret)
8244                 goto free_work;
8245
8246         /* We borrow the event spin lock for protecting unpin_work */
8247         spin_lock_irqsave(&dev->event_lock, flags);
8248         if (intel_crtc->unpin_work) {
8249                 spin_unlock_irqrestore(&dev->event_lock, flags);
8250                 kfree(work);
8251                 drm_vblank_put(dev, intel_crtc->pipe);
8252
8253                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8254                 return -EBUSY;
8255         }
8256         intel_crtc->unpin_work = work;
8257         spin_unlock_irqrestore(&dev->event_lock, flags);
8258
8259         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8260                 flush_workqueue(dev_priv->wq);
8261
8262         ret = i915_mutex_lock_interruptible(dev);
8263         if (ret)
8264                 goto cleanup;
8265
8266         /* Reference the objects for the scheduled work. */
8267         drm_gem_object_reference(&work->old_fb_obj->base);
8268         drm_gem_object_reference(&obj->base);
8269
8270         crtc->fb = fb;
8271
8272         work->pending_flip_obj = obj;
8273
8274         work->enable_stall_check = true;
8275
8276         atomic_inc(&intel_crtc->unpin_work_count);
8277         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8278
8279         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8280         if (ret)
8281                 goto cleanup_pending;
8282
8283         intel_disable_fbc(dev);
8284         intel_mark_fb_busy(obj, NULL);
8285         mutex_unlock(&dev->struct_mutex);
8286
8287         trace_i915_flip_request(intel_crtc->plane, obj);
8288
8289         return 0;
8290
8291 cleanup_pending:
8292         atomic_dec(&intel_crtc->unpin_work_count);
8293         crtc->fb = old_fb;
8294         drm_gem_object_unreference(&work->old_fb_obj->base);
8295         drm_gem_object_unreference(&obj->base);
8296         mutex_unlock(&dev->struct_mutex);
8297
8298 cleanup:
8299         spin_lock_irqsave(&dev->event_lock, flags);
8300         intel_crtc->unpin_work = NULL;
8301         spin_unlock_irqrestore(&dev->event_lock, flags);
8302
8303         drm_vblank_put(dev, intel_crtc->pipe);
8304 free_work:
8305         kfree(work);
8306
8307         return ret;
8308 }
8309
8310 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8311         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8312         .load_lut = intel_crtc_load_lut,
8313 };
8314
8315 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8316                                   struct drm_crtc *crtc)
8317 {
8318         struct drm_device *dev;
8319         struct drm_crtc *tmp;
8320         int crtc_mask = 1;
8321
8322         WARN(!crtc, "checking null crtc?\n");
8323
8324         dev = crtc->dev;
8325
8326         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8327                 if (tmp == crtc)
8328                         break;
8329                 crtc_mask <<= 1;
8330         }
8331
8332         if (encoder->possible_crtcs & crtc_mask)
8333                 return true;
8334         return false;
8335 }
8336
8337 /**
8338  * intel_modeset_update_staged_output_state
8339  *
8340  * Updates the staged output configuration state, e.g. after we've read out the
8341  * current hw state.
8342  */
8343 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8344 {
8345         struct intel_encoder *encoder;
8346         struct intel_connector *connector;
8347
8348         list_for_each_entry(connector, &dev->mode_config.connector_list,
8349                             base.head) {
8350                 connector->new_encoder =
8351                         to_intel_encoder(connector->base.encoder);
8352         }
8353
8354         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8355                             base.head) {
8356                 encoder->new_crtc =
8357                         to_intel_crtc(encoder->base.crtc);
8358         }
8359 }
8360
8361 /**
8362  * intel_modeset_commit_output_state
8363  *
8364  * This function copies the stage display pipe configuration to the real one.
8365  */
8366 static void intel_modeset_commit_output_state(struct drm_device *dev)
8367 {
8368         struct intel_encoder *encoder;
8369         struct intel_connector *connector;
8370
8371         list_for_each_entry(connector, &dev->mode_config.connector_list,
8372                             base.head) {
8373                 connector->base.encoder = &connector->new_encoder->base;
8374         }
8375
8376         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8377                             base.head) {
8378                 encoder->base.crtc = &encoder->new_crtc->base;
8379         }
8380 }
8381
8382 static void
8383 connected_sink_compute_bpp(struct intel_connector * connector,
8384                            struct intel_crtc_config *pipe_config)
8385 {
8386         int bpp = pipe_config->pipe_bpp;
8387
8388         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8389                 connector->base.base.id,
8390                 drm_get_connector_name(&connector->base));
8391
8392         /* Don't use an invalid EDID bpc value */
8393         if (connector->base.display_info.bpc &&
8394             connector->base.display_info.bpc * 3 < bpp) {
8395                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8396                               bpp, connector->base.display_info.bpc*3);
8397                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8398         }
8399
8400         /* Clamp bpp to 8 on screens without EDID 1.4 */
8401         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8402                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8403                               bpp);
8404                 pipe_config->pipe_bpp = 24;
8405         }
8406 }
8407
8408 static int
8409 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8410                           struct drm_framebuffer *fb,
8411                           struct intel_crtc_config *pipe_config)
8412 {
8413         struct drm_device *dev = crtc->base.dev;
8414         struct intel_connector *connector;
8415         int bpp;
8416
8417         switch (fb->pixel_format) {
8418         case DRM_FORMAT_C8:
8419                 bpp = 8*3; /* since we go through a colormap */
8420                 break;
8421         case DRM_FORMAT_XRGB1555:
8422         case DRM_FORMAT_ARGB1555:
8423                 /* checked in intel_framebuffer_init already */
8424                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8425                         return -EINVAL;
8426         case DRM_FORMAT_RGB565:
8427                 bpp = 6*3; /* min is 18bpp */
8428                 break;
8429         case DRM_FORMAT_XBGR8888:
8430         case DRM_FORMAT_ABGR8888:
8431                 /* checked in intel_framebuffer_init already */
8432                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8433                         return -EINVAL;
8434         case DRM_FORMAT_XRGB8888:
8435         case DRM_FORMAT_ARGB8888:
8436                 bpp = 8*3;
8437                 break;
8438         case DRM_FORMAT_XRGB2101010:
8439         case DRM_FORMAT_ARGB2101010:
8440         case DRM_FORMAT_XBGR2101010:
8441         case DRM_FORMAT_ABGR2101010:
8442                 /* checked in intel_framebuffer_init already */
8443                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8444                         return -EINVAL;
8445                 bpp = 10*3;
8446                 break;
8447         /* TODO: gen4+ supports 16 bpc floating point, too. */
8448         default:
8449                 DRM_DEBUG_KMS("unsupported depth\n");
8450                 return -EINVAL;
8451         }
8452
8453         pipe_config->pipe_bpp = bpp;
8454
8455         /* Clamp display bpp to EDID value */
8456         list_for_each_entry(connector, &dev->mode_config.connector_list,
8457                             base.head) {
8458                 if (!connector->new_encoder ||
8459                     connector->new_encoder->new_crtc != crtc)
8460                         continue;
8461
8462                 connected_sink_compute_bpp(connector, pipe_config);
8463         }
8464
8465         return bpp;
8466 }
8467
8468 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8469 {
8470         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8471                         "type: 0x%x flags: 0x%x\n",
8472                 mode->crtc_clock,
8473                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8474                 mode->crtc_hsync_end, mode->crtc_htotal,
8475                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8476                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8477 }
8478
8479 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8480                                    struct intel_crtc_config *pipe_config,
8481                                    const char *context)
8482 {
8483         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8484                       context, pipe_name(crtc->pipe));
8485
8486         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8487         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8488                       pipe_config->pipe_bpp, pipe_config->dither);
8489         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8490                       pipe_config->has_pch_encoder,
8491                       pipe_config->fdi_lanes,
8492                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8493                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8494                       pipe_config->fdi_m_n.tu);
8495         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8496                       pipe_config->has_dp_encoder,
8497                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8498                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8499                       pipe_config->dp_m_n.tu);
8500         DRM_DEBUG_KMS("requested mode:\n");
8501         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8502         DRM_DEBUG_KMS("adjusted mode:\n");
8503         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8504         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8505         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8506         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8507                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8508         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8509                       pipe_config->gmch_pfit.control,
8510                       pipe_config->gmch_pfit.pgm_ratios,
8511                       pipe_config->gmch_pfit.lvds_border_bits);
8512         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8513                       pipe_config->pch_pfit.pos,
8514                       pipe_config->pch_pfit.size,
8515                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8516         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8517         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8518 }
8519
8520 static bool check_encoder_cloning(struct drm_crtc *crtc)
8521 {
8522         int num_encoders = 0;
8523         bool uncloneable_encoders = false;
8524         struct intel_encoder *encoder;
8525
8526         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8527                             base.head) {
8528                 if (&encoder->new_crtc->base != crtc)
8529                         continue;
8530
8531                 num_encoders++;
8532                 if (!encoder->cloneable)
8533                         uncloneable_encoders = true;
8534         }
8535
8536         return !(num_encoders > 1 && uncloneable_encoders);
8537 }
8538
8539 static struct intel_crtc_config *
8540 intel_modeset_pipe_config(struct drm_crtc *crtc,
8541                           struct drm_framebuffer *fb,
8542                           struct drm_display_mode *mode)
8543 {
8544         struct drm_device *dev = crtc->dev;
8545         struct intel_encoder *encoder;
8546         struct intel_crtc_config *pipe_config;
8547         int plane_bpp, ret = -EINVAL;
8548         bool retry = true;
8549
8550         if (!check_encoder_cloning(crtc)) {
8551                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8552                 return ERR_PTR(-EINVAL);
8553         }
8554
8555         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8556         if (!pipe_config)
8557                 return ERR_PTR(-ENOMEM);
8558
8559         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8560         drm_mode_copy(&pipe_config->requested_mode, mode);
8561
8562         pipe_config->cpu_transcoder =
8563                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8564         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8565
8566         /*
8567          * Sanitize sync polarity flags based on requested ones. If neither
8568          * positive or negative polarity is requested, treat this as meaning
8569          * negative polarity.
8570          */
8571         if (!(pipe_config->adjusted_mode.flags &
8572               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8573                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8574
8575         if (!(pipe_config->adjusted_mode.flags &
8576               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8577                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8578
8579         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8580          * plane pixel format and any sink constraints into account. Returns the
8581          * source plane bpp so that dithering can be selected on mismatches
8582          * after encoders and crtc also have had their say. */
8583         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8584                                               fb, pipe_config);
8585         if (plane_bpp < 0)
8586                 goto fail;
8587
8588         /*
8589          * Determine the real pipe dimensions. Note that stereo modes can
8590          * increase the actual pipe size due to the frame doubling and
8591          * insertion of additional space for blanks between the frame. This
8592          * is stored in the crtc timings. We use the requested mode to do this
8593          * computation to clearly distinguish it from the adjusted mode, which
8594          * can be changed by the connectors in the below retry loop.
8595          */
8596         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8597         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8598         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8599
8600 encoder_retry:
8601         /* Ensure the port clock defaults are reset when retrying. */
8602         pipe_config->port_clock = 0;
8603         pipe_config->pixel_multiplier = 1;
8604
8605         /* Fill in default crtc timings, allow encoders to overwrite them. */
8606         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
8607
8608         /* Pass our mode to the connectors and the CRTC to give them a chance to
8609          * adjust it according to limitations or connector properties, and also
8610          * a chance to reject the mode entirely.
8611          */
8612         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8613                             base.head) {
8614
8615                 if (&encoder->new_crtc->base != crtc)
8616                         continue;
8617
8618                 if (!(encoder->compute_config(encoder, pipe_config))) {
8619                         DRM_DEBUG_KMS("Encoder config failure\n");
8620                         goto fail;
8621                 }
8622         }
8623
8624         /* Set default port clock if not overwritten by the encoder. Needs to be
8625          * done afterwards in case the encoder adjusts the mode. */
8626         if (!pipe_config->port_clock)
8627                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8628                         * pipe_config->pixel_multiplier;
8629
8630         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8631         if (ret < 0) {
8632                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8633                 goto fail;
8634         }
8635
8636         if (ret == RETRY) {
8637                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8638                         ret = -EINVAL;
8639                         goto fail;
8640                 }
8641
8642                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8643                 retry = false;
8644                 goto encoder_retry;
8645         }
8646
8647         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8648         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8649                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8650
8651         return pipe_config;
8652 fail:
8653         kfree(pipe_config);
8654         return ERR_PTR(ret);
8655 }
8656
8657 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8658  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8659 static void
8660 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8661                              unsigned *prepare_pipes, unsigned *disable_pipes)
8662 {
8663         struct intel_crtc *intel_crtc;
8664         struct drm_device *dev = crtc->dev;
8665         struct intel_encoder *encoder;
8666         struct intel_connector *connector;
8667         struct drm_crtc *tmp_crtc;
8668
8669         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8670
8671         /* Check which crtcs have changed outputs connected to them, these need
8672          * to be part of the prepare_pipes mask. We don't (yet) support global
8673          * modeset across multiple crtcs, so modeset_pipes will only have one
8674          * bit set at most. */
8675         list_for_each_entry(connector, &dev->mode_config.connector_list,
8676                             base.head) {
8677                 if (connector->base.encoder == &connector->new_encoder->base)
8678                         continue;
8679
8680                 if (connector->base.encoder) {
8681                         tmp_crtc = connector->base.encoder->crtc;
8682
8683                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8684                 }
8685
8686                 if (connector->new_encoder)
8687                         *prepare_pipes |=
8688                                 1 << connector->new_encoder->new_crtc->pipe;
8689         }
8690
8691         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8692                             base.head) {
8693                 if (encoder->base.crtc == &encoder->new_crtc->base)
8694                         continue;
8695
8696                 if (encoder->base.crtc) {
8697                         tmp_crtc = encoder->base.crtc;
8698
8699                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8700                 }
8701
8702                 if (encoder->new_crtc)
8703                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8704         }
8705
8706         /* Check for any pipes that will be fully disabled ... */
8707         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8708                             base.head) {
8709                 bool used = false;
8710
8711                 /* Don't try to disable disabled crtcs. */
8712                 if (!intel_crtc->base.enabled)
8713                         continue;
8714
8715                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8716                                     base.head) {
8717                         if (encoder->new_crtc == intel_crtc)
8718                                 used = true;
8719                 }
8720
8721                 if (!used)
8722                         *disable_pipes |= 1 << intel_crtc->pipe;
8723         }
8724
8725
8726         /* set_mode is also used to update properties on life display pipes. */
8727         intel_crtc = to_intel_crtc(crtc);
8728         if (crtc->enabled)
8729                 *prepare_pipes |= 1 << intel_crtc->pipe;
8730
8731         /*
8732          * For simplicity do a full modeset on any pipe where the output routing
8733          * changed. We could be more clever, but that would require us to be
8734          * more careful with calling the relevant encoder->mode_set functions.
8735          */
8736         if (*prepare_pipes)
8737                 *modeset_pipes = *prepare_pipes;
8738
8739         /* ... and mask these out. */
8740         *modeset_pipes &= ~(*disable_pipes);
8741         *prepare_pipes &= ~(*disable_pipes);
8742
8743         /*
8744          * HACK: We don't (yet) fully support global modesets. intel_set_config
8745          * obies this rule, but the modeset restore mode of
8746          * intel_modeset_setup_hw_state does not.
8747          */
8748         *modeset_pipes &= 1 << intel_crtc->pipe;
8749         *prepare_pipes &= 1 << intel_crtc->pipe;
8750
8751         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8752                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8753 }
8754
8755 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8756 {
8757         struct drm_encoder *encoder;
8758         struct drm_device *dev = crtc->dev;
8759
8760         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8761                 if (encoder->crtc == crtc)
8762                         return true;
8763
8764         return false;
8765 }
8766
8767 static void
8768 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8769 {
8770         struct intel_encoder *intel_encoder;
8771         struct intel_crtc *intel_crtc;
8772         struct drm_connector *connector;
8773
8774         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8775                             base.head) {
8776                 if (!intel_encoder->base.crtc)
8777                         continue;
8778
8779                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8780
8781                 if (prepare_pipes & (1 << intel_crtc->pipe))
8782                         intel_encoder->connectors_active = false;
8783         }
8784
8785         intel_modeset_commit_output_state(dev);
8786
8787         /* Update computed state. */
8788         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8789                             base.head) {
8790                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8791         }
8792
8793         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8794                 if (!connector->encoder || !connector->encoder->crtc)
8795                         continue;
8796
8797                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8798
8799                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8800                         struct drm_property *dpms_property =
8801                                 dev->mode_config.dpms_property;
8802
8803                         connector->dpms = DRM_MODE_DPMS_ON;
8804                         drm_object_property_set_value(&connector->base,
8805                                                          dpms_property,
8806                                                          DRM_MODE_DPMS_ON);
8807
8808                         intel_encoder = to_intel_encoder(connector->encoder);
8809                         intel_encoder->connectors_active = true;
8810                 }
8811         }
8812
8813 }
8814
8815 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8816 {
8817         int diff;
8818
8819         if (clock1 == clock2)
8820                 return true;
8821
8822         if (!clock1 || !clock2)
8823                 return false;
8824
8825         diff = abs(clock1 - clock2);
8826
8827         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8828                 return true;
8829
8830         return false;
8831 }
8832
8833 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8834         list_for_each_entry((intel_crtc), \
8835                             &(dev)->mode_config.crtc_list, \
8836                             base.head) \
8837                 if (mask & (1 <<(intel_crtc)->pipe))
8838
8839 static bool
8840 intel_pipe_config_compare(struct drm_device *dev,
8841                           struct intel_crtc_config *current_config,
8842                           struct intel_crtc_config *pipe_config)
8843 {
8844 #define PIPE_CONF_CHECK_X(name) \
8845         if (current_config->name != pipe_config->name) { \
8846                 DRM_ERROR("mismatch in " #name " " \
8847                           "(expected 0x%08x, found 0x%08x)\n", \
8848                           current_config->name, \
8849                           pipe_config->name); \
8850                 return false; \
8851         }
8852
8853 #define PIPE_CONF_CHECK_I(name) \
8854         if (current_config->name != pipe_config->name) { \
8855                 DRM_ERROR("mismatch in " #name " " \
8856                           "(expected %i, found %i)\n", \
8857                           current_config->name, \
8858                           pipe_config->name); \
8859                 return false; \
8860         }
8861
8862 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8863         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8864                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8865                           "(expected %i, found %i)\n", \
8866                           current_config->name & (mask), \
8867                           pipe_config->name & (mask)); \
8868                 return false; \
8869         }
8870
8871 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8872         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8873                 DRM_ERROR("mismatch in " #name " " \
8874                           "(expected %i, found %i)\n", \
8875                           current_config->name, \
8876                           pipe_config->name); \
8877                 return false; \
8878         }
8879
8880 #define PIPE_CONF_QUIRK(quirk)  \
8881         ((current_config->quirks | pipe_config->quirks) & (quirk))
8882
8883         PIPE_CONF_CHECK_I(cpu_transcoder);
8884
8885         PIPE_CONF_CHECK_I(has_pch_encoder);
8886         PIPE_CONF_CHECK_I(fdi_lanes);
8887         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8888         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8889         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8890         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8891         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8892
8893         PIPE_CONF_CHECK_I(has_dp_encoder);
8894         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8895         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8896         PIPE_CONF_CHECK_I(dp_m_n.link_m);
8897         PIPE_CONF_CHECK_I(dp_m_n.link_n);
8898         PIPE_CONF_CHECK_I(dp_m_n.tu);
8899
8900         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8901         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8902         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8903         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8904         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8905         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8906
8907         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8908         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8909         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8910         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8911         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8912         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8913
8914         PIPE_CONF_CHECK_I(pixel_multiplier);
8915
8916         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8917                               DRM_MODE_FLAG_INTERLACE);
8918
8919         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8920                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8921                                       DRM_MODE_FLAG_PHSYNC);
8922                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8923                                       DRM_MODE_FLAG_NHSYNC);
8924                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8925                                       DRM_MODE_FLAG_PVSYNC);
8926                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8927                                       DRM_MODE_FLAG_NVSYNC);
8928         }
8929
8930         PIPE_CONF_CHECK_I(pipe_src_w);
8931         PIPE_CONF_CHECK_I(pipe_src_h);
8932
8933         PIPE_CONF_CHECK_I(gmch_pfit.control);
8934         /* pfit ratios are autocomputed by the hw on gen4+ */
8935         if (INTEL_INFO(dev)->gen < 4)
8936                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8937         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8938         PIPE_CONF_CHECK_I(pch_pfit.enabled);
8939         if (current_config->pch_pfit.enabled) {
8940                 PIPE_CONF_CHECK_I(pch_pfit.pos);
8941                 PIPE_CONF_CHECK_I(pch_pfit.size);
8942         }
8943
8944         PIPE_CONF_CHECK_I(ips_enabled);
8945
8946         PIPE_CONF_CHECK_I(double_wide);
8947
8948         PIPE_CONF_CHECK_I(shared_dpll);
8949         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8950         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8951         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8952         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8953
8954         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8955                 PIPE_CONF_CHECK_I(pipe_bpp);
8956
8957         if (!IS_HASWELL(dev)) {
8958                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
8959                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8960         }
8961
8962 #undef PIPE_CONF_CHECK_X
8963 #undef PIPE_CONF_CHECK_I
8964 #undef PIPE_CONF_CHECK_FLAGS
8965 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8966 #undef PIPE_CONF_QUIRK
8967
8968         return true;
8969 }
8970
8971 static void
8972 check_connector_state(struct drm_device *dev)
8973 {
8974         struct intel_connector *connector;
8975
8976         list_for_each_entry(connector, &dev->mode_config.connector_list,
8977                             base.head) {
8978                 /* This also checks the encoder/connector hw state with the
8979                  * ->get_hw_state callbacks. */
8980                 intel_connector_check_state(connector);
8981
8982                 WARN(&connector->new_encoder->base != connector->base.encoder,
8983                      "connector's staged encoder doesn't match current encoder\n");
8984         }
8985 }
8986
8987 static void
8988 check_encoder_state(struct drm_device *dev)
8989 {
8990         struct intel_encoder *encoder;
8991         struct intel_connector *connector;
8992
8993         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8994                             base.head) {
8995                 bool enabled = false;
8996                 bool active = false;
8997                 enum pipe pipe, tracked_pipe;
8998
8999                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9000                               encoder->base.base.id,
9001                               drm_get_encoder_name(&encoder->base));
9002
9003                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9004                      "encoder's stage crtc doesn't match current crtc\n");
9005                 WARN(encoder->connectors_active && !encoder->base.crtc,
9006                      "encoder's active_connectors set, but no crtc\n");
9007
9008                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9009                                     base.head) {
9010                         if (connector->base.encoder != &encoder->base)
9011                                 continue;
9012                         enabled = true;
9013                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9014                                 active = true;
9015                 }
9016                 WARN(!!encoder->base.crtc != enabled,
9017                      "encoder's enabled state mismatch "
9018                      "(expected %i, found %i)\n",
9019                      !!encoder->base.crtc, enabled);
9020                 WARN(active && !encoder->base.crtc,
9021                      "active encoder with no crtc\n");
9022
9023                 WARN(encoder->connectors_active != active,
9024                      "encoder's computed active state doesn't match tracked active state "
9025                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9026
9027                 active = encoder->get_hw_state(encoder, &pipe);
9028                 WARN(active != encoder->connectors_active,
9029                      "encoder's hw state doesn't match sw tracking "
9030                      "(expected %i, found %i)\n",
9031                      encoder->connectors_active, active);
9032
9033                 if (!encoder->base.crtc)
9034                         continue;
9035
9036                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9037                 WARN(active && pipe != tracked_pipe,
9038                      "active encoder's pipe doesn't match"
9039                      "(expected %i, found %i)\n",
9040                      tracked_pipe, pipe);
9041
9042         }
9043 }
9044
9045 static void
9046 check_crtc_state(struct drm_device *dev)
9047 {
9048         drm_i915_private_t *dev_priv = dev->dev_private;
9049         struct intel_crtc *crtc;
9050         struct intel_encoder *encoder;
9051         struct intel_crtc_config pipe_config;
9052
9053         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9054                             base.head) {
9055                 bool enabled = false;
9056                 bool active = false;
9057
9058                 memset(&pipe_config, 0, sizeof(pipe_config));
9059
9060                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9061                               crtc->base.base.id);
9062
9063                 WARN(crtc->active && !crtc->base.enabled,
9064                      "active crtc, but not enabled in sw tracking\n");
9065
9066                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9067                                     base.head) {
9068                         if (encoder->base.crtc != &crtc->base)
9069                                 continue;
9070                         enabled = true;
9071                         if (encoder->connectors_active)
9072                                 active = true;
9073                 }
9074
9075                 WARN(active != crtc->active,
9076                      "crtc's computed active state doesn't match tracked active state "
9077                      "(expected %i, found %i)\n", active, crtc->active);
9078                 WARN(enabled != crtc->base.enabled,
9079                      "crtc's computed enabled state doesn't match tracked enabled state "
9080                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9081
9082                 active = dev_priv->display.get_pipe_config(crtc,
9083                                                            &pipe_config);
9084
9085                 /* hw state is inconsistent with the pipe A quirk */
9086                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9087                         active = crtc->active;
9088
9089                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9090                                     base.head) {
9091                         enum pipe pipe;
9092                         if (encoder->base.crtc != &crtc->base)
9093                                 continue;
9094                         if (encoder->get_config &&
9095                             encoder->get_hw_state(encoder, &pipe))
9096                                 encoder->get_config(encoder, &pipe_config);
9097                 }
9098
9099                 WARN(crtc->active != active,
9100                      "crtc active state doesn't match with hw state "
9101                      "(expected %i, found %i)\n", crtc->active, active);
9102
9103                 if (active &&
9104                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9105                         WARN(1, "pipe state doesn't match!\n");
9106                         intel_dump_pipe_config(crtc, &pipe_config,
9107                                                "[hw state]");
9108                         intel_dump_pipe_config(crtc, &crtc->config,
9109                                                "[sw state]");
9110                 }
9111         }
9112 }
9113
9114 static void
9115 check_shared_dpll_state(struct drm_device *dev)
9116 {
9117         drm_i915_private_t *dev_priv = dev->dev_private;
9118         struct intel_crtc *crtc;
9119         struct intel_dpll_hw_state dpll_hw_state;
9120         int i;
9121
9122         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9123                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9124                 int enabled_crtcs = 0, active_crtcs = 0;
9125                 bool active;
9126
9127                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9128
9129                 DRM_DEBUG_KMS("%s\n", pll->name);
9130
9131                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9132
9133                 WARN(pll->active > pll->refcount,
9134                      "more active pll users than references: %i vs %i\n",
9135                      pll->active, pll->refcount);
9136                 WARN(pll->active && !pll->on,
9137                      "pll in active use but not on in sw tracking\n");
9138                 WARN(pll->on && !pll->active,
9139                      "pll in on but not on in use in sw tracking\n");
9140                 WARN(pll->on != active,
9141                      "pll on state mismatch (expected %i, found %i)\n",
9142                      pll->on, active);
9143
9144                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9145                                     base.head) {
9146                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9147                                 enabled_crtcs++;
9148                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9149                                 active_crtcs++;
9150                 }
9151                 WARN(pll->active != active_crtcs,
9152                      "pll active crtcs mismatch (expected %i, found %i)\n",
9153                      pll->active, active_crtcs);
9154                 WARN(pll->refcount != enabled_crtcs,
9155                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9156                      pll->refcount, enabled_crtcs);
9157
9158                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9159                                        sizeof(dpll_hw_state)),
9160                      "pll hw state mismatch\n");
9161         }
9162 }
9163
9164 void
9165 intel_modeset_check_state(struct drm_device *dev)
9166 {
9167         check_connector_state(dev);
9168         check_encoder_state(dev);
9169         check_crtc_state(dev);
9170         check_shared_dpll_state(dev);
9171 }
9172
9173 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9174                                      int dotclock)
9175 {
9176         /*
9177          * FDI already provided one idea for the dotclock.
9178          * Yell if the encoder disagrees.
9179          */
9180         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9181              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9182              pipe_config->adjusted_mode.crtc_clock, dotclock);
9183 }
9184
9185 static int __intel_set_mode(struct drm_crtc *crtc,
9186                             struct drm_display_mode *mode,
9187                             int x, int y, struct drm_framebuffer *fb)
9188 {
9189         struct drm_device *dev = crtc->dev;
9190         drm_i915_private_t *dev_priv = dev->dev_private;
9191         struct drm_display_mode *saved_mode, *saved_hwmode;
9192         struct intel_crtc_config *pipe_config = NULL;
9193         struct intel_crtc *intel_crtc;
9194         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9195         int ret = 0;
9196
9197         saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9198         if (!saved_mode)
9199                 return -ENOMEM;
9200         saved_hwmode = saved_mode + 1;
9201
9202         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9203                                      &prepare_pipes, &disable_pipes);
9204
9205         *saved_hwmode = crtc->hwmode;
9206         *saved_mode = crtc->mode;
9207
9208         /* Hack: Because we don't (yet) support global modeset on multiple
9209          * crtcs, we don't keep track of the new mode for more than one crtc.
9210          * Hence simply check whether any bit is set in modeset_pipes in all the
9211          * pieces of code that are not yet converted to deal with mutliple crtcs
9212          * changing their mode at the same time. */
9213         if (modeset_pipes) {
9214                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9215                 if (IS_ERR(pipe_config)) {
9216                         ret = PTR_ERR(pipe_config);
9217                         pipe_config = NULL;
9218
9219                         goto out;
9220                 }
9221                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9222                                        "[modeset]");
9223         }
9224
9225         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9226                 intel_crtc_disable(&intel_crtc->base);
9227
9228         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9229                 if (intel_crtc->base.enabled)
9230                         dev_priv->display.crtc_disable(&intel_crtc->base);
9231         }
9232
9233         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9234          * to set it here already despite that we pass it down the callchain.
9235          */
9236         if (modeset_pipes) {
9237                 crtc->mode = *mode;
9238                 /* mode_set/enable/disable functions rely on a correct pipe
9239                  * config. */
9240                 to_intel_crtc(crtc)->config = *pipe_config;
9241         }
9242
9243         /* Only after disabling all output pipelines that will be changed can we
9244          * update the the output configuration. */
9245         intel_modeset_update_state(dev, prepare_pipes);
9246
9247         if (dev_priv->display.modeset_global_resources)
9248                 dev_priv->display.modeset_global_resources(dev);
9249
9250         /* Set up the DPLL and any encoders state that needs to adjust or depend
9251          * on the DPLL.
9252          */
9253         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9254                 ret = intel_crtc_mode_set(&intel_crtc->base,
9255                                           x, y, fb);
9256                 if (ret)
9257                         goto done;
9258         }
9259
9260         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9261         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9262                 dev_priv->display.crtc_enable(&intel_crtc->base);
9263
9264         if (modeset_pipes) {
9265                 /* Store real post-adjustment hardware mode. */
9266                 crtc->hwmode = pipe_config->adjusted_mode;
9267
9268                 /* Calculate and store various constants which
9269                  * are later needed by vblank and swap-completion
9270                  * timestamping. They are derived from true hwmode.
9271                  */
9272                 drm_calc_timestamping_constants(crtc);
9273         }
9274
9275         /* FIXME: add subpixel order */
9276 done:
9277         if (ret && crtc->enabled) {
9278                 crtc->hwmode = *saved_hwmode;
9279                 crtc->mode = *saved_mode;
9280         }
9281
9282 out:
9283         kfree(pipe_config);
9284         kfree(saved_mode);
9285         return ret;
9286 }
9287
9288 static int intel_set_mode(struct drm_crtc *crtc,
9289                           struct drm_display_mode *mode,
9290                           int x, int y, struct drm_framebuffer *fb)
9291 {
9292         int ret;
9293
9294         ret = __intel_set_mode(crtc, mode, x, y, fb);
9295
9296         if (ret == 0)
9297                 intel_modeset_check_state(crtc->dev);
9298
9299         return ret;
9300 }
9301
9302 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9303 {
9304         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9305 }
9306
9307 #undef for_each_intel_crtc_masked
9308
9309 static void intel_set_config_free(struct intel_set_config *config)
9310 {
9311         if (!config)
9312                 return;
9313
9314         kfree(config->save_connector_encoders);
9315         kfree(config->save_encoder_crtcs);
9316         kfree(config);
9317 }
9318
9319 static int intel_set_config_save_state(struct drm_device *dev,
9320                                        struct intel_set_config *config)
9321 {
9322         struct drm_encoder *encoder;
9323         struct drm_connector *connector;
9324         int count;
9325
9326         config->save_encoder_crtcs =
9327                 kcalloc(dev->mode_config.num_encoder,
9328                         sizeof(struct drm_crtc *), GFP_KERNEL);
9329         if (!config->save_encoder_crtcs)
9330                 return -ENOMEM;
9331
9332         config->save_connector_encoders =
9333                 kcalloc(dev->mode_config.num_connector,
9334                         sizeof(struct drm_encoder *), GFP_KERNEL);
9335         if (!config->save_connector_encoders)
9336                 return -ENOMEM;
9337
9338         /* Copy data. Note that driver private data is not affected.
9339          * Should anything bad happen only the expected state is
9340          * restored, not the drivers personal bookkeeping.
9341          */
9342         count = 0;
9343         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9344                 config->save_encoder_crtcs[count++] = encoder->crtc;
9345         }
9346
9347         count = 0;
9348         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9349                 config->save_connector_encoders[count++] = connector->encoder;
9350         }
9351
9352         return 0;
9353 }
9354
9355 static void intel_set_config_restore_state(struct drm_device *dev,
9356                                            struct intel_set_config *config)
9357 {
9358         struct intel_encoder *encoder;
9359         struct intel_connector *connector;
9360         int count;
9361
9362         count = 0;
9363         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9364                 encoder->new_crtc =
9365                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9366         }
9367
9368         count = 0;
9369         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9370                 connector->new_encoder =
9371                         to_intel_encoder(config->save_connector_encoders[count++]);
9372         }
9373 }
9374
9375 static bool
9376 is_crtc_connector_off(struct drm_mode_set *set)
9377 {
9378         int i;
9379
9380         if (set->num_connectors == 0)
9381                 return false;
9382
9383         if (WARN_ON(set->connectors == NULL))
9384                 return false;
9385
9386         for (i = 0; i < set->num_connectors; i++)
9387                 if (set->connectors[i]->encoder &&
9388                     set->connectors[i]->encoder->crtc == set->crtc &&
9389                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9390                         return true;
9391
9392         return false;
9393 }
9394
9395 static void
9396 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9397                                       struct intel_set_config *config)
9398 {
9399
9400         /* We should be able to check here if the fb has the same properties
9401          * and then just flip_or_move it */
9402         if (is_crtc_connector_off(set)) {
9403                 config->mode_changed = true;
9404         } else if (set->crtc->fb != set->fb) {
9405                 /* If we have no fb then treat it as a full mode set */
9406                 if (set->crtc->fb == NULL) {
9407                         struct intel_crtc *intel_crtc =
9408                                 to_intel_crtc(set->crtc);
9409
9410                         if (intel_crtc->active && i915_fastboot) {
9411                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9412                                 config->fb_changed = true;
9413                         } else {
9414                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9415                                 config->mode_changed = true;
9416                         }
9417                 } else if (set->fb == NULL) {
9418                         config->mode_changed = true;
9419                 } else if (set->fb->pixel_format !=
9420                            set->crtc->fb->pixel_format) {
9421                         config->mode_changed = true;
9422                 } else {
9423                         config->fb_changed = true;
9424                 }
9425         }
9426
9427         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9428                 config->fb_changed = true;
9429
9430         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9431                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9432                 drm_mode_debug_printmodeline(&set->crtc->mode);
9433                 drm_mode_debug_printmodeline(set->mode);
9434                 config->mode_changed = true;
9435         }
9436
9437         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9438                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9439 }
9440
9441 static int
9442 intel_modeset_stage_output_state(struct drm_device *dev,
9443                                  struct drm_mode_set *set,
9444                                  struct intel_set_config *config)
9445 {
9446         struct drm_crtc *new_crtc;
9447         struct intel_connector *connector;
9448         struct intel_encoder *encoder;
9449         int ro;
9450
9451         /* The upper layers ensure that we either disable a crtc or have a list
9452          * of connectors. For paranoia, double-check this. */
9453         WARN_ON(!set->fb && (set->num_connectors != 0));
9454         WARN_ON(set->fb && (set->num_connectors == 0));
9455
9456         list_for_each_entry(connector, &dev->mode_config.connector_list,
9457                             base.head) {
9458                 /* Otherwise traverse passed in connector list and get encoders
9459                  * for them. */
9460                 for (ro = 0; ro < set->num_connectors; ro++) {
9461                         if (set->connectors[ro] == &connector->base) {
9462                                 connector->new_encoder = connector->encoder;
9463                                 break;
9464                         }
9465                 }
9466
9467                 /* If we disable the crtc, disable all its connectors. Also, if
9468                  * the connector is on the changing crtc but not on the new
9469                  * connector list, disable it. */
9470                 if ((!set->fb || ro == set->num_connectors) &&
9471                     connector->base.encoder &&
9472                     connector->base.encoder->crtc == set->crtc) {
9473                         connector->new_encoder = NULL;
9474
9475                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9476                                 connector->base.base.id,
9477                                 drm_get_connector_name(&connector->base));
9478                 }
9479
9480
9481                 if (&connector->new_encoder->base != connector->base.encoder) {
9482                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9483                         config->mode_changed = true;
9484                 }
9485         }
9486         /* connector->new_encoder is now updated for all connectors. */
9487
9488         /* Update crtc of enabled connectors. */
9489         list_for_each_entry(connector, &dev->mode_config.connector_list,
9490                             base.head) {
9491                 if (!connector->new_encoder)
9492                         continue;
9493
9494                 new_crtc = connector->new_encoder->base.crtc;
9495
9496                 for (ro = 0; ro < set->num_connectors; ro++) {
9497                         if (set->connectors[ro] == &connector->base)
9498                                 new_crtc = set->crtc;
9499                 }
9500
9501                 /* Make sure the new CRTC will work with the encoder */
9502                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9503                                            new_crtc)) {
9504                         return -EINVAL;
9505                 }
9506                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9507
9508                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9509                         connector->base.base.id,
9510                         drm_get_connector_name(&connector->base),
9511                         new_crtc->base.id);
9512         }
9513
9514         /* Check for any encoders that needs to be disabled. */
9515         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9516                             base.head) {
9517                 list_for_each_entry(connector,
9518                                     &dev->mode_config.connector_list,
9519                                     base.head) {
9520                         if (connector->new_encoder == encoder) {
9521                                 WARN_ON(!connector->new_encoder->new_crtc);
9522
9523                                 goto next_encoder;
9524                         }
9525                 }
9526                 encoder->new_crtc = NULL;
9527 next_encoder:
9528                 /* Only now check for crtc changes so we don't miss encoders
9529                  * that will be disabled. */
9530                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9531                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9532                         config->mode_changed = true;
9533                 }
9534         }
9535         /* Now we've also updated encoder->new_crtc for all encoders. */
9536
9537         return 0;
9538 }
9539
9540 static int intel_crtc_set_config(struct drm_mode_set *set)
9541 {
9542         struct drm_device *dev;
9543         struct drm_mode_set save_set;
9544         struct intel_set_config *config;
9545         int ret;
9546
9547         BUG_ON(!set);
9548         BUG_ON(!set->crtc);
9549         BUG_ON(!set->crtc->helper_private);
9550
9551         /* Enforce sane interface api - has been abused by the fb helper. */
9552         BUG_ON(!set->mode && set->fb);
9553         BUG_ON(set->fb && set->num_connectors == 0);
9554
9555         if (set->fb) {
9556                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9557                                 set->crtc->base.id, set->fb->base.id,
9558                                 (int)set->num_connectors, set->x, set->y);
9559         } else {
9560                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9561         }
9562
9563         dev = set->crtc->dev;
9564
9565         ret = -ENOMEM;
9566         config = kzalloc(sizeof(*config), GFP_KERNEL);
9567         if (!config)
9568                 goto out_config;
9569
9570         ret = intel_set_config_save_state(dev, config);
9571         if (ret)
9572                 goto out_config;
9573
9574         save_set.crtc = set->crtc;
9575         save_set.mode = &set->crtc->mode;
9576         save_set.x = set->crtc->x;
9577         save_set.y = set->crtc->y;
9578         save_set.fb = set->crtc->fb;
9579
9580         /* Compute whether we need a full modeset, only an fb base update or no
9581          * change at all. In the future we might also check whether only the
9582          * mode changed, e.g. for LVDS where we only change the panel fitter in
9583          * such cases. */
9584         intel_set_config_compute_mode_changes(set, config);
9585
9586         ret = intel_modeset_stage_output_state(dev, set, config);
9587         if (ret)
9588                 goto fail;
9589
9590         if (config->mode_changed) {
9591                 ret = intel_set_mode(set->crtc, set->mode,
9592                                      set->x, set->y, set->fb);
9593         } else if (config->fb_changed) {
9594                 intel_crtc_wait_for_pending_flips(set->crtc);
9595
9596                 ret = intel_pipe_set_base(set->crtc,
9597                                           set->x, set->y, set->fb);
9598         }
9599
9600         if (ret) {
9601                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9602                               set->crtc->base.id, ret);
9603 fail:
9604                 intel_set_config_restore_state(dev, config);
9605
9606                 /* Try to restore the config */
9607                 if (config->mode_changed &&
9608                     intel_set_mode(save_set.crtc, save_set.mode,
9609                                    save_set.x, save_set.y, save_set.fb))
9610                         DRM_ERROR("failed to restore config after modeset failure\n");
9611         }
9612
9613 out_config:
9614         intel_set_config_free(config);
9615         return ret;
9616 }
9617
9618 static const struct drm_crtc_funcs intel_crtc_funcs = {
9619         .cursor_set = intel_crtc_cursor_set,
9620         .cursor_move = intel_crtc_cursor_move,
9621         .gamma_set = intel_crtc_gamma_set,
9622         .set_config = intel_crtc_set_config,
9623         .destroy = intel_crtc_destroy,
9624         .page_flip = intel_crtc_page_flip,
9625 };
9626
9627 static void intel_cpu_pll_init(struct drm_device *dev)
9628 {
9629         if (HAS_DDI(dev))
9630                 intel_ddi_pll_init(dev);
9631 }
9632
9633 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9634                                       struct intel_shared_dpll *pll,
9635                                       struct intel_dpll_hw_state *hw_state)
9636 {
9637         uint32_t val;
9638
9639         val = I915_READ(PCH_DPLL(pll->id));
9640         hw_state->dpll = val;
9641         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9642         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9643
9644         return val & DPLL_VCO_ENABLE;
9645 }
9646
9647 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9648                                   struct intel_shared_dpll *pll)
9649 {
9650         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9651         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9652 }
9653
9654 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9655                                 struct intel_shared_dpll *pll)
9656 {
9657         /* PCH refclock must be enabled first */
9658         assert_pch_refclk_enabled(dev_priv);
9659
9660         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9661
9662         /* Wait for the clocks to stabilize. */
9663         POSTING_READ(PCH_DPLL(pll->id));
9664         udelay(150);
9665
9666         /* The pixel multiplier can only be updated once the
9667          * DPLL is enabled and the clocks are stable.
9668          *
9669          * So write it again.
9670          */
9671         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9672         POSTING_READ(PCH_DPLL(pll->id));
9673         udelay(200);
9674 }
9675
9676 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9677                                  struct intel_shared_dpll *pll)
9678 {
9679         struct drm_device *dev = dev_priv->dev;
9680         struct intel_crtc *crtc;
9681
9682         /* Make sure no transcoder isn't still depending on us. */
9683         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9684                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9685                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9686         }
9687
9688         I915_WRITE(PCH_DPLL(pll->id), 0);
9689         POSTING_READ(PCH_DPLL(pll->id));
9690         udelay(200);
9691 }
9692
9693 static char *ibx_pch_dpll_names[] = {
9694         "PCH DPLL A",
9695         "PCH DPLL B",
9696 };
9697
9698 static void ibx_pch_dpll_init(struct drm_device *dev)
9699 {
9700         struct drm_i915_private *dev_priv = dev->dev_private;
9701         int i;
9702
9703         dev_priv->num_shared_dpll = 2;
9704
9705         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9706                 dev_priv->shared_dplls[i].id = i;
9707                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9708                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9709                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9710                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9711                 dev_priv->shared_dplls[i].get_hw_state =
9712                         ibx_pch_dpll_get_hw_state;
9713         }
9714 }
9715
9716 static void intel_shared_dpll_init(struct drm_device *dev)
9717 {
9718         struct drm_i915_private *dev_priv = dev->dev_private;
9719
9720         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9721                 ibx_pch_dpll_init(dev);
9722         else
9723                 dev_priv->num_shared_dpll = 0;
9724
9725         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9726         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9727                       dev_priv->num_shared_dpll);
9728 }
9729
9730 static void intel_crtc_init(struct drm_device *dev, int pipe)
9731 {
9732         drm_i915_private_t *dev_priv = dev->dev_private;
9733         struct intel_crtc *intel_crtc;
9734         int i;
9735
9736         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
9737         if (intel_crtc == NULL)
9738                 return;
9739
9740         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9741
9742         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9743         for (i = 0; i < 256; i++) {
9744                 intel_crtc->lut_r[i] = i;
9745                 intel_crtc->lut_g[i] = i;
9746                 intel_crtc->lut_b[i] = i;
9747         }
9748
9749         /* Swap pipes & planes for FBC on pre-965 */
9750         intel_crtc->pipe = pipe;
9751         intel_crtc->plane = pipe;
9752         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9753                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9754                 intel_crtc->plane = !pipe;
9755         }
9756
9757         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9758                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9759         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9760         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9761
9762         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9763 }
9764
9765 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9766                                 struct drm_file *file)
9767 {
9768         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9769         struct drm_mode_object *drmmode_obj;
9770         struct intel_crtc *crtc;
9771
9772         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9773                 return -ENODEV;
9774
9775         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9776                         DRM_MODE_OBJECT_CRTC);
9777
9778         if (!drmmode_obj) {
9779                 DRM_ERROR("no such CRTC id\n");
9780                 return -EINVAL;
9781         }
9782
9783         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9784         pipe_from_crtc_id->pipe = crtc->pipe;
9785
9786         return 0;
9787 }
9788
9789 static int intel_encoder_clones(struct intel_encoder *encoder)
9790 {
9791         struct drm_device *dev = encoder->base.dev;
9792         struct intel_encoder *source_encoder;
9793         int index_mask = 0;
9794         int entry = 0;
9795
9796         list_for_each_entry(source_encoder,
9797                             &dev->mode_config.encoder_list, base.head) {
9798
9799                 if (encoder == source_encoder)
9800                         index_mask |= (1 << entry);
9801
9802                 /* Intel hw has only one MUX where enocoders could be cloned. */
9803                 if (encoder->cloneable && source_encoder->cloneable)
9804                         index_mask |= (1 << entry);
9805
9806                 entry++;
9807         }
9808
9809         return index_mask;
9810 }
9811
9812 static bool has_edp_a(struct drm_device *dev)
9813 {
9814         struct drm_i915_private *dev_priv = dev->dev_private;
9815
9816         if (!IS_MOBILE(dev))
9817                 return false;
9818
9819         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9820                 return false;
9821
9822         if (IS_GEN5(dev) &&
9823             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9824                 return false;
9825
9826         return true;
9827 }
9828
9829 static void intel_setup_outputs(struct drm_device *dev)
9830 {
9831         struct drm_i915_private *dev_priv = dev->dev_private;
9832         struct intel_encoder *encoder;
9833         bool dpd_is_edp = false;
9834
9835         intel_lvds_init(dev);
9836
9837         if (!IS_ULT(dev))
9838                 intel_crt_init(dev);
9839
9840         if (HAS_DDI(dev)) {
9841                 int found;
9842
9843                 /* Haswell uses DDI functions to detect digital outputs */
9844                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9845                 /* DDI A only supports eDP */
9846                 if (found)
9847                         intel_ddi_init(dev, PORT_A);
9848
9849                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9850                  * register */
9851                 found = I915_READ(SFUSE_STRAP);
9852
9853                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9854                         intel_ddi_init(dev, PORT_B);
9855                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9856                         intel_ddi_init(dev, PORT_C);
9857                 if (found & SFUSE_STRAP_DDID_DETECTED)
9858                         intel_ddi_init(dev, PORT_D);
9859         } else if (HAS_PCH_SPLIT(dev)) {
9860                 int found;
9861                 dpd_is_edp = intel_dpd_is_edp(dev);
9862
9863                 if (has_edp_a(dev))
9864                         intel_dp_init(dev, DP_A, PORT_A);
9865
9866                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9867                         /* PCH SDVOB multiplex with HDMIB */
9868                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9869                         if (!found)
9870                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9871                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9872                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9873                 }
9874
9875                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9876                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9877
9878                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9879                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9880
9881                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9882                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9883
9884                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9885                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9886         } else if (IS_VALLEYVIEW(dev)) {
9887                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9888                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9889                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9890                                         PORT_C);
9891                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9892                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9893                                               PORT_C);
9894                 }
9895
9896                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9897                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9898                                         PORT_B);
9899                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9900                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9901                 }
9902
9903                 intel_dsi_init(dev);
9904         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9905                 bool found = false;
9906
9907                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9908                         DRM_DEBUG_KMS("probing SDVOB\n");
9909                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9910                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9911                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9912                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9913                         }
9914
9915                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9916                                 intel_dp_init(dev, DP_B, PORT_B);
9917                 }
9918
9919                 /* Before G4X SDVOC doesn't have its own detect register */
9920
9921                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9922                         DRM_DEBUG_KMS("probing SDVOC\n");
9923                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9924                 }
9925
9926                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9927
9928                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9929                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9930                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9931                         }
9932                         if (SUPPORTS_INTEGRATED_DP(dev))
9933                                 intel_dp_init(dev, DP_C, PORT_C);
9934                 }
9935
9936                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9937                     (I915_READ(DP_D) & DP_DETECTED))
9938                         intel_dp_init(dev, DP_D, PORT_D);
9939         } else if (IS_GEN2(dev))
9940                 intel_dvo_init(dev);
9941
9942         if (SUPPORTS_TV(dev))
9943                 intel_tv_init(dev);
9944
9945         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9946                 encoder->base.possible_crtcs = encoder->crtc_mask;
9947                 encoder->base.possible_clones =
9948                         intel_encoder_clones(encoder);
9949         }
9950
9951         intel_init_pch_refclk(dev);
9952
9953         drm_helper_move_panel_connectors_to_head(dev);
9954 }
9955
9956 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9957 {
9958         drm_framebuffer_cleanup(&fb->base);
9959         drm_gem_object_unreference_unlocked(&fb->obj->base);
9960 }
9961
9962 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9963 {
9964         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9965
9966         intel_framebuffer_fini(intel_fb);
9967         kfree(intel_fb);
9968 }
9969
9970 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9971                                                 struct drm_file *file,
9972                                                 unsigned int *handle)
9973 {
9974         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9975         struct drm_i915_gem_object *obj = intel_fb->obj;
9976
9977         return drm_gem_handle_create(file, &obj->base, handle);
9978 }
9979
9980 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9981         .destroy = intel_user_framebuffer_destroy,
9982         .create_handle = intel_user_framebuffer_create_handle,
9983 };
9984
9985 int intel_framebuffer_init(struct drm_device *dev,
9986                            struct intel_framebuffer *intel_fb,
9987                            struct drm_mode_fb_cmd2 *mode_cmd,
9988                            struct drm_i915_gem_object *obj)
9989 {
9990         int pitch_limit;
9991         int ret;
9992
9993         if (obj->tiling_mode == I915_TILING_Y) {
9994                 DRM_DEBUG("hardware does not support tiling Y\n");
9995                 return -EINVAL;
9996         }
9997
9998         if (mode_cmd->pitches[0] & 63) {
9999                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10000                           mode_cmd->pitches[0]);
10001                 return -EINVAL;
10002         }
10003
10004         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10005                 pitch_limit = 32*1024;
10006         } else if (INTEL_INFO(dev)->gen >= 4) {
10007                 if (obj->tiling_mode)
10008                         pitch_limit = 16*1024;
10009                 else
10010                         pitch_limit = 32*1024;
10011         } else if (INTEL_INFO(dev)->gen >= 3) {
10012                 if (obj->tiling_mode)
10013                         pitch_limit = 8*1024;
10014                 else
10015                         pitch_limit = 16*1024;
10016         } else
10017                 /* XXX DSPC is limited to 4k tiled */
10018                 pitch_limit = 8*1024;
10019
10020         if (mode_cmd->pitches[0] > pitch_limit) {
10021                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10022                           obj->tiling_mode ? "tiled" : "linear",
10023                           mode_cmd->pitches[0], pitch_limit);
10024                 return -EINVAL;
10025         }
10026
10027         if (obj->tiling_mode != I915_TILING_NONE &&
10028             mode_cmd->pitches[0] != obj->stride) {
10029                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10030                           mode_cmd->pitches[0], obj->stride);
10031                 return -EINVAL;
10032         }
10033
10034         /* Reject formats not supported by any plane early. */
10035         switch (mode_cmd->pixel_format) {
10036         case DRM_FORMAT_C8:
10037         case DRM_FORMAT_RGB565:
10038         case DRM_FORMAT_XRGB8888:
10039         case DRM_FORMAT_ARGB8888:
10040                 break;
10041         case DRM_FORMAT_XRGB1555:
10042         case DRM_FORMAT_ARGB1555:
10043                 if (INTEL_INFO(dev)->gen > 3) {
10044                         DRM_DEBUG("unsupported pixel format: %s\n",
10045                                   drm_get_format_name(mode_cmd->pixel_format));
10046                         return -EINVAL;
10047                 }
10048                 break;
10049         case DRM_FORMAT_XBGR8888:
10050         case DRM_FORMAT_ABGR8888:
10051         case DRM_FORMAT_XRGB2101010:
10052         case DRM_FORMAT_ARGB2101010:
10053         case DRM_FORMAT_XBGR2101010:
10054         case DRM_FORMAT_ABGR2101010:
10055                 if (INTEL_INFO(dev)->gen < 4) {
10056                         DRM_DEBUG("unsupported pixel format: %s\n",
10057                                   drm_get_format_name(mode_cmd->pixel_format));
10058                         return -EINVAL;
10059                 }
10060                 break;
10061         case DRM_FORMAT_YUYV:
10062         case DRM_FORMAT_UYVY:
10063         case DRM_FORMAT_YVYU:
10064         case DRM_FORMAT_VYUY:
10065                 if (INTEL_INFO(dev)->gen < 5) {
10066                         DRM_DEBUG("unsupported pixel format: %s\n",
10067                                   drm_get_format_name(mode_cmd->pixel_format));
10068                         return -EINVAL;
10069                 }
10070                 break;
10071         default:
10072                 DRM_DEBUG("unsupported pixel format: %s\n",
10073                           drm_get_format_name(mode_cmd->pixel_format));
10074                 return -EINVAL;
10075         }
10076
10077         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10078         if (mode_cmd->offsets[0] != 0)
10079                 return -EINVAL;
10080
10081         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10082         intel_fb->obj = obj;
10083
10084         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10085         if (ret) {
10086                 DRM_ERROR("framebuffer init failed %d\n", ret);
10087                 return ret;
10088         }
10089
10090         return 0;
10091 }
10092
10093 static struct drm_framebuffer *
10094 intel_user_framebuffer_create(struct drm_device *dev,
10095                               struct drm_file *filp,
10096                               struct drm_mode_fb_cmd2 *mode_cmd)
10097 {
10098         struct drm_i915_gem_object *obj;
10099
10100         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10101                                                 mode_cmd->handles[0]));
10102         if (&obj->base == NULL)
10103                 return ERR_PTR(-ENOENT);
10104
10105         return intel_framebuffer_create(dev, mode_cmd, obj);
10106 }
10107
10108 #ifndef CONFIG_DRM_I915_FBDEV
10109 static inline void intel_fb_output_poll_changed(struct drm_device *dev)
10110 {
10111 }
10112 #endif
10113
10114 static const struct drm_mode_config_funcs intel_mode_funcs = {
10115         .fb_create = intel_user_framebuffer_create,
10116         .output_poll_changed = intel_fb_output_poll_changed,
10117 };
10118
10119 /* Set up chip specific display functions */
10120 static void intel_init_display(struct drm_device *dev)
10121 {
10122         struct drm_i915_private *dev_priv = dev->dev_private;
10123
10124         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10125                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10126         else if (IS_VALLEYVIEW(dev))
10127                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10128         else if (IS_PINEVIEW(dev))
10129                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10130         else
10131                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10132
10133         if (HAS_DDI(dev)) {
10134                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10135                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10136                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10137                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10138                 dev_priv->display.off = haswell_crtc_off;
10139                 dev_priv->display.update_plane = ironlake_update_plane;
10140         } else if (HAS_PCH_SPLIT(dev)) {
10141                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10142                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10143                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10144                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10145                 dev_priv->display.off = ironlake_crtc_off;
10146                 dev_priv->display.update_plane = ironlake_update_plane;
10147         } else if (IS_VALLEYVIEW(dev)) {
10148                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10149                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10150                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10151                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10152                 dev_priv->display.off = i9xx_crtc_off;
10153                 dev_priv->display.update_plane = i9xx_update_plane;
10154         } else {
10155                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10156                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10157                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10158                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10159                 dev_priv->display.off = i9xx_crtc_off;
10160                 dev_priv->display.update_plane = i9xx_update_plane;
10161         }
10162
10163         /* Returns the core display clock speed */
10164         if (IS_VALLEYVIEW(dev))
10165                 dev_priv->display.get_display_clock_speed =
10166                         valleyview_get_display_clock_speed;
10167         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10168                 dev_priv->display.get_display_clock_speed =
10169                         i945_get_display_clock_speed;
10170         else if (IS_I915G(dev))
10171                 dev_priv->display.get_display_clock_speed =
10172                         i915_get_display_clock_speed;
10173         else if (IS_I945GM(dev) || IS_845G(dev))
10174                 dev_priv->display.get_display_clock_speed =
10175                         i9xx_misc_get_display_clock_speed;
10176         else if (IS_PINEVIEW(dev))
10177                 dev_priv->display.get_display_clock_speed =
10178                         pnv_get_display_clock_speed;
10179         else if (IS_I915GM(dev))
10180                 dev_priv->display.get_display_clock_speed =
10181                         i915gm_get_display_clock_speed;
10182         else if (IS_I865G(dev))
10183                 dev_priv->display.get_display_clock_speed =
10184                         i865_get_display_clock_speed;
10185         else if (IS_I85X(dev))
10186                 dev_priv->display.get_display_clock_speed =
10187                         i855_get_display_clock_speed;
10188         else /* 852, 830 */
10189                 dev_priv->display.get_display_clock_speed =
10190                         i830_get_display_clock_speed;
10191
10192         if (HAS_PCH_SPLIT(dev)) {
10193                 if (IS_GEN5(dev)) {
10194                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10195                         dev_priv->display.write_eld = ironlake_write_eld;
10196                 } else if (IS_GEN6(dev)) {
10197                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10198                         dev_priv->display.write_eld = ironlake_write_eld;
10199                 } else if (IS_IVYBRIDGE(dev)) {
10200                         /* FIXME: detect B0+ stepping and use auto training */
10201                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10202                         dev_priv->display.write_eld = ironlake_write_eld;
10203                         dev_priv->display.modeset_global_resources =
10204                                 ivb_modeset_global_resources;
10205                 } else if (IS_HASWELL(dev)) {
10206                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10207                         dev_priv->display.write_eld = haswell_write_eld;
10208                         dev_priv->display.modeset_global_resources =
10209                                 haswell_modeset_global_resources;
10210                 }
10211         } else if (IS_G4X(dev)) {
10212                 dev_priv->display.write_eld = g4x_write_eld;
10213         }
10214
10215         /* Default just returns -ENODEV to indicate unsupported */
10216         dev_priv->display.queue_flip = intel_default_queue_flip;
10217
10218         switch (INTEL_INFO(dev)->gen) {
10219         case 2:
10220                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10221                 break;
10222
10223         case 3:
10224                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10225                 break;
10226
10227         case 4:
10228         case 5:
10229                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10230                 break;
10231
10232         case 6:
10233                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10234                 break;
10235         case 7:
10236                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10237                 break;
10238         }
10239 }
10240
10241 /*
10242  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10243  * resume, or other times.  This quirk makes sure that's the case for
10244  * affected systems.
10245  */
10246 static void quirk_pipea_force(struct drm_device *dev)
10247 {
10248         struct drm_i915_private *dev_priv = dev->dev_private;
10249
10250         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10251         DRM_INFO("applying pipe a force quirk\n");
10252 }
10253
10254 /*
10255  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10256  */
10257 static void quirk_ssc_force_disable(struct drm_device *dev)
10258 {
10259         struct drm_i915_private *dev_priv = dev->dev_private;
10260         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10261         DRM_INFO("applying lvds SSC disable quirk\n");
10262 }
10263
10264 /*
10265  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10266  * brightness value
10267  */
10268 static void quirk_invert_brightness(struct drm_device *dev)
10269 {
10270         struct drm_i915_private *dev_priv = dev->dev_private;
10271         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10272         DRM_INFO("applying inverted panel brightness quirk\n");
10273 }
10274
10275 /*
10276  * Some machines (Dell XPS13) suffer broken backlight controls if
10277  * BLM_PCH_PWM_ENABLE is set.
10278  */
10279 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10280 {
10281         struct drm_i915_private *dev_priv = dev->dev_private;
10282         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10283         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10284 }
10285
10286 struct intel_quirk {
10287         int device;
10288         int subsystem_vendor;
10289         int subsystem_device;
10290         void (*hook)(struct drm_device *dev);
10291 };
10292
10293 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10294 struct intel_dmi_quirk {
10295         void (*hook)(struct drm_device *dev);
10296         const struct dmi_system_id (*dmi_id_list)[];
10297 };
10298
10299 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10300 {
10301         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10302         return 1;
10303 }
10304
10305 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10306         {
10307                 .dmi_id_list = &(const struct dmi_system_id[]) {
10308                         {
10309                                 .callback = intel_dmi_reverse_brightness,
10310                                 .ident = "NCR Corporation",
10311                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10312                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10313                                 },
10314                         },
10315                         { }  /* terminating entry */
10316                 },
10317                 .hook = quirk_invert_brightness,
10318         },
10319 };
10320
10321 static struct intel_quirk intel_quirks[] = {
10322         /* HP Mini needs pipe A force quirk (LP: #322104) */
10323         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10324
10325         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10326         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10327
10328         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10329         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10330
10331         /* 830 needs to leave pipe A & dpll A up */
10332         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10333
10334         /* Lenovo U160 cannot use SSC on LVDS */
10335         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10336
10337         /* Sony Vaio Y cannot use SSC on LVDS */
10338         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10339
10340         /*
10341          * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10342          * seem to use inverted backlight PWM.
10343          */
10344         { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10345
10346         /* Dell XPS13 HD Sandy Bridge */
10347         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10348         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10349         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10350 };
10351
10352 static void intel_init_quirks(struct drm_device *dev)
10353 {
10354         struct pci_dev *d = dev->pdev;
10355         int i;
10356
10357         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10358                 struct intel_quirk *q = &intel_quirks[i];
10359
10360                 if (d->device == q->device &&
10361                     (d->subsystem_vendor == q->subsystem_vendor ||
10362                      q->subsystem_vendor == PCI_ANY_ID) &&
10363                     (d->subsystem_device == q->subsystem_device ||
10364                      q->subsystem_device == PCI_ANY_ID))
10365                         q->hook(dev);
10366         }
10367         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10368                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10369                         intel_dmi_quirks[i].hook(dev);
10370         }
10371 }
10372
10373 /* Disable the VGA plane that we never use */
10374 static void i915_disable_vga(struct drm_device *dev)
10375 {
10376         struct drm_i915_private *dev_priv = dev->dev_private;
10377         u8 sr1;
10378         u32 vga_reg = i915_vgacntrl_reg(dev);
10379
10380         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10381         outb(SR01, VGA_SR_INDEX);
10382         sr1 = inb(VGA_SR_DATA);
10383         outb(sr1 | 1<<5, VGA_SR_DATA);
10384         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10385         udelay(300);
10386
10387         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10388         POSTING_READ(vga_reg);
10389 }
10390
10391 static void i915_enable_vga_mem(struct drm_device *dev)
10392 {
10393         /* Enable VGA memory on Intel HD */
10394         if (HAS_PCH_SPLIT(dev)) {
10395                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10396                 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10397                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10398                                                    VGA_RSRC_LEGACY_MEM |
10399                                                    VGA_RSRC_NORMAL_IO |
10400                                                    VGA_RSRC_NORMAL_MEM);
10401                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10402         }
10403 }
10404
10405 void i915_disable_vga_mem(struct drm_device *dev)
10406 {
10407         /* Disable VGA memory on Intel HD */
10408         if (HAS_PCH_SPLIT(dev)) {
10409                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10410                 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10411                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10412                                                    VGA_RSRC_NORMAL_IO |
10413                                                    VGA_RSRC_NORMAL_MEM);
10414                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10415         }
10416 }
10417
10418 void intel_modeset_init_hw(struct drm_device *dev)
10419 {
10420         struct drm_i915_private *dev_priv = dev->dev_private;
10421
10422         intel_prepare_ddi(dev);
10423
10424         intel_init_clock_gating(dev);
10425
10426         /* Enable the CRI clock source so we can get at the display */
10427         if (IS_VALLEYVIEW(dev))
10428                 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10429                            DPLL_INTEGRATED_CRI_CLK_VLV);
10430
10431         intel_init_dpio(dev);
10432
10433         mutex_lock(&dev->struct_mutex);
10434         intel_enable_gt_powersave(dev);
10435         mutex_unlock(&dev->struct_mutex);
10436 }
10437
10438 void intel_modeset_suspend_hw(struct drm_device *dev)
10439 {
10440         intel_suspend_hw(dev);
10441 }
10442
10443 void intel_modeset_init(struct drm_device *dev)
10444 {
10445         struct drm_i915_private *dev_priv = dev->dev_private;
10446         int i, j, ret;
10447
10448         drm_mode_config_init(dev);
10449
10450         dev->mode_config.min_width = 0;
10451         dev->mode_config.min_height = 0;
10452
10453         dev->mode_config.preferred_depth = 24;
10454         dev->mode_config.prefer_shadow = 1;
10455
10456         dev->mode_config.funcs = &intel_mode_funcs;
10457
10458         intel_init_quirks(dev);
10459
10460         intel_init_pm(dev);
10461
10462         if (INTEL_INFO(dev)->num_pipes == 0)
10463                 return;
10464
10465         intel_init_display(dev);
10466
10467         if (IS_GEN2(dev)) {
10468                 dev->mode_config.max_width = 2048;
10469                 dev->mode_config.max_height = 2048;
10470         } else if (IS_GEN3(dev)) {
10471                 dev->mode_config.max_width = 4096;
10472                 dev->mode_config.max_height = 4096;
10473         } else {
10474                 dev->mode_config.max_width = 8192;
10475                 dev->mode_config.max_height = 8192;
10476         }
10477         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10478
10479         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10480                       INTEL_INFO(dev)->num_pipes,
10481                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10482
10483         for_each_pipe(i) {
10484                 intel_crtc_init(dev, i);
10485                 for (j = 0; j < dev_priv->num_plane; j++) {
10486                         ret = intel_plane_init(dev, i, j);
10487                         if (ret)
10488                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10489                                               pipe_name(i), sprite_name(i, j), ret);
10490                 }
10491         }
10492
10493         intel_cpu_pll_init(dev);
10494         intel_shared_dpll_init(dev);
10495
10496         /* Just disable it once at startup */
10497         i915_disable_vga(dev);
10498         intel_setup_outputs(dev);
10499
10500         /* Just in case the BIOS is doing something questionable. */
10501         intel_disable_fbc(dev);
10502 }
10503
10504 static void
10505 intel_connector_break_all_links(struct intel_connector *connector)
10506 {
10507         connector->base.dpms = DRM_MODE_DPMS_OFF;
10508         connector->base.encoder = NULL;
10509         connector->encoder->connectors_active = false;
10510         connector->encoder->base.crtc = NULL;
10511 }
10512
10513 static void intel_enable_pipe_a(struct drm_device *dev)
10514 {
10515         struct intel_connector *connector;
10516         struct drm_connector *crt = NULL;
10517         struct intel_load_detect_pipe load_detect_temp;
10518
10519         /* We can't just switch on the pipe A, we need to set things up with a
10520          * proper mode and output configuration. As a gross hack, enable pipe A
10521          * by enabling the load detect pipe once. */
10522         list_for_each_entry(connector,
10523                             &dev->mode_config.connector_list,
10524                             base.head) {
10525                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10526                         crt = &connector->base;
10527                         break;
10528                 }
10529         }
10530
10531         if (!crt)
10532                 return;
10533
10534         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10535                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10536
10537
10538 }
10539
10540 static bool
10541 intel_check_plane_mapping(struct intel_crtc *crtc)
10542 {
10543         struct drm_device *dev = crtc->base.dev;
10544         struct drm_i915_private *dev_priv = dev->dev_private;
10545         u32 reg, val;
10546
10547         if (INTEL_INFO(dev)->num_pipes == 1)
10548                 return true;
10549
10550         reg = DSPCNTR(!crtc->plane);
10551         val = I915_READ(reg);
10552
10553         if ((val & DISPLAY_PLANE_ENABLE) &&
10554             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10555                 return false;
10556
10557         return true;
10558 }
10559
10560 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10561 {
10562         struct drm_device *dev = crtc->base.dev;
10563         struct drm_i915_private *dev_priv = dev->dev_private;
10564         u32 reg;
10565
10566         /* Clear any frame start delays used for debugging left by the BIOS */
10567         reg = PIPECONF(crtc->config.cpu_transcoder);
10568         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10569
10570         /* We need to sanitize the plane -> pipe mapping first because this will
10571          * disable the crtc (and hence change the state) if it is wrong. Note
10572          * that gen4+ has a fixed plane -> pipe mapping.  */
10573         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10574                 struct intel_connector *connector;
10575                 bool plane;
10576
10577                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10578                               crtc->base.base.id);
10579
10580                 /* Pipe has the wrong plane attached and the plane is active.
10581                  * Temporarily change the plane mapping and disable everything
10582                  * ...  */
10583                 plane = crtc->plane;
10584                 crtc->plane = !plane;
10585                 dev_priv->display.crtc_disable(&crtc->base);
10586                 crtc->plane = plane;
10587
10588                 /* ... and break all links. */
10589                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10590                                     base.head) {
10591                         if (connector->encoder->base.crtc != &crtc->base)
10592                                 continue;
10593
10594                         intel_connector_break_all_links(connector);
10595                 }
10596
10597                 WARN_ON(crtc->active);
10598                 crtc->base.enabled = false;
10599         }
10600
10601         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10602             crtc->pipe == PIPE_A && !crtc->active) {
10603                 /* BIOS forgot to enable pipe A, this mostly happens after
10604                  * resume. Force-enable the pipe to fix this, the update_dpms
10605                  * call below we restore the pipe to the right state, but leave
10606                  * the required bits on. */
10607                 intel_enable_pipe_a(dev);
10608         }
10609
10610         /* Adjust the state of the output pipe according to whether we
10611          * have active connectors/encoders. */
10612         intel_crtc_update_dpms(&crtc->base);
10613
10614         if (crtc->active != crtc->base.enabled) {
10615                 struct intel_encoder *encoder;
10616
10617                 /* This can happen either due to bugs in the get_hw_state
10618                  * functions or because the pipe is force-enabled due to the
10619                  * pipe A quirk. */
10620                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10621                               crtc->base.base.id,
10622                               crtc->base.enabled ? "enabled" : "disabled",
10623                               crtc->active ? "enabled" : "disabled");
10624
10625                 crtc->base.enabled = crtc->active;
10626
10627                 /* Because we only establish the connector -> encoder ->
10628                  * crtc links if something is active, this means the
10629                  * crtc is now deactivated. Break the links. connector
10630                  * -> encoder links are only establish when things are
10631                  *  actually up, hence no need to break them. */
10632                 WARN_ON(crtc->active);
10633
10634                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10635                         WARN_ON(encoder->connectors_active);
10636                         encoder->base.crtc = NULL;
10637                 }
10638         }
10639 }
10640
10641 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10642 {
10643         struct intel_connector *connector;
10644         struct drm_device *dev = encoder->base.dev;
10645
10646         /* We need to check both for a crtc link (meaning that the
10647          * encoder is active and trying to read from a pipe) and the
10648          * pipe itself being active. */
10649         bool has_active_crtc = encoder->base.crtc &&
10650                 to_intel_crtc(encoder->base.crtc)->active;
10651
10652         if (encoder->connectors_active && !has_active_crtc) {
10653                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10654                               encoder->base.base.id,
10655                               drm_get_encoder_name(&encoder->base));
10656
10657                 /* Connector is active, but has no active pipe. This is
10658                  * fallout from our resume register restoring. Disable
10659                  * the encoder manually again. */
10660                 if (encoder->base.crtc) {
10661                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10662                                       encoder->base.base.id,
10663                                       drm_get_encoder_name(&encoder->base));
10664                         encoder->disable(encoder);
10665                 }
10666
10667                 /* Inconsistent output/port/pipe state happens presumably due to
10668                  * a bug in one of the get_hw_state functions. Or someplace else
10669                  * in our code, like the register restore mess on resume. Clamp
10670                  * things to off as a safer default. */
10671                 list_for_each_entry(connector,
10672                                     &dev->mode_config.connector_list,
10673                                     base.head) {
10674                         if (connector->encoder != encoder)
10675                                 continue;
10676
10677                         intel_connector_break_all_links(connector);
10678                 }
10679         }
10680         /* Enabled encoders without active connectors will be fixed in
10681          * the crtc fixup. */
10682 }
10683
10684 void i915_redisable_vga(struct drm_device *dev)
10685 {
10686         struct drm_i915_private *dev_priv = dev->dev_private;
10687         u32 vga_reg = i915_vgacntrl_reg(dev);
10688
10689         /* This function can be called both from intel_modeset_setup_hw_state or
10690          * at a very early point in our resume sequence, where the power well
10691          * structures are not yet restored. Since this function is at a very
10692          * paranoid "someone might have enabled VGA while we were not looking"
10693          * level, just check if the power well is enabled instead of trying to
10694          * follow the "don't touch the power well if we don't need it" policy
10695          * the rest of the driver uses. */
10696         if (HAS_POWER_WELL(dev) &&
10697             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10698                 return;
10699
10700         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
10701                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10702                 i915_disable_vga(dev);
10703                 i915_disable_vga_mem(dev);
10704         }
10705 }
10706
10707 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10708 {
10709         struct drm_i915_private *dev_priv = dev->dev_private;
10710         enum pipe pipe;
10711         struct intel_crtc *crtc;
10712         struct intel_encoder *encoder;
10713         struct intel_connector *connector;
10714         int i;
10715
10716         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10717                             base.head) {
10718                 memset(&crtc->config, 0, sizeof(crtc->config));
10719
10720                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10721                                                                  &crtc->config);
10722
10723                 crtc->base.enabled = crtc->active;
10724                 crtc->primary_enabled = crtc->active;
10725
10726                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10727                               crtc->base.base.id,
10728                               crtc->active ? "enabled" : "disabled");
10729         }
10730
10731         /* FIXME: Smash this into the new shared dpll infrastructure. */
10732         if (HAS_DDI(dev))
10733                 intel_ddi_setup_hw_pll_state(dev);
10734
10735         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10736                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10737
10738                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10739                 pll->active = 0;
10740                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10741                                     base.head) {
10742                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10743                                 pll->active++;
10744                 }
10745                 pll->refcount = pll->active;
10746
10747                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10748                               pll->name, pll->refcount, pll->on);
10749         }
10750
10751         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10752                             base.head) {
10753                 pipe = 0;
10754
10755                 if (encoder->get_hw_state(encoder, &pipe)) {
10756                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10757                         encoder->base.crtc = &crtc->base;
10758                         if (encoder->get_config)
10759                                 encoder->get_config(encoder, &crtc->config);
10760                 } else {
10761                         encoder->base.crtc = NULL;
10762                 }
10763
10764                 encoder->connectors_active = false;
10765                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10766                               encoder->base.base.id,
10767                               drm_get_encoder_name(&encoder->base),
10768                               encoder->base.crtc ? "enabled" : "disabled",
10769                               pipe);
10770         }
10771
10772         list_for_each_entry(connector, &dev->mode_config.connector_list,
10773                             base.head) {
10774                 if (connector->get_hw_state(connector)) {
10775                         connector->base.dpms = DRM_MODE_DPMS_ON;
10776                         connector->encoder->connectors_active = true;
10777                         connector->base.encoder = &connector->encoder->base;
10778                 } else {
10779                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10780                         connector->base.encoder = NULL;
10781                 }
10782                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10783                               connector->base.base.id,
10784                               drm_get_connector_name(&connector->base),
10785                               connector->base.encoder ? "enabled" : "disabled");
10786         }
10787 }
10788
10789 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10790  * and i915 state tracking structures. */
10791 void intel_modeset_setup_hw_state(struct drm_device *dev,
10792                                   bool force_restore)
10793 {
10794         struct drm_i915_private *dev_priv = dev->dev_private;
10795         enum pipe pipe;
10796         struct intel_crtc *crtc;
10797         struct intel_encoder *encoder;
10798         int i;
10799
10800         intel_modeset_readout_hw_state(dev);
10801
10802         /*
10803          * Now that we have the config, copy it to each CRTC struct
10804          * Note that this could go away if we move to using crtc_config
10805          * checking everywhere.
10806          */
10807         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10808                             base.head) {
10809                 if (crtc->active && i915_fastboot) {
10810                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10811
10812                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10813                                       crtc->base.base.id);
10814                         drm_mode_debug_printmodeline(&crtc->base.mode);
10815                 }
10816         }
10817
10818         /* HW state is read out, now we need to sanitize this mess. */
10819         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10820                             base.head) {
10821                 intel_sanitize_encoder(encoder);
10822         }
10823
10824         for_each_pipe(pipe) {
10825                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10826                 intel_sanitize_crtc(crtc);
10827                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10828         }
10829
10830         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10831                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10832
10833                 if (!pll->on || pll->active)
10834                         continue;
10835
10836                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10837
10838                 pll->disable(dev_priv, pll);
10839                 pll->on = false;
10840         }
10841
10842         if (force_restore) {
10843                 i915_redisable_vga(dev);
10844
10845                 /*
10846                  * We need to use raw interfaces for restoring state to avoid
10847                  * checking (bogus) intermediate states.
10848                  */
10849                 for_each_pipe(pipe) {
10850                         struct drm_crtc *crtc =
10851                                 dev_priv->pipe_to_crtc_mapping[pipe];
10852
10853                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10854                                          crtc->fb);
10855                 }
10856         } else {
10857                 intel_modeset_update_staged_output_state(dev);
10858         }
10859
10860         intel_modeset_check_state(dev);
10861
10862         drm_mode_config_reset(dev);
10863 }
10864
10865 void intel_modeset_gem_init(struct drm_device *dev)
10866 {
10867         intel_modeset_init_hw(dev);
10868
10869         intel_setup_overlay(dev);
10870
10871         intel_modeset_setup_hw_state(dev, false);
10872 }
10873
10874 void intel_modeset_cleanup(struct drm_device *dev)
10875 {
10876         struct drm_i915_private *dev_priv = dev->dev_private;
10877         struct drm_crtc *crtc;
10878         struct drm_connector *connector;
10879
10880         /*
10881          * Interrupts and polling as the first thing to avoid creating havoc.
10882          * Too much stuff here (turning of rps, connectors, ...) would
10883          * experience fancy races otherwise.
10884          */
10885         drm_irq_uninstall(dev);
10886         cancel_work_sync(&dev_priv->hotplug_work);
10887         /*
10888          * Due to the hpd irq storm handling the hotplug work can re-arm the
10889          * poll handlers. Hence disable polling after hpd handling is shut down.
10890          */
10891         drm_kms_helper_poll_fini(dev);
10892
10893         mutex_lock(&dev->struct_mutex);
10894
10895         intel_unregister_dsm_handler();
10896
10897         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10898                 /* Skip inactive CRTCs */
10899                 if (!crtc->fb)
10900                         continue;
10901
10902                 intel_increase_pllclock(crtc);
10903         }
10904
10905         intel_disable_fbc(dev);
10906
10907         i915_enable_vga_mem(dev);
10908
10909         intel_disable_gt_powersave(dev);
10910
10911         ironlake_teardown_rc6(dev);
10912
10913         mutex_unlock(&dev->struct_mutex);
10914
10915         /* flush any delayed tasks or pending work */
10916         flush_scheduled_work();
10917
10918         /* destroy backlight, if any, before the connectors */
10919         intel_panel_destroy_backlight(dev);
10920
10921         /* destroy the sysfs files before encoders/connectors */
10922         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10923                 drm_sysfs_connector_remove(connector);
10924
10925         drm_mode_config_cleanup(dev);
10926
10927         intel_cleanup_overlay(dev);
10928 }
10929
10930 /*
10931  * Return which encoder is currently attached for connector.
10932  */
10933 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10934 {
10935         return &intel_attached_encoder(connector)->base;
10936 }
10937
10938 void intel_connector_attach_encoder(struct intel_connector *connector,
10939                                     struct intel_encoder *encoder)
10940 {
10941         connector->encoder = encoder;
10942         drm_mode_connector_attach_encoder(&connector->base,
10943                                           &encoder->base);
10944 }
10945
10946 /*
10947  * set vga decode state - true == enable VGA decode
10948  */
10949 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10950 {
10951         struct drm_i915_private *dev_priv = dev->dev_private;
10952         u16 gmch_ctrl;
10953
10954         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10955         if (state)
10956                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10957         else
10958                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10959         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10960         return 0;
10961 }
10962
10963 struct intel_display_error_state {
10964
10965         u32 power_well_driver;
10966
10967         int num_transcoders;
10968
10969         struct intel_cursor_error_state {
10970                 u32 control;
10971                 u32 position;
10972                 u32 base;
10973                 u32 size;
10974         } cursor[I915_MAX_PIPES];
10975
10976         struct intel_pipe_error_state {
10977                 u32 source;
10978         } pipe[I915_MAX_PIPES];
10979
10980         struct intel_plane_error_state {
10981                 u32 control;
10982                 u32 stride;
10983                 u32 size;
10984                 u32 pos;
10985                 u32 addr;
10986                 u32 surface;
10987                 u32 tile_offset;
10988         } plane[I915_MAX_PIPES];
10989
10990         struct intel_transcoder_error_state {
10991                 enum transcoder cpu_transcoder;
10992
10993                 u32 conf;
10994
10995                 u32 htotal;
10996                 u32 hblank;
10997                 u32 hsync;
10998                 u32 vtotal;
10999                 u32 vblank;
11000                 u32 vsync;
11001         } transcoder[4];
11002 };
11003
11004 struct intel_display_error_state *
11005 intel_display_capture_error_state(struct drm_device *dev)
11006 {
11007         drm_i915_private_t *dev_priv = dev->dev_private;
11008         struct intel_display_error_state *error;
11009         int transcoders[] = {
11010                 TRANSCODER_A,
11011                 TRANSCODER_B,
11012                 TRANSCODER_C,
11013                 TRANSCODER_EDP,
11014         };
11015         int i;
11016
11017         if (INTEL_INFO(dev)->num_pipes == 0)
11018                 return NULL;
11019
11020         error = kmalloc(sizeof(*error), GFP_ATOMIC);
11021         if (error == NULL)
11022                 return NULL;
11023
11024         if (HAS_POWER_WELL(dev))
11025                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11026
11027         for_each_pipe(i) {
11028                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11029                         error->cursor[i].control = I915_READ(CURCNTR(i));
11030                         error->cursor[i].position = I915_READ(CURPOS(i));
11031                         error->cursor[i].base = I915_READ(CURBASE(i));
11032                 } else {
11033                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11034                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11035                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11036                 }
11037
11038                 error->plane[i].control = I915_READ(DSPCNTR(i));
11039                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11040                 if (INTEL_INFO(dev)->gen <= 3) {
11041                         error->plane[i].size = I915_READ(DSPSIZE(i));
11042                         error->plane[i].pos = I915_READ(DSPPOS(i));
11043                 }
11044                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11045                         error->plane[i].addr = I915_READ(DSPADDR(i));
11046                 if (INTEL_INFO(dev)->gen >= 4) {
11047                         error->plane[i].surface = I915_READ(DSPSURF(i));
11048                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11049                 }
11050
11051                 error->pipe[i].source = I915_READ(PIPESRC(i));
11052         }
11053
11054         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11055         if (HAS_DDI(dev_priv->dev))
11056                 error->num_transcoders++; /* Account for eDP. */
11057
11058         for (i = 0; i < error->num_transcoders; i++) {
11059                 enum transcoder cpu_transcoder = transcoders[i];
11060
11061                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11062
11063                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11064                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11065                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11066                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11067                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11068                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11069                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11070         }
11071
11072         /* In the code above we read the registers without checking if the power
11073          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11074          * prevent the next I915_WRITE from detecting it and printing an error
11075          * message. */
11076         intel_uncore_clear_errors(dev);
11077
11078         return error;
11079 }
11080
11081 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11082
11083 void
11084 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11085                                 struct drm_device *dev,
11086                                 struct intel_display_error_state *error)
11087 {
11088         int i;
11089
11090         if (!error)
11091                 return;
11092
11093         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11094         if (HAS_POWER_WELL(dev))
11095                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11096                            error->power_well_driver);
11097         for_each_pipe(i) {
11098                 err_printf(m, "Pipe [%d]:\n", i);
11099                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11100
11101                 err_printf(m, "Plane [%d]:\n", i);
11102                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11103                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11104                 if (INTEL_INFO(dev)->gen <= 3) {
11105                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11106                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11107                 }
11108                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11109                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11110                 if (INTEL_INFO(dev)->gen >= 4) {
11111                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11112                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11113                 }
11114
11115                 err_printf(m, "Cursor [%d]:\n", i);
11116                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11117                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11118                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11119         }
11120
11121         for (i = 0; i < error->num_transcoders; i++) {
11122                 err_printf(m, "  CPU transcoder: %c\n",
11123                            transcoder_name(error->transcoder[i].cpu_transcoder));
11124                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11125                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11126                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11127                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11128                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11129                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11130                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11131         }
11132 }