drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_clflush.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 static bool is_mmio_work(struct intel_flip_work *work)
  53 {
  54         return work->mmio_work.func;
  55 }
  56
  57 /* Primary plane formats for gen <= 3 */
  58 static const uint32_t i8xx_primary_formats[] = {
  59         DRM_FORMAT_C8,
  60         DRM_FORMAT_RGB565,
  61         DRM_FORMAT_XRGB1555,
  62         DRM_FORMAT_XRGB8888,
  63 };
  64
  65 /* Primary plane formats for gen >= 4 */
  66 static const uint32_t i965_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_XRGB2101010,
  72         DRM_FORMAT_XBGR2101010,
  73 };
  74
  75 static const uint32_t skl_primary_formats[] = {
  76         DRM_FORMAT_C8,
  77         DRM_FORMAT_RGB565,
  78         DRM_FORMAT_XRGB8888,
  79         DRM_FORMAT_XBGR8888,
  80         DRM_FORMAT_ARGB8888,
  81         DRM_FORMAT_ABGR8888,
  82         DRM_FORMAT_XRGB2101010,
  83         DRM_FORMAT_XBGR2101010,
  84         DRM_FORMAT_YUYV,
  85         DRM_FORMAT_YVYU,
  86         DRM_FORMAT_UYVY,
  87         DRM_FORMAT_VYUY,
  88 };
  89
  90 /* Cursor formats */
  91 static const uint32_t intel_cursor_formats[] = {
  92         DRM_FORMAT_ARGB8888,
  93 };
  94
  95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  96                                 struct intel_crtc_state *pipe_config);
  97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  98                                    struct intel_crtc_state *pipe_config);
  99
 100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 101                                   struct drm_i915_gem_object *obj,
 102                                   struct drm_mode_fb_cmd2 *mode_cmd);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 119                                     struct intel_crtc_state *crtc_state);
 120 static void skylake_pfit_enable(struct intel_crtc *crtc);
 121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 125
 126 struct intel_limit {
 127         struct {
 128                 int min, max;
 129         } dot, vco, n, m, m1, m2, p, p1;
 130
 131         struct {
 132                 int dot_limit;
 133                 int p2_slow, p2_fast;
 134         } p2;
 135 };
 136
 137 /* returns HPLL frequency in kHz */
 138 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 139 {
 140         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 141
 142         /* Obtain SKU information */
 143         mutex_lock(&dev_priv->sb_lock);
 144         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 145                 CCK_FUSE_HPLL_FREQ_MASK;
 146         mutex_unlock(&dev_priv->sb_lock);
 147
 148         return vco_freq[hpll_freq] * 1000;
 149 }
 150
 151 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 152                       const char *name, u32 reg, int ref_freq)
 153 {
 154         u32 val;
 155         int divider;
 156
 157         mutex_lock(&dev_priv->sb_lock);
 158         val = vlv_cck_read(dev_priv, reg);
 159         mutex_unlock(&dev_priv->sb_lock);
 160
 161         divider = val & CCK_FREQUENCY_VALUES;
 162
 163         WARN((val & CCK_FREQUENCY_STATUS) !=
 164              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 165              "%s change in progress\n", name);
 166
 167         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 168 }
 169
 170 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 171                            const char *name, u32 reg)
 172 {
 173         if (dev_priv->hpll_freq == 0)
 174                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 175
 176         return vlv_get_cck_clock(dev_priv, name, reg,
 177                                  dev_priv->hpll_freq);
 178 }
 179
 180 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 181 {
 182         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 183                 return;
 184
 185         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 186                                                       CCK_CZ_CLOCK_CONTROL);
 187
 188         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 189 }
 190
 191 static inline u32 /* units of 100MHz */
 192 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 193                     const struct intel_crtc_state *pipe_config)
 194 {
 195         if (HAS_DDI(dev_priv))
 196                 return pipe_config->port_clock; /* SPLL */
 197         else if (IS_GEN5(dev_priv))
 198                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 199         else
 200                 return 270000;
 201 }
 202
 203 static const struct intel_limit intel_limits_i8xx_dac = {
 204         .dot = { .min = 25000, .max = 350000 },
 205         .vco = { .min = 908000, .max = 1512000 },
 206         .n = { .min = 2, .max = 16 },
 207         .m = { .min = 96, .max = 140 },
 208         .m1 = { .min = 18, .max = 26 },
 209         .m2 = { .min = 6, .max = 16 },
 210         .p = { .min = 4, .max = 128 },
 211         .p1 = { .min = 2, .max = 33 },
 212         .p2 = { .dot_limit = 165000,
 213                 .p2_slow = 4, .p2_fast = 2 },
 214 };
 215
 216 static const struct intel_limit intel_limits_i8xx_dvo = {
 217         .dot = { .min = 25000, .max = 350000 },
 218         .vco = { .min = 908000, .max = 1512000 },
 219         .n = { .min = 2, .max = 16 },
 220         .m = { .min = 96, .max = 140 },
 221         .m1 = { .min = 18, .max = 26 },
 222         .m2 = { .min = 6, .max = 16 },
 223         .p = { .min = 4, .max = 128 },
 224         .p1 = { .min = 2, .max = 33 },
 225         .p2 = { .dot_limit = 165000,
 226                 .p2_slow = 4, .p2_fast = 4 },
 227 };
 228
 229 static const struct intel_limit intel_limits_i8xx_lvds = {
 230         .dot = { .min = 25000, .max = 350000 },
 231         .vco = { .min = 908000, .max = 1512000 },
 232         .n = { .min = 2, .max = 16 },
 233         .m = { .min = 96, .max = 140 },
 234         .m1 = { .min = 18, .max = 26 },
 235         .m2 = { .min = 6, .max = 16 },
 236         .p = { .min = 4, .max = 128 },
 237         .p1 = { .min = 1, .max = 6 },
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 14, .p2_fast = 7 },
 240 };
 241
 242 static const struct intel_limit intel_limits_i9xx_sdvo = {
 243         .dot = { .min = 20000, .max = 400000 },
 244         .vco = { .min = 1400000, .max = 2800000 },
 245         .n = { .min = 1, .max = 6 },
 246         .m = { .min = 70, .max = 120 },
 247         .m1 = { .min = 8, .max = 18 },
 248         .m2 = { .min = 3, .max = 7 },
 249         .p = { .min = 5, .max = 80 },
 250         .p1 = { .min = 1, .max = 8 },
 251         .p2 = { .dot_limit = 200000,
 252                 .p2_slow = 10, .p2_fast = 5 },
 253 };
 254
 255 static const struct intel_limit intel_limits_i9xx_lvds = {
 256         .dot = { .min = 20000, .max = 400000 },
 257         .vco = { .min = 1400000, .max = 2800000 },
 258         .n = { .min = 1, .max = 6 },
 259         .m = { .min = 70, .max = 120 },
 260         .m1 = { .min = 8, .max = 18 },
 261         .m2 = { .min = 3, .max = 7 },
 262         .p = { .min = 7, .max = 98 },
 263         .p1 = { .min = 1, .max = 8 },
 264         .p2 = { .dot_limit = 112000,
 265                 .p2_slow = 14, .p2_fast = 7 },
 266 };
 267
 268
 269 static const struct intel_limit intel_limits_g4x_sdvo = {
 270         .dot = { .min = 25000, .max = 270000 },
 271         .vco = { .min = 1750000, .max = 3500000},
 272         .n = { .min = 1, .max = 4 },
 273         .m = { .min = 104, .max = 138 },
 274         .m1 = { .min = 17, .max = 23 },
 275         .m2 = { .min = 5, .max = 11 },
 276         .p = { .min = 10, .max = 30 },
 277         .p1 = { .min = 1, .max = 3},
 278         .p2 = { .dot_limit = 270000,
 279                 .p2_slow = 10,
 280                 .p2_fast = 10
 281         },
 282 };
 283
 284 static const struct intel_limit intel_limits_g4x_hdmi = {
 285         .dot = { .min = 22000, .max = 400000 },
 286         .vco = { .min = 1750000, .max = 3500000},
 287         .n = { .min = 1, .max = 4 },
 288         .m = { .min = 104, .max = 138 },
 289         .m1 = { .min = 16, .max = 23 },
 290         .m2 = { .min = 5, .max = 11 },
 291         .p = { .min = 5, .max = 80 },
 292         .p1 = { .min = 1, .max = 8},
 293         .p2 = { .dot_limit = 165000,
 294                 .p2_slow = 10, .p2_fast = 5 },
 295 };
 296
 297 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 298         .dot = { .min = 20000, .max = 115000 },
 299         .vco = { .min = 1750000, .max = 3500000 },
 300         .n = { .min = 1, .max = 3 },
 301         .m = { .min = 104, .max = 138 },
 302         .m1 = { .min = 17, .max = 23 },
 303         .m2 = { .min = 5, .max = 11 },
 304         .p = { .min = 28, .max = 112 },
 305         .p1 = { .min = 2, .max = 8 },
 306         .p2 = { .dot_limit = 0,
 307                 .p2_slow = 14, .p2_fast = 14
 308         },
 309 };
 310
 311 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 312         .dot = { .min = 80000, .max = 224000 },
 313         .vco = { .min = 1750000, .max = 3500000 },
 314         .n = { .min = 1, .max = 3 },
 315         .m = { .min = 104, .max = 138 },
 316         .m1 = { .min = 17, .max = 23 },
 317         .m2 = { .min = 5, .max = 11 },
 318         .p = { .min = 14, .max = 42 },
 319         .p1 = { .min = 2, .max = 6 },
 320         .p2 = { .dot_limit = 0,
 321                 .p2_slow = 7, .p2_fast = 7
 322         },
 323 };
 324
 325 static const struct intel_limit intel_limits_pineview_sdvo = {
 326         .dot = { .min = 20000, .max = 400000},
 327         .vco = { .min = 1700000, .max = 3500000 },
 328         /* Pineview's Ncounter is a ring counter */
 329         .n = { .min = 3, .max = 6 },
 330         .m = { .min = 2, .max = 256 },
 331         /* Pineview only has one combined m divider, which we treat as m2. */
 332         .m1 = { .min = 0, .max = 0 },
 333         .m2 = { .min = 0, .max = 254 },
 334         .p = { .min = 5, .max = 80 },
 335         .p1 = { .min = 1, .max = 8 },
 336         .p2 = { .dot_limit = 200000,
 337                 .p2_slow = 10, .p2_fast = 5 },
 338 };
 339
 340 static const struct intel_limit intel_limits_pineview_lvds = {
 341         .dot = { .min = 20000, .max = 400000 },
 342         .vco = { .min = 1700000, .max = 3500000 },
 343         .n = { .min = 3, .max = 6 },
 344         .m = { .min = 2, .max = 256 },
 345         .m1 = { .min = 0, .max = 0 },
 346         .m2 = { .min = 0, .max = 254 },
 347         .p = { .min = 7, .max = 112 },
 348         .p1 = { .min = 1, .max = 8 },
 349         .p2 = { .dot_limit = 112000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 /* Ironlake / Sandybridge
 354  *
 355  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 356  * the range value for them is (actual_value - 2).
 357  */
 358 static const struct intel_limit intel_limits_ironlake_dac = {
 359         .dot = { .min = 25000, .max = 350000 },
 360         .vco = { .min = 1760000, .max = 3510000 },
 361         .n = { .min = 1, .max = 5 },
 362         .m = { .min = 79, .max = 127 },
 363         .m1 = { .min = 12, .max = 22 },
 364         .m2 = { .min = 5, .max = 9 },
 365         .p = { .min = 5, .max = 80 },
 366         .p1 = { .min = 1, .max = 8 },
 367         .p2 = { .dot_limit = 225000,
 368                 .p2_slow = 10, .p2_fast = 5 },
 369 };
 370
 371 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 372         .dot = { .min = 25000, .max = 350000 },
 373         .vco = { .min = 1760000, .max = 3510000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 79, .max = 118 },
 376         .m1 = { .min = 12, .max = 22 },
 377         .m2 = { .min = 5, .max = 9 },
 378         .p = { .min = 28, .max = 112 },
 379         .p1 = { .min = 2, .max = 8 },
 380         .p2 = { .dot_limit = 225000,
 381                 .p2_slow = 14, .p2_fast = 14 },
 382 };
 383
 384 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 385         .dot = { .min = 25000, .max = 350000 },
 386         .vco = { .min = 1760000, .max = 3510000 },
 387         .n = { .min = 1, .max = 3 },
 388         .m = { .min = 79, .max = 127 },
 389         .m1 = { .min = 12, .max = 22 },
 390         .m2 = { .min = 5, .max = 9 },
 391         .p = { .min = 14, .max = 56 },
 392         .p1 = { .min = 2, .max = 8 },
 393         .p2 = { .dot_limit = 225000,
 394                 .p2_slow = 7, .p2_fast = 7 },
 395 };
 396
 397 /* LVDS 100mhz refclk limits. */
 398 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 399         .dot = { .min = 25000, .max = 350000 },
 400         .vco = { .min = 1760000, .max = 3510000 },
 401         .n = { .min = 1, .max = 2 },
 402         .m = { .min = 79, .max = 126 },
 403         .m1 = { .min = 12, .max = 22 },
 404         .m2 = { .min = 5, .max = 9 },
 405         .p = { .min = 28, .max = 112 },
 406         .p1 = { .min = 2, .max = 8 },
 407         .p2 = { .dot_limit = 225000,
 408                 .p2_slow = 14, .p2_fast = 14 },
 409 };
 410
 411 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 412         .dot = { .min = 25000, .max = 350000 },
 413         .vco = { .min = 1760000, .max = 3510000 },
 414         .n = { .min = 1, .max = 3 },
 415         .m = { .min = 79, .max = 126 },
 416         .m1 = { .min = 12, .max = 22 },
 417         .m2 = { .min = 5, .max = 9 },
 418         .p = { .min = 14, .max = 42 },
 419         .p1 = { .min = 2, .max = 6 },
 420         .p2 = { .dot_limit = 225000,
 421                 .p2_slow = 7, .p2_fast = 7 },
 422 };
 423
 424 static const struct intel_limit intel_limits_vlv = {
 425          /*
 426           * These are the data rate limits (measured in fast clocks)
 427           * since those are the strictest limits we have. The fast
 428           * clock and actual rate limits are more relaxed, so checking
 429           * them would make no difference.
 430           */
 431         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 432         .vco = { .min = 4000000, .max = 6000000 },
 433         .n = { .min = 1, .max = 7 },
 434         .m1 = { .min = 2, .max = 3 },
 435         .m2 = { .min = 11, .max = 156 },
 436         .p1 = { .min = 2, .max = 3 },
 437         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 438 };
 439
 440 static const struct intel_limit intel_limits_chv = {
 441         /*
 442          * These are the data rate limits (measured in fast clocks)
 443          * since those are the strictest limits we have.  The fast
 444          * clock and actual rate limits are more relaxed, so checking
 445          * them would make no difference.
 446          */
 447         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 448         .vco = { .min = 4800000, .max = 6480000 },
 449         .n = { .min = 1, .max = 1 },
 450         .m1 = { .min = 2, .max = 2 },
 451         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 452         .p1 = { .min = 2, .max = 4 },
 453         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 454 };
 455
 456 static const struct intel_limit intel_limits_bxt = {
 457         /* FIXME: find real dot limits */
 458         .dot = { .min = 0, .max = INT_MAX },
 459         .vco = { .min = 4800000, .max = 6700000 },
 460         .n = { .min = 1, .max = 1 },
 461         .m1 = { .min = 2, .max = 2 },
 462         /* FIXME: find real m2 limits */
 463         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 464         .p1 = { .min = 2, .max = 4 },
 465         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 466 };
 467
 468 static bool
 469 needs_modeset(struct drm_crtc_state *state)
 470 {
 471         return drm_atomic_crtc_needs_modeset(state);
 472 }
 473
 474 /*
 475  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 476  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 477  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 478  * The helpers' return value is the rate of the clock that is fed to the
 479  * display engine's pipe which can be the above fast dot clock rate or a
 480  * divided-down version of it.
 481  */
 482 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 483 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 484 {
 485         clock->m = clock->m2 + 2;
 486         clock->p = clock->p1 * clock->p2;
 487         if (WARN_ON(clock->n == 0 || clock->p == 0))
 488                 return 0;
 489         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 490         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 491
 492         return clock->dot;
 493 }
 494
 495 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 496 {
 497         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 498 }
 499
 500 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 501 {
 502         clock->m = i9xx_dpll_compute_m(clock);
 503         clock->p = clock->p1 * clock->p2;
 504         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 505                 return 0;
 506         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 507         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 508
 509         return clock->dot;
 510 }
 511
 512 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 513 {
 514         clock->m = clock->m1 * clock->m2;
 515         clock->p = clock->p1 * clock->p2;
 516         if (WARN_ON(clock->n == 0 || clock->p == 0))
 517                 return 0;
 518         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 519         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 520
 521         return clock->dot / 5;
 522 }
 523
 524 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 525 {
 526         clock->m = clock->m1 * clock->m2;
 527         clock->p = clock->p1 * clock->p2;
 528         if (WARN_ON(clock->n == 0 || clock->p == 0))
 529                 return 0;
 530         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 531                         clock->n << 22);
 532         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 533
 534         return clock->dot / 5;
 535 }
 536
 537 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 538 /**
 539  * Returns whether the given set of divisors are valid for a given refclk with
 540  * the given connectors.
 541  */
 542
 543 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 544                                const struct intel_limit *limit,
 545                                const struct dpll *clock)
 546 {
 547         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 548                 INTELPllInvalid("n out of range\n");
 549         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 550                 INTELPllInvalid("p1 out of range\n");
 551         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 552                 INTELPllInvalid("m2 out of range\n");
 553         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 554                 INTELPllInvalid("m1 out of range\n");
 555
 556         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 557             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 558                 if (clock->m1 <= clock->m2)
 559                         INTELPllInvalid("m1 <= m2\n");
 560
 561         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 562             !IS_GEN9_LP(dev_priv)) {
 563                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 564                         INTELPllInvalid("p out of range\n");
 565                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 566                         INTELPllInvalid("m out of range\n");
 567         }
 568
 569         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 570                 INTELPllInvalid("vco out of range\n");
 571         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 572          * connector, etc., rather than just a single range.
 573          */
 574         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 575                 INTELPllInvalid("dot out of range\n");
 576
 577         return true;
 578 }
 579
 580 static int
 581 i9xx_select_p2_div(const struct intel_limit *limit,
 582                    const struct intel_crtc_state *crtc_state,
 583                    int target)
 584 {
 585         struct drm_device *dev = crtc_state->base.crtc->dev;
 586
 587         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 588                 /*
 589                  * For LVDS just rely on its current settings for dual-channel.
 590                  * We haven't figured out how to reliably set up different
 591                  * single/dual channel state, if we even can.
 592                  */
 593                 if (intel_is_dual_link_lvds(dev))
 594                         return limit->p2.p2_fast;
 595                 else
 596                         return limit->p2.p2_slow;
 597         } else {
 598                 if (target < limit->p2.dot_limit)
 599                         return limit->p2.p2_slow;
 600                 else
 601                         return limit->p2.p2_fast;
 602         }
 603 }
 604
 605 /*
 606  * Returns a set of divisors for the desired target clock with the given
 607  * refclk, or FALSE.  The returned values represent the clock equation:
 608  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 609  *
 610  * Target and reference clocks are specified in kHz.
 611  *
 612  * If match_clock is provided, then best_clock P divider must match the P
 613  * divider from @match_clock used for LVDS downclocking.
 614  */
 615 static bool
 616 i9xx_find_best_dpll(const struct intel_limit *limit,
 617                     struct intel_crtc_state *crtc_state,
 618                     int target, int refclk, struct dpll *match_clock,
 619                     struct dpll *best_clock)
 620 {
 621         struct drm_device *dev = crtc_state->base.crtc->dev;
 622         struct dpll clock;
 623         int err = target;
 624
 625         memset(best_clock, 0, sizeof(*best_clock));
 626
 627         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 628
 629         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 630              clock.m1++) {
 631                 for (clock.m2 = limit->m2.min;
 632                      clock.m2 <= limit->m2.max; clock.m2++) {
 633                         if (clock.m2 >= clock.m1)
 634                                 break;
 635                         for (clock.n = limit->n.min;
 636                              clock.n <= limit->n.max; clock.n++) {
 637                                 for (clock.p1 = limit->p1.min;
 638                                         clock.p1 <= limit->p1.max; clock.p1++) {
 639                                         int this_err;
 640
 641                                         i9xx_calc_dpll_params(refclk, &clock);
 642                                         if (!intel_PLL_is_valid(to_i915(dev),
 643                                                                 limit,
 644                                                                 &clock))
 645                                                 continue;
 646                                         if (match_clock &&
 647                                             clock.p != match_clock->p)
 648                                                 continue;
 649
 650                                         this_err = abs(clock.dot - target);
 651                                         if (this_err < err) {
 652                                                 *best_clock = clock;
 653                                                 err = this_err;
 654                                         }
 655                                 }
 656                         }
 657                 }
 658         }
 659
 660         return (err != target);
 661 }
 662
 663 /*
 664  * Returns a set of divisors for the desired target clock with the given
 665  * refclk, or FALSE.  The returned values represent the clock equation:
 666  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 667  *
 668  * Target and reference clocks are specified in kHz.
 669  *
 670  * If match_clock is provided, then best_clock P divider must match the P
 671  * divider from @match_clock used for LVDS downclocking.
 672  */
 673 static bool
 674 pnv_find_best_dpll(const struct intel_limit *limit,
 675                    struct intel_crtc_state *crtc_state,
 676                    int target, int refclk, struct dpll *match_clock,
 677                    struct dpll *best_clock)
 678 {
 679         struct drm_device *dev = crtc_state->base.crtc->dev;
 680         struct dpll clock;
 681         int err = target;
 682
 683         memset(best_clock, 0, sizeof(*best_clock));
 684
 685         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pnv_calc_dpll_params(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(to_i915(dev),
 699                                                                 limit,
 700                                                                 &clock))
 701                                                 continue;
 702                                         if (match_clock &&
 703                                             clock.p != match_clock->p)
 704                                                 continue;
 705
 706                                         this_err = abs(clock.dot - target);
 707                                         if (this_err < err) {
 708                                                 *best_clock = clock;
 709                                                 err = this_err;
 710                                         }
 711                                 }
 712                         }
 713                 }
 714         }
 715
 716         return (err != target);
 717 }
 718
 719 /*
 720  * Returns a set of divisors for the desired target clock with the given
 721  * refclk, or FALSE.  The returned values represent the clock equation:
 722  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 723  *
 724  * Target and reference clocks are specified in kHz.
 725  *
 726  * If match_clock is provided, then best_clock P divider must match the P
 727  * divider from @match_clock used for LVDS downclocking.
 728  */
 729 static bool
 730 g4x_find_best_dpll(const struct intel_limit *limit,
 731                    struct intel_crtc_state *crtc_state,
 732                    int target, int refclk, struct dpll *match_clock,
 733                    struct dpll *best_clock)
 734 {
 735         struct drm_device *dev = crtc_state->base.crtc->dev;
 736         struct dpll clock;
 737         int max_n;
 738         bool found = false;
 739         /* approximately equals target * 0.00585 */
 740         int err_most = (target >> 8) + (target >> 9);
 741
 742         memset(best_clock, 0, sizeof(*best_clock));
 743
 744         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 745
 746         max_n = limit->n.max;
 747         /* based on hardware requirement, prefer smaller n to precision */
 748         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 749                 /* based on hardware requirement, prefere larger m1,m2 */
 750                 for (clock.m1 = limit->m1.max;
 751                      clock.m1 >= limit->m1.min; clock.m1--) {
 752                         for (clock.m2 = limit->m2.max;
 753                              clock.m2 >= limit->m2.min; clock.m2--) {
 754                                 for (clock.p1 = limit->p1.max;
 755                                      clock.p1 >= limit->p1.min; clock.p1--) {
 756                                         int this_err;
 757
 758                                         i9xx_calc_dpll_params(refclk, &clock);
 759                                         if (!intel_PLL_is_valid(to_i915(dev),
 760                                                                 limit,
 761                                                                 &clock))
 762                                                 continue;
 763
 764                                         this_err = abs(clock.dot - target);
 765                                         if (this_err < err_most) {
 766                                                 *best_clock = clock;
 767                                                 err_most = this_err;
 768                                                 max_n = clock.n;
 769                                                 found = true;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775         return found;
 776 }
 777
 778 /*
 779  * Check if the calculated PLL configuration is more optimal compared to the
 780  * best configuration and error found so far. Return the calculated error.
 781  */
 782 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 783                                const struct dpll *calculated_clock,
 784                                const struct dpll *best_clock,
 785                                unsigned int best_error_ppm,
 786                                unsigned int *error_ppm)
 787 {
 788         /*
 789          * For CHV ignore the error and consider only the P value.
 790          * Prefer a bigger P value based on HW requirements.
 791          */
 792         if (IS_CHERRYVIEW(to_i915(dev))) {
 793                 *error_ppm = 0;
 794
 795                 return calculated_clock->p > best_clock->p;
 796         }
 797
 798         if (WARN_ON_ONCE(!target_freq))
 799                 return false;
 800
 801         *error_ppm = div_u64(1000000ULL *
 802                                 abs(target_freq - calculated_clock->dot),
 803                              target_freq);
 804         /*
 805          * Prefer a better P value over a better (smaller) error if the error
 806          * is small. Ensure this preference for future configurations too by
 807          * setting the error to 0.
 808          */
 809         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 810                 *error_ppm = 0;
 811
 812                 return true;
 813         }
 814
 815         return *error_ppm + 10 < best_error_ppm;
 816 }
 817
 818 /*
 819  * Returns a set of divisors for the desired target clock with the given
 820  * refclk, or FALSE.  The returned values represent the clock equation:
 821  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 822  */
 823 static bool
 824 vlv_find_best_dpll(const struct intel_limit *limit,
 825                    struct intel_crtc_state *crtc_state,
 826                    int target, int refclk, struct dpll *match_clock,
 827                    struct dpll *best_clock)
 828 {
 829         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 830         struct drm_device *dev = crtc->base.dev;
 831         struct dpll clock;
 832         unsigned int bestppm = 1000000;
 833         /* min update 19.2 MHz */
 834         int max_n = min(limit->n.max, refclk / 19200);
 835         bool found = false;
 836
 837         target *= 5; /* fast clock */
 838
 839         memset(best_clock, 0, sizeof(*best_clock));
 840
 841         /* based on hardware requirement, prefer smaller n to precision */
 842         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 843                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 844                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 845                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 846                                 clock.p = clock.p1 * clock.p2;
 847                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 848                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 849                                         unsigned int ppm;
 850
 851                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 852                                                                      refclk * clock.m1);
 853
 854                                         vlv_calc_dpll_params(refclk, &clock);
 855
 856                                         if (!intel_PLL_is_valid(to_i915(dev),
 857                                                                 limit,
 858                                                                 &clock))
 859                                                 continue;
 860
 861                                         if (!vlv_PLL_is_optimal(dev, target,
 862                                                                 &clock,
 863                                                                 best_clock,
 864                                                                 bestppm, &ppm))
 865                                                 continue;
 866
 867                                         *best_clock = clock;
 868                                         bestppm = ppm;
 869                                         found = true;
 870                                 }
 871                         }
 872                 }
 873         }
 874
 875         return found;
 876 }
 877
 878 /*
 879  * Returns a set of divisors for the desired target clock with the given
 880  * refclk, or FALSE.  The returned values represent the clock equation:
 881  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 882  */
 883 static bool
 884 chv_find_best_dpll(const struct intel_limit *limit,
 885                    struct intel_crtc_state *crtc_state,
 886                    int target, int refclk, struct dpll *match_clock,
 887                    struct dpll *best_clock)
 888 {
 889         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 890         struct drm_device *dev = crtc->base.dev;
 891         unsigned int best_error_ppm;
 892         struct dpll clock;
 893         uint64_t m2;
 894         int found = false;
 895
 896         memset(best_clock, 0, sizeof(*best_clock));
 897         best_error_ppm = 1000000;
 898
 899         /*
 900          * Based on hardware doc, the n always set to 1, and m1 always
 901          * set to 2.  If requires to support 200Mhz refclk, we need to
 902          * revisit this because n may not 1 anymore.
 903          */
 904         clock.n = 1, clock.m1 = 2;
 905         target *= 5;    /* fast clock */
 906
 907         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 908                 for (clock.p2 = limit->p2.p2_fast;
 909                                 clock.p2 >= limit->p2.p2_slow;
 910                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 911                         unsigned int error_ppm;
 912
 913                         clock.p = clock.p1 * clock.p2;
 914
 915                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 916                                         clock.n) << 22, refclk * clock.m1);
 917
 918                         if (m2 > INT_MAX/clock.m1)
 919                                 continue;
 920
 921                         clock.m2 = m2;
 922
 923                         chv_calc_dpll_params(refclk, &clock);
 924
 925                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 926                                 continue;
 927
 928                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 929                                                 best_error_ppm, &error_ppm))
 930                                 continue;
 931
 932                         *best_clock = clock;
 933                         best_error_ppm = error_ppm;
 934                         found = true;
 935                 }
 936         }
 937
 938         return found;
 939 }
 940
 941 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 942                         struct dpll *best_clock)
 943 {
 944         int refclk = 100000;
 945         const struct intel_limit *limit = &intel_limits_bxt;
 946
 947         return chv_find_best_dpll(limit, crtc_state,
 948                                   target_clock, refclk, NULL, best_clock);
 949 }
 950
 951 bool intel_crtc_active(struct intel_crtc *crtc)
 952 {
 953         /* Be paranoid as we can arrive here with only partial
 954          * state retrieved from the hardware during setup.
 955          *
 956          * We can ditch the adjusted_mode.crtc_clock check as soon
 957          * as Haswell has gained clock readout/fastboot support.
 958          *
 959          * We can ditch the crtc->primary->fb check as soon as we can
 960          * properly reconstruct framebuffers.
 961          *
 962          * FIXME: The intel_crtc->active here should be switched to
 963          * crtc->state->active once we have proper CRTC states wired up
 964          * for atomic.
 965          */
 966         return crtc->active && crtc->base.primary->state->fb &&
 967                 crtc->config->base.adjusted_mode.crtc_clock;
 968 }
 969
 970 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 971                                              enum pipe pipe)
 972 {
 973         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 974
 975         return crtc->config->cpu_transcoder;
 976 }
 977
 978 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
 979 {
 980         i915_reg_t reg = PIPEDSL(pipe);
 981         u32 line1, line2;
 982         u32 line_mask;
 983
 984         if (IS_GEN2(dev_priv))
 985                 line_mask = DSL_LINEMASK_GEN2;
 986         else
 987                 line_mask = DSL_LINEMASK_GEN3;
 988
 989         line1 = I915_READ(reg) & line_mask;
 990         msleep(5);
 991         line2 = I915_READ(reg) & line_mask;
 992
 993         return line1 == line2;
 994 }
 995
 996 /*
 997  * intel_wait_for_pipe_off - wait for pipe to turn off
 998  * @crtc: crtc whose pipe to wait for
 999  *
1000  * After disabling a pipe, we can't wait for vblank in the usual way,
1001  * spinning on the vblank interrupt status bit, since we won't actually
1002  * see an interrupt when the pipe is disabled.
1003  *
1004  * On Gen4 and above:
1005  *   wait for the pipe register state bit to turn off
1006  *
1007  * Otherwise:
1008  *   wait for the display line value to settle (it usually
1009  *   ends up stopping at the start of the next frame).
1010  *
1011  */
1012 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1013 {
1014         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1015         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1016         enum pipe pipe = crtc->pipe;
1017
1018         if (INTEL_GEN(dev_priv) >= 4) {
1019                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1020
1021                 /* Wait for the Pipe State to go off */
1022                 if (intel_wait_for_register(dev_priv,
1023                                             reg, I965_PIPECONF_ACTIVE, 0,
1024                                             100))
1025                         WARN(1, "pipe_off wait timed out\n");
1026         } else {
1027                 /* Wait for the display line to settle */
1028                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1029                         WARN(1, "pipe_off wait timed out\n");
1030         }
1031 }
1032
1033 /* Only for pre-ILK configs */
1034 void assert_pll(struct drm_i915_private *dev_priv,
1035                 enum pipe pipe, bool state)
1036 {
1037         u32 val;
1038         bool cur_state;
1039
1040         val = I915_READ(DPLL(pipe));
1041         cur_state = !!(val & DPLL_VCO_ENABLE);
1042         I915_STATE_WARN(cur_state != state,
1043              "PLL state assertion failure (expected %s, current %s)\n",
1044                         onoff(state), onoff(cur_state));
1045 }
1046
1047 /* XXX: the dsi pll is shared between MIPI DSI ports */
1048 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1049 {
1050         u32 val;
1051         bool cur_state;
1052
1053         mutex_lock(&dev_priv->sb_lock);
1054         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1055         mutex_unlock(&dev_priv->sb_lock);
1056
1057         cur_state = val & DSI_PLL_VCO_EN;
1058         I915_STATE_WARN(cur_state != state,
1059              "DSI PLL state assertion failure (expected %s, current %s)\n",
1060                         onoff(state), onoff(cur_state));
1061 }
1062
1063 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1064                           enum pipe pipe, bool state)
1065 {
1066         bool cur_state;
1067         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1068                                                                       pipe);
1069
1070         if (HAS_DDI(dev_priv)) {
1071                 /* DDI does not have a specific FDI_TX register */
1072                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1073                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1074         } else {
1075                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1076                 cur_state = !!(val & FDI_TX_ENABLE);
1077         }
1078         I915_STATE_WARN(cur_state != state,
1079              "FDI TX state assertion failure (expected %s, current %s)\n",
1080                         onoff(state), onoff(cur_state));
1081 }
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1084
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086                           enum pipe pipe, bool state)
1087 {
1088         u32 val;
1089         bool cur_state;
1090
1091         val = I915_READ(FDI_RX_CTL(pipe));
1092         cur_state = !!(val & FDI_RX_ENABLE);
1093         I915_STATE_WARN(cur_state != state,
1094              "FDI RX state assertion failure (expected %s, current %s)\n",
1095                         onoff(state), onoff(cur_state));
1096 }
1097 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1098 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1099
1100 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1101                                       enum pipe pipe)
1102 {
1103         u32 val;
1104
1105         /* ILK FDI PLL is always enabled */
1106         if (IS_GEN5(dev_priv))
1107                 return;
1108
1109         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1110         if (HAS_DDI(dev_priv))
1111                 return;
1112
1113         val = I915_READ(FDI_TX_CTL(pipe));
1114         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1115 }
1116
1117 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1118                        enum pipe pipe, bool state)
1119 {
1120         u32 val;
1121         bool cur_state;
1122
1123         val = I915_READ(FDI_RX_CTL(pipe));
1124         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1125         I915_STATE_WARN(cur_state != state,
1126              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1127                         onoff(state), onoff(cur_state));
1128 }
1129
1130 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1131 {
1132         i915_reg_t pp_reg;
1133         u32 val;
1134         enum pipe panel_pipe = PIPE_A;
1135         bool locked = true;
1136
1137         if (WARN_ON(HAS_DDI(dev_priv)))
1138                 return;
1139
1140         if (HAS_PCH_SPLIT(dev_priv)) {
1141                 u32 port_sel;
1142
1143                 pp_reg = PP_CONTROL(0);
1144                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1145
1146                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1147                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1148                         panel_pipe = PIPE_B;
1149                 /* XXX: else fix for eDP */
1150         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1151                 /* presumably write lock depends on pipe, not port select */
1152                 pp_reg = PP_CONTROL(pipe);
1153                 panel_pipe = pipe;
1154         } else {
1155                 pp_reg = PP_CONTROL(0);
1156                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1157                         panel_pipe = PIPE_B;
1158         }
1159
1160         val = I915_READ(pp_reg);
1161         if (!(val & PANEL_POWER_ON) ||
1162             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1163                 locked = false;
1164
1165         I915_STATE_WARN(panel_pipe == pipe && locked,
1166              "panel assertion failure, pipe %c regs locked\n",
1167              pipe_name(pipe));
1168 }
1169
1170 static void assert_cursor(struct drm_i915_private *dev_priv,
1171                           enum pipe pipe, bool state)
1172 {
1173         bool cur_state;
1174
1175         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1176                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1177         else
1178                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1179
1180         I915_STATE_WARN(cur_state != state,
1181              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1182                         pipe_name(pipe), onoff(state), onoff(cur_state));
1183 }
1184 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1185 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1186
1187 void assert_pipe(struct drm_i915_private *dev_priv,
1188                  enum pipe pipe, bool state)
1189 {
1190         bool cur_state;
1191         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192                                                                       pipe);
1193         enum intel_display_power_domain power_domain;
1194
1195         /* if we need the pipe quirk it must be always on */
1196         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1197             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1198                 state = true;
1199
1200         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203                 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205                 intel_display_power_put(dev_priv, power_domain);
1206         } else {
1207                 cur_state = false;
1208         }
1209
1210         I915_STATE_WARN(cur_state != state,
1211              "pipe %c assertion failure (expected %s, current %s)\n",
1212                         pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216                          enum plane plane, bool state)
1217 {
1218         u32 val;
1219         bool cur_state;
1220
1221         val = I915_READ(DSPCNTR(plane));
1222         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223         I915_STATE_WARN(cur_state != state,
1224              "plane %c assertion failure (expected %s, current %s)\n",
1225                         plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232                                    enum pipe pipe)
1233 {
1234         int i;
1235
1236         /* Primary planes are fixed to pipes on gen4+ */
1237         if (INTEL_GEN(dev_priv) >= 4) {
1238                 u32 val = I915_READ(DSPCNTR(pipe));
1239                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240                      "plane %c assertion failure, should be disabled but not\n",
1241                      plane_name(pipe));
1242                 return;
1243         }
1244
1245         /* Need to check both planes against the pipe */
1246         for_each_pipe(dev_priv, i) {
1247                 u32 val = I915_READ(DSPCNTR(i));
1248                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249                         DISPPLANE_SEL_PIPE_SHIFT;
1250                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252                      plane_name(i), pipe_name(pipe));
1253         }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257                                     enum pipe pipe)
1258 {
1259         int sprite;
1260
1261         if (INTEL_GEN(dev_priv) >= 9) {
1262                 for_each_sprite(dev_priv, pipe, sprite) {
1263                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266                              sprite, pipe_name(pipe));
1267                 }
1268         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269                 for_each_sprite(dev_priv, pipe, sprite) {
1270                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271                         I915_STATE_WARN(val & SP_ENABLE,
1272                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273                              sprite_name(pipe, sprite), pipe_name(pipe));
1274                 }
1275         } else if (INTEL_GEN(dev_priv) >= 7) {
1276                 u32 val = I915_READ(SPRCTL(pipe));
1277                 I915_STATE_WARN(val & SPRITE_ENABLE,
1278                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279                      plane_name(pipe), pipe_name(pipe));
1280         } else if (INTEL_GEN(dev_priv) >= 5) {
1281                 u32 val = I915_READ(DVSCNTR(pipe));
1282                 I915_STATE_WARN(val & DVS_ENABLE,
1283                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284                      plane_name(pipe), pipe_name(pipe));
1285         }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291                 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295                                     enum pipe pipe)
1296 {
1297         u32 val;
1298         bool enabled;
1299
1300         val = I915_READ(PCH_TRANSCONF(pipe));
1301         enabled = !!(val & TRANS_ENABLE);
1302         I915_STATE_WARN(enabled,
1303              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304              pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308                             enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310         if ((val & DP_PORT_EN) == 0)
1311                 return false;
1312
1313         if (HAS_PCH_CPT(dev_priv)) {
1314                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else if (IS_CHERRYVIEW(dev_priv)) {
1318                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319                         return false;
1320         } else {
1321                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322                         return false;
1323         }
1324         return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328                               enum pipe pipe, u32 val)
1329 {
1330         if ((val & SDVO_ENABLE) == 0)
1331                 return false;
1332
1333         if (HAS_PCH_CPT(dev_priv)) {
1334                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335                         return false;
1336         } else if (IS_CHERRYVIEW(dev_priv)) {
1337                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338                         return false;
1339         } else {
1340                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341                         return false;
1342         }
1343         return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347                               enum pipe pipe, u32 val)
1348 {
1349         if ((val & LVDS_PORT_EN) == 0)
1350                 return false;
1351
1352         if (HAS_PCH_CPT(dev_priv)) {
1353                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354                         return false;
1355         } else {
1356                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357                         return false;
1358         }
1359         return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363                               enum pipe pipe, u32 val)
1364 {
1365         if ((val & ADPA_DAC_ENABLE) == 0)
1366                 return false;
1367         if (HAS_PCH_CPT(dev_priv)) {
1368                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369                         return false;
1370         } else {
1371                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372                         return false;
1373         }
1374         return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378                                    enum pipe pipe, i915_reg_t reg,
1379                                    u32 port_sel)
1380 {
1381         u32 val = I915_READ(reg);
1382         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384              i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387              && (val & DP_PIPEB_SELECT),
1388              "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392                                      enum pipe pipe, i915_reg_t reg)
1393 {
1394         u32 val = I915_READ(reg);
1395         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397              i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400              && (val & SDVO_PIPE_B_SELECT),
1401              "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405                                       enum pipe pipe)
1406 {
1407         u32 val;
1408
1409         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413         val = I915_READ(PCH_ADPA);
1414         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415              "PCH VGA enabled on transcoder %c, should be disabled\n",
1416              pipe_name(pipe));
1417
1418         val = I915_READ(PCH_LVDS);
1419         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421              pipe_name(pipe));
1422
1423         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429                             const struct intel_crtc_state *pipe_config)
1430 {
1431         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432         enum pipe pipe = crtc->pipe;
1433
1434         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435         POSTING_READ(DPLL(pipe));
1436         udelay(150);
1437
1438         if (intel_wait_for_register(dev_priv,
1439                                     DPLL(pipe),
1440                                     DPLL_LOCK_VLV,
1441                                     DPLL_LOCK_VLV,
1442                                     1))
1443                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447                            const struct intel_crtc_state *pipe_config)
1448 {
1449         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450         enum pipe pipe = crtc->pipe;
1451
1452         assert_pipe_disabled(dev_priv, pipe);
1453
1454         /* PLL is protected by panel, make sure we can write it */
1455         assert_panel_unlocked(dev_priv, pipe);
1456
1457         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458                 _vlv_enable_pll(crtc, pipe_config);
1459
1460         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461         POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466                             const struct intel_crtc_state *pipe_config)
1467 {
1468         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469         enum pipe pipe = crtc->pipe;
1470         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471         u32 tmp;
1472
1473         mutex_lock(&dev_priv->sb_lock);
1474
1475         /* Enable back the 10bit clock to display controller */
1476         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477         tmp |= DPIO_DCLKP_EN;
1478         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480         mutex_unlock(&dev_priv->sb_lock);
1481
1482         /*
1483          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484          */
1485         udelay(1);
1486
1487         /* Enable PLL */
1488         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490         /* Check PLL is locked */
1491         if (intel_wait_for_register(dev_priv,
1492                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493                                     1))
1494                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498                            const struct intel_crtc_state *pipe_config)
1499 {
1500         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501         enum pipe pipe = crtc->pipe;
1502
1503         assert_pipe_disabled(dev_priv, pipe);
1504
1505         /* PLL is protected by panel, make sure we can write it */
1506         assert_panel_unlocked(dev_priv, pipe);
1507
1508         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509                 _chv_enable_pll(crtc, pipe_config);
1510
1511         if (pipe != PIPE_A) {
1512                 /*
1513                  * WaPixelRepeatModeFixForC0:chv
1514                  *
1515                  * DPLLCMD is AWOL. Use chicken bits to propagate
1516                  * the value from DPLLBMD to either pipe B or C.
1517                  */
1518                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520                 I915_WRITE(CBR4_VLV, 0);
1521                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523                 /*
1524                  * DPLLB VGA mode also seems to cause problems.
1525                  * We should always have it disabled.
1526                  */
1527                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528         } else {
1529                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530                 POSTING_READ(DPLL_MD(pipe));
1531         }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536         struct intel_crtc *crtc;
1537         int count = 0;
1538
1539         for_each_intel_crtc(&dev_priv->drm, crtc) {
1540                 count += crtc->base.state->active &&
1541                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542         }
1543
1544         return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550         i915_reg_t reg = DPLL(crtc->pipe);
1551         u32 dpll = crtc->config->dpll_hw_state.dpll;
1552
1553         assert_pipe_disabled(dev_priv, crtc->pipe);
1554
1555         /* PLL is protected by panel, make sure we can write it */
1556         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1557                 assert_panel_unlocked(dev_priv, crtc->pipe);
1558
1559         /* Enable DVO 2x clock on both PLLs if necessary */
1560         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1561                 /*
1562                  * It appears to be important that we don't enable this
1563                  * for the current pipe before otherwise configuring the
1564                  * PLL. No idea how this should be handled if multiple
1565                  * DVO outputs are enabled simultaneosly.
1566                  */
1567                 dpll |= DPLL_DVO_2X_MODE;
1568                 I915_WRITE(DPLL(!crtc->pipe),
1569                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1570         }
1571
1572         /*
1573          * Apparently we need to have VGA mode enabled prior to changing
1574          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1575          * dividers, even though the register value does change.
1576          */
1577         I915_WRITE(reg, 0);
1578
1579         I915_WRITE(reg, dpll);
1580
1581         /* Wait for the clocks to stabilize. */
1582         POSTING_READ(reg);
1583         udelay(150);
1584
1585         if (INTEL_GEN(dev_priv) >= 4) {
1586                 I915_WRITE(DPLL_MD(crtc->pipe),
1587                            crtc->config->dpll_hw_state.dpll_md);
1588         } else {
1589                 /* The pixel multiplier can only be updated once the
1590                  * DPLL is enabled and the clocks are stable.
1591                  *
1592                  * So write it again.
1593                  */
1594                 I915_WRITE(reg, dpll);
1595         }
1596
1597         /* We do this three times for luck */
1598         I915_WRITE(reg, dpll);
1599         POSTING_READ(reg);
1600         udelay(150); /* wait for warmup */
1601         I915_WRITE(reg, dpll);
1602         POSTING_READ(reg);
1603         udelay(150); /* wait for warmup */
1604         I915_WRITE(reg, dpll);
1605         POSTING_READ(reg);
1606         udelay(150); /* wait for warmup */
1607 }
1608
1609 /**
1610  * i9xx_disable_pll - disable a PLL
1611  * @dev_priv: i915 private structure
1612  * @pipe: pipe PLL to disable
1613  *
1614  * Disable the PLL for @pipe, making sure the pipe is off first.
1615  *
1616  * Note!  This is for pre-ILK only.
1617  */
1618 static void i9xx_disable_pll(struct intel_crtc *crtc)
1619 {
1620         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1621         enum pipe pipe = crtc->pipe;
1622
1623         /* Disable DVO 2x clock on both PLLs if necessary */
1624         if (IS_I830(dev_priv) &&
1625             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1626             !intel_num_dvo_pipes(dev_priv)) {
1627                 I915_WRITE(DPLL(PIPE_B),
1628                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1629                 I915_WRITE(DPLL(PIPE_A),
1630                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1631         }
1632
1633         /* Don't disable pipe or pipe PLLs if needed */
1634         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1635             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1636                 return;
1637
1638         /* Make sure the pipe isn't still relying on us */
1639         assert_pipe_disabled(dev_priv, pipe);
1640
1641         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1642         POSTING_READ(DPLL(pipe));
1643 }
1644
1645 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1646 {
1647         u32 val;
1648
1649         /* Make sure the pipe isn't still relying on us */
1650         assert_pipe_disabled(dev_priv, pipe);
1651
1652         val = DPLL_INTEGRATED_REF_CLK_VLV |
1653                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1654         if (pipe != PIPE_A)
1655                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1656
1657         I915_WRITE(DPLL(pipe), val);
1658         POSTING_READ(DPLL(pipe));
1659 }
1660
1661 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1662 {
1663         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1664         u32 val;
1665
1666         /* Make sure the pipe isn't still relying on us */
1667         assert_pipe_disabled(dev_priv, pipe);
1668
1669         val = DPLL_SSC_REF_CLK_CHV |
1670                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1671         if (pipe != PIPE_A)
1672                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1673
1674         I915_WRITE(DPLL(pipe), val);
1675         POSTING_READ(DPLL(pipe));
1676
1677         mutex_lock(&dev_priv->sb_lock);
1678
1679         /* Disable 10bit clock to display controller */
1680         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1681         val &= ~DPIO_DCLKP_EN;
1682         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1683
1684         mutex_unlock(&dev_priv->sb_lock);
1685 }
1686
1687 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1688                          struct intel_digital_port *dport,
1689                          unsigned int expected_mask)
1690 {
1691         u32 port_mask;
1692         i915_reg_t dpll_reg;
1693
1694         switch (dport->port) {
1695         case PORT_B:
1696                 port_mask = DPLL_PORTB_READY_MASK;
1697                 dpll_reg = DPLL(0);
1698                 break;
1699         case PORT_C:
1700                 port_mask = DPLL_PORTC_READY_MASK;
1701                 dpll_reg = DPLL(0);
1702                 expected_mask <<= 4;
1703                 break;
1704         case PORT_D:
1705                 port_mask = DPLL_PORTD_READY_MASK;
1706                 dpll_reg = DPIO_PHY_STATUS;
1707                 break;
1708         default:
1709                 BUG();
1710         }
1711
1712         if (intel_wait_for_register(dev_priv,
1713                                     dpll_reg, port_mask, expected_mask,
1714                                     1000))
1715                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1716                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1717 }
1718
1719 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1720                                            enum pipe pipe)
1721 {
1722         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1723                                                                 pipe);
1724         i915_reg_t reg;
1725         uint32_t val, pipeconf_val;
1726
1727         /* Make sure PCH DPLL is enabled */
1728         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1729
1730         /* FDI must be feeding us bits for PCH ports */
1731         assert_fdi_tx_enabled(dev_priv, pipe);
1732         assert_fdi_rx_enabled(dev_priv, pipe);
1733
1734         if (HAS_PCH_CPT(dev_priv)) {
1735                 /* Workaround: Set the timing override bit before enabling the
1736                  * pch transcoder. */
1737                 reg = TRANS_CHICKEN2(pipe);
1738                 val = I915_READ(reg);
1739                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1740                 I915_WRITE(reg, val);
1741         }
1742
1743         reg = PCH_TRANSCONF(pipe);
1744         val = I915_READ(reg);
1745         pipeconf_val = I915_READ(PIPECONF(pipe));
1746
1747         if (HAS_PCH_IBX(dev_priv)) {
1748                 /*
1749                  * Make the BPC in transcoder be consistent with
1750                  * that in pipeconf reg. For HDMI we must use 8bpc
1751                  * here for both 8bpc and 12bpc.
1752                  */
1753                 val &= ~PIPECONF_BPC_MASK;
1754                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1755                         val |= PIPECONF_8BPC;
1756                 else
1757                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1758         }
1759
1760         val &= ~TRANS_INTERLACE_MASK;
1761         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1762                 if (HAS_PCH_IBX(dev_priv) &&
1763                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1764                         val |= TRANS_LEGACY_INTERLACED_ILK;
1765                 else
1766                         val |= TRANS_INTERLACED;
1767         else
1768                 val |= TRANS_PROGRESSIVE;
1769
1770         I915_WRITE(reg, val | TRANS_ENABLE);
1771         if (intel_wait_for_register(dev_priv,
1772                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1773                                     100))
1774                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1775 }
1776
1777 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1778                                       enum transcoder cpu_transcoder)
1779 {
1780         u32 val, pipeconf_val;
1781
1782         /* FDI must be feeding us bits for PCH ports */
1783         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1784         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1785
1786         /* Workaround: set timing override bit. */
1787         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1788         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1789         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1790
1791         val = TRANS_ENABLE;
1792         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1793
1794         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1795             PIPECONF_INTERLACED_ILK)
1796                 val |= TRANS_INTERLACED;
1797         else
1798                 val |= TRANS_PROGRESSIVE;
1799
1800         I915_WRITE(LPT_TRANSCONF, val);
1801         if (intel_wait_for_register(dev_priv,
1802                                     LPT_TRANSCONF,
1803                                     TRANS_STATE_ENABLE,
1804                                     TRANS_STATE_ENABLE,
1805                                     100))
1806                 DRM_ERROR("Failed to enable PCH transcoder\n");
1807 }
1808
1809 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1810                                             enum pipe pipe)
1811 {
1812         i915_reg_t reg;
1813         uint32_t val;
1814
1815         /* FDI relies on the transcoder */
1816         assert_fdi_tx_disabled(dev_priv, pipe);
1817         assert_fdi_rx_disabled(dev_priv, pipe);
1818
1819         /* Ports must be off as well */
1820         assert_pch_ports_disabled(dev_priv, pipe);
1821
1822         reg = PCH_TRANSCONF(pipe);
1823         val = I915_READ(reg);
1824         val &= ~TRANS_ENABLE;
1825         I915_WRITE(reg, val);
1826         /* wait for PCH transcoder off, transcoder state */
1827         if (intel_wait_for_register(dev_priv,
1828                                     reg, TRANS_STATE_ENABLE, 0,
1829                                     50))
1830                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1831
1832         if (HAS_PCH_CPT(dev_priv)) {
1833                 /* Workaround: Clear the timing override chicken bit again. */
1834                 reg = TRANS_CHICKEN2(pipe);
1835                 val = I915_READ(reg);
1836                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1837                 I915_WRITE(reg, val);
1838         }
1839 }
1840
1841 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1842 {
1843         u32 val;
1844
1845         val = I915_READ(LPT_TRANSCONF);
1846         val &= ~TRANS_ENABLE;
1847         I915_WRITE(LPT_TRANSCONF, val);
1848         /* wait for PCH transcoder off, transcoder state */
1849         if (intel_wait_for_register(dev_priv,
1850                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1851                                     50))
1852                 DRM_ERROR("Failed to disable PCH transcoder\n");
1853
1854         /* Workaround: clear timing override bit. */
1855         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1857         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858 }
1859
1860 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1861 {
1862         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1863
1864         WARN_ON(!crtc->config->has_pch_encoder);
1865
1866         if (HAS_PCH_LPT(dev_priv))
1867                 return TRANSCODER_A;
1868         else
1869                 return (enum transcoder) crtc->pipe;
1870 }
1871
1872 /**
1873  * intel_enable_pipe - enable a pipe, asserting requirements
1874  * @crtc: crtc responsible for the pipe
1875  *
1876  * Enable @crtc's pipe, making sure that various hardware specific requirements
1877  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1878  */
1879 static void intel_enable_pipe(struct intel_crtc *crtc)
1880 {
1881         struct drm_device *dev = crtc->base.dev;
1882         struct drm_i915_private *dev_priv = to_i915(dev);
1883         enum pipe pipe = crtc->pipe;
1884         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1885         i915_reg_t reg;
1886         u32 val;
1887
1888         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1889
1890         assert_planes_disabled(dev_priv, pipe);
1891         assert_cursor_disabled(dev_priv, pipe);
1892         assert_sprites_disabled(dev_priv, pipe);
1893
1894         /*
1895          * A pipe without a PLL won't actually be able to drive bits from
1896          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1897          * need the check.
1898          */
1899         if (HAS_GMCH_DISPLAY(dev_priv)) {
1900                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1901                         assert_dsi_pll_enabled(dev_priv);
1902                 else
1903                         assert_pll_enabled(dev_priv, pipe);
1904         } else {
1905                 if (crtc->config->has_pch_encoder) {
1906                         /* if driving the PCH, we need FDI enabled */
1907                         assert_fdi_rx_pll_enabled(dev_priv,
1908                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1909                         assert_fdi_tx_pll_enabled(dev_priv,
1910                                                   (enum pipe) cpu_transcoder);
1911                 }
1912                 /* FIXME: assert CPU port conditions for SNB+ */
1913         }
1914
1915         reg = PIPECONF(cpu_transcoder);
1916         val = I915_READ(reg);
1917         if (val & PIPECONF_ENABLE) {
1918                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1919                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1920                 return;
1921         }
1922
1923         I915_WRITE(reg, val | PIPECONF_ENABLE);
1924         POSTING_READ(reg);
1925
1926         /*
1927          * Until the pipe starts DSL will read as 0, which would cause
1928          * an apparent vblank timestamp jump, which messes up also the
1929          * frame count when it's derived from the timestamps. So let's
1930          * wait for the pipe to start properly before we call
1931          * drm_crtc_vblank_on()
1932          */
1933         if (dev->max_vblank_count == 0 &&
1934             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1935                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1936 }
1937
1938 /**
1939  * intel_disable_pipe - disable a pipe, asserting requirements
1940  * @crtc: crtc whose pipes is to be disabled
1941  *
1942  * Disable the pipe of @crtc, making sure that various hardware
1943  * specific requirements are met, if applicable, e.g. plane
1944  * disabled, panel fitter off, etc.
1945  *
1946  * Will wait until the pipe has shut down before returning.
1947  */
1948 static void intel_disable_pipe(struct intel_crtc *crtc)
1949 {
1950         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1951         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1952         enum pipe pipe = crtc->pipe;
1953         i915_reg_t reg;
1954         u32 val;
1955
1956         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1957
1958         /*
1959          * Make sure planes won't keep trying to pump pixels to us,
1960          * or we might hang the display.
1961          */
1962         assert_planes_disabled(dev_priv, pipe);
1963         assert_cursor_disabled(dev_priv, pipe);
1964         assert_sprites_disabled(dev_priv, pipe);
1965
1966         reg = PIPECONF(cpu_transcoder);
1967         val = I915_READ(reg);
1968         if ((val & PIPECONF_ENABLE) == 0)
1969                 return;
1970
1971         /*
1972          * Double wide has implications for planes
1973          * so best keep it disabled when not needed.
1974          */
1975         if (crtc->config->double_wide)
1976                 val &= ~PIPECONF_DOUBLE_WIDE;
1977
1978         /* Don't disable pipe or pipe PLLs if needed */
1979         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
1980             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1981                 val &= ~PIPECONF_ENABLE;
1982
1983         I915_WRITE(reg, val);
1984         if ((val & PIPECONF_ENABLE) == 0)
1985                 intel_wait_for_pipe_off(crtc);
1986 }
1987
1988 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1989 {
1990         return IS_GEN2(dev_priv) ? 2048 : 4096;
1991 }
1992
1993 static unsigned int
1994 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1995 {
1996         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1997         unsigned int cpp = fb->format->cpp[plane];
1998
1999         switch (fb->modifier) {
2000         case DRM_FORMAT_MOD_LINEAR:
2001                 return cpp;
2002         case I915_FORMAT_MOD_X_TILED:
2003                 if (IS_GEN2(dev_priv))
2004                         return 128;
2005                 else
2006                         return 512;
2007         case I915_FORMAT_MOD_Y_TILED:
2008                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2009                         return 128;
2010                 else
2011                         return 512;
2012         case I915_FORMAT_MOD_Yf_TILED:
2013                 switch (cpp) {
2014                 case 1:
2015                         return 64;
2016                 case 2:
2017                 case 4:
2018                         return 128;
2019                 case 8:
2020                 case 16:
2021                         return 256;
2022                 default:
2023                         MISSING_CASE(cpp);
2024                         return cpp;
2025                 }
2026                 break;
2027         default:
2028                 MISSING_CASE(fb->modifier);
2029                 return cpp;
2030         }
2031 }
2032
2033 static unsigned int
2034 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2035 {
2036         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2037                 return 1;
2038         else
2039                 return intel_tile_size(to_i915(fb->dev)) /
2040                         intel_tile_width_bytes(fb, plane);
2041 }
2042
2043 /* Return the tile dimensions in pixel units */
2044 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2045                             unsigned int *tile_width,
2046                             unsigned int *tile_height)
2047 {
2048         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2049         unsigned int cpp = fb->format->cpp[plane];
2050
2051         *tile_width = tile_width_bytes / cpp;
2052         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2053 }
2054
2055 unsigned int
2056 intel_fb_align_height(const struct drm_framebuffer *fb,
2057                       int plane, unsigned int height)
2058 {
2059         unsigned int tile_height = intel_tile_height(fb, plane);
2060
2061         return ALIGN(height, tile_height);
2062 }
2063
2064 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2065 {
2066         unsigned int size = 0;
2067         int i;
2068
2069         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2070                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2071
2072         return size;
2073 }
2074
2075 static void
2076 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2077                         const struct drm_framebuffer *fb,
2078                         unsigned int rotation)
2079 {
2080         view->type = I915_GGTT_VIEW_NORMAL;
2081         if (drm_rotation_90_or_270(rotation)) {
2082                 view->type = I915_GGTT_VIEW_ROTATED;
2083                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2084         }
2085 }
2086
2087 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2088 {
2089         if (INTEL_INFO(dev_priv)->gen >= 9)
2090                 return 256 * 1024;
2091         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2092                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2093                 return 128 * 1024;
2094         else if (INTEL_INFO(dev_priv)->gen >= 4)
2095                 return 4 * 1024;
2096         else
2097                 return 0;
2098 }
2099
2100 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2101                                          int plane)
2102 {
2103         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2104
2105         /* AUX_DIST needs only 4K alignment */
2106         if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2107                 return 4096;
2108
2109         switch (fb->modifier) {
2110         case DRM_FORMAT_MOD_LINEAR:
2111                 return intel_linear_alignment(dev_priv);
2112         case I915_FORMAT_MOD_X_TILED:
2113                 if (INTEL_GEN(dev_priv) >= 9)
2114                         return 256 * 1024;
2115                 return 0;
2116         case I915_FORMAT_MOD_Y_TILED:
2117         case I915_FORMAT_MOD_Yf_TILED:
2118                 return 1 * 1024 * 1024;
2119         default:
2120                 MISSING_CASE(fb->modifier);
2121                 return 0;
2122         }
2123 }
2124
2125 struct i915_vma *
2126 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2127 {
2128         struct drm_device *dev = fb->dev;
2129         struct drm_i915_private *dev_priv = to_i915(dev);
2130         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2131         struct i915_ggtt_view view;
2132         struct i915_vma *vma;
2133         u32 alignment;
2134
2135         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2136
2137         alignment = intel_surf_alignment(fb, 0);
2138
2139         intel_fill_fb_ggtt_view(&view, fb, rotation);
2140
2141         /* Note that the w/a also requires 64 PTE of padding following the
2142          * bo. We currently fill all unused PTE with the shadow page and so
2143          * we should always have valid PTE following the scanout preventing
2144          * the VT-d warning.
2145          */
2146         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2147                 alignment = 256 * 1024;
2148
2149         /*
2150          * Global gtt pte registers are special registers which actually forward
2151          * writes to a chunk of system memory. Which means that there is no risk
2152          * that the register values disappear as soon as we call
2153          * intel_runtime_pm_put(), so it is correct to wrap only the
2154          * pin/unpin/fence and not more.
2155          */
2156         intel_runtime_pm_get(dev_priv);
2157
2158         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2159         if (IS_ERR(vma))
2160                 goto err;
2161
2162         if (i915_vma_is_map_and_fenceable(vma)) {
2163                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2164                  * fence, whereas 965+ only requires a fence if using
2165                  * framebuffer compression.  For simplicity, we always, when
2166                  * possible, install a fence as the cost is not that onerous.
2167                  *
2168                  * If we fail to fence the tiled scanout, then either the
2169                  * modeset will reject the change (which is highly unlikely as
2170                  * the affected systems, all but one, do not have unmappable
2171                  * space) or we will not be able to enable full powersaving
2172                  * techniques (also likely not to apply due to various limits
2173                  * FBC and the like impose on the size of the buffer, which
2174                  * presumably we violated anyway with this unmappable buffer).
2175                  * Anyway, it is presumably better to stumble onwards with
2176                  * something and try to run the system in a "less than optimal"
2177                  * mode that matches the user configuration.
2178                  */
2179                 if (i915_vma_get_fence(vma) == 0)
2180                         i915_vma_pin_fence(vma);
2181         }
2182
2183         i915_vma_get(vma);
2184 err:
2185         intel_runtime_pm_put(dev_priv);
2186         return vma;
2187 }
2188
2189 void intel_unpin_fb_vma(struct i915_vma *vma)
2190 {
2191         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2192
2193         i915_vma_unpin_fence(vma);
2194         i915_gem_object_unpin_from_display_plane(vma);
2195         i915_vma_put(vma);
2196 }
2197
2198 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2199                           unsigned int rotation)
2200 {
2201         if (drm_rotation_90_or_270(rotation))
2202                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2203         else
2204                 return fb->pitches[plane];
2205 }
2206
2207 /*
2208  * Convert the x/y offsets into a linear offset.
2209  * Only valid with 0/180 degree rotation, which is fine since linear
2210  * offset is only used with linear buffers on pre-hsw and tiled buffers
2211  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2212  */
2213 u32 intel_fb_xy_to_linear(int x, int y,
2214                           const struct intel_plane_state *state,
2215                           int plane)
2216 {
2217         const struct drm_framebuffer *fb = state->base.fb;
2218         unsigned int cpp = fb->format->cpp[plane];
2219         unsigned int pitch = fb->pitches[plane];
2220
2221         return y * pitch + x * cpp;
2222 }
2223
2224 /*
2225  * Add the x/y offsets derived from fb->offsets[] to the user
2226  * specified plane src x/y offsets. The resulting x/y offsets
2227  * specify the start of scanout from the beginning of the gtt mapping.
2228  */
2229 void intel_add_fb_offsets(int *x, int *y,
2230                           const struct intel_plane_state *state,
2231                           int plane)
2232
2233 {
2234         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2235         unsigned int rotation = state->base.rotation;
2236
2237         if (drm_rotation_90_or_270(rotation)) {
2238                 *x += intel_fb->rotated[plane].x;
2239                 *y += intel_fb->rotated[plane].y;
2240         } else {
2241                 *x += intel_fb->normal[plane].x;
2242                 *y += intel_fb->normal[plane].y;
2243         }
2244 }
2245
2246 /*
2247  * Input tile dimensions and pitch must already be
2248  * rotated to match x and y, and in pixel units.
2249  */
2250 static u32 _intel_adjust_tile_offset(int *x, int *y,
2251                                      unsigned int tile_width,
2252                                      unsigned int tile_height,
2253                                      unsigned int tile_size,
2254                                      unsigned int pitch_tiles,
2255                                      u32 old_offset,
2256                                      u32 new_offset)
2257 {
2258         unsigned int pitch_pixels = pitch_tiles * tile_width;
2259         unsigned int tiles;
2260
2261         WARN_ON(old_offset & (tile_size - 1));
2262         WARN_ON(new_offset & (tile_size - 1));
2263         WARN_ON(new_offset > old_offset);
2264
2265         tiles = (old_offset - new_offset) / tile_size;
2266
2267         *y += tiles / pitch_tiles * tile_height;
2268         *x += tiles % pitch_tiles * tile_width;
2269
2270         /* minimize x in case it got needlessly big */
2271         *y += *x / pitch_pixels * tile_height;
2272         *x %= pitch_pixels;
2273
2274         return new_offset;
2275 }
2276
2277 /*
2278  * Adjust the tile offset by moving the difference into
2279  * the x/y offsets.
2280  */
2281 static u32 intel_adjust_tile_offset(int *x, int *y,
2282                                     const struct intel_plane_state *state, int plane,
2283                                     u32 old_offset, u32 new_offset)
2284 {
2285         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2286         const struct drm_framebuffer *fb = state->base.fb;
2287         unsigned int cpp = fb->format->cpp[plane];
2288         unsigned int rotation = state->base.rotation;
2289         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2290
2291         WARN_ON(new_offset > old_offset);
2292
2293         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2294                 unsigned int tile_size, tile_width, tile_height;
2295                 unsigned int pitch_tiles;
2296
2297                 tile_size = intel_tile_size(dev_priv);
2298                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2299
2300                 if (drm_rotation_90_or_270(rotation)) {
2301                         pitch_tiles = pitch / tile_height;
2302                         swap(tile_width, tile_height);
2303                 } else {
2304                         pitch_tiles = pitch / (tile_width * cpp);
2305                 }
2306
2307                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2308                                           tile_size, pitch_tiles,
2309                                           old_offset, new_offset);
2310         } else {
2311                 old_offset += *y * pitch + *x * cpp;
2312
2313                 *y = (old_offset - new_offset) / pitch;
2314                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2315         }
2316
2317         return new_offset;
2318 }
2319
2320 /*
2321  * Computes the linear offset to the base tile and adjusts
2322  * x, y. bytes per pixel is assumed to be a power-of-two.
2323  *
2324  * In the 90/270 rotated case, x and y are assumed
2325  * to be already rotated to match the rotated GTT view, and
2326  * pitch is the tile_height aligned framebuffer height.
2327  *
2328  * This function is used when computing the derived information
2329  * under intel_framebuffer, so using any of that information
2330  * here is not allowed. Anything under drm_framebuffer can be
2331  * used. This is why the user has to pass in the pitch since it
2332  * is specified in the rotated orientation.
2333  */
2334 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2335                                       int *x, int *y,
2336                                       const struct drm_framebuffer *fb, int plane,
2337                                       unsigned int pitch,
2338                                       unsigned int rotation,
2339                                       u32 alignment)
2340 {
2341         uint64_t fb_modifier = fb->modifier;
2342         unsigned int cpp = fb->format->cpp[plane];
2343         u32 offset, offset_aligned;
2344
2345         if (alignment)
2346                 alignment--;
2347
2348         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2349                 unsigned int tile_size, tile_width, tile_height;
2350                 unsigned int tile_rows, tiles, pitch_tiles;
2351
2352                 tile_size = intel_tile_size(dev_priv);
2353                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2354
2355                 if (drm_rotation_90_or_270(rotation)) {
2356                         pitch_tiles = pitch / tile_height;
2357                         swap(tile_width, tile_height);
2358                 } else {
2359                         pitch_tiles = pitch / (tile_width * cpp);
2360                 }
2361
2362                 tile_rows = *y / tile_height;
2363                 *y %= tile_height;
2364
2365                 tiles = *x / tile_width;
2366                 *x %= tile_width;
2367
2368                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2369                 offset_aligned = offset & ~alignment;
2370
2371                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2372                                           tile_size, pitch_tiles,
2373                                           offset, offset_aligned);
2374         } else {
2375                 offset = *y * pitch + *x * cpp;
2376                 offset_aligned = offset & ~alignment;
2377
2378                 *y = (offset & alignment) / pitch;
2379                 *x = ((offset & alignment) - *y * pitch) / cpp;
2380         }
2381
2382         return offset_aligned;
2383 }
2384
2385 u32 intel_compute_tile_offset(int *x, int *y,
2386                               const struct intel_plane_state *state,
2387                               int plane)
2388 {
2389         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2390         const struct drm_framebuffer *fb = state->base.fb;
2391         unsigned int rotation = state->base.rotation;
2392         int pitch = intel_fb_pitch(fb, plane, rotation);
2393         u32 alignment = intel_surf_alignment(fb, plane);
2394
2395         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2396                                           rotation, alignment);
2397 }
2398
2399 /* Convert the fb->offset[] linear offset into x/y offsets */
2400 static void intel_fb_offset_to_xy(int *x, int *y,
2401                                   const struct drm_framebuffer *fb, int plane)
2402 {
2403         unsigned int cpp = fb->format->cpp[plane];
2404         unsigned int pitch = fb->pitches[plane];
2405         u32 linear_offset = fb->offsets[plane];
2406
2407         *y = linear_offset / pitch;
2408         *x = linear_offset % pitch / cpp;
2409 }
2410
2411 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2412 {
2413         switch (fb_modifier) {
2414         case I915_FORMAT_MOD_X_TILED:
2415                 return I915_TILING_X;
2416         case I915_FORMAT_MOD_Y_TILED:
2417                 return I915_TILING_Y;
2418         default:
2419                 return I915_TILING_NONE;
2420         }
2421 }
2422
2423 static int
2424 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2425                    struct drm_framebuffer *fb)
2426 {
2427         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2428         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2429         u32 gtt_offset_rotated = 0;
2430         unsigned int max_size = 0;
2431         int i, num_planes = fb->format->num_planes;
2432         unsigned int tile_size = intel_tile_size(dev_priv);
2433
2434         for (i = 0; i < num_planes; i++) {
2435                 unsigned int width, height;
2436                 unsigned int cpp, size;
2437                 u32 offset;
2438                 int x, y;
2439
2440                 cpp = fb->format->cpp[i];
2441                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2442                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2443
2444                 intel_fb_offset_to_xy(&x, &y, fb, i);
2445
2446                 /*
2447                  * The fence (if used) is aligned to the start of the object
2448                  * so having the framebuffer wrap around across the edge of the
2449                  * fenced region doesn't really work. We have no API to configure
2450                  * the fence start offset within the object (nor could we probably
2451                  * on gen2/3). So it's just easier if we just require that the
2452                  * fb layout agrees with the fence layout. We already check that the
2453                  * fb stride matches the fence stride elsewhere.
2454                  */
2455                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2456                     (x + width) * cpp > fb->pitches[i]) {
2457                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2458                                       i, fb->offsets[i]);
2459                         return -EINVAL;
2460                 }
2461
2462                 /*
2463                  * First pixel of the framebuffer from
2464                  * the start of the normal gtt mapping.
2465                  */
2466                 intel_fb->normal[i].x = x;
2467                 intel_fb->normal[i].y = y;
2468
2469                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2470                                                     fb, i, fb->pitches[i],
2471                                                     DRM_ROTATE_0, tile_size);
2472                 offset /= tile_size;
2473
2474                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2475                         unsigned int tile_width, tile_height;
2476                         unsigned int pitch_tiles;
2477                         struct drm_rect r;
2478
2479                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2480
2481                         rot_info->plane[i].offset = offset;
2482                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2483                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2484                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2485
2486                         intel_fb->rotated[i].pitch =
2487                                 rot_info->plane[i].height * tile_height;
2488
2489                         /* how many tiles does this plane need */
2490                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2491                         /*
2492                          * If the plane isn't horizontally tile aligned,
2493                          * we need one more tile.
2494                          */
2495                         if (x != 0)
2496                                 size++;
2497
2498                         /* rotate the x/y offsets to match the GTT view */
2499                         r.x1 = x;
2500                         r.y1 = y;
2501                         r.x2 = x + width;
2502                         r.y2 = y + height;
2503                         drm_rect_rotate(&r,
2504                                         rot_info->plane[i].width * tile_width,
2505                                         rot_info->plane[i].height * tile_height,
2506                                         DRM_ROTATE_270);
2507                         x = r.x1;
2508                         y = r.y1;
2509
2510                         /* rotate the tile dimensions to match the GTT view */
2511                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2512                         swap(tile_width, tile_height);
2513
2514                         /*
2515                          * We only keep the x/y offsets, so push all of the
2516                          * gtt offset into the x/y offsets.
2517                          */
2518                         _intel_adjust_tile_offset(&x, &y,
2519                                                   tile_width, tile_height,
2520                                                   tile_size, pitch_tiles,
2521                                                   gtt_offset_rotated * tile_size, 0);
2522
2523                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2524
2525                         /*
2526                          * First pixel of the framebuffer from
2527                          * the start of the rotated gtt mapping.
2528                          */
2529                         intel_fb->rotated[i].x = x;
2530                         intel_fb->rotated[i].y = y;
2531                 } else {
2532                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2533                                             x * cpp, tile_size);
2534                 }
2535
2536                 /* how many tiles in total needed in the bo */
2537                 max_size = max(max_size, offset + size);
2538         }
2539
2540         if (max_size * tile_size > intel_fb->obj->base.size) {
2541                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2542                               max_size * tile_size, intel_fb->obj->base.size);
2543                 return -EINVAL;
2544         }
2545
2546         return 0;
2547 }
2548
2549 static int i9xx_format_to_fourcc(int format)
2550 {
2551         switch (format) {
2552         case DISPPLANE_8BPP:
2553                 return DRM_FORMAT_C8;
2554         case DISPPLANE_BGRX555:
2555                 return DRM_FORMAT_XRGB1555;
2556         case DISPPLANE_BGRX565:
2557                 return DRM_FORMAT_RGB565;
2558         default:
2559         case DISPPLANE_BGRX888:
2560                 return DRM_FORMAT_XRGB8888;
2561         case DISPPLANE_RGBX888:
2562                 return DRM_FORMAT_XBGR8888;
2563         case DISPPLANE_BGRX101010:
2564                 return DRM_FORMAT_XRGB2101010;
2565         case DISPPLANE_RGBX101010:
2566                 return DRM_FORMAT_XBGR2101010;
2567         }
2568 }
2569
2570 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2571 {
2572         switch (format) {
2573         case PLANE_CTL_FORMAT_RGB_565:
2574                 return DRM_FORMAT_RGB565;
2575         default:
2576         case PLANE_CTL_FORMAT_XRGB_8888:
2577                 if (rgb_order) {
2578                         if (alpha)
2579                                 return DRM_FORMAT_ABGR8888;
2580                         else
2581                                 return DRM_FORMAT_XBGR8888;
2582                 } else {
2583                         if (alpha)
2584                                 return DRM_FORMAT_ARGB8888;
2585                         else
2586                                 return DRM_FORMAT_XRGB8888;
2587                 }
2588         case PLANE_CTL_FORMAT_XRGB_2101010:
2589                 if (rgb_order)
2590                         return DRM_FORMAT_XBGR2101010;
2591                 else
2592                         return DRM_FORMAT_XRGB2101010;
2593         }
2594 }
2595
2596 static bool
2597 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2598                               struct intel_initial_plane_config *plane_config)
2599 {
2600         struct drm_device *dev = crtc->base.dev;
2601         struct drm_i915_private *dev_priv = to_i915(dev);
2602         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2603         struct drm_i915_gem_object *obj = NULL;
2604         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2605         struct drm_framebuffer *fb = &plane_config->fb->base;
2606         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2607         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2608                                     PAGE_SIZE);
2609
2610         size_aligned -= base_aligned;
2611
2612         if (plane_config->size == 0)
2613                 return false;
2614
2615         /* If the FB is too big, just don't use it since fbdev is not very
2616          * important and we should probably use that space with FBC or other
2617          * features. */
2618         if (size_aligned * 2 > ggtt->stolen_usable_size)
2619                 return false;
2620
2621         mutex_lock(&dev->struct_mutex);
2622         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2623                                                              base_aligned,
2624                                                              base_aligned,
2625                                                              size_aligned);
2626         mutex_unlock(&dev->struct_mutex);
2627         if (!obj)
2628                 return false;
2629
2630         if (plane_config->tiling == I915_TILING_X)
2631                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2632
2633         mode_cmd.pixel_format = fb->format->format;
2634         mode_cmd.width = fb->width;
2635         mode_cmd.height = fb->height;
2636         mode_cmd.pitches[0] = fb->pitches[0];
2637         mode_cmd.modifier[0] = fb->modifier;
2638         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2639
2640         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2641                 DRM_DEBUG_KMS("intel fb init failed\n");
2642                 goto out_unref_obj;
2643         }
2644
2645
2646         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2647         return true;
2648
2649 out_unref_obj:
2650         i915_gem_object_put(obj);
2651         return false;
2652 }
2653
2654 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2655 static void
2656 update_state_fb(struct drm_plane *plane)
2657 {
2658         if (plane->fb == plane->state->fb)
2659                 return;
2660
2661         if (plane->state->fb)
2662                 drm_framebuffer_unreference(plane->state->fb);
2663         plane->state->fb = plane->fb;
2664         if (plane->state->fb)
2665                 drm_framebuffer_reference(plane->state->fb);
2666 }
2667
2668 static void
2669 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2670                         struct intel_plane_state *plane_state,
2671                         bool visible)
2672 {
2673         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2674
2675         plane_state->base.visible = visible;
2676
2677         /* FIXME pre-g4x don't work like this */
2678         if (visible) {
2679                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2680                 crtc_state->active_planes |= BIT(plane->id);
2681         } else {
2682                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2683                 crtc_state->active_planes &= ~BIT(plane->id);
2684         }
2685
2686         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2687                       crtc_state->base.crtc->name,
2688                       crtc_state->active_planes);
2689 }
2690
2691 static void
2692 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2693                              struct intel_initial_plane_config *plane_config)
2694 {
2695         struct drm_device *dev = intel_crtc->base.dev;
2696         struct drm_i915_private *dev_priv = to_i915(dev);
2697         struct drm_crtc *c;
2698         struct drm_i915_gem_object *obj;
2699         struct drm_plane *primary = intel_crtc->base.primary;
2700         struct drm_plane_state *plane_state = primary->state;
2701         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2702         struct intel_plane *intel_plane = to_intel_plane(primary);
2703         struct intel_plane_state *intel_state =
2704                 to_intel_plane_state(plane_state);
2705         struct drm_framebuffer *fb;
2706
2707         if (!plane_config->fb)
2708                 return;
2709
2710         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2711                 fb = &plane_config->fb->base;
2712                 goto valid_fb;
2713         }
2714
2715         kfree(plane_config->fb);
2716
2717         /*
2718          * Failed to alloc the obj, check to see if we should share
2719          * an fb with another CRTC instead
2720          */
2721         for_each_crtc(dev, c) {
2722                 struct intel_plane_state *state;
2723
2724                 if (c == &intel_crtc->base)
2725                         continue;
2726
2727                 if (!to_intel_crtc(c)->active)
2728                         continue;
2729
2730                 state = to_intel_plane_state(c->primary->state);
2731                 if (!state->vma)
2732                         continue;
2733
2734                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2735                         fb = c->primary->fb;
2736                         drm_framebuffer_reference(fb);
2737                         goto valid_fb;
2738                 }
2739         }
2740
2741         /*
2742          * We've failed to reconstruct the BIOS FB.  Current display state
2743          * indicates that the primary plane is visible, but has a NULL FB,
2744          * which will lead to problems later if we don't fix it up.  The
2745          * simplest solution is to just disable the primary plane now and
2746          * pretend the BIOS never had it enabled.
2747          */
2748         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2749                                 to_intel_plane_state(plane_state),
2750                                 false);
2751         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2752         trace_intel_disable_plane(primary, intel_crtc);
2753         intel_plane->disable_plane(primary, &intel_crtc->base);
2754
2755         return;
2756
2757 valid_fb:
2758         mutex_lock(&dev->struct_mutex);
2759         intel_state->vma =
2760                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2761         mutex_unlock(&dev->struct_mutex);
2762         if (IS_ERR(intel_state->vma)) {
2763                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2764                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2765
2766                 intel_state->vma = NULL;
2767                 drm_framebuffer_unreference(fb);
2768                 return;
2769         }
2770
2771         plane_state->src_x = 0;
2772         plane_state->src_y = 0;
2773         plane_state->src_w = fb->width << 16;
2774         plane_state->src_h = fb->height << 16;
2775
2776         plane_state->crtc_x = 0;
2777         plane_state->crtc_y = 0;
2778         plane_state->crtc_w = fb->width;
2779         plane_state->crtc_h = fb->height;
2780
2781         intel_state->base.src = drm_plane_state_src(plane_state);
2782         intel_state->base.dst = drm_plane_state_dest(plane_state);
2783
2784         obj = intel_fb_obj(fb);
2785         if (i915_gem_object_is_tiled(obj))
2786                 dev_priv->preserve_bios_swizzle = true;
2787
2788         drm_framebuffer_reference(fb);
2789         primary->fb = primary->state->fb = fb;
2790         primary->crtc = primary->state->crtc = &intel_crtc->base;
2791
2792         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2793                                 to_intel_plane_state(plane_state),
2794                                 true);
2795
2796         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2797                   &obj->frontbuffer_bits);
2798 }
2799
2800 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2801                                unsigned int rotation)
2802 {
2803         int cpp = fb->format->cpp[plane];
2804
2805         switch (fb->modifier) {
2806         case DRM_FORMAT_MOD_LINEAR:
2807         case I915_FORMAT_MOD_X_TILED:
2808                 switch (cpp) {
2809                 case 8:
2810                         return 4096;
2811                 case 4:
2812                 case 2:
2813                 case 1:
2814                         return 8192;
2815                 default:
2816                         MISSING_CASE(cpp);
2817                         break;
2818                 }
2819                 break;
2820         case I915_FORMAT_MOD_Y_TILED:
2821         case I915_FORMAT_MOD_Yf_TILED:
2822                 switch (cpp) {
2823                 case 8:
2824                         return 2048;
2825                 case 4:
2826                         return 4096;
2827                 case 2:
2828                 case 1:
2829                         return 8192;
2830                 default:
2831                         MISSING_CASE(cpp);
2832                         break;
2833                 }
2834                 break;
2835         default:
2836                 MISSING_CASE(fb->modifier);
2837         }
2838
2839         return 2048;
2840 }
2841
2842 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2843 {
2844         const struct drm_framebuffer *fb = plane_state->base.fb;
2845         unsigned int rotation = plane_state->base.rotation;
2846         int x = plane_state->base.src.x1 >> 16;
2847         int y = plane_state->base.src.y1 >> 16;
2848         int w = drm_rect_width(&plane_state->base.src) >> 16;
2849         int h = drm_rect_height(&plane_state->base.src) >> 16;
2850         int max_width = skl_max_plane_width(fb, 0, rotation);
2851         int max_height = 4096;
2852         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2853
2854         if (w > max_width || h > max_height) {
2855                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2856                               w, h, max_width, max_height);
2857                 return -EINVAL;
2858         }
2859
2860         intel_add_fb_offsets(&x, &y, plane_state, 0);
2861         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2862         alignment = intel_surf_alignment(fb, 0);
2863
2864         /*
2865          * AUX surface offset is specified as the distance from the
2866          * main surface offset, and it must be non-negative. Make
2867          * sure that is what we will get.
2868          */
2869         if (offset > aux_offset)
2870                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2871                                                   offset, aux_offset & ~(alignment - 1));
2872
2873         /*
2874          * When using an X-tiled surface, the plane blows up
2875          * if the x offset + width exceed the stride.
2876          *
2877          * TODO: linear and Y-tiled seem fine, Yf untested,
2878          */
2879         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2880                 int cpp = fb->format->cpp[0];
2881
2882                 while ((x + w) * cpp > fb->pitches[0]) {
2883                         if (offset == 0) {
2884                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2885                                 return -EINVAL;
2886                         }
2887
2888                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2889                                                           offset, offset - alignment);
2890                 }
2891         }
2892
2893         plane_state->main.offset = offset;
2894         plane_state->main.x = x;
2895         plane_state->main.y = y;
2896
2897         return 0;
2898 }
2899
2900 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2901 {
2902         const struct drm_framebuffer *fb = plane_state->base.fb;
2903         unsigned int rotation = plane_state->base.rotation;
2904         int max_width = skl_max_plane_width(fb, 1, rotation);
2905         int max_height = 4096;
2906         int x = plane_state->base.src.x1 >> 17;
2907         int y = plane_state->base.src.y1 >> 17;
2908         int w = drm_rect_width(&plane_state->base.src) >> 17;
2909         int h = drm_rect_height(&plane_state->base.src) >> 17;
2910         u32 offset;
2911
2912         intel_add_fb_offsets(&x, &y, plane_state, 1);
2913         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2914
2915         /* FIXME not quite sure how/if these apply to the chroma plane */
2916         if (w > max_width || h > max_height) {
2917                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2918                               w, h, max_width, max_height);
2919                 return -EINVAL;
2920         }
2921
2922         plane_state->aux.offset = offset;
2923         plane_state->aux.x = x;
2924         plane_state->aux.y = y;
2925
2926         return 0;
2927 }
2928
2929 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2930 {
2931         const struct drm_framebuffer *fb = plane_state->base.fb;
2932         unsigned int rotation = plane_state->base.rotation;
2933         int ret;
2934
2935         if (!plane_state->base.visible)
2936                 return 0;
2937
2938         /* Rotate src coordinates to match rotated GTT view */
2939         if (drm_rotation_90_or_270(rotation))
2940                 drm_rect_rotate(&plane_state->base.src,
2941                                 fb->width << 16, fb->height << 16,
2942                                 DRM_ROTATE_270);
2943
2944         /*
2945          * Handle the AUX surface first since
2946          * the main surface setup depends on it.
2947          */
2948         if (fb->format->format == DRM_FORMAT_NV12) {
2949                 ret = skl_check_nv12_aux_surface(plane_state);
2950                 if (ret)
2951                         return ret;
2952         } else {
2953                 plane_state->aux.offset = ~0xfff;
2954                 plane_state->aux.x = 0;
2955                 plane_state->aux.y = 0;
2956         }
2957
2958         ret = skl_check_main_surface(plane_state);
2959         if (ret)
2960                 return ret;
2961
2962         return 0;
2963 }
2964
2965 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2966                           const struct intel_plane_state *plane_state)
2967 {
2968         struct drm_i915_private *dev_priv =
2969                 to_i915(plane_state->base.plane->dev);
2970         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2971         const struct drm_framebuffer *fb = plane_state->base.fb;
2972         unsigned int rotation = plane_state->base.rotation;
2973         u32 dspcntr;
2974
2975         dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
2976
2977         if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
2978             IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2979                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2980
2981         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2982                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2983
2984         if (INTEL_GEN(dev_priv) < 4) {
2985                 if (crtc->pipe == PIPE_B)
2986                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2987         }
2988
2989         switch (fb->format->format) {
2990         case DRM_FORMAT_C8:
2991                 dspcntr |= DISPPLANE_8BPP;
2992                 break;
2993         case DRM_FORMAT_XRGB1555:
2994                 dspcntr |= DISPPLANE_BGRX555;
2995                 break;
2996         case DRM_FORMAT_RGB565:
2997                 dspcntr |= DISPPLANE_BGRX565;
2998                 break;
2999         case DRM_FORMAT_XRGB8888:
3000                 dspcntr |= DISPPLANE_BGRX888;
3001                 break;
3002         case DRM_FORMAT_XBGR8888:
3003                 dspcntr |= DISPPLANE_RGBX888;
3004                 break;
3005         case DRM_FORMAT_XRGB2101010:
3006                 dspcntr |= DISPPLANE_BGRX101010;
3007                 break;
3008         case DRM_FORMAT_XBGR2101010:
3009                 dspcntr |= DISPPLANE_RGBX101010;
3010                 break;
3011         default:
3012                 MISSING_CASE(fb->format->format);
3013                 return 0;
3014         }
3015
3016         if (INTEL_GEN(dev_priv) >= 4 &&
3017             fb->modifier == I915_FORMAT_MOD_X_TILED)
3018                 dspcntr |= DISPPLANE_TILED;
3019
3020         if (rotation & DRM_ROTATE_180)
3021                 dspcntr |= DISPPLANE_ROTATE_180;
3022
3023         if (rotation & DRM_REFLECT_X)
3024                 dspcntr |= DISPPLANE_MIRROR;
3025
3026         return dspcntr;
3027 }
3028
3029 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3030 {
3031         struct drm_i915_private *dev_priv =
3032                 to_i915(plane_state->base.plane->dev);
3033         int src_x = plane_state->base.src.x1 >> 16;
3034         int src_y = plane_state->base.src.y1 >> 16;
3035         u32 offset;
3036
3037         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3038
3039         if (INTEL_GEN(dev_priv) >= 4)
3040                 offset = intel_compute_tile_offset(&src_x, &src_y,
3041                                                    plane_state, 0);
3042         else
3043                 offset = 0;
3044
3045         /* HSW/BDW do this automagically in hardware */
3046         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3047                 unsigned int rotation = plane_state->base.rotation;
3048                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3049                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3050
3051                 if (rotation & DRM_ROTATE_180) {
3052                         src_x += src_w - 1;
3053                         src_y += src_h - 1;
3054                 } else if (rotation & DRM_REFLECT_X) {
3055                         src_x += src_w - 1;
3056                 }
3057         }
3058
3059         plane_state->main.offset = offset;
3060         plane_state->main.x = src_x;
3061         plane_state->main.y = src_y;
3062
3063         return 0;
3064 }
3065
3066 static void i9xx_update_primary_plane(struct drm_plane *primary,
3067                                       const struct intel_crtc_state *crtc_state,
3068                                       const struct intel_plane_state *plane_state)
3069 {
3070         struct drm_i915_private *dev_priv = to_i915(primary->dev);
3071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3072         struct drm_framebuffer *fb = plane_state->base.fb;
3073         int plane = intel_crtc->plane;
3074         u32 linear_offset;
3075         u32 dspcntr = plane_state->ctl;
3076         i915_reg_t reg = DSPCNTR(plane);
3077         int x = plane_state->main.x;
3078         int y = plane_state->main.y;
3079         unsigned long irqflags;
3080
3081         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3082
3083         if (INTEL_GEN(dev_priv) >= 4)
3084                 intel_crtc->dspaddr_offset = plane_state->main.offset;
3085         else
3086                 intel_crtc->dspaddr_offset = linear_offset;
3087
3088         intel_crtc->adjusted_x = x;
3089         intel_crtc->adjusted_y = y;
3090
3091         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3092
3093         if (INTEL_GEN(dev_priv) < 4) {
3094                 /* pipesrc and dspsize control the size that is scaled from,
3095                  * which should always be the user's requested size.
3096                  */
3097                 I915_WRITE_FW(DSPSIZE(plane),
3098                               ((crtc_state->pipe_src_h - 1) << 16) |
3099                               (crtc_state->pipe_src_w - 1));
3100                 I915_WRITE_FW(DSPPOS(plane), 0);
3101         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3102                 I915_WRITE_FW(PRIMSIZE(plane),
3103                               ((crtc_state->pipe_src_h - 1) << 16) |
3104                               (crtc_state->pipe_src_w - 1));
3105                 I915_WRITE_FW(PRIMPOS(plane), 0);
3106                 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3107         }
3108
3109         I915_WRITE_FW(reg, dspcntr);
3110
3111         I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3112         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3113                 I915_WRITE_FW(DSPSURF(plane),
3114                               intel_plane_ggtt_offset(plane_state) +
3115                               intel_crtc->dspaddr_offset);
3116                 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3117         } else if (INTEL_GEN(dev_priv) >= 4) {
3118                 I915_WRITE_FW(DSPSURF(plane),
3119                               intel_plane_ggtt_offset(plane_state) +
3120                               intel_crtc->dspaddr_offset);
3121                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3122                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3123         } else {
3124                 I915_WRITE_FW(DSPADDR(plane),
3125                               intel_plane_ggtt_offset(plane_state) +
3126                               intel_crtc->dspaddr_offset);
3127         }
3128         POSTING_READ_FW(reg);
3129
3130         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3131 }
3132
3133 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3134                                        struct drm_crtc *crtc)
3135 {
3136         struct drm_device *dev = crtc->dev;
3137         struct drm_i915_private *dev_priv = to_i915(dev);
3138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3139         int plane = intel_crtc->plane;
3140         unsigned long irqflags;
3141
3142         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3143
3144         I915_WRITE_FW(DSPCNTR(plane), 0);
3145         if (INTEL_INFO(dev_priv)->gen >= 4)
3146                 I915_WRITE_FW(DSPSURF(plane), 0);
3147         else
3148                 I915_WRITE_FW(DSPADDR(plane), 0);
3149         POSTING_READ_FW(DSPCNTR(plane));
3150
3151         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3152 }
3153
3154 static u32
3155 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3156 {
3157         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3158                 return 64;
3159         else
3160                 return intel_tile_width_bytes(fb, plane);
3161 }
3162
3163 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3164 {
3165         struct drm_device *dev = intel_crtc->base.dev;
3166         struct drm_i915_private *dev_priv = to_i915(dev);
3167
3168         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3169         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3170         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3171 }
3172
3173 /*
3174  * This function detaches (aka. unbinds) unused scalers in hardware
3175  */
3176 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3177 {
3178         struct intel_crtc_scaler_state *scaler_state;
3179         int i;
3180
3181         scaler_state = &intel_crtc->config->scaler_state;
3182
3183         /* loop through and disable scalers that aren't in use */
3184         for (i = 0; i < intel_crtc->num_scalers; i++) {
3185                 if (!scaler_state->scalers[i].in_use)
3186                         skl_detach_scaler(intel_crtc, i);
3187         }
3188 }
3189
3190 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3191                      unsigned int rotation)
3192 {
3193         u32 stride;
3194
3195         if (plane >= fb->format->num_planes)
3196                 return 0;
3197
3198         stride = intel_fb_pitch(fb, plane, rotation);
3199
3200         /*
3201          * The stride is either expressed as a multiple of 64 bytes chunks for
3202          * linear buffers or in number of tiles for tiled buffers.
3203          */
3204         if (drm_rotation_90_or_270(rotation))
3205                 stride /= intel_tile_height(fb, plane);
3206         else
3207                 stride /= intel_fb_stride_alignment(fb, plane);
3208
3209         return stride;
3210 }
3211
3212 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3213 {
3214         switch (pixel_format) {
3215         case DRM_FORMAT_C8:
3216                 return PLANE_CTL_FORMAT_INDEXED;
3217         case DRM_FORMAT_RGB565:
3218                 return PLANE_CTL_FORMAT_RGB_565;
3219         case DRM_FORMAT_XBGR8888:
3220                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3221         case DRM_FORMAT_XRGB8888:
3222                 return PLANE_CTL_FORMAT_XRGB_8888;
3223         /*
3224          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3225          * to be already pre-multiplied. We need to add a knob (or a different
3226          * DRM_FORMAT) for user-space to configure that.
3227          */
3228         case DRM_FORMAT_ABGR8888:
3229                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3230                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3231         case DRM_FORMAT_ARGB8888:
3232                 return PLANE_CTL_FORMAT_XRGB_8888 |
3233                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3234         case DRM_FORMAT_XRGB2101010:
3235                 return PLANE_CTL_FORMAT_XRGB_2101010;
3236         case DRM_FORMAT_XBGR2101010:
3237                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3238         case DRM_FORMAT_YUYV:
3239                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3240         case DRM_FORMAT_YVYU:
3241                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3242         case DRM_FORMAT_UYVY:
3243                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3244         case DRM_FORMAT_VYUY:
3245                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3246         default:
3247                 MISSING_CASE(pixel_format);
3248         }
3249
3250         return 0;
3251 }
3252
3253 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3254 {
3255         switch (fb_modifier) {
3256         case DRM_FORMAT_MOD_LINEAR:
3257                 break;
3258         case I915_FORMAT_MOD_X_TILED:
3259                 return PLANE_CTL_TILED_X;
3260         case I915_FORMAT_MOD_Y_TILED:
3261                 return PLANE_CTL_TILED_Y;
3262         case I915_FORMAT_MOD_Yf_TILED:
3263                 return PLANE_CTL_TILED_YF;
3264         default:
3265                 MISSING_CASE(fb_modifier);
3266         }
3267
3268         return 0;
3269 }
3270
3271 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3272 {
3273         switch (rotation) {
3274         case DRM_ROTATE_0:
3275                 break;
3276         /*
3277          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3278          * while i915 HW rotation is clockwise, thats why this swapping.
3279          */
3280         case DRM_ROTATE_90:
3281                 return PLANE_CTL_ROTATE_270;
3282         case DRM_ROTATE_180:
3283                 return PLANE_CTL_ROTATE_180;
3284         case DRM_ROTATE_270:
3285                 return PLANE_CTL_ROTATE_90;
3286         default:
3287                 MISSING_CASE(rotation);
3288         }
3289
3290         return 0;
3291 }
3292
3293 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3294                   const struct intel_plane_state *plane_state)
3295 {
3296         struct drm_i915_private *dev_priv =
3297                 to_i915(plane_state->base.plane->dev);
3298         const struct drm_framebuffer *fb = plane_state->base.fb;
3299         unsigned int rotation = plane_state->base.rotation;
3300         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3301         u32 plane_ctl;
3302
3303         plane_ctl = PLANE_CTL_ENABLE;
3304
3305         if (!IS_GEMINILAKE(dev_priv)) {
3306                 plane_ctl |=
3307                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3308                         PLANE_CTL_PIPE_CSC_ENABLE |
3309                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3310         }
3311
3312         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3313         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3314         plane_ctl |= skl_plane_ctl_rotation(rotation);
3315
3316         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3317                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3318         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3319                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3320
3321         return plane_ctl;
3322 }
3323
3324 static void skylake_update_primary_plane(struct drm_plane *plane,
3325                                          const struct intel_crtc_state *crtc_state,
3326                                          const struct intel_plane_state *plane_state)
3327 {
3328         struct drm_device *dev = plane->dev;
3329         struct drm_i915_private *dev_priv = to_i915(dev);
3330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3331         struct drm_framebuffer *fb = plane_state->base.fb;
3332         enum plane_id plane_id = to_intel_plane(plane)->id;
3333         enum pipe pipe = to_intel_plane(plane)->pipe;
3334         u32 plane_ctl = plane_state->ctl;
3335         unsigned int rotation = plane_state->base.rotation;
3336         u32 stride = skl_plane_stride(fb, 0, rotation);
3337         u32 surf_addr = plane_state->main.offset;
3338         int scaler_id = plane_state->scaler_id;
3339         int src_x = plane_state->main.x;
3340         int src_y = plane_state->main.y;
3341         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3342         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3343         int dst_x = plane_state->base.dst.x1;
3344         int dst_y = plane_state->base.dst.y1;
3345         int dst_w = drm_rect_width(&plane_state->base.dst);
3346         int dst_h = drm_rect_height(&plane_state->base.dst);
3347         unsigned long irqflags;
3348
3349         /* Sizes are 0 based */
3350         src_w--;
3351         src_h--;
3352         dst_w--;
3353         dst_h--;
3354
3355         intel_crtc->dspaddr_offset = surf_addr;
3356
3357         intel_crtc->adjusted_x = src_x;
3358         intel_crtc->adjusted_y = src_y;
3359
3360         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3361
3362         if (IS_GEMINILAKE(dev_priv)) {
3363                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3364                               PLANE_COLOR_PIPE_GAMMA_ENABLE |
3365                               PLANE_COLOR_PIPE_CSC_ENABLE |
3366                               PLANE_COLOR_PLANE_GAMMA_DISABLE);
3367         }
3368
3369         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3370         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3371         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3372         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3373
3374         if (scaler_id >= 0) {
3375                 uint32_t ps_ctrl = 0;
3376
3377                 WARN_ON(!dst_w || !dst_h);
3378                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3379                         crtc_state->scaler_state.scalers[scaler_id].mode;
3380                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3381                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3382                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3383                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3384                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3385         } else {
3386                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3387         }
3388
3389         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3390                       intel_plane_ggtt_offset(plane_state) + surf_addr);
3391
3392         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3393
3394         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3395 }
3396
3397 static void skylake_disable_primary_plane(struct drm_plane *primary,
3398                                           struct drm_crtc *crtc)
3399 {
3400         struct drm_device *dev = crtc->dev;
3401         struct drm_i915_private *dev_priv = to_i915(dev);
3402         enum plane_id plane_id = to_intel_plane(primary)->id;
3403         enum pipe pipe = to_intel_plane(primary)->pipe;
3404         unsigned long irqflags;
3405
3406         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3407
3408         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3409         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3410         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3411
3412         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3413 }
3414
3415 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3416 static int
3417 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3418                            int x, int y, enum mode_set_atomic state)
3419 {
3420         /* Support for kgdboc is disabled, this needs a major rework. */
3421         DRM_ERROR("legacy panic handler not supported any more.\n");
3422
3423         return -ENODEV;
3424 }
3425
3426 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3427 {
3428         struct intel_crtc *crtc;
3429
3430         for_each_intel_crtc(&dev_priv->drm, crtc)
3431                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3432 }
3433
3434 static void intel_update_primary_planes(struct drm_device *dev)
3435 {
3436         struct drm_crtc *crtc;
3437
3438         for_each_crtc(dev, crtc) {
3439                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3440                 struct intel_plane_state *plane_state =
3441                         to_intel_plane_state(plane->base.state);
3442
3443                 if (plane_state->base.visible) {
3444                         trace_intel_update_plane(&plane->base,
3445                                                  to_intel_crtc(crtc));
3446
3447                         plane->update_plane(&plane->base,
3448                                             to_intel_crtc_state(crtc->state),
3449                                             plane_state);
3450                 }
3451         }
3452 }
3453
3454 static int
3455 __intel_display_resume(struct drm_device *dev,
3456                        struct drm_atomic_state *state,
3457                        struct drm_modeset_acquire_ctx *ctx)
3458 {
3459         struct drm_crtc_state *crtc_state;
3460         struct drm_crtc *crtc;
3461         int i, ret;
3462
3463         intel_modeset_setup_hw_state(dev);
3464         i915_redisable_vga(to_i915(dev));
3465
3466         if (!state)
3467                 return 0;
3468
3469         /*
3470          * We've duplicated the state, pointers to the old state are invalid.
3471          *
3472          * Don't attempt to use the old state until we commit the duplicated state.
3473          */
3474         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3475                 /*
3476                  * Force recalculation even if we restore
3477                  * current state. With fast modeset this may not result
3478                  * in a modeset when the state is compatible.
3479                  */
3480                 crtc_state->mode_changed = true;
3481         }
3482
3483         /* ignore any reset values/BIOS leftovers in the WM registers */
3484         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3485                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3486
3487         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3488
3489         WARN_ON(ret == -EDEADLK);
3490         return ret;
3491 }
3492
3493 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3494 {
3495         return intel_has_gpu_reset(dev_priv) &&
3496                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3497 }
3498
3499 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3500 {
3501         struct drm_device *dev = &dev_priv->drm;
3502         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3503         struct drm_atomic_state *state;
3504         int ret;
3505
3506         /*
3507          * Need mode_config.mutex so that we don't
3508          * trample ongoing ->detect() and whatnot.
3509          */
3510         mutex_lock(&dev->mode_config.mutex);
3511         drm_modeset_acquire_init(ctx, 0);
3512         while (1) {
3513                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3514                 if (ret != -EDEADLK)
3515                         break;
3516
3517                 drm_modeset_backoff(ctx);
3518         }
3519
3520         /* reset doesn't touch the display, but flips might get nuked anyway, */
3521         if (!i915.force_reset_modeset_test &&
3522             !gpu_reset_clobbers_display(dev_priv))
3523                 return;
3524
3525         /*
3526          * Disabling the crtcs gracefully seems nicer. Also the
3527          * g33 docs say we should at least disable all the planes.
3528          */
3529         state = drm_atomic_helper_duplicate_state(dev, ctx);
3530         if (IS_ERR(state)) {
3531                 ret = PTR_ERR(state);
3532                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3533                 return;
3534         }
3535
3536         ret = drm_atomic_helper_disable_all(dev, ctx);
3537         if (ret) {
3538                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3539                 drm_atomic_state_put(state);
3540                 return;
3541         }
3542
3543         dev_priv->modeset_restore_state = state;
3544         state->acquire_ctx = ctx;
3545 }
3546
3547 void intel_finish_reset(struct drm_i915_private *dev_priv)
3548 {
3549         struct drm_device *dev = &dev_priv->drm;
3550         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3551         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3552         int ret;
3553
3554         /*
3555          * Flips in the rings will be nuked by the reset,
3556          * so complete all pending flips so that user space
3557          * will get its events and not get stuck.
3558          */
3559         intel_complete_page_flips(dev_priv);
3560
3561         dev_priv->modeset_restore_state = NULL;
3562
3563         /* reset doesn't touch the display */
3564         if (!gpu_reset_clobbers_display(dev_priv)) {
3565                 if (!state) {
3566                         /*
3567                          * Flips in the rings have been nuked by the reset,
3568                          * so update the base address of all primary
3569                          * planes to the the last fb to make sure we're
3570                          * showing the correct fb after a reset.
3571                          *
3572                          * FIXME: Atomic will make this obsolete since we won't schedule
3573                          * CS-based flips (which might get lost in gpu resets) any more.
3574                          */
3575                         intel_update_primary_planes(dev);
3576                 } else {
3577                         ret = __intel_display_resume(dev, state, ctx);
3578                         if (ret)
3579                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3580                 }
3581         } else {
3582                 /*
3583                  * The display has been reset as well,
3584                  * so need a full re-initialization.
3585                  */
3586                 intel_runtime_pm_disable_interrupts(dev_priv);
3587                 intel_runtime_pm_enable_interrupts(dev_priv);
3588
3589                 intel_pps_unlock_regs_wa(dev_priv);
3590                 intel_modeset_init_hw(dev);
3591
3592                 spin_lock_irq(&dev_priv->irq_lock);
3593                 if (dev_priv->display.hpd_irq_setup)
3594                         dev_priv->display.hpd_irq_setup(dev_priv);
3595                 spin_unlock_irq(&dev_priv->irq_lock);
3596
3597                 ret = __intel_display_resume(dev, state, ctx);
3598                 if (ret)
3599                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3600
3601                 intel_hpd_init(dev_priv);
3602         }
3603
3604         if (state)
3605                 drm_atomic_state_put(state);
3606         drm_modeset_drop_locks(ctx);
3607         drm_modeset_acquire_fini(ctx);
3608         mutex_unlock(&dev->mode_config.mutex);
3609 }
3610
3611 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3612 {
3613         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3614
3615         if (i915_reset_backoff(error))
3616                 return true;
3617
3618         if (crtc->reset_count != i915_reset_count(error))
3619                 return true;
3620
3621         return false;
3622 }
3623
3624 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3625 {
3626         struct drm_device *dev = crtc->dev;
3627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3628         bool pending;
3629
3630         if (abort_flip_on_reset(intel_crtc))
3631                 return false;
3632
3633         spin_lock_irq(&dev->event_lock);
3634         pending = to_intel_crtc(crtc)->flip_work != NULL;
3635         spin_unlock_irq(&dev->event_lock);
3636
3637         return pending;
3638 }
3639
3640 static void intel_update_pipe_config(struct intel_crtc *crtc,
3641                                      struct intel_crtc_state *old_crtc_state)
3642 {
3643         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3644         struct intel_crtc_state *pipe_config =
3645                 to_intel_crtc_state(crtc->base.state);
3646
3647         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3648         crtc->base.mode = crtc->base.state->mode;
3649
3650         /*
3651          * Update pipe size and adjust fitter if needed: the reason for this is
3652          * that in compute_mode_changes we check the native mode (not the pfit
3653          * mode) to see if we can flip rather than do a full mode set. In the
3654          * fastboot case, we'll flip, but if we don't update the pipesrc and
3655          * pfit state, we'll end up with a big fb scanned out into the wrong
3656          * sized surface.
3657          */
3658
3659         I915_WRITE(PIPESRC(crtc->pipe),
3660                    ((pipe_config->pipe_src_w - 1) << 16) |
3661                    (pipe_config->pipe_src_h - 1));
3662
3663         /* on skylake this is done by detaching scalers */
3664         if (INTEL_GEN(dev_priv) >= 9) {
3665                 skl_detach_scalers(crtc);
3666
3667                 if (pipe_config->pch_pfit.enabled)
3668                         skylake_pfit_enable(crtc);
3669         } else if (HAS_PCH_SPLIT(dev_priv)) {
3670                 if (pipe_config->pch_pfit.enabled)
3671                         ironlake_pfit_enable(crtc);
3672                 else if (old_crtc_state->pch_pfit.enabled)
3673                         ironlake_pfit_disable(crtc, true);
3674         }
3675 }
3676
3677 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3678 {
3679         struct drm_device *dev = crtc->base.dev;
3680         struct drm_i915_private *dev_priv = to_i915(dev);
3681         int pipe = crtc->pipe;
3682         i915_reg_t reg;
3683         u32 temp;
3684
3685         /* enable normal train */
3686         reg = FDI_TX_CTL(pipe);
3687         temp = I915_READ(reg);
3688         if (IS_IVYBRIDGE(dev_priv)) {
3689                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3690                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3691         } else {
3692                 temp &= ~FDI_LINK_TRAIN_NONE;
3693                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3694         }
3695         I915_WRITE(reg, temp);
3696
3697         reg = FDI_RX_CTL(pipe);
3698         temp = I915_READ(reg);
3699         if (HAS_PCH_CPT(dev_priv)) {
3700                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3701                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3702         } else {
3703                 temp &= ~FDI_LINK_TRAIN_NONE;
3704                 temp |= FDI_LINK_TRAIN_NONE;
3705         }
3706         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3707
3708         /* wait one idle pattern time */
3709         POSTING_READ(reg);
3710         udelay(1000);
3711
3712         /* IVB wants error correction enabled */
3713         if (IS_IVYBRIDGE(dev_priv))
3714                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3715                            FDI_FE_ERRC_ENABLE);
3716 }
3717
3718 /* The FDI link training functions for ILK/Ibexpeak. */
3719 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3720                                     const struct intel_crtc_state *crtc_state)
3721 {
3722         struct drm_device *dev = crtc->base.dev;
3723         struct drm_i915_private *dev_priv = to_i915(dev);
3724         int pipe = crtc->pipe;
3725         i915_reg_t reg;
3726         u32 temp, tries;
3727
3728         /* FDI needs bits from pipe first */
3729         assert_pipe_enabled(dev_priv, pipe);
3730
3731         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3732            for train result */
3733         reg = FDI_RX_IMR(pipe);
3734         temp = I915_READ(reg);
3735         temp &= ~FDI_RX_SYMBOL_LOCK;
3736         temp &= ~FDI_RX_BIT_LOCK;
3737         I915_WRITE(reg, temp);
3738         I915_READ(reg);
3739         udelay(150);
3740
3741         /* enable CPU FDI TX and PCH FDI RX */
3742         reg = FDI_TX_CTL(pipe);
3743         temp = I915_READ(reg);
3744         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3745         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3746         temp &= ~FDI_LINK_TRAIN_NONE;
3747         temp |= FDI_LINK_TRAIN_PATTERN_1;
3748         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3749
3750         reg = FDI_RX_CTL(pipe);
3751         temp = I915_READ(reg);
3752         temp &= ~FDI_LINK_TRAIN_NONE;
3753         temp |= FDI_LINK_TRAIN_PATTERN_1;
3754         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3755
3756         POSTING_READ(reg);
3757         udelay(150);
3758
3759         /* Ironlake workaround, enable clock pointer after FDI enable*/
3760         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3761         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3762                    FDI_RX_PHASE_SYNC_POINTER_EN);
3763
3764         reg = FDI_RX_IIR(pipe);
3765         for (tries = 0; tries < 5; tries++) {
3766                 temp = I915_READ(reg);
3767                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3768
3769                 if ((temp & FDI_RX_BIT_LOCK)) {
3770                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3771                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3772                         break;
3773                 }
3774         }
3775         if (tries == 5)
3776                 DRM_ERROR("FDI train 1 fail!\n");
3777
3778         /* Train 2 */
3779         reg = FDI_TX_CTL(pipe);
3780         temp = I915_READ(reg);
3781         temp &= ~FDI_LINK_TRAIN_NONE;
3782         temp |= FDI_LINK_TRAIN_PATTERN_2;
3783         I915_WRITE(reg, temp);
3784
3785         reg = FDI_RX_CTL(pipe);
3786         temp = I915_READ(reg);
3787         temp &= ~FDI_LINK_TRAIN_NONE;
3788         temp |= FDI_LINK_TRAIN_PATTERN_2;
3789         I915_WRITE(reg, temp);
3790
3791         POSTING_READ(reg);
3792         udelay(150);
3793
3794         reg = FDI_RX_IIR(pipe);
3795         for (tries = 0; tries < 5; tries++) {
3796                 temp = I915_READ(reg);
3797                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3798
3799                 if (temp & FDI_RX_SYMBOL_LOCK) {
3800                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3801                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3802                         break;
3803                 }
3804         }
3805         if (tries == 5)
3806                 DRM_ERROR("FDI train 2 fail!\n");
3807
3808         DRM_DEBUG_KMS("FDI train done\n");
3809
3810 }
3811
3812 static const int snb_b_fdi_train_param[] = {
3813         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3814         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3815         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3816         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3817 };
3818
3819 /* The FDI link training functions for SNB/Cougarpoint. */
3820 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3821                                 const struct intel_crtc_state *crtc_state)
3822 {
3823         struct drm_device *dev = crtc->base.dev;
3824         struct drm_i915_private *dev_priv = to_i915(dev);
3825         int pipe = crtc->pipe;
3826         i915_reg_t reg;
3827         u32 temp, i, retry;
3828
3829         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3830            for train result */
3831         reg = FDI_RX_IMR(pipe);
3832         temp = I915_READ(reg);
3833         temp &= ~FDI_RX_SYMBOL_LOCK;
3834         temp &= ~FDI_RX_BIT_LOCK;
3835         I915_WRITE(reg, temp);
3836
3837         POSTING_READ(reg);
3838         udelay(150);
3839
3840         /* enable CPU FDI TX and PCH FDI RX */
3841         reg = FDI_TX_CTL(pipe);
3842         temp = I915_READ(reg);
3843         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3844         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3845         temp &= ~FDI_LINK_TRAIN_NONE;
3846         temp |= FDI_LINK_TRAIN_PATTERN_1;
3847         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3848         /* SNB-B */
3849         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3850         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3851
3852         I915_WRITE(FDI_RX_MISC(pipe),
3853                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3854
3855         reg = FDI_RX_CTL(pipe);
3856         temp = I915_READ(reg);
3857         if (HAS_PCH_CPT(dev_priv)) {
3858                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3859                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3860         } else {
3861                 temp &= ~FDI_LINK_TRAIN_NONE;
3862                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3863         }
3864         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3865
3866         POSTING_READ(reg);
3867         udelay(150);
3868
3869         for (i = 0; i < 4; i++) {
3870                 reg = FDI_TX_CTL(pipe);
3871                 temp = I915_READ(reg);
3872                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3873                 temp |= snb_b_fdi_train_param[i];
3874                 I915_WRITE(reg, temp);
3875
3876                 POSTING_READ(reg);
3877                 udelay(500);
3878
3879                 for (retry = 0; retry < 5; retry++) {
3880                         reg = FDI_RX_IIR(pipe);
3881                         temp = I915_READ(reg);
3882                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3883                         if (temp & FDI_RX_BIT_LOCK) {
3884                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3885                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3886                                 break;
3887                         }
3888                         udelay(50);
3889                 }
3890                 if (retry < 5)
3891                         break;
3892         }
3893         if (i == 4)
3894                 DRM_ERROR("FDI train 1 fail!\n");
3895
3896         /* Train 2 */
3897         reg = FDI_TX_CTL(pipe);
3898         temp = I915_READ(reg);
3899         temp &= ~FDI_LINK_TRAIN_NONE;
3900         temp |= FDI_LINK_TRAIN_PATTERN_2;
3901         if (IS_GEN6(dev_priv)) {
3902                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3903                 /* SNB-B */
3904                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3905         }
3906         I915_WRITE(reg, temp);
3907
3908         reg = FDI_RX_CTL(pipe);
3909         temp = I915_READ(reg);
3910         if (HAS_PCH_CPT(dev_priv)) {
3911                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3912                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3913         } else {
3914                 temp &= ~FDI_LINK_TRAIN_NONE;
3915                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3916         }
3917         I915_WRITE(reg, temp);
3918
3919         POSTING_READ(reg);
3920         udelay(150);
3921
3922         for (i = 0; i < 4; i++) {
3923                 reg = FDI_TX_CTL(pipe);
3924                 temp = I915_READ(reg);
3925                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3926                 temp |= snb_b_fdi_train_param[i];
3927                 I915_WRITE(reg, temp);
3928
3929                 POSTING_READ(reg);
3930                 udelay(500);
3931
3932                 for (retry = 0; retry < 5; retry++) {
3933                         reg = FDI_RX_IIR(pipe);
3934                         temp = I915_READ(reg);
3935                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3936                         if (temp & FDI_RX_SYMBOL_LOCK) {
3937                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3938                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3939                                 break;
3940                         }
3941                         udelay(50);
3942                 }
3943                 if (retry < 5)
3944                         break;
3945         }
3946         if (i == 4)
3947                 DRM_ERROR("FDI train 2 fail!\n");
3948
3949         DRM_DEBUG_KMS("FDI train done.\n");
3950 }
3951
3952 /* Manual link training for Ivy Bridge A0 parts */
3953 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3954                                       const struct intel_crtc_state *crtc_state)
3955 {
3956         struct drm_device *dev = crtc->base.dev;
3957         struct drm_i915_private *dev_priv = to_i915(dev);
3958         int pipe = crtc->pipe;
3959         i915_reg_t reg;
3960         u32 temp, i, j;
3961
3962         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3963            for train result */
3964         reg = FDI_RX_IMR(pipe);
3965         temp = I915_READ(reg);
3966         temp &= ~FDI_RX_SYMBOL_LOCK;
3967         temp &= ~FDI_RX_BIT_LOCK;
3968         I915_WRITE(reg, temp);
3969
3970         POSTING_READ(reg);
3971         udelay(150);
3972
3973         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3974                       I915_READ(FDI_RX_IIR(pipe)));
3975
3976         /* Try each vswing and preemphasis setting twice before moving on */
3977         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3978                 /* disable first in case we need to retry */
3979                 reg = FDI_TX_CTL(pipe);
3980                 temp = I915_READ(reg);
3981                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3982                 temp &= ~FDI_TX_ENABLE;
3983                 I915_WRITE(reg, temp);
3984
3985                 reg = FDI_RX_CTL(pipe);
3986                 temp = I915_READ(reg);
3987                 temp &= ~FDI_LINK_TRAIN_AUTO;
3988                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3989                 temp &= ~FDI_RX_ENABLE;
3990                 I915_WRITE(reg, temp);
3991
3992                 /* enable CPU FDI TX and PCH FDI RX */
3993                 reg = FDI_TX_CTL(pipe);
3994                 temp = I915_READ(reg);
3995                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3996                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3997                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3998                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3999                 temp |= snb_b_fdi_train_param[j/2];
4000                 temp |= FDI_COMPOSITE_SYNC;
4001                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4002
4003                 I915_WRITE(FDI_RX_MISC(pipe),
4004                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4005
4006                 reg = FDI_RX_CTL(pipe);
4007                 temp = I915_READ(reg);
4008                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4009                 temp |= FDI_COMPOSITE_SYNC;
4010                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4011
4012                 POSTING_READ(reg);
4013                 udelay(1); /* should be 0.5us */
4014
4015                 for (i = 0; i < 4; i++) {
4016                         reg = FDI_RX_IIR(pipe);
4017                         temp = I915_READ(reg);
4018                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4019
4020                         if (temp & FDI_RX_BIT_LOCK ||
4021                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4022                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4023                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4024                                               i);
4025                                 break;
4026                         }
4027                         udelay(1); /* should be 0.5us */
4028                 }
4029                 if (i == 4) {
4030                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4031                         continue;
4032                 }
4033
4034                 /* Train 2 */
4035                 reg = FDI_TX_CTL(pipe);
4036                 temp = I915_READ(reg);
4037                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4038                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4039                 I915_WRITE(reg, temp);
4040
4041                 reg = FDI_RX_CTL(pipe);
4042                 temp = I915_READ(reg);
4043                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4044                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4045                 I915_WRITE(reg, temp);
4046
4047                 POSTING_READ(reg);
4048                 udelay(2); /* should be 1.5us */
4049
4050                 for (i = 0; i < 4; i++) {
4051                         reg = FDI_RX_IIR(pipe);
4052                         temp = I915_READ(reg);
4053                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4054
4055                         if (temp & FDI_RX_SYMBOL_LOCK ||
4056                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4057                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4058                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4059                                               i);
4060                                 goto train_done;
4061                         }
4062                         udelay(2); /* should be 1.5us */
4063                 }
4064                 if (i == 4)
4065                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4066         }
4067
4068 train_done:
4069         DRM_DEBUG_KMS("FDI train done.\n");
4070 }
4071
4072 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4073 {
4074         struct drm_device *dev = intel_crtc->base.dev;
4075         struct drm_i915_private *dev_priv = to_i915(dev);
4076         int pipe = intel_crtc->pipe;
4077         i915_reg_t reg;
4078         u32 temp;
4079
4080         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4081         reg = FDI_RX_CTL(pipe);
4082         temp = I915_READ(reg);
4083         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4084         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4085         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4086         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4087
4088         POSTING_READ(reg);
4089         udelay(200);
4090
4091         /* Switch from Rawclk to PCDclk */
4092         temp = I915_READ(reg);
4093         I915_WRITE(reg, temp | FDI_PCDCLK);
4094
4095         POSTING_READ(reg);
4096         udelay(200);
4097
4098         /* Enable CPU FDI TX PLL, always on for Ironlake */
4099         reg = FDI_TX_CTL(pipe);
4100         temp = I915_READ(reg);
4101         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4102                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4103
4104                 POSTING_READ(reg);
4105                 udelay(100);
4106         }
4107 }
4108
4109 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4110 {
4111         struct drm_device *dev = intel_crtc->base.dev;
4112         struct drm_i915_private *dev_priv = to_i915(dev);
4113         int pipe = intel_crtc->pipe;
4114         i915_reg_t reg;
4115         u32 temp;
4116
4117         /* Switch from PCDclk to Rawclk */
4118         reg = FDI_RX_CTL(pipe);
4119         temp = I915_READ(reg);
4120         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4121
4122         /* Disable CPU FDI TX PLL */
4123         reg = FDI_TX_CTL(pipe);
4124         temp = I915_READ(reg);
4125         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4126
4127         POSTING_READ(reg);
4128         udelay(100);
4129
4130         reg = FDI_RX_CTL(pipe);
4131         temp = I915_READ(reg);
4132         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4133
4134         /* Wait for the clocks to turn off. */
4135         POSTING_READ(reg);
4136         udelay(100);
4137 }
4138
4139 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4140 {
4141         struct drm_device *dev = crtc->dev;
4142         struct drm_i915_private *dev_priv = to_i915(dev);
4143         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4144         int pipe = intel_crtc->pipe;
4145         i915_reg_t reg;
4146         u32 temp;
4147
4148         /* disable CPU FDI tx and PCH FDI rx */
4149         reg = FDI_TX_CTL(pipe);
4150         temp = I915_READ(reg);
4151         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4152         POSTING_READ(reg);
4153
4154         reg = FDI_RX_CTL(pipe);
4155         temp = I915_READ(reg);
4156         temp &= ~(0x7 << 16);
4157         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4158         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4159
4160         POSTING_READ(reg);
4161         udelay(100);
4162
4163         /* Ironlake workaround, disable clock pointer after downing FDI */
4164         if (HAS_PCH_IBX(dev_priv))
4165                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4166
4167         /* still set train pattern 1 */
4168         reg = FDI_TX_CTL(pipe);
4169         temp = I915_READ(reg);
4170         temp &= ~FDI_LINK_TRAIN_NONE;
4171         temp |= FDI_LINK_TRAIN_PATTERN_1;
4172         I915_WRITE(reg, temp);
4173
4174         reg = FDI_RX_CTL(pipe);
4175         temp = I915_READ(reg);
4176         if (HAS_PCH_CPT(dev_priv)) {
4177                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4178                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4179         } else {
4180                 temp &= ~FDI_LINK_TRAIN_NONE;
4181                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4182         }
4183         /* BPC in FDI rx is consistent with that in PIPECONF */
4184         temp &= ~(0x07 << 16);
4185         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4186         I915_WRITE(reg, temp);
4187
4188         POSTING_READ(reg);
4189         udelay(100);
4190 }
4191
4192 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4193 {
4194         struct intel_crtc *crtc;
4195
4196         /* Note that we don't need to be called with mode_config.lock here
4197          * as our list of CRTC objects is static for the lifetime of the
4198          * device and so cannot disappear as we iterate. Similarly, we can
4199          * happily treat the predicates as racy, atomic checks as userspace
4200          * cannot claim and pin a new fb without at least acquring the
4201          * struct_mutex and so serialising with us.
4202          */
4203         for_each_intel_crtc(&dev_priv->drm, crtc) {
4204                 if (atomic_read(&crtc->unpin_work_count) == 0)
4205                         continue;
4206
4207                 if (crtc->flip_work)
4208                         intel_wait_for_vblank(dev_priv, crtc->pipe);
4209
4210                 return true;
4211         }
4212
4213         return false;
4214 }
4215
4216 static void page_flip_completed(struct intel_crtc *intel_crtc)
4217 {
4218         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4219         struct intel_flip_work *work = intel_crtc->flip_work;
4220
4221         intel_crtc->flip_work = NULL;
4222
4223         if (work->event)
4224                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4225
4226         drm_crtc_vblank_put(&intel_crtc->base);
4227
4228         wake_up_all(&dev_priv->pending_flip_queue);
4229         trace_i915_flip_complete(intel_crtc->plane,
4230                                  work->pending_flip_obj);
4231
4232         queue_work(dev_priv->wq, &work->unpin_work);
4233 }
4234
4235 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4236 {
4237         struct drm_device *dev = crtc->dev;
4238         struct drm_i915_private *dev_priv = to_i915(dev);
4239         long ret;
4240
4241         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4242
4243         ret = wait_event_interruptible_timeout(
4244                                         dev_priv->pending_flip_queue,
4245                                         !intel_crtc_has_pending_flip(crtc),
4246                                         60*HZ);
4247
4248         if (ret < 0)
4249                 return ret;
4250
4251         if (ret == 0) {
4252                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4253                 struct intel_flip_work *work;
4254
4255                 spin_lock_irq(&dev->event_lock);
4256                 work = intel_crtc->flip_work;
4257                 if (work && !is_mmio_work(work)) {
4258                         WARN_ONCE(1, "Removing stuck page flip\n");
4259                         page_flip_completed(intel_crtc);
4260                 }
4261                 spin_unlock_irq(&dev->event_lock);
4262         }
4263
4264         return 0;
4265 }
4266
4267 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4268 {
4269         u32 temp;
4270
4271         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4272
4273         mutex_lock(&dev_priv->sb_lock);
4274
4275         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4276         temp |= SBI_SSCCTL_DISABLE;
4277         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4278
4279         mutex_unlock(&dev_priv->sb_lock);
4280 }
4281
4282 /* Program iCLKIP clock to the desired frequency */
4283 static void lpt_program_iclkip(struct intel_crtc *crtc)
4284 {
4285         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4286         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4287         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4288         u32 temp;
4289
4290         lpt_disable_iclkip(dev_priv);
4291
4292         /* The iCLK virtual clock root frequency is in MHz,
4293          * but the adjusted_mode->crtc_clock in in KHz. To get the
4294          * divisors, it is necessary to divide one by another, so we
4295          * convert the virtual clock precision to KHz here for higher
4296          * precision.
4297          */
4298         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4299                 u32 iclk_virtual_root_freq = 172800 * 1000;
4300                 u32 iclk_pi_range = 64;
4301                 u32 desired_divisor;
4302
4303                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4304                                                     clock << auxdiv);
4305                 divsel = (desired_divisor / iclk_pi_range) - 2;
4306                 phaseinc = desired_divisor % iclk_pi_range;
4307
4308                 /*
4309                  * Near 20MHz is a corner case which is
4310                  * out of range for the 7-bit divisor
4311                  */
4312                 if (divsel <= 0x7f)
4313                         break;
4314         }
4315
4316         /* This should not happen with any sane values */
4317         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4318                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4319         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4320                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4321
4322         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4323                         clock,
4324                         auxdiv,
4325                         divsel,
4326                         phasedir,
4327                         phaseinc);
4328
4329         mutex_lock(&dev_priv->sb_lock);
4330
4331         /* Program SSCDIVINTPHASE6 */
4332         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4333         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4334         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4335         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4336         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4337         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4338         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4339         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4340
4341         /* Program SSCAUXDIV */
4342         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4343         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4344         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4345         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4346
4347         /* Enable modulator and associated divider */
4348         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4349         temp &= ~SBI_SSCCTL_DISABLE;
4350         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4351
4352         mutex_unlock(&dev_priv->sb_lock);
4353
4354         /* Wait for initialization time */
4355         udelay(24);
4356
4357         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4358 }
4359
4360 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4361 {
4362         u32 divsel, phaseinc, auxdiv;
4363         u32 iclk_virtual_root_freq = 172800 * 1000;
4364         u32 iclk_pi_range = 64;
4365         u32 desired_divisor;
4366         u32 temp;
4367
4368         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4369                 return 0;
4370
4371         mutex_lock(&dev_priv->sb_lock);
4372
4373         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4374         if (temp & SBI_SSCCTL_DISABLE) {
4375                 mutex_unlock(&dev_priv->sb_lock);
4376                 return 0;
4377         }
4378
4379         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4380         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4381                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4382         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4383                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4384
4385         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4386         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4387                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4388
4389         mutex_unlock(&dev_priv->sb_lock);
4390
4391         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4392
4393         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4394                                  desired_divisor << auxdiv);
4395 }
4396
4397 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4398                                                 enum pipe pch_transcoder)
4399 {
4400         struct drm_device *dev = crtc->base.dev;
4401         struct drm_i915_private *dev_priv = to_i915(dev);
4402         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4403
4404         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4405                    I915_READ(HTOTAL(cpu_transcoder)));
4406         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4407                    I915_READ(HBLANK(cpu_transcoder)));
4408         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4409                    I915_READ(HSYNC(cpu_transcoder)));
4410
4411         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4412                    I915_READ(VTOTAL(cpu_transcoder)));
4413         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4414                    I915_READ(VBLANK(cpu_transcoder)));
4415         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4416                    I915_READ(VSYNC(cpu_transcoder)));
4417         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4418                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4419 }
4420
4421 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4422 {
4423         struct drm_i915_private *dev_priv = to_i915(dev);
4424         uint32_t temp;
4425
4426         temp = I915_READ(SOUTH_CHICKEN1);
4427         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4428                 return;
4429
4430         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4431         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4432
4433         temp &= ~FDI_BC_BIFURCATION_SELECT;
4434         if (enable)
4435                 temp |= FDI_BC_BIFURCATION_SELECT;
4436
4437         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4438         I915_WRITE(SOUTH_CHICKEN1, temp);
4439         POSTING_READ(SOUTH_CHICKEN1);
4440 }
4441
4442 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4443 {
4444         struct drm_device *dev = intel_crtc->base.dev;
4445
4446         switch (intel_crtc->pipe) {
4447         case PIPE_A:
4448                 break;
4449         case PIPE_B:
4450                 if (intel_crtc->config->fdi_lanes > 2)
4451                         cpt_set_fdi_bc_bifurcation(dev, false);
4452                 else
4453                         cpt_set_fdi_bc_bifurcation(dev, true);
4454
4455                 break;
4456         case PIPE_C:
4457                 cpt_set_fdi_bc_bifurcation(dev, true);
4458
4459                 break;
4460         default:
4461                 BUG();
4462         }
4463 }
4464
4465 /* Return which DP Port should be selected for Transcoder DP control */
4466 static enum port
4467 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4468 {
4469         struct drm_device *dev = crtc->base.dev;
4470         struct intel_encoder *encoder;
4471
4472         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4473                 if (encoder->type == INTEL_OUTPUT_DP ||
4474                     encoder->type == INTEL_OUTPUT_EDP)
4475                         return enc_to_dig_port(&encoder->base)->port;
4476         }
4477
4478         return -1;
4479 }
4480
4481 /*
4482  * Enable PCH resources required for PCH ports:
4483  *   - PCH PLLs
4484  *   - FDI training & RX/TX
4485  *   - update transcoder timings
4486  *   - DP transcoding bits
4487  *   - transcoder
4488  */
4489 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4490 {
4491         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4492         struct drm_device *dev = crtc->base.dev;
4493         struct drm_i915_private *dev_priv = to_i915(dev);
4494         int pipe = crtc->pipe;
4495         u32 temp;
4496
4497         assert_pch_transcoder_disabled(dev_priv, pipe);
4498
4499         if (IS_IVYBRIDGE(dev_priv))
4500                 ivybridge_update_fdi_bc_bifurcation(crtc);
4501
4502         /* Write the TU size bits before fdi link training, so that error
4503          * detection works. */
4504         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4505                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4506
4507         /* For PCH output, training FDI link */
4508         dev_priv->display.fdi_link_train(crtc, crtc_state);
4509
4510         /* We need to program the right clock selection before writing the pixel
4511          * mutliplier into the DPLL. */
4512         if (HAS_PCH_CPT(dev_priv)) {
4513                 u32 sel;
4514
4515                 temp = I915_READ(PCH_DPLL_SEL);
4516                 temp |= TRANS_DPLL_ENABLE(pipe);
4517                 sel = TRANS_DPLLB_SEL(pipe);
4518                 if (crtc_state->shared_dpll ==
4519                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4520                         temp |= sel;
4521                 else
4522                         temp &= ~sel;
4523                 I915_WRITE(PCH_DPLL_SEL, temp);
4524         }
4525
4526         /* XXX: pch pll's can be enabled any time before we enable the PCH
4527          * transcoder, and we actually should do this to not upset any PCH
4528          * transcoder that already use the clock when we share it.
4529          *
4530          * Note that enable_shared_dpll tries to do the right thing, but
4531          * get_shared_dpll unconditionally resets the pll - we need that to have
4532          * the right LVDS enable sequence. */
4533         intel_enable_shared_dpll(crtc);
4534
4535         /* set transcoder timing, panel must allow it */
4536         assert_panel_unlocked(dev_priv, pipe);
4537         ironlake_pch_transcoder_set_timings(crtc, pipe);
4538
4539         intel_fdi_normal_train(crtc);
4540
4541         /* For PCH DP, enable TRANS_DP_CTL */
4542         if (HAS_PCH_CPT(dev_priv) &&
4543             intel_crtc_has_dp_encoder(crtc_state)) {
4544                 const struct drm_display_mode *adjusted_mode =
4545                         &crtc_state->base.adjusted_mode;
4546                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4547                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4548                 temp = I915_READ(reg);
4549                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4550                           TRANS_DP_SYNC_MASK |
4551                           TRANS_DP_BPC_MASK);
4552                 temp |= TRANS_DP_OUTPUT_ENABLE;
4553                 temp |= bpc << 9; /* same format but at 11:9 */
4554
4555                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4556                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4557                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4558                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4559
4560                 switch (intel_trans_dp_port_sel(crtc)) {
4561                 case PORT_B:
4562                         temp |= TRANS_DP_PORT_SEL_B;
4563                         break;
4564                 case PORT_C:
4565                         temp |= TRANS_DP_PORT_SEL_C;
4566                         break;
4567                 case PORT_D:
4568                         temp |= TRANS_DP_PORT_SEL_D;
4569                         break;
4570                 default:
4571                         BUG();
4572                 }
4573
4574                 I915_WRITE(reg, temp);
4575         }
4576
4577         ironlake_enable_pch_transcoder(dev_priv, pipe);
4578 }
4579
4580 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4581 {
4582         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4583         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4584         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4585
4586         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4587
4588         lpt_program_iclkip(crtc);
4589
4590         /* Set transcoder timing. */
4591         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4592
4593         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4594 }
4595
4596 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4597 {
4598         struct drm_i915_private *dev_priv = to_i915(dev);
4599         i915_reg_t dslreg = PIPEDSL(pipe);
4600         u32 temp;
4601
4602         temp = I915_READ(dslreg);
4603         udelay(500);
4604         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4605                 if (wait_for(I915_READ(dslreg) != temp, 5))
4606                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4607         }
4608 }
4609
4610 static int
4611 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4612                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4613                   int src_w, int src_h, int dst_w, int dst_h)
4614 {
4615         struct intel_crtc_scaler_state *scaler_state =
4616                 &crtc_state->scaler_state;
4617         struct intel_crtc *intel_crtc =
4618                 to_intel_crtc(crtc_state->base.crtc);
4619         int need_scaling;
4620
4621         need_scaling = drm_rotation_90_or_270(rotation) ?
4622                 (src_h != dst_w || src_w != dst_h):
4623                 (src_w != dst_w || src_h != dst_h);
4624
4625         /*
4626          * if plane is being disabled or scaler is no more required or force detach
4627          *  - free scaler binded to this plane/crtc
4628          *  - in order to do this, update crtc->scaler_usage
4629          *
4630          * Here scaler state in crtc_state is set free so that
4631          * scaler can be assigned to other user. Actual register
4632          * update to free the scaler is done in plane/panel-fit programming.
4633          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4634          */
4635         if (force_detach || !need_scaling) {
4636                 if (*scaler_id >= 0) {
4637                         scaler_state->scaler_users &= ~(1 << scaler_user);
4638                         scaler_state->scalers[*scaler_id].in_use = 0;
4639
4640                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4641                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4642                                 intel_crtc->pipe, scaler_user, *scaler_id,
4643                                 scaler_state->scaler_users);
4644                         *scaler_id = -1;
4645                 }
4646                 return 0;
4647         }
4648
4649         /* range checks */
4650         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4651                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4652
4653                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4654                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4655                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4656                         "size is out of scaler range\n",
4657                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4658                 return -EINVAL;
4659         }
4660
4661         /* mark this plane as a scaler user in crtc_state */
4662         scaler_state->scaler_users |= (1 << scaler_user);
4663         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4664                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4665                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4666                 scaler_state->scaler_users);
4667
4668         return 0;
4669 }
4670
4671 /**
4672  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4673  *
4674  * @state: crtc's scaler state
4675  *
4676  * Return
4677  *     0 - scaler_usage updated successfully
4678  *    error - requested scaling cannot be supported or other error condition
4679  */
4680 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4681 {
4682         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4683
4684         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4685                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4686                 state->pipe_src_w, state->pipe_src_h,
4687                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4688 }
4689
4690 /**
4691  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4692  *
4693  * @state: crtc's scaler state
4694  * @plane_state: atomic plane state to update
4695  *
4696  * Return
4697  *     0 - scaler_usage updated successfully
4698  *    error - requested scaling cannot be supported or other error condition
4699  */
4700 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4701                                    struct intel_plane_state *plane_state)
4702 {
4703
4704         struct intel_plane *intel_plane =
4705                 to_intel_plane(plane_state->base.plane);
4706         struct drm_framebuffer *fb = plane_state->base.fb;
4707         int ret;
4708
4709         bool force_detach = !fb || !plane_state->base.visible;
4710
4711         ret = skl_update_scaler(crtc_state, force_detach,
4712                                 drm_plane_index(&intel_plane->base),
4713                                 &plane_state->scaler_id,
4714                                 plane_state->base.rotation,
4715                                 drm_rect_width(&plane_state->base.src) >> 16,
4716                                 drm_rect_height(&plane_state->base.src) >> 16,
4717                                 drm_rect_width(&plane_state->base.dst),
4718                                 drm_rect_height(&plane_state->base.dst));
4719
4720         if (ret || plane_state->scaler_id < 0)
4721                 return ret;
4722
4723         /* check colorkey */
4724         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4725                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4726                               intel_plane->base.base.id,
4727                               intel_plane->base.name);
4728                 return -EINVAL;
4729         }
4730
4731         /* Check src format */
4732         switch (fb->format->format) {
4733         case DRM_FORMAT_RGB565:
4734         case DRM_FORMAT_XBGR8888:
4735         case DRM_FORMAT_XRGB8888:
4736         case DRM_FORMAT_ABGR8888:
4737         case DRM_FORMAT_ARGB8888:
4738         case DRM_FORMAT_XRGB2101010:
4739         case DRM_FORMAT_XBGR2101010:
4740         case DRM_FORMAT_YUYV:
4741         case DRM_FORMAT_YVYU:
4742         case DRM_FORMAT_UYVY:
4743         case DRM_FORMAT_VYUY:
4744                 break;
4745         default:
4746                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4747                               intel_plane->base.base.id, intel_plane->base.name,
4748                               fb->base.id, fb->format->format);
4749                 return -EINVAL;
4750         }
4751
4752         return 0;
4753 }
4754
4755 static void skylake_scaler_disable(struct intel_crtc *crtc)
4756 {
4757         int i;
4758
4759         for (i = 0; i < crtc->num_scalers; i++)
4760                 skl_detach_scaler(crtc, i);
4761 }
4762
4763 static void skylake_pfit_enable(struct intel_crtc *crtc)
4764 {
4765         struct drm_device *dev = crtc->base.dev;
4766         struct drm_i915_private *dev_priv = to_i915(dev);
4767         int pipe = crtc->pipe;
4768         struct intel_crtc_scaler_state *scaler_state =
4769                 &crtc->config->scaler_state;
4770
4771         if (crtc->config->pch_pfit.enabled) {
4772                 int id;
4773
4774                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4775                         return;
4776
4777                 id = scaler_state->scaler_id;
4778                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4779                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4780                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4781                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4782         }
4783 }
4784
4785 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4786 {
4787         struct drm_device *dev = crtc->base.dev;
4788         struct drm_i915_private *dev_priv = to_i915(dev);
4789         int pipe = crtc->pipe;
4790
4791         if (crtc->config->pch_pfit.enabled) {
4792                 /* Force use of hard-coded filter coefficients
4793                  * as some pre-programmed values are broken,
4794                  * e.g. x201.
4795                  */
4796                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4797                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4798                                                  PF_PIPE_SEL_IVB(pipe));
4799                 else
4800                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4801                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4802                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4803         }
4804 }
4805
4806 void hsw_enable_ips(struct intel_crtc *crtc)
4807 {
4808         struct drm_device *dev = crtc->base.dev;
4809         struct drm_i915_private *dev_priv = to_i915(dev);
4810
4811         if (!crtc->config->ips_enabled)
4812                 return;
4813
4814         /*
4815          * We can only enable IPS after we enable a plane and wait for a vblank
4816          * This function is called from post_plane_update, which is run after
4817          * a vblank wait.
4818          */
4819
4820         assert_plane_enabled(dev_priv, crtc->plane);
4821         if (IS_BROADWELL(dev_priv)) {
4822                 mutex_lock(&dev_priv->rps.hw_lock);
4823                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4824                 mutex_unlock(&dev_priv->rps.hw_lock);
4825                 /* Quoting Art Runyan: "its not safe to expect any particular
4826                  * value in IPS_CTL bit 31 after enabling IPS through the
4827                  * mailbox." Moreover, the mailbox may return a bogus state,
4828                  * so we need to just enable it and continue on.
4829                  */
4830         } else {
4831                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4832                 /* The bit only becomes 1 in the next vblank, so this wait here
4833                  * is essentially intel_wait_for_vblank. If we don't have this
4834                  * and don't wait for vblanks until the end of crtc_enable, then
4835                  * the HW state readout code will complain that the expected
4836                  * IPS_CTL value is not the one we read. */
4837                 if (intel_wait_for_register(dev_priv,
4838                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4839                                             50))
4840                         DRM_ERROR("Timed out waiting for IPS enable\n");
4841         }
4842 }
4843
4844 void hsw_disable_ips(struct intel_crtc *crtc)
4845 {
4846         struct drm_device *dev = crtc->base.dev;
4847         struct drm_i915_private *dev_priv = to_i915(dev);
4848
4849         if (!crtc->config->ips_enabled)
4850                 return;
4851
4852         assert_plane_enabled(dev_priv, crtc->plane);
4853         if (IS_BROADWELL(dev_priv)) {
4854                 mutex_lock(&dev_priv->rps.hw_lock);
4855                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4856                 mutex_unlock(&dev_priv->rps.hw_lock);
4857                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4858                 if (intel_wait_for_register(dev_priv,
4859                                             IPS_CTL, IPS_ENABLE, 0,
4860                                             42))
4861                         DRM_ERROR("Timed out waiting for IPS disable\n");
4862         } else {
4863                 I915_WRITE(IPS_CTL, 0);
4864                 POSTING_READ(IPS_CTL);
4865         }
4866
4867         /* We need to wait for a vblank before we can disable the plane. */
4868         intel_wait_for_vblank(dev_priv, crtc->pipe);
4869 }
4870
4871 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4872 {
4873         if (intel_crtc->overlay) {
4874                 struct drm_device *dev = intel_crtc->base.dev;
4875                 struct drm_i915_private *dev_priv = to_i915(dev);
4876
4877                 mutex_lock(&dev->struct_mutex);
4878                 dev_priv->mm.interruptible = false;
4879                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4880                 dev_priv->mm.interruptible = true;
4881                 mutex_unlock(&dev->struct_mutex);
4882         }
4883
4884         /* Let userspace switch the overlay on again. In most cases userspace
4885          * has to recompute where to put it anyway.
4886          */
4887 }
4888
4889 /**
4890  * intel_post_enable_primary - Perform operations after enabling primary plane
4891  * @crtc: the CRTC whose primary plane was just enabled
4892  *
4893  * Performs potentially sleeping operations that must be done after the primary
4894  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4895  * called due to an explicit primary plane update, or due to an implicit
4896  * re-enable that is caused when a sprite plane is updated to no longer
4897  * completely hide the primary plane.
4898  */
4899 static void
4900 intel_post_enable_primary(struct drm_crtc *crtc)
4901 {
4902         struct drm_device *dev = crtc->dev;
4903         struct drm_i915_private *dev_priv = to_i915(dev);
4904         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4905         int pipe = intel_crtc->pipe;
4906
4907         /*
4908          * FIXME IPS should be fine as long as one plane is
4909          * enabled, but in practice it seems to have problems
4910          * when going from primary only to sprite only and vice
4911          * versa.
4912          */
4913         hsw_enable_ips(intel_crtc);
4914
4915         /*
4916          * Gen2 reports pipe underruns whenever all planes are disabled.
4917          * So don't enable underrun reporting before at least some planes
4918          * are enabled.
4919          * FIXME: Need to fix the logic to work when we turn off all planes
4920          * but leave the pipe running.
4921          */
4922         if (IS_GEN2(dev_priv))
4923                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4924
4925         /* Underruns don't always raise interrupts, so check manually. */
4926         intel_check_cpu_fifo_underruns(dev_priv);
4927         intel_check_pch_fifo_underruns(dev_priv);
4928 }
4929
4930 /* FIXME move all this to pre_plane_update() with proper state tracking */
4931 static void
4932 intel_pre_disable_primary(struct drm_crtc *crtc)
4933 {
4934         struct drm_device *dev = crtc->dev;
4935         struct drm_i915_private *dev_priv = to_i915(dev);
4936         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4937         int pipe = intel_crtc->pipe;
4938
4939         /*
4940          * Gen2 reports pipe underruns whenever all planes are disabled.
4941          * So diasble underrun reporting before all the planes get disabled.
4942          * FIXME: Need to fix the logic to work when we turn off all planes
4943          * but leave the pipe running.
4944          */
4945         if (IS_GEN2(dev_priv))
4946                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4947
4948         /*
4949          * FIXME IPS should be fine as long as one plane is
4950          * enabled, but in practice it seems to have problems
4951          * when going from primary only to sprite only and vice
4952          * versa.
4953          */
4954         hsw_disable_ips(intel_crtc);
4955 }
4956
4957 /* FIXME get rid of this and use pre_plane_update */
4958 static void
4959 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4960 {
4961         struct drm_device *dev = crtc->dev;
4962         struct drm_i915_private *dev_priv = to_i915(dev);
4963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4964         int pipe = intel_crtc->pipe;
4965
4966         intel_pre_disable_primary(crtc);
4967
4968         /*
4969          * Vblank time updates from the shadow to live plane control register
4970          * are blocked if the memory self-refresh mode is active at that
4971          * moment. So to make sure the plane gets truly disabled, disable
4972          * first the self-refresh mode. The self-refresh enable bit in turn
4973          * will be checked/applied by the HW only at the next frame start
4974          * event which is after the vblank start event, so we need to have a
4975          * wait-for-vblank between disabling the plane and the pipe.
4976          */
4977         if (HAS_GMCH_DISPLAY(dev_priv) &&
4978             intel_set_memory_cxsr(dev_priv, false))
4979                 intel_wait_for_vblank(dev_priv, pipe);
4980 }
4981
4982 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4983 {
4984         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4985         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4986         struct intel_crtc_state *pipe_config =
4987                 to_intel_crtc_state(crtc->base.state);
4988         struct drm_plane *primary = crtc->base.primary;
4989         struct drm_plane_state *old_pri_state =
4990                 drm_atomic_get_existing_plane_state(old_state, primary);
4991
4992         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
4993
4994         if (pipe_config->update_wm_post && pipe_config->base.active)
4995                 intel_update_watermarks(crtc);
4996
4997         if (old_pri_state) {
4998                 struct intel_plane_state *primary_state =
4999                         to_intel_plane_state(primary->state);
5000                 struct intel_plane_state *old_primary_state =
5001                         to_intel_plane_state(old_pri_state);
5002
5003                 intel_fbc_post_update(crtc);
5004
5005                 if (primary_state->base.visible &&
5006                     (needs_modeset(&pipe_config->base) ||
5007                      !old_primary_state->base.visible))
5008                         intel_post_enable_primary(&crtc->base);
5009         }
5010 }
5011
5012 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5013                                    struct intel_crtc_state *pipe_config)
5014 {
5015         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5016         struct drm_device *dev = crtc->base.dev;
5017         struct drm_i915_private *dev_priv = to_i915(dev);
5018         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5019         struct drm_plane *primary = crtc->base.primary;
5020         struct drm_plane_state *old_pri_state =
5021                 drm_atomic_get_existing_plane_state(old_state, primary);
5022         bool modeset = needs_modeset(&pipe_config->base);
5023         struct intel_atomic_state *old_intel_state =
5024                 to_intel_atomic_state(old_state);
5025
5026         if (old_pri_state) {
5027                 struct intel_plane_state *primary_state =
5028                         to_intel_plane_state(primary->state);
5029                 struct intel_plane_state *old_primary_state =
5030                         to_intel_plane_state(old_pri_state);
5031
5032                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5033
5034                 if (old_primary_state->base.visible &&
5035                     (modeset || !primary_state->base.visible))
5036                         intel_pre_disable_primary(&crtc->base);
5037         }
5038
5039         /*
5040          * Vblank time updates from the shadow to live plane control register
5041          * are blocked if the memory self-refresh mode is active at that
5042          * moment. So to make sure the plane gets truly disabled, disable
5043          * first the self-refresh mode. The self-refresh enable bit in turn
5044          * will be checked/applied by the HW only at the next frame start
5045          * event which is after the vblank start event, so we need to have a
5046          * wait-for-vblank between disabling the plane and the pipe.
5047          */
5048         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5049             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5050                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5051
5052         /*
5053          * IVB workaround: must disable low power watermarks for at least
5054          * one frame before enabling scaling.  LP watermarks can be re-enabled
5055          * when scaling is disabled.
5056          *
5057          * WaCxSRDisabledForSpriteScaling:ivb
5058          */
5059         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5060                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5061
5062         /*
5063          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5064          * watermark programming here.
5065          */
5066         if (needs_modeset(&pipe_config->base))
5067                 return;
5068
5069         /*
5070          * For platforms that support atomic watermarks, program the
5071          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5072          * will be the intermediate values that are safe for both pre- and
5073          * post- vblank; when vblank happens, the 'active' values will be set
5074          * to the final 'target' values and we'll do this again to get the
5075          * optimal watermarks.  For gen9+ platforms, the values we program here
5076          * will be the final target values which will get automatically latched
5077          * at vblank time; no further programming will be necessary.
5078          *
5079          * If a platform hasn't been transitioned to atomic watermarks yet,
5080          * we'll continue to update watermarks the old way, if flags tell
5081          * us to.
5082          */
5083         if (dev_priv->display.initial_watermarks != NULL)
5084                 dev_priv->display.initial_watermarks(old_intel_state,
5085                                                      pipe_config);
5086         else if (pipe_config->update_wm_pre)
5087                 intel_update_watermarks(crtc);
5088 }
5089
5090 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5091 {
5092         struct drm_device *dev = crtc->dev;
5093         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5094         struct drm_plane *p;
5095         int pipe = intel_crtc->pipe;
5096
5097         intel_crtc_dpms_overlay_disable(intel_crtc);
5098
5099         drm_for_each_plane_mask(p, dev, plane_mask)
5100                 to_intel_plane(p)->disable_plane(p, crtc);
5101
5102         /*
5103          * FIXME: Once we grow proper nuclear flip support out of this we need
5104          * to compute the mask of flip planes precisely. For the time being
5105          * consider this a flip to a NULL plane.
5106          */
5107         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5108 }
5109
5110 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5111                                           struct intel_crtc_state *crtc_state,
5112                                           struct drm_atomic_state *old_state)
5113 {
5114         struct drm_connector_state *conn_state;
5115         struct drm_connector *conn;
5116         int i;
5117
5118         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5119                 struct intel_encoder *encoder =
5120                         to_intel_encoder(conn_state->best_encoder);
5121
5122                 if (conn_state->crtc != crtc)
5123                         continue;
5124
5125                 if (encoder->pre_pll_enable)
5126                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5127         }
5128 }
5129
5130 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5131                                       struct intel_crtc_state *crtc_state,
5132                                       struct drm_atomic_state *old_state)
5133 {
5134         struct drm_connector_state *conn_state;
5135         struct drm_connector *conn;
5136         int i;
5137
5138         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5139                 struct intel_encoder *encoder =
5140                         to_intel_encoder(conn_state->best_encoder);
5141
5142                 if (conn_state->crtc != crtc)
5143                         continue;
5144
5145                 if (encoder->pre_enable)
5146                         encoder->pre_enable(encoder, crtc_state, conn_state);
5147         }
5148 }
5149
5150 static void intel_encoders_enable(struct drm_crtc *crtc,
5151                                   struct intel_crtc_state *crtc_state,
5152                                   struct drm_atomic_state *old_state)
5153 {
5154         struct drm_connector_state *conn_state;
5155         struct drm_connector *conn;
5156         int i;
5157
5158         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5159                 struct intel_encoder *encoder =
5160                         to_intel_encoder(conn_state->best_encoder);
5161
5162                 if (conn_state->crtc != crtc)
5163                         continue;
5164
5165                 encoder->enable(encoder, crtc_state, conn_state);
5166                 intel_opregion_notify_encoder(encoder, true);
5167         }
5168 }
5169
5170 static void intel_encoders_disable(struct drm_crtc *crtc,
5171                                    struct intel_crtc_state *old_crtc_state,
5172                                    struct drm_atomic_state *old_state)
5173 {
5174         struct drm_connector_state *old_conn_state;
5175         struct drm_connector *conn;
5176         int i;
5177
5178         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5179                 struct intel_encoder *encoder =
5180                         to_intel_encoder(old_conn_state->best_encoder);
5181
5182                 if (old_conn_state->crtc != crtc)
5183                         continue;
5184
5185                 intel_opregion_notify_encoder(encoder, false);
5186                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5187         }
5188 }
5189
5190 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5191                                         struct intel_crtc_state *old_crtc_state,
5192                                         struct drm_atomic_state *old_state)
5193 {
5194         struct drm_connector_state *old_conn_state;
5195         struct drm_connector *conn;
5196         int i;
5197
5198         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5199                 struct intel_encoder *encoder =
5200                         to_intel_encoder(old_conn_state->best_encoder);
5201
5202                 if (old_conn_state->crtc != crtc)
5203                         continue;
5204
5205                 if (encoder->post_disable)
5206                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5207         }
5208 }
5209
5210 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5211                                             struct intel_crtc_state *old_crtc_state,
5212                                             struct drm_atomic_state *old_state)
5213 {
5214         struct drm_connector_state *old_conn_state;
5215         struct drm_connector *conn;
5216         int i;
5217
5218         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5219                 struct intel_encoder *encoder =
5220                         to_intel_encoder(old_conn_state->best_encoder);
5221
5222                 if (old_conn_state->crtc != crtc)
5223                         continue;
5224
5225                 if (encoder->post_pll_disable)
5226                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5227         }
5228 }
5229
5230 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5231                                  struct drm_atomic_state *old_state)
5232 {
5233         struct drm_crtc *crtc = pipe_config->base.crtc;
5234         struct drm_device *dev = crtc->dev;
5235         struct drm_i915_private *dev_priv = to_i915(dev);
5236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5237         int pipe = intel_crtc->pipe;
5238         struct intel_atomic_state *old_intel_state =
5239                 to_intel_atomic_state(old_state);
5240
5241         if (WARN_ON(intel_crtc->active))
5242                 return;
5243
5244         /*
5245          * Sometimes spurious CPU pipe underruns happen during FDI
5246          * training, at least with VGA+HDMI cloning. Suppress them.
5247          *
5248          * On ILK we get an occasional spurious CPU pipe underruns
5249          * between eDP port A enable and vdd enable. Also PCH port
5250          * enable seems to result in the occasional CPU pipe underrun.
5251          *
5252          * Spurious PCH underruns also occur during PCH enabling.
5253          */
5254         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5255                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5256         if (intel_crtc->config->has_pch_encoder)
5257                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5258
5259         if (intel_crtc->config->has_pch_encoder)
5260                 intel_prepare_shared_dpll(intel_crtc);
5261
5262         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5263                 intel_dp_set_m_n(intel_crtc, M1_N1);
5264
5265         intel_set_pipe_timings(intel_crtc);
5266         intel_set_pipe_src_size(intel_crtc);
5267
5268         if (intel_crtc->config->has_pch_encoder) {
5269                 intel_cpu_transcoder_set_m_n(intel_crtc,
5270                                      &intel_crtc->config->fdi_m_n, NULL);
5271         }
5272
5273         ironlake_set_pipeconf(crtc);
5274
5275         intel_crtc->active = true;
5276
5277         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5278
5279         if (intel_crtc->config->has_pch_encoder) {
5280                 /* Note: FDI PLL enabling _must_ be done before we enable the
5281                  * cpu pipes, hence this is separate from all the other fdi/pch
5282                  * enabling. */
5283                 ironlake_fdi_pll_enable(intel_crtc);
5284         } else {
5285                 assert_fdi_tx_disabled(dev_priv, pipe);
5286                 assert_fdi_rx_disabled(dev_priv, pipe);
5287         }
5288
5289         ironlake_pfit_enable(intel_crtc);
5290
5291         /*
5292          * On ILK+ LUT must be loaded before the pipe is running but with
5293          * clocks enabled
5294          */
5295         intel_color_load_luts(&pipe_config->base);
5296
5297         if (dev_priv->display.initial_watermarks != NULL)
5298                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5299         intel_enable_pipe(intel_crtc);
5300
5301         if (intel_crtc->config->has_pch_encoder)
5302                 ironlake_pch_enable(pipe_config);
5303
5304         assert_vblank_disabled(crtc);
5305         drm_crtc_vblank_on(crtc);
5306
5307         intel_encoders_enable(crtc, pipe_config, old_state);
5308
5309         if (HAS_PCH_CPT(dev_priv))
5310                 cpt_verify_modeset(dev, intel_crtc->pipe);
5311
5312         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5313         if (intel_crtc->config->has_pch_encoder)
5314                 intel_wait_for_vblank(dev_priv, pipe);
5315         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5316         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5317 }
5318
5319 /* IPS only exists on ULT machines and is tied to pipe A. */
5320 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5321 {
5322         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5323 }
5324
5325 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5326                                 struct drm_atomic_state *old_state)
5327 {
5328         struct drm_crtc *crtc = pipe_config->base.crtc;
5329         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5331         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5332         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5333         struct intel_atomic_state *old_intel_state =
5334                 to_intel_atomic_state(old_state);
5335
5336         if (WARN_ON(intel_crtc->active))
5337                 return;
5338
5339         if (intel_crtc->config->has_pch_encoder)
5340                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5341                                                       false);
5342
5343         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5344
5345         if (intel_crtc->config->shared_dpll)
5346                 intel_enable_shared_dpll(intel_crtc);
5347
5348         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5349                 intel_dp_set_m_n(intel_crtc, M1_N1);
5350
5351         if (!transcoder_is_dsi(cpu_transcoder))
5352                 intel_set_pipe_timings(intel_crtc);
5353
5354         intel_set_pipe_src_size(intel_crtc);
5355
5356         if (cpu_transcoder != TRANSCODER_EDP &&
5357             !transcoder_is_dsi(cpu_transcoder)) {
5358                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5359                            intel_crtc->config->pixel_multiplier - 1);
5360         }
5361
5362         if (intel_crtc->config->has_pch_encoder) {
5363                 intel_cpu_transcoder_set_m_n(intel_crtc,
5364                                      &intel_crtc->config->fdi_m_n, NULL);
5365         }
5366
5367         if (!transcoder_is_dsi(cpu_transcoder))
5368                 haswell_set_pipeconf(crtc);
5369
5370         haswell_set_pipemisc(crtc);
5371
5372         intel_color_set_csc(&pipe_config->base);
5373
5374         intel_crtc->active = true;
5375
5376         if (intel_crtc->config->has_pch_encoder)
5377                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5378         else
5379                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5380
5381         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5382
5383         if (intel_crtc->config->has_pch_encoder)
5384                 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5385
5386         if (!transcoder_is_dsi(cpu_transcoder))
5387                 intel_ddi_enable_pipe_clock(pipe_config);
5388
5389         if (INTEL_GEN(dev_priv) >= 9)
5390                 skylake_pfit_enable(intel_crtc);
5391         else
5392                 ironlake_pfit_enable(intel_crtc);
5393
5394         /*
5395          * On ILK+ LUT must be loaded before the pipe is running but with
5396          * clocks enabled
5397          */
5398         intel_color_load_luts(&pipe_config->base);
5399
5400         intel_ddi_set_pipe_settings(pipe_config);
5401         if (!transcoder_is_dsi(cpu_transcoder))
5402                 intel_ddi_enable_transcoder_func(pipe_config);
5403
5404         if (dev_priv->display.initial_watermarks != NULL)
5405                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5406
5407         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5408         if (!transcoder_is_dsi(cpu_transcoder))
5409                 intel_enable_pipe(intel_crtc);
5410
5411         if (intel_crtc->config->has_pch_encoder)
5412                 lpt_pch_enable(pipe_config);
5413
5414         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5415                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5416
5417         assert_vblank_disabled(crtc);
5418         drm_crtc_vblank_on(crtc);
5419
5420         intel_encoders_enable(crtc, pipe_config, old_state);
5421
5422         if (intel_crtc->config->has_pch_encoder) {
5423                 intel_wait_for_vblank(dev_priv, pipe);
5424                 intel_wait_for_vblank(dev_priv, pipe);
5425                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5426                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5427                                                       true);
5428         }
5429
5430         /* If we change the relative order between pipe/planes enabling, we need
5431          * to change the workaround. */
5432         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5433         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5434                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5435                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5436         }
5437 }
5438
5439 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5440 {
5441         struct drm_device *dev = crtc->base.dev;
5442         struct drm_i915_private *dev_priv = to_i915(dev);
5443         int pipe = crtc->pipe;
5444
5445         /* To avoid upsetting the power well on haswell only disable the pfit if
5446          * it's in use. The hw state code will make sure we get this right. */
5447         if (force || crtc->config->pch_pfit.enabled) {
5448                 I915_WRITE(PF_CTL(pipe), 0);
5449                 I915_WRITE(PF_WIN_POS(pipe), 0);
5450                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5451         }
5452 }
5453
5454 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5455                                   struct drm_atomic_state *old_state)
5456 {
5457         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5458         struct drm_device *dev = crtc->dev;
5459         struct drm_i915_private *dev_priv = to_i915(dev);
5460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5461         int pipe = intel_crtc->pipe;
5462
5463         /*
5464          * Sometimes spurious CPU pipe underruns happen when the
5465          * pipe is already disabled, but FDI RX/TX is still enabled.
5466          * Happens at least with VGA+HDMI cloning. Suppress them.
5467          */
5468         if (intel_crtc->config->has_pch_encoder) {
5469                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5470                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5471         }
5472
5473         intel_encoders_disable(crtc, old_crtc_state, old_state);
5474
5475         drm_crtc_vblank_off(crtc);
5476         assert_vblank_disabled(crtc);
5477
5478         intel_disable_pipe(intel_crtc);
5479
5480         ironlake_pfit_disable(intel_crtc, false);
5481
5482         if (intel_crtc->config->has_pch_encoder)
5483                 ironlake_fdi_disable(crtc);
5484
5485         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5486
5487         if (intel_crtc->config->has_pch_encoder) {
5488                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5489
5490                 if (HAS_PCH_CPT(dev_priv)) {
5491                         i915_reg_t reg;
5492                         u32 temp;
5493
5494                         /* disable TRANS_DP_CTL */
5495                         reg = TRANS_DP_CTL(pipe);
5496                         temp = I915_READ(reg);
5497                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5498                                   TRANS_DP_PORT_SEL_MASK);
5499                         temp |= TRANS_DP_PORT_SEL_NONE;
5500                         I915_WRITE(reg, temp);
5501
5502                         /* disable DPLL_SEL */
5503                         temp = I915_READ(PCH_DPLL_SEL);
5504                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5505                         I915_WRITE(PCH_DPLL_SEL, temp);
5506                 }
5507
5508                 ironlake_fdi_pll_disable(intel_crtc);
5509         }
5510
5511         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5512         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5513 }
5514
5515 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5516                                  struct drm_atomic_state *old_state)
5517 {
5518         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5519         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5521         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5522
5523         if (intel_crtc->config->has_pch_encoder)
5524                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5525                                                       false);
5526
5527         intel_encoders_disable(crtc, old_crtc_state, old_state);
5528
5529         drm_crtc_vblank_off(crtc);
5530         assert_vblank_disabled(crtc);
5531
5532         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5533         if (!transcoder_is_dsi(cpu_transcoder))
5534                 intel_disable_pipe(intel_crtc);
5535
5536         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5537                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5538
5539         if (!transcoder_is_dsi(cpu_transcoder))
5540                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5541
5542         if (INTEL_GEN(dev_priv) >= 9)
5543                 skylake_scaler_disable(intel_crtc);
5544         else
5545                 ironlake_pfit_disable(intel_crtc, false);
5546
5547         if (!transcoder_is_dsi(cpu_transcoder))
5548                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5549
5550         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5551
5552         if (old_crtc_state->has_pch_encoder)
5553                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5554                                                       true);
5555 }
5556
5557 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5558 {
5559         struct drm_device *dev = crtc->base.dev;
5560         struct drm_i915_private *dev_priv = to_i915(dev);
5561         struct intel_crtc_state *pipe_config = crtc->config;
5562
5563         if (!pipe_config->gmch_pfit.control)
5564                 return;
5565
5566         /*
5567          * The panel fitter should only be adjusted whilst the pipe is disabled,
5568          * according to register description and PRM.
5569          */
5570         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5571         assert_pipe_disabled(dev_priv, crtc->pipe);
5572
5573         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5574         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5575
5576         /* Border color in case we don't scale up to the full screen. Black by
5577          * default, change to something else for debugging. */
5578         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5579 }
5580
5581 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5582 {
5583         switch (port) {
5584         case PORT_A:
5585                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5586         case PORT_B:
5587                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5588         case PORT_C:
5589                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5590         case PORT_D:
5591                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5592         case PORT_E:
5593                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5594         default:
5595                 MISSING_CASE(port);
5596                 return POWER_DOMAIN_PORT_OTHER;
5597         }
5598 }
5599
5600 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5601                                   struct intel_crtc_state *crtc_state)
5602 {
5603         struct drm_device *dev = crtc->dev;
5604         struct drm_i915_private *dev_priv = to_i915(dev);
5605         struct drm_encoder *encoder;
5606         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5607         enum pipe pipe = intel_crtc->pipe;
5608         u64 mask;
5609         enum transcoder transcoder = crtc_state->cpu_transcoder;
5610
5611         if (!crtc_state->base.active)
5612                 return 0;
5613
5614         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5615         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5616         if (crtc_state->pch_pfit.enabled ||
5617             crtc_state->pch_pfit.force_thru)
5618                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5619
5620         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5621                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5622
5623                 mask |= BIT_ULL(intel_encoder->power_domain);
5624         }
5625
5626         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5627                 mask |= BIT(POWER_DOMAIN_AUDIO);
5628
5629         if (crtc_state->shared_dpll)
5630                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5631
5632         return mask;
5633 }
5634
5635 static u64
5636 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5637                                struct intel_crtc_state *crtc_state)
5638 {
5639         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5640         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5641         enum intel_display_power_domain domain;
5642         u64 domains, new_domains, old_domains;
5643
5644         old_domains = intel_crtc->enabled_power_domains;
5645         intel_crtc->enabled_power_domains = new_domains =
5646                 get_crtc_power_domains(crtc, crtc_state);
5647
5648         domains = new_domains & ~old_domains;
5649
5650         for_each_power_domain(domain, domains)
5651                 intel_display_power_get(dev_priv, domain);
5652
5653         return old_domains & ~new_domains;
5654 }
5655
5656 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5657                                       u64 domains)
5658 {
5659         enum intel_display_power_domain domain;
5660
5661         for_each_power_domain(domain, domains)
5662                 intel_display_power_put(dev_priv, domain);
5663 }
5664
5665 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5666                                    struct drm_atomic_state *old_state)
5667 {
5668         struct intel_atomic_state *old_intel_state =
5669                 to_intel_atomic_state(old_state);
5670         struct drm_crtc *crtc = pipe_config->base.crtc;
5671         struct drm_device *dev = crtc->dev;
5672         struct drm_i915_private *dev_priv = to_i915(dev);
5673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5674         int pipe = intel_crtc->pipe;
5675
5676         if (WARN_ON(intel_crtc->active))
5677                 return;
5678
5679         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5680                 intel_dp_set_m_n(intel_crtc, M1_N1);
5681
5682         intel_set_pipe_timings(intel_crtc);
5683         intel_set_pipe_src_size(intel_crtc);
5684
5685         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5686                 struct drm_i915_private *dev_priv = to_i915(dev);
5687
5688                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5689                 I915_WRITE(CHV_CANVAS(pipe), 0);
5690         }
5691
5692         i9xx_set_pipeconf(intel_crtc);
5693
5694         intel_crtc->active = true;
5695
5696         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5697
5698         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5699
5700         if (IS_CHERRYVIEW(dev_priv)) {
5701                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5702                 chv_enable_pll(intel_crtc, intel_crtc->config);
5703         } else {
5704                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5705                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5706         }
5707
5708         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5709
5710         i9xx_pfit_enable(intel_crtc);
5711
5712         intel_color_load_luts(&pipe_config->base);
5713
5714         dev_priv->display.initial_watermarks(old_intel_state,
5715                                              pipe_config);
5716         intel_enable_pipe(intel_crtc);
5717
5718         assert_vblank_disabled(crtc);
5719         drm_crtc_vblank_on(crtc);
5720
5721         intel_encoders_enable(crtc, pipe_config, old_state);
5722 }
5723
5724 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5725 {
5726         struct drm_device *dev = crtc->base.dev;
5727         struct drm_i915_private *dev_priv = to_i915(dev);
5728
5729         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5730         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5731 }
5732
5733 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5734                              struct drm_atomic_state *old_state)
5735 {
5736         struct drm_crtc *crtc = pipe_config->base.crtc;
5737         struct drm_device *dev = crtc->dev;
5738         struct drm_i915_private *dev_priv = to_i915(dev);
5739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5740         enum pipe pipe = intel_crtc->pipe;
5741
5742         if (WARN_ON(intel_crtc->active))
5743                 return;
5744
5745         i9xx_set_pll_dividers(intel_crtc);
5746
5747         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5748                 intel_dp_set_m_n(intel_crtc, M1_N1);
5749
5750         intel_set_pipe_timings(intel_crtc);
5751         intel_set_pipe_src_size(intel_crtc);
5752
5753         i9xx_set_pipeconf(intel_crtc);
5754
5755         intel_crtc->active = true;
5756
5757         if (!IS_GEN2(dev_priv))
5758                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5759
5760         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5761
5762         i9xx_enable_pll(intel_crtc);
5763
5764         i9xx_pfit_enable(intel_crtc);
5765
5766         intel_color_load_luts(&pipe_config->base);
5767
5768         intel_update_watermarks(intel_crtc);
5769         intel_enable_pipe(intel_crtc);
5770
5771         assert_vblank_disabled(crtc);
5772         drm_crtc_vblank_on(crtc);
5773
5774         intel_encoders_enable(crtc, pipe_config, old_state);
5775 }
5776
5777 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5778 {
5779         struct drm_device *dev = crtc->base.dev;
5780         struct drm_i915_private *dev_priv = to_i915(dev);
5781
5782         if (!crtc->config->gmch_pfit.control)
5783                 return;
5784
5785         assert_pipe_disabled(dev_priv, crtc->pipe);
5786
5787         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5788                          I915_READ(PFIT_CONTROL));
5789         I915_WRITE(PFIT_CONTROL, 0);
5790 }
5791
5792 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5793                               struct drm_atomic_state *old_state)
5794 {
5795         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5796         struct drm_device *dev = crtc->dev;
5797         struct drm_i915_private *dev_priv = to_i915(dev);
5798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5799         int pipe = intel_crtc->pipe;
5800
5801         /*
5802          * On gen2 planes are double buffered but the pipe isn't, so we must
5803          * wait for planes to fully turn off before disabling the pipe.
5804          */
5805         if (IS_GEN2(dev_priv))
5806                 intel_wait_for_vblank(dev_priv, pipe);
5807
5808         intel_encoders_disable(crtc, old_crtc_state, old_state);
5809
5810         drm_crtc_vblank_off(crtc);
5811         assert_vblank_disabled(crtc);
5812
5813         intel_disable_pipe(intel_crtc);
5814
5815         i9xx_pfit_disable(intel_crtc);
5816
5817         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5818
5819         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5820                 if (IS_CHERRYVIEW(dev_priv))
5821                         chv_disable_pll(dev_priv, pipe);
5822                 else if (IS_VALLEYVIEW(dev_priv))
5823                         vlv_disable_pll(dev_priv, pipe);
5824                 else
5825                         i9xx_disable_pll(intel_crtc);
5826         }
5827
5828         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5829
5830         if (!IS_GEN2(dev_priv))
5831                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5832
5833         if (!dev_priv->display.initial_watermarks)
5834                 intel_update_watermarks(intel_crtc);
5835 }
5836
5837 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
5838 {
5839         struct intel_encoder *encoder;
5840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5841         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5842         enum intel_display_power_domain domain;
5843         u64 domains;
5844         struct drm_atomic_state *state;
5845         struct intel_crtc_state *crtc_state;
5846         int ret;
5847
5848         if (!intel_crtc->active)
5849                 return;
5850
5851         if (crtc->primary->state->visible) {
5852                 WARN_ON(intel_crtc->flip_work);
5853
5854                 intel_pre_disable_primary_noatomic(crtc);
5855
5856                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5857                 crtc->primary->state->visible = false;
5858         }
5859
5860         state = drm_atomic_state_alloc(crtc->dev);
5861         if (!state) {
5862                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5863                               crtc->base.id, crtc->name);
5864                 return;
5865         }
5866
5867         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
5868
5869         /* Everything's already locked, -EDEADLK can't happen. */
5870         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5871         ret = drm_atomic_add_affected_connectors(state, crtc);
5872
5873         WARN_ON(IS_ERR(crtc_state) || ret);
5874
5875         dev_priv->display.crtc_disable(crtc_state, state);
5876
5877         drm_atomic_state_put(state);
5878
5879         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5880                       crtc->base.id, crtc->name);
5881
5882         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5883         crtc->state->active = false;
5884         intel_crtc->active = false;
5885         crtc->enabled = false;
5886         crtc->state->connector_mask = 0;
5887         crtc->state->encoder_mask = 0;
5888
5889         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5890                 encoder->base.crtc = NULL;
5891
5892         intel_fbc_disable(intel_crtc);
5893         intel_update_watermarks(intel_crtc);
5894         intel_disable_shared_dpll(intel_crtc);
5895
5896         domains = intel_crtc->enabled_power_domains;
5897         for_each_power_domain(domain, domains)
5898                 intel_display_power_put(dev_priv, domain);
5899         intel_crtc->enabled_power_domains = 0;
5900
5901         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5902         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5903 }
5904
5905 /*
5906  * turn all crtc's off, but do not adjust state
5907  * This has to be paired with a call to intel_modeset_setup_hw_state.
5908  */
5909 int intel_display_suspend(struct drm_device *dev)
5910 {
5911         struct drm_i915_private *dev_priv = to_i915(dev);
5912         struct drm_atomic_state *state;
5913         int ret;
5914
5915         state = drm_atomic_helper_suspend(dev);
5916         ret = PTR_ERR_OR_ZERO(state);
5917         if (ret)
5918                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5919         else
5920                 dev_priv->modeset_restore_state = state;
5921         return ret;
5922 }
5923
5924 void intel_encoder_destroy(struct drm_encoder *encoder)
5925 {
5926         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5927
5928         drm_encoder_cleanup(encoder);
5929         kfree(intel_encoder);
5930 }
5931
5932 /* Cross check the actual hw state with our own modeset state tracking (and it's
5933  * internal consistency). */
5934 static void intel_connector_verify_state(struct intel_connector *connector)
5935 {
5936         struct drm_crtc *crtc = connector->base.state->crtc;
5937
5938         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5939                       connector->base.base.id,
5940                       connector->base.name);
5941
5942         if (connector->get_hw_state(connector)) {
5943                 struct intel_encoder *encoder = connector->encoder;
5944                 struct drm_connector_state *conn_state = connector->base.state;
5945
5946                 I915_STATE_WARN(!crtc,
5947                          "connector enabled without attached crtc\n");
5948
5949                 if (!crtc)
5950                         return;
5951
5952                 I915_STATE_WARN(!crtc->state->active,
5953                       "connector is active, but attached crtc isn't\n");
5954
5955                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5956                         return;
5957
5958                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5959                         "atomic encoder doesn't match attached encoder\n");
5960
5961                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5962                         "attached encoder crtc differs from connector crtc\n");
5963         } else {
5964                 I915_STATE_WARN(crtc && crtc->state->active,
5965                         "attached crtc is active, but connector isn't\n");
5966                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
5967                         "best encoder set without crtc!\n");
5968         }
5969 }
5970
5971 int intel_connector_init(struct intel_connector *connector)
5972 {
5973         drm_atomic_helper_connector_reset(&connector->base);
5974
5975         if (!connector->base.state)
5976                 return -ENOMEM;
5977
5978         return 0;
5979 }
5980
5981 struct intel_connector *intel_connector_alloc(void)
5982 {
5983         struct intel_connector *connector;
5984
5985         connector = kzalloc(sizeof *connector, GFP_KERNEL);
5986         if (!connector)
5987                 return NULL;
5988
5989         if (intel_connector_init(connector) < 0) {
5990                 kfree(connector);
5991                 return NULL;
5992         }
5993
5994         return connector;
5995 }
5996
5997 /* Simple connector->get_hw_state implementation for encoders that support only
5998  * one connector and no cloning and hence the encoder state determines the state
5999  * of the connector. */
6000 bool intel_connector_get_hw_state(struct intel_connector *connector)
6001 {
6002         enum pipe pipe = 0;
6003         struct intel_encoder *encoder = connector->encoder;
6004
6005         return encoder->get_hw_state(encoder, &pipe);
6006 }
6007
6008 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6009 {
6010         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6011                 return crtc_state->fdi_lanes;
6012
6013         return 0;
6014 }
6015
6016 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6017                                      struct intel_crtc_state *pipe_config)
6018 {
6019         struct drm_i915_private *dev_priv = to_i915(dev);
6020         struct drm_atomic_state *state = pipe_config->base.state;
6021         struct intel_crtc *other_crtc;
6022         struct intel_crtc_state *other_crtc_state;
6023
6024         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6025                       pipe_name(pipe), pipe_config->fdi_lanes);
6026         if (pipe_config->fdi_lanes > 4) {
6027                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6028                               pipe_name(pipe), pipe_config->fdi_lanes);
6029                 return -EINVAL;
6030         }
6031
6032         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6033                 if (pipe_config->fdi_lanes > 2) {
6034                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6035                                       pipe_config->fdi_lanes);
6036                         return -EINVAL;
6037                 } else {
6038                         return 0;
6039                 }
6040         }
6041
6042         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6043                 return 0;
6044
6045         /* Ivybridge 3 pipe is really complicated */
6046         switch (pipe) {
6047         case PIPE_A:
6048                 return 0;
6049         case PIPE_B:
6050                 if (pipe_config->fdi_lanes <= 2)
6051                         return 0;
6052
6053                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6054                 other_crtc_state =
6055                         intel_atomic_get_crtc_state(state, other_crtc);
6056                 if (IS_ERR(other_crtc_state))
6057                         return PTR_ERR(other_crtc_state);
6058
6059                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6060                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6061                                       pipe_name(pipe), pipe_config->fdi_lanes);
6062                         return -EINVAL;
6063                 }
6064                 return 0;
6065         case PIPE_C:
6066                 if (pipe_config->fdi_lanes > 2) {
6067                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6068                                       pipe_name(pipe), pipe_config->fdi_lanes);
6069                         return -EINVAL;
6070                 }
6071
6072                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6073                 other_crtc_state =
6074                         intel_atomic_get_crtc_state(state, other_crtc);
6075                 if (IS_ERR(other_crtc_state))
6076                         return PTR_ERR(other_crtc_state);
6077
6078                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6079                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6080                         return -EINVAL;
6081                 }
6082                 return 0;
6083         default:
6084                 BUG();
6085         }
6086 }
6087
6088 #define RETRY 1
6089 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6090                                        struct intel_crtc_state *pipe_config)
6091 {
6092         struct drm_device *dev = intel_crtc->base.dev;
6093         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6094         int lane, link_bw, fdi_dotclock, ret;
6095         bool needs_recompute = false;
6096
6097 retry:
6098         /* FDI is a binary signal running at ~2.7GHz, encoding
6099          * each output octet as 10 bits. The actual frequency
6100          * is stored as a divider into a 100MHz clock, and the
6101          * mode pixel clock is stored in units of 1KHz.
6102          * Hence the bw of each lane in terms of the mode signal
6103          * is:
6104          */
6105         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6106
6107         fdi_dotclock = adjusted_mode->crtc_clock;
6108
6109         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6110                                            pipe_config->pipe_bpp);
6111
6112         pipe_config->fdi_lanes = lane;
6113
6114         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6115                                link_bw, &pipe_config->fdi_m_n);
6116
6117         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6118         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6119                 pipe_config->pipe_bpp -= 2*3;
6120                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6121                               pipe_config->pipe_bpp);
6122                 needs_recompute = true;
6123                 pipe_config->bw_constrained = true;
6124
6125                 goto retry;
6126         }
6127
6128         if (needs_recompute)
6129                 return RETRY;
6130
6131         return ret;
6132 }
6133
6134 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6135                                      struct intel_crtc_state *pipe_config)
6136 {
6137         if (pipe_config->pipe_bpp > 24)
6138                 return false;
6139
6140         /* HSW can handle pixel rate up to cdclk? */
6141         if (IS_HASWELL(dev_priv))
6142                 return true;
6143
6144         /*
6145          * We compare against max which means we must take
6146          * the increased cdclk requirement into account when
6147          * calculating the new cdclk.
6148          *
6149          * Should measure whether using a lower cdclk w/o IPS
6150          */
6151         return pipe_config->pixel_rate <=
6152                 dev_priv->max_cdclk_freq * 95 / 100;
6153 }
6154
6155 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6156                                    struct intel_crtc_state *pipe_config)
6157 {
6158         struct drm_device *dev = crtc->base.dev;
6159         struct drm_i915_private *dev_priv = to_i915(dev);
6160
6161         pipe_config->ips_enabled = i915.enable_ips &&
6162                 hsw_crtc_supports_ips(crtc) &&
6163                 pipe_config_supports_ips(dev_priv, pipe_config);
6164 }
6165
6166 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6167 {
6168         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6169
6170         /* GDG double wide on either pipe, otherwise pipe A only */
6171         return INTEL_INFO(dev_priv)->gen < 4 &&
6172                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6173 }
6174
6175 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6176 {
6177         uint32_t pixel_rate;
6178
6179         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6180
6181         /*
6182          * We only use IF-ID interlacing. If we ever use
6183          * PF-ID we'll need to adjust the pixel_rate here.
6184          */
6185
6186         if (pipe_config->pch_pfit.enabled) {
6187                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6188                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6189
6190                 pipe_w = pipe_config->pipe_src_w;
6191                 pipe_h = pipe_config->pipe_src_h;
6192
6193                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6194                 pfit_h = pfit_size & 0xFFFF;
6195                 if (pipe_w < pfit_w)
6196                         pipe_w = pfit_w;
6197                 if (pipe_h < pfit_h)
6198                         pipe_h = pfit_h;
6199
6200                 if (WARN_ON(!pfit_w || !pfit_h))
6201                         return pixel_rate;
6202
6203                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6204                                      pfit_w * pfit_h);
6205         }
6206
6207         return pixel_rate;
6208 }
6209
6210 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6211 {
6212         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6213
6214         if (HAS_GMCH_DISPLAY(dev_priv))
6215                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6216                 crtc_state->pixel_rate =
6217                         crtc_state->base.adjusted_mode.crtc_clock;
6218         else
6219                 crtc_state->pixel_rate =
6220                         ilk_pipe_pixel_rate(crtc_state);
6221 }
6222
6223 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6224                                      struct intel_crtc_state *pipe_config)
6225 {
6226         struct drm_device *dev = crtc->base.dev;
6227         struct drm_i915_private *dev_priv = to_i915(dev);
6228         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6229         int clock_limit = dev_priv->max_dotclk_freq;
6230
6231         if (INTEL_GEN(dev_priv) < 4) {
6232                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6233
6234                 /*
6235                  * Enable double wide mode when the dot clock
6236                  * is > 90% of the (display) core speed.
6237                  */
6238                 if (intel_crtc_supports_double_wide(crtc) &&
6239                     adjusted_mode->crtc_clock > clock_limit) {
6240                         clock_limit = dev_priv->max_dotclk_freq;
6241                         pipe_config->double_wide = true;
6242                 }
6243         }
6244
6245         if (adjusted_mode->crtc_clock > clock_limit) {
6246                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6247                               adjusted_mode->crtc_clock, clock_limit,
6248                               yesno(pipe_config->double_wide));
6249                 return -EINVAL;
6250         }
6251
6252         /*
6253          * Pipe horizontal size must be even in:
6254          * - DVO ganged mode
6255          * - LVDS dual channel mode
6256          * - Double wide pipe
6257          */
6258         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6259              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6260                 pipe_config->pipe_src_w &= ~1;
6261
6262         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6263          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6264          */
6265         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6266                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6267                 return -EINVAL;
6268
6269         intel_crtc_compute_pixel_rate(pipe_config);
6270
6271         if (HAS_IPS(dev_priv))
6272                 hsw_compute_ips_config(crtc, pipe_config);
6273
6274         if (pipe_config->has_pch_encoder)
6275                 return ironlake_fdi_compute_config(crtc, pipe_config);
6276
6277         return 0;
6278 }
6279
6280 static void
6281 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6282 {
6283         while (*num > DATA_LINK_M_N_MASK ||
6284                *den > DATA_LINK_M_N_MASK) {
6285                 *num >>= 1;
6286                 *den >>= 1;
6287         }
6288 }
6289
6290 static void compute_m_n(unsigned int m, unsigned int n,
6291                         uint32_t *ret_m, uint32_t *ret_n)
6292 {
6293         /*
6294          * Reduce M/N as much as possible without loss in precision. Several DP
6295          * dongles in particular seem to be fussy about too large *link* M/N
6296          * values. The passed in values are more likely to have the least
6297          * significant bits zero than M after rounding below, so do this first.
6298          */
6299         while ((m & 1) == 0 && (n & 1) == 0) {
6300                 m >>= 1;
6301                 n >>= 1;
6302         }
6303
6304         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6305         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6306         intel_reduce_m_n_ratio(ret_m, ret_n);
6307 }
6308
6309 void
6310 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6311                        int pixel_clock, int link_clock,
6312                        struct intel_link_m_n *m_n)
6313 {
6314         m_n->tu = 64;
6315
6316         compute_m_n(bits_per_pixel * pixel_clock,
6317                     link_clock * nlanes * 8,
6318                     &m_n->gmch_m, &m_n->gmch_n);
6319
6320         compute_m_n(pixel_clock, link_clock,
6321                     &m_n->link_m, &m_n->link_n);
6322 }
6323
6324 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6325 {
6326         if (i915.panel_use_ssc >= 0)
6327                 return i915.panel_use_ssc != 0;
6328         return dev_priv->vbt.lvds_use_ssc
6329                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6330 }
6331
6332 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6333 {
6334         return (1 << dpll->n) << 16 | dpll->m2;
6335 }
6336
6337 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6338 {
6339         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6340 }
6341
6342 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6343                                      struct intel_crtc_state *crtc_state,
6344                                      struct dpll *reduced_clock)
6345 {
6346         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6347         u32 fp, fp2 = 0;
6348
6349         if (IS_PINEVIEW(dev_priv)) {
6350                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6351                 if (reduced_clock)
6352                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6353         } else {
6354                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6355                 if (reduced_clock)
6356                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6357         }
6358
6359         crtc_state->dpll_hw_state.fp0 = fp;
6360
6361         crtc->lowfreq_avail = false;
6362         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6363             reduced_clock) {
6364                 crtc_state->dpll_hw_state.fp1 = fp2;
6365                 crtc->lowfreq_avail = true;
6366         } else {
6367                 crtc_state->dpll_hw_state.fp1 = fp;
6368         }
6369 }
6370
6371 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6372                 pipe)
6373 {
6374         u32 reg_val;
6375
6376         /*
6377          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6378          * and set it to a reasonable value instead.
6379          */
6380         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6381         reg_val &= 0xffffff00;
6382         reg_val |= 0x00000030;
6383         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6384
6385         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6386         reg_val &= 0x8cffffff;
6387         reg_val = 0x8c000000;
6388         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6389
6390         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6391         reg_val &= 0xffffff00;
6392         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6393
6394         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6395         reg_val &= 0x00ffffff;
6396         reg_val |= 0xb0000000;
6397         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6398 }
6399
6400 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6401                                          struct intel_link_m_n *m_n)
6402 {
6403         struct drm_device *dev = crtc->base.dev;
6404         struct drm_i915_private *dev_priv = to_i915(dev);
6405         int pipe = crtc->pipe;
6406
6407         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6408         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6409         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6410         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6411 }
6412
6413 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6414                                          struct intel_link_m_n *m_n,
6415                                          struct intel_link_m_n *m2_n2)
6416 {
6417         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6418         int pipe = crtc->pipe;
6419         enum transcoder transcoder = crtc->config->cpu_transcoder;
6420
6421         if (INTEL_GEN(dev_priv) >= 5) {
6422                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6423                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6424                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6425                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6426                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6427                  * for gen < 8) and if DRRS is supported (to make sure the
6428                  * registers are not unnecessarily accessed).
6429                  */
6430                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6431                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6432                         I915_WRITE(PIPE_DATA_M2(transcoder),
6433                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6434                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6435                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6436                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6437                 }
6438         } else {
6439                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6440                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6441                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6442                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6443         }
6444 }
6445
6446 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6447 {
6448         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6449
6450         if (m_n == M1_N1) {
6451                 dp_m_n = &crtc->config->dp_m_n;
6452                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6453         } else if (m_n == M2_N2) {
6454
6455                 /*
6456                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6457                  * needs to be programmed into M1_N1.
6458                  */
6459                 dp_m_n = &crtc->config->dp_m2_n2;
6460         } else {
6461                 DRM_ERROR("Unsupported divider value\n");
6462                 return;
6463         }
6464
6465         if (crtc->config->has_pch_encoder)
6466                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6467         else
6468                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6469 }
6470
6471 static void vlv_compute_dpll(struct intel_crtc *crtc,
6472                              struct intel_crtc_state *pipe_config)
6473 {
6474         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6475                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6476         if (crtc->pipe != PIPE_A)
6477                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6478
6479         /* DPLL not used with DSI, but still need the rest set up */
6480         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6481                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6482                         DPLL_EXT_BUFFER_ENABLE_VLV;
6483
6484         pipe_config->dpll_hw_state.dpll_md =
6485                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6486 }
6487
6488 static void chv_compute_dpll(struct intel_crtc *crtc,
6489                              struct intel_crtc_state *pipe_config)
6490 {
6491         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6492                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6493         if (crtc->pipe != PIPE_A)
6494                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6495
6496         /* DPLL not used with DSI, but still need the rest set up */
6497         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6498                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6499
6500         pipe_config->dpll_hw_state.dpll_md =
6501                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6502 }
6503
6504 static void vlv_prepare_pll(struct intel_crtc *crtc,
6505                             const struct intel_crtc_state *pipe_config)
6506 {
6507         struct drm_device *dev = crtc->base.dev;
6508         struct drm_i915_private *dev_priv = to_i915(dev);
6509         enum pipe pipe = crtc->pipe;
6510         u32 mdiv;
6511         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6512         u32 coreclk, reg_val;
6513
6514         /* Enable Refclk */
6515         I915_WRITE(DPLL(pipe),
6516                    pipe_config->dpll_hw_state.dpll &
6517                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6518
6519         /* No need to actually set up the DPLL with DSI */
6520         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6521                 return;
6522
6523         mutex_lock(&dev_priv->sb_lock);
6524
6525         bestn = pipe_config->dpll.n;
6526         bestm1 = pipe_config->dpll.m1;
6527         bestm2 = pipe_config->dpll.m2;
6528         bestp1 = pipe_config->dpll.p1;
6529         bestp2 = pipe_config->dpll.p2;
6530
6531         /* See eDP HDMI DPIO driver vbios notes doc */
6532
6533         /* PLL B needs special handling */
6534         if (pipe == PIPE_B)
6535                 vlv_pllb_recal_opamp(dev_priv, pipe);
6536
6537         /* Set up Tx target for periodic Rcomp update */
6538         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6539
6540         /* Disable target IRef on PLL */
6541         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6542         reg_val &= 0x00ffffff;
6543         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6544
6545         /* Disable fast lock */
6546         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6547
6548         /* Set idtafcrecal before PLL is enabled */
6549         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6550         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6551         mdiv |= ((bestn << DPIO_N_SHIFT));
6552         mdiv |= (1 << DPIO_K_SHIFT);
6553
6554         /*
6555          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6556          * but we don't support that).
6557          * Note: don't use the DAC post divider as it seems unstable.
6558          */
6559         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6560         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6561
6562         mdiv |= DPIO_ENABLE_CALIBRATION;
6563         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6564
6565         /* Set HBR and RBR LPF coefficients */
6566         if (pipe_config->port_clock == 162000 ||
6567             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6568             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6569                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6570                                  0x009f0003);
6571         else
6572                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6573                                  0x00d0000f);
6574
6575         if (intel_crtc_has_dp_encoder(pipe_config)) {
6576                 /* Use SSC source */
6577                 if (pipe == PIPE_A)
6578                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6579                                          0x0df40000);
6580                 else
6581                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6582                                          0x0df70000);
6583         } else { /* HDMI or VGA */
6584                 /* Use bend source */
6585                 if (pipe == PIPE_A)
6586                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6587                                          0x0df70000);
6588                 else
6589                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6590                                          0x0df40000);
6591         }
6592
6593         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6594         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6595         if (intel_crtc_has_dp_encoder(crtc->config))
6596                 coreclk |= 0x01000000;
6597         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6598
6599         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6600         mutex_unlock(&dev_priv->sb_lock);
6601 }
6602
6603 static void chv_prepare_pll(struct intel_crtc *crtc,
6604                             const struct intel_crtc_state *pipe_config)
6605 {
6606         struct drm_device *dev = crtc->base.dev;
6607         struct drm_i915_private *dev_priv = to_i915(dev);
6608         enum pipe pipe = crtc->pipe;
6609         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6610         u32 loopfilter, tribuf_calcntr;
6611         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6612         u32 dpio_val;
6613         int vco;
6614
6615         /* Enable Refclk and SSC */
6616         I915_WRITE(DPLL(pipe),
6617                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6618
6619         /* No need to actually set up the DPLL with DSI */
6620         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6621                 return;
6622
6623         bestn = pipe_config->dpll.n;
6624         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6625         bestm1 = pipe_config->dpll.m1;
6626         bestm2 = pipe_config->dpll.m2 >> 22;
6627         bestp1 = pipe_config->dpll.p1;
6628         bestp2 = pipe_config->dpll.p2;
6629         vco = pipe_config->dpll.vco;
6630         dpio_val = 0;
6631         loopfilter = 0;
6632
6633         mutex_lock(&dev_priv->sb_lock);
6634
6635         /* p1 and p2 divider */
6636         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6637                         5 << DPIO_CHV_S1_DIV_SHIFT |
6638                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6639                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6640                         1 << DPIO_CHV_K_DIV_SHIFT);
6641
6642         /* Feedback post-divider - m2 */
6643         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6644
6645         /* Feedback refclk divider - n and m1 */
6646         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6647                         DPIO_CHV_M1_DIV_BY_2 |
6648                         1 << DPIO_CHV_N_DIV_SHIFT);
6649
6650         /* M2 fraction division */
6651         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6652
6653         /* M2 fraction division enable */
6654         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6655         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6656         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6657         if (bestm2_frac)
6658                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6659         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6660
6661         /* Program digital lock detect threshold */
6662         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6663         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6664                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6665         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6666         if (!bestm2_frac)
6667                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6668         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6669
6670         /* Loop filter */
6671         if (vco == 5400000) {
6672                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6673                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6674                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6675                 tribuf_calcntr = 0x9;
6676         } else if (vco <= 6200000) {
6677                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6678                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6679                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6680                 tribuf_calcntr = 0x9;
6681         } else if (vco <= 6480000) {
6682                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6683                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6684                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6685                 tribuf_calcntr = 0x8;
6686         } else {
6687                 /* Not supported. Apply the same limits as in the max case */
6688                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6689                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6690                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6691                 tribuf_calcntr = 0;
6692         }
6693         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6694
6695         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6696         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6697         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6698         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6699
6700         /* AFC Recal */
6701         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6702                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6703                         DPIO_AFC_RECAL);
6704
6705         mutex_unlock(&dev_priv->sb_lock);
6706 }
6707
6708 /**
6709  * vlv_force_pll_on - forcibly enable just the PLL
6710  * @dev_priv: i915 private structure
6711  * @pipe: pipe PLL to enable
6712  * @dpll: PLL configuration
6713  *
6714  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6715  * in cases where we need the PLL enabled even when @pipe is not going to
6716  * be enabled.
6717  */
6718 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6719                      const struct dpll *dpll)
6720 {
6721         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6722         struct intel_crtc_state *pipe_config;
6723
6724         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6725         if (!pipe_config)
6726                 return -ENOMEM;
6727
6728         pipe_config->base.crtc = &crtc->base;
6729         pipe_config->pixel_multiplier = 1;
6730         pipe_config->dpll = *dpll;
6731
6732         if (IS_CHERRYVIEW(dev_priv)) {
6733                 chv_compute_dpll(crtc, pipe_config);
6734                 chv_prepare_pll(crtc, pipe_config);
6735                 chv_enable_pll(crtc, pipe_config);
6736         } else {
6737                 vlv_compute_dpll(crtc, pipe_config);
6738                 vlv_prepare_pll(crtc, pipe_config);
6739                 vlv_enable_pll(crtc, pipe_config);
6740         }
6741
6742         kfree(pipe_config);
6743
6744         return 0;
6745 }
6746
6747 /**
6748  * vlv_force_pll_off - forcibly disable just the PLL
6749  * @dev_priv: i915 private structure
6750  * @pipe: pipe PLL to disable
6751  *
6752  * Disable the PLL for @pipe. To be used in cases where we need
6753  * the PLL enabled even when @pipe is not going to be enabled.
6754  */
6755 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6756 {
6757         if (IS_CHERRYVIEW(dev_priv))
6758                 chv_disable_pll(dev_priv, pipe);
6759         else
6760                 vlv_disable_pll(dev_priv, pipe);
6761 }
6762
6763 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6764                               struct intel_crtc_state *crtc_state,
6765                               struct dpll *reduced_clock)
6766 {
6767         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6768         u32 dpll;
6769         struct dpll *clock = &crtc_state->dpll;
6770
6771         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6772
6773         dpll = DPLL_VGA_MODE_DIS;
6774
6775         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6776                 dpll |= DPLLB_MODE_LVDS;
6777         else
6778                 dpll |= DPLLB_MODE_DAC_SERIAL;
6779
6780         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6781             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6782                 dpll |= (crtc_state->pixel_multiplier - 1)
6783                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6784         }
6785
6786         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6787             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6788                 dpll |= DPLL_SDVO_HIGH_SPEED;
6789
6790         if (intel_crtc_has_dp_encoder(crtc_state))
6791                 dpll |= DPLL_SDVO_HIGH_SPEED;
6792
6793         /* compute bitmask from p1 value */
6794         if (IS_PINEVIEW(dev_priv))
6795                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6796         else {
6797                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6798                 if (IS_G4X(dev_priv) && reduced_clock)
6799                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6800         }
6801         switch (clock->p2) {
6802         case 5:
6803                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6804                 break;
6805         case 7:
6806                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6807                 break;
6808         case 10:
6809                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6810                 break;
6811         case 14:
6812                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6813                 break;
6814         }
6815         if (INTEL_GEN(dev_priv) >= 4)
6816                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6817
6818         if (crtc_state->sdvo_tv_clock)
6819                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6820         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6821                  intel_panel_use_ssc(dev_priv))
6822                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6823         else
6824                 dpll |= PLL_REF_INPUT_DREFCLK;
6825
6826         dpll |= DPLL_VCO_ENABLE;
6827         crtc_state->dpll_hw_state.dpll = dpll;
6828
6829         if (INTEL_GEN(dev_priv) >= 4) {
6830                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6831                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6832                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6833         }
6834 }
6835
6836 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6837                               struct intel_crtc_state *crtc_state,
6838                               struct dpll *reduced_clock)
6839 {
6840         struct drm_device *dev = crtc->base.dev;
6841         struct drm_i915_private *dev_priv = to_i915(dev);
6842         u32 dpll;
6843         struct dpll *clock = &crtc_state->dpll;
6844
6845         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6846
6847         dpll = DPLL_VGA_MODE_DIS;
6848
6849         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6850                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6851         } else {
6852                 if (clock->p1 == 2)
6853                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6854                 else
6855                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6856                 if (clock->p2 == 4)
6857                         dpll |= PLL_P2_DIVIDE_BY_4;
6858         }
6859
6860         if (!IS_I830(dev_priv) &&
6861             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6862                 dpll |= DPLL_DVO_2X_MODE;
6863
6864         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6865             intel_panel_use_ssc(dev_priv))
6866                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6867         else
6868                 dpll |= PLL_REF_INPUT_DREFCLK;
6869
6870         dpll |= DPLL_VCO_ENABLE;
6871         crtc_state->dpll_hw_state.dpll = dpll;
6872 }
6873
6874 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6875 {
6876         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6877         enum pipe pipe = intel_crtc->pipe;
6878         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6879         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6880         uint32_t crtc_vtotal, crtc_vblank_end;
6881         int vsyncshift = 0;
6882
6883         /* We need to be careful not to changed the adjusted mode, for otherwise
6884          * the hw state checker will get angry at the mismatch. */
6885         crtc_vtotal = adjusted_mode->crtc_vtotal;
6886         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6887
6888         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6889                 /* the chip adds 2 halflines automatically */
6890                 crtc_vtotal -= 1;
6891                 crtc_vblank_end -= 1;
6892
6893                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6894                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6895                 else
6896                         vsyncshift = adjusted_mode->crtc_hsync_start -
6897                                 adjusted_mode->crtc_htotal / 2;
6898                 if (vsyncshift < 0)
6899                         vsyncshift += adjusted_mode->crtc_htotal;
6900         }
6901
6902         if (INTEL_GEN(dev_priv) > 3)
6903                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6904
6905         I915_WRITE(HTOTAL(cpu_transcoder),
6906                    (adjusted_mode->crtc_hdisplay - 1) |
6907                    ((adjusted_mode->crtc_htotal - 1) << 16));
6908         I915_WRITE(HBLANK(cpu_transcoder),
6909                    (adjusted_mode->crtc_hblank_start - 1) |
6910                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6911         I915_WRITE(HSYNC(cpu_transcoder),
6912                    (adjusted_mode->crtc_hsync_start - 1) |
6913                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6914
6915         I915_WRITE(VTOTAL(cpu_transcoder),
6916                    (adjusted_mode->crtc_vdisplay - 1) |
6917                    ((crtc_vtotal - 1) << 16));
6918         I915_WRITE(VBLANK(cpu_transcoder),
6919                    (adjusted_mode->crtc_vblank_start - 1) |
6920                    ((crtc_vblank_end - 1) << 16));
6921         I915_WRITE(VSYNC(cpu_transcoder),
6922                    (adjusted_mode->crtc_vsync_start - 1) |
6923                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6924
6925         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6926          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6927          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6928          * bits. */
6929         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6930             (pipe == PIPE_B || pipe == PIPE_C))
6931                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6932
6933 }
6934
6935 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6936 {
6937         struct drm_device *dev = intel_crtc->base.dev;
6938         struct drm_i915_private *dev_priv = to_i915(dev);
6939         enum pipe pipe = intel_crtc->pipe;
6940
6941         /* pipesrc controls the size that is scaled from, which should
6942          * always be the user's requested size.
6943          */
6944         I915_WRITE(PIPESRC(pipe),
6945                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6946                    (intel_crtc->config->pipe_src_h - 1));
6947 }
6948
6949 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6950                                    struct intel_crtc_state *pipe_config)
6951 {
6952         struct drm_device *dev = crtc->base.dev;
6953         struct drm_i915_private *dev_priv = to_i915(dev);
6954         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6955         uint32_t tmp;
6956
6957         tmp = I915_READ(HTOTAL(cpu_transcoder));
6958         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6959         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6960         tmp = I915_READ(HBLANK(cpu_transcoder));
6961         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6962         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6963         tmp = I915_READ(HSYNC(cpu_transcoder));
6964         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6965         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6966
6967         tmp = I915_READ(VTOTAL(cpu_transcoder));
6968         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6969         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6970         tmp = I915_READ(VBLANK(cpu_transcoder));
6971         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6972         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6973         tmp = I915_READ(VSYNC(cpu_transcoder));
6974         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6975         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6976
6977         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6978                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6979                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6980                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6981         }
6982 }
6983
6984 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
6985                                     struct intel_crtc_state *pipe_config)
6986 {
6987         struct drm_device *dev = crtc->base.dev;
6988         struct drm_i915_private *dev_priv = to_i915(dev);
6989         u32 tmp;
6990
6991         tmp = I915_READ(PIPESRC(crtc->pipe));
6992         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6993         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6994
6995         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6996         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6997 }
6998
6999 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7000                                  struct intel_crtc_state *pipe_config)
7001 {
7002         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7003         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7004         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7005         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7006
7007         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7008         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7009         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7010         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7011
7012         mode->flags = pipe_config->base.adjusted_mode.flags;
7013         mode->type = DRM_MODE_TYPE_DRIVER;
7014
7015         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7016
7017         mode->hsync = drm_mode_hsync(mode);
7018         mode->vrefresh = drm_mode_vrefresh(mode);
7019         drm_mode_set_name(mode);
7020 }
7021
7022 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7023 {
7024         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7025         uint32_t pipeconf;
7026
7027         pipeconf = 0;
7028
7029         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7030             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7031                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7032
7033         if (intel_crtc->config->double_wide)
7034                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7035
7036         /* only g4x and later have fancy bpc/dither controls */
7037         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7038             IS_CHERRYVIEW(dev_priv)) {
7039                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7040                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7041                         pipeconf |= PIPECONF_DITHER_EN |
7042                                     PIPECONF_DITHER_TYPE_SP;
7043
7044                 switch (intel_crtc->config->pipe_bpp) {
7045                 case 18:
7046                         pipeconf |= PIPECONF_6BPC;
7047                         break;
7048                 case 24:
7049                         pipeconf |= PIPECONF_8BPC;
7050                         break;
7051                 case 30:
7052                         pipeconf |= PIPECONF_10BPC;
7053                         break;
7054                 default:
7055                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7056                         BUG();
7057                 }
7058         }
7059
7060         if (HAS_PIPE_CXSR(dev_priv)) {
7061                 if (intel_crtc->lowfreq_avail) {
7062                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7063                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7064                 } else {
7065                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7066                 }
7067         }
7068
7069         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7070                 if (INTEL_GEN(dev_priv) < 4 ||
7071                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7072                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7073                 else
7074                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7075         } else
7076                 pipeconf |= PIPECONF_PROGRESSIVE;
7077
7078         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7079              intel_crtc->config->limited_color_range)
7080                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7081
7082         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7083         POSTING_READ(PIPECONF(intel_crtc->pipe));
7084 }
7085
7086 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7087                                    struct intel_crtc_state *crtc_state)
7088 {
7089         struct drm_device *dev = crtc->base.dev;
7090         struct drm_i915_private *dev_priv = to_i915(dev);
7091         const struct intel_limit *limit;
7092         int refclk = 48000;
7093
7094         memset(&crtc_state->dpll_hw_state, 0,
7095                sizeof(crtc_state->dpll_hw_state));
7096
7097         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7098                 if (intel_panel_use_ssc(dev_priv)) {
7099                         refclk = dev_priv->vbt.lvds_ssc_freq;
7100                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7101                 }
7102
7103                 limit = &intel_limits_i8xx_lvds;
7104         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7105                 limit = &intel_limits_i8xx_dvo;
7106         } else {
7107                 limit = &intel_limits_i8xx_dac;
7108         }
7109
7110         if (!crtc_state->clock_set &&
7111             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7112                                  refclk, NULL, &crtc_state->dpll)) {
7113                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7114                 return -EINVAL;
7115         }
7116
7117         i8xx_compute_dpll(crtc, crtc_state, NULL);
7118
7119         return 0;
7120 }
7121
7122 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7123                                   struct intel_crtc_state *crtc_state)
7124 {
7125         struct drm_device *dev = crtc->base.dev;
7126         struct drm_i915_private *dev_priv = to_i915(dev);
7127         const struct intel_limit *limit;
7128         int refclk = 96000;
7129
7130         memset(&crtc_state->dpll_hw_state, 0,
7131                sizeof(crtc_state->dpll_hw_state));
7132
7133         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7134                 if (intel_panel_use_ssc(dev_priv)) {
7135                         refclk = dev_priv->vbt.lvds_ssc_freq;
7136                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7137                 }
7138
7139                 if (intel_is_dual_link_lvds(dev))
7140                         limit = &intel_limits_g4x_dual_channel_lvds;
7141                 else
7142                         limit = &intel_limits_g4x_single_channel_lvds;
7143         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7144                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7145                 limit = &intel_limits_g4x_hdmi;
7146         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7147                 limit = &intel_limits_g4x_sdvo;
7148         } else {
7149                 /* The option is for other outputs */
7150                 limit = &intel_limits_i9xx_sdvo;
7151         }
7152
7153         if (!crtc_state->clock_set &&
7154             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7155                                 refclk, NULL, &crtc_state->dpll)) {
7156                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7157                 return -EINVAL;
7158         }
7159
7160         i9xx_compute_dpll(crtc, crtc_state, NULL);
7161
7162         return 0;
7163 }
7164
7165 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7166                                   struct intel_crtc_state *crtc_state)
7167 {
7168         struct drm_device *dev = crtc->base.dev;
7169         struct drm_i915_private *dev_priv = to_i915(dev);
7170         const struct intel_limit *limit;
7171         int refclk = 96000;
7172
7173         memset(&crtc_state->dpll_hw_state, 0,
7174                sizeof(crtc_state->dpll_hw_state));
7175
7176         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7177                 if (intel_panel_use_ssc(dev_priv)) {
7178                         refclk = dev_priv->vbt.lvds_ssc_freq;
7179                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7180                 }
7181
7182                 limit = &intel_limits_pineview_lvds;
7183         } else {
7184                 limit = &intel_limits_pineview_sdvo;
7185         }
7186
7187         if (!crtc_state->clock_set &&
7188             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7189                                 refclk, NULL, &crtc_state->dpll)) {
7190                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7191                 return -EINVAL;
7192         }
7193
7194         i9xx_compute_dpll(crtc, crtc_state, NULL);
7195
7196         return 0;
7197 }
7198
7199 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7200                                    struct intel_crtc_state *crtc_state)
7201 {
7202         struct drm_device *dev = crtc->base.dev;
7203         struct drm_i915_private *dev_priv = to_i915(dev);
7204         const struct intel_limit *limit;
7205         int refclk = 96000;
7206
7207         memset(&crtc_state->dpll_hw_state, 0,
7208                sizeof(crtc_state->dpll_hw_state));
7209
7210         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7211                 if (intel_panel_use_ssc(dev_priv)) {
7212                         refclk = dev_priv->vbt.lvds_ssc_freq;
7213                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7214                 }
7215
7216                 limit = &intel_limits_i9xx_lvds;
7217         } else {
7218                 limit = &intel_limits_i9xx_sdvo;
7219         }
7220
7221         if (!crtc_state->clock_set &&
7222             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7223                                  refclk, NULL, &crtc_state->dpll)) {
7224                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7225                 return -EINVAL;
7226         }
7227
7228         i9xx_compute_dpll(crtc, crtc_state, NULL);
7229
7230         return 0;
7231 }
7232
7233 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7234                                   struct intel_crtc_state *crtc_state)
7235 {
7236         int refclk = 100000;
7237         const struct intel_limit *limit = &intel_limits_chv;
7238
7239         memset(&crtc_state->dpll_hw_state, 0,
7240                sizeof(crtc_state->dpll_hw_state));
7241
7242         if (!crtc_state->clock_set &&
7243             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7244                                 refclk, NULL, &crtc_state->dpll)) {
7245                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7246                 return -EINVAL;
7247         }
7248
7249         chv_compute_dpll(crtc, crtc_state);
7250
7251         return 0;
7252 }
7253
7254 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7255                                   struct intel_crtc_state *crtc_state)
7256 {
7257         int refclk = 100000;
7258         const struct intel_limit *limit = &intel_limits_vlv;
7259
7260         memset(&crtc_state->dpll_hw_state, 0,
7261                sizeof(crtc_state->dpll_hw_state));
7262
7263         if (!crtc_state->clock_set &&
7264             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7265                                 refclk, NULL, &crtc_state->dpll)) {
7266                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7267                 return -EINVAL;
7268         }
7269
7270         vlv_compute_dpll(crtc, crtc_state);
7271
7272         return 0;
7273 }
7274
7275 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7276                                  struct intel_crtc_state *pipe_config)
7277 {
7278         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7279         uint32_t tmp;
7280
7281         if (INTEL_GEN(dev_priv) <= 3 &&
7282             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7283                 return;
7284
7285         tmp = I915_READ(PFIT_CONTROL);
7286         if (!(tmp & PFIT_ENABLE))
7287                 return;
7288
7289         /* Check whether the pfit is attached to our pipe. */
7290         if (INTEL_GEN(dev_priv) < 4) {
7291                 if (crtc->pipe != PIPE_B)
7292                         return;
7293         } else {
7294                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7295                         return;
7296         }
7297
7298         pipe_config->gmch_pfit.control = tmp;
7299         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7300 }
7301
7302 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7303                                struct intel_crtc_state *pipe_config)
7304 {
7305         struct drm_device *dev = crtc->base.dev;
7306         struct drm_i915_private *dev_priv = to_i915(dev);
7307         int pipe = pipe_config->cpu_transcoder;
7308         struct dpll clock;
7309         u32 mdiv;
7310         int refclk = 100000;
7311
7312         /* In case of DSI, DPLL will not be used */
7313         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7314                 return;
7315
7316         mutex_lock(&dev_priv->sb_lock);
7317         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7318         mutex_unlock(&dev_priv->sb_lock);
7319
7320         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7321         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7322         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7323         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7324         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7325
7326         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7327 }
7328
7329 static void
7330 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7331                               struct intel_initial_plane_config *plane_config)
7332 {
7333         struct drm_device *dev = crtc->base.dev;
7334         struct drm_i915_private *dev_priv = to_i915(dev);
7335         u32 val, base, offset;
7336         int pipe = crtc->pipe, plane = crtc->plane;
7337         int fourcc, pixel_format;
7338         unsigned int aligned_height;
7339         struct drm_framebuffer *fb;
7340         struct intel_framebuffer *intel_fb;
7341
7342         val = I915_READ(DSPCNTR(plane));
7343         if (!(val & DISPLAY_PLANE_ENABLE))
7344                 return;
7345
7346         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7347         if (!intel_fb) {
7348                 DRM_DEBUG_KMS("failed to alloc fb\n");
7349                 return;
7350         }
7351
7352         fb = &intel_fb->base;
7353
7354         fb->dev = dev;
7355
7356         if (INTEL_GEN(dev_priv) >= 4) {
7357                 if (val & DISPPLANE_TILED) {
7358                         plane_config->tiling = I915_TILING_X;
7359                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7360                 }
7361         }
7362
7363         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7364         fourcc = i9xx_format_to_fourcc(pixel_format);
7365         fb->format = drm_format_info(fourcc);
7366
7367         if (INTEL_GEN(dev_priv) >= 4) {
7368                 if (plane_config->tiling)
7369                         offset = I915_READ(DSPTILEOFF(plane));
7370                 else
7371                         offset = I915_READ(DSPLINOFF(plane));
7372                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7373         } else {
7374                 base = I915_READ(DSPADDR(plane));
7375         }
7376         plane_config->base = base;
7377
7378         val = I915_READ(PIPESRC(pipe));
7379         fb->width = ((val >> 16) & 0xfff) + 1;
7380         fb->height = ((val >> 0) & 0xfff) + 1;
7381
7382         val = I915_READ(DSPSTRIDE(pipe));
7383         fb->pitches[0] = val & 0xffffffc0;
7384
7385         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7386
7387         plane_config->size = fb->pitches[0] * aligned_height;
7388
7389         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7390                       pipe_name(pipe), plane, fb->width, fb->height,
7391                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7392                       plane_config->size);
7393
7394         plane_config->fb = intel_fb;
7395 }
7396
7397 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7398                                struct intel_crtc_state *pipe_config)
7399 {
7400         struct drm_device *dev = crtc->base.dev;
7401         struct drm_i915_private *dev_priv = to_i915(dev);
7402         int pipe = pipe_config->cpu_transcoder;
7403         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7404         struct dpll clock;
7405         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7406         int refclk = 100000;
7407
7408         /* In case of DSI, DPLL will not be used */
7409         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7410                 return;
7411
7412         mutex_lock(&dev_priv->sb_lock);
7413         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7414         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7415         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7416         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7417         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7418         mutex_unlock(&dev_priv->sb_lock);
7419
7420         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7421         clock.m2 = (pll_dw0 & 0xff) << 22;
7422         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7423                 clock.m2 |= pll_dw2 & 0x3fffff;
7424         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7425         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7426         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7427
7428         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7429 }
7430
7431 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7432                                  struct intel_crtc_state *pipe_config)
7433 {
7434         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7435         enum intel_display_power_domain power_domain;
7436         uint32_t tmp;
7437         bool ret;
7438
7439         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7440         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7441                 return false;
7442
7443         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7444         pipe_config->shared_dpll = NULL;
7445
7446         ret = false;
7447
7448         tmp = I915_READ(PIPECONF(crtc->pipe));
7449         if (!(tmp & PIPECONF_ENABLE))
7450                 goto out;
7451
7452         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7453             IS_CHERRYVIEW(dev_priv)) {
7454                 switch (tmp & PIPECONF_BPC_MASK) {
7455                 case PIPECONF_6BPC:
7456                         pipe_config->pipe_bpp = 18;
7457                         break;
7458                 case PIPECONF_8BPC:
7459                         pipe_config->pipe_bpp = 24;
7460                         break;
7461                 case PIPECONF_10BPC:
7462                         pipe_config->pipe_bpp = 30;
7463                         break;
7464                 default:
7465                         break;
7466                 }
7467         }
7468
7469         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7470             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7471                 pipe_config->limited_color_range = true;
7472
7473         if (INTEL_GEN(dev_priv) < 4)
7474                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7475
7476         intel_get_pipe_timings(crtc, pipe_config);
7477         intel_get_pipe_src_size(crtc, pipe_config);
7478
7479         i9xx_get_pfit_config(crtc, pipe_config);
7480
7481         if (INTEL_GEN(dev_priv) >= 4) {
7482                 /* No way to read it out on pipes B and C */
7483                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7484                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7485                 else
7486                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7487                 pipe_config->pixel_multiplier =
7488                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7489                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7490                 pipe_config->dpll_hw_state.dpll_md = tmp;
7491         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7492                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7493                 tmp = I915_READ(DPLL(crtc->pipe));
7494                 pipe_config->pixel_multiplier =
7495                         ((tmp & SDVO_MULTIPLIER_MASK)
7496                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7497         } else {
7498                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7499                  * port and will be fixed up in the encoder->get_config
7500                  * function. */
7501                 pipe_config->pixel_multiplier = 1;
7502         }
7503         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7504         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7505                 /*
7506                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7507                  * on 830. Filter it out here so that we don't
7508                  * report errors due to that.
7509                  */
7510                 if (IS_I830(dev_priv))
7511                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7512
7513                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7514                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7515         } else {
7516                 /* Mask out read-only status bits. */
7517                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7518                                                      DPLL_PORTC_READY_MASK |
7519                                                      DPLL_PORTB_READY_MASK);
7520         }
7521
7522         if (IS_CHERRYVIEW(dev_priv))
7523                 chv_crtc_clock_get(crtc, pipe_config);
7524         else if (IS_VALLEYVIEW(dev_priv))
7525                 vlv_crtc_clock_get(crtc, pipe_config);
7526         else
7527                 i9xx_crtc_clock_get(crtc, pipe_config);
7528
7529         /*
7530          * Normally the dotclock is filled in by the encoder .get_config()
7531          * but in case the pipe is enabled w/o any ports we need a sane
7532          * default.
7533          */
7534         pipe_config->base.adjusted_mode.crtc_clock =
7535                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7536
7537         ret = true;
7538
7539 out:
7540         intel_display_power_put(dev_priv, power_domain);
7541
7542         return ret;
7543 }
7544
7545 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7546 {
7547         struct intel_encoder *encoder;
7548         int i;
7549         u32 val, final;
7550         bool has_lvds = false;
7551         bool has_cpu_edp = false;
7552         bool has_panel = false;
7553         bool has_ck505 = false;
7554         bool can_ssc = false;
7555         bool using_ssc_source = false;
7556
7557         /* We need to take the global config into account */
7558         for_each_intel_encoder(&dev_priv->drm, encoder) {
7559                 switch (encoder->type) {
7560                 case INTEL_OUTPUT_LVDS:
7561                         has_panel = true;
7562                         has_lvds = true;
7563                         break;
7564                 case INTEL_OUTPUT_EDP:
7565                         has_panel = true;
7566                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7567                                 has_cpu_edp = true;
7568                         break;
7569                 default:
7570                         break;
7571                 }
7572         }
7573
7574         if (HAS_PCH_IBX(dev_priv)) {
7575                 has_ck505 = dev_priv->vbt.display_clock_mode;
7576                 can_ssc = has_ck505;
7577         } else {
7578                 has_ck505 = false;
7579                 can_ssc = true;
7580         }
7581
7582         /* Check if any DPLLs are using the SSC source */
7583         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7584                 u32 temp = I915_READ(PCH_DPLL(i));
7585
7586                 if (!(temp & DPLL_VCO_ENABLE))
7587                         continue;
7588
7589                 if ((temp & PLL_REF_INPUT_MASK) ==
7590                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7591                         using_ssc_source = true;
7592                         break;
7593                 }
7594         }
7595
7596         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7597                       has_panel, has_lvds, has_ck505, using_ssc_source);
7598
7599         /* Ironlake: try to setup display ref clock before DPLL
7600          * enabling. This is only under driver's control after
7601          * PCH B stepping, previous chipset stepping should be
7602          * ignoring this setting.
7603          */
7604         val = I915_READ(PCH_DREF_CONTROL);
7605
7606         /* As we must carefully and slowly disable/enable each source in turn,
7607          * compute the final state we want first and check if we need to
7608          * make any changes at all.
7609          */
7610         final = val;
7611         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7612         if (has_ck505)
7613                 final |= DREF_NONSPREAD_CK505_ENABLE;
7614         else
7615                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7616
7617         final &= ~DREF_SSC_SOURCE_MASK;
7618         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7619         final &= ~DREF_SSC1_ENABLE;
7620
7621         if (has_panel) {
7622                 final |= DREF_SSC_SOURCE_ENABLE;
7623
7624                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7625                         final |= DREF_SSC1_ENABLE;
7626
7627                 if (has_cpu_edp) {
7628                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7629                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7630                         else
7631                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7632                 } else
7633                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7634         } else if (using_ssc_source) {
7635                 final |= DREF_SSC_SOURCE_ENABLE;
7636                 final |= DREF_SSC1_ENABLE;
7637         }
7638
7639         if (final == val)
7640                 return;
7641
7642         /* Always enable nonspread source */
7643         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7644
7645         if (has_ck505)
7646                 val |= DREF_NONSPREAD_CK505_ENABLE;
7647         else
7648                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7649
7650         if (has_panel) {
7651                 val &= ~DREF_SSC_SOURCE_MASK;
7652                 val |= DREF_SSC_SOURCE_ENABLE;
7653
7654                 /* SSC must be turned on before enabling the CPU output  */
7655                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7656                         DRM_DEBUG_KMS("Using SSC on panel\n");
7657                         val |= DREF_SSC1_ENABLE;
7658                 } else
7659                         val &= ~DREF_SSC1_ENABLE;
7660
7661                 /* Get SSC going before enabling the outputs */
7662                 I915_WRITE(PCH_DREF_CONTROL, val);
7663                 POSTING_READ(PCH_DREF_CONTROL);
7664                 udelay(200);
7665
7666                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7667
7668                 /* Enable CPU source on CPU attached eDP */
7669                 if (has_cpu_edp) {
7670                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7671                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7672                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7673                         } else
7674                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7675                 } else
7676                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7677
7678                 I915_WRITE(PCH_DREF_CONTROL, val);
7679                 POSTING_READ(PCH_DREF_CONTROL);
7680                 udelay(200);
7681         } else {
7682                 DRM_DEBUG_KMS("Disabling CPU source output\n");
7683
7684                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7685
7686                 /* Turn off CPU output */
7687                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7688
7689                 I915_WRITE(PCH_DREF_CONTROL, val);
7690                 POSTING_READ(PCH_DREF_CONTROL);
7691                 udelay(200);
7692
7693                 if (!using_ssc_source) {
7694                         DRM_DEBUG_KMS("Disabling SSC source\n");
7695
7696                         /* Turn off the SSC source */
7697                         val &= ~DREF_SSC_SOURCE_MASK;
7698                         val |= DREF_SSC_SOURCE_DISABLE;
7699
7700                         /* Turn off SSC1 */
7701                         val &= ~DREF_SSC1_ENABLE;
7702
7703                         I915_WRITE(PCH_DREF_CONTROL, val);
7704                         POSTING_READ(PCH_DREF_CONTROL);
7705                         udelay(200);
7706                 }
7707         }
7708
7709         BUG_ON(val != final);
7710 }
7711
7712 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7713 {
7714         uint32_t tmp;
7715
7716         tmp = I915_READ(SOUTH_CHICKEN2);
7717         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7718         I915_WRITE(SOUTH_CHICKEN2, tmp);
7719
7720         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7721                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7722                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7723
7724         tmp = I915_READ(SOUTH_CHICKEN2);
7725         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7726         I915_WRITE(SOUTH_CHICKEN2, tmp);
7727
7728         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7729                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7730                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7731 }
7732
7733 /* WaMPhyProgramming:hsw */
7734 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7735 {
7736         uint32_t tmp;
7737
7738         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7739         tmp &= ~(0xFF << 24);
7740         tmp |= (0x12 << 24);
7741         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7742
7743         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7744         tmp |= (1 << 11);
7745         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7746
7747         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7748         tmp |= (1 << 11);
7749         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7750
7751         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7752         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7753         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7754
7755         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7756         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7757         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7758
7759         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7760         tmp &= ~(7 << 13);
7761         tmp |= (5 << 13);
7762         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7763
7764         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7765         tmp &= ~(7 << 13);
7766         tmp |= (5 << 13);
7767         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7768
7769         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7770         tmp &= ~0xFF;
7771         tmp |= 0x1C;
7772         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7773
7774         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7775         tmp &= ~0xFF;
7776         tmp |= 0x1C;
7777         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7778
7779         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7780         tmp &= ~(0xFF << 16);
7781         tmp |= (0x1C << 16);
7782         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7783
7784         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7785         tmp &= ~(0xFF << 16);
7786         tmp |= (0x1C << 16);
7787         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7788
7789         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7790         tmp |= (1 << 27);
7791         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7792
7793         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7794         tmp |= (1 << 27);
7795         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7796
7797         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7798         tmp &= ~(0xF << 28);
7799         tmp |= (4 << 28);
7800         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7801
7802         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7803         tmp &= ~(0xF << 28);
7804         tmp |= (4 << 28);
7805         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7806 }
7807
7808 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7809  * Programming" based on the parameters passed:
7810  * - Sequence to enable CLKOUT_DP
7811  * - Sequence to enable CLKOUT_DP without spread
7812  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7813  */
7814 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7815                                  bool with_spread, bool with_fdi)
7816 {
7817         uint32_t reg, tmp;
7818
7819         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7820                 with_spread = true;
7821         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7822             with_fdi, "LP PCH doesn't have FDI\n"))
7823                 with_fdi = false;
7824
7825         mutex_lock(&dev_priv->sb_lock);
7826
7827         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7828         tmp &= ~SBI_SSCCTL_DISABLE;
7829         tmp |= SBI_SSCCTL_PATHALT;
7830         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7831
7832         udelay(24);
7833
7834         if (with_spread) {
7835                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7836                 tmp &= ~SBI_SSCCTL_PATHALT;
7837                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7838
7839                 if (with_fdi) {
7840                         lpt_reset_fdi_mphy(dev_priv);
7841                         lpt_program_fdi_mphy(dev_priv);
7842                 }
7843         }
7844
7845         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7846         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7847         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7848         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7849
7850         mutex_unlock(&dev_priv->sb_lock);
7851 }
7852
7853 /* Sequence to disable CLKOUT_DP */
7854 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7855 {
7856         uint32_t reg, tmp;
7857
7858         mutex_lock(&dev_priv->sb_lock);
7859
7860         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7861         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7862         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7863         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7864
7865         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7866         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7867                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7868                         tmp |= SBI_SSCCTL_PATHALT;
7869                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7870                         udelay(32);
7871                 }
7872                 tmp |= SBI_SSCCTL_DISABLE;
7873                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7874         }
7875
7876         mutex_unlock(&dev_priv->sb_lock);
7877 }
7878
7879 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7880
7881 static const uint16_t sscdivintphase[] = {
7882         [BEND_IDX( 50)] = 0x3B23,
7883         [BEND_IDX( 45)] = 0x3B23,
7884         [BEND_IDX( 40)] = 0x3C23,
7885         [BEND_IDX( 35)] = 0x3C23,
7886         [BEND_IDX( 30)] = 0x3D23,
7887         [BEND_IDX( 25)] = 0x3D23,
7888         [BEND_IDX( 20)] = 0x3E23,
7889         [BEND_IDX( 15)] = 0x3E23,
7890         [BEND_IDX( 10)] = 0x3F23,
7891         [BEND_IDX(  5)] = 0x3F23,
7892         [BEND_IDX(  0)] = 0x0025,
7893         [BEND_IDX( -5)] = 0x0025,
7894         [BEND_IDX(-10)] = 0x0125,
7895         [BEND_IDX(-15)] = 0x0125,
7896         [BEND_IDX(-20)] = 0x0225,
7897         [BEND_IDX(-25)] = 0x0225,
7898         [BEND_IDX(-30)] = 0x0325,
7899         [BEND_IDX(-35)] = 0x0325,
7900         [BEND_IDX(-40)] = 0x0425,
7901         [BEND_IDX(-45)] = 0x0425,
7902         [BEND_IDX(-50)] = 0x0525,
7903 };
7904
7905 /*
7906  * Bend CLKOUT_DP
7907  * steps -50 to 50 inclusive, in steps of 5
7908  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7909  * change in clock period = -(steps / 10) * 5.787 ps
7910  */
7911 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7912 {
7913         uint32_t tmp;
7914         int idx = BEND_IDX(steps);
7915
7916         if (WARN_ON(steps % 5 != 0))
7917                 return;
7918
7919         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7920                 return;
7921
7922         mutex_lock(&dev_priv->sb_lock);
7923
7924         if (steps % 10 != 0)
7925                 tmp = 0xAAAAAAAB;
7926         else
7927                 tmp = 0x00000000;
7928         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7929
7930         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7931         tmp &= 0xffff0000;
7932         tmp |= sscdivintphase[idx];
7933         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7934
7935         mutex_unlock(&dev_priv->sb_lock);
7936 }
7937
7938 #undef BEND_IDX
7939
7940 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7941 {
7942         struct intel_encoder *encoder;
7943         bool has_vga = false;
7944
7945         for_each_intel_encoder(&dev_priv->drm, encoder) {
7946                 switch (encoder->type) {
7947                 case INTEL_OUTPUT_ANALOG:
7948                         has_vga = true;
7949                         break;
7950                 default:
7951                         break;
7952                 }
7953         }
7954
7955         if (has_vga) {
7956                 lpt_bend_clkout_dp(dev_priv, 0);
7957                 lpt_enable_clkout_dp(dev_priv, true, true);
7958         } else {
7959                 lpt_disable_clkout_dp(dev_priv);
7960         }
7961 }
7962
7963 /*
7964  * Initialize reference clocks when the driver loads
7965  */
7966 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7967 {
7968         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7969                 ironlake_init_pch_refclk(dev_priv);
7970         else if (HAS_PCH_LPT(dev_priv))
7971                 lpt_init_pch_refclk(dev_priv);
7972 }
7973
7974 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7975 {
7976         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7977         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7978         int pipe = intel_crtc->pipe;
7979         uint32_t val;
7980
7981         val = 0;
7982
7983         switch (intel_crtc->config->pipe_bpp) {
7984         case 18:
7985                 val |= PIPECONF_6BPC;
7986                 break;
7987         case 24:
7988                 val |= PIPECONF_8BPC;
7989                 break;
7990         case 30:
7991                 val |= PIPECONF_10BPC;
7992                 break;
7993         case 36:
7994                 val |= PIPECONF_12BPC;
7995                 break;
7996         default:
7997                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7998                 BUG();
7999         }
8000
8001         if (intel_crtc->config->dither)
8002                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8003
8004         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8005                 val |= PIPECONF_INTERLACED_ILK;
8006         else
8007                 val |= PIPECONF_PROGRESSIVE;
8008
8009         if (intel_crtc->config->limited_color_range)
8010                 val |= PIPECONF_COLOR_RANGE_SELECT;
8011
8012         I915_WRITE(PIPECONF(pipe), val);
8013         POSTING_READ(PIPECONF(pipe));
8014 }
8015
8016 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8017 {
8018         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8020         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8021         u32 val = 0;
8022
8023         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8024                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8025
8026         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8027                 val |= PIPECONF_INTERLACED_ILK;
8028         else
8029                 val |= PIPECONF_PROGRESSIVE;
8030
8031         I915_WRITE(PIPECONF(cpu_transcoder), val);
8032         POSTING_READ(PIPECONF(cpu_transcoder));
8033 }
8034
8035 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8036 {
8037         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8039
8040         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8041                 u32 val = 0;
8042
8043                 switch (intel_crtc->config->pipe_bpp) {
8044                 case 18:
8045                         val |= PIPEMISC_DITHER_6_BPC;
8046                         break;
8047                 case 24:
8048                         val |= PIPEMISC_DITHER_8_BPC;
8049                         break;
8050                 case 30:
8051                         val |= PIPEMISC_DITHER_10_BPC;
8052                         break;
8053                 case 36:
8054                         val |= PIPEMISC_DITHER_12_BPC;
8055                         break;
8056                 default:
8057                         /* Case prevented by pipe_config_set_bpp. */
8058                         BUG();
8059                 }
8060
8061                 if (intel_crtc->config->dither)
8062                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8063
8064                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8065         }
8066 }
8067
8068 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8069 {
8070         /*
8071          * Account for spread spectrum to avoid
8072          * oversubscribing the link. Max center spread
8073          * is 2.5%; use 5% for safety's sake.
8074          */
8075         u32 bps = target_clock * bpp * 21 / 20;
8076         return DIV_ROUND_UP(bps, link_bw * 8);
8077 }
8078
8079 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8080 {
8081         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8082 }
8083
8084 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8085                                   struct intel_crtc_state *crtc_state,
8086                                   struct dpll *reduced_clock)
8087 {
8088         struct drm_crtc *crtc = &intel_crtc->base;
8089         struct drm_device *dev = crtc->dev;
8090         struct drm_i915_private *dev_priv = to_i915(dev);
8091         u32 dpll, fp, fp2;
8092         int factor;
8093
8094         /* Enable autotuning of the PLL clock (if permissible) */
8095         factor = 21;
8096         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8097                 if ((intel_panel_use_ssc(dev_priv) &&
8098                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8099                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8100                         factor = 25;
8101         } else if (crtc_state->sdvo_tv_clock)
8102                 factor = 20;
8103
8104         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8105
8106         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8107                 fp |= FP_CB_TUNE;
8108
8109         if (reduced_clock) {
8110                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8111
8112                 if (reduced_clock->m < factor * reduced_clock->n)
8113                         fp2 |= FP_CB_TUNE;
8114         } else {
8115                 fp2 = fp;
8116         }
8117
8118         dpll = 0;
8119
8120         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8121                 dpll |= DPLLB_MODE_LVDS;
8122         else
8123                 dpll |= DPLLB_MODE_DAC_SERIAL;
8124
8125         dpll |= (crtc_state->pixel_multiplier - 1)
8126                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8127
8128         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8129             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8130                 dpll |= DPLL_SDVO_HIGH_SPEED;
8131
8132         if (intel_crtc_has_dp_encoder(crtc_state))
8133                 dpll |= DPLL_SDVO_HIGH_SPEED;
8134
8135         /*
8136          * The high speed IO clock is only really required for
8137          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8138          * possible to share the DPLL between CRT and HDMI. Enabling
8139          * the clock needlessly does no real harm, except use up a
8140          * bit of power potentially.
8141          *
8142          * We'll limit this to IVB with 3 pipes, since it has only two
8143          * DPLLs and so DPLL sharing is the only way to get three pipes
8144          * driving PCH ports at the same time. On SNB we could do this,
8145          * and potentially avoid enabling the second DPLL, but it's not
8146          * clear if it''s a win or loss power wise. No point in doing
8147          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8148          */
8149         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8150             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8151                 dpll |= DPLL_SDVO_HIGH_SPEED;
8152
8153         /* compute bitmask from p1 value */
8154         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8155         /* also FPA1 */
8156         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8157
8158         switch (crtc_state->dpll.p2) {
8159         case 5:
8160                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8161                 break;
8162         case 7:
8163                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8164                 break;
8165         case 10:
8166                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8167                 break;
8168         case 14:
8169                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8170                 break;
8171         }
8172
8173         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8174             intel_panel_use_ssc(dev_priv))
8175                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8176         else
8177                 dpll |= PLL_REF_INPUT_DREFCLK;
8178
8179         dpll |= DPLL_VCO_ENABLE;
8180
8181         crtc_state->dpll_hw_state.dpll = dpll;
8182         crtc_state->dpll_hw_state.fp0 = fp;
8183         crtc_state->dpll_hw_state.fp1 = fp2;
8184 }
8185
8186 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8187                                        struct intel_crtc_state *crtc_state)
8188 {
8189         struct drm_device *dev = crtc->base.dev;
8190         struct drm_i915_private *dev_priv = to_i915(dev);
8191         struct dpll reduced_clock;
8192         bool has_reduced_clock = false;
8193         struct intel_shared_dpll *pll;
8194         const struct intel_limit *limit;
8195         int refclk = 120000;
8196
8197         memset(&crtc_state->dpll_hw_state, 0,
8198                sizeof(crtc_state->dpll_hw_state));
8199
8200         crtc->lowfreq_avail = false;
8201
8202         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8203         if (!crtc_state->has_pch_encoder)
8204                 return 0;
8205
8206         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8207                 if (intel_panel_use_ssc(dev_priv)) {
8208                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8209                                       dev_priv->vbt.lvds_ssc_freq);
8210                         refclk = dev_priv->vbt.lvds_ssc_freq;
8211                 }
8212
8213                 if (intel_is_dual_link_lvds(dev)) {
8214                         if (refclk == 100000)
8215                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8216                         else
8217                                 limit = &intel_limits_ironlake_dual_lvds;
8218                 } else {
8219                         if (refclk == 100000)
8220                                 limit = &intel_limits_ironlake_single_lvds_100m;
8221                         else
8222                                 limit = &intel_limits_ironlake_single_lvds;
8223                 }
8224         } else {
8225                 limit = &intel_limits_ironlake_dac;
8226         }
8227
8228         if (!crtc_state->clock_set &&
8229             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8230                                 refclk, NULL, &crtc_state->dpll)) {
8231                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8232                 return -EINVAL;
8233         }
8234
8235         ironlake_compute_dpll(crtc, crtc_state,
8236                               has_reduced_clock ? &reduced_clock : NULL);
8237
8238         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8239         if (pll == NULL) {
8240                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8241                                  pipe_name(crtc->pipe));
8242                 return -EINVAL;
8243         }
8244
8245         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8246             has_reduced_clock)
8247                 crtc->lowfreq_avail = true;
8248
8249         return 0;
8250 }
8251
8252 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8253                                          struct intel_link_m_n *m_n)
8254 {
8255         struct drm_device *dev = crtc->base.dev;
8256         struct drm_i915_private *dev_priv = to_i915(dev);
8257         enum pipe pipe = crtc->pipe;
8258
8259         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8260         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8261         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8262                 & ~TU_SIZE_MASK;
8263         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8264         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8265                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8266 }
8267
8268 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8269                                          enum transcoder transcoder,
8270                                          struct intel_link_m_n *m_n,
8271                                          struct intel_link_m_n *m2_n2)
8272 {
8273         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8274         enum pipe pipe = crtc->pipe;
8275
8276         if (INTEL_GEN(dev_priv) >= 5) {
8277                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8278                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8279                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8280                         & ~TU_SIZE_MASK;
8281                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8282                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8283                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8284                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8285                  * gen < 8) and if DRRS is supported (to make sure the
8286                  * registers are not unnecessarily read).
8287                  */
8288                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8289                         crtc->config->has_drrs) {
8290                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8291                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8292                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8293                                         & ~TU_SIZE_MASK;
8294                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8295                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8296                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8297                 }
8298         } else {
8299                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8300                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8301                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8302                         & ~TU_SIZE_MASK;
8303                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8304                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8305                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8306         }
8307 }
8308
8309 void intel_dp_get_m_n(struct intel_crtc *crtc,
8310                       struct intel_crtc_state *pipe_config)
8311 {
8312         if (pipe_config->has_pch_encoder)
8313                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8314         else
8315                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8316                                              &pipe_config->dp_m_n,
8317                                              &pipe_config->dp_m2_n2);
8318 }
8319
8320 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8321                                         struct intel_crtc_state *pipe_config)
8322 {
8323         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8324                                      &pipe_config->fdi_m_n, NULL);
8325 }
8326
8327 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8328                                     struct intel_crtc_state *pipe_config)
8329 {
8330         struct drm_device *dev = crtc->base.dev;
8331         struct drm_i915_private *dev_priv = to_i915(dev);
8332         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8333         uint32_t ps_ctrl = 0;
8334         int id = -1;
8335         int i;
8336
8337         /* find scaler attached to this pipe */
8338         for (i = 0; i < crtc->num_scalers; i++) {
8339                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8340                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8341                         id = i;
8342                         pipe_config->pch_pfit.enabled = true;
8343                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8344                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8345                         break;
8346                 }
8347         }
8348
8349         scaler_state->scaler_id = id;
8350         if (id >= 0) {
8351                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8352         } else {
8353                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8354         }
8355 }
8356
8357 static void
8358 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8359                                  struct intel_initial_plane_config *plane_config)
8360 {
8361         struct drm_device *dev = crtc->base.dev;
8362         struct drm_i915_private *dev_priv = to_i915(dev);
8363         u32 val, base, offset, stride_mult, tiling;
8364         int pipe = crtc->pipe;
8365         int fourcc, pixel_format;
8366         unsigned int aligned_height;
8367         struct drm_framebuffer *fb;
8368         struct intel_framebuffer *intel_fb;
8369
8370         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8371         if (!intel_fb) {
8372                 DRM_DEBUG_KMS("failed to alloc fb\n");
8373                 return;
8374         }
8375
8376         fb = &intel_fb->base;
8377
8378         fb->dev = dev;
8379
8380         val = I915_READ(PLANE_CTL(pipe, 0));
8381         if (!(val & PLANE_CTL_ENABLE))
8382                 goto error;
8383
8384         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8385         fourcc = skl_format_to_fourcc(pixel_format,
8386                                       val & PLANE_CTL_ORDER_RGBX,
8387                                       val & PLANE_CTL_ALPHA_MASK);
8388         fb->format = drm_format_info(fourcc);
8389
8390         tiling = val & PLANE_CTL_TILED_MASK;
8391         switch (tiling) {
8392         case PLANE_CTL_TILED_LINEAR:
8393                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8394                 break;
8395         case PLANE_CTL_TILED_X:
8396                 plane_config->tiling = I915_TILING_X;
8397                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8398                 break;
8399         case PLANE_CTL_TILED_Y:
8400                 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8401                 break;
8402         case PLANE_CTL_TILED_YF:
8403                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8404                 break;
8405         default:
8406                 MISSING_CASE(tiling);
8407                 goto error;
8408         }
8409
8410         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8411         plane_config->base = base;
8412
8413         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8414
8415         val = I915_READ(PLANE_SIZE(pipe, 0));
8416         fb->height = ((val >> 16) & 0xfff) + 1;
8417         fb->width = ((val >> 0) & 0x1fff) + 1;
8418
8419         val = I915_READ(PLANE_STRIDE(pipe, 0));
8420         stride_mult = intel_fb_stride_alignment(fb, 0);
8421         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8422
8423         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8424
8425         plane_config->size = fb->pitches[0] * aligned_height;
8426
8427         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8428                       pipe_name(pipe), fb->width, fb->height,
8429                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8430                       plane_config->size);
8431
8432         plane_config->fb = intel_fb;
8433         return;
8434
8435 error:
8436         kfree(intel_fb);
8437 }
8438
8439 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8440                                      struct intel_crtc_state *pipe_config)
8441 {
8442         struct drm_device *dev = crtc->base.dev;
8443         struct drm_i915_private *dev_priv = to_i915(dev);
8444         uint32_t tmp;
8445
8446         tmp = I915_READ(PF_CTL(crtc->pipe));
8447
8448         if (tmp & PF_ENABLE) {
8449                 pipe_config->pch_pfit.enabled = true;
8450                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8451                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8452
8453                 /* We currently do not free assignements of panel fitters on
8454                  * ivb/hsw (since we don't use the higher upscaling modes which
8455                  * differentiates them) so just WARN about this case for now. */
8456                 if (IS_GEN7(dev_priv)) {
8457                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8458                                 PF_PIPE_SEL_IVB(crtc->pipe));
8459                 }
8460         }
8461 }
8462
8463 static void
8464 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8465                                   struct intel_initial_plane_config *plane_config)
8466 {
8467         struct drm_device *dev = crtc->base.dev;
8468         struct drm_i915_private *dev_priv = to_i915(dev);
8469         u32 val, base, offset;
8470         int pipe = crtc->pipe;
8471         int fourcc, pixel_format;
8472         unsigned int aligned_height;
8473         struct drm_framebuffer *fb;
8474         struct intel_framebuffer *intel_fb;
8475
8476         val = I915_READ(DSPCNTR(pipe));
8477         if (!(val & DISPLAY_PLANE_ENABLE))
8478                 return;
8479
8480         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8481         if (!intel_fb) {
8482                 DRM_DEBUG_KMS("failed to alloc fb\n");
8483                 return;
8484         }
8485
8486         fb = &intel_fb->base;
8487
8488         fb->dev = dev;
8489
8490         if (INTEL_GEN(dev_priv) >= 4) {
8491                 if (val & DISPPLANE_TILED) {
8492                         plane_config->tiling = I915_TILING_X;
8493                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8494                 }
8495         }
8496
8497         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8498         fourcc = i9xx_format_to_fourcc(pixel_format);
8499         fb->format = drm_format_info(fourcc);
8500
8501         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8502         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8503                 offset = I915_READ(DSPOFFSET(pipe));
8504         } else {
8505                 if (plane_config->tiling)
8506                         offset = I915_READ(DSPTILEOFF(pipe));
8507                 else
8508                         offset = I915_READ(DSPLINOFF(pipe));
8509         }
8510         plane_config->base = base;
8511
8512         val = I915_READ(PIPESRC(pipe));
8513         fb->width = ((val >> 16) & 0xfff) + 1;
8514         fb->height = ((val >> 0) & 0xfff) + 1;
8515
8516         val = I915_READ(DSPSTRIDE(pipe));
8517         fb->pitches[0] = val & 0xffffffc0;
8518
8519         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8520
8521         plane_config->size = fb->pitches[0] * aligned_height;
8522
8523         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8524                       pipe_name(pipe), fb->width, fb->height,
8525                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8526                       plane_config->size);
8527
8528         plane_config->fb = intel_fb;
8529 }
8530
8531 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8532                                      struct intel_crtc_state *pipe_config)
8533 {
8534         struct drm_device *dev = crtc->base.dev;
8535         struct drm_i915_private *dev_priv = to_i915(dev);
8536         enum intel_display_power_domain power_domain;
8537         uint32_t tmp;
8538         bool ret;
8539
8540         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8541         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8542                 return false;
8543
8544         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8545         pipe_config->shared_dpll = NULL;
8546
8547         ret = false;
8548         tmp = I915_READ(PIPECONF(crtc->pipe));
8549         if (!(tmp & PIPECONF_ENABLE))
8550                 goto out;
8551
8552         switch (tmp & PIPECONF_BPC_MASK) {
8553         case PIPECONF_6BPC:
8554                 pipe_config->pipe_bpp = 18;
8555                 break;
8556         case PIPECONF_8BPC:
8557                 pipe_config->pipe_bpp = 24;
8558                 break;
8559         case PIPECONF_10BPC:
8560                 pipe_config->pipe_bpp = 30;
8561                 break;
8562         case PIPECONF_12BPC:
8563                 pipe_config->pipe_bpp = 36;
8564                 break;
8565         default:
8566                 break;
8567         }
8568
8569         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8570                 pipe_config->limited_color_range = true;
8571
8572         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8573                 struct intel_shared_dpll *pll;
8574                 enum intel_dpll_id pll_id;
8575
8576                 pipe_config->has_pch_encoder = true;
8577
8578                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8579                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8580                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8581
8582                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8583
8584                 if (HAS_PCH_IBX(dev_priv)) {
8585                         /*
8586                          * The pipe->pch transcoder and pch transcoder->pll
8587                          * mapping is fixed.
8588                          */
8589                         pll_id = (enum intel_dpll_id) crtc->pipe;
8590                 } else {
8591                         tmp = I915_READ(PCH_DPLL_SEL);
8592                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8593                                 pll_id = DPLL_ID_PCH_PLL_B;
8594                         else
8595                                 pll_id= DPLL_ID_PCH_PLL_A;
8596                 }
8597
8598                 pipe_config->shared_dpll =
8599                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8600                 pll = pipe_config->shared_dpll;
8601
8602                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8603                                                  &pipe_config->dpll_hw_state));
8604
8605                 tmp = pipe_config->dpll_hw_state.dpll;
8606                 pipe_config->pixel_multiplier =
8607                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8608                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8609
8610                 ironlake_pch_clock_get(crtc, pipe_config);
8611         } else {
8612                 pipe_config->pixel_multiplier = 1;
8613         }
8614
8615         intel_get_pipe_timings(crtc, pipe_config);
8616         intel_get_pipe_src_size(crtc, pipe_config);
8617
8618         ironlake_get_pfit_config(crtc, pipe_config);
8619
8620         ret = true;
8621
8622 out:
8623         intel_display_power_put(dev_priv, power_domain);
8624
8625         return ret;
8626 }
8627
8628 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8629 {
8630         struct drm_device *dev = &dev_priv->drm;
8631         struct intel_crtc *crtc;
8632
8633         for_each_intel_crtc(dev, crtc)
8634                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8635                      pipe_name(crtc->pipe));
8636
8637         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8638         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8639         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8640         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8641         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8642         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8643              "CPU PWM1 enabled\n");
8644         if (IS_HASWELL(dev_priv))
8645                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8646                      "CPU PWM2 enabled\n");
8647         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8648              "PCH PWM1 enabled\n");
8649         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8650              "Utility pin enabled\n");
8651         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8652
8653         /*
8654          * In theory we can still leave IRQs enabled, as long as only the HPD
8655          * interrupts remain enabled. We used to check for that, but since it's
8656          * gen-specific and since we only disable LCPLL after we fully disable
8657          * the interrupts, the check below should be enough.
8658          */
8659         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8660 }
8661
8662 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8663 {
8664         if (IS_HASWELL(dev_priv))
8665                 return I915_READ(D_COMP_HSW);
8666         else
8667                 return I915_READ(D_COMP_BDW);
8668 }
8669
8670 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8671 {
8672         if (IS_HASWELL(dev_priv)) {
8673                 mutex_lock(&dev_priv->rps.hw_lock);
8674                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8675                                             val))
8676                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8677                 mutex_unlock(&dev_priv->rps.hw_lock);
8678         } else {
8679                 I915_WRITE(D_COMP_BDW, val);
8680                 POSTING_READ(D_COMP_BDW);
8681         }
8682 }
8683
8684 /*
8685  * This function implements pieces of two sequences from BSpec:
8686  * - Sequence for display software to disable LCPLL
8687  * - Sequence for display software to allow package C8+
8688  * The steps implemented here are just the steps that actually touch the LCPLL
8689  * register. Callers should take care of disabling all the display engine
8690  * functions, doing the mode unset, fixing interrupts, etc.
8691  */
8692 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8693                               bool switch_to_fclk, bool allow_power_down)
8694 {
8695         uint32_t val;
8696
8697         assert_can_disable_lcpll(dev_priv);
8698
8699         val = I915_READ(LCPLL_CTL);
8700
8701         if (switch_to_fclk) {
8702                 val |= LCPLL_CD_SOURCE_FCLK;
8703                 I915_WRITE(LCPLL_CTL, val);
8704
8705                 if (wait_for_us(I915_READ(LCPLL_CTL) &
8706                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8707                         DRM_ERROR("Switching to FCLK failed\n");
8708
8709                 val = I915_READ(LCPLL_CTL);
8710         }
8711
8712         val |= LCPLL_PLL_DISABLE;
8713         I915_WRITE(LCPLL_CTL, val);
8714         POSTING_READ(LCPLL_CTL);
8715
8716         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8717                 DRM_ERROR("LCPLL still locked\n");
8718
8719         val = hsw_read_dcomp(dev_priv);
8720         val |= D_COMP_COMP_DISABLE;
8721         hsw_write_dcomp(dev_priv, val);
8722         ndelay(100);
8723
8724         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8725                      1))
8726                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8727
8728         if (allow_power_down) {
8729                 val = I915_READ(LCPLL_CTL);
8730                 val |= LCPLL_POWER_DOWN_ALLOW;
8731                 I915_WRITE(LCPLL_CTL, val);
8732                 POSTING_READ(LCPLL_CTL);
8733         }
8734 }
8735
8736 /*
8737  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8738  * source.
8739  */
8740 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8741 {
8742         uint32_t val;
8743
8744         val = I915_READ(LCPLL_CTL);
8745
8746         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8747                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8748                 return;
8749
8750         /*
8751          * Make sure we're not on PC8 state before disabling PC8, otherwise
8752          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8753          */
8754         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8755
8756         if (val & LCPLL_POWER_DOWN_ALLOW) {
8757                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8758                 I915_WRITE(LCPLL_CTL, val);
8759                 POSTING_READ(LCPLL_CTL);
8760         }
8761
8762         val = hsw_read_dcomp(dev_priv);
8763         val |= D_COMP_COMP_FORCE;
8764         val &= ~D_COMP_COMP_DISABLE;
8765         hsw_write_dcomp(dev_priv, val);
8766
8767         val = I915_READ(LCPLL_CTL);
8768         val &= ~LCPLL_PLL_DISABLE;
8769         I915_WRITE(LCPLL_CTL, val);
8770
8771         if (intel_wait_for_register(dev_priv,
8772                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8773                                     5))
8774                 DRM_ERROR("LCPLL not locked yet\n");
8775
8776         if (val & LCPLL_CD_SOURCE_FCLK) {
8777                 val = I915_READ(LCPLL_CTL);
8778                 val &= ~LCPLL_CD_SOURCE_FCLK;
8779                 I915_WRITE(LCPLL_CTL, val);
8780
8781                 if (wait_for_us((I915_READ(LCPLL_CTL) &
8782                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8783                         DRM_ERROR("Switching back to LCPLL failed\n");
8784         }
8785
8786         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8787         intel_update_cdclk(dev_priv);
8788 }
8789
8790 /*
8791  * Package states C8 and deeper are really deep PC states that can only be
8792  * reached when all the devices on the system allow it, so even if the graphics
8793  * device allows PC8+, it doesn't mean the system will actually get to these
8794  * states. Our driver only allows PC8+ when going into runtime PM.
8795  *
8796  * The requirements for PC8+ are that all the outputs are disabled, the power
8797  * well is disabled and most interrupts are disabled, and these are also
8798  * requirements for runtime PM. When these conditions are met, we manually do
8799  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8800  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8801  * hang the machine.
8802  *
8803  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8804  * the state of some registers, so when we come back from PC8+ we need to
8805  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8806  * need to take care of the registers kept by RC6. Notice that this happens even
8807  * if we don't put the device in PCI D3 state (which is what currently happens
8808  * because of the runtime PM support).
8809  *
8810  * For more, read "Display Sequences for Package C8" on the hardware
8811  * documentation.
8812  */
8813 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8814 {
8815         uint32_t val;
8816
8817         DRM_DEBUG_KMS("Enabling package C8+\n");
8818
8819         if (HAS_PCH_LPT_LP(dev_priv)) {
8820                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8821                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8822                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8823         }
8824
8825         lpt_disable_clkout_dp(dev_priv);
8826         hsw_disable_lcpll(dev_priv, true, true);
8827 }
8828
8829 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8830 {
8831         uint32_t val;
8832
8833         DRM_DEBUG_KMS("Disabling package C8+\n");
8834
8835         hsw_restore_lcpll(dev_priv);
8836         lpt_init_pch_refclk(dev_priv);
8837
8838         if (HAS_PCH_LPT_LP(dev_priv)) {
8839                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8840                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8841                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8842         }
8843 }
8844
8845 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8846                                       struct intel_crtc_state *crtc_state)
8847 {
8848         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8849                 struct intel_encoder *encoder =
8850                         intel_ddi_get_crtc_new_encoder(crtc_state);
8851
8852                 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8853                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8854                                          pipe_name(crtc->pipe));
8855                         return -EINVAL;
8856                 }
8857         }
8858
8859         crtc->lowfreq_avail = false;
8860
8861         return 0;
8862 }
8863
8864 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8865                                 enum port port,
8866                                 struct intel_crtc_state *pipe_config)
8867 {
8868         enum intel_dpll_id id;
8869
8870         switch (port) {
8871         case PORT_A:
8872                 id = DPLL_ID_SKL_DPLL0;
8873                 break;
8874         case PORT_B:
8875                 id = DPLL_ID_SKL_DPLL1;
8876                 break;
8877         case PORT_C:
8878                 id = DPLL_ID_SKL_DPLL2;
8879                 break;
8880         default:
8881                 DRM_ERROR("Incorrect port type\n");
8882                 return;
8883         }
8884
8885         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8886 }
8887
8888 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8889                                 enum port port,
8890                                 struct intel_crtc_state *pipe_config)
8891 {
8892         enum intel_dpll_id id;
8893         u32 temp;
8894
8895         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8896         id = temp >> (port * 3 + 1);
8897
8898         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8899                 return;
8900
8901         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8902 }
8903
8904 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8905                                 enum port port,
8906                                 struct intel_crtc_state *pipe_config)
8907 {
8908         enum intel_dpll_id id;
8909         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8910
8911         switch (ddi_pll_sel) {
8912         case PORT_CLK_SEL_WRPLL1:
8913                 id = DPLL_ID_WRPLL1;
8914                 break;
8915         case PORT_CLK_SEL_WRPLL2:
8916                 id = DPLL_ID_WRPLL2;
8917                 break;
8918         case PORT_CLK_SEL_SPLL:
8919                 id = DPLL_ID_SPLL;
8920                 break;
8921         case PORT_CLK_SEL_LCPLL_810:
8922                 id = DPLL_ID_LCPLL_810;
8923                 break;
8924         case PORT_CLK_SEL_LCPLL_1350:
8925                 id = DPLL_ID_LCPLL_1350;
8926                 break;
8927         case PORT_CLK_SEL_LCPLL_2700:
8928                 id = DPLL_ID_LCPLL_2700;
8929                 break;
8930         default:
8931                 MISSING_CASE(ddi_pll_sel);
8932                 /* fall through */
8933         case PORT_CLK_SEL_NONE:
8934                 return;
8935         }
8936
8937         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8938 }
8939
8940 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8941                                      struct intel_crtc_state *pipe_config,
8942                                      u64 *power_domain_mask)
8943 {
8944         struct drm_device *dev = crtc->base.dev;
8945         struct drm_i915_private *dev_priv = to_i915(dev);
8946         enum intel_display_power_domain power_domain;
8947         u32 tmp;
8948
8949         /*
8950          * The pipe->transcoder mapping is fixed with the exception of the eDP
8951          * transcoder handled below.
8952          */
8953         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8954
8955         /*
8956          * XXX: Do intel_display_power_get_if_enabled before reading this (for
8957          * consistency and less surprising code; it's in always on power).
8958          */
8959         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8960         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8961                 enum pipe trans_edp_pipe;
8962                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8963                 default:
8964                         WARN(1, "unknown pipe linked to edp transcoder\n");
8965                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8966                 case TRANS_DDI_EDP_INPUT_A_ON:
8967                         trans_edp_pipe = PIPE_A;
8968                         break;
8969                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8970                         trans_edp_pipe = PIPE_B;
8971                         break;
8972                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8973                         trans_edp_pipe = PIPE_C;
8974                         break;
8975                 }
8976
8977                 if (trans_edp_pipe == crtc->pipe)
8978                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8979         }
8980
8981         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
8982         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8983                 return false;
8984         *power_domain_mask |= BIT_ULL(power_domain);
8985
8986         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8987
8988         return tmp & PIPECONF_ENABLE;
8989 }
8990
8991 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
8992                                          struct intel_crtc_state *pipe_config,
8993                                          u64 *power_domain_mask)
8994 {
8995         struct drm_device *dev = crtc->base.dev;
8996         struct drm_i915_private *dev_priv = to_i915(dev);
8997         enum intel_display_power_domain power_domain;
8998         enum port port;
8999         enum transcoder cpu_transcoder;
9000         u32 tmp;
9001
9002         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9003                 if (port == PORT_A)
9004                         cpu_transcoder = TRANSCODER_DSI_A;
9005                 else
9006                         cpu_transcoder = TRANSCODER_DSI_C;
9007
9008                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9009                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9010                         continue;
9011                 *power_domain_mask |= BIT_ULL(power_domain);
9012
9013                 /*
9014                  * The PLL needs to be enabled with a valid divider
9015                  * configuration, otherwise accessing DSI registers will hang
9016                  * the machine. See BSpec North Display Engine
9017                  * registers/MIPI[BXT]. We can break out here early, since we
9018                  * need the same DSI PLL to be enabled for both DSI ports.
9019                  */
9020                 if (!intel_dsi_pll_is_enabled(dev_priv))
9021                         break;
9022
9023                 /* XXX: this works for video mode only */
9024                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9025                 if (!(tmp & DPI_ENABLE))
9026                         continue;
9027
9028                 tmp = I915_READ(MIPI_CTRL(port));
9029                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9030                         continue;
9031
9032                 pipe_config->cpu_transcoder = cpu_transcoder;
9033                 break;
9034         }
9035
9036         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9037 }
9038
9039 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9040                                        struct intel_crtc_state *pipe_config)
9041 {
9042         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9043         struct intel_shared_dpll *pll;
9044         enum port port;
9045         uint32_t tmp;
9046
9047         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9048
9049         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9050
9051         if (IS_GEN9_BC(dev_priv))
9052                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9053         else if (IS_GEN9_LP(dev_priv))
9054                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9055         else
9056                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9057
9058         pll = pipe_config->shared_dpll;
9059         if (pll) {
9060                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9061                                                  &pipe_config->dpll_hw_state));
9062         }
9063
9064         /*
9065          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9066          * DDI E. So just check whether this pipe is wired to DDI E and whether
9067          * the PCH transcoder is on.
9068          */
9069         if (INTEL_GEN(dev_priv) < 9 &&
9070             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9071                 pipe_config->has_pch_encoder = true;
9072
9073                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9074                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9075                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9076
9077                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9078         }
9079 }
9080
9081 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9082                                     struct intel_crtc_state *pipe_config)
9083 {
9084         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9085         enum intel_display_power_domain power_domain;
9086         u64 power_domain_mask;
9087         bool active;
9088
9089         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9090         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9091                 return false;
9092         power_domain_mask = BIT_ULL(power_domain);
9093
9094         pipe_config->shared_dpll = NULL;
9095
9096         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9097
9098         if (IS_GEN9_LP(dev_priv) &&
9099             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9100                 WARN_ON(active);
9101                 active = true;
9102         }
9103
9104         if (!active)
9105                 goto out;
9106
9107         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9108                 haswell_get_ddi_port_state(crtc, pipe_config);
9109                 intel_get_pipe_timings(crtc, pipe_config);
9110         }
9111
9112         intel_get_pipe_src_size(crtc, pipe_config);
9113
9114         pipe_config->gamma_mode =
9115                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9116
9117         if (INTEL_GEN(dev_priv) >= 9) {
9118                 intel_crtc_init_scalers(crtc, pipe_config);
9119
9120                 pipe_config->scaler_state.scaler_id = -1;
9121                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9122         }
9123
9124         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9125         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9126                 power_domain_mask |= BIT_ULL(power_domain);
9127                 if (INTEL_GEN(dev_priv) >= 9)
9128                         skylake_get_pfit_config(crtc, pipe_config);
9129                 else
9130                         ironlake_get_pfit_config(crtc, pipe_config);
9131         }
9132
9133         if (IS_HASWELL(dev_priv))
9134                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9135                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9136
9137         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9138             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9139                 pipe_config->pixel_multiplier =
9140                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9141         } else {
9142                 pipe_config->pixel_multiplier = 1;
9143         }
9144
9145 out:
9146         for_each_power_domain(power_domain, power_domain_mask)
9147                 intel_display_power_put(dev_priv, power_domain);
9148
9149         return active;
9150 }
9151
9152 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9153                            const struct intel_plane_state *plane_state)
9154 {
9155         unsigned int width = plane_state->base.crtc_w;
9156         unsigned int stride = roundup_pow_of_two(width) * 4;
9157
9158         switch (stride) {
9159         default:
9160                 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9161                           width, stride);
9162                 stride = 256;
9163                 /* fallthrough */
9164         case 256:
9165         case 512:
9166         case 1024:
9167         case 2048:
9168                 break;
9169         }
9170
9171         return CURSOR_ENABLE |
9172                 CURSOR_GAMMA_ENABLE |
9173                 CURSOR_FORMAT_ARGB |
9174                 CURSOR_STRIDE(stride);
9175 }
9176
9177 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
9178                                const struct intel_plane_state *plane_state)
9179 {
9180         struct drm_device *dev = crtc->dev;
9181         struct drm_i915_private *dev_priv = to_i915(dev);
9182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9183         uint32_t cntl = 0, size = 0;
9184
9185         if (plane_state && plane_state->base.visible) {
9186                 unsigned int width = plane_state->base.crtc_w;
9187                 unsigned int height = plane_state->base.crtc_h;
9188
9189                 cntl = plane_state->ctl;
9190                 size = (height << 12) | width;
9191         }
9192
9193         if (intel_crtc->cursor_cntl != 0 &&
9194             (intel_crtc->cursor_base != base ||
9195              intel_crtc->cursor_size != size ||
9196              intel_crtc->cursor_cntl != cntl)) {
9197                 /* On these chipsets we can only modify the base/size/stride
9198                  * whilst the cursor is disabled.
9199                  */
9200                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9201                 POSTING_READ_FW(CURCNTR(PIPE_A));
9202                 intel_crtc->cursor_cntl = 0;
9203         }
9204
9205         if (intel_crtc->cursor_base != base) {
9206                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9207                 intel_crtc->cursor_base = base;
9208         }
9209
9210         if (intel_crtc->cursor_size != size) {
9211                 I915_WRITE_FW(CURSIZE, size);
9212                 intel_crtc->cursor_size = size;
9213         }
9214
9215         if (intel_crtc->cursor_cntl != cntl) {
9216                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9217                 POSTING_READ_FW(CURCNTR(PIPE_A));
9218                 intel_crtc->cursor_cntl = cntl;
9219         }
9220 }
9221
9222 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9223                            const struct intel_plane_state *plane_state)
9224 {
9225         struct drm_i915_private *dev_priv =
9226                 to_i915(plane_state->base.plane->dev);
9227         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9228         enum pipe pipe = crtc->pipe;
9229         u32 cntl;
9230
9231         cntl = MCURSOR_GAMMA_ENABLE;
9232
9233         if (HAS_DDI(dev_priv))
9234                 cntl |= CURSOR_PIPE_CSC_ENABLE;
9235
9236         cntl |= pipe << 28; /* Connect to correct pipe */
9237
9238         switch (plane_state->base.crtc_w) {
9239         case 64:
9240                 cntl |= CURSOR_MODE_64_ARGB_AX;
9241                 break;
9242         case 128:
9243                 cntl |= CURSOR_MODE_128_ARGB_AX;
9244                 break;
9245         case 256:
9246                 cntl |= CURSOR_MODE_256_ARGB_AX;
9247                 break;
9248         default:
9249                 MISSING_CASE(plane_state->base.crtc_w);
9250                 return 0;
9251         }
9252
9253         if (plane_state->base.rotation & DRM_ROTATE_180)
9254                 cntl |= CURSOR_ROTATE_180;
9255
9256         return cntl;
9257 }
9258
9259 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
9260                                const struct intel_plane_state *plane_state)
9261 {
9262         struct drm_device *dev = crtc->dev;
9263         struct drm_i915_private *dev_priv = to_i915(dev);
9264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9265         int pipe = intel_crtc->pipe;
9266         uint32_t cntl = 0;
9267
9268         if (plane_state && plane_state->base.visible)
9269                 cntl = plane_state->ctl;
9270
9271         if (intel_crtc->cursor_cntl != cntl) {
9272                 I915_WRITE_FW(CURCNTR(pipe), cntl);
9273                 POSTING_READ_FW(CURCNTR(pipe));
9274                 intel_crtc->cursor_cntl = cntl;
9275         }
9276
9277         /* and commit changes on next vblank */
9278         I915_WRITE_FW(CURBASE(pipe), base);
9279         POSTING_READ_FW(CURBASE(pipe));
9280
9281         intel_crtc->cursor_base = base;
9282 }
9283
9284 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9285 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9286                                      const struct intel_plane_state *plane_state)
9287 {
9288         struct drm_device *dev = crtc->dev;
9289         struct drm_i915_private *dev_priv = to_i915(dev);
9290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9291         int pipe = intel_crtc->pipe;
9292         u32 base = intel_crtc->cursor_addr;
9293         unsigned long irqflags;
9294         u32 pos = 0;
9295
9296         if (plane_state) {
9297                 int x = plane_state->base.crtc_x;
9298                 int y = plane_state->base.crtc_y;
9299
9300                 if (x < 0) {
9301                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9302                         x = -x;
9303                 }
9304                 pos |= x << CURSOR_X_SHIFT;
9305
9306                 if (y < 0) {
9307                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9308                         y = -y;
9309                 }
9310                 pos |= y << CURSOR_Y_SHIFT;
9311
9312                 /* ILK+ do this automagically */
9313                 if (HAS_GMCH_DISPLAY(dev_priv) &&
9314                     plane_state->base.rotation & DRM_ROTATE_180) {
9315                         base += (plane_state->base.crtc_h *
9316                                  plane_state->base.crtc_w - 1) * 4;
9317                 }
9318         }
9319
9320         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9321
9322         I915_WRITE_FW(CURPOS(pipe), pos);
9323
9324         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
9325                 i845_update_cursor(crtc, base, plane_state);
9326         else
9327                 i9xx_update_cursor(crtc, base, plane_state);
9328
9329         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9330 }
9331
9332 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
9333                            uint32_t width, uint32_t height)
9334 {
9335         if (width == 0 || height == 0)
9336                 return false;
9337
9338         /*
9339          * 845g/865g are special in that they are only limited by
9340          * the width of their cursors, the height is arbitrary up to
9341          * the precision of the register. Everything else requires
9342          * square cursors, limited to a few power-of-two sizes.
9343          */
9344         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
9345                 if ((width & 63) != 0)
9346                         return false;
9347
9348                 if (width > (IS_I845G(dev_priv) ? 64 : 512))
9349                         return false;
9350
9351                 if (height > 1023)
9352                         return false;
9353         } else {
9354                 switch (width | height) {
9355                 case 256:
9356                 case 128:
9357                         if (IS_GEN2(dev_priv))
9358                                 return false;
9359                 case 64:
9360                         break;
9361                 default:
9362                         return false;
9363                 }
9364         }
9365
9366         return true;
9367 }
9368
9369 /* VESA 640x480x72Hz mode to set on the pipe */
9370 static struct drm_display_mode load_detect_mode = {
9371         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9372                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9373 };
9374
9375 struct drm_framebuffer *
9376 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9377                          struct drm_mode_fb_cmd2 *mode_cmd)
9378 {
9379         struct intel_framebuffer *intel_fb;
9380         int ret;
9381
9382         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9383         if (!intel_fb)
9384                 return ERR_PTR(-ENOMEM);
9385
9386         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9387         if (ret)
9388                 goto err;
9389
9390         return &intel_fb->base;
9391
9392 err:
9393         kfree(intel_fb);
9394         return ERR_PTR(ret);
9395 }
9396
9397 static u32
9398 intel_framebuffer_pitch_for_width(int width, int bpp)
9399 {
9400         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9401         return ALIGN(pitch, 64);
9402 }
9403
9404 static u32
9405 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9406 {
9407         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9408         return PAGE_ALIGN(pitch * mode->vdisplay);
9409 }
9410
9411 static struct drm_framebuffer *
9412 intel_framebuffer_create_for_mode(struct drm_device *dev,
9413                                   struct drm_display_mode *mode,
9414                                   int depth, int bpp)
9415 {
9416         struct drm_framebuffer *fb;
9417         struct drm_i915_gem_object *obj;
9418         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9419
9420         obj = i915_gem_object_create(to_i915(dev),
9421                                     intel_framebuffer_size_for_mode(mode, bpp));
9422         if (IS_ERR(obj))
9423                 return ERR_CAST(obj);
9424
9425         mode_cmd.width = mode->hdisplay;
9426         mode_cmd.height = mode->vdisplay;
9427         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9428                                                                 bpp);
9429         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9430
9431         fb = intel_framebuffer_create(obj, &mode_cmd);
9432         if (IS_ERR(fb))
9433                 i915_gem_object_put(obj);
9434
9435         return fb;
9436 }
9437
9438 static struct drm_framebuffer *
9439 mode_fits_in_fbdev(struct drm_device *dev,
9440                    struct drm_display_mode *mode)
9441 {
9442 #ifdef CONFIG_DRM_FBDEV_EMULATION
9443         struct drm_i915_private *dev_priv = to_i915(dev);
9444         struct drm_i915_gem_object *obj;
9445         struct drm_framebuffer *fb;
9446
9447         if (!dev_priv->fbdev)
9448                 return NULL;
9449
9450         if (!dev_priv->fbdev->fb)
9451                 return NULL;
9452
9453         obj = dev_priv->fbdev->fb->obj;
9454         BUG_ON(!obj);
9455
9456         fb = &dev_priv->fbdev->fb->base;
9457         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9458                                                                fb->format->cpp[0] * 8))
9459                 return NULL;
9460
9461         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9462                 return NULL;
9463
9464         drm_framebuffer_reference(fb);
9465         return fb;
9466 #else
9467         return NULL;
9468 #endif
9469 }
9470
9471 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9472                                            struct drm_crtc *crtc,
9473                                            struct drm_display_mode *mode,
9474                                            struct drm_framebuffer *fb,
9475                                            int x, int y)
9476 {
9477         struct drm_plane_state *plane_state;
9478         int hdisplay, vdisplay;
9479         int ret;
9480
9481         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9482         if (IS_ERR(plane_state))
9483                 return PTR_ERR(plane_state);
9484
9485         if (mode)
9486                 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9487         else
9488                 hdisplay = vdisplay = 0;
9489
9490         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9491         if (ret)
9492                 return ret;
9493         drm_atomic_set_fb_for_plane(plane_state, fb);
9494         plane_state->crtc_x = 0;
9495         plane_state->crtc_y = 0;
9496         plane_state->crtc_w = hdisplay;
9497         plane_state->crtc_h = vdisplay;
9498         plane_state->src_x = x << 16;
9499         plane_state->src_y = y << 16;
9500         plane_state->src_w = hdisplay << 16;
9501         plane_state->src_h = vdisplay << 16;
9502
9503         return 0;
9504 }
9505
9506 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9507                                 struct drm_display_mode *mode,
9508                                 struct intel_load_detect_pipe *old,
9509                                 struct drm_modeset_acquire_ctx *ctx)
9510 {
9511         struct intel_crtc *intel_crtc;
9512         struct intel_encoder *intel_encoder =
9513                 intel_attached_encoder(connector);
9514         struct drm_crtc *possible_crtc;
9515         struct drm_encoder *encoder = &intel_encoder->base;
9516         struct drm_crtc *crtc = NULL;
9517         struct drm_device *dev = encoder->dev;
9518         struct drm_i915_private *dev_priv = to_i915(dev);
9519         struct drm_framebuffer *fb;
9520         struct drm_mode_config *config = &dev->mode_config;
9521         struct drm_atomic_state *state = NULL, *restore_state = NULL;
9522         struct drm_connector_state *connector_state;
9523         struct intel_crtc_state *crtc_state;
9524         int ret, i = -1;
9525
9526         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9527                       connector->base.id, connector->name,
9528                       encoder->base.id, encoder->name);
9529
9530         old->restore_state = NULL;
9531
9532 retry:
9533         ret = drm_modeset_lock(&config->connection_mutex, ctx);
9534         if (ret)
9535                 goto fail;
9536
9537         /*
9538          * Algorithm gets a little messy:
9539          *
9540          *   - if the connector already has an assigned crtc, use it (but make
9541          *     sure it's on first)
9542          *
9543          *   - try to find the first unused crtc that can drive this connector,
9544          *     and use that if we find one
9545          */
9546
9547         /* See if we already have a CRTC for this connector */
9548         if (connector->state->crtc) {
9549                 crtc = connector->state->crtc;
9550
9551                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9552                 if (ret)
9553                         goto fail;
9554
9555                 /* Make sure the crtc and connector are running */
9556                 goto found;
9557         }
9558
9559         /* Find an unused one (if possible) */
9560         for_each_crtc(dev, possible_crtc) {
9561                 i++;
9562                 if (!(encoder->possible_crtcs & (1 << i)))
9563                         continue;
9564
9565                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9566                 if (ret)
9567                         goto fail;
9568
9569                 if (possible_crtc->state->enable) {
9570                         drm_modeset_unlock(&possible_crtc->mutex);
9571                         continue;
9572                 }
9573
9574                 crtc = possible_crtc;
9575                 break;
9576         }
9577
9578         /*
9579          * If we didn't find an unused CRTC, don't use any.
9580          */
9581         if (!crtc) {
9582                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9583                 goto fail;
9584         }
9585
9586 found:
9587         intel_crtc = to_intel_crtc(crtc);
9588
9589         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9590         if (ret)
9591                 goto fail;
9592
9593         state = drm_atomic_state_alloc(dev);
9594         restore_state = drm_atomic_state_alloc(dev);
9595         if (!state || !restore_state) {
9596                 ret = -ENOMEM;
9597                 goto fail;
9598         }
9599
9600         state->acquire_ctx = ctx;
9601         restore_state->acquire_ctx = ctx;
9602
9603         connector_state = drm_atomic_get_connector_state(state, connector);
9604         if (IS_ERR(connector_state)) {
9605                 ret = PTR_ERR(connector_state);
9606                 goto fail;
9607         }
9608
9609         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9610         if (ret)
9611                 goto fail;
9612
9613         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9614         if (IS_ERR(crtc_state)) {
9615                 ret = PTR_ERR(crtc_state);
9616                 goto fail;
9617         }
9618
9619         crtc_state->base.active = crtc_state->base.enable = true;
9620
9621         if (!mode)
9622                 mode = &load_detect_mode;
9623
9624         /* We need a framebuffer large enough to accommodate all accesses
9625          * that the plane may generate whilst we perform load detection.
9626          * We can not rely on the fbcon either being present (we get called
9627          * during its initialisation to detect all boot displays, or it may
9628          * not even exist) or that it is large enough to satisfy the
9629          * requested mode.
9630          */
9631         fb = mode_fits_in_fbdev(dev, mode);
9632         if (fb == NULL) {
9633                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9634                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9635         } else
9636                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9637         if (IS_ERR(fb)) {
9638                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9639                 goto fail;
9640         }
9641
9642         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9643         if (ret)
9644                 goto fail;
9645
9646         drm_framebuffer_unreference(fb);
9647
9648         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9649         if (ret)
9650                 goto fail;
9651
9652         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9653         if (!ret)
9654                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9655         if (!ret)
9656                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9657         if (ret) {
9658                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9659                 goto fail;
9660         }
9661
9662         ret = drm_atomic_commit(state);
9663         if (ret) {
9664                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9665                 goto fail;
9666         }
9667
9668         old->restore_state = restore_state;
9669         drm_atomic_state_put(state);
9670
9671         /* let the connector get through one full cycle before testing */
9672         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9673         return true;
9674
9675 fail:
9676         if (state) {
9677                 drm_atomic_state_put(state);
9678                 state = NULL;
9679         }
9680         if (restore_state) {
9681                 drm_atomic_state_put(restore_state);
9682                 restore_state = NULL;
9683         }
9684
9685         if (ret == -EDEADLK) {
9686                 drm_modeset_backoff(ctx);
9687                 goto retry;
9688         }
9689
9690         return false;
9691 }
9692
9693 void intel_release_load_detect_pipe(struct drm_connector *connector,
9694                                     struct intel_load_detect_pipe *old,
9695                                     struct drm_modeset_acquire_ctx *ctx)
9696 {
9697         struct intel_encoder *intel_encoder =
9698                 intel_attached_encoder(connector);
9699         struct drm_encoder *encoder = &intel_encoder->base;
9700         struct drm_atomic_state *state = old->restore_state;
9701         int ret;
9702
9703         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9704                       connector->base.id, connector->name,
9705                       encoder->base.id, encoder->name);
9706
9707         if (!state)
9708                 return;
9709
9710         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9711         if (ret)
9712                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9713         drm_atomic_state_put(state);
9714 }
9715
9716 static int i9xx_pll_refclk(struct drm_device *dev,
9717                            const struct intel_crtc_state *pipe_config)
9718 {
9719         struct drm_i915_private *dev_priv = to_i915(dev);
9720         u32 dpll = pipe_config->dpll_hw_state.dpll;
9721
9722         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9723                 return dev_priv->vbt.lvds_ssc_freq;
9724         else if (HAS_PCH_SPLIT(dev_priv))
9725                 return 120000;
9726         else if (!IS_GEN2(dev_priv))
9727                 return 96000;
9728         else
9729                 return 48000;
9730 }
9731
9732 /* Returns the clock of the currently programmed mode of the given pipe. */
9733 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9734                                 struct intel_crtc_state *pipe_config)
9735 {
9736         struct drm_device *dev = crtc->base.dev;
9737         struct drm_i915_private *dev_priv = to_i915(dev);
9738         int pipe = pipe_config->cpu_transcoder;
9739         u32 dpll = pipe_config->dpll_hw_state.dpll;
9740         u32 fp;
9741         struct dpll clock;
9742         int port_clock;
9743         int refclk = i9xx_pll_refclk(dev, pipe_config);
9744
9745         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9746                 fp = pipe_config->dpll_hw_state.fp0;
9747         else
9748                 fp = pipe_config->dpll_hw_state.fp1;
9749
9750         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9751         if (IS_PINEVIEW(dev_priv)) {
9752                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9753                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9754         } else {
9755                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9756                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9757         }
9758
9759         if (!IS_GEN2(dev_priv)) {
9760                 if (IS_PINEVIEW(dev_priv))
9761                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9762                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9763                 else
9764                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9765                                DPLL_FPA01_P1_POST_DIV_SHIFT);
9766
9767                 switch (dpll & DPLL_MODE_MASK) {
9768                 case DPLLB_MODE_DAC_SERIAL:
9769                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9770                                 5 : 10;
9771                         break;
9772                 case DPLLB_MODE_LVDS:
9773                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9774                                 7 : 14;
9775                         break;
9776                 default:
9777                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9778                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
9779                         return;
9780                 }
9781
9782                 if (IS_PINEVIEW(dev_priv))
9783                         port_clock = pnv_calc_dpll_params(refclk, &clock);
9784                 else
9785                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
9786         } else {
9787                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9788                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9789
9790                 if (is_lvds) {
9791                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9792                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
9793
9794                         if (lvds & LVDS_CLKB_POWER_UP)
9795                                 clock.p2 = 7;
9796                         else
9797                                 clock.p2 = 14;
9798                 } else {
9799                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
9800                                 clock.p1 = 2;
9801                         else {
9802                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9803                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9804                         }
9805                         if (dpll & PLL_P2_DIVIDE_BY_4)
9806                                 clock.p2 = 4;
9807                         else
9808                                 clock.p2 = 2;
9809                 }
9810
9811                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9812         }
9813
9814         /*
9815          * This value includes pixel_multiplier. We will use
9816          * port_clock to compute adjusted_mode.crtc_clock in the
9817          * encoder's get_config() function.
9818          */
9819         pipe_config->port_clock = port_clock;
9820 }
9821
9822 int intel_dotclock_calculate(int link_freq,
9823                              const struct intel_link_m_n *m_n)
9824 {
9825         /*
9826          * The calculation for the data clock is:
9827          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9828          * But we want to avoid losing precison if possible, so:
9829          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9830          *
9831          * and the link clock is simpler:
9832          * link_clock = (m * link_clock) / n
9833          */
9834
9835         if (!m_n->link_n)
9836                 return 0;
9837
9838         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9839 }
9840
9841 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9842                                    struct intel_crtc_state *pipe_config)
9843 {
9844         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9845
9846         /* read out port_clock from the DPLL */
9847         i9xx_crtc_clock_get(crtc, pipe_config);
9848
9849         /*
9850          * In case there is an active pipe without active ports,
9851          * we may need some idea for the dotclock anyway.
9852          * Calculate one based on the FDI configuration.
9853          */
9854         pipe_config->base.adjusted_mode.crtc_clock =
9855                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
9856                                          &pipe_config->fdi_m_n);
9857 }
9858
9859 /** Returns the currently programmed mode of the given pipe. */
9860 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9861                                              struct drm_crtc *crtc)
9862 {
9863         struct drm_i915_private *dev_priv = to_i915(dev);
9864         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9865         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9866         struct drm_display_mode *mode;
9867         struct intel_crtc_state *pipe_config;
9868         int htot = I915_READ(HTOTAL(cpu_transcoder));
9869         int hsync = I915_READ(HSYNC(cpu_transcoder));
9870         int vtot = I915_READ(VTOTAL(cpu_transcoder));
9871         int vsync = I915_READ(VSYNC(cpu_transcoder));
9872         enum pipe pipe = intel_crtc->pipe;
9873
9874         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9875         if (!mode)
9876                 return NULL;
9877
9878         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9879         if (!pipe_config) {
9880                 kfree(mode);
9881                 return NULL;
9882         }
9883
9884         /*
9885          * Construct a pipe_config sufficient for getting the clock info
9886          * back out of crtc_clock_get.
9887          *
9888          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9889          * to use a real value here instead.
9890          */
9891         pipe_config->cpu_transcoder = (enum transcoder) pipe;
9892         pipe_config->pixel_multiplier = 1;
9893         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9894         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9895         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9896         i9xx_crtc_clock_get(intel_crtc, pipe_config);
9897
9898         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
9899         mode->hdisplay = (htot & 0xffff) + 1;
9900         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9901         mode->hsync_start = (hsync & 0xffff) + 1;
9902         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9903         mode->vdisplay = (vtot & 0xffff) + 1;
9904         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9905         mode->vsync_start = (vsync & 0xffff) + 1;
9906         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9907
9908         drm_mode_set_name(mode);
9909
9910         kfree(pipe_config);
9911
9912         return mode;
9913 }
9914
9915 static void intel_crtc_destroy(struct drm_crtc *crtc)
9916 {
9917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9918         struct drm_device *dev = crtc->dev;
9919         struct intel_flip_work *work;
9920
9921         spin_lock_irq(&dev->event_lock);
9922         work = intel_crtc->flip_work;
9923         intel_crtc->flip_work = NULL;
9924         spin_unlock_irq(&dev->event_lock);
9925
9926         if (work) {
9927                 cancel_work_sync(&work->mmio_work);
9928                 cancel_work_sync(&work->unpin_work);
9929                 kfree(work);
9930         }
9931
9932         drm_crtc_cleanup(crtc);
9933
9934         kfree(intel_crtc);
9935 }
9936
9937 static void intel_unpin_work_fn(struct work_struct *__work)
9938 {
9939         struct intel_flip_work *work =
9940                 container_of(__work, struct intel_flip_work, unpin_work);
9941         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
9942         struct drm_device *dev = crtc->base.dev;
9943         struct drm_plane *primary = crtc->base.primary;
9944
9945         if (is_mmio_work(work))
9946                 flush_work(&work->mmio_work);
9947
9948         mutex_lock(&dev->struct_mutex);
9949         intel_unpin_fb_vma(work->old_vma);
9950         i915_gem_object_put(work->pending_flip_obj);
9951         mutex_unlock(&dev->struct_mutex);
9952
9953         i915_gem_request_put(work->flip_queued_req);
9954
9955         intel_frontbuffer_flip_complete(to_i915(dev),
9956                                         to_intel_plane(primary)->frontbuffer_bit);
9957         intel_fbc_post_update(crtc);
9958         drm_framebuffer_unreference(work->old_fb);
9959
9960         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
9961         atomic_dec(&crtc->unpin_work_count);
9962
9963         kfree(work);
9964 }
9965
9966 /* Is 'a' after or equal to 'b'? */
9967 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9968 {
9969         return !((a - b) & 0x80000000);
9970 }
9971
9972 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
9973                                    struct intel_flip_work *work)
9974 {
9975         struct drm_device *dev = crtc->base.dev;
9976         struct drm_i915_private *dev_priv = to_i915(dev);
9977
9978         if (abort_flip_on_reset(crtc))
9979                 return true;
9980
9981         /*
9982          * The relevant registers doen't exist on pre-ctg.
9983          * As the flip done interrupt doesn't trigger for mmio
9984          * flips on gmch platforms, a flip count check isn't
9985          * really needed there. But since ctg has the registers,
9986          * include it in the check anyway.
9987          */
9988         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
9989                 return true;
9990
9991         /*
9992          * BDW signals flip done immediately if the plane
9993          * is disabled, even if the plane enable is already
9994          * armed to occur at the next vblank :(
9995          */
9996
9997         /*
9998          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9999          * used the same base address. In that case the mmio flip might
10000          * have completed, but the CS hasn't even executed the flip yet.
10001          *
10002          * A flip count check isn't enough as the CS might have updated
10003          * the base address just after start of vblank, but before we
10004          * managed to process the interrupt. This means we'd complete the
10005          * CS flip too soon.
10006          *
10007          * Combining both checks should get us a good enough result. It may
10008          * still happen that the CS flip has been executed, but has not
10009          * yet actually completed. But in case the base address is the same
10010          * anyway, we don't really care.
10011          */
10012         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10013                 crtc->flip_work->gtt_offset &&
10014                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10015                                     crtc->flip_work->flip_count);
10016 }
10017
10018 static bool
10019 __pageflip_finished_mmio(struct intel_crtc *crtc,
10020                                struct intel_flip_work *work)
10021 {
10022         /*
10023          * MMIO work completes when vblank is different from
10024          * flip_queued_vblank.
10025          *
10026          * Reset counter value doesn't matter, this is handled by
10027          * i915_wait_request finishing early, so no need to handle
10028          * reset here.
10029          */
10030         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10031 }
10032
10033
10034 static bool pageflip_finished(struct intel_crtc *crtc,
10035                               struct intel_flip_work *work)
10036 {
10037         if (!atomic_read(&work->pending))
10038                 return false;
10039
10040         smp_rmb();
10041
10042         if (is_mmio_work(work))
10043                 return __pageflip_finished_mmio(crtc, work);
10044         else
10045                 return __pageflip_finished_cs(crtc, work);
10046 }
10047
10048 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10049 {
10050         struct drm_device *dev = &dev_priv->drm;
10051         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10052         struct intel_flip_work *work;
10053         unsigned long flags;
10054
10055         /* Ignore early vblank irqs */
10056         if (!crtc)
10057                 return;
10058
10059         /*
10060          * This is called both by irq handlers and the reset code (to complete
10061          * lost pageflips) so needs the full irqsave spinlocks.
10062          */
10063         spin_lock_irqsave(&dev->event_lock, flags);
10064         work = crtc->flip_work;
10065
10066         if (work != NULL &&
10067             !is_mmio_work(work) &&
10068             pageflip_finished(crtc, work))
10069                 page_flip_completed(crtc);
10070
10071         spin_unlock_irqrestore(&dev->event_lock, flags);
10072 }
10073
10074 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10075 {
10076         struct drm_device *dev = &dev_priv->drm;
10077         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10078         struct intel_flip_work *work;
10079         unsigned long flags;
10080
10081         /* Ignore early vblank irqs */
10082         if (!crtc)
10083                 return;
10084
10085         /*
10086          * This is called both by irq handlers and the reset code (to complete
10087          * lost pageflips) so needs the full irqsave spinlocks.
10088          */
10089         spin_lock_irqsave(&dev->event_lock, flags);
10090         work = crtc->flip_work;
10091
10092         if (work != NULL &&
10093             is_mmio_work(work) &&
10094             pageflip_finished(crtc, work))
10095                 page_flip_completed(crtc);
10096
10097         spin_unlock_irqrestore(&dev->event_lock, flags);
10098 }
10099
10100 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10101                                                struct intel_flip_work *work)
10102 {
10103         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10104
10105         /* Ensure that the work item is consistent when activating it ... */
10106         smp_mb__before_atomic();
10107         atomic_set(&work->pending, 1);
10108 }
10109
10110 static int intel_gen2_queue_flip(struct drm_device *dev,
10111                                  struct drm_crtc *crtc,
10112                                  struct drm_framebuffer *fb,
10113                                  struct drm_i915_gem_object *obj,
10114                                  struct drm_i915_gem_request *req,
10115                                  uint32_t flags)
10116 {
10117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10118         u32 flip_mask, *cs;
10119
10120         cs = intel_ring_begin(req, 6);
10121         if (IS_ERR(cs))
10122                 return PTR_ERR(cs);
10123
10124         /* Can't queue multiple flips, so wait for the previous
10125          * one to finish before executing the next.
10126          */
10127         if (intel_crtc->plane)
10128                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10129         else
10130                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10131         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10132         *cs++ = MI_NOOP;
10133         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10134         *cs++ = fb->pitches[0];
10135         *cs++ = intel_crtc->flip_work->gtt_offset;
10136         *cs++ = 0; /* aux display base address, unused */
10137
10138         return 0;
10139 }
10140
10141 static int intel_gen3_queue_flip(struct drm_device *dev,
10142                                  struct drm_crtc *crtc,
10143                                  struct drm_framebuffer *fb,
10144                                  struct drm_i915_gem_object *obj,
10145                                  struct drm_i915_gem_request *req,
10146                                  uint32_t flags)
10147 {
10148         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10149         u32 flip_mask, *cs;
10150
10151         cs = intel_ring_begin(req, 6);
10152         if (IS_ERR(cs))
10153                 return PTR_ERR(cs);
10154
10155         if (intel_crtc->plane)
10156                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10157         else
10158                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10159         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10160         *cs++ = MI_NOOP;
10161         *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10162         *cs++ = fb->pitches[0];
10163         *cs++ = intel_crtc->flip_work->gtt_offset;
10164         *cs++ = MI_NOOP;
10165
10166         return 0;
10167 }
10168
10169 static int intel_gen4_queue_flip(struct drm_device *dev,
10170                                  struct drm_crtc *crtc,
10171                                  struct drm_framebuffer *fb,
10172                                  struct drm_i915_gem_object *obj,
10173                                  struct drm_i915_gem_request *req,
10174                                  uint32_t flags)
10175 {
10176         struct drm_i915_private *dev_priv = to_i915(dev);
10177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10178         u32 pf, pipesrc, *cs;
10179
10180         cs = intel_ring_begin(req, 4);
10181         if (IS_ERR(cs))
10182                 return PTR_ERR(cs);
10183
10184         /* i965+ uses the linear or tiled offsets from the
10185          * Display Registers (which do not change across a page-flip)
10186          * so we need only reprogram the base address.
10187          */
10188         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10189         *cs++ = fb->pitches[0];
10190         *cs++ = intel_crtc->flip_work->gtt_offset |
10191                 intel_fb_modifier_to_tiling(fb->modifier);
10192
10193         /* XXX Enabling the panel-fitter across page-flip is so far
10194          * untested on non-native modes, so ignore it for now.
10195          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10196          */
10197         pf = 0;
10198         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10199         *cs++ = pf | pipesrc;
10200
10201         return 0;
10202 }
10203
10204 static int intel_gen6_queue_flip(struct drm_device *dev,
10205                                  struct drm_crtc *crtc,
10206                                  struct drm_framebuffer *fb,
10207                                  struct drm_i915_gem_object *obj,
10208                                  struct drm_i915_gem_request *req,
10209                                  uint32_t flags)
10210 {
10211         struct drm_i915_private *dev_priv = to_i915(dev);
10212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10213         u32 pf, pipesrc, *cs;
10214
10215         cs = intel_ring_begin(req, 4);
10216         if (IS_ERR(cs))
10217                 return PTR_ERR(cs);
10218
10219         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10220         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10221         *cs++ = intel_crtc->flip_work->gtt_offset;
10222
10223         /* Contrary to the suggestions in the documentation,
10224          * "Enable Panel Fitter" does not seem to be required when page
10225          * flipping with a non-native mode, and worse causes a normal
10226          * modeset to fail.
10227          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10228          */
10229         pf = 0;
10230         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10231         *cs++ = pf | pipesrc;
10232
10233         return 0;
10234 }
10235
10236 static int intel_gen7_queue_flip(struct drm_device *dev,
10237                                  struct drm_crtc *crtc,
10238                                  struct drm_framebuffer *fb,
10239                                  struct drm_i915_gem_object *obj,
10240                                  struct drm_i915_gem_request *req,
10241                                  uint32_t flags)
10242 {
10243         struct drm_i915_private *dev_priv = to_i915(dev);
10244         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10245         u32 *cs, plane_bit = 0;
10246         int len, ret;
10247
10248         switch (intel_crtc->plane) {
10249         case PLANE_A:
10250                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10251                 break;
10252         case PLANE_B:
10253                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10254                 break;
10255         case PLANE_C:
10256                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10257                 break;
10258         default:
10259                 WARN_ONCE(1, "unknown plane in flip command\n");
10260                 return -ENODEV;
10261         }
10262
10263         len = 4;
10264         if (req->engine->id == RCS) {
10265                 len += 6;
10266                 /*
10267                  * On Gen 8, SRM is now taking an extra dword to accommodate
10268                  * 48bits addresses, and we need a NOOP for the batch size to
10269                  * stay even.
10270                  */
10271                 if (IS_GEN8(dev_priv))
10272                         len += 2;
10273         }
10274
10275         /*
10276          * BSpec MI_DISPLAY_FLIP for IVB:
10277          * "The full packet must be contained within the same cache line."
10278          *
10279          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10280          * cacheline, if we ever start emitting more commands before
10281          * the MI_DISPLAY_FLIP we may need to first emit everything else,
10282          * then do the cacheline alignment, and finally emit the
10283          * MI_DISPLAY_FLIP.
10284          */
10285         ret = intel_ring_cacheline_align(req);
10286         if (ret)
10287                 return ret;
10288
10289         cs = intel_ring_begin(req, len);
10290         if (IS_ERR(cs))
10291                 return PTR_ERR(cs);
10292
10293         /* Unmask the flip-done completion message. Note that the bspec says that
10294          * we should do this for both the BCS and RCS, and that we must not unmask
10295          * more than one flip event at any time (or ensure that one flip message
10296          * can be sent by waiting for flip-done prior to queueing new flips).
10297          * Experimentation says that BCS works despite DERRMR masking all
10298          * flip-done completion events and that unmasking all planes at once
10299          * for the RCS also doesn't appear to drop events. Setting the DERRMR
10300          * to zero does lead to lockups within MI_DISPLAY_FLIP.
10301          */
10302         if (req->engine->id == RCS) {
10303                 *cs++ = MI_LOAD_REGISTER_IMM(1);
10304                 *cs++ = i915_mmio_reg_offset(DERRMR);
10305                 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10306                           DERRMR_PIPEB_PRI_FLIP_DONE |
10307                           DERRMR_PIPEC_PRI_FLIP_DONE);
10308                 if (IS_GEN8(dev_priv))
10309                         *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10310                                 MI_SRM_LRM_GLOBAL_GTT;
10311                 else
10312                         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10313                 *cs++ = i915_mmio_reg_offset(DERRMR);
10314                 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
10315                 if (IS_GEN8(dev_priv)) {
10316                         *cs++ = 0;
10317                         *cs++ = MI_NOOP;
10318                 }
10319         }
10320
10321         *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10322         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10323         *cs++ = intel_crtc->flip_work->gtt_offset;
10324         *cs++ = MI_NOOP;
10325
10326         return 0;
10327 }
10328
10329 static bool use_mmio_flip(struct intel_engine_cs *engine,
10330                           struct drm_i915_gem_object *obj)
10331 {
10332         /*
10333          * This is not being used for older platforms, because
10334          * non-availability of flip done interrupt forces us to use
10335          * CS flips. Older platforms derive flip done using some clever
10336          * tricks involving the flip_pending status bits and vblank irqs.
10337          * So using MMIO flips there would disrupt this mechanism.
10338          */
10339
10340         if (engine == NULL)
10341                 return true;
10342
10343         if (INTEL_GEN(engine->i915) < 5)
10344                 return false;
10345
10346         if (i915.use_mmio_flip < 0)
10347                 return false;
10348         else if (i915.use_mmio_flip > 0)
10349                 return true;
10350         else if (i915.enable_execlists)
10351                 return true;
10352
10353         return engine != i915_gem_object_last_write_engine(obj);
10354 }
10355
10356 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10357                              unsigned int rotation,
10358                              struct intel_flip_work *work)
10359 {
10360         struct drm_device *dev = intel_crtc->base.dev;
10361         struct drm_i915_private *dev_priv = to_i915(dev);
10362         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10363         const enum pipe pipe = intel_crtc->pipe;
10364         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10365
10366         ctl = I915_READ(PLANE_CTL(pipe, 0));
10367         ctl &= ~PLANE_CTL_TILED_MASK;
10368         switch (fb->modifier) {
10369         case DRM_FORMAT_MOD_LINEAR:
10370                 break;
10371         case I915_FORMAT_MOD_X_TILED:
10372                 ctl |= PLANE_CTL_TILED_X;
10373                 break;
10374         case I915_FORMAT_MOD_Y_TILED:
10375                 ctl |= PLANE_CTL_TILED_Y;
10376                 break;
10377         case I915_FORMAT_MOD_Yf_TILED:
10378                 ctl |= PLANE_CTL_TILED_YF;
10379                 break;
10380         default:
10381                 MISSING_CASE(fb->modifier);
10382         }
10383
10384         /*
10385          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10386          * PLANE_SURF updates, the update is then guaranteed to be atomic.
10387          */
10388         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10389         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10390
10391         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10392         POSTING_READ(PLANE_SURF(pipe, 0));
10393 }
10394
10395 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10396                              struct intel_flip_work *work)
10397 {
10398         struct drm_device *dev = intel_crtc->base.dev;
10399         struct drm_i915_private *dev_priv = to_i915(dev);
10400         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10401         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10402         u32 dspcntr;
10403
10404         dspcntr = I915_READ(reg);
10405
10406         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10407                 dspcntr |= DISPPLANE_TILED;
10408         else
10409                 dspcntr &= ~DISPPLANE_TILED;
10410
10411         I915_WRITE(reg, dspcntr);
10412
10413         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10414         POSTING_READ(DSPSURF(intel_crtc->plane));
10415 }
10416
10417 static void intel_mmio_flip_work_func(struct work_struct *w)
10418 {
10419         struct intel_flip_work *work =
10420                 container_of(w, struct intel_flip_work, mmio_work);
10421         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10422         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10423         struct intel_framebuffer *intel_fb =
10424                 to_intel_framebuffer(crtc->base.primary->fb);
10425         struct drm_i915_gem_object *obj = intel_fb->obj;
10426
10427         WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10428
10429         intel_pipe_update_start(crtc);
10430
10431         if (INTEL_GEN(dev_priv) >= 9)
10432                 skl_do_mmio_flip(crtc, work->rotation, work);
10433         else
10434                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10435                 ilk_do_mmio_flip(crtc, work);
10436
10437         intel_pipe_update_end(crtc, work);
10438 }
10439
10440 static int intel_default_queue_flip(struct drm_device *dev,
10441                                     struct drm_crtc *crtc,
10442                                     struct drm_framebuffer *fb,
10443                                     struct drm_i915_gem_object *obj,
10444                                     struct drm_i915_gem_request *req,
10445                                     uint32_t flags)
10446 {
10447         return -ENODEV;
10448 }
10449
10450 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10451                                       struct intel_crtc *intel_crtc,
10452                                       struct intel_flip_work *work)
10453 {
10454         u32 addr, vblank;
10455
10456         if (!atomic_read(&work->pending))
10457                 return false;
10458
10459         smp_rmb();
10460
10461         vblank = intel_crtc_get_vblank_counter(intel_crtc);
10462         if (work->flip_ready_vblank == 0) {
10463                 if (work->flip_queued_req &&
10464                     !i915_gem_request_completed(work->flip_queued_req))
10465                         return false;
10466
10467                 work->flip_ready_vblank = vblank;
10468         }
10469
10470         if (vblank - work->flip_ready_vblank < 3)
10471                 return false;
10472
10473         /* Potential stall - if we see that the flip has happened,
10474          * assume a missed interrupt. */
10475         if (INTEL_GEN(dev_priv) >= 4)
10476                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10477         else
10478                 addr = I915_READ(DSPADDR(intel_crtc->plane));
10479
10480         /* There is a potential issue here with a false positive after a flip
10481          * to the same address. We could address this by checking for a
10482          * non-incrementing frame counter.
10483          */
10484         return addr == work->gtt_offset;
10485 }
10486
10487 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10488 {
10489         struct drm_device *dev = &dev_priv->drm;
10490         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10491         struct intel_flip_work *work;
10492
10493         WARN_ON(!in_interrupt());
10494
10495         if (crtc == NULL)
10496                 return;
10497
10498         spin_lock(&dev->event_lock);
10499         work = crtc->flip_work;
10500
10501         if (work != NULL && !is_mmio_work(work) &&
10502             __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10503                 WARN_ONCE(1,
10504                           "Kicking stuck page flip: queued at %d, now %d\n",
10505                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10506                 page_flip_completed(crtc);
10507                 work = NULL;
10508         }
10509
10510         if (work != NULL && !is_mmio_work(work) &&
10511             intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10512                 intel_queue_rps_boost_for_request(work->flip_queued_req);
10513         spin_unlock(&dev->event_lock);
10514 }
10515
10516 __maybe_unused
10517 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10518                                 struct drm_framebuffer *fb,
10519                                 struct drm_pending_vblank_event *event,
10520                                 uint32_t page_flip_flags)
10521 {
10522         struct drm_device *dev = crtc->dev;
10523         struct drm_i915_private *dev_priv = to_i915(dev);
10524         struct drm_framebuffer *old_fb = crtc->primary->fb;
10525         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10527         struct drm_plane *primary = crtc->primary;
10528         enum pipe pipe = intel_crtc->pipe;
10529         struct intel_flip_work *work;
10530         struct intel_engine_cs *engine;
10531         bool mmio_flip;
10532         struct drm_i915_gem_request *request;
10533         struct i915_vma *vma;
10534         int ret;
10535
10536         /*
10537          * drm_mode_page_flip_ioctl() should already catch this, but double
10538          * check to be safe.  In the future we may enable pageflipping from
10539          * a disabled primary plane.
10540          */
10541         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10542                 return -EBUSY;
10543
10544         /* Can't change pixel format via MI display flips. */
10545         if (fb->format != crtc->primary->fb->format)
10546                 return -EINVAL;
10547
10548         /*
10549          * TILEOFF/LINOFF registers can't be changed via MI display flips.
10550          * Note that pitch changes could also affect these register.
10551          */
10552         if (INTEL_GEN(dev_priv) > 3 &&
10553             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10554              fb->pitches[0] != crtc->primary->fb->pitches[0]))
10555                 return -EINVAL;
10556
10557         if (i915_terminally_wedged(&dev_priv->gpu_error))
10558                 goto out_hang;
10559
10560         work = kzalloc(sizeof(*work), GFP_KERNEL);
10561         if (work == NULL)
10562                 return -ENOMEM;
10563
10564         work->event = event;
10565         work->crtc = crtc;
10566         work->old_fb = old_fb;
10567         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10568
10569         ret = drm_crtc_vblank_get(crtc);
10570         if (ret)
10571                 goto free_work;
10572
10573         /* We borrow the event spin lock for protecting flip_work */
10574         spin_lock_irq(&dev->event_lock);
10575         if (intel_crtc->flip_work) {
10576                 /* Before declaring the flip queue wedged, check if
10577                  * the hardware completed the operation behind our backs.
10578                  */
10579                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10580                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10581                         page_flip_completed(intel_crtc);
10582                 } else {
10583                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10584                         spin_unlock_irq(&dev->event_lock);
10585
10586                         drm_crtc_vblank_put(crtc);
10587                         kfree(work);
10588                         return -EBUSY;
10589                 }
10590         }
10591         intel_crtc->flip_work = work;
10592         spin_unlock_irq(&dev->event_lock);
10593
10594         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10595                 flush_workqueue(dev_priv->wq);
10596
10597         /* Reference the objects for the scheduled work. */
10598         drm_framebuffer_reference(work->old_fb);
10599
10600         crtc->primary->fb = fb;
10601         update_state_fb(crtc->primary);
10602
10603         work->pending_flip_obj = i915_gem_object_get(obj);
10604
10605         ret = i915_mutex_lock_interruptible(dev);
10606         if (ret)
10607                 goto cleanup;
10608
10609         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10610         if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) {
10611                 ret = -EIO;
10612                 goto unlock;
10613         }
10614
10615         atomic_inc(&intel_crtc->unpin_work_count);
10616
10617         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10618                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10619
10620         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10621                 engine = dev_priv->engine[BCS];
10622                 if (fb->modifier != old_fb->modifier)
10623                         /* vlv: DISPLAY_FLIP fails to change tiling */
10624                         engine = NULL;
10625         } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10626                 engine = dev_priv->engine[BCS];
10627         } else if (INTEL_GEN(dev_priv) >= 7) {
10628                 engine = i915_gem_object_last_write_engine(obj);
10629                 if (engine == NULL || engine->id != RCS)
10630                         engine = dev_priv->engine[BCS];
10631         } else {
10632                 engine = dev_priv->engine[RCS];
10633         }
10634
10635         mmio_flip = use_mmio_flip(engine, obj);
10636
10637         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10638         if (IS_ERR(vma)) {
10639                 ret = PTR_ERR(vma);
10640                 goto cleanup_pending;
10641         }
10642
10643         work->old_vma = to_intel_plane_state(primary->state)->vma;
10644         to_intel_plane_state(primary->state)->vma = vma;
10645
10646         work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10647         work->rotation = crtc->primary->state->rotation;
10648
10649         /*
10650          * There's the potential that the next frame will not be compatible with
10651          * FBC, so we want to call pre_update() before the actual page flip.
10652          * The problem is that pre_update() caches some information about the fb
10653          * object, so we want to do this only after the object is pinned. Let's
10654          * be on the safe side and do this immediately before scheduling the
10655          * flip.
10656          */
10657         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10658                              to_intel_plane_state(primary->state));
10659
10660         if (mmio_flip) {
10661                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10662                 queue_work(system_unbound_wq, &work->mmio_work);
10663         } else {
10664                 request = i915_gem_request_alloc(engine,
10665                                                  dev_priv->kernel_context);
10666                 if (IS_ERR(request)) {
10667                         ret = PTR_ERR(request);
10668                         goto cleanup_unpin;
10669                 }
10670
10671                 ret = i915_gem_request_await_object(request, obj, false);
10672                 if (ret)
10673                         goto cleanup_request;
10674
10675                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10676                                                    page_flip_flags);
10677                 if (ret)
10678                         goto cleanup_request;
10679
10680                 intel_mark_page_flip_active(intel_crtc, work);
10681
10682                 work->flip_queued_req = i915_gem_request_get(request);
10683                 i915_add_request(request);
10684         }
10685
10686         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10687         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10688                           to_intel_plane(primary)->frontbuffer_bit);
10689         mutex_unlock(&dev->struct_mutex);
10690
10691         intel_frontbuffer_flip_prepare(to_i915(dev),
10692                                        to_intel_plane(primary)->frontbuffer_bit);
10693
10694         trace_i915_flip_request(intel_crtc->plane, obj);
10695
10696         return 0;
10697
10698 cleanup_request:
10699         i915_add_request(request);
10700 cleanup_unpin:
10701         to_intel_plane_state(primary->state)->vma = work->old_vma;
10702         intel_unpin_fb_vma(vma);
10703 cleanup_pending:
10704         atomic_dec(&intel_crtc->unpin_work_count);
10705 unlock:
10706         mutex_unlock(&dev->struct_mutex);
10707 cleanup:
10708         crtc->primary->fb = old_fb;
10709         update_state_fb(crtc->primary);
10710
10711         i915_gem_object_put(obj);
10712         drm_framebuffer_unreference(work->old_fb);
10713
10714         spin_lock_irq(&dev->event_lock);
10715         intel_crtc->flip_work = NULL;
10716         spin_unlock_irq(&dev->event_lock);
10717
10718         drm_crtc_vblank_put(crtc);
10719 free_work:
10720         kfree(work);
10721
10722         if (ret == -EIO) {
10723                 struct drm_atomic_state *state;
10724                 struct drm_plane_state *plane_state;
10725
10726 out_hang:
10727                 state = drm_atomic_state_alloc(dev);
10728                 if (!state)
10729                         return -ENOMEM;
10730                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
10731
10732 retry:
10733                 plane_state = drm_atomic_get_plane_state(state, primary);
10734                 ret = PTR_ERR_OR_ZERO(plane_state);
10735                 if (!ret) {
10736                         drm_atomic_set_fb_for_plane(plane_state, fb);
10737
10738                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10739                         if (!ret)
10740                                 ret = drm_atomic_commit(state);
10741                 }
10742
10743                 if (ret == -EDEADLK) {
10744                         drm_modeset_backoff(state->acquire_ctx);
10745                         drm_atomic_state_clear(state);
10746                         goto retry;
10747                 }
10748
10749                 drm_atomic_state_put(state);
10750
10751                 if (ret == 0 && event) {
10752                         spin_lock_irq(&dev->event_lock);
10753                         drm_crtc_send_vblank_event(crtc, event);
10754                         spin_unlock_irq(&dev->event_lock);
10755                 }
10756         }
10757         return ret;
10758 }
10759
10760
10761 /**
10762  * intel_wm_need_update - Check whether watermarks need updating
10763  * @plane: drm plane
10764  * @state: new plane state
10765  *
10766  * Check current plane state versus the new one to determine whether
10767  * watermarks need to be recalculated.
10768  *
10769  * Returns true or false.
10770  */
10771 static bool intel_wm_need_update(struct drm_plane *plane,
10772                                  struct drm_plane_state *state)
10773 {
10774         struct intel_plane_state *new = to_intel_plane_state(state);
10775         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10776
10777         /* Update watermarks on tiling or size changes. */
10778         if (new->base.visible != cur->base.visible)
10779                 return true;
10780
10781         if (!cur->base.fb || !new->base.fb)
10782                 return false;
10783
10784         if (cur->base.fb->modifier != new->base.fb->modifier ||
10785             cur->base.rotation != new->base.rotation ||
10786             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10787             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10788             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10789             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10790                 return true;
10791
10792         return false;
10793 }
10794
10795 static bool needs_scaling(struct intel_plane_state *state)
10796 {
10797         int src_w = drm_rect_width(&state->base.src) >> 16;
10798         int src_h = drm_rect_height(&state->base.src) >> 16;
10799         int dst_w = drm_rect_width(&state->base.dst);
10800         int dst_h = drm_rect_height(&state->base.dst);
10801
10802         return (src_w != dst_w || src_h != dst_h);
10803 }
10804
10805 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10806                                     struct drm_plane_state *plane_state)
10807 {
10808         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10809         struct drm_crtc *crtc = crtc_state->crtc;
10810         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10811         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10812         struct drm_device *dev = crtc->dev;
10813         struct drm_i915_private *dev_priv = to_i915(dev);
10814         struct intel_plane_state *old_plane_state =
10815                 to_intel_plane_state(plane->base.state);
10816         bool mode_changed = needs_modeset(crtc_state);
10817         bool was_crtc_enabled = crtc->state->active;
10818         bool is_crtc_enabled = crtc_state->active;
10819         bool turn_off, turn_on, visible, was_visible;
10820         struct drm_framebuffer *fb = plane_state->fb;
10821         int ret;
10822
10823         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10824                 ret = skl_update_scaler_plane(
10825                         to_intel_crtc_state(crtc_state),
10826                         to_intel_plane_state(plane_state));
10827                 if (ret)
10828                         return ret;
10829         }
10830
10831         was_visible = old_plane_state->base.visible;
10832         visible = plane_state->visible;
10833
10834         if (!was_crtc_enabled && WARN_ON(was_visible))
10835                 was_visible = false;
10836
10837         /*
10838          * Visibility is calculated as if the crtc was on, but
10839          * after scaler setup everything depends on it being off
10840          * when the crtc isn't active.
10841          *
10842          * FIXME this is wrong for watermarks. Watermarks should also
10843          * be computed as if the pipe would be active. Perhaps move
10844          * per-plane wm computation to the .check_plane() hook, and
10845          * only combine the results from all planes in the current place?
10846          */
10847         if (!is_crtc_enabled) {
10848                 plane_state->visible = visible = false;
10849                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10850         }
10851
10852         if (!was_visible && !visible)
10853                 return 0;
10854
10855         if (fb != old_plane_state->base.fb)
10856                 pipe_config->fb_changed = true;
10857
10858         turn_off = was_visible && (!visible || mode_changed);
10859         turn_on = visible && (!was_visible || mode_changed);
10860
10861         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10862                          intel_crtc->base.base.id, intel_crtc->base.name,
10863                          plane->base.base.id, plane->base.name,
10864                          fb ? fb->base.id : -1);
10865
10866         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10867                          plane->base.base.id, plane->base.name,
10868                          was_visible, visible,
10869                          turn_off, turn_on, mode_changed);
10870
10871         if (turn_on) {
10872                 if (INTEL_GEN(dev_priv) < 5)
10873                         pipe_config->update_wm_pre = true;
10874
10875                 /* must disable cxsr around plane enable/disable */
10876                 if (plane->id != PLANE_CURSOR)
10877                         pipe_config->disable_cxsr = true;
10878         } else if (turn_off) {
10879                 if (INTEL_GEN(dev_priv) < 5)
10880                         pipe_config->update_wm_post = true;
10881
10882                 /* must disable cxsr around plane enable/disable */
10883                 if (plane->id != PLANE_CURSOR)
10884                         pipe_config->disable_cxsr = true;
10885         } else if (intel_wm_need_update(&plane->base, plane_state)) {
10886                 if (INTEL_GEN(dev_priv) < 5) {
10887                         /* FIXME bollocks */
10888                         pipe_config->update_wm_pre = true;
10889                         pipe_config->update_wm_post = true;
10890                 }
10891         }
10892
10893         if (visible || was_visible)
10894                 pipe_config->fb_bits |= plane->frontbuffer_bit;
10895
10896         /*
10897          * WaCxSRDisabledForSpriteScaling:ivb
10898          *
10899          * cstate->update_wm was already set above, so this flag will
10900          * take effect when we commit and program watermarks.
10901          */
10902         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10903             needs_scaling(to_intel_plane_state(plane_state)) &&
10904             !needs_scaling(old_plane_state))
10905                 pipe_config->disable_lp_wm = true;
10906
10907         return 0;
10908 }
10909
10910 static bool encoders_cloneable(const struct intel_encoder *a,
10911                                const struct intel_encoder *b)
10912 {
10913         /* masks could be asymmetric, so check both ways */
10914         return a == b || (a->cloneable & (1 << b->type) &&
10915                           b->cloneable & (1 << a->type));
10916 }
10917
10918 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10919                                          struct intel_crtc *crtc,
10920                                          struct intel_encoder *encoder)
10921 {
10922         struct intel_encoder *source_encoder;
10923         struct drm_connector *connector;
10924         struct drm_connector_state *connector_state;
10925         int i;
10926
10927         for_each_new_connector_in_state(state, connector, connector_state, i) {
10928                 if (connector_state->crtc != &crtc->base)
10929                         continue;
10930
10931                 source_encoder =
10932                         to_intel_encoder(connector_state->best_encoder);
10933                 if (!encoders_cloneable(encoder, source_encoder))
10934                         return false;
10935         }
10936
10937         return true;
10938 }
10939
10940 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10941                                    struct drm_crtc_state *crtc_state)
10942 {
10943         struct drm_device *dev = crtc->dev;
10944         struct drm_i915_private *dev_priv = to_i915(dev);
10945         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10946         struct intel_crtc_state *pipe_config =
10947                 to_intel_crtc_state(crtc_state);
10948         struct drm_atomic_state *state = crtc_state->state;
10949         int ret;
10950         bool mode_changed = needs_modeset(crtc_state);
10951
10952         if (mode_changed && !crtc_state->active)
10953                 pipe_config->update_wm_post = true;
10954
10955         if (mode_changed && crtc_state->enable &&
10956             dev_priv->display.crtc_compute_clock &&
10957             !WARN_ON(pipe_config->shared_dpll)) {
10958                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10959                                                            pipe_config);
10960                 if (ret)
10961                         return ret;
10962         }
10963
10964         if (crtc_state->color_mgmt_changed) {
10965                 ret = intel_color_check(crtc, crtc_state);
10966                 if (ret)
10967                         return ret;
10968
10969                 /*
10970                  * Changing color management on Intel hardware is
10971                  * handled as part of planes update.
10972                  */
10973                 crtc_state->planes_changed = true;
10974         }
10975
10976         ret = 0;
10977         if (dev_priv->display.compute_pipe_wm) {
10978                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10979                 if (ret) {
10980                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10981                         return ret;
10982                 }
10983         }
10984
10985         if (dev_priv->display.compute_intermediate_wm &&
10986             !to_intel_atomic_state(state)->skip_intermediate_wm) {
10987                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10988                         return 0;
10989
10990                 /*
10991                  * Calculate 'intermediate' watermarks that satisfy both the
10992                  * old state and the new state.  We can program these
10993                  * immediately.
10994                  */
10995                 ret = dev_priv->display.compute_intermediate_wm(dev,
10996                                                                 intel_crtc,
10997                                                                 pipe_config);
10998                 if (ret) {
10999                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11000                         return ret;
11001                 }
11002         } else if (dev_priv->display.compute_intermediate_wm) {
11003                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
11004                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
11005         }
11006
11007         if (INTEL_GEN(dev_priv) >= 9) {
11008                 if (mode_changed)
11009                         ret = skl_update_scaler_crtc(pipe_config);
11010
11011                 if (!ret)
11012                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11013                                                          pipe_config);
11014         }
11015
11016         return ret;
11017 }
11018
11019 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11020         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11021         .atomic_begin = intel_begin_crtc_commit,
11022         .atomic_flush = intel_finish_crtc_commit,
11023         .atomic_check = intel_crtc_atomic_check,
11024 };
11025
11026 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11027 {
11028         struct intel_connector *connector;
11029         struct drm_connector_list_iter conn_iter;
11030
11031         drm_connector_list_iter_begin(dev, &conn_iter);
11032         for_each_intel_connector_iter(connector, &conn_iter) {
11033                 if (connector->base.state->crtc)
11034                         drm_connector_unreference(&connector->base);
11035
11036                 if (connector->base.encoder) {
11037                         connector->base.state->best_encoder =
11038                                 connector->base.encoder;
11039                         connector->base.state->crtc =
11040                                 connector->base.encoder->crtc;
11041
11042                         drm_connector_reference(&connector->base);
11043                 } else {
11044                         connector->base.state->best_encoder = NULL;
11045                         connector->base.state->crtc = NULL;
11046                 }
11047         }
11048         drm_connector_list_iter_end(&conn_iter);
11049 }
11050
11051 static void
11052 connected_sink_compute_bpp(struct intel_connector *connector,
11053                            struct intel_crtc_state *pipe_config)
11054 {
11055         const struct drm_display_info *info = &connector->base.display_info;
11056         int bpp = pipe_config->pipe_bpp;
11057
11058         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11059                       connector->base.base.id,
11060                       connector->base.name);
11061
11062         /* Don't use an invalid EDID bpc value */
11063         if (info->bpc != 0 && info->bpc * 3 < bpp) {
11064                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11065                               bpp, info->bpc * 3);
11066                 pipe_config->pipe_bpp = info->bpc * 3;
11067         }
11068
11069         /* Clamp bpp to 8 on screens without EDID 1.4 */
11070         if (info->bpc == 0 && bpp > 24) {
11071                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11072                               bpp);
11073                 pipe_config->pipe_bpp = 24;
11074         }
11075 }
11076
11077 static int
11078 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11079                           struct intel_crtc_state *pipe_config)
11080 {
11081         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11082         struct drm_atomic_state *state;
11083         struct drm_connector *connector;
11084         struct drm_connector_state *connector_state;
11085         int bpp, i;
11086
11087         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11088             IS_CHERRYVIEW(dev_priv)))
11089                 bpp = 10*3;
11090         else if (INTEL_GEN(dev_priv) >= 5)
11091                 bpp = 12*3;
11092         else
11093                 bpp = 8*3;
11094
11095
11096         pipe_config->pipe_bpp = bpp;
11097
11098         state = pipe_config->base.state;
11099
11100         /* Clamp display bpp to EDID value */
11101         for_each_new_connector_in_state(state, connector, connector_state, i) {
11102                 if (connector_state->crtc != &crtc->base)
11103                         continue;
11104
11105                 connected_sink_compute_bpp(to_intel_connector(connector),
11106                                            pipe_config);
11107         }
11108
11109         return bpp;
11110 }
11111
11112 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11113 {
11114         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11115                         "type: 0x%x flags: 0x%x\n",
11116                 mode->crtc_clock,
11117                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11118                 mode->crtc_hsync_end, mode->crtc_htotal,
11119                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11120                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11121 }
11122
11123 static inline void
11124 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11125                       unsigned int lane_count, struct intel_link_m_n *m_n)
11126 {
11127         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11128                       id, lane_count,
11129                       m_n->gmch_m, m_n->gmch_n,
11130                       m_n->link_m, m_n->link_n, m_n->tu);
11131 }
11132
11133 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11134                                    struct intel_crtc_state *pipe_config,
11135                                    const char *context)
11136 {
11137         struct drm_device *dev = crtc->base.dev;
11138         struct drm_i915_private *dev_priv = to_i915(dev);
11139         struct drm_plane *plane;
11140         struct intel_plane *intel_plane;
11141         struct intel_plane_state *state;
11142         struct drm_framebuffer *fb;
11143
11144         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11145                       crtc->base.base.id, crtc->base.name, context);
11146
11147         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11148                       transcoder_name(pipe_config->cpu_transcoder),
11149                       pipe_config->pipe_bpp, pipe_config->dither);
11150
11151         if (pipe_config->has_pch_encoder)
11152                 intel_dump_m_n_config(pipe_config, "fdi",
11153                                       pipe_config->fdi_lanes,
11154                                       &pipe_config->fdi_m_n);
11155
11156         if (intel_crtc_has_dp_encoder(pipe_config)) {
11157                 intel_dump_m_n_config(pipe_config, "dp m_n",
11158                                 pipe_config->lane_count, &pipe_config->dp_m_n);
11159                 if (pipe_config->has_drrs)
11160                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
11161                                               pipe_config->lane_count,
11162                                               &pipe_config->dp_m2_n2);
11163         }
11164
11165         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11166                       pipe_config->has_audio, pipe_config->has_infoframe);
11167
11168         DRM_DEBUG_KMS("requested mode:\n");
11169         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11170         DRM_DEBUG_KMS("adjusted mode:\n");
11171         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11172         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11173         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11174                       pipe_config->port_clock,
11175                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11176                       pipe_config->pixel_rate);
11177
11178         if (INTEL_GEN(dev_priv) >= 9)
11179                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11180                               crtc->num_scalers,
11181                               pipe_config->scaler_state.scaler_users,
11182                               pipe_config->scaler_state.scaler_id);
11183
11184         if (HAS_GMCH_DISPLAY(dev_priv))
11185                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11186                               pipe_config->gmch_pfit.control,
11187                               pipe_config->gmch_pfit.pgm_ratios,
11188                               pipe_config->gmch_pfit.lvds_border_bits);
11189         else
11190                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11191                               pipe_config->pch_pfit.pos,
11192                               pipe_config->pch_pfit.size,
11193                               enableddisabled(pipe_config->pch_pfit.enabled));
11194
11195         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11196                       pipe_config->ips_enabled, pipe_config->double_wide);
11197
11198         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11199
11200         DRM_DEBUG_KMS("planes on this crtc\n");
11201         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11202                 struct drm_format_name_buf format_name;
11203                 intel_plane = to_intel_plane(plane);
11204                 if (intel_plane->pipe != crtc->pipe)
11205                         continue;
11206
11207                 state = to_intel_plane_state(plane->state);
11208                 fb = state->base.fb;
11209                 if (!fb) {
11210                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11211                                       plane->base.id, plane->name, state->scaler_id);
11212                         continue;
11213                 }
11214
11215                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11216                               plane->base.id, plane->name,
11217                               fb->base.id, fb->width, fb->height,
11218                               drm_get_format_name(fb->format->format, &format_name));
11219                 if (INTEL_GEN(dev_priv) >= 9)
11220                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11221                                       state->scaler_id,
11222                                       state->base.src.x1 >> 16,
11223                                       state->base.src.y1 >> 16,
11224                                       drm_rect_width(&state->base.src) >> 16,
11225                                       drm_rect_height(&state->base.src) >> 16,
11226                                       state->base.dst.x1, state->base.dst.y1,
11227                                       drm_rect_width(&state->base.dst),
11228                                       drm_rect_height(&state->base.dst));
11229         }
11230 }
11231
11232 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11233 {
11234         struct drm_device *dev = state->dev;
11235         struct drm_connector *connector;
11236         unsigned int used_ports = 0;
11237         unsigned int used_mst_ports = 0;
11238
11239         /*
11240          * Walk the connector list instead of the encoder
11241          * list to detect the problem on ddi platforms
11242          * where there's just one encoder per digital port.
11243          */
11244         drm_for_each_connector(connector, dev) {
11245                 struct drm_connector_state *connector_state;
11246                 struct intel_encoder *encoder;
11247
11248                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11249                 if (!connector_state)
11250                         connector_state = connector->state;
11251
11252                 if (!connector_state->best_encoder)
11253                         continue;
11254
11255                 encoder = to_intel_encoder(connector_state->best_encoder);
11256
11257                 WARN_ON(!connector_state->crtc);
11258
11259                 switch (encoder->type) {
11260                         unsigned int port_mask;
11261                 case INTEL_OUTPUT_UNKNOWN:
11262                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
11263                                 break;
11264                 case INTEL_OUTPUT_DP:
11265                 case INTEL_OUTPUT_HDMI:
11266                 case INTEL_OUTPUT_EDP:
11267                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11268
11269                         /* the same port mustn't appear more than once */
11270                         if (used_ports & port_mask)
11271                                 return false;
11272
11273                         used_ports |= port_mask;
11274                         break;
11275                 case INTEL_OUTPUT_DP_MST:
11276                         used_mst_ports |=
11277                                 1 << enc_to_mst(&encoder->base)->primary->port;
11278                         break;
11279                 default:
11280                         break;
11281                 }
11282         }
11283
11284         /* can't mix MST and SST/HDMI on the same port */
11285         if (used_ports & used_mst_ports)
11286                 return false;
11287
11288         return true;
11289 }
11290
11291 static void
11292 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11293 {
11294         struct drm_i915_private *dev_priv =
11295                 to_i915(crtc_state->base.crtc->dev);
11296         struct intel_crtc_scaler_state scaler_state;
11297         struct intel_dpll_hw_state dpll_hw_state;
11298         struct intel_shared_dpll *shared_dpll;
11299         struct intel_crtc_wm_state wm_state;
11300         bool force_thru;
11301
11302         /* FIXME: before the switch to atomic started, a new pipe_config was
11303          * kzalloc'd. Code that depends on any field being zero should be
11304          * fixed, so that the crtc_state can be safely duplicated. For now,
11305          * only fields that are know to not cause problems are preserved. */
11306
11307         scaler_state = crtc_state->scaler_state;
11308         shared_dpll = crtc_state->shared_dpll;
11309         dpll_hw_state = crtc_state->dpll_hw_state;
11310         force_thru = crtc_state->pch_pfit.force_thru;
11311         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11312                 wm_state = crtc_state->wm;
11313
11314         /* Keep base drm_crtc_state intact, only clear our extended struct */
11315         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11316         memset(&crtc_state->base + 1, 0,
11317                sizeof(*crtc_state) - sizeof(crtc_state->base));
11318
11319         crtc_state->scaler_state = scaler_state;
11320         crtc_state->shared_dpll = shared_dpll;
11321         crtc_state->dpll_hw_state = dpll_hw_state;
11322         crtc_state->pch_pfit.force_thru = force_thru;
11323         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11324                 crtc_state->wm = wm_state;
11325 }
11326
11327 static int
11328 intel_modeset_pipe_config(struct drm_crtc *crtc,
11329                           struct intel_crtc_state *pipe_config)
11330 {
11331         struct drm_atomic_state *state = pipe_config->base.state;
11332         struct intel_encoder *encoder;
11333         struct drm_connector *connector;
11334         struct drm_connector_state *connector_state;
11335         int base_bpp, ret = -EINVAL;
11336         int i;
11337         bool retry = true;
11338
11339         clear_intel_crtc_state(pipe_config);
11340
11341         pipe_config->cpu_transcoder =
11342                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11343
11344         /*
11345          * Sanitize sync polarity flags based on requested ones. If neither
11346          * positive or negative polarity is requested, treat this as meaning
11347          * negative polarity.
11348          */
11349         if (!(pipe_config->base.adjusted_mode.flags &
11350               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11351                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11352
11353         if (!(pipe_config->base.adjusted_mode.flags &
11354               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11355                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11356
11357         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11358                                              pipe_config);
11359         if (base_bpp < 0)
11360                 goto fail;
11361
11362         /*
11363          * Determine the real pipe dimensions. Note that stereo modes can
11364          * increase the actual pipe size due to the frame doubling and
11365          * insertion of additional space for blanks between the frame. This
11366          * is stored in the crtc timings. We use the requested mode to do this
11367          * computation to clearly distinguish it from the adjusted mode, which
11368          * can be changed by the connectors in the below retry loop.
11369          */
11370         drm_mode_get_hv_timing(&pipe_config->base.mode,
11371                                &pipe_config->pipe_src_w,
11372                                &pipe_config->pipe_src_h);
11373
11374         for_each_new_connector_in_state(state, connector, connector_state, i) {
11375                 if (connector_state->crtc != crtc)
11376                         continue;
11377
11378                 encoder = to_intel_encoder(connector_state->best_encoder);
11379
11380                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11381                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11382                         goto fail;
11383                 }
11384
11385                 /*
11386                  * Determine output_types before calling the .compute_config()
11387                  * hooks so that the hooks can use this information safely.
11388                  */
11389                 pipe_config->output_types |= 1 << encoder->type;
11390         }
11391
11392 encoder_retry:
11393         /* Ensure the port clock defaults are reset when retrying. */
11394         pipe_config->port_clock = 0;
11395         pipe_config->pixel_multiplier = 1;
11396
11397         /* Fill in default crtc timings, allow encoders to overwrite them. */
11398         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11399                               CRTC_STEREO_DOUBLE);
11400
11401         /* Pass our mode to the connectors and the CRTC to give them a chance to
11402          * adjust it according to limitations or connector properties, and also
11403          * a chance to reject the mode entirely.
11404          */
11405         for_each_new_connector_in_state(state, connector, connector_state, i) {
11406                 if (connector_state->crtc != crtc)
11407                         continue;
11408
11409                 encoder = to_intel_encoder(connector_state->best_encoder);
11410
11411                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11412                         DRM_DEBUG_KMS("Encoder config failure\n");
11413                         goto fail;
11414                 }
11415         }
11416
11417         /* Set default port clock if not overwritten by the encoder. Needs to be
11418          * done afterwards in case the encoder adjusts the mode. */
11419         if (!pipe_config->port_clock)
11420                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11421                         * pipe_config->pixel_multiplier;
11422
11423         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11424         if (ret < 0) {
11425                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11426                 goto fail;
11427         }
11428
11429         if (ret == RETRY) {
11430                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11431                         ret = -EINVAL;
11432                         goto fail;
11433                 }
11434
11435                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11436                 retry = false;
11437                 goto encoder_retry;
11438         }
11439
11440         /* Dithering seems to not pass-through bits correctly when it should, so
11441          * only enable it on 6bpc panels and when its not a compliance
11442          * test requesting 6bpc video pattern.
11443          */
11444         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11445                 !pipe_config->dither_force_disable;
11446         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11447                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11448
11449 fail:
11450         return ret;
11451 }
11452
11453 static void
11454 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11455 {
11456         struct drm_crtc *crtc;
11457         struct drm_crtc_state *new_crtc_state;
11458         int i;
11459
11460         /* Double check state. */
11461         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11462                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11463
11464                 /* Update hwmode for vblank functions */
11465                 if (new_crtc_state->active)
11466                         crtc->hwmode = new_crtc_state->adjusted_mode;
11467                 else
11468                         crtc->hwmode.crtc_clock = 0;
11469
11470                 /*
11471                  * Update legacy state to satisfy fbc code. This can
11472                  * be removed when fbc uses the atomic state.
11473                  */
11474                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11475                         struct drm_plane_state *plane_state = crtc->primary->state;
11476
11477                         crtc->primary->fb = plane_state->fb;
11478                         crtc->x = plane_state->src_x >> 16;
11479                         crtc->y = plane_state->src_y >> 16;
11480                 }
11481         }
11482 }
11483
11484 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11485 {
11486         int diff;
11487
11488         if (clock1 == clock2)
11489                 return true;
11490
11491         if (!clock1 || !clock2)
11492                 return false;
11493
11494         diff = abs(clock1 - clock2);
11495
11496         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11497                 return true;
11498
11499         return false;
11500 }
11501
11502 static bool
11503 intel_compare_m_n(unsigned int m, unsigned int n,
11504                   unsigned int m2, unsigned int n2,
11505                   bool exact)
11506 {
11507         if (m == m2 && n == n2)
11508                 return true;
11509
11510         if (exact || !m || !n || !m2 || !n2)
11511                 return false;
11512
11513         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11514
11515         if (n > n2) {
11516                 while (n > n2) {
11517                         m2 <<= 1;
11518                         n2 <<= 1;
11519                 }
11520         } else if (n < n2) {
11521                 while (n < n2) {
11522                         m <<= 1;
11523                         n <<= 1;
11524                 }
11525         }
11526
11527         if (n != n2)
11528                 return false;
11529
11530         return intel_fuzzy_clock_check(m, m2);
11531 }
11532
11533 static bool
11534 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11535                        struct intel_link_m_n *m2_n2,
11536                        bool adjust)
11537 {
11538         if (m_n->tu == m2_n2->tu &&
11539             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11540                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11541             intel_compare_m_n(m_n->link_m, m_n->link_n,
11542                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11543                 if (adjust)
11544                         *m2_n2 = *m_n;
11545
11546                 return true;
11547         }
11548
11549         return false;
11550 }
11551
11552 static void __printf(3, 4)
11553 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11554 {
11555         char *level;
11556         unsigned int category;
11557         struct va_format vaf;
11558         va_list args;
11559
11560         if (adjust) {
11561                 level = KERN_DEBUG;
11562                 category = DRM_UT_KMS;
11563         } else {
11564                 level = KERN_ERR;
11565                 category = DRM_UT_NONE;
11566         }
11567
11568         va_start(args, format);
11569         vaf.fmt = format;
11570         vaf.va = &args;
11571
11572         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11573
11574         va_end(args);
11575 }
11576
11577 static bool
11578 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11579                           struct intel_crtc_state *current_config,
11580                           struct intel_crtc_state *pipe_config,
11581                           bool adjust)
11582 {
11583         bool ret = true;
11584
11585 #define PIPE_CONF_CHECK_X(name) \
11586         if (current_config->name != pipe_config->name) { \
11587                 pipe_config_err(adjust, __stringify(name), \
11588                           "(expected 0x%08x, found 0x%08x)\n", \
11589                           current_config->name, \
11590                           pipe_config->name); \
11591                 ret = false; \
11592         }
11593
11594 #define PIPE_CONF_CHECK_I(name) \
11595         if (current_config->name != pipe_config->name) { \
11596                 pipe_config_err(adjust, __stringify(name), \
11597                           "(expected %i, found %i)\n", \
11598                           current_config->name, \
11599                           pipe_config->name); \
11600                 ret = false; \
11601         }
11602
11603 #define PIPE_CONF_CHECK_P(name) \
11604         if (current_config->name != pipe_config->name) { \
11605                 pipe_config_err(adjust, __stringify(name), \
11606                           "(expected %p, found %p)\n", \
11607                           current_config->name, \
11608                           pipe_config->name); \
11609                 ret = false; \
11610         }
11611
11612 #define PIPE_CONF_CHECK_M_N(name) \
11613         if (!intel_compare_link_m_n(&current_config->name, \
11614                                     &pipe_config->name,\
11615                                     adjust)) { \
11616                 pipe_config_err(adjust, __stringify(name), \
11617                           "(expected tu %i gmch %i/%i link %i/%i, " \
11618                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11619                           current_config->name.tu, \
11620                           current_config->name.gmch_m, \
11621                           current_config->name.gmch_n, \
11622                           current_config->name.link_m, \
11623                           current_config->name.link_n, \
11624                           pipe_config->name.tu, \
11625                           pipe_config->name.gmch_m, \
11626                           pipe_config->name.gmch_n, \
11627                           pipe_config->name.link_m, \
11628                           pipe_config->name.link_n); \
11629                 ret = false; \
11630         }
11631
11632 /* This is required for BDW+ where there is only one set of registers for
11633  * switching between high and low RR.
11634  * This macro can be used whenever a comparison has to be made between one
11635  * hw state and multiple sw state variables.
11636  */
11637 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11638         if (!intel_compare_link_m_n(&current_config->name, \
11639                                     &pipe_config->name, adjust) && \
11640             !intel_compare_link_m_n(&current_config->alt_name, \
11641                                     &pipe_config->name, adjust)) { \
11642                 pipe_config_err(adjust, __stringify(name), \
11643                           "(expected tu %i gmch %i/%i link %i/%i, " \
11644                           "or tu %i gmch %i/%i link %i/%i, " \
11645                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11646                           current_config->name.tu, \
11647                           current_config->name.gmch_m, \
11648                           current_config->name.gmch_n, \
11649                           current_config->name.link_m, \
11650                           current_config->name.link_n, \
11651                           current_config->alt_name.tu, \
11652                           current_config->alt_name.gmch_m, \
11653                           current_config->alt_name.gmch_n, \
11654                           current_config->alt_name.link_m, \
11655                           current_config->alt_name.link_n, \
11656                           pipe_config->name.tu, \
11657                           pipe_config->name.gmch_m, \
11658                           pipe_config->name.gmch_n, \
11659                           pipe_config->name.link_m, \
11660                           pipe_config->name.link_n); \
11661                 ret = false; \
11662         }
11663
11664 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11665         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11666                 pipe_config_err(adjust, __stringify(name), \
11667                           "(%x) (expected %i, found %i)\n", \
11668                           (mask), \
11669                           current_config->name & (mask), \
11670                           pipe_config->name & (mask)); \
11671                 ret = false; \
11672         }
11673
11674 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11675         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11676                 pipe_config_err(adjust, __stringify(name), \
11677                           "(expected %i, found %i)\n", \
11678                           current_config->name, \
11679                           pipe_config->name); \
11680                 ret = false; \
11681         }
11682
11683 #define PIPE_CONF_QUIRK(quirk)  \
11684         ((current_config->quirks | pipe_config->quirks) & (quirk))
11685
11686         PIPE_CONF_CHECK_I(cpu_transcoder);
11687
11688         PIPE_CONF_CHECK_I(has_pch_encoder);
11689         PIPE_CONF_CHECK_I(fdi_lanes);
11690         PIPE_CONF_CHECK_M_N(fdi_m_n);
11691
11692         PIPE_CONF_CHECK_I(lane_count);
11693         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11694
11695         if (INTEL_GEN(dev_priv) < 8) {
11696                 PIPE_CONF_CHECK_M_N(dp_m_n);
11697
11698                 if (current_config->has_drrs)
11699                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11700         } else
11701                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11702
11703         PIPE_CONF_CHECK_X(output_types);
11704
11705         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11706         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11707         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11708         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11709         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11710         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11711
11712         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11713         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11714         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11715         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11716         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11717         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11718
11719         PIPE_CONF_CHECK_I(pixel_multiplier);
11720         PIPE_CONF_CHECK_I(has_hdmi_sink);
11721         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11722             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11723                 PIPE_CONF_CHECK_I(limited_color_range);
11724
11725         PIPE_CONF_CHECK_I(hdmi_scrambling);
11726         PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11727         PIPE_CONF_CHECK_I(has_infoframe);
11728
11729         PIPE_CONF_CHECK_I(has_audio);
11730
11731         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11732                               DRM_MODE_FLAG_INTERLACE);
11733
11734         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11735                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11736                                       DRM_MODE_FLAG_PHSYNC);
11737                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11738                                       DRM_MODE_FLAG_NHSYNC);
11739                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11740                                       DRM_MODE_FLAG_PVSYNC);
11741                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11742                                       DRM_MODE_FLAG_NVSYNC);
11743         }
11744
11745         PIPE_CONF_CHECK_X(gmch_pfit.control);
11746         /* pfit ratios are autocomputed by the hw on gen4+ */
11747         if (INTEL_GEN(dev_priv) < 4)
11748                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11749         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11750
11751         if (!adjust) {
11752                 PIPE_CONF_CHECK_I(pipe_src_w);
11753                 PIPE_CONF_CHECK_I(pipe_src_h);
11754
11755                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11756                 if (current_config->pch_pfit.enabled) {
11757                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11758                         PIPE_CONF_CHECK_X(pch_pfit.size);
11759                 }
11760
11761                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11762                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11763         }
11764
11765         /* BDW+ don't expose a synchronous way to read the state */
11766         if (IS_HASWELL(dev_priv))
11767                 PIPE_CONF_CHECK_I(ips_enabled);
11768
11769         PIPE_CONF_CHECK_I(double_wide);
11770
11771         PIPE_CONF_CHECK_P(shared_dpll);
11772         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11773         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11774         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11775         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11776         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11777         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11778         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11779         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11780         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11781
11782         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11783         PIPE_CONF_CHECK_X(dsi_pll.div);
11784
11785         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11786                 PIPE_CONF_CHECK_I(pipe_bpp);
11787
11788         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11789         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11790
11791 #undef PIPE_CONF_CHECK_X
11792 #undef PIPE_CONF_CHECK_I
11793 #undef PIPE_CONF_CHECK_P
11794 #undef PIPE_CONF_CHECK_FLAGS
11795 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11796 #undef PIPE_CONF_QUIRK
11797
11798         return ret;
11799 }
11800
11801 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11802                                            const struct intel_crtc_state *pipe_config)
11803 {
11804         if (pipe_config->has_pch_encoder) {
11805                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11806                                                             &pipe_config->fdi_m_n);
11807                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11808
11809                 /*
11810                  * FDI already provided one idea for the dotclock.
11811                  * Yell if the encoder disagrees.
11812                  */
11813                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11814                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11815                      fdi_dotclock, dotclock);
11816         }
11817 }
11818
11819 static void verify_wm_state(struct drm_crtc *crtc,
11820                             struct drm_crtc_state *new_state)
11821 {
11822         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11823         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11824         struct skl_pipe_wm hw_wm, *sw_wm;
11825         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11826         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11828         const enum pipe pipe = intel_crtc->pipe;
11829         int plane, level, max_level = ilk_wm_max_level(dev_priv);
11830
11831         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11832                 return;
11833
11834         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11835         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11836
11837         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11838         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11839
11840         /* planes */
11841         for_each_universal_plane(dev_priv, pipe, plane) {
11842                 hw_plane_wm = &hw_wm.planes[plane];
11843                 sw_plane_wm = &sw_wm->planes[plane];
11844
11845                 /* Watermarks */
11846                 for (level = 0; level <= max_level; level++) {
11847                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11848                                                 &sw_plane_wm->wm[level]))
11849                                 continue;
11850
11851                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11852                                   pipe_name(pipe), plane + 1, level,
11853                                   sw_plane_wm->wm[level].plane_en,
11854                                   sw_plane_wm->wm[level].plane_res_b,
11855                                   sw_plane_wm->wm[level].plane_res_l,
11856                                   hw_plane_wm->wm[level].plane_en,
11857                                   hw_plane_wm->wm[level].plane_res_b,
11858                                   hw_plane_wm->wm[level].plane_res_l);
11859                 }
11860
11861                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11862                                          &sw_plane_wm->trans_wm)) {
11863                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11864                                   pipe_name(pipe), plane + 1,
11865                                   sw_plane_wm->trans_wm.plane_en,
11866                                   sw_plane_wm->trans_wm.plane_res_b,
11867                                   sw_plane_wm->trans_wm.plane_res_l,
11868                                   hw_plane_wm->trans_wm.plane_en,
11869                                   hw_plane_wm->trans_wm.plane_res_b,
11870                                   hw_plane_wm->trans_wm.plane_res_l);
11871                 }
11872
11873                 /* DDB */
11874                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11875                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11876
11877                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11878                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11879                                   pipe_name(pipe), plane + 1,
11880                                   sw_ddb_entry->start, sw_ddb_entry->end,
11881                                   hw_ddb_entry->start, hw_ddb_entry->end);
11882                 }
11883         }
11884
11885         /*
11886          * cursor
11887          * If the cursor plane isn't active, we may not have updated it's ddb
11888          * allocation. In that case since the ddb allocation will be updated
11889          * once the plane becomes visible, we can skip this check
11890          */
11891         if (intel_crtc->cursor_addr) {
11892                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11893                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11894
11895                 /* Watermarks */
11896                 for (level = 0; level <= max_level; level++) {
11897                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11898                                                 &sw_plane_wm->wm[level]))
11899                                 continue;
11900
11901                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11902                                   pipe_name(pipe), level,
11903                                   sw_plane_wm->wm[level].plane_en,
11904                                   sw_plane_wm->wm[level].plane_res_b,
11905                                   sw_plane_wm->wm[level].plane_res_l,
11906                                   hw_plane_wm->wm[level].plane_en,
11907                                   hw_plane_wm->wm[level].plane_res_b,
11908                                   hw_plane_wm->wm[level].plane_res_l);
11909                 }
11910
11911                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11912                                          &sw_plane_wm->trans_wm)) {
11913                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11914                                   pipe_name(pipe),
11915                                   sw_plane_wm->trans_wm.plane_en,
11916                                   sw_plane_wm->trans_wm.plane_res_b,
11917                                   sw_plane_wm->trans_wm.plane_res_l,
11918                                   hw_plane_wm->trans_wm.plane_en,
11919                                   hw_plane_wm->trans_wm.plane_res_b,
11920                                   hw_plane_wm->trans_wm.plane_res_l);
11921                 }
11922
11923                 /* DDB */
11924                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11925                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11926
11927                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11928                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11929                                   pipe_name(pipe),
11930                                   sw_ddb_entry->start, sw_ddb_entry->end,
11931                                   hw_ddb_entry->start, hw_ddb_entry->end);
11932                 }
11933         }
11934 }
11935
11936 static void
11937 verify_connector_state(struct drm_device *dev,
11938                        struct drm_atomic_state *state,
11939                        struct drm_crtc *crtc)
11940 {
11941         struct drm_connector *connector;
11942         struct drm_connector_state *new_conn_state;
11943         int i;
11944
11945         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11946                 struct drm_encoder *encoder = connector->encoder;
11947
11948                 if (new_conn_state->crtc != crtc)
11949                         continue;
11950
11951                 intel_connector_verify_state(to_intel_connector(connector));
11952
11953                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11954                      "connector's atomic encoder doesn't match legacy encoder\n");
11955         }
11956 }
11957
11958 static void
11959 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11960 {
11961         struct intel_encoder *encoder;
11962         struct drm_connector *connector;
11963         struct drm_connector_state *old_conn_state, *new_conn_state;
11964         int i;
11965
11966         for_each_intel_encoder(dev, encoder) {
11967                 bool enabled = false, found = false;
11968                 enum pipe pipe;
11969
11970                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11971                               encoder->base.base.id,
11972                               encoder->base.name);
11973
11974                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11975                                                    new_conn_state, i) {
11976                         if (old_conn_state->best_encoder == &encoder->base)
11977                                 found = true;
11978
11979                         if (new_conn_state->best_encoder != &encoder->base)
11980                                 continue;
11981                         found = enabled = true;
11982
11983                         I915_STATE_WARN(new_conn_state->crtc !=
11984                                         encoder->base.crtc,
11985                              "connector's crtc doesn't match encoder crtc\n");
11986                 }
11987
11988                 if (!found)
11989                         continue;
11990
11991                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11992                      "encoder's enabled state mismatch "
11993                      "(expected %i, found %i)\n",
11994                      !!encoder->base.crtc, enabled);
11995
11996                 if (!encoder->base.crtc) {
11997                         bool active;
11998
11999                         active = encoder->get_hw_state(encoder, &pipe);
12000                         I915_STATE_WARN(active,
12001                              "encoder detached but still enabled on pipe %c.\n",
12002                              pipe_name(pipe));
12003                 }
12004         }
12005 }
12006
12007 static void
12008 verify_crtc_state(struct drm_crtc *crtc,
12009                   struct drm_crtc_state *old_crtc_state,
12010                   struct drm_crtc_state *new_crtc_state)
12011 {
12012         struct drm_device *dev = crtc->dev;
12013         struct drm_i915_private *dev_priv = to_i915(dev);
12014         struct intel_encoder *encoder;
12015         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12016         struct intel_crtc_state *pipe_config, *sw_config;
12017         struct drm_atomic_state *old_state;
12018         bool active;
12019
12020         old_state = old_crtc_state->state;
12021         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12022         pipe_config = to_intel_crtc_state(old_crtc_state);
12023         memset(pipe_config, 0, sizeof(*pipe_config));
12024         pipe_config->base.crtc = crtc;
12025         pipe_config->base.state = old_state;
12026
12027         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12028
12029         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12030
12031         /* hw state is inconsistent with the pipe quirk */
12032         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12033             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12034                 active = new_crtc_state->active;
12035
12036         I915_STATE_WARN(new_crtc_state->active != active,
12037              "crtc active state doesn't match with hw state "
12038              "(expected %i, found %i)\n", new_crtc_state->active, active);
12039
12040         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12041              "transitional active state does not match atomic hw state "
12042              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12043
12044         for_each_encoder_on_crtc(dev, crtc, encoder) {
12045                 enum pipe pipe;
12046
12047                 active = encoder->get_hw_state(encoder, &pipe);
12048                 I915_STATE_WARN(active != new_crtc_state->active,
12049                         "[ENCODER:%i] active %i with crtc active %i\n",
12050                         encoder->base.base.id, active, new_crtc_state->active);
12051
12052                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12053                                 "Encoder connected to wrong pipe %c\n",
12054                                 pipe_name(pipe));
12055
12056                 if (active) {
12057                         pipe_config->output_types |= 1 << encoder->type;
12058                         encoder->get_config(encoder, pipe_config);
12059                 }
12060         }
12061
12062         intel_crtc_compute_pixel_rate(pipe_config);
12063
12064         if (!new_crtc_state->active)
12065                 return;
12066
12067         intel_pipe_config_sanity_check(dev_priv, pipe_config);
12068
12069         sw_config = to_intel_crtc_state(crtc->state);
12070         if (!intel_pipe_config_compare(dev_priv, sw_config,
12071                                        pipe_config, false)) {
12072                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12073                 intel_dump_pipe_config(intel_crtc, pipe_config,
12074                                        "[hw state]");
12075                 intel_dump_pipe_config(intel_crtc, sw_config,
12076                                        "[sw state]");
12077         }
12078 }
12079
12080 static void
12081 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12082                          struct intel_shared_dpll *pll,
12083                          struct drm_crtc *crtc,
12084                          struct drm_crtc_state *new_state)
12085 {
12086         struct intel_dpll_hw_state dpll_hw_state;
12087         unsigned crtc_mask;
12088         bool active;
12089
12090         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12091
12092         DRM_DEBUG_KMS("%s\n", pll->name);
12093
12094         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12095
12096         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12097                 I915_STATE_WARN(!pll->on && pll->active_mask,
12098                      "pll in active use but not on in sw tracking\n");
12099                 I915_STATE_WARN(pll->on && !pll->active_mask,
12100                      "pll is on but not used by any active crtc\n");
12101                 I915_STATE_WARN(pll->on != active,
12102                      "pll on state mismatch (expected %i, found %i)\n",
12103                      pll->on, active);
12104         }
12105
12106         if (!crtc) {
12107                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12108                                 "more active pll users than references: %x vs %x\n",
12109                                 pll->active_mask, pll->state.crtc_mask);
12110
12111                 return;
12112         }
12113
12114         crtc_mask = 1 << drm_crtc_index(crtc);
12115
12116         if (new_state->active)
12117                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12118                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12119                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12120         else
12121                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12122                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12123                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12124
12125         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12126                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12127                         crtc_mask, pll->state.crtc_mask);
12128
12129         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12130                                           &dpll_hw_state,
12131                                           sizeof(dpll_hw_state)),
12132                         "pll hw state mismatch\n");
12133 }
12134
12135 static void
12136 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12137                          struct drm_crtc_state *old_crtc_state,
12138                          struct drm_crtc_state *new_crtc_state)
12139 {
12140         struct drm_i915_private *dev_priv = to_i915(dev);
12141         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12142         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12143
12144         if (new_state->shared_dpll)
12145                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12146
12147         if (old_state->shared_dpll &&
12148             old_state->shared_dpll != new_state->shared_dpll) {
12149                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12150                 struct intel_shared_dpll *pll = old_state->shared_dpll;
12151
12152                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12153                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12154                                 pipe_name(drm_crtc_index(crtc)));
12155                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12156                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12157                                 pipe_name(drm_crtc_index(crtc)));
12158         }
12159 }
12160
12161 static void
12162 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12163                           struct drm_atomic_state *state,
12164                           struct drm_crtc_state *old_state,
12165                           struct drm_crtc_state *new_state)
12166 {
12167         if (!needs_modeset(new_state) &&
12168             !to_intel_crtc_state(new_state)->update_pipe)
12169                 return;
12170
12171         verify_wm_state(crtc, new_state);
12172         verify_connector_state(crtc->dev, state, crtc);
12173         verify_crtc_state(crtc, old_state, new_state);
12174         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12175 }
12176
12177 static void
12178 verify_disabled_dpll_state(struct drm_device *dev)
12179 {
12180         struct drm_i915_private *dev_priv = to_i915(dev);
12181         int i;
12182
12183         for (i = 0; i < dev_priv->num_shared_dpll; i++)
12184                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12185 }
12186
12187 static void
12188 intel_modeset_verify_disabled(struct drm_device *dev,
12189                               struct drm_atomic_state *state)
12190 {
12191         verify_encoder_state(dev, state);
12192         verify_connector_state(dev, state, NULL);
12193         verify_disabled_dpll_state(dev);
12194 }
12195
12196 static void update_scanline_offset(struct intel_crtc *crtc)
12197 {
12198         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12199
12200         /*
12201          * The scanline counter increments at the leading edge of hsync.
12202          *
12203          * On most platforms it starts counting from vtotal-1 on the
12204          * first active line. That means the scanline counter value is
12205          * always one less than what we would expect. Ie. just after
12206          * start of vblank, which also occurs at start of hsync (on the
12207          * last active line), the scanline counter will read vblank_start-1.
12208          *
12209          * On gen2 the scanline counter starts counting from 1 instead
12210          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12211          * to keep the value positive), instead of adding one.
12212          *
12213          * On HSW+ the behaviour of the scanline counter depends on the output
12214          * type. For DP ports it behaves like most other platforms, but on HDMI
12215          * there's an extra 1 line difference. So we need to add two instead of
12216          * one to the value.
12217          */
12218         if (IS_GEN2(dev_priv)) {
12219                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12220                 int vtotal;
12221
12222                 vtotal = adjusted_mode->crtc_vtotal;
12223                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12224                         vtotal /= 2;
12225
12226                 crtc->scanline_offset = vtotal - 1;
12227         } else if (HAS_DDI(dev_priv) &&
12228                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12229                 crtc->scanline_offset = 2;
12230         } else
12231                 crtc->scanline_offset = 1;
12232 }
12233
12234 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12235 {
12236         struct drm_device *dev = state->dev;
12237         struct drm_i915_private *dev_priv = to_i915(dev);
12238         struct drm_crtc *crtc;
12239         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12240         int i;
12241
12242         if (!dev_priv->display.crtc_compute_clock)
12243                 return;
12244
12245         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12246                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12247                 struct intel_shared_dpll *old_dpll =
12248                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
12249
12250                 if (!needs_modeset(new_crtc_state))
12251                         continue;
12252
12253                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12254
12255                 if (!old_dpll)
12256                         continue;
12257
12258                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12259         }
12260 }
12261
12262 /*
12263  * This implements the workaround described in the "notes" section of the mode
12264  * set sequence documentation. When going from no pipes or single pipe to
12265  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12266  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12267  */
12268 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12269 {
12270         struct drm_crtc_state *crtc_state;
12271         struct intel_crtc *intel_crtc;
12272         struct drm_crtc *crtc;
12273         struct intel_crtc_state *first_crtc_state = NULL;
12274         struct intel_crtc_state *other_crtc_state = NULL;
12275         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12276         int i;
12277
12278         /* look at all crtc's that are going to be enabled in during modeset */
12279         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12280                 intel_crtc = to_intel_crtc(crtc);
12281
12282                 if (!crtc_state->active || !needs_modeset(crtc_state))
12283                         continue;
12284
12285                 if (first_crtc_state) {
12286                         other_crtc_state = to_intel_crtc_state(crtc_state);
12287                         break;
12288                 } else {
12289                         first_crtc_state = to_intel_crtc_state(crtc_state);
12290                         first_pipe = intel_crtc->pipe;
12291                 }
12292         }
12293
12294         /* No workaround needed? */
12295         if (!first_crtc_state)
12296                 return 0;
12297
12298         /* w/a possibly needed, check how many crtc's are already enabled. */
12299         for_each_intel_crtc(state->dev, intel_crtc) {
12300                 struct intel_crtc_state *pipe_config;
12301
12302                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12303                 if (IS_ERR(pipe_config))
12304                         return PTR_ERR(pipe_config);
12305
12306                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12307
12308                 if (!pipe_config->base.active ||
12309                     needs_modeset(&pipe_config->base))
12310                         continue;
12311
12312                 /* 2 or more enabled crtcs means no need for w/a */
12313                 if (enabled_pipe != INVALID_PIPE)
12314                         return 0;
12315
12316                 enabled_pipe = intel_crtc->pipe;
12317         }
12318
12319         if (enabled_pipe != INVALID_PIPE)
12320                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12321         else if (other_crtc_state)
12322                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12323
12324         return 0;
12325 }
12326
12327 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12328 {
12329         struct drm_crtc *crtc;
12330
12331         /* Add all pipes to the state */
12332         for_each_crtc(state->dev, crtc) {
12333                 struct drm_crtc_state *crtc_state;
12334
12335                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12336                 if (IS_ERR(crtc_state))
12337                         return PTR_ERR(crtc_state);
12338         }
12339
12340         return 0;
12341 }
12342
12343 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12344 {
12345         struct drm_crtc *crtc;
12346
12347         /*
12348          * Add all pipes to the state, and force
12349          * a modeset on all the active ones.
12350          */
12351         for_each_crtc(state->dev, crtc) {
12352                 struct drm_crtc_state *crtc_state;
12353                 int ret;
12354
12355                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12356                 if (IS_ERR(crtc_state))
12357                         return PTR_ERR(crtc_state);
12358
12359                 if (!crtc_state->active || needs_modeset(crtc_state))
12360                         continue;
12361
12362                 crtc_state->mode_changed = true;
12363
12364                 ret = drm_atomic_add_affected_connectors(state, crtc);
12365                 if (ret)
12366                         return ret;
12367
12368                 ret = drm_atomic_add_affected_planes(state, crtc);
12369                 if (ret)
12370                         return ret;
12371         }
12372
12373         return 0;
12374 }
12375
12376 static int intel_modeset_checks(struct drm_atomic_state *state)
12377 {
12378         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12379         struct drm_i915_private *dev_priv = to_i915(state->dev);
12380         struct drm_crtc *crtc;
12381         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12382         int ret = 0, i;
12383
12384         if (!check_digital_port_conflicts(state)) {
12385                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12386                 return -EINVAL;
12387         }
12388
12389         intel_state->modeset = true;
12390         intel_state->active_crtcs = dev_priv->active_crtcs;
12391         intel_state->cdclk.logical = dev_priv->cdclk.logical;
12392         intel_state->cdclk.actual = dev_priv->cdclk.actual;
12393
12394         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12395                 if (new_crtc_state->active)
12396                         intel_state->active_crtcs |= 1 << i;
12397                 else
12398                         intel_state->active_crtcs &= ~(1 << i);
12399
12400                 if (old_crtc_state->active != new_crtc_state->active)
12401                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12402         }
12403
12404         /*
12405          * See if the config requires any additional preparation, e.g.
12406          * to adjust global state with pipes off.  We need to do this
12407          * here so we can get the modeset_pipe updated config for the new
12408          * mode set on this crtc.  For other crtcs we need to use the
12409          * adjusted_mode bits in the crtc directly.
12410          */
12411         if (dev_priv->display.modeset_calc_cdclk) {
12412                 ret = dev_priv->display.modeset_calc_cdclk(state);
12413                 if (ret < 0)
12414                         return ret;
12415
12416                 /*
12417                  * Writes to dev_priv->cdclk.logical must protected by
12418                  * holding all the crtc locks, even if we don't end up
12419                  * touching the hardware
12420                  */
12421                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12422                                                &intel_state->cdclk.logical)) {
12423                         ret = intel_lock_all_pipes(state);
12424                         if (ret < 0)
12425                                 return ret;
12426                 }
12427
12428                 /* All pipes must be switched off while we change the cdclk. */
12429                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12430                                                &intel_state->cdclk.actual)) {
12431                         ret = intel_modeset_all_pipes(state);
12432                         if (ret < 0)
12433                                 return ret;
12434                 }
12435
12436                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12437                               intel_state->cdclk.logical.cdclk,
12438                               intel_state->cdclk.actual.cdclk);
12439         } else {
12440                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12441         }
12442
12443         intel_modeset_clear_plls(state);
12444
12445         if (IS_HASWELL(dev_priv))
12446                 return haswell_mode_set_planes_workaround(state);
12447
12448         return 0;
12449 }
12450
12451 /*
12452  * Handle calculation of various watermark data at the end of the atomic check
12453  * phase.  The code here should be run after the per-crtc and per-plane 'check'
12454  * handlers to ensure that all derived state has been updated.
12455  */
12456 static int calc_watermark_data(struct drm_atomic_state *state)
12457 {
12458         struct drm_device *dev = state->dev;
12459         struct drm_i915_private *dev_priv = to_i915(dev);
12460
12461         /* Is there platform-specific watermark information to calculate? */
12462         if (dev_priv->display.compute_global_watermarks)
12463                 return dev_priv->display.compute_global_watermarks(state);
12464
12465         return 0;
12466 }
12467
12468 /**
12469  * intel_atomic_check - validate state object
12470  * @dev: drm device
12471  * @state: state to validate
12472  */
12473 static int intel_atomic_check(struct drm_device *dev,
12474                               struct drm_atomic_state *state)
12475 {
12476         struct drm_i915_private *dev_priv = to_i915(dev);
12477         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12478         struct drm_crtc *crtc;
12479         struct drm_crtc_state *old_crtc_state, *crtc_state;
12480         int ret, i;
12481         bool any_ms = false;
12482
12483         ret = drm_atomic_helper_check_modeset(dev, state);
12484         if (ret)
12485                 return ret;
12486
12487         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12488                 struct intel_crtc_state *pipe_config =
12489                         to_intel_crtc_state(crtc_state);
12490
12491                 /* Catch I915_MODE_FLAG_INHERITED */
12492                 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12493                         crtc_state->mode_changed = true;
12494
12495                 if (!needs_modeset(crtc_state))
12496                         continue;
12497
12498                 if (!crtc_state->enable) {
12499                         any_ms = true;
12500                         continue;
12501                 }
12502
12503                 /* FIXME: For only active_changed we shouldn't need to do any
12504                  * state recomputation at all. */
12505
12506                 ret = drm_atomic_add_affected_connectors(state, crtc);
12507                 if (ret)
12508                         return ret;
12509
12510                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12511                 if (ret) {
12512                         intel_dump_pipe_config(to_intel_crtc(crtc),
12513                                                pipe_config, "[failed]");
12514                         return ret;
12515                 }
12516
12517                 if (i915.fastboot &&
12518                     intel_pipe_config_compare(dev_priv,
12519                                         to_intel_crtc_state(old_crtc_state),
12520                                         pipe_config, true)) {
12521                         crtc_state->mode_changed = false;
12522                         pipe_config->update_pipe = true;
12523                 }
12524
12525                 if (needs_modeset(crtc_state))
12526                         any_ms = true;
12527
12528                 ret = drm_atomic_add_affected_planes(state, crtc);
12529                 if (ret)
12530                         return ret;
12531
12532                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12533                                        needs_modeset(crtc_state) ?
12534                                        "[modeset]" : "[fastset]");
12535         }
12536
12537         if (any_ms) {
12538                 ret = intel_modeset_checks(state);
12539
12540                 if (ret)
12541                         return ret;
12542         } else {
12543                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12544         }
12545
12546         ret = drm_atomic_helper_check_planes(dev, state);
12547         if (ret)
12548                 return ret;
12549
12550         intel_fbc_choose_crtc(dev_priv, state);
12551         return calc_watermark_data(state);
12552 }
12553
12554 static int intel_atomic_prepare_commit(struct drm_device *dev,
12555                                        struct drm_atomic_state *state)
12556 {
12557         struct drm_i915_private *dev_priv = to_i915(dev);
12558         struct drm_crtc_state *crtc_state;
12559         struct drm_crtc *crtc;
12560         int i, ret;
12561
12562         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12563                 if (state->legacy_cursor_update)
12564                         continue;
12565
12566                 ret = intel_crtc_wait_for_pending_flips(crtc);
12567                 if (ret)
12568                         return ret;
12569
12570                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12571                         flush_workqueue(dev_priv->wq);
12572         }
12573
12574         ret = mutex_lock_interruptible(&dev->struct_mutex);
12575         if (ret)
12576                 return ret;
12577
12578         ret = drm_atomic_helper_prepare_planes(dev, state);
12579         mutex_unlock(&dev->struct_mutex);
12580
12581         return ret;
12582 }
12583
12584 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12585 {
12586         struct drm_device *dev = crtc->base.dev;
12587
12588         if (!dev->max_vblank_count)
12589                 return drm_accurate_vblank_count(&crtc->base);
12590
12591         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12592 }
12593
12594 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12595                                           struct drm_i915_private *dev_priv,
12596                                           unsigned crtc_mask)
12597 {
12598         unsigned last_vblank_count[I915_MAX_PIPES];
12599         enum pipe pipe;
12600         int ret;
12601
12602         if (!crtc_mask)
12603                 return;
12604
12605         for_each_pipe(dev_priv, pipe) {
12606                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12607                                                                   pipe);
12608
12609                 if (!((1 << pipe) & crtc_mask))
12610                         continue;
12611
12612                 ret = drm_crtc_vblank_get(&crtc->base);
12613                 if (WARN_ON(ret != 0)) {
12614                         crtc_mask &= ~(1 << pipe);
12615                         continue;
12616                 }
12617
12618                 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12619         }
12620
12621         for_each_pipe(dev_priv, pipe) {
12622                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12623                                                                   pipe);
12624                 long lret;
12625
12626                 if (!((1 << pipe) & crtc_mask))
12627                         continue;
12628
12629                 lret = wait_event_timeout(dev->vblank[pipe].queue,
12630                                 last_vblank_count[pipe] !=
12631                                         drm_crtc_vblank_count(&crtc->base),
12632                                 msecs_to_jiffies(50));
12633
12634                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12635
12636                 drm_crtc_vblank_put(&crtc->base);
12637         }
12638 }
12639
12640 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12641 {
12642         /* fb updated, need to unpin old fb */
12643         if (crtc_state->fb_changed)
12644                 return true;
12645
12646         /* wm changes, need vblank before final wm's */
12647         if (crtc_state->update_wm_post)
12648                 return true;
12649
12650         if (crtc_state->wm.need_postvbl_update)
12651                 return true;
12652
12653         return false;
12654 }
12655
12656 static void intel_update_crtc(struct drm_crtc *crtc,
12657                               struct drm_atomic_state *state,
12658                               struct drm_crtc_state *old_crtc_state,
12659                               struct drm_crtc_state *new_crtc_state,
12660                               unsigned int *crtc_vblank_mask)
12661 {
12662         struct drm_device *dev = crtc->dev;
12663         struct drm_i915_private *dev_priv = to_i915(dev);
12664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12665         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12666         bool modeset = needs_modeset(new_crtc_state);
12667
12668         if (modeset) {
12669                 update_scanline_offset(intel_crtc);
12670                 dev_priv->display.crtc_enable(pipe_config, state);
12671         } else {
12672                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12673                                        pipe_config);
12674         }
12675
12676         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12677                 intel_fbc_enable(
12678                     intel_crtc, pipe_config,
12679                     to_intel_plane_state(crtc->primary->state));
12680         }
12681
12682         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12683
12684         if (needs_vblank_wait(pipe_config))
12685                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12686 }
12687
12688 static void intel_update_crtcs(struct drm_atomic_state *state,
12689                                unsigned int *crtc_vblank_mask)
12690 {
12691         struct drm_crtc *crtc;
12692         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12693         int i;
12694
12695         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12696                 if (!new_crtc_state->active)
12697                         continue;
12698
12699                 intel_update_crtc(crtc, state, old_crtc_state,
12700                                   new_crtc_state, crtc_vblank_mask);
12701         }
12702 }
12703
12704 static void skl_update_crtcs(struct drm_atomic_state *state,
12705                              unsigned int *crtc_vblank_mask)
12706 {
12707         struct drm_i915_private *dev_priv = to_i915(state->dev);
12708         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12709         struct drm_crtc *crtc;
12710         struct intel_crtc *intel_crtc;
12711         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12712         struct intel_crtc_state *cstate;
12713         unsigned int updated = 0;
12714         bool progress;
12715         enum pipe pipe;
12716         int i;
12717
12718         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12719
12720         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12721                 /* ignore allocations for crtc's that have been turned off. */
12722                 if (new_crtc_state->active)
12723                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12724
12725         /*
12726          * Whenever the number of active pipes changes, we need to make sure we
12727          * update the pipes in the right order so that their ddb allocations
12728          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12729          * cause pipe underruns and other bad stuff.
12730          */
12731         do {
12732                 progress = false;
12733
12734                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12735                         bool vbl_wait = false;
12736                         unsigned int cmask = drm_crtc_mask(crtc);
12737
12738                         intel_crtc = to_intel_crtc(crtc);
12739                         cstate = to_intel_crtc_state(crtc->state);
12740                         pipe = intel_crtc->pipe;
12741
12742                         if (updated & cmask || !cstate->base.active)
12743                                 continue;
12744
12745                         if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12746                                 continue;
12747
12748                         updated |= cmask;
12749                         entries[i] = &cstate->wm.skl.ddb;
12750
12751                         /*
12752                          * If this is an already active pipe, it's DDB changed,
12753                          * and this isn't the last pipe that needs updating
12754                          * then we need to wait for a vblank to pass for the
12755                          * new ddb allocation to take effect.
12756                          */
12757                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12758                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12759                             !new_crtc_state->active_changed &&
12760                             intel_state->wm_results.dirty_pipes != updated)
12761                                 vbl_wait = true;
12762
12763                         intel_update_crtc(crtc, state, old_crtc_state,
12764                                           new_crtc_state, crtc_vblank_mask);
12765
12766                         if (vbl_wait)
12767                                 intel_wait_for_vblank(dev_priv, pipe);
12768
12769                         progress = true;
12770                 }
12771         } while (progress);
12772 }
12773
12774 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12775 {
12776         struct intel_atomic_state *state, *next;
12777         struct llist_node *freed;
12778
12779         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12780         llist_for_each_entry_safe(state, next, freed, freed)
12781                 drm_atomic_state_put(&state->base);
12782 }
12783
12784 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12785 {
12786         struct drm_i915_private *dev_priv =
12787                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12788
12789         intel_atomic_helper_free_state(dev_priv);
12790 }
12791
12792 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12793 {
12794         struct drm_device *dev = state->dev;
12795         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12796         struct drm_i915_private *dev_priv = to_i915(dev);
12797         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12798         struct drm_crtc *crtc;
12799         struct intel_crtc_state *intel_cstate;
12800         bool hw_check = intel_state->modeset;
12801         u64 put_domains[I915_MAX_PIPES] = {};
12802         unsigned crtc_vblank_mask = 0;
12803         int i;
12804
12805         drm_atomic_helper_wait_for_dependencies(state);
12806
12807         if (intel_state->modeset)
12808                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12809
12810         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12811                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12812
12813                 if (needs_modeset(new_crtc_state) ||
12814                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
12815                         hw_check = true;
12816
12817                         put_domains[to_intel_crtc(crtc)->pipe] =
12818                                 modeset_get_crtc_power_domains(crtc,
12819                                         to_intel_crtc_state(new_crtc_state));
12820                 }
12821
12822                 if (!needs_modeset(new_crtc_state))
12823                         continue;
12824
12825                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12826                                        to_intel_crtc_state(new_crtc_state));
12827
12828                 if (old_crtc_state->active) {
12829                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12830                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12831                         intel_crtc->active = false;
12832                         intel_fbc_disable(intel_crtc);
12833                         intel_disable_shared_dpll(intel_crtc);
12834
12835                         /*
12836                          * Underruns don't always raise
12837                          * interrupts, so check manually.
12838                          */
12839                         intel_check_cpu_fifo_underruns(dev_priv);
12840                         intel_check_pch_fifo_underruns(dev_priv);
12841
12842                         if (!crtc->state->active) {
12843                                 /*
12844                                  * Make sure we don't call initial_watermarks
12845                                  * for ILK-style watermark updates.
12846                                  *
12847                                  * No clue what this is supposed to achieve.
12848                                  */
12849                                 if (INTEL_GEN(dev_priv) >= 9)
12850                                         dev_priv->display.initial_watermarks(intel_state,
12851                                                                              to_intel_crtc_state(crtc->state));
12852                         }
12853                 }
12854         }
12855
12856         /* Only after disabling all output pipelines that will be changed can we
12857          * update the the output configuration. */
12858         intel_modeset_update_crtc_state(state);
12859
12860         if (intel_state->modeset) {
12861                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12862
12863                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12864
12865                 /*
12866                  * SKL workaround: bspec recommends we disable the SAGV when we
12867                  * have more then one pipe enabled
12868                  */
12869                 if (!intel_can_enable_sagv(state))
12870                         intel_disable_sagv(dev_priv);
12871
12872                 intel_modeset_verify_disabled(dev, state);
12873         }
12874
12875         /* Complete the events for pipes that have now been disabled */
12876         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12877                 bool modeset = needs_modeset(new_crtc_state);
12878
12879                 /* Complete events for now disable pipes here. */
12880                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12881                         spin_lock_irq(&dev->event_lock);
12882                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12883                         spin_unlock_irq(&dev->event_lock);
12884
12885                         new_crtc_state->event = NULL;
12886                 }
12887         }
12888
12889         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12890         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12891
12892         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12893          * already, but still need the state for the delayed optimization. To
12894          * fix this:
12895          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12896          * - schedule that vblank worker _before_ calling hw_done
12897          * - at the start of commit_tail, cancel it _synchrously
12898          * - switch over to the vblank wait helper in the core after that since
12899          *   we don't need out special handling any more.
12900          */
12901         if (!state->legacy_cursor_update)
12902                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12903
12904         /*
12905          * Now that the vblank has passed, we can go ahead and program the
12906          * optimal watermarks on platforms that need two-step watermark
12907          * programming.
12908          *
12909          * TODO: Move this (and other cleanup) to an async worker eventually.
12910          */
12911         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12912                 intel_cstate = to_intel_crtc_state(new_crtc_state);
12913
12914                 if (dev_priv->display.optimize_watermarks)
12915                         dev_priv->display.optimize_watermarks(intel_state,
12916                                                               intel_cstate);
12917         }
12918
12919         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12920                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12921
12922                 if (put_domains[i])
12923                         modeset_put_power_domains(dev_priv, put_domains[i]);
12924
12925                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12926         }
12927
12928         if (intel_state->modeset && intel_can_enable_sagv(state))
12929                 intel_enable_sagv(dev_priv);
12930
12931         drm_atomic_helper_commit_hw_done(state);
12932
12933         if (intel_state->modeset)
12934                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12935
12936         mutex_lock(&dev->struct_mutex);
12937         drm_atomic_helper_cleanup_planes(dev, state);
12938         mutex_unlock(&dev->struct_mutex);
12939
12940         drm_atomic_helper_commit_cleanup_done(state);
12941
12942         drm_atomic_state_put(state);
12943
12944         /* As one of the primary mmio accessors, KMS has a high likelihood
12945          * of triggering bugs in unclaimed access. After we finish
12946          * modesetting, see if an error has been flagged, and if so
12947          * enable debugging for the next modeset - and hope we catch
12948          * the culprit.
12949          *
12950          * XXX note that we assume display power is on at this point.
12951          * This might hold true now but we need to add pm helper to check
12952          * unclaimed only when the hardware is on, as atomic commits
12953          * can happen also when the device is completely off.
12954          */
12955         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12956
12957         intel_atomic_helper_free_state(dev_priv);
12958 }
12959
12960 static void intel_atomic_commit_work(struct work_struct *work)
12961 {
12962         struct drm_atomic_state *state =
12963                 container_of(work, struct drm_atomic_state, commit_work);
12964
12965         intel_atomic_commit_tail(state);
12966 }
12967
12968 static int __i915_sw_fence_call
12969 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12970                           enum i915_sw_fence_notify notify)
12971 {
12972         struct intel_atomic_state *state =
12973                 container_of(fence, struct intel_atomic_state, commit_ready);
12974
12975         switch (notify) {
12976         case FENCE_COMPLETE:
12977                 if (state->base.commit_work.func)
12978                         queue_work(system_unbound_wq, &state->base.commit_work);
12979                 break;
12980
12981         case FENCE_FREE:
12982                 {
12983                         struct intel_atomic_helper *helper =
12984                                 &to_i915(state->base.dev)->atomic_helper;
12985
12986                         if (llist_add(&state->freed, &helper->free_list))
12987                                 schedule_work(&helper->free_work);
12988                         break;
12989                 }
12990         }
12991
12992         return NOTIFY_DONE;
12993 }
12994
12995 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12996 {
12997         struct drm_plane_state *old_plane_state, *new_plane_state;
12998         struct drm_plane *plane;
12999         int i;
13000
13001         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
13002                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13003                                   intel_fb_obj(new_plane_state->fb),
13004                                   to_intel_plane(plane)->frontbuffer_bit);
13005 }
13006
13007 /**
13008  * intel_atomic_commit - commit validated state object
13009  * @dev: DRM device
13010  * @state: the top-level driver state object
13011  * @nonblock: nonblocking commit
13012  *
13013  * This function commits a top-level state object that has been validated
13014  * with drm_atomic_helper_check().
13015  *
13016  * RETURNS
13017  * Zero for success or -errno.
13018  */
13019 static int intel_atomic_commit(struct drm_device *dev,
13020                                struct drm_atomic_state *state,
13021                                bool nonblock)
13022 {
13023         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13024         struct drm_i915_private *dev_priv = to_i915(dev);
13025         int ret = 0;
13026
13027         /*
13028          * The intel_legacy_cursor_update() fast path takes care
13029          * of avoiding the vblank waits for simple cursor
13030          * movement and flips. For cursor on/off and size changes,
13031          * we want to perform the vblank waits so that watermark
13032          * updates happen during the correct frames. Gen9+ have
13033          * double buffered watermarks and so shouldn't need this.
13034          */
13035         if (INTEL_GEN(dev_priv) < 9)
13036                 state->legacy_cursor_update = false;
13037
13038         ret = drm_atomic_helper_setup_commit(state, nonblock);
13039         if (ret)
13040                 return ret;
13041
13042         drm_atomic_state_get(state);
13043         i915_sw_fence_init(&intel_state->commit_ready,
13044                            intel_atomic_commit_ready);
13045
13046         ret = intel_atomic_prepare_commit(dev, state);
13047         if (ret) {
13048                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13049                 i915_sw_fence_commit(&intel_state->commit_ready);
13050                 return ret;
13051         }
13052
13053         drm_atomic_helper_swap_state(state, true);
13054         dev_priv->wm.distrust_bios_wm = false;
13055         intel_shared_dpll_swap_state(state);
13056         intel_atomic_track_fbs(state);
13057
13058         if (intel_state->modeset) {
13059                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13060                        sizeof(intel_state->min_pixclk));
13061                 dev_priv->active_crtcs = intel_state->active_crtcs;
13062                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13063                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13064         }
13065
13066         drm_atomic_state_get(state);
13067         INIT_WORK(&state->commit_work,
13068                   nonblock ? intel_atomic_commit_work : NULL);
13069
13070         i915_sw_fence_commit(&intel_state->commit_ready);
13071         if (!nonblock) {
13072                 i915_sw_fence_wait(&intel_state->commit_ready);
13073                 intel_atomic_commit_tail(state);
13074         }
13075
13076         return 0;
13077 }
13078
13079 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13080 {
13081         struct drm_device *dev = crtc->dev;
13082         struct drm_atomic_state *state;
13083         struct drm_crtc_state *crtc_state;
13084         int ret;
13085
13086         state = drm_atomic_state_alloc(dev);
13087         if (!state) {
13088                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13089                               crtc->base.id, crtc->name);
13090                 return;
13091         }
13092
13093         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13094
13095 retry:
13096         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13097         ret = PTR_ERR_OR_ZERO(crtc_state);
13098         if (!ret) {
13099                 if (!crtc_state->active)
13100                         goto out;
13101
13102                 crtc_state->mode_changed = true;
13103                 ret = drm_atomic_commit(state);
13104         }
13105
13106         if (ret == -EDEADLK) {
13107                 drm_atomic_state_clear(state);
13108                 drm_modeset_backoff(state->acquire_ctx);
13109                 goto retry;
13110         }
13111
13112 out:
13113         drm_atomic_state_put(state);
13114 }
13115
13116 /*
13117  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
13118  *        drm_atomic_helper_legacy_gamma_set() directly.
13119  */
13120 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
13121                                          u16 *red, u16 *green, u16 *blue,
13122                                          uint32_t size)
13123 {
13124         struct drm_device *dev = crtc->dev;
13125         struct drm_mode_config *config = &dev->mode_config;
13126         struct drm_crtc_state *state;
13127         int ret;
13128
13129         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
13130         if (ret)
13131                 return ret;
13132
13133         /*
13134          * Make sure we update the legacy properties so this works when
13135          * atomic is not enabled.
13136          */
13137
13138         state = crtc->state;
13139
13140         drm_object_property_set_value(&crtc->base,
13141                                       config->degamma_lut_property,
13142                                       (state->degamma_lut) ?
13143                                       state->degamma_lut->base.id : 0);
13144
13145         drm_object_property_set_value(&crtc->base,
13146                                       config->ctm_property,
13147                                       (state->ctm) ?
13148                                       state->ctm->base.id : 0);
13149
13150         drm_object_property_set_value(&crtc->base,
13151                                       config->gamma_lut_property,
13152                                       (state->gamma_lut) ?
13153                                       state->gamma_lut->base.id : 0);
13154
13155         return 0;
13156 }
13157
13158 static const struct drm_crtc_funcs intel_crtc_funcs = {
13159         .gamma_set = intel_atomic_legacy_gamma_set,
13160         .set_config = drm_atomic_helper_set_config,
13161         .set_property = drm_atomic_helper_crtc_set_property,
13162         .destroy = intel_crtc_destroy,
13163         .page_flip = drm_atomic_helper_page_flip,
13164         .atomic_duplicate_state = intel_crtc_duplicate_state,
13165         .atomic_destroy_state = intel_crtc_destroy_state,
13166         .set_crc_source = intel_crtc_set_crc_source,
13167 };
13168
13169 /**
13170  * intel_prepare_plane_fb - Prepare fb for usage on plane
13171  * @plane: drm plane to prepare for
13172  * @fb: framebuffer to prepare for presentation
13173  *
13174  * Prepares a framebuffer for usage on a display plane.  Generally this
13175  * involves pinning the underlying object and updating the frontbuffer tracking
13176  * bits.  Some older platforms need special physical address handling for
13177  * cursor planes.
13178  *
13179  * Must be called with struct_mutex held.
13180  *
13181  * Returns 0 on success, negative error code on failure.
13182  */
13183 int
13184 intel_prepare_plane_fb(struct drm_plane *plane,
13185                        struct drm_plane_state *new_state)
13186 {
13187         struct intel_atomic_state *intel_state =
13188                 to_intel_atomic_state(new_state->state);
13189         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13190         struct drm_framebuffer *fb = new_state->fb;
13191         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13192         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13193         int ret;
13194
13195         if (obj) {
13196                 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13197                     INTEL_INFO(dev_priv)->cursor_needs_physical) {
13198                         const int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13199
13200                         ret = i915_gem_object_attach_phys(obj, align);
13201                         if (ret) {
13202                                 DRM_DEBUG_KMS("failed to attach phys object\n");
13203                                 return ret;
13204                         }
13205                 } else {
13206                         struct i915_vma *vma;
13207
13208                         vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13209                         if (IS_ERR(vma)) {
13210                                 DRM_DEBUG_KMS("failed to pin object\n");
13211                                 return PTR_ERR(vma);
13212                         }
13213
13214                         to_intel_plane_state(new_state)->vma = vma;
13215                 }
13216         }
13217
13218         if (!obj && !old_obj)
13219                 return 0;
13220
13221         if (old_obj) {
13222                 struct drm_crtc_state *crtc_state =
13223                         drm_atomic_get_existing_crtc_state(new_state->state,
13224                                                            plane->state->crtc);
13225
13226                 /* Big Hammer, we also need to ensure that any pending
13227                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13228                  * current scanout is retired before unpinning the old
13229                  * framebuffer. Note that we rely on userspace rendering
13230                  * into the buffer attached to the pipe they are waiting
13231                  * on. If not, userspace generates a GPU hang with IPEHR
13232                  * point to the MI_WAIT_FOR_EVENT.
13233                  *
13234                  * This should only fail upon a hung GPU, in which case we
13235                  * can safely continue.
13236                  */
13237                 if (needs_modeset(crtc_state)) {
13238                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13239                                                               old_obj->resv, NULL,
13240                                                               false, 0,
13241                                                               GFP_KERNEL);
13242                         if (ret < 0)
13243                                 return ret;
13244                 }
13245         }
13246
13247         if (new_state->fence) { /* explicit fencing */
13248                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13249                                                     new_state->fence,
13250                                                     I915_FENCE_TIMEOUT,
13251                                                     GFP_KERNEL);
13252                 if (ret < 0)
13253                         return ret;
13254         }
13255
13256         if (!obj)
13257                 return 0;
13258
13259         if (!new_state->fence) { /* implicit fencing */
13260                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13261                                                       obj->resv, NULL,
13262                                                       false, I915_FENCE_TIMEOUT,
13263                                                       GFP_KERNEL);
13264                 if (ret < 0)
13265                         return ret;
13266
13267                 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13268         }
13269
13270         return 0;
13271 }
13272
13273 /**
13274  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13275  * @plane: drm plane to clean up for
13276  * @fb: old framebuffer that was on plane
13277  *
13278  * Cleans up a framebuffer that has just been removed from a plane.
13279  *
13280  * Must be called with struct_mutex held.
13281  */
13282 void
13283 intel_cleanup_plane_fb(struct drm_plane *plane,
13284                        struct drm_plane_state *old_state)
13285 {
13286         struct i915_vma *vma;
13287
13288         /* Should only be called after a successful intel_prepare_plane_fb()! */
13289         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13290         if (vma)
13291                 intel_unpin_fb_vma(vma);
13292 }
13293
13294 int
13295 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13296 {
13297         struct drm_i915_private *dev_priv;
13298         int max_scale;
13299         int crtc_clock, max_dotclk;
13300
13301         if (!intel_crtc || !crtc_state->base.enable)
13302                 return DRM_PLANE_HELPER_NO_SCALING;
13303
13304         dev_priv = to_i915(intel_crtc->base.dev);
13305
13306         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13307         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13308
13309         if (IS_GEMINILAKE(dev_priv))
13310                 max_dotclk *= 2;
13311
13312         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13313                 return DRM_PLANE_HELPER_NO_SCALING;
13314
13315         /*
13316          * skl max scale is lower of:
13317          *    close to 3 but not 3, -1 is for that purpose
13318          *            or
13319          *    cdclk/crtc_clock
13320          */
13321         max_scale = min((1 << 16) * 3 - 1,
13322                         (1 << 8) * ((max_dotclk << 8) / crtc_clock));
13323
13324         return max_scale;
13325 }
13326
13327 static int
13328 intel_check_primary_plane(struct drm_plane *plane,
13329                           struct intel_crtc_state *crtc_state,
13330                           struct intel_plane_state *state)
13331 {
13332         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13333         struct drm_crtc *crtc = state->base.crtc;
13334         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13335         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13336         bool can_position = false;
13337         int ret;
13338
13339         if (INTEL_GEN(dev_priv) >= 9) {
13340                 /* use scaler when colorkey is not required */
13341                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13342                         min_scale = 1;
13343                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13344                 }
13345                 can_position = true;
13346         }
13347
13348         ret = drm_plane_helper_check_state(&state->base,
13349                                            &state->clip,
13350                                            min_scale, max_scale,
13351                                            can_position, true);
13352         if (ret)
13353                 return ret;
13354
13355         if (!state->base.fb)
13356                 return 0;
13357
13358         if (INTEL_GEN(dev_priv) >= 9) {
13359                 ret = skl_check_plane_surface(state);
13360                 if (ret)
13361                         return ret;
13362
13363                 state->ctl = skl_plane_ctl(crtc_state, state);
13364         } else {
13365                 ret = i9xx_check_plane_surface(state);
13366                 if (ret)
13367                         return ret;
13368
13369                 state->ctl = i9xx_plane_ctl(crtc_state, state);
13370         }
13371
13372         return 0;
13373 }
13374
13375 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13376                                     struct drm_crtc_state *old_crtc_state)
13377 {
13378         struct drm_device *dev = crtc->dev;
13379         struct drm_i915_private *dev_priv = to_i915(dev);
13380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13381         struct intel_crtc_state *intel_cstate =
13382                 to_intel_crtc_state(crtc->state);
13383         struct intel_crtc_state *old_intel_cstate =
13384                 to_intel_crtc_state(old_crtc_state);
13385         struct intel_atomic_state *old_intel_state =
13386                 to_intel_atomic_state(old_crtc_state->state);
13387         bool modeset = needs_modeset(crtc->state);
13388
13389         if (!modeset &&
13390             (intel_cstate->base.color_mgmt_changed ||
13391              intel_cstate->update_pipe)) {
13392                 intel_color_set_csc(crtc->state);
13393                 intel_color_load_luts(crtc->state);
13394         }
13395
13396         /* Perform vblank evasion around commit operation */
13397         intel_pipe_update_start(intel_crtc);
13398
13399         if (modeset)
13400                 goto out;
13401
13402         if (intel_cstate->update_pipe)
13403                 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13404         else if (INTEL_GEN(dev_priv) >= 9)
13405                 skl_detach_scalers(intel_crtc);
13406
13407 out:
13408         if (dev_priv->display.atomic_update_watermarks)
13409                 dev_priv->display.atomic_update_watermarks(old_intel_state,
13410                                                            intel_cstate);
13411 }
13412
13413 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13414                                      struct drm_crtc_state *old_crtc_state)
13415 {
13416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13417
13418         intel_pipe_update_end(intel_crtc, NULL);
13419 }
13420
13421 /**
13422  * intel_plane_destroy - destroy a plane
13423  * @plane: plane to destroy
13424  *
13425  * Common destruction function for all types of planes (primary, cursor,
13426  * sprite).
13427  */
13428 void intel_plane_destroy(struct drm_plane *plane)
13429 {
13430         drm_plane_cleanup(plane);
13431         kfree(to_intel_plane(plane));
13432 }
13433
13434 const struct drm_plane_funcs intel_plane_funcs = {
13435         .update_plane = drm_atomic_helper_update_plane,
13436         .disable_plane = drm_atomic_helper_disable_plane,
13437         .destroy = intel_plane_destroy,
13438         .set_property = drm_atomic_helper_plane_set_property,
13439         .atomic_get_property = intel_plane_atomic_get_property,
13440         .atomic_set_property = intel_plane_atomic_set_property,
13441         .atomic_duplicate_state = intel_plane_duplicate_state,
13442         .atomic_destroy_state = intel_plane_destroy_state,
13443 };
13444
13445 static int
13446 intel_legacy_cursor_update(struct drm_plane *plane,
13447                            struct drm_crtc *crtc,
13448                            struct drm_framebuffer *fb,
13449                            int crtc_x, int crtc_y,
13450                            unsigned int crtc_w, unsigned int crtc_h,
13451                            uint32_t src_x, uint32_t src_y,
13452                            uint32_t src_w, uint32_t src_h)
13453 {
13454         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13455         int ret;
13456         struct drm_plane_state *old_plane_state, *new_plane_state;
13457         struct intel_plane *intel_plane = to_intel_plane(plane);
13458         struct drm_framebuffer *old_fb;
13459         struct drm_crtc_state *crtc_state = crtc->state;
13460         struct i915_vma *old_vma;
13461
13462         /*
13463          * When crtc is inactive or there is a modeset pending,
13464          * wait for it to complete in the slowpath
13465          */
13466         if (!crtc_state->active || needs_modeset(crtc_state) ||
13467             to_intel_crtc_state(crtc_state)->update_pipe)
13468                 goto slow;
13469
13470         old_plane_state = plane->state;
13471
13472         /*
13473          * If any parameters change that may affect watermarks,
13474          * take the slowpath. Only changing fb or position should be
13475          * in the fastpath.
13476          */
13477         if (old_plane_state->crtc != crtc ||
13478             old_plane_state->src_w != src_w ||
13479             old_plane_state->src_h != src_h ||
13480             old_plane_state->crtc_w != crtc_w ||
13481             old_plane_state->crtc_h != crtc_h ||
13482             !old_plane_state->fb != !fb)
13483                 goto slow;
13484
13485         new_plane_state = intel_plane_duplicate_state(plane);
13486         if (!new_plane_state)
13487                 return -ENOMEM;
13488
13489         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13490
13491         new_plane_state->src_x = src_x;
13492         new_plane_state->src_y = src_y;
13493         new_plane_state->src_w = src_w;
13494         new_plane_state->src_h = src_h;
13495         new_plane_state->crtc_x = crtc_x;
13496         new_plane_state->crtc_y = crtc_y;
13497         new_plane_state->crtc_w = crtc_w;
13498         new_plane_state->crtc_h = crtc_h;
13499
13500         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13501                                                   to_intel_plane_state(new_plane_state));
13502         if (ret)
13503                 goto out_free;
13504
13505         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13506         if (ret)
13507                 goto out_free;
13508
13509         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13510                 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13511
13512                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13513                 if (ret) {
13514                         DRM_DEBUG_KMS("failed to attach phys object\n");
13515                         goto out_unlock;
13516                 }
13517         } else {
13518                 struct i915_vma *vma;
13519
13520                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13521                 if (IS_ERR(vma)) {
13522                         DRM_DEBUG_KMS("failed to pin object\n");
13523
13524                         ret = PTR_ERR(vma);
13525                         goto out_unlock;
13526                 }
13527
13528                 to_intel_plane_state(new_plane_state)->vma = vma;
13529         }
13530
13531         old_fb = old_plane_state->fb;
13532         old_vma = to_intel_plane_state(old_plane_state)->vma;
13533
13534         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13535                           intel_plane->frontbuffer_bit);
13536
13537         /* Swap plane state */
13538         new_plane_state->fence = old_plane_state->fence;
13539         *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13540         new_plane_state->fence = NULL;
13541         new_plane_state->fb = old_fb;
13542         to_intel_plane_state(new_plane_state)->vma = old_vma;
13543
13544         if (plane->state->visible) {
13545                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13546                 intel_plane->update_plane(plane,
13547                                           to_intel_crtc_state(crtc->state),
13548                                           to_intel_plane_state(plane->state));
13549         } else {
13550                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13551                 intel_plane->disable_plane(plane, crtc);
13552         }
13553
13554         intel_cleanup_plane_fb(plane, new_plane_state);
13555
13556 out_unlock:
13557         mutex_unlock(&dev_priv->drm.struct_mutex);
13558 out_free:
13559         intel_plane_destroy_state(plane, new_plane_state);
13560         return ret;
13561
13562 slow:
13563         return drm_atomic_helper_update_plane(plane, crtc, fb,
13564                                               crtc_x, crtc_y, crtc_w, crtc_h,
13565                                               src_x, src_y, src_w, src_h);
13566 }
13567
13568 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13569         .update_plane = intel_legacy_cursor_update,
13570         .disable_plane = drm_atomic_helper_disable_plane,
13571         .destroy = intel_plane_destroy,
13572         .set_property = drm_atomic_helper_plane_set_property,
13573         .atomic_get_property = intel_plane_atomic_get_property,
13574         .atomic_set_property = intel_plane_atomic_set_property,
13575         .atomic_duplicate_state = intel_plane_duplicate_state,
13576         .atomic_destroy_state = intel_plane_destroy_state,
13577 };
13578
13579 static struct intel_plane *
13580 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13581 {
13582         struct intel_plane *primary = NULL;
13583         struct intel_plane_state *state = NULL;
13584         const uint32_t *intel_primary_formats;
13585         unsigned int supported_rotations;
13586         unsigned int num_formats;
13587         int ret;
13588
13589         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13590         if (!primary) {
13591                 ret = -ENOMEM;
13592                 goto fail;
13593         }
13594
13595         state = intel_create_plane_state(&primary->base);
13596         if (!state) {
13597                 ret = -ENOMEM;
13598                 goto fail;
13599         }
13600
13601         primary->base.state = &state->base;
13602
13603         primary->can_scale = false;
13604         primary->max_downscale = 1;
13605         if (INTEL_GEN(dev_priv) >= 9) {
13606                 primary->can_scale = true;
13607                 state->scaler_id = -1;
13608         }
13609         primary->pipe = pipe;
13610         /*
13611          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13612          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13613          */
13614         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13615                 primary->plane = (enum plane) !pipe;
13616         else
13617                 primary->plane = (enum plane) pipe;
13618         primary->id = PLANE_PRIMARY;
13619         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13620         primary->check_plane = intel_check_primary_plane;
13621
13622         if (INTEL_GEN(dev_priv) >= 9) {
13623                 intel_primary_formats = skl_primary_formats;
13624                 num_formats = ARRAY_SIZE(skl_primary_formats);
13625
13626                 primary->update_plane = skylake_update_primary_plane;
13627                 primary->disable_plane = skylake_disable_primary_plane;
13628         } else if (INTEL_GEN(dev_priv) >= 4) {
13629                 intel_primary_formats = i965_primary_formats;
13630                 num_formats = ARRAY_SIZE(i965_primary_formats);
13631
13632                 primary->update_plane = i9xx_update_primary_plane;
13633                 primary->disable_plane = i9xx_disable_primary_plane;
13634         } else {
13635                 intel_primary_formats = i8xx_primary_formats;
13636                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13637
13638                 primary->update_plane = i9xx_update_primary_plane;
13639                 primary->disable_plane = i9xx_disable_primary_plane;
13640         }
13641
13642         if (INTEL_GEN(dev_priv) >= 9)
13643                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13644                                                0, &intel_plane_funcs,
13645                                                intel_primary_formats, num_formats,
13646                                                DRM_PLANE_TYPE_PRIMARY,
13647                                                "plane 1%c", pipe_name(pipe));
13648         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13649                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13650                                                0, &intel_plane_funcs,
13651                                                intel_primary_formats, num_formats,
13652                                                DRM_PLANE_TYPE_PRIMARY,
13653                                                "primary %c", pipe_name(pipe));
13654         else
13655                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13656                                                0, &intel_plane_funcs,
13657                                                intel_primary_formats, num_formats,
13658                                                DRM_PLANE_TYPE_PRIMARY,
13659                                                "plane %c", plane_name(primary->plane));
13660         if (ret)
13661                 goto fail;
13662
13663         if (INTEL_GEN(dev_priv) >= 9) {
13664                 supported_rotations =
13665                         DRM_ROTATE_0 | DRM_ROTATE_90 |
13666                         DRM_ROTATE_180 | DRM_ROTATE_270;
13667         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13668                 supported_rotations =
13669                         DRM_ROTATE_0 | DRM_ROTATE_180 |
13670                         DRM_REFLECT_X;
13671         } else if (INTEL_GEN(dev_priv) >= 4) {
13672                 supported_rotations =
13673                         DRM_ROTATE_0 | DRM_ROTATE_180;
13674         } else {
13675                 supported_rotations = DRM_ROTATE_0;
13676         }
13677
13678         if (INTEL_GEN(dev_priv) >= 4)
13679                 drm_plane_create_rotation_property(&primary->base,
13680                                                    DRM_ROTATE_0,
13681                                                    supported_rotations);
13682
13683         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13684
13685         return primary;
13686
13687 fail:
13688         kfree(state);
13689         kfree(primary);
13690
13691         return ERR_PTR(ret);
13692 }
13693
13694 static int
13695 intel_check_cursor_plane(struct drm_plane *plane,
13696                          struct intel_crtc_state *crtc_state,
13697                          struct intel_plane_state *state)
13698 {
13699         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13700         struct drm_framebuffer *fb = state->base.fb;
13701         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13702         enum pipe pipe = to_intel_plane(plane)->pipe;
13703         unsigned stride;
13704         int ret;
13705
13706         ret = drm_plane_helper_check_state(&state->base,
13707                                            &state->clip,
13708                                            DRM_PLANE_HELPER_NO_SCALING,
13709                                            DRM_PLANE_HELPER_NO_SCALING,
13710                                            true, true);
13711         if (ret)
13712                 return ret;
13713
13714         /* if we want to turn off the cursor ignore width and height */
13715         if (!obj)
13716                 return 0;
13717
13718         /* Check for which cursor types we support */
13719         if (!cursor_size_ok(dev_priv, state->base.crtc_w,
13720                             state->base.crtc_h)) {
13721                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13722                           state->base.crtc_w, state->base.crtc_h);
13723                 return -EINVAL;
13724         }
13725
13726         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13727         if (obj->base.size < stride * state->base.crtc_h) {
13728                 DRM_DEBUG_KMS("buffer is too small\n");
13729                 return -ENOMEM;
13730         }
13731
13732         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
13733                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13734                 return -EINVAL;
13735         }
13736
13737         /*
13738          * There's something wrong with the cursor on CHV pipe C.
13739          * If it straddles the left edge of the screen then
13740          * moving it away from the edge or disabling it often
13741          * results in a pipe underrun, and often that can lead to
13742          * dead pipe (constant underrun reported, and it scans
13743          * out just a solid color). To recover from that, the
13744          * display power well must be turned off and on again.
13745          * Refuse the put the cursor into that compromised position.
13746          */
13747         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
13748             state->base.visible && state->base.crtc_x < 0) {
13749                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13750                 return -EINVAL;
13751         }
13752
13753         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
13754                 state->ctl = i845_cursor_ctl(crtc_state, state);
13755         else
13756                 state->ctl = i9xx_cursor_ctl(crtc_state, state);
13757
13758         return 0;
13759 }
13760
13761 static void
13762 intel_disable_cursor_plane(struct drm_plane *plane,
13763                            struct drm_crtc *crtc)
13764 {
13765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13766
13767         intel_crtc->cursor_addr = 0;
13768         intel_crtc_update_cursor(crtc, NULL);
13769 }
13770
13771 static void
13772 intel_update_cursor_plane(struct drm_plane *plane,
13773                           const struct intel_crtc_state *crtc_state,
13774                           const struct intel_plane_state *state)
13775 {
13776         struct drm_crtc *crtc = crtc_state->base.crtc;
13777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13778         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13779         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13780         uint32_t addr;
13781
13782         if (!obj)
13783                 addr = 0;
13784         else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
13785                 addr = intel_plane_ggtt_offset(state);
13786         else
13787                 addr = obj->phys_handle->busaddr;
13788
13789         intel_crtc->cursor_addr = addr;
13790         intel_crtc_update_cursor(crtc, state);
13791 }
13792
13793 static struct intel_plane *
13794 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13795 {
13796         struct intel_plane *cursor = NULL;
13797         struct intel_plane_state *state = NULL;
13798         int ret;
13799
13800         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13801         if (!cursor) {
13802                 ret = -ENOMEM;
13803                 goto fail;
13804         }
13805
13806         state = intel_create_plane_state(&cursor->base);
13807         if (!state) {
13808                 ret = -ENOMEM;
13809                 goto fail;
13810         }
13811
13812         cursor->base.state = &state->base;
13813
13814         cursor->can_scale = false;
13815         cursor->max_downscale = 1;
13816         cursor->pipe = pipe;
13817         cursor->plane = pipe;
13818         cursor->id = PLANE_CURSOR;
13819         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13820         cursor->check_plane = intel_check_cursor_plane;
13821         cursor->update_plane = intel_update_cursor_plane;
13822         cursor->disable_plane = intel_disable_cursor_plane;
13823
13824         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13825                                        0, &intel_cursor_plane_funcs,
13826                                        intel_cursor_formats,
13827                                        ARRAY_SIZE(intel_cursor_formats),
13828                                        DRM_PLANE_TYPE_CURSOR,
13829                                        "cursor %c", pipe_name(pipe));
13830         if (ret)
13831                 goto fail;
13832
13833         if (INTEL_GEN(dev_priv) >= 4)
13834                 drm_plane_create_rotation_property(&cursor->base,
13835                                                    DRM_ROTATE_0,
13836                                                    DRM_ROTATE_0 |
13837                                                    DRM_ROTATE_180);
13838
13839         if (INTEL_GEN(dev_priv) >= 9)
13840                 state->scaler_id = -1;
13841
13842         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13843
13844         return cursor;
13845
13846 fail:
13847         kfree(state);
13848         kfree(cursor);
13849
13850         return ERR_PTR(ret);
13851 }
13852
13853 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13854                                     struct intel_crtc_state *crtc_state)
13855 {
13856         struct intel_crtc_scaler_state *scaler_state =
13857                 &crtc_state->scaler_state;
13858         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13859         int i;
13860
13861         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13862         if (!crtc->num_scalers)
13863                 return;
13864
13865         for (i = 0; i < crtc->num_scalers; i++) {
13866                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13867
13868                 scaler->in_use = 0;
13869                 scaler->mode = PS_SCALER_MODE_DYN;
13870         }
13871
13872         scaler_state->scaler_id = -1;
13873 }
13874
13875 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13876 {
13877         struct intel_crtc *intel_crtc;
13878         struct intel_crtc_state *crtc_state = NULL;
13879         struct intel_plane *primary = NULL;
13880         struct intel_plane *cursor = NULL;
13881         int sprite, ret;
13882
13883         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13884         if (!intel_crtc)
13885                 return -ENOMEM;
13886
13887         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13888         if (!crtc_state) {
13889                 ret = -ENOMEM;
13890                 goto fail;
13891         }
13892         intel_crtc->config = crtc_state;
13893         intel_crtc->base.state = &crtc_state->base;
13894         crtc_state->base.crtc = &intel_crtc->base;
13895
13896         primary = intel_primary_plane_create(dev_priv, pipe);
13897         if (IS_ERR(primary)) {
13898                 ret = PTR_ERR(primary);
13899                 goto fail;
13900         }
13901         intel_crtc->plane_ids_mask |= BIT(primary->id);
13902
13903         for_each_sprite(dev_priv, pipe, sprite) {
13904                 struct intel_plane *plane;
13905
13906                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13907                 if (IS_ERR(plane)) {
13908                         ret = PTR_ERR(plane);
13909                         goto fail;
13910                 }
13911                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13912         }
13913
13914         cursor = intel_cursor_plane_create(dev_priv, pipe);
13915         if (IS_ERR(cursor)) {
13916                 ret = PTR_ERR(cursor);
13917                 goto fail;
13918         }
13919         intel_crtc->plane_ids_mask |= BIT(cursor->id);
13920
13921         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13922                                         &primary->base, &cursor->base,
13923                                         &intel_crtc_funcs,
13924                                         "pipe %c", pipe_name(pipe));
13925         if (ret)
13926                 goto fail;
13927
13928         intel_crtc->pipe = pipe;
13929         intel_crtc->plane = primary->plane;
13930
13931         intel_crtc->cursor_base = ~0;
13932         intel_crtc->cursor_cntl = ~0;
13933         intel_crtc->cursor_size = ~0;
13934
13935         /* initialize shared scalers */
13936         intel_crtc_init_scalers(intel_crtc, crtc_state);
13937
13938         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13939                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13940         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13941         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13942
13943         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13944
13945         intel_color_init(&intel_crtc->base);
13946
13947         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13948
13949         return 0;
13950
13951 fail:
13952         /*
13953          * drm_mode_config_cleanup() will free up any
13954          * crtcs/planes already initialized.
13955          */
13956         kfree(crtc_state);
13957         kfree(intel_crtc);
13958
13959         return ret;
13960 }
13961
13962 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13963 {
13964         struct drm_device *dev = connector->base.dev;
13965
13966         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13967
13968         if (!connector->base.state->crtc)
13969                 return INVALID_PIPE;
13970
13971         return to_intel_crtc(connector->base.state->crtc)->pipe;
13972 }
13973
13974 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13975                                 struct drm_file *file)
13976 {
13977         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13978         struct drm_crtc *drmmode_crtc;
13979         struct intel_crtc *crtc;
13980
13981         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13982         if (!drmmode_crtc)
13983                 return -ENOENT;
13984
13985         crtc = to_intel_crtc(drmmode_crtc);
13986         pipe_from_crtc_id->pipe = crtc->pipe;
13987
13988         return 0;
13989 }
13990
13991 static int intel_encoder_clones(struct intel_encoder *encoder)
13992 {
13993         struct drm_device *dev = encoder->base.dev;
13994         struct intel_encoder *source_encoder;
13995         int index_mask = 0;
13996         int entry = 0;
13997
13998         for_each_intel_encoder(dev, source_encoder) {
13999                 if (encoders_cloneable(encoder, source_encoder))
14000                         index_mask |= (1 << entry);
14001
14002                 entry++;
14003         }
14004
14005         return index_mask;
14006 }
14007
14008 static bool has_edp_a(struct drm_i915_private *dev_priv)
14009 {
14010         if (!IS_MOBILE(dev_priv))
14011                 return false;
14012
14013         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14014                 return false;
14015
14016         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14017                 return false;
14018
14019         return true;
14020 }
14021
14022 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14023 {
14024         if (INTEL_GEN(dev_priv) >= 9)
14025                 return false;
14026
14027         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14028                 return false;
14029
14030         if (IS_CHERRYVIEW(dev_priv))
14031                 return false;
14032
14033         if (HAS_PCH_LPT_H(dev_priv) &&
14034             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14035                 return false;
14036
14037         /* DDI E can't be used if DDI A requires 4 lanes */
14038         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14039                 return false;
14040
14041         if (!dev_priv->vbt.int_crt_support)
14042                 return false;
14043
14044         return true;
14045 }
14046
14047 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14048 {
14049         int pps_num;
14050         int pps_idx;
14051
14052         if (HAS_DDI(dev_priv))
14053                 return;
14054         /*
14055          * This w/a is needed at least on CPT/PPT, but to be sure apply it
14056          * everywhere where registers can be write protected.
14057          */
14058         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14059                 pps_num = 2;
14060         else
14061                 pps_num = 1;
14062
14063         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14064                 u32 val = I915_READ(PP_CONTROL(pps_idx));
14065
14066                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14067                 I915_WRITE(PP_CONTROL(pps_idx), val);
14068         }
14069 }
14070
14071 static void intel_pps_init(struct drm_i915_private *dev_priv)
14072 {
14073         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14074                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14075         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14076                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14077         else
14078                 dev_priv->pps_mmio_base = PPS_BASE;
14079
14080         intel_pps_unlock_regs_wa(dev_priv);
14081 }
14082
14083 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14084 {
14085         struct intel_encoder *encoder;
14086         bool dpd_is_edp = false;
14087
14088         intel_pps_init(dev_priv);
14089
14090         /*
14091          * intel_edp_init_connector() depends on this completing first, to
14092          * prevent the registeration of both eDP and LVDS and the incorrect
14093          * sharing of the PPS.
14094          */
14095         intel_lvds_init(dev_priv);
14096
14097         if (intel_crt_present(dev_priv))
14098                 intel_crt_init(dev_priv);
14099
14100         if (IS_GEN9_LP(dev_priv)) {
14101                 /*
14102                  * FIXME: Broxton doesn't support port detection via the
14103                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14104                  * detect the ports.
14105                  */
14106                 intel_ddi_init(dev_priv, PORT_A);
14107                 intel_ddi_init(dev_priv, PORT_B);
14108                 intel_ddi_init(dev_priv, PORT_C);
14109
14110                 intel_dsi_init(dev_priv);
14111         } else if (HAS_DDI(dev_priv)) {
14112                 int found;
14113
14114                 /*
14115                  * Haswell uses DDI functions to detect digital outputs.
14116                  * On SKL pre-D0 the strap isn't connected, so we assume
14117                  * it's there.
14118                  */
14119                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14120                 /* WaIgnoreDDIAStrap: skl */
14121                 if (found || IS_GEN9_BC(dev_priv))
14122                         intel_ddi_init(dev_priv, PORT_A);
14123
14124                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14125                  * register */
14126                 found = I915_READ(SFUSE_STRAP);
14127
14128                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14129                         intel_ddi_init(dev_priv, PORT_B);
14130                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14131                         intel_ddi_init(dev_priv, PORT_C);
14132                 if (found & SFUSE_STRAP_DDID_DETECTED)
14133                         intel_ddi_init(dev_priv, PORT_D);
14134                 /*
14135                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14136                  */
14137                 if (IS_GEN9_BC(dev_priv) &&
14138                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14139                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14140                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14141                         intel_ddi_init(dev_priv, PORT_E);
14142
14143         } else if (HAS_PCH_SPLIT(dev_priv)) {
14144                 int found;
14145                 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14146
14147                 if (has_edp_a(dev_priv))
14148                         intel_dp_init(dev_priv, DP_A, PORT_A);
14149
14150                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14151                         /* PCH SDVOB multiplex with HDMIB */
14152                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14153                         if (!found)
14154                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14155                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14156                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14157                 }
14158
14159                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14160                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14161
14162                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14163                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14164
14165                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14166                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14167
14168                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14169                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14170         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14171                 bool has_edp, has_port;
14172
14173                 /*
14174                  * The DP_DETECTED bit is the latched state of the DDC
14175                  * SDA pin at boot. However since eDP doesn't require DDC
14176                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14177                  * eDP ports may have been muxed to an alternate function.
14178                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14179                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14180                  * detect eDP ports.
14181                  *
14182                  * Sadly the straps seem to be missing sometimes even for HDMI
14183                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14184                  * and VBT for the presence of the port. Additionally we can't
14185                  * trust the port type the VBT declares as we've seen at least
14186                  * HDMI ports that the VBT claim are DP or eDP.
14187                  */
14188                 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14189                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14190                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14191                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14192                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14193                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14194
14195                 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14196                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14197                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14198                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14199                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14200                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14201
14202                 if (IS_CHERRYVIEW(dev_priv)) {
14203                         /*
14204                          * eDP not supported on port D,
14205                          * so no need to worry about it
14206                          */
14207                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14208                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14209                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14210                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14211                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14212                 }
14213
14214                 intel_dsi_init(dev_priv);
14215         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14216                 bool found = false;
14217
14218                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14219                         DRM_DEBUG_KMS("probing SDVOB\n");
14220                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14221                         if (!found && IS_G4X(dev_priv)) {
14222                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14223                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14224                         }
14225
14226                         if (!found && IS_G4X(dev_priv))
14227                                 intel_dp_init(dev_priv, DP_B, PORT_B);
14228                 }
14229
14230                 /* Before G4X SDVOC doesn't have its own detect register */
14231
14232                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14233                         DRM_DEBUG_KMS("probing SDVOC\n");
14234                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14235                 }
14236
14237                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14238
14239                         if (IS_G4X(dev_priv)) {
14240                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14241                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14242                         }
14243                         if (IS_G4X(dev_priv))
14244                                 intel_dp_init(dev_priv, DP_C, PORT_C);
14245                 }
14246
14247                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14248                         intel_dp_init(dev_priv, DP_D, PORT_D);
14249         } else if (IS_GEN2(dev_priv))
14250                 intel_dvo_init(dev_priv);
14251
14252         if (SUPPORTS_TV(dev_priv))
14253                 intel_tv_init(dev_priv);
14254
14255         intel_psr_init(dev_priv);
14256
14257         for_each_intel_encoder(&dev_priv->drm, encoder) {
14258                 encoder->base.possible_crtcs = encoder->crtc_mask;
14259                 encoder->base.possible_clones =
14260                         intel_encoder_clones(encoder);
14261         }
14262
14263         intel_init_pch_refclk(dev_priv);
14264
14265         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14266 }
14267
14268 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14269 {
14270         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14271
14272         drm_framebuffer_cleanup(fb);
14273
14274         i915_gem_object_lock(intel_fb->obj);
14275         WARN_ON(!intel_fb->obj->framebuffer_references--);
14276         i915_gem_object_unlock(intel_fb->obj);
14277
14278         i915_gem_object_put(intel_fb->obj);
14279
14280         kfree(intel_fb);
14281 }
14282
14283 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14284                                                 struct drm_file *file,
14285                                                 unsigned int *handle)
14286 {
14287         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14288         struct drm_i915_gem_object *obj = intel_fb->obj;
14289
14290         if (obj->userptr.mm) {
14291                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14292                 return -EINVAL;
14293         }
14294
14295         return drm_gem_handle_create(file, &obj->base, handle);
14296 }
14297
14298 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14299                                         struct drm_file *file,
14300                                         unsigned flags, unsigned color,
14301                                         struct drm_clip_rect *clips,
14302                                         unsigned num_clips)
14303 {
14304         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14305
14306         i915_gem_object_flush_if_display(obj);
14307         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14308
14309         return 0;
14310 }
14311
14312 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14313         .destroy = intel_user_framebuffer_destroy,
14314         .create_handle = intel_user_framebuffer_create_handle,
14315         .dirty = intel_user_framebuffer_dirty,
14316 };
14317
14318 static
14319 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14320                          uint64_t fb_modifier, uint32_t pixel_format)
14321 {
14322         u32 gen = INTEL_GEN(dev_priv);
14323
14324         if (gen >= 9) {
14325                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14326
14327                 /* "The stride in bytes must not exceed the of the size of 8K
14328                  *  pixels and 32K bytes."
14329                  */
14330                 return min(8192 * cpp, 32768);
14331         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14332                 return 32*1024;
14333         } else if (gen >= 4) {
14334                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14335                         return 16*1024;
14336                 else
14337                         return 32*1024;
14338         } else if (gen >= 3) {
14339                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14340                         return 8*1024;
14341                 else
14342                         return 16*1024;
14343         } else {
14344                 /* XXX DSPC is limited to 4k tiled */
14345                 return 8*1024;
14346         }
14347 }
14348
14349 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14350                                   struct drm_i915_gem_object *obj,
14351                                   struct drm_mode_fb_cmd2 *mode_cmd)
14352 {
14353         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14354         struct drm_format_name_buf format_name;
14355         u32 pitch_limit, stride_alignment;
14356         unsigned int tiling, stride;
14357         int ret = -EINVAL;
14358
14359         i915_gem_object_lock(obj);
14360         obj->framebuffer_references++;
14361         tiling = i915_gem_object_get_tiling(obj);
14362         stride = i915_gem_object_get_stride(obj);
14363         i915_gem_object_unlock(obj);
14364
14365         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14366                 /*
14367                  * If there's a fence, enforce that
14368                  * the fb modifier and tiling mode match.
14369                  */
14370                 if (tiling != I915_TILING_NONE &&
14371                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14372                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14373                         goto err;
14374                 }
14375         } else {
14376                 if (tiling == I915_TILING_X) {
14377                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14378                 } else if (tiling == I915_TILING_Y) {
14379                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14380                         goto err;
14381                 }
14382         }
14383
14384         /* Passed in modifier sanity checking. */
14385         switch (mode_cmd->modifier[0]) {
14386         case I915_FORMAT_MOD_Y_TILED:
14387         case I915_FORMAT_MOD_Yf_TILED:
14388                 if (INTEL_GEN(dev_priv) < 9) {
14389                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14390                                       mode_cmd->modifier[0]);
14391                         goto err;
14392                 }
14393         case DRM_FORMAT_MOD_LINEAR:
14394         case I915_FORMAT_MOD_X_TILED:
14395                 break;
14396         default:
14397                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14398                               mode_cmd->modifier[0]);
14399                 goto err;
14400         }
14401
14402         /*
14403          * gen2/3 display engine uses the fence if present,
14404          * so the tiling mode must match the fb modifier exactly.
14405          */
14406         if (INTEL_INFO(dev_priv)->gen < 4 &&
14407             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14408                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14409                 goto err;
14410         }
14411
14412         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14413                                            mode_cmd->pixel_format);
14414         if (mode_cmd->pitches[0] > pitch_limit) {
14415                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14416                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14417                               "tiled" : "linear",
14418                               mode_cmd->pitches[0], pitch_limit);
14419                 goto err;
14420         }
14421
14422         /*
14423          * If there's a fence, enforce that
14424          * the fb pitch and fence stride match.
14425          */
14426         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14427                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14428                               mode_cmd->pitches[0], stride);
14429                 goto err;
14430         }
14431
14432         /* Reject formats not supported by any plane early. */
14433         switch (mode_cmd->pixel_format) {
14434         case DRM_FORMAT_C8:
14435         case DRM_FORMAT_RGB565:
14436         case DRM_FORMAT_XRGB8888:
14437         case DRM_FORMAT_ARGB8888:
14438                 break;
14439         case DRM_FORMAT_XRGB1555:
14440                 if (INTEL_GEN(dev_priv) > 3) {
14441                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14442                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14443                         goto err;
14444                 }
14445                 break;
14446         case DRM_FORMAT_ABGR8888:
14447                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14448                     INTEL_GEN(dev_priv) < 9) {
14449                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14450                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14451                         goto err;
14452                 }
14453                 break;
14454         case DRM_FORMAT_XBGR8888:
14455         case DRM_FORMAT_XRGB2101010:
14456         case DRM_FORMAT_XBGR2101010:
14457                 if (INTEL_GEN(dev_priv) < 4) {
14458                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14459                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14460                         goto err;
14461                 }
14462                 break;
14463         case DRM_FORMAT_ABGR2101010:
14464                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14465                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14466                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14467                         goto err;
14468                 }
14469                 break;
14470         case DRM_FORMAT_YUYV:
14471         case DRM_FORMAT_UYVY:
14472         case DRM_FORMAT_YVYU:
14473         case DRM_FORMAT_VYUY:
14474                 if (INTEL_GEN(dev_priv) < 5) {
14475                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14476                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14477                         goto err;
14478                 }
14479                 break;
14480         default:
14481                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14482                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
14483                 goto err;
14484         }
14485
14486         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14487         if (mode_cmd->offsets[0] != 0)
14488                 goto err;
14489
14490         drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14491                                        &intel_fb->base, mode_cmd);
14492
14493         stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
14494         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14495                 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
14496                               mode_cmd->pitches[0], stride_alignment);
14497                 goto err;
14498         }
14499
14500         intel_fb->obj = obj;
14501
14502         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14503         if (ret)
14504                 goto err;
14505
14506         ret = drm_framebuffer_init(obj->base.dev,
14507                                    &intel_fb->base,
14508                                    &intel_fb_funcs);
14509         if (ret) {
14510                 DRM_ERROR("framebuffer init failed %d\n", ret);
14511                 goto err;
14512         }
14513
14514         return 0;
14515
14516 err:
14517         i915_gem_object_lock(obj);
14518         obj->framebuffer_references--;
14519         i915_gem_object_unlock(obj);
14520         return ret;
14521 }
14522
14523 static struct drm_framebuffer *
14524 intel_user_framebuffer_create(struct drm_device *dev,
14525                               struct drm_file *filp,
14526                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14527 {
14528         struct drm_framebuffer *fb;
14529         struct drm_i915_gem_object *obj;
14530         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14531
14532         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14533         if (!obj)
14534                 return ERR_PTR(-ENOENT);
14535
14536         fb = intel_framebuffer_create(obj, &mode_cmd);
14537         if (IS_ERR(fb))
14538                 i915_gem_object_put(obj);
14539
14540         return fb;
14541 }
14542
14543 static void intel_atomic_state_free(struct drm_atomic_state *state)
14544 {
14545         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14546
14547         drm_atomic_state_default_release(state);
14548
14549         i915_sw_fence_fini(&intel_state->commit_ready);
14550
14551         kfree(state);
14552 }
14553
14554 static const struct drm_mode_config_funcs intel_mode_funcs = {
14555         .fb_create = intel_user_framebuffer_create,
14556         .output_poll_changed = intel_fbdev_output_poll_changed,
14557         .atomic_check = intel_atomic_check,
14558         .atomic_commit = intel_atomic_commit,
14559         .atomic_state_alloc = intel_atomic_state_alloc,
14560         .atomic_state_clear = intel_atomic_state_clear,
14561         .atomic_state_free = intel_atomic_state_free,
14562 };
14563
14564 /**
14565  * intel_init_display_hooks - initialize the display modesetting hooks
14566  * @dev_priv: device private
14567  */
14568 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14569 {
14570         intel_init_cdclk_hooks(dev_priv);
14571
14572         if (INTEL_INFO(dev_priv)->gen >= 9) {
14573                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14574                 dev_priv->display.get_initial_plane_config =
14575                         skylake_get_initial_plane_config;
14576                 dev_priv->display.crtc_compute_clock =
14577                         haswell_crtc_compute_clock;
14578                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14579                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14580         } else if (HAS_DDI(dev_priv)) {
14581                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14582                 dev_priv->display.get_initial_plane_config =
14583                         ironlake_get_initial_plane_config;
14584                 dev_priv->display.crtc_compute_clock =
14585                         haswell_crtc_compute_clock;
14586                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14587                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14588         } else if (HAS_PCH_SPLIT(dev_priv)) {
14589                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14590                 dev_priv->display.get_initial_plane_config =
14591                         ironlake_get_initial_plane_config;
14592                 dev_priv->display.crtc_compute_clock =
14593                         ironlake_crtc_compute_clock;
14594                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14595                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14596         } else if (IS_CHERRYVIEW(dev_priv)) {
14597                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14598                 dev_priv->display.get_initial_plane_config =
14599                         i9xx_get_initial_plane_config;
14600                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14601                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14602                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14603         } else if (IS_VALLEYVIEW(dev_priv)) {
14604                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14605                 dev_priv->display.get_initial_plane_config =
14606                         i9xx_get_initial_plane_config;
14607                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14608                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14609                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14610         } else if (IS_G4X(dev_priv)) {
14611                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14612                 dev_priv->display.get_initial_plane_config =
14613                         i9xx_get_initial_plane_config;
14614                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14615                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14616                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14617         } else if (IS_PINEVIEW(dev_priv)) {
14618                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14619                 dev_priv->display.get_initial_plane_config =
14620                         i9xx_get_initial_plane_config;
14621                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14622                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14623                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14624         } else if (!IS_GEN2(dev_priv)) {
14625                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14626                 dev_priv->display.get_initial_plane_config =
14627                         i9xx_get_initial_plane_config;
14628                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14629                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14630                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14631         } else {
14632                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14633                 dev_priv->display.get_initial_plane_config =
14634                         i9xx_get_initial_plane_config;
14635                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14636                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14637                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14638         }
14639
14640         if (IS_GEN5(dev_priv)) {
14641                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14642         } else if (IS_GEN6(dev_priv)) {
14643                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14644         } else if (IS_IVYBRIDGE(dev_priv)) {
14645                 /* FIXME: detect B0+ stepping and use auto training */
14646                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14647         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14648                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14649         }
14650
14651         if (dev_priv->info.gen >= 9)
14652                 dev_priv->display.update_crtcs = skl_update_crtcs;
14653         else
14654                 dev_priv->display.update_crtcs = intel_update_crtcs;
14655
14656         switch (INTEL_INFO(dev_priv)->gen) {
14657         case 2:
14658                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14659                 break;
14660
14661         case 3:
14662                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14663                 break;
14664
14665         case 4:
14666         case 5:
14667                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14668                 break;
14669
14670         case 6:
14671                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14672                 break;
14673         case 7:
14674         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14675                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14676                 break;
14677         case 9:
14678                 /* Drop through - unsupported since execlist only. */
14679         default:
14680                 /* Default just returns -ENODEV to indicate unsupported */
14681                 dev_priv->display.queue_flip = intel_default_queue_flip;
14682         }
14683 }
14684
14685 /*
14686  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14687  * resume, or other times.  This quirk makes sure that's the case for
14688  * affected systems.
14689  */
14690 static void quirk_pipea_force(struct drm_device *dev)
14691 {
14692         struct drm_i915_private *dev_priv = to_i915(dev);
14693
14694         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14695         DRM_INFO("applying pipe a force quirk\n");
14696 }
14697
14698 static void quirk_pipeb_force(struct drm_device *dev)
14699 {
14700         struct drm_i915_private *dev_priv = to_i915(dev);
14701
14702         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14703         DRM_INFO("applying pipe b force quirk\n");
14704 }
14705
14706 /*
14707  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14708  */
14709 static void quirk_ssc_force_disable(struct drm_device *dev)
14710 {
14711         struct drm_i915_private *dev_priv = to_i915(dev);
14712         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14713         DRM_INFO("applying lvds SSC disable quirk\n");
14714 }
14715
14716 /*
14717  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14718  * brightness value
14719  */
14720 static void quirk_invert_brightness(struct drm_device *dev)
14721 {
14722         struct drm_i915_private *dev_priv = to_i915(dev);
14723         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14724         DRM_INFO("applying inverted panel brightness quirk\n");
14725 }
14726
14727 /* Some VBT's incorrectly indicate no backlight is present */
14728 static void quirk_backlight_present(struct drm_device *dev)
14729 {
14730         struct drm_i915_private *dev_priv = to_i915(dev);
14731         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14732         DRM_INFO("applying backlight present quirk\n");
14733 }
14734
14735 struct intel_quirk {
14736         int device;
14737         int subsystem_vendor;
14738         int subsystem_device;
14739         void (*hook)(struct drm_device *dev);
14740 };
14741
14742 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14743 struct intel_dmi_quirk {
14744         void (*hook)(struct drm_device *dev);
14745         const struct dmi_system_id (*dmi_id_list)[];
14746 };
14747
14748 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14749 {
14750         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14751         return 1;
14752 }
14753
14754 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14755         {
14756                 .dmi_id_list = &(const struct dmi_system_id[]) {
14757                         {
14758                                 .callback = intel_dmi_reverse_brightness,
14759                                 .ident = "NCR Corporation",
14760                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14761                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14762                                 },
14763                         },
14764                         { }  /* terminating entry */
14765                 },
14766                 .hook = quirk_invert_brightness,
14767         },
14768 };
14769
14770 static struct intel_quirk intel_quirks[] = {
14771         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14772         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14773
14774         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14775         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14776
14777         /* 830 needs to leave pipe A & dpll A up */
14778         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14779
14780         /* 830 needs to leave pipe B & dpll B up */
14781         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14782
14783         /* Lenovo U160 cannot use SSC on LVDS */
14784         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14785
14786         /* Sony Vaio Y cannot use SSC on LVDS */
14787         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14788
14789         /* Acer Aspire 5734Z must invert backlight brightness */
14790         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14791
14792         /* Acer/eMachines G725 */
14793         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14794
14795         /* Acer/eMachines e725 */
14796         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14797
14798         /* Acer/Packard Bell NCL20 */
14799         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14800
14801         /* Acer Aspire 4736Z */
14802         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14803
14804         /* Acer Aspire 5336 */
14805         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14806
14807         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14808         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14809
14810         /* Acer C720 Chromebook (Core i3 4005U) */
14811         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14812
14813         /* Apple Macbook 2,1 (Core 2 T7400) */
14814         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14815
14816         /* Apple Macbook 4,1 */
14817         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14818
14819         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14820         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14821
14822         /* HP Chromebook 14 (Celeron 2955U) */
14823         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14824
14825         /* Dell Chromebook 11 */
14826         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14827
14828         /* Dell Chromebook 11 (2015 version) */
14829         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14830 };
14831
14832 static void intel_init_quirks(struct drm_device *dev)
14833 {
14834         struct pci_dev *d = dev->pdev;
14835         int i;
14836
14837         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14838                 struct intel_quirk *q = &intel_quirks[i];
14839
14840                 if (d->device == q->device &&
14841                     (d->subsystem_vendor == q->subsystem_vendor ||
14842                      q->subsystem_vendor == PCI_ANY_ID) &&
14843                     (d->subsystem_device == q->subsystem_device ||
14844                      q->subsystem_device == PCI_ANY_ID))
14845                         q->hook(dev);
14846         }
14847         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14848                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14849                         intel_dmi_quirks[i].hook(dev);
14850         }
14851 }
14852
14853 /* Disable the VGA plane that we never use */
14854 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14855 {
14856         struct pci_dev *pdev = dev_priv->drm.pdev;
14857         u8 sr1;
14858         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14859
14860         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14861         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14862         outb(SR01, VGA_SR_INDEX);
14863         sr1 = inb(VGA_SR_DATA);
14864         outb(sr1 | 1<<5, VGA_SR_DATA);
14865         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14866         udelay(300);
14867
14868         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14869         POSTING_READ(vga_reg);
14870 }
14871
14872 void intel_modeset_init_hw(struct drm_device *dev)
14873 {
14874         struct drm_i915_private *dev_priv = to_i915(dev);
14875
14876         intel_update_cdclk(dev_priv);
14877         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14878
14879         intel_init_clock_gating(dev_priv);
14880 }
14881
14882 /*
14883  * Calculate what we think the watermarks should be for the state we've read
14884  * out of the hardware and then immediately program those watermarks so that
14885  * we ensure the hardware settings match our internal state.
14886  *
14887  * We can calculate what we think WM's should be by creating a duplicate of the
14888  * current state (which was constructed during hardware readout) and running it
14889  * through the atomic check code to calculate new watermark values in the
14890  * state object.
14891  */
14892 static void sanitize_watermarks(struct drm_device *dev)
14893 {
14894         struct drm_i915_private *dev_priv = to_i915(dev);
14895         struct drm_atomic_state *state;
14896         struct intel_atomic_state *intel_state;
14897         struct drm_crtc *crtc;
14898         struct drm_crtc_state *cstate;
14899         struct drm_modeset_acquire_ctx ctx;
14900         int ret;
14901         int i;
14902
14903         /* Only supported on platforms that use atomic watermark design */
14904         if (!dev_priv->display.optimize_watermarks)
14905                 return;
14906
14907         /*
14908          * We need to hold connection_mutex before calling duplicate_state so
14909          * that the connector loop is protected.
14910          */
14911         drm_modeset_acquire_init(&ctx, 0);
14912 retry:
14913         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14914         if (ret == -EDEADLK) {
14915                 drm_modeset_backoff(&ctx);
14916                 goto retry;
14917         } else if (WARN_ON(ret)) {
14918                 goto fail;
14919         }
14920
14921         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14922         if (WARN_ON(IS_ERR(state)))
14923                 goto fail;
14924
14925         intel_state = to_intel_atomic_state(state);
14926
14927         /*
14928          * Hardware readout is the only time we don't want to calculate
14929          * intermediate watermarks (since we don't trust the current
14930          * watermarks).
14931          */
14932         if (!HAS_GMCH_DISPLAY(dev_priv))
14933                 intel_state->skip_intermediate_wm = true;
14934
14935         ret = intel_atomic_check(dev, state);
14936         if (ret) {
14937                 /*
14938                  * If we fail here, it means that the hardware appears to be
14939                  * programmed in a way that shouldn't be possible, given our
14940                  * understanding of watermark requirements.  This might mean a
14941                  * mistake in the hardware readout code or a mistake in the
14942                  * watermark calculations for a given platform.  Raise a WARN
14943                  * so that this is noticeable.
14944                  *
14945                  * If this actually happens, we'll have to just leave the
14946                  * BIOS-programmed watermarks untouched and hope for the best.
14947                  */
14948                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14949                 goto put_state;
14950         }
14951
14952         /* Write calculated watermark values back */
14953         for_each_new_crtc_in_state(state, crtc, cstate, i) {
14954                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14955
14956                 cs->wm.need_postvbl_update = true;
14957                 dev_priv->display.optimize_watermarks(intel_state, cs);
14958         }
14959
14960 put_state:
14961         drm_atomic_state_put(state);
14962 fail:
14963         drm_modeset_drop_locks(&ctx);
14964         drm_modeset_acquire_fini(&ctx);
14965 }
14966
14967 int intel_modeset_init(struct drm_device *dev)
14968 {
14969         struct drm_i915_private *dev_priv = to_i915(dev);
14970         struct i915_ggtt *ggtt = &dev_priv->ggtt;
14971         enum pipe pipe;
14972         struct intel_crtc *crtc;
14973
14974         drm_mode_config_init(dev);
14975
14976         dev->mode_config.min_width = 0;
14977         dev->mode_config.min_height = 0;
14978
14979         dev->mode_config.preferred_depth = 24;
14980         dev->mode_config.prefer_shadow = 1;
14981
14982         dev->mode_config.allow_fb_modifiers = true;
14983
14984         dev->mode_config.funcs = &intel_mode_funcs;
14985
14986         INIT_WORK(&dev_priv->atomic_helper.free_work,
14987                   intel_atomic_helper_free_state_worker);
14988
14989         intel_init_quirks(dev);
14990
14991         intel_init_pm(dev_priv);
14992
14993         if (INTEL_INFO(dev_priv)->num_pipes == 0)
14994                 return 0;
14995
14996         /*
14997          * There may be no VBT; and if the BIOS enabled SSC we can
14998          * just keep using it to avoid unnecessary flicker.  Whereas if the
14999          * BIOS isn't using it, don't assume it will work even if the VBT
15000          * indicates as much.
15001          */
15002         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15003                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15004                                             DREF_SSC1_ENABLE);
15005
15006                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15007                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15008                                      bios_lvds_use_ssc ? "en" : "dis",
15009                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15010                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15011                 }
15012         }
15013
15014         if (IS_GEN2(dev_priv)) {
15015                 dev->mode_config.max_width = 2048;
15016                 dev->mode_config.max_height = 2048;
15017         } else if (IS_GEN3(dev_priv)) {
15018                 dev->mode_config.max_width = 4096;
15019                 dev->mode_config.max_height = 4096;
15020         } else {
15021                 dev->mode_config.max_width = 8192;
15022                 dev->mode_config.max_height = 8192;
15023         }
15024
15025         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15026                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15027                 dev->mode_config.cursor_height = 1023;
15028         } else if (IS_GEN2(dev_priv)) {
15029                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15030                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15031         } else {
15032                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15033                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15034         }
15035
15036         dev->mode_config.fb_base = ggtt->mappable_base;
15037
15038         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15039                       INTEL_INFO(dev_priv)->num_pipes,
15040                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15041
15042         for_each_pipe(dev_priv, pipe) {
15043                 int ret;
15044
15045                 ret = intel_crtc_init(dev_priv, pipe);
15046                 if (ret) {
15047                         drm_mode_config_cleanup(dev);
15048                         return ret;
15049                 }
15050         }
15051
15052         intel_shared_dpll_init(dev);
15053
15054         intel_update_czclk(dev_priv);
15055         intel_modeset_init_hw(dev);
15056
15057         if (dev_priv->max_cdclk_freq == 0)
15058                 intel_update_max_cdclk(dev_priv);
15059
15060         /* Just disable it once at startup */
15061         i915_disable_vga(dev_priv);
15062         intel_setup_outputs(dev_priv);
15063
15064         drm_modeset_lock_all(dev);
15065         intel_modeset_setup_hw_state(dev);
15066         drm_modeset_unlock_all(dev);
15067
15068         for_each_intel_crtc(dev, crtc) {
15069                 struct intel_initial_plane_config plane_config = {};
15070
15071                 if (!crtc->active)
15072                         continue;
15073
15074                 /*
15075                  * Note that reserving the BIOS fb up front prevents us
15076                  * from stuffing other stolen allocations like the ring
15077                  * on top.  This prevents some ugliness at boot time, and
15078                  * can even allow for smooth boot transitions if the BIOS
15079                  * fb is large enough for the active pipe configuration.
15080                  */
15081                 dev_priv->display.get_initial_plane_config(crtc,
15082                                                            &plane_config);
15083
15084                 /*
15085                  * If the fb is shared between multiple heads, we'll
15086                  * just get the first one.
15087                  */
15088                 intel_find_initial_plane_obj(crtc, &plane_config);
15089         }
15090
15091         /*
15092          * Make sure hardware watermarks really match the state we read out.
15093          * Note that we need to do this after reconstructing the BIOS fb's
15094          * since the watermark calculation done here will use pstate->fb.
15095          */
15096         if (!HAS_GMCH_DISPLAY(dev_priv))
15097                 sanitize_watermarks(dev);
15098
15099         return 0;
15100 }
15101
15102 static void intel_enable_pipe_a(struct drm_device *dev)
15103 {
15104         struct intel_connector *connector;
15105         struct drm_connector_list_iter conn_iter;
15106         struct drm_connector *crt = NULL;
15107         struct intel_load_detect_pipe load_detect_temp;
15108         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15109
15110         /* We can't just switch on the pipe A, we need to set things up with a
15111          * proper mode and output configuration. As a gross hack, enable pipe A
15112          * by enabling the load detect pipe once. */
15113         drm_connector_list_iter_begin(dev, &conn_iter);
15114         for_each_intel_connector_iter(connector, &conn_iter) {
15115                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15116                         crt = &connector->base;
15117                         break;
15118                 }
15119         }
15120         drm_connector_list_iter_end(&conn_iter);
15121
15122         if (!crt)
15123                 return;
15124
15125         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15126                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15127 }
15128
15129 static bool
15130 intel_check_plane_mapping(struct intel_crtc *crtc)
15131 {
15132         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15133         u32 val;
15134
15135         if (INTEL_INFO(dev_priv)->num_pipes == 1)
15136                 return true;
15137
15138         val = I915_READ(DSPCNTR(!crtc->plane));
15139
15140         if ((val & DISPLAY_PLANE_ENABLE) &&
15141             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15142                 return false;
15143
15144         return true;
15145 }
15146
15147 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15148 {
15149         struct drm_device *dev = crtc->base.dev;
15150         struct intel_encoder *encoder;
15151
15152         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15153                 return true;
15154
15155         return false;
15156 }
15157
15158 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15159 {
15160         struct drm_device *dev = encoder->base.dev;
15161         struct intel_connector *connector;
15162
15163         for_each_connector_on_encoder(dev, &encoder->base, connector)
15164                 return connector;
15165
15166         return NULL;
15167 }
15168
15169 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15170                               enum transcoder pch_transcoder)
15171 {
15172         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15173                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15174 }
15175
15176 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15177 {
15178         struct drm_device *dev = crtc->base.dev;
15179         struct drm_i915_private *dev_priv = to_i915(dev);
15180         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15181
15182         /* Clear any frame start delays used for debugging left by the BIOS */
15183         if (!transcoder_is_dsi(cpu_transcoder)) {
15184                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15185
15186                 I915_WRITE(reg,
15187                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15188         }
15189
15190         /* restore vblank interrupts to correct state */
15191         drm_crtc_vblank_reset(&crtc->base);
15192         if (crtc->active) {
15193                 struct intel_plane *plane;
15194
15195                 drm_crtc_vblank_on(&crtc->base);
15196
15197                 /* Disable everything but the primary plane */
15198                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15199                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15200                                 continue;
15201
15202                         trace_intel_disable_plane(&plane->base, crtc);
15203                         plane->disable_plane(&plane->base, &crtc->base);
15204                 }
15205         }
15206
15207         /* We need to sanitize the plane -> pipe mapping first because this will
15208          * disable the crtc (and hence change the state) if it is wrong. Note
15209          * that gen4+ has a fixed plane -> pipe mapping.  */
15210         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15211                 bool plane;
15212
15213                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15214                               crtc->base.base.id, crtc->base.name);
15215
15216                 /* Pipe has the wrong plane attached and the plane is active.
15217                  * Temporarily change the plane mapping and disable everything
15218                  * ...  */
15219                 plane = crtc->plane;
15220                 crtc->base.primary->state->visible = true;
15221                 crtc->plane = !plane;
15222                 intel_crtc_disable_noatomic(&crtc->base);
15223                 crtc->plane = plane;
15224         }
15225
15226         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15227             crtc->pipe == PIPE_A && !crtc->active) {
15228                 /* BIOS forgot to enable pipe A, this mostly happens after
15229                  * resume. Force-enable the pipe to fix this, the update_dpms
15230                  * call below we restore the pipe to the right state, but leave
15231                  * the required bits on. */
15232                 intel_enable_pipe_a(dev);
15233         }
15234
15235         /* Adjust the state of the output pipe according to whether we
15236          * have active connectors/encoders. */
15237         if (crtc->active && !intel_crtc_has_encoders(crtc))
15238                 intel_crtc_disable_noatomic(&crtc->base);
15239
15240         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15241                 /*
15242                  * We start out with underrun reporting disabled to avoid races.
15243                  * For correct bookkeeping mark this on active crtcs.
15244                  *
15245                  * Also on gmch platforms we dont have any hardware bits to
15246                  * disable the underrun reporting. Which means we need to start
15247                  * out with underrun reporting disabled also on inactive pipes,
15248                  * since otherwise we'll complain about the garbage we read when
15249                  * e.g. coming up after runtime pm.
15250                  *
15251                  * No protection against concurrent access is required - at
15252                  * worst a fifo underrun happens which also sets this to false.
15253                  */
15254                 crtc->cpu_fifo_underrun_disabled = true;
15255                 /*
15256                  * We track the PCH trancoder underrun reporting state
15257                  * within the crtc. With crtc for pipe A housing the underrun
15258                  * reporting state for PCH transcoder A, crtc for pipe B housing
15259                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15260                  * and marking underrun reporting as disabled for the non-existing
15261                  * PCH transcoders B and C would prevent enabling the south
15262                  * error interrupt (see cpt_can_enable_serr_int()).
15263                  */
15264                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15265                         crtc->pch_fifo_underrun_disabled = true;
15266         }
15267 }
15268
15269 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15270 {
15271         struct intel_connector *connector;
15272
15273         /* We need to check both for a crtc link (meaning that the
15274          * encoder is active and trying to read from a pipe) and the
15275          * pipe itself being active. */
15276         bool has_active_crtc = encoder->base.crtc &&
15277                 to_intel_crtc(encoder->base.crtc)->active;
15278
15279         connector = intel_encoder_find_connector(encoder);
15280         if (connector && !has_active_crtc) {
15281                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15282                               encoder->base.base.id,
15283                               encoder->base.name);
15284
15285                 /* Connector is active, but has no active pipe. This is
15286                  * fallout from our resume register restoring. Disable
15287                  * the encoder manually again. */
15288                 if (encoder->base.crtc) {
15289                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15290
15291                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15292                                       encoder->base.base.id,
15293                                       encoder->base.name);
15294                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15295                         if (encoder->post_disable)
15296                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15297                 }
15298                 encoder->base.crtc = NULL;
15299
15300                 /* Inconsistent output/port/pipe state happens presumably due to
15301                  * a bug in one of the get_hw_state functions. Or someplace else
15302                  * in our code, like the register restore mess on resume. Clamp
15303                  * things to off as a safer default. */
15304
15305                 connector->base.dpms = DRM_MODE_DPMS_OFF;
15306                 connector->base.encoder = NULL;
15307         }
15308         /* Enabled encoders without active connectors will be fixed in
15309          * the crtc fixup. */
15310 }
15311
15312 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15313 {
15314         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15315
15316         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15317                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15318                 i915_disable_vga(dev_priv);
15319         }
15320 }
15321
15322 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15323 {
15324         /* This function can be called both from intel_modeset_setup_hw_state or
15325          * at a very early point in our resume sequence, where the power well
15326          * structures are not yet restored. Since this function is at a very
15327          * paranoid "someone might have enabled VGA while we were not looking"
15328          * level, just check if the power well is enabled instead of trying to
15329          * follow the "don't touch the power well if we don't need it" policy
15330          * the rest of the driver uses. */
15331         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15332                 return;
15333
15334         i915_redisable_vga_power_on(dev_priv);
15335
15336         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15337 }
15338
15339 static bool primary_get_hw_state(struct intel_plane *plane)
15340 {
15341         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15342
15343         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15344 }
15345
15346 /* FIXME read out full plane state for all planes */
15347 static void readout_plane_state(struct intel_crtc *crtc)
15348 {
15349         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
15350         bool visible;
15351
15352         visible = crtc->active && primary_get_hw_state(primary);
15353
15354         intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
15355                                 to_intel_plane_state(primary->base.state),
15356                                 visible);
15357 }
15358
15359 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15360 {
15361         struct drm_i915_private *dev_priv = to_i915(dev);
15362         enum pipe pipe;
15363         struct intel_crtc *crtc;
15364         struct intel_encoder *encoder;
15365         struct intel_connector *connector;
15366         struct drm_connector_list_iter conn_iter;
15367         int i;
15368
15369         dev_priv->active_crtcs = 0;
15370
15371         for_each_intel_crtc(dev, crtc) {
15372                 struct intel_crtc_state *crtc_state =
15373                         to_intel_crtc_state(crtc->base.state);
15374
15375                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15376                 memset(crtc_state, 0, sizeof(*crtc_state));
15377                 crtc_state->base.crtc = &crtc->base;
15378
15379                 crtc_state->base.active = crtc_state->base.enable =
15380                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15381
15382                 crtc->base.enabled = crtc_state->base.enable;
15383                 crtc->active = crtc_state->base.active;
15384
15385                 if (crtc_state->base.active)
15386                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15387
15388                 readout_plane_state(crtc);
15389
15390                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15391                               crtc->base.base.id, crtc->base.name,
15392                               enableddisabled(crtc_state->base.active));
15393         }
15394
15395         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15396                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15397
15398                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15399                                                   &pll->state.hw_state);
15400                 pll->state.crtc_mask = 0;
15401                 for_each_intel_crtc(dev, crtc) {
15402                         struct intel_crtc_state *crtc_state =
15403                                 to_intel_crtc_state(crtc->base.state);
15404
15405                         if (crtc_state->base.active &&
15406                             crtc_state->shared_dpll == pll)
15407                                 pll->state.crtc_mask |= 1 << crtc->pipe;
15408                 }
15409                 pll->active_mask = pll->state.crtc_mask;
15410
15411                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15412                               pll->name, pll->state.crtc_mask, pll->on);
15413         }
15414
15415         for_each_intel_encoder(dev, encoder) {
15416                 pipe = 0;
15417
15418                 if (encoder->get_hw_state(encoder, &pipe)) {
15419                         struct intel_crtc_state *crtc_state;
15420
15421                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15422                         crtc_state = to_intel_crtc_state(crtc->base.state);
15423
15424                         encoder->base.crtc = &crtc->base;
15425                         crtc_state->output_types |= 1 << encoder->type;
15426                         encoder->get_config(encoder, crtc_state);
15427                 } else {
15428                         encoder->base.crtc = NULL;
15429                 }
15430
15431                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15432                               encoder->base.base.id, encoder->base.name,
15433                               enableddisabled(encoder->base.crtc),
15434                               pipe_name(pipe));
15435         }
15436
15437         drm_connector_list_iter_begin(dev, &conn_iter);
15438         for_each_intel_connector_iter(connector, &conn_iter) {
15439                 if (connector->get_hw_state(connector)) {
15440                         connector->base.dpms = DRM_MODE_DPMS_ON;
15441
15442                         encoder = connector->encoder;
15443                         connector->base.encoder = &encoder->base;
15444
15445                         if (encoder->base.crtc &&
15446                             encoder->base.crtc->state->active) {
15447                                 /*
15448                                  * This has to be done during hardware readout
15449                                  * because anything calling .crtc_disable may
15450                                  * rely on the connector_mask being accurate.
15451                                  */
15452                                 encoder->base.crtc->state->connector_mask |=
15453                                         1 << drm_connector_index(&connector->base);
15454                                 encoder->base.crtc->state->encoder_mask |=
15455                                         1 << drm_encoder_index(&encoder->base);
15456                         }
15457
15458                 } else {
15459                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15460                         connector->base.encoder = NULL;
15461                 }
15462                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15463                               connector->base.base.id, connector->base.name,
15464                               enableddisabled(connector->base.encoder));
15465         }
15466         drm_connector_list_iter_end(&conn_iter);
15467
15468         for_each_intel_crtc(dev, crtc) {
15469                 struct intel_crtc_state *crtc_state =
15470                         to_intel_crtc_state(crtc->base.state);
15471                 int pixclk = 0;
15472
15473                 crtc->base.hwmode = crtc_state->base.adjusted_mode;
15474
15475                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15476                 if (crtc_state->base.active) {
15477                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15478                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15479                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15480
15481                         /*
15482                          * The initial mode needs to be set in order to keep
15483                          * the atomic core happy. It wants a valid mode if the
15484                          * crtc's enabled, so we do the above call.
15485                          *
15486                          * But we don't set all the derived state fully, hence
15487                          * set a flag to indicate that a full recalculation is
15488                          * needed on the next commit.
15489                          */
15490                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15491
15492                         intel_crtc_compute_pixel_rate(crtc_state);
15493
15494                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15495                             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15496                                 pixclk = crtc_state->pixel_rate;
15497                         else
15498                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15499
15500                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15501                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15502                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15503
15504                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15505                         update_scanline_offset(crtc);
15506                 }
15507
15508                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15509
15510                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15511         }
15512 }
15513
15514 static void
15515 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15516 {
15517         struct intel_encoder *encoder;
15518
15519         for_each_intel_encoder(&dev_priv->drm, encoder) {
15520                 u64 get_domains;
15521                 enum intel_display_power_domain domain;
15522
15523                 if (!encoder->get_power_domains)
15524                         continue;
15525
15526                 get_domains = encoder->get_power_domains(encoder);
15527                 for_each_power_domain(domain, get_domains)
15528                         intel_display_power_get(dev_priv, domain);
15529         }
15530 }
15531
15532 /* Scan out the current hw modeset state,
15533  * and sanitizes it to the current state
15534  */
15535 static void
15536 intel_modeset_setup_hw_state(struct drm_device *dev)
15537 {
15538         struct drm_i915_private *dev_priv = to_i915(dev);
15539         enum pipe pipe;
15540         struct intel_crtc *crtc;
15541         struct intel_encoder *encoder;
15542         int i;
15543
15544         intel_modeset_readout_hw_state(dev);
15545
15546         /* HW state is read out, now we need to sanitize this mess. */
15547         get_encoder_power_domains(dev_priv);
15548
15549         for_each_intel_encoder(dev, encoder) {
15550                 intel_sanitize_encoder(encoder);
15551         }
15552
15553         for_each_pipe(dev_priv, pipe) {
15554                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15555
15556                 intel_sanitize_crtc(crtc);
15557                 intel_dump_pipe_config(crtc, crtc->config,
15558                                        "[setup_hw_state]");
15559         }
15560
15561         intel_modeset_update_connector_atomic_state(dev);
15562
15563         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15564                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15565
15566                 if (!pll->on || pll->active_mask)
15567                         continue;
15568
15569                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15570
15571                 pll->funcs.disable(dev_priv, pll);
15572                 pll->on = false;
15573         }
15574
15575         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15576                 vlv_wm_get_hw_state(dev);
15577                 vlv_wm_sanitize(dev_priv);
15578         } else if (IS_GEN9(dev_priv)) {
15579                 skl_wm_get_hw_state(dev);
15580         } else if (HAS_PCH_SPLIT(dev_priv)) {
15581                 ilk_wm_get_hw_state(dev);
15582         }
15583
15584         for_each_intel_crtc(dev, crtc) {
15585                 u64 put_domains;
15586
15587                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15588                 if (WARN_ON(put_domains))
15589                         modeset_put_power_domains(dev_priv, put_domains);
15590         }
15591         intel_display_set_init_power(dev_priv, false);
15592
15593         intel_power_domains_verify_state(dev_priv);
15594
15595         intel_fbc_init_pipe_state(dev_priv);
15596 }
15597
15598 void intel_display_resume(struct drm_device *dev)
15599 {
15600         struct drm_i915_private *dev_priv = to_i915(dev);
15601         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15602         struct drm_modeset_acquire_ctx ctx;
15603         int ret;
15604
15605         dev_priv->modeset_restore_state = NULL;
15606         if (state)
15607                 state->acquire_ctx = &ctx;
15608
15609         /*
15610          * This is a cludge because with real atomic modeset mode_config.mutex
15611          * won't be taken. Unfortunately some probed state like
15612          * audio_codec_enable is still protected by mode_config.mutex, so lock
15613          * it here for now.
15614          */
15615         mutex_lock(&dev->mode_config.mutex);
15616         drm_modeset_acquire_init(&ctx, 0);
15617
15618         while (1) {
15619                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15620                 if (ret != -EDEADLK)
15621                         break;
15622
15623                 drm_modeset_backoff(&ctx);
15624         }
15625
15626         if (!ret)
15627                 ret = __intel_display_resume(dev, state, &ctx);
15628
15629         drm_modeset_drop_locks(&ctx);
15630         drm_modeset_acquire_fini(&ctx);
15631         mutex_unlock(&dev->mode_config.mutex);
15632
15633         if (ret)
15634                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15635         if (state)
15636                 drm_atomic_state_put(state);
15637 }
15638
15639 void intel_modeset_gem_init(struct drm_device *dev)
15640 {
15641         struct drm_i915_private *dev_priv = to_i915(dev);
15642
15643         intel_init_gt_powersave(dev_priv);
15644
15645         intel_setup_overlay(dev_priv);
15646 }
15647
15648 int intel_connector_register(struct drm_connector *connector)
15649 {
15650         struct intel_connector *intel_connector = to_intel_connector(connector);
15651         int ret;
15652
15653         ret = intel_backlight_device_register(intel_connector);
15654         if (ret)
15655                 goto err;
15656
15657         return 0;
15658
15659 err:
15660         return ret;
15661 }
15662
15663 void intel_connector_unregister(struct drm_connector *connector)
15664 {
15665         struct intel_connector *intel_connector = to_intel_connector(connector);
15666
15667         intel_backlight_device_unregister(intel_connector);
15668         intel_panel_destroy_backlight(connector);
15669 }
15670
15671 void intel_modeset_cleanup(struct drm_device *dev)
15672 {
15673         struct drm_i915_private *dev_priv = to_i915(dev);
15674
15675         flush_work(&dev_priv->atomic_helper.free_work);
15676         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15677
15678         intel_disable_gt_powersave(dev_priv);
15679
15680         /*
15681          * Interrupts and polling as the first thing to avoid creating havoc.
15682          * Too much stuff here (turning of connectors, ...) would
15683          * experience fancy races otherwise.
15684          */
15685         intel_irq_uninstall(dev_priv);
15686
15687         /*
15688          * Due to the hpd irq storm handling the hotplug work can re-arm the
15689          * poll handlers. Hence disable polling after hpd handling is shut down.
15690          */
15691         drm_kms_helper_poll_fini(dev);
15692
15693         intel_unregister_dsm_handler();
15694
15695         intel_fbc_global_disable(dev_priv);
15696
15697         /* flush any delayed tasks or pending work */
15698         flush_scheduled_work();
15699
15700         drm_mode_config_cleanup(dev);
15701
15702         intel_cleanup_overlay(dev_priv);
15703
15704         intel_cleanup_gt_powersave(dev_priv);
15705
15706         intel_teardown_gmbus(dev_priv);
15707 }
15708
15709 void intel_connector_attach_encoder(struct intel_connector *connector,
15710                                     struct intel_encoder *encoder)
15711 {
15712         connector->encoder = encoder;
15713         drm_mode_connector_attach_encoder(&connector->base,
15714                                           &encoder->base);
15715 }
15716
15717 /*
15718  * set vga decode state - true == enable VGA decode
15719  */
15720 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15721 {
15722         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15723         u16 gmch_ctrl;
15724
15725         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15726                 DRM_ERROR("failed to read control word\n");
15727                 return -EIO;
15728         }
15729
15730         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15731                 return 0;
15732
15733         if (state)
15734                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15735         else
15736                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15737
15738         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15739                 DRM_ERROR("failed to write control word\n");
15740                 return -EIO;
15741         }
15742
15743         return 0;
15744 }
15745
15746 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15747
15748 struct intel_display_error_state {
15749
15750         u32 power_well_driver;
15751
15752         int num_transcoders;
15753
15754         struct intel_cursor_error_state {
15755                 u32 control;
15756                 u32 position;
15757                 u32 base;
15758                 u32 size;
15759         } cursor[I915_MAX_PIPES];
15760
15761         struct intel_pipe_error_state {
15762                 bool power_domain_on;
15763                 u32 source;
15764                 u32 stat;
15765         } pipe[I915_MAX_PIPES];
15766
15767         struct intel_plane_error_state {
15768                 u32 control;
15769                 u32 stride;
15770                 u32 size;
15771                 u32 pos;
15772                 u32 addr;
15773                 u32 surface;
15774                 u32 tile_offset;
15775         } plane[I915_MAX_PIPES];
15776
15777         struct intel_transcoder_error_state {
15778                 bool power_domain_on;
15779                 enum transcoder cpu_transcoder;
15780
15781                 u32 conf;
15782
15783                 u32 htotal;
15784                 u32 hblank;
15785                 u32 hsync;
15786                 u32 vtotal;
15787                 u32 vblank;
15788                 u32 vsync;
15789         } transcoder[4];
15790 };
15791
15792 struct intel_display_error_state *
15793 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15794 {
15795         struct intel_display_error_state *error;
15796         int transcoders[] = {
15797                 TRANSCODER_A,
15798                 TRANSCODER_B,
15799                 TRANSCODER_C,
15800                 TRANSCODER_EDP,
15801         };
15802         int i;
15803
15804         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15805                 return NULL;
15806
15807         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15808         if (error == NULL)
15809                 return NULL;
15810
15811         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15812                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15813
15814         for_each_pipe(dev_priv, i) {
15815                 error->pipe[i].power_domain_on =
15816                         __intel_display_power_is_enabled(dev_priv,
15817                                                          POWER_DOMAIN_PIPE(i));
15818                 if (!error->pipe[i].power_domain_on)
15819                         continue;
15820
15821                 error->cursor[i].control = I915_READ(CURCNTR(i));
15822                 error->cursor[i].position = I915_READ(CURPOS(i));
15823                 error->cursor[i].base = I915_READ(CURBASE(i));
15824
15825                 error->plane[i].control = I915_READ(DSPCNTR(i));
15826                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15827                 if (INTEL_GEN(dev_priv) <= 3) {
15828                         error->plane[i].size = I915_READ(DSPSIZE(i));
15829                         error->plane[i].pos = I915_READ(DSPPOS(i));
15830                 }
15831                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15832                         error->plane[i].addr = I915_READ(DSPADDR(i));
15833                 if (INTEL_GEN(dev_priv) >= 4) {
15834                         error->plane[i].surface = I915_READ(DSPSURF(i));
15835                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15836                 }
15837
15838                 error->pipe[i].source = I915_READ(PIPESRC(i));
15839
15840                 if (HAS_GMCH_DISPLAY(dev_priv))
15841                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15842         }
15843
15844         /* Note: this does not include DSI transcoders. */
15845         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15846         if (HAS_DDI(dev_priv))
15847                 error->num_transcoders++; /* Account for eDP. */
15848
15849         for (i = 0; i < error->num_transcoders; i++) {
15850                 enum transcoder cpu_transcoder = transcoders[i];
15851
15852                 error->transcoder[i].power_domain_on =
15853                         __intel_display_power_is_enabled(dev_priv,
15854                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15855                 if (!error->transcoder[i].power_domain_on)
15856                         continue;
15857
15858                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15859
15860                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15861                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15862                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15863                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15864                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15865                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15866                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15867         }
15868
15869         return error;
15870 }
15871
15872 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15873
15874 void
15875 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15876                                 struct intel_display_error_state *error)
15877 {
15878         struct drm_i915_private *dev_priv = m->i915;
15879         int i;
15880
15881         if (!error)
15882                 return;
15883
15884         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15885         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15886                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15887                            error->power_well_driver);
15888         for_each_pipe(dev_priv, i) {
15889                 err_printf(m, "Pipe [%d]:\n", i);
15890                 err_printf(m, "  Power: %s\n",
15891                            onoff(error->pipe[i].power_domain_on));
15892                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15893                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15894
15895                 err_printf(m, "Plane [%d]:\n", i);
15896                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15897                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15898                 if (INTEL_GEN(dev_priv) <= 3) {
15899                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15900                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15901                 }
15902                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15903                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15904                 if (INTEL_GEN(dev_priv) >= 4) {
15905                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15906                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15907                 }
15908
15909                 err_printf(m, "Cursor [%d]:\n", i);
15910                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15911                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15912                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15913         }
15914
15915         for (i = 0; i < error->num_transcoders; i++) {
15916                 err_printf(m, "CPU transcoder: %s\n",
15917                            transcoder_name(error->transcoder[i].cpu_transcoder));
15918                 err_printf(m, "  Power: %s\n",
15919                            onoff(error->transcoder[i].power_domain_on));
15920                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15921                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15922                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15923                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15924                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15925                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15926                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15927         }
15928 }
15929
15930 #endif