drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54
  55
  56 typedef struct {
  57         int     min, max;
  58 } intel_range_t;
  59
  60 typedef struct {
  61         int     dot_limit;
  62         int     p2_slow, p2_fast;
  63 } intel_p2_t;
  64
  65 typedef struct intel_limit intel_limit_t;
  66 struct intel_limit {
  67         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  68         intel_p2_t          p2;
  69 };
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 908000, .max = 1512000 },
  94         .n = { .min = 2, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 908000, .max = 1512000 },
 107         .n = { .min = 2, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 908000, .max = 1512000 },
 120         .n = { .min = 2, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv = {
 313          /*
 314           * These are the data rate limits (measured in fast clocks)
 315           * since those are the strictest limits we have. The fast
 316           * clock and actual rate limits are more relaxed, so checking
 317           * them would make no difference.
 318           */
 319         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 320         .vco = { .min = 4000000, .max = 6000000 },
 321         .n = { .min = 1, .max = 7 },
 322         .m1 = { .min = 2, .max = 3 },
 323         .m2 = { .min = 11, .max = 156 },
 324         .p1 = { .min = 2, .max = 3 },
 325         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 326 };
 327
 328 static void vlv_clock(int refclk, intel_clock_t *clock)
 329 {
 330         clock->m = clock->m1 * clock->m2;
 331         clock->p = clock->p1 * clock->p2;
 332         if (WARN_ON(clock->n == 0 || clock->p == 0))
 333                 return;
 334         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 335         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 336 }
 337
 338 /**
 339  * Returns whether any output on the specified pipe is of the specified type
 340  */
 341 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 342 {
 343         struct drm_device *dev = crtc->dev;
 344         struct intel_encoder *encoder;
 345
 346         for_each_encoder_on_crtc(dev, crtc, encoder)
 347                 if (encoder->type == type)
 348                         return true;
 349
 350         return false;
 351 }
 352
 353 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 354                                                 int refclk)
 355 {
 356         struct drm_device *dev = crtc->dev;
 357         const intel_limit_t *limit;
 358
 359         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 360                 if (intel_is_dual_link_lvds(dev)) {
 361                         if (refclk == 100000)
 362                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 363                         else
 364                                 limit = &intel_limits_ironlake_dual_lvds;
 365                 } else {
 366                         if (refclk == 100000)
 367                                 limit = &intel_limits_ironlake_single_lvds_100m;
 368                         else
 369                                 limit = &intel_limits_ironlake_single_lvds;
 370                 }
 371         } else
 372                 limit = &intel_limits_ironlake_dac;
 373
 374         return limit;
 375 }
 376
 377 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 378 {
 379         struct drm_device *dev = crtc->dev;
 380         const intel_limit_t *limit;
 381
 382         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 383                 if (intel_is_dual_link_lvds(dev))
 384                         limit = &intel_limits_g4x_dual_channel_lvds;
 385                 else
 386                         limit = &intel_limits_g4x_single_channel_lvds;
 387         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 388                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 389                 limit = &intel_limits_g4x_hdmi;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 391                 limit = &intel_limits_g4x_sdvo;
 392         } else /* The option is for other outputs */
 393                 limit = &intel_limits_i9xx_sdvo;
 394
 395         return limit;
 396 }
 397
 398 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 399 {
 400         struct drm_device *dev = crtc->dev;
 401         const intel_limit_t *limit;
 402
 403         if (HAS_PCH_SPLIT(dev))
 404                 limit = intel_ironlake_limit(crtc, refclk);
 405         else if (IS_G4X(dev)) {
 406                 limit = intel_g4x_limit(crtc);
 407         } else if (IS_PINEVIEW(dev)) {
 408                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 409                         limit = &intel_limits_pineview_lvds;
 410                 else
 411                         limit = &intel_limits_pineview_sdvo;
 412         } else if (IS_VALLEYVIEW(dev)) {
 413                 limit = &intel_limits_vlv;
 414         } else if (!IS_GEN2(dev)) {
 415                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 416                         limit = &intel_limits_i9xx_lvds;
 417                 else
 418                         limit = &intel_limits_i9xx_sdvo;
 419         } else {
 420                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 421                         limit = &intel_limits_i8xx_lvds;
 422                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 423                         limit = &intel_limits_i8xx_dvo;
 424                 else
 425                         limit = &intel_limits_i8xx_dac;
 426         }
 427         return limit;
 428 }
 429
 430 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 431 static void pineview_clock(int refclk, intel_clock_t *clock)
 432 {
 433         clock->m = clock->m2 + 2;
 434         clock->p = clock->p1 * clock->p2;
 435         if (WARN_ON(clock->n == 0 || clock->p == 0))
 436                 return;
 437         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 438         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 439 }
 440
 441 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 442 {
 443         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 444 }
 445
 446 static void i9xx_clock(int refclk, intel_clock_t *clock)
 447 {
 448         clock->m = i9xx_dpll_compute_m(clock);
 449         clock->p = clock->p1 * clock->p2;
 450         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 451                 return;
 452         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 453         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 454 }
 455
 456 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 457 /**
 458  * Returns whether the given set of divisors are valid for a given refclk with
 459  * the given connectors.
 460  */
 461
 462 static bool intel_PLL_is_valid(struct drm_device *dev,
 463                                const intel_limit_t *limit,
 464                                const intel_clock_t *clock)
 465 {
 466         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 467                 INTELPllInvalid("n out of range\n");
 468         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 469                 INTELPllInvalid("p1 out of range\n");
 470         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 471                 INTELPllInvalid("m2 out of range\n");
 472         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 473                 INTELPllInvalid("m1 out of range\n");
 474
 475         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 476                 if (clock->m1 <= clock->m2)
 477                         INTELPllInvalid("m1 <= m2\n");
 478
 479         if (!IS_VALLEYVIEW(dev)) {
 480                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 481                         INTELPllInvalid("p out of range\n");
 482                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 483                         INTELPllInvalid("m out of range\n");
 484         }
 485
 486         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 487                 INTELPllInvalid("vco out of range\n");
 488         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 489          * connector, etc., rather than just a single range.
 490          */
 491         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 492                 INTELPllInvalid("dot out of range\n");
 493
 494         return true;
 495 }
 496
 497 static bool
 498 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 499                     int target, int refclk, intel_clock_t *match_clock,
 500                     intel_clock_t *best_clock)
 501 {
 502         struct drm_device *dev = crtc->dev;
 503         intel_clock_t clock;
 504         int err = target;
 505
 506         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 507                 /*
 508                  * For LVDS just rely on its current settings for dual-channel.
 509                  * We haven't figured out how to reliably set up different
 510                  * single/dual channel state, if we even can.
 511                  */
 512                 if (intel_is_dual_link_lvds(dev))
 513                         clock.p2 = limit->p2.p2_fast;
 514                 else
 515                         clock.p2 = limit->p2.p2_slow;
 516         } else {
 517                 if (target < limit->p2.dot_limit)
 518                         clock.p2 = limit->p2.p2_slow;
 519                 else
 520                         clock.p2 = limit->p2.p2_fast;
 521         }
 522
 523         memset(best_clock, 0, sizeof(*best_clock));
 524
 525         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 526              clock.m1++) {
 527                 for (clock.m2 = limit->m2.min;
 528                      clock.m2 <= limit->m2.max; clock.m2++) {
 529                         if (clock.m2 >= clock.m1)
 530                                 break;
 531                         for (clock.n = limit->n.min;
 532                              clock.n <= limit->n.max; clock.n++) {
 533                                 for (clock.p1 = limit->p1.min;
 534                                         clock.p1 <= limit->p1.max; clock.p1++) {
 535                                         int this_err;
 536
 537                                         i9xx_clock(refclk, &clock);
 538                                         if (!intel_PLL_is_valid(dev, limit,
 539                                                                 &clock))
 540                                                 continue;
 541                                         if (match_clock &&
 542                                             clock.p != match_clock->p)
 543                                                 continue;
 544
 545                                         this_err = abs(clock.dot - target);
 546                                         if (this_err < err) {
 547                                                 *best_clock = clock;
 548                                                 err = this_err;
 549                                         }
 550                                 }
 551                         }
 552                 }
 553         }
 554
 555         return (err != target);
 556 }
 557
 558 static bool
 559 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 560                    int target, int refclk, intel_clock_t *match_clock,
 561                    intel_clock_t *best_clock)
 562 {
 563         struct drm_device *dev = crtc->dev;
 564         intel_clock_t clock;
 565         int err = target;
 566
 567         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 568                 /*
 569                  * For LVDS just rely on its current settings for dual-channel.
 570                  * We haven't figured out how to reliably set up different
 571                  * single/dual channel state, if we even can.
 572                  */
 573                 if (intel_is_dual_link_lvds(dev))
 574                         clock.p2 = limit->p2.p2_fast;
 575                 else
 576                         clock.p2 = limit->p2.p2_slow;
 577         } else {
 578                 if (target < limit->p2.dot_limit)
 579                         clock.p2 = limit->p2.p2_slow;
 580                 else
 581                         clock.p2 = limit->p2.p2_fast;
 582         }
 583
 584         memset(best_clock, 0, sizeof(*best_clock));
 585
 586         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 587              clock.m1++) {
 588                 for (clock.m2 = limit->m2.min;
 589                      clock.m2 <= limit->m2.max; clock.m2++) {
 590                         for (clock.n = limit->n.min;
 591                              clock.n <= limit->n.max; clock.n++) {
 592                                 for (clock.p1 = limit->p1.min;
 593                                         clock.p1 <= limit->p1.max; clock.p1++) {
 594                                         int this_err;
 595
 596                                         pineview_clock(refclk, &clock);
 597                                         if (!intel_PLL_is_valid(dev, limit,
 598                                                                 &clock))
 599                                                 continue;
 600                                         if (match_clock &&
 601                                             clock.p != match_clock->p)
 602                                                 continue;
 603
 604                                         this_err = abs(clock.dot - target);
 605                                         if (this_err < err) {
 606                                                 *best_clock = clock;
 607                                                 err = this_err;
 608                                         }
 609                                 }
 610                         }
 611                 }
 612         }
 613
 614         return (err != target);
 615 }
 616
 617 static bool
 618 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 619                    int target, int refclk, intel_clock_t *match_clock,
 620                    intel_clock_t *best_clock)
 621 {
 622         struct drm_device *dev = crtc->dev;
 623         intel_clock_t clock;
 624         int max_n;
 625         bool found;
 626         /* approximately equals target * 0.00585 */
 627         int err_most = (target >> 8) + (target >> 9);
 628         found = false;
 629
 630         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 631                 if (intel_is_dual_link_lvds(dev))
 632                         clock.p2 = limit->p2.p2_fast;
 633                 else
 634                         clock.p2 = limit->p2.p2_slow;
 635         } else {
 636                 if (target < limit->p2.dot_limit)
 637                         clock.p2 = limit->p2.p2_slow;
 638                 else
 639                         clock.p2 = limit->p2.p2_fast;
 640         }
 641
 642         memset(best_clock, 0, sizeof(*best_clock));
 643         max_n = limit->n.max;
 644         /* based on hardware requirement, prefer smaller n to precision */
 645         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 646                 /* based on hardware requirement, prefere larger m1,m2 */
 647                 for (clock.m1 = limit->m1.max;
 648                      clock.m1 >= limit->m1.min; clock.m1--) {
 649                         for (clock.m2 = limit->m2.max;
 650                              clock.m2 >= limit->m2.min; clock.m2--) {
 651                                 for (clock.p1 = limit->p1.max;
 652                                      clock.p1 >= limit->p1.min; clock.p1--) {
 653                                         int this_err;
 654
 655                                         i9xx_clock(refclk, &clock);
 656                                         if (!intel_PLL_is_valid(dev, limit,
 657                                                                 &clock))
 658                                                 continue;
 659
 660                                         this_err = abs(clock.dot - target);
 661                                         if (this_err < err_most) {
 662                                                 *best_clock = clock;
 663                                                 err_most = this_err;
 664                                                 max_n = clock.n;
 665                                                 found = true;
 666                                         }
 667                                 }
 668                         }
 669                 }
 670         }
 671         return found;
 672 }
 673
 674 static bool
 675 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 676                    int target, int refclk, intel_clock_t *match_clock,
 677                    intel_clock_t *best_clock)
 678 {
 679         struct drm_device *dev = crtc->dev;
 680         intel_clock_t clock;
 681         unsigned int bestppm = 1000000;
 682         /* min update 19.2 MHz */
 683         int max_n = min(limit->n.max, refclk / 19200);
 684         bool found = false;
 685
 686         target *= 5; /* fast clock */
 687
 688         memset(best_clock, 0, sizeof(*best_clock));
 689
 690         /* based on hardware requirement, prefer smaller n to precision */
 691         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 692                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 693                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 694                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 695                                 clock.p = clock.p1 * clock.p2;
 696                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 697                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 698                                         unsigned int ppm, diff;
 699
 700                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 701                                                                      refclk * clock.m1);
 702
 703                                         vlv_clock(refclk, &clock);
 704
 705                                         if (!intel_PLL_is_valid(dev, limit,
 706                                                                 &clock))
 707                                                 continue;
 708
 709                                         diff = abs(clock.dot - target);
 710                                         ppm = div_u64(1000000ULL * diff, target);
 711
 712                                         if (ppm < 100 && clock.p > best_clock->p) {
 713                                                 bestppm = 0;
 714                                                 *best_clock = clock;
 715                                                 found = true;
 716                                         }
 717
 718                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 719                                                 bestppm = ppm;
 720                                                 *best_clock = clock;
 721                                                 found = true;
 722                                         }
 723                                 }
 724                         }
 725                 }
 726         }
 727
 728         return found;
 729 }
 730
 731 bool intel_crtc_active(struct drm_crtc *crtc)
 732 {
 733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 734
 735         /* Be paranoid as we can arrive here with only partial
 736          * state retrieved from the hardware during setup.
 737          *
 738          * We can ditch the adjusted_mode.crtc_clock check as soon
 739          * as Haswell has gained clock readout/fastboot support.
 740          *
 741          * We can ditch the crtc->fb check as soon as we can
 742          * properly reconstruct framebuffers.
 743          */
 744         return intel_crtc->active && crtc->fb &&
 745                 intel_crtc->config.adjusted_mode.crtc_clock;
 746 }
 747
 748 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 749                                              enum pipe pipe)
 750 {
 751         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 752         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 753
 754         return intel_crtc->config.cpu_transcoder;
 755 }
 756
 757 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 758 {
 759         struct drm_i915_private *dev_priv = dev->dev_private;
 760         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 761
 762         frame = I915_READ(frame_reg);
 763
 764         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 765                 DRM_DEBUG_KMS("vblank wait timed out\n");
 766 }
 767
 768 /**
 769  * intel_wait_for_vblank - wait for vblank on a given pipe
 770  * @dev: drm device
 771  * @pipe: pipe to wait for
 772  *
 773  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 774  * mode setting code.
 775  */
 776 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 777 {
 778         struct drm_i915_private *dev_priv = dev->dev_private;
 779         int pipestat_reg = PIPESTAT(pipe);
 780
 781         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 782                 g4x_wait_for_vblank(dev, pipe);
 783                 return;
 784         }
 785
 786         /* Clear existing vblank status. Note this will clear any other
 787          * sticky status fields as well.
 788          *
 789          * This races with i915_driver_irq_handler() with the result
 790          * that either function could miss a vblank event.  Here it is not
 791          * fatal, as we will either wait upon the next vblank interrupt or
 792          * timeout.  Generally speaking intel_wait_for_vblank() is only
 793          * called during modeset at which time the GPU should be idle and
 794          * should *not* be performing page flips and thus not waiting on
 795          * vblanks...
 796          * Currently, the result of us stealing a vblank from the irq
 797          * handler is that a single frame will be skipped during swapbuffers.
 798          */
 799         I915_WRITE(pipestat_reg,
 800                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 801
 802         /* Wait for vblank interrupt bit to set */
 803         if (wait_for(I915_READ(pipestat_reg) &
 804                      PIPE_VBLANK_INTERRUPT_STATUS,
 805                      50))
 806                 DRM_DEBUG_KMS("vblank wait timed out\n");
 807 }
 808
 809 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 810 {
 811         struct drm_i915_private *dev_priv = dev->dev_private;
 812         u32 reg = PIPEDSL(pipe);
 813         u32 line1, line2;
 814         u32 line_mask;
 815
 816         if (IS_GEN2(dev))
 817                 line_mask = DSL_LINEMASK_GEN2;
 818         else
 819                 line_mask = DSL_LINEMASK_GEN3;
 820
 821         line1 = I915_READ(reg) & line_mask;
 822         mdelay(5);
 823         line2 = I915_READ(reg) & line_mask;
 824
 825         return line1 == line2;
 826 }
 827
 828 /*
 829  * intel_wait_for_pipe_off - wait for pipe to turn off
 830  * @dev: drm device
 831  * @pipe: pipe to wait for
 832  *
 833  * After disabling a pipe, we can't wait for vblank in the usual way,
 834  * spinning on the vblank interrupt status bit, since we won't actually
 835  * see an interrupt when the pipe is disabled.
 836  *
 837  * On Gen4 and above:
 838  *   wait for the pipe register state bit to turn off
 839  *
 840  * Otherwise:
 841  *   wait for the display line value to settle (it usually
 842  *   ends up stopping at the start of the next frame).
 843  *
 844  */
 845 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 846 {
 847         struct drm_i915_private *dev_priv = dev->dev_private;
 848         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 849                                                                       pipe);
 850
 851         if (INTEL_INFO(dev)->gen >= 4) {
 852                 int reg = PIPECONF(cpu_transcoder);
 853
 854                 /* Wait for the Pipe State to go off */
 855                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 856                              100))
 857                         WARN(1, "pipe_off wait timed out\n");
 858         } else {
 859                 /* Wait for the display line to settle */
 860                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 861                         WARN(1, "pipe_off wait timed out\n");
 862         }
 863 }
 864
 865 /*
 866  * ibx_digital_port_connected - is the specified port connected?
 867  * @dev_priv: i915 private structure
 868  * @port: the port to test
 869  *
 870  * Returns true if @port is connected, false otherwise.
 871  */
 872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 873                                 struct intel_digital_port *port)
 874 {
 875         u32 bit;
 876
 877         if (HAS_PCH_IBX(dev_priv->dev)) {
 878                 switch(port->port) {
 879                 case PORT_B:
 880                         bit = SDE_PORTB_HOTPLUG;
 881                         break;
 882                 case PORT_C:
 883                         bit = SDE_PORTC_HOTPLUG;
 884                         break;
 885                 case PORT_D:
 886                         bit = SDE_PORTD_HOTPLUG;
 887                         break;
 888                 default:
 889                         return true;
 890                 }
 891         } else {
 892                 switch(port->port) {
 893                 case PORT_B:
 894                         bit = SDE_PORTB_HOTPLUG_CPT;
 895                         break;
 896                 case PORT_C:
 897                         bit = SDE_PORTC_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_D:
 900                         bit = SDE_PORTD_HOTPLUG_CPT;
 901                         break;
 902                 default:
 903                         return true;
 904                 }
 905         }
 906
 907         return I915_READ(SDEISR) & bit;
 908 }
 909
 910 static const char *state_string(bool enabled)
 911 {
 912         return enabled ? "on" : "off";
 913 }
 914
 915 /* Only for pre-ILK configs */
 916 void assert_pll(struct drm_i915_private *dev_priv,
 917                 enum pipe pipe, bool state)
 918 {
 919         int reg;
 920         u32 val;
 921         bool cur_state;
 922
 923         reg = DPLL(pipe);
 924         val = I915_READ(reg);
 925         cur_state = !!(val & DPLL_VCO_ENABLE);
 926         WARN(cur_state != state,
 927              "PLL state assertion failure (expected %s, current %s)\n",
 928              state_string(state), state_string(cur_state));
 929 }
 930
 931 /* XXX: the dsi pll is shared between MIPI DSI ports */
 932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 933 {
 934         u32 val;
 935         bool cur_state;
 936
 937         mutex_lock(&dev_priv->dpio_lock);
 938         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 939         mutex_unlock(&dev_priv->dpio_lock);
 940
 941         cur_state = val & DSI_PLL_VCO_EN;
 942         WARN(cur_state != state,
 943              "DSI PLL state assertion failure (expected %s, current %s)\n",
 944              state_string(state), state_string(cur_state));
 945 }
 946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 948
 949 struct intel_shared_dpll *
 950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 951 {
 952         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 953
 954         if (crtc->config.shared_dpll < 0)
 955                 return NULL;
 956
 957         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 958 }
 959
 960 /* For ILK+ */
 961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 962                         struct intel_shared_dpll *pll,
 963                         bool state)
 964 {
 965         bool cur_state;
 966         struct intel_dpll_hw_state hw_state;
 967
 968         if (HAS_PCH_LPT(dev_priv->dev)) {
 969                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 970                 return;
 971         }
 972
 973         if (WARN (!pll,
 974                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 975                 return;
 976
 977         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 978         WARN(cur_state != state,
 979              "%s assertion failure (expected %s, current %s)\n",
 980              pll->name, state_string(state), state_string(cur_state));
 981 }
 982
 983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 984                           enum pipe pipe, bool state)
 985 {
 986         int reg;
 987         u32 val;
 988         bool cur_state;
 989         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 990                                                                       pipe);
 991
 992         if (HAS_DDI(dev_priv->dev)) {
 993                 /* DDI does not have a specific FDI_TX register */
 994                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 995                 val = I915_READ(reg);
 996                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 997         } else {
 998                 reg = FDI_TX_CTL(pipe);
 999                 val = I915_READ(reg);
1000                 cur_state = !!(val & FDI_TX_ENABLE);
1001         }
1002         WARN(cur_state != state,
1003              "FDI TX state assertion failure (expected %s, current %s)\n",
1004              state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010                           enum pipe pipe, bool state)
1011 {
1012         int reg;
1013         u32 val;
1014         bool cur_state;
1015
1016         reg = FDI_RX_CTL(pipe);
1017         val = I915_READ(reg);
1018         cur_state = !!(val & FDI_RX_ENABLE);
1019         WARN(cur_state != state,
1020              "FDI RX state assertion failure (expected %s, current %s)\n",
1021              state_string(state), state_string(cur_state));
1022 }
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027                                       enum pipe pipe)
1028 {
1029         int reg;
1030         u32 val;
1031
1032         /* ILK FDI PLL is always enabled */
1033         if (dev_priv->info->gen == 5)
1034                 return;
1035
1036         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037         if (HAS_DDI(dev_priv->dev))
1038                 return;
1039
1040         reg = FDI_TX_CTL(pipe);
1041         val = I915_READ(reg);
1042         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043 }
1044
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046                        enum pipe pipe, bool state)
1047 {
1048         int reg;
1049         u32 val;
1050         bool cur_state;
1051
1052         reg = FDI_RX_CTL(pipe);
1053         val = I915_READ(reg);
1054         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055         WARN(cur_state != state,
1056              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057              state_string(state), state_string(cur_state));
1058 }
1059
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061                                   enum pipe pipe)
1062 {
1063         int pp_reg, lvds_reg;
1064         u32 val;
1065         enum pipe panel_pipe = PIPE_A;
1066         bool locked = true;
1067
1068         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069                 pp_reg = PCH_PP_CONTROL;
1070                 lvds_reg = PCH_LVDS;
1071         } else {
1072                 pp_reg = PP_CONTROL;
1073                 lvds_reg = LVDS;
1074         }
1075
1076         val = I915_READ(pp_reg);
1077         if (!(val & PANEL_POWER_ON) ||
1078             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079                 locked = false;
1080
1081         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082                 panel_pipe = PIPE_B;
1083
1084         WARN(panel_pipe == pipe && locked,
1085              "panel assertion failure, pipe %c regs locked\n",
1086              pipe_name(pipe));
1087 }
1088
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090                           enum pipe pipe, bool state)
1091 {
1092         struct drm_device *dev = dev_priv->dev;
1093         bool cur_state;
1094
1095         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097         else if (IS_845G(dev) || IS_I865G(dev))
1098                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099         else
1100                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102         WARN(cur_state != state,
1103              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104              pipe_name(pipe), state_string(state), state_string(cur_state));
1105 }
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110                  enum pipe pipe, bool state)
1111 {
1112         int reg;
1113         u32 val;
1114         bool cur_state;
1115         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116                                                                       pipe);
1117
1118         /* if we need the pipe A quirk it must be always on */
1119         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120                 state = true;
1121
1122         if (!intel_display_power_enabled(dev_priv->dev,
1123                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1124                 cur_state = false;
1125         } else {
1126                 reg = PIPECONF(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & PIPECONF_ENABLE);
1129         }
1130
1131         WARN(cur_state != state,
1132              "pipe %c assertion failure (expected %s, current %s)\n",
1133              pipe_name(pipe), state_string(state), state_string(cur_state));
1134 }
1135
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137                          enum plane plane, bool state)
1138 {
1139         int reg;
1140         u32 val;
1141         bool cur_state;
1142
1143         reg = DSPCNTR(plane);
1144         val = I915_READ(reg);
1145         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146         WARN(cur_state != state,
1147              "plane %c assertion failure (expected %s, current %s)\n",
1148              plane_name(plane), state_string(state), state_string(cur_state));
1149 }
1150
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155                                    enum pipe pipe)
1156 {
1157         struct drm_device *dev = dev_priv->dev;
1158         int reg, i;
1159         u32 val;
1160         int cur_pipe;
1161
1162         /* Primary planes are fixed to pipes on gen4+ */
1163         if (INTEL_INFO(dev)->gen >= 4) {
1164                 reg = DSPCNTR(pipe);
1165                 val = I915_READ(reg);
1166                 WARN((val & DISPLAY_PLANE_ENABLE),
1167                      "plane %c assertion failure, should be disabled but not\n",
1168                      plane_name(pipe));
1169                 return;
1170         }
1171
1172         /* Need to check both planes against the pipe */
1173         for_each_pipe(i) {
1174                 reg = DSPCNTR(i);
1175                 val = I915_READ(reg);
1176                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177                         DISPPLANE_SEL_PIPE_SHIFT;
1178                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180                      plane_name(i), pipe_name(pipe));
1181         }
1182 }
1183
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185                                     enum pipe pipe)
1186 {
1187         struct drm_device *dev = dev_priv->dev;
1188         int reg, i;
1189         u32 val;
1190
1191         if (IS_VALLEYVIEW(dev)) {
1192                 for (i = 0; i < dev_priv->num_plane; i++) {
1193                         reg = SPCNTR(pipe, i);
1194                         val = I915_READ(reg);
1195                         WARN((val & SP_ENABLE),
1196                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197                              sprite_name(pipe, i), pipe_name(pipe));
1198                 }
1199         } else if (INTEL_INFO(dev)->gen >= 7) {
1200                 reg = SPRCTL(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & SPRITE_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         } else if (INTEL_INFO(dev)->gen >= 5) {
1206                 reg = DVSCNTR(pipe);
1207                 val = I915_READ(reg);
1208                 WARN((val & DVS_ENABLE),
1209                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210                      plane_name(pipe), pipe_name(pipe));
1211         }
1212 }
1213
1214 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215 {
1216         u32 val;
1217         bool enabled;
1218
1219         if (HAS_PCH_LPT(dev_priv->dev)) {
1220                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221                 return;
1222         }
1223
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367         if (!IS_VALLEYVIEW(dev))
1368                 return;
1369
1370         /* Enable the CRI clock source so we can get at the display */
1371         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1372                    DPLL_INTEGRATED_CRI_CLK_VLV);
1373
1374         DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1375 }
1376
1377 static void intel_reset_dpio(struct drm_device *dev)
1378 {
1379         struct drm_i915_private *dev_priv = dev->dev_private;
1380
1381         if (!IS_VALLEYVIEW(dev))
1382                 return;
1383
1384         /*
1385          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1386          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1387          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1388          *   b. The other bits such as sfr settings / modesel may all be set
1389          *      to 0.
1390          *
1391          * This should only be done on init and resume from S3 with both
1392          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1393          */
1394         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1395 }
1396
1397 static void vlv_enable_pll(struct intel_crtc *crtc)
1398 {
1399         struct drm_device *dev = crtc->base.dev;
1400         struct drm_i915_private *dev_priv = dev->dev_private;
1401         int reg = DPLL(crtc->pipe);
1402         u32 dpll = crtc->config.dpll_hw_state.dpll;
1403
1404         assert_pipe_disabled(dev_priv, crtc->pipe);
1405
1406         /* No really, not for ILK+ */
1407         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1408
1409         /* PLL is protected by panel, make sure we can write it */
1410         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1411                 assert_panel_unlocked(dev_priv, crtc->pipe);
1412
1413         I915_WRITE(reg, dpll);
1414         POSTING_READ(reg);
1415         udelay(150);
1416
1417         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1418                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1419
1420         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1421         POSTING_READ(DPLL_MD(crtc->pipe));
1422
1423         /* We do this three times for luck */
1424         I915_WRITE(reg, dpll);
1425         POSTING_READ(reg);
1426         udelay(150); /* wait for warmup */
1427         I915_WRITE(reg, dpll);
1428         POSTING_READ(reg);
1429         udelay(150); /* wait for warmup */
1430         I915_WRITE(reg, dpll);
1431         POSTING_READ(reg);
1432         udelay(150); /* wait for warmup */
1433 }
1434
1435 static void i9xx_enable_pll(struct intel_crtc *crtc)
1436 {
1437         struct drm_device *dev = crtc->base.dev;
1438         struct drm_i915_private *dev_priv = dev->dev_private;
1439         int reg = DPLL(crtc->pipe);
1440         u32 dpll = crtc->config.dpll_hw_state.dpll;
1441
1442         assert_pipe_disabled(dev_priv, crtc->pipe);
1443
1444         /* No really, not for ILK+ */
1445         BUG_ON(dev_priv->info->gen >= 5);
1446
1447         /* PLL is protected by panel, make sure we can write it */
1448         if (IS_MOBILE(dev) && !IS_I830(dev))
1449                 assert_panel_unlocked(dev_priv, crtc->pipe);
1450
1451         I915_WRITE(reg, dpll);
1452
1453         /* Wait for the clocks to stabilize. */
1454         POSTING_READ(reg);
1455         udelay(150);
1456
1457         if (INTEL_INFO(dev)->gen >= 4) {
1458                 I915_WRITE(DPLL_MD(crtc->pipe),
1459                            crtc->config.dpll_hw_state.dpll_md);
1460         } else {
1461                 /* The pixel multiplier can only be updated once the
1462                  * DPLL is enabled and the clocks are stable.
1463                  *
1464                  * So write it again.
1465                  */
1466                 I915_WRITE(reg, dpll);
1467         }
1468
1469         /* We do this three times for luck */
1470         I915_WRITE(reg, dpll);
1471         POSTING_READ(reg);
1472         udelay(150); /* wait for warmup */
1473         I915_WRITE(reg, dpll);
1474         POSTING_READ(reg);
1475         udelay(150); /* wait for warmup */
1476         I915_WRITE(reg, dpll);
1477         POSTING_READ(reg);
1478         udelay(150); /* wait for warmup */
1479 }
1480
1481 /**
1482  * i9xx_disable_pll - disable a PLL
1483  * @dev_priv: i915 private structure
1484  * @pipe: pipe PLL to disable
1485  *
1486  * Disable the PLL for @pipe, making sure the pipe is off first.
1487  *
1488  * Note!  This is for pre-ILK only.
1489  */
1490 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1491 {
1492         /* Don't disable pipe A or pipe A PLLs if needed */
1493         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1494                 return;
1495
1496         /* Make sure the pipe isn't still relying on us */
1497         assert_pipe_disabled(dev_priv, pipe);
1498
1499         I915_WRITE(DPLL(pipe), 0);
1500         POSTING_READ(DPLL(pipe));
1501 }
1502
1503 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1504 {
1505         u32 val = 0;
1506
1507         /* Make sure the pipe isn't still relying on us */
1508         assert_pipe_disabled(dev_priv, pipe);
1509
1510         /* Leave integrated clock source enabled */
1511         if (pipe == PIPE_B)
1512                 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1513         I915_WRITE(DPLL(pipe), val);
1514         POSTING_READ(DPLL(pipe));
1515 }
1516
1517 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1518                 struct intel_digital_port *dport)
1519 {
1520         u32 port_mask;
1521
1522         switch (dport->port) {
1523         case PORT_B:
1524                 port_mask = DPLL_PORTB_READY_MASK;
1525                 break;
1526         case PORT_C:
1527                 port_mask = DPLL_PORTC_READY_MASK;
1528                 break;
1529         default:
1530                 BUG();
1531         }
1532
1533         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1534                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1535                      port_name(dport->port), I915_READ(DPLL(0)));
1536 }
1537
1538 /**
1539  * ironlake_enable_shared_dpll - enable PCH PLL
1540  * @dev_priv: i915 private structure
1541  * @pipe: pipe PLL to enable
1542  *
1543  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1544  * drives the transcoder clock.
1545  */
1546 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1547 {
1548         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1549         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1550
1551         /* PCH PLLs only available on ILK, SNB and IVB */
1552         BUG_ON(dev_priv->info->gen < 5);
1553         if (WARN_ON(pll == NULL))
1554                 return;
1555
1556         if (WARN_ON(pll->refcount == 0))
1557                 return;
1558
1559         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1560                       pll->name, pll->active, pll->on,
1561                       crtc->base.base.id);
1562
1563         if (pll->active++) {
1564                 WARN_ON(!pll->on);
1565                 assert_shared_dpll_enabled(dev_priv, pll);
1566                 return;
1567         }
1568         WARN_ON(pll->on);
1569
1570         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1571         pll->enable(dev_priv, pll);
1572         pll->on = true;
1573 }
1574
1575 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1576 {
1577         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1578         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1579
1580         /* PCH only available on ILK+ */
1581         BUG_ON(dev_priv->info->gen < 5);
1582         if (WARN_ON(pll == NULL))
1583                return;
1584
1585         if (WARN_ON(pll->refcount == 0))
1586                 return;
1587
1588         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1589                       pll->name, pll->active, pll->on,
1590                       crtc->base.base.id);
1591
1592         if (WARN_ON(pll->active == 0)) {
1593                 assert_shared_dpll_disabled(dev_priv, pll);
1594                 return;
1595         }
1596
1597         assert_shared_dpll_enabled(dev_priv, pll);
1598         WARN_ON(!pll->on);
1599         if (--pll->active)
1600                 return;
1601
1602         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1603         pll->disable(dev_priv, pll);
1604         pll->on = false;
1605 }
1606
1607 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1608                                            enum pipe pipe)
1609 {
1610         struct drm_device *dev = dev_priv->dev;
1611         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1612         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1613         uint32_t reg, val, pipeconf_val;
1614
1615         /* PCH only available on ILK+ */
1616         BUG_ON(dev_priv->info->gen < 5);
1617
1618         /* Make sure PCH DPLL is enabled */
1619         assert_shared_dpll_enabled(dev_priv,
1620                                    intel_crtc_to_shared_dpll(intel_crtc));
1621
1622         /* FDI must be feeding us bits for PCH ports */
1623         assert_fdi_tx_enabled(dev_priv, pipe);
1624         assert_fdi_rx_enabled(dev_priv, pipe);
1625
1626         if (HAS_PCH_CPT(dev)) {
1627                 /* Workaround: Set the timing override bit before enabling the
1628                  * pch transcoder. */
1629                 reg = TRANS_CHICKEN2(pipe);
1630                 val = I915_READ(reg);
1631                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1632                 I915_WRITE(reg, val);
1633         }
1634
1635         reg = PCH_TRANSCONF(pipe);
1636         val = I915_READ(reg);
1637         pipeconf_val = I915_READ(PIPECONF(pipe));
1638
1639         if (HAS_PCH_IBX(dev_priv->dev)) {
1640                 /*
1641                  * make the BPC in transcoder be consistent with
1642                  * that in pipeconf reg.
1643                  */
1644                 val &= ~PIPECONF_BPC_MASK;
1645                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1646         }
1647
1648         val &= ~TRANS_INTERLACE_MASK;
1649         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1650                 if (HAS_PCH_IBX(dev_priv->dev) &&
1651                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1652                         val |= TRANS_LEGACY_INTERLACED_ILK;
1653                 else
1654                         val |= TRANS_INTERLACED;
1655         else
1656                 val |= TRANS_PROGRESSIVE;
1657
1658         I915_WRITE(reg, val | TRANS_ENABLE);
1659         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1660                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1661 }
1662
1663 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1664                                       enum transcoder cpu_transcoder)
1665 {
1666         u32 val, pipeconf_val;
1667
1668         /* PCH only available on ILK+ */
1669         BUG_ON(dev_priv->info->gen < 5);
1670
1671         /* FDI must be feeding us bits for PCH ports */
1672         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1673         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1674
1675         /* Workaround: set timing override bit. */
1676         val = I915_READ(_TRANSA_CHICKEN2);
1677         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1678         I915_WRITE(_TRANSA_CHICKEN2, val);
1679
1680         val = TRANS_ENABLE;
1681         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1682
1683         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1684             PIPECONF_INTERLACED_ILK)
1685                 val |= TRANS_INTERLACED;
1686         else
1687                 val |= TRANS_PROGRESSIVE;
1688
1689         I915_WRITE(LPT_TRANSCONF, val);
1690         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1691                 DRM_ERROR("Failed to enable PCH transcoder\n");
1692 }
1693
1694 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1695                                             enum pipe pipe)
1696 {
1697         struct drm_device *dev = dev_priv->dev;
1698         uint32_t reg, val;
1699
1700         /* FDI relies on the transcoder */
1701         assert_fdi_tx_disabled(dev_priv, pipe);
1702         assert_fdi_rx_disabled(dev_priv, pipe);
1703
1704         /* Ports must be off as well */
1705         assert_pch_ports_disabled(dev_priv, pipe);
1706
1707         reg = PCH_TRANSCONF(pipe);
1708         val = I915_READ(reg);
1709         val &= ~TRANS_ENABLE;
1710         I915_WRITE(reg, val);
1711         /* wait for PCH transcoder off, transcoder state */
1712         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1713                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1714
1715         if (!HAS_PCH_IBX(dev)) {
1716                 /* Workaround: Clear the timing override chicken bit again. */
1717                 reg = TRANS_CHICKEN2(pipe);
1718                 val = I915_READ(reg);
1719                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1720                 I915_WRITE(reg, val);
1721         }
1722 }
1723
1724 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1725 {
1726         u32 val;
1727
1728         val = I915_READ(LPT_TRANSCONF);
1729         val &= ~TRANS_ENABLE;
1730         I915_WRITE(LPT_TRANSCONF, val);
1731         /* wait for PCH transcoder off, transcoder state */
1732         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1733                 DRM_ERROR("Failed to disable PCH transcoder\n");
1734
1735         /* Workaround: clear timing override bit. */
1736         val = I915_READ(_TRANSA_CHICKEN2);
1737         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1738         I915_WRITE(_TRANSA_CHICKEN2, val);
1739 }
1740
1741 /**
1742  * intel_enable_pipe - enable a pipe, asserting requirements
1743  * @dev_priv: i915 private structure
1744  * @pipe: pipe to enable
1745  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1746  *
1747  * Enable @pipe, making sure that various hardware specific requirements
1748  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1749  *
1750  * @pipe should be %PIPE_A or %PIPE_B.
1751  *
1752  * Will wait until the pipe is actually running (i.e. first vblank) before
1753  * returning.
1754  */
1755 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1756                               bool pch_port, bool dsi)
1757 {
1758         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1759                                                                       pipe);
1760         enum pipe pch_transcoder;
1761         int reg;
1762         u32 val;
1763
1764         assert_planes_disabled(dev_priv, pipe);
1765         assert_cursor_disabled(dev_priv, pipe);
1766         assert_sprites_disabled(dev_priv, pipe);
1767
1768         if (HAS_PCH_LPT(dev_priv->dev))
1769                 pch_transcoder = TRANSCODER_A;
1770         else
1771                 pch_transcoder = pipe;
1772
1773         /*
1774          * A pipe without a PLL won't actually be able to drive bits from
1775          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1776          * need the check.
1777          */
1778         if (!HAS_PCH_SPLIT(dev_priv->dev))
1779                 if (dsi)
1780                         assert_dsi_pll_enabled(dev_priv);
1781                 else
1782                         assert_pll_enabled(dev_priv, pipe);
1783         else {
1784                 if (pch_port) {
1785                         /* if driving the PCH, we need FDI enabled */
1786                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1787                         assert_fdi_tx_pll_enabled(dev_priv,
1788                                                   (enum pipe) cpu_transcoder);
1789                 }
1790                 /* FIXME: assert CPU port conditions for SNB+ */
1791         }
1792
1793         reg = PIPECONF(cpu_transcoder);
1794         val = I915_READ(reg);
1795         if (val & PIPECONF_ENABLE)
1796                 return;
1797
1798         I915_WRITE(reg, val | PIPECONF_ENABLE);
1799         intel_wait_for_vblank(dev_priv->dev, pipe);
1800 }
1801
1802 /**
1803  * intel_disable_pipe - disable a pipe, asserting requirements
1804  * @dev_priv: i915 private structure
1805  * @pipe: pipe to disable
1806  *
1807  * Disable @pipe, making sure that various hardware specific requirements
1808  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1809  *
1810  * @pipe should be %PIPE_A or %PIPE_B.
1811  *
1812  * Will wait until the pipe has shut down before returning.
1813  */
1814 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1815                                enum pipe pipe)
1816 {
1817         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1818                                                                       pipe);
1819         int reg;
1820         u32 val;
1821
1822         /*
1823          * Make sure planes won't keep trying to pump pixels to us,
1824          * or we might hang the display.
1825          */
1826         assert_planes_disabled(dev_priv, pipe);
1827         assert_cursor_disabled(dev_priv, pipe);
1828         assert_sprites_disabled(dev_priv, pipe);
1829
1830         /* Don't disable pipe A or pipe A PLLs if needed */
1831         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1832                 return;
1833
1834         reg = PIPECONF(cpu_transcoder);
1835         val = I915_READ(reg);
1836         if ((val & PIPECONF_ENABLE) == 0)
1837                 return;
1838
1839         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1840         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1841 }
1842
1843 /*
1844  * Plane regs are double buffered, going from enabled->disabled needs a
1845  * trigger in order to latch.  The display address reg provides this.
1846  */
1847 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1848                                enum plane plane)
1849 {
1850         u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1851
1852         I915_WRITE(reg, I915_READ(reg));
1853         POSTING_READ(reg);
1854 }
1855
1856 /**
1857  * intel_enable_primary_plane - enable the primary plane on a given pipe
1858  * @dev_priv: i915 private structure
1859  * @plane: plane to enable
1860  * @pipe: pipe being fed
1861  *
1862  * Enable @plane on @pipe, making sure that @pipe is running first.
1863  */
1864 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1865                                        enum plane plane, enum pipe pipe)
1866 {
1867         struct intel_crtc *intel_crtc =
1868                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1869         int reg;
1870         u32 val;
1871
1872         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1873         assert_pipe_enabled(dev_priv, pipe);
1874
1875         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1876
1877         intel_crtc->primary_enabled = true;
1878
1879         reg = DSPCNTR(plane);
1880         val = I915_READ(reg);
1881         if (val & DISPLAY_PLANE_ENABLE)
1882                 return;
1883
1884         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1885         intel_flush_primary_plane(dev_priv, plane);
1886         intel_wait_for_vblank(dev_priv->dev, pipe);
1887 }
1888
1889 /**
1890  * intel_disable_primary_plane - disable the primary plane
1891  * @dev_priv: i915 private structure
1892  * @plane: plane to disable
1893  * @pipe: pipe consuming the data
1894  *
1895  * Disable @plane; should be an independent operation.
1896  */
1897 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1898                                         enum plane plane, enum pipe pipe)
1899 {
1900         struct intel_crtc *intel_crtc =
1901                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1902         int reg;
1903         u32 val;
1904
1905         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1906
1907         intel_crtc->primary_enabled = false;
1908
1909         reg = DSPCNTR(plane);
1910         val = I915_READ(reg);
1911         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1912                 return;
1913
1914         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1915         intel_flush_primary_plane(dev_priv, plane);
1916         intel_wait_for_vblank(dev_priv->dev, pipe);
1917 }
1918
1919 static bool need_vtd_wa(struct drm_device *dev)
1920 {
1921 #ifdef CONFIG_INTEL_IOMMU
1922         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1923                 return true;
1924 #endif
1925         return false;
1926 }
1927
1928 int
1929 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1930                            struct drm_i915_gem_object *obj,
1931                            struct intel_ring_buffer *pipelined)
1932 {
1933         struct drm_i915_private *dev_priv = dev->dev_private;
1934         u32 alignment;
1935         int ret;
1936
1937         switch (obj->tiling_mode) {
1938         case I915_TILING_NONE:
1939                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1940                         alignment = 128 * 1024;
1941                 else if (INTEL_INFO(dev)->gen >= 4)
1942                         alignment = 4 * 1024;
1943                 else
1944                         alignment = 64 * 1024;
1945                 break;
1946         case I915_TILING_X:
1947                 /* pin() will align the object as required by fence */
1948                 alignment = 0;
1949                 break;
1950         case I915_TILING_Y:
1951                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1952                 return -EINVAL;
1953         default:
1954                 BUG();
1955         }
1956
1957         /* Note that the w/a also requires 64 PTE of padding following the
1958          * bo. We currently fill all unused PTE with the shadow page and so
1959          * we should always have valid PTE following the scanout preventing
1960          * the VT-d warning.
1961          */
1962         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1963                 alignment = 256 * 1024;
1964
1965         dev_priv->mm.interruptible = false;
1966         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1967         if (ret)
1968                 goto err_interruptible;
1969
1970         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1971          * fence, whereas 965+ only requires a fence if using
1972          * framebuffer compression.  For simplicity, we always install
1973          * a fence as the cost is not that onerous.
1974          */
1975         ret = i915_gem_object_get_fence(obj);
1976         if (ret)
1977                 goto err_unpin;
1978
1979         i915_gem_object_pin_fence(obj);
1980
1981         dev_priv->mm.interruptible = true;
1982         return 0;
1983
1984 err_unpin:
1985         i915_gem_object_unpin_from_display_plane(obj);
1986 err_interruptible:
1987         dev_priv->mm.interruptible = true;
1988         return ret;
1989 }
1990
1991 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1992 {
1993         i915_gem_object_unpin_fence(obj);
1994         i915_gem_object_unpin_from_display_plane(obj);
1995 }
1996
1997 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1998  * is assumed to be a power-of-two. */
1999 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2000                                              unsigned int tiling_mode,
2001                                              unsigned int cpp,
2002                                              unsigned int pitch)
2003 {
2004         if (tiling_mode != I915_TILING_NONE) {
2005                 unsigned int tile_rows, tiles;
2006
2007                 tile_rows = *y / 8;
2008                 *y %= 8;
2009
2010                 tiles = *x / (512/cpp);
2011                 *x %= 512/cpp;
2012
2013                 return tile_rows * pitch * 8 + tiles * 4096;
2014         } else {
2015                 unsigned int offset;
2016
2017                 offset = *y * pitch + *x * cpp;
2018                 *y = 0;
2019                 *x = (offset & 4095) / cpp;
2020                 return offset & -4096;
2021         }
2022 }
2023
2024 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2025                              int x, int y)
2026 {
2027         struct drm_device *dev = crtc->dev;
2028         struct drm_i915_private *dev_priv = dev->dev_private;
2029         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2030         struct intel_framebuffer *intel_fb;
2031         struct drm_i915_gem_object *obj;
2032         int plane = intel_crtc->plane;
2033         unsigned long linear_offset;
2034         u32 dspcntr;
2035         u32 reg;
2036
2037         switch (plane) {
2038         case 0:
2039         case 1:
2040                 break;
2041         default:
2042                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2043                 return -EINVAL;
2044         }
2045
2046         intel_fb = to_intel_framebuffer(fb);
2047         obj = intel_fb->obj;
2048
2049         reg = DSPCNTR(plane);
2050         dspcntr = I915_READ(reg);
2051         /* Mask out pixel format bits in case we change it */
2052         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2053         switch (fb->pixel_format) {
2054         case DRM_FORMAT_C8:
2055                 dspcntr |= DISPPLANE_8BPP;
2056                 break;
2057         case DRM_FORMAT_XRGB1555:
2058         case DRM_FORMAT_ARGB1555:
2059                 dspcntr |= DISPPLANE_BGRX555;
2060                 break;
2061         case DRM_FORMAT_RGB565:
2062                 dspcntr |= DISPPLANE_BGRX565;
2063                 break;
2064         case DRM_FORMAT_XRGB8888:
2065         case DRM_FORMAT_ARGB8888:
2066                 dspcntr |= DISPPLANE_BGRX888;
2067                 break;
2068         case DRM_FORMAT_XBGR8888:
2069         case DRM_FORMAT_ABGR8888:
2070                 dspcntr |= DISPPLANE_RGBX888;
2071                 break;
2072         case DRM_FORMAT_XRGB2101010:
2073         case DRM_FORMAT_ARGB2101010:
2074                 dspcntr |= DISPPLANE_BGRX101010;
2075                 break;
2076         case DRM_FORMAT_XBGR2101010:
2077         case DRM_FORMAT_ABGR2101010:
2078                 dspcntr |= DISPPLANE_RGBX101010;
2079                 break;
2080         default:
2081                 BUG();
2082         }
2083
2084         if (INTEL_INFO(dev)->gen >= 4) {
2085                 if (obj->tiling_mode != I915_TILING_NONE)
2086                         dspcntr |= DISPPLANE_TILED;
2087                 else
2088                         dspcntr &= ~DISPPLANE_TILED;
2089         }
2090
2091         if (IS_G4X(dev))
2092                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2093
2094         I915_WRITE(reg, dspcntr);
2095
2096         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2097
2098         if (INTEL_INFO(dev)->gen >= 4) {
2099                 intel_crtc->dspaddr_offset =
2100                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2101                                                        fb->bits_per_pixel / 8,
2102                                                        fb->pitches[0]);
2103                 linear_offset -= intel_crtc->dspaddr_offset;
2104         } else {
2105                 intel_crtc->dspaddr_offset = linear_offset;
2106         }
2107
2108         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2109                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2110                       fb->pitches[0]);
2111         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2112         if (INTEL_INFO(dev)->gen >= 4) {
2113                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2114                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2115                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2116                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2117         } else
2118                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2119         POSTING_READ(reg);
2120
2121         return 0;
2122 }
2123
2124 static int ironlake_update_plane(struct drm_crtc *crtc,
2125                                  struct drm_framebuffer *fb, int x, int y)
2126 {
2127         struct drm_device *dev = crtc->dev;
2128         struct drm_i915_private *dev_priv = dev->dev_private;
2129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2130         struct intel_framebuffer *intel_fb;
2131         struct drm_i915_gem_object *obj;
2132         int plane = intel_crtc->plane;
2133         unsigned long linear_offset;
2134         u32 dspcntr;
2135         u32 reg;
2136
2137         switch (plane) {
2138         case 0:
2139         case 1:
2140         case 2:
2141                 break;
2142         default:
2143                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2144                 return -EINVAL;
2145         }
2146
2147         intel_fb = to_intel_framebuffer(fb);
2148         obj = intel_fb->obj;
2149
2150         reg = DSPCNTR(plane);
2151         dspcntr = I915_READ(reg);
2152         /* Mask out pixel format bits in case we change it */
2153         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2154         switch (fb->pixel_format) {
2155         case DRM_FORMAT_C8:
2156                 dspcntr |= DISPPLANE_8BPP;
2157                 break;
2158         case DRM_FORMAT_RGB565:
2159                 dspcntr |= DISPPLANE_BGRX565;
2160                 break;
2161         case DRM_FORMAT_XRGB8888:
2162         case DRM_FORMAT_ARGB8888:
2163                 dspcntr |= DISPPLANE_BGRX888;
2164                 break;
2165         case DRM_FORMAT_XBGR8888:
2166         case DRM_FORMAT_ABGR8888:
2167                 dspcntr |= DISPPLANE_RGBX888;
2168                 break;
2169         case DRM_FORMAT_XRGB2101010:
2170         case DRM_FORMAT_ARGB2101010:
2171                 dspcntr |= DISPPLANE_BGRX101010;
2172                 break;
2173         case DRM_FORMAT_XBGR2101010:
2174         case DRM_FORMAT_ABGR2101010:
2175                 dspcntr |= DISPPLANE_RGBX101010;
2176                 break;
2177         default:
2178                 BUG();
2179         }
2180
2181         if (obj->tiling_mode != I915_TILING_NONE)
2182                 dspcntr |= DISPPLANE_TILED;
2183         else
2184                 dspcntr &= ~DISPPLANE_TILED;
2185
2186         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2187                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2188         else
2189                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2190
2191         I915_WRITE(reg, dspcntr);
2192
2193         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2194         intel_crtc->dspaddr_offset =
2195                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2196                                                fb->bits_per_pixel / 8,
2197                                                fb->pitches[0]);
2198         linear_offset -= intel_crtc->dspaddr_offset;
2199
2200         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2201                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2202                       fb->pitches[0]);
2203         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2204         I915_MODIFY_DISPBASE(DSPSURF(plane),
2205                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2206         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2207                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2208         } else {
2209                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2210                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2211         }
2212         POSTING_READ(reg);
2213
2214         return 0;
2215 }
2216
2217 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2218 static int
2219 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2220                            int x, int y, enum mode_set_atomic state)
2221 {
2222         struct drm_device *dev = crtc->dev;
2223         struct drm_i915_private *dev_priv = dev->dev_private;
2224
2225         if (dev_priv->display.disable_fbc)
2226                 dev_priv->display.disable_fbc(dev);
2227         intel_increase_pllclock(crtc);
2228
2229         return dev_priv->display.update_plane(crtc, fb, x, y);
2230 }
2231
2232 void intel_display_handle_reset(struct drm_device *dev)
2233 {
2234         struct drm_i915_private *dev_priv = dev->dev_private;
2235         struct drm_crtc *crtc;
2236
2237         /*
2238          * Flips in the rings have been nuked by the reset,
2239          * so complete all pending flips so that user space
2240          * will get its events and not get stuck.
2241          *
2242          * Also update the base address of all primary
2243          * planes to the the last fb to make sure we're
2244          * showing the correct fb after a reset.
2245          *
2246          * Need to make two loops over the crtcs so that we
2247          * don't try to grab a crtc mutex before the
2248          * pending_flip_queue really got woken up.
2249          */
2250
2251         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2252                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2253                 enum plane plane = intel_crtc->plane;
2254
2255                 intel_prepare_page_flip(dev, plane);
2256                 intel_finish_page_flip_plane(dev, plane);
2257         }
2258
2259         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2260                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2261
2262                 mutex_lock(&crtc->mutex);
2263                 /*
2264                  * FIXME: Once we have proper support for primary planes (and
2265                  * disabling them without disabling the entire crtc) allow again
2266                  * a NULL crtc->fb.
2267                  */
2268                 if (intel_crtc->active && crtc->fb)
2269                         dev_priv->display.update_plane(crtc, crtc->fb,
2270                                                        crtc->x, crtc->y);
2271                 mutex_unlock(&crtc->mutex);
2272         }
2273 }
2274
2275 static int
2276 intel_finish_fb(struct drm_framebuffer *old_fb)
2277 {
2278         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2279         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2280         bool was_interruptible = dev_priv->mm.interruptible;
2281         int ret;
2282
2283         /* Big Hammer, we also need to ensure that any pending
2284          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2285          * current scanout is retired before unpinning the old
2286          * framebuffer.
2287          *
2288          * This should only fail upon a hung GPU, in which case we
2289          * can safely continue.
2290          */
2291         dev_priv->mm.interruptible = false;
2292         ret = i915_gem_object_finish_gpu(obj);
2293         dev_priv->mm.interruptible = was_interruptible;
2294
2295         return ret;
2296 }
2297
2298 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2299 {
2300         struct drm_device *dev = crtc->dev;
2301         struct drm_i915_master_private *master_priv;
2302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2303
2304         if (!dev->primary->master)
2305                 return;
2306
2307         master_priv = dev->primary->master->driver_priv;
2308         if (!master_priv->sarea_priv)
2309                 return;
2310
2311         switch (intel_crtc->pipe) {
2312         case 0:
2313                 master_priv->sarea_priv->pipeA_x = x;
2314                 master_priv->sarea_priv->pipeA_y = y;
2315                 break;
2316         case 1:
2317                 master_priv->sarea_priv->pipeB_x = x;
2318                 master_priv->sarea_priv->pipeB_y = y;
2319                 break;
2320         default:
2321                 break;
2322         }
2323 }
2324
2325 static int
2326 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2327                     struct drm_framebuffer *fb)
2328 {
2329         struct drm_device *dev = crtc->dev;
2330         struct drm_i915_private *dev_priv = dev->dev_private;
2331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2332         struct drm_framebuffer *old_fb;
2333         int ret;
2334
2335         /* no fb bound */
2336         if (!fb) {
2337                 DRM_ERROR("No FB bound\n");
2338                 return 0;
2339         }
2340
2341         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2342                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2343                           plane_name(intel_crtc->plane),
2344                           INTEL_INFO(dev)->num_pipes);
2345                 return -EINVAL;
2346         }
2347
2348         mutex_lock(&dev->struct_mutex);
2349         ret = intel_pin_and_fence_fb_obj(dev,
2350                                          to_intel_framebuffer(fb)->obj,
2351                                          NULL);
2352         if (ret != 0) {
2353                 mutex_unlock(&dev->struct_mutex);
2354                 DRM_ERROR("pin & fence failed\n");
2355                 return ret;
2356         }
2357
2358         /*
2359          * Update pipe size and adjust fitter if needed: the reason for this is
2360          * that in compute_mode_changes we check the native mode (not the pfit
2361          * mode) to see if we can flip rather than do a full mode set. In the
2362          * fastboot case, we'll flip, but if we don't update the pipesrc and
2363          * pfit state, we'll end up with a big fb scanned out into the wrong
2364          * sized surface.
2365          *
2366          * To fix this properly, we need to hoist the checks up into
2367          * compute_mode_changes (or above), check the actual pfit state and
2368          * whether the platform allows pfit disable with pipe active, and only
2369          * then update the pipesrc and pfit state, even on the flip path.
2370          */
2371         if (i915_fastboot) {
2372                 const struct drm_display_mode *adjusted_mode =
2373                         &intel_crtc->config.adjusted_mode;
2374
2375                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2376                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2377                            (adjusted_mode->crtc_vdisplay - 1));
2378                 if (!intel_crtc->config.pch_pfit.enabled &&
2379                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2380                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2381                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2382                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2383                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2384                 }
2385                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2386                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2387         }
2388
2389         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2390         if (ret) {
2391                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2392                 mutex_unlock(&dev->struct_mutex);
2393                 DRM_ERROR("failed to update base address\n");
2394                 return ret;
2395         }
2396
2397         old_fb = crtc->fb;
2398         crtc->fb = fb;
2399         crtc->x = x;
2400         crtc->y = y;
2401
2402         if (old_fb) {
2403                 if (intel_crtc->active && old_fb != fb)
2404                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2405                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2406         }
2407
2408         intel_update_fbc(dev);
2409         intel_edp_psr_update(dev);
2410         mutex_unlock(&dev->struct_mutex);
2411
2412         intel_crtc_update_sarea_pos(crtc, x, y);
2413
2414         return 0;
2415 }
2416
2417 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2418 {
2419         struct drm_device *dev = crtc->dev;
2420         struct drm_i915_private *dev_priv = dev->dev_private;
2421         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2422         int pipe = intel_crtc->pipe;
2423         u32 reg, temp;
2424
2425         /* enable normal train */
2426         reg = FDI_TX_CTL(pipe);
2427         temp = I915_READ(reg);
2428         if (IS_IVYBRIDGE(dev)) {
2429                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2430                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2431         } else {
2432                 temp &= ~FDI_LINK_TRAIN_NONE;
2433                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2434         }
2435         I915_WRITE(reg, temp);
2436
2437         reg = FDI_RX_CTL(pipe);
2438         temp = I915_READ(reg);
2439         if (HAS_PCH_CPT(dev)) {
2440                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2441                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2442         } else {
2443                 temp &= ~FDI_LINK_TRAIN_NONE;
2444                 temp |= FDI_LINK_TRAIN_NONE;
2445         }
2446         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2447
2448         /* wait one idle pattern time */
2449         POSTING_READ(reg);
2450         udelay(1000);
2451
2452         /* IVB wants error correction enabled */
2453         if (IS_IVYBRIDGE(dev))
2454                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2455                            FDI_FE_ERRC_ENABLE);
2456 }
2457
2458 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2459 {
2460         return crtc->base.enabled && crtc->active &&
2461                 crtc->config.has_pch_encoder;
2462 }
2463
2464 static void ivb_modeset_global_resources(struct drm_device *dev)
2465 {
2466         struct drm_i915_private *dev_priv = dev->dev_private;
2467         struct intel_crtc *pipe_B_crtc =
2468                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2469         struct intel_crtc *pipe_C_crtc =
2470                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2471         uint32_t temp;
2472
2473         /*
2474          * When everything is off disable fdi C so that we could enable fdi B
2475          * with all lanes. Note that we don't care about enabled pipes without
2476          * an enabled pch encoder.
2477          */
2478         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2479             !pipe_has_enabled_pch(pipe_C_crtc)) {
2480                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2481                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2482
2483                 temp = I915_READ(SOUTH_CHICKEN1);
2484                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2485                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2486                 I915_WRITE(SOUTH_CHICKEN1, temp);
2487         }
2488 }
2489
2490 /* The FDI link training functions for ILK/Ibexpeak. */
2491 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2492 {
2493         struct drm_device *dev = crtc->dev;
2494         struct drm_i915_private *dev_priv = dev->dev_private;
2495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2496         int pipe = intel_crtc->pipe;
2497         int plane = intel_crtc->plane;
2498         u32 reg, temp, tries;
2499
2500         /* FDI needs bits from pipe & plane first */
2501         assert_pipe_enabled(dev_priv, pipe);
2502         assert_plane_enabled(dev_priv, plane);
2503
2504         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2505            for train result */
2506         reg = FDI_RX_IMR(pipe);
2507         temp = I915_READ(reg);
2508         temp &= ~FDI_RX_SYMBOL_LOCK;
2509         temp &= ~FDI_RX_BIT_LOCK;
2510         I915_WRITE(reg, temp);
2511         I915_READ(reg);
2512         udelay(150);
2513
2514         /* enable CPU FDI TX and PCH FDI RX */
2515         reg = FDI_TX_CTL(pipe);
2516         temp = I915_READ(reg);
2517         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2518         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2519         temp &= ~FDI_LINK_TRAIN_NONE;
2520         temp |= FDI_LINK_TRAIN_PATTERN_1;
2521         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2522
2523         reg = FDI_RX_CTL(pipe);
2524         temp = I915_READ(reg);
2525         temp &= ~FDI_LINK_TRAIN_NONE;
2526         temp |= FDI_LINK_TRAIN_PATTERN_1;
2527         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2528
2529         POSTING_READ(reg);
2530         udelay(150);
2531
2532         /* Ironlake workaround, enable clock pointer after FDI enable*/
2533         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2534         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2535                    FDI_RX_PHASE_SYNC_POINTER_EN);
2536
2537         reg = FDI_RX_IIR(pipe);
2538         for (tries = 0; tries < 5; tries++) {
2539                 temp = I915_READ(reg);
2540                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2541
2542                 if ((temp & FDI_RX_BIT_LOCK)) {
2543                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2544                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2545                         break;
2546                 }
2547         }
2548         if (tries == 5)
2549                 DRM_ERROR("FDI train 1 fail!\n");
2550
2551         /* Train 2 */
2552         reg = FDI_TX_CTL(pipe);
2553         temp = I915_READ(reg);
2554         temp &= ~FDI_LINK_TRAIN_NONE;
2555         temp |= FDI_LINK_TRAIN_PATTERN_2;
2556         I915_WRITE(reg, temp);
2557
2558         reg = FDI_RX_CTL(pipe);
2559         temp = I915_READ(reg);
2560         temp &= ~FDI_LINK_TRAIN_NONE;
2561         temp |= FDI_LINK_TRAIN_PATTERN_2;
2562         I915_WRITE(reg, temp);
2563
2564         POSTING_READ(reg);
2565         udelay(150);
2566
2567         reg = FDI_RX_IIR(pipe);
2568         for (tries = 0; tries < 5; tries++) {
2569                 temp = I915_READ(reg);
2570                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2571
2572                 if (temp & FDI_RX_SYMBOL_LOCK) {
2573                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2574                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2575                         break;
2576                 }
2577         }
2578         if (tries == 5)
2579                 DRM_ERROR("FDI train 2 fail!\n");
2580
2581         DRM_DEBUG_KMS("FDI train done\n");
2582
2583 }
2584
2585 static const int snb_b_fdi_train_param[] = {
2586         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2587         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2588         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2589         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2590 };
2591
2592 /* The FDI link training functions for SNB/Cougarpoint. */
2593 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2594 {
2595         struct drm_device *dev = crtc->dev;
2596         struct drm_i915_private *dev_priv = dev->dev_private;
2597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2598         int pipe = intel_crtc->pipe;
2599         u32 reg, temp, i, retry;
2600
2601         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2602            for train result */
2603         reg = FDI_RX_IMR(pipe);
2604         temp = I915_READ(reg);
2605         temp &= ~FDI_RX_SYMBOL_LOCK;
2606         temp &= ~FDI_RX_BIT_LOCK;
2607         I915_WRITE(reg, temp);
2608
2609         POSTING_READ(reg);
2610         udelay(150);
2611
2612         /* enable CPU FDI TX and PCH FDI RX */
2613         reg = FDI_TX_CTL(pipe);
2614         temp = I915_READ(reg);
2615         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2616         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2617         temp &= ~FDI_LINK_TRAIN_NONE;
2618         temp |= FDI_LINK_TRAIN_PATTERN_1;
2619         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2620         /* SNB-B */
2621         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2622         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2623
2624         I915_WRITE(FDI_RX_MISC(pipe),
2625                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2626
2627         reg = FDI_RX_CTL(pipe);
2628         temp = I915_READ(reg);
2629         if (HAS_PCH_CPT(dev)) {
2630                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2631                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2632         } else {
2633                 temp &= ~FDI_LINK_TRAIN_NONE;
2634                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2635         }
2636         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2637
2638         POSTING_READ(reg);
2639         udelay(150);
2640
2641         for (i = 0; i < 4; i++) {
2642                 reg = FDI_TX_CTL(pipe);
2643                 temp = I915_READ(reg);
2644                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645                 temp |= snb_b_fdi_train_param[i];
2646                 I915_WRITE(reg, temp);
2647
2648                 POSTING_READ(reg);
2649                 udelay(500);
2650
2651                 for (retry = 0; retry < 5; retry++) {
2652                         reg = FDI_RX_IIR(pipe);
2653                         temp = I915_READ(reg);
2654                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2655                         if (temp & FDI_RX_BIT_LOCK) {
2656                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2657                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2658                                 break;
2659                         }
2660                         udelay(50);
2661                 }
2662                 if (retry < 5)
2663                         break;
2664         }
2665         if (i == 4)
2666                 DRM_ERROR("FDI train 1 fail!\n");
2667
2668         /* Train 2 */
2669         reg = FDI_TX_CTL(pipe);
2670         temp = I915_READ(reg);
2671         temp &= ~FDI_LINK_TRAIN_NONE;
2672         temp |= FDI_LINK_TRAIN_PATTERN_2;
2673         if (IS_GEN6(dev)) {
2674                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2675                 /* SNB-B */
2676                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2677         }
2678         I915_WRITE(reg, temp);
2679
2680         reg = FDI_RX_CTL(pipe);
2681         temp = I915_READ(reg);
2682         if (HAS_PCH_CPT(dev)) {
2683                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2684                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2685         } else {
2686                 temp &= ~FDI_LINK_TRAIN_NONE;
2687                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2688         }
2689         I915_WRITE(reg, temp);
2690
2691         POSTING_READ(reg);
2692         udelay(150);
2693
2694         for (i = 0; i < 4; i++) {
2695                 reg = FDI_TX_CTL(pipe);
2696                 temp = I915_READ(reg);
2697                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2698                 temp |= snb_b_fdi_train_param[i];
2699                 I915_WRITE(reg, temp);
2700
2701                 POSTING_READ(reg);
2702                 udelay(500);
2703
2704                 for (retry = 0; retry < 5; retry++) {
2705                         reg = FDI_RX_IIR(pipe);
2706                         temp = I915_READ(reg);
2707                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2708                         if (temp & FDI_RX_SYMBOL_LOCK) {
2709                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2710                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2711                                 break;
2712                         }
2713                         udelay(50);
2714                 }
2715                 if (retry < 5)
2716                         break;
2717         }
2718         if (i == 4)
2719                 DRM_ERROR("FDI train 2 fail!\n");
2720
2721         DRM_DEBUG_KMS("FDI train done.\n");
2722 }
2723
2724 /* Manual link training for Ivy Bridge A0 parts */
2725 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2726 {
2727         struct drm_device *dev = crtc->dev;
2728         struct drm_i915_private *dev_priv = dev->dev_private;
2729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2730         int pipe = intel_crtc->pipe;
2731         u32 reg, temp, i, j;
2732
2733         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2734            for train result */
2735         reg = FDI_RX_IMR(pipe);
2736         temp = I915_READ(reg);
2737         temp &= ~FDI_RX_SYMBOL_LOCK;
2738         temp &= ~FDI_RX_BIT_LOCK;
2739         I915_WRITE(reg, temp);
2740
2741         POSTING_READ(reg);
2742         udelay(150);
2743
2744         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2745                       I915_READ(FDI_RX_IIR(pipe)));
2746
2747         /* Try each vswing and preemphasis setting twice before moving on */
2748         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2749                 /* disable first in case we need to retry */
2750                 reg = FDI_TX_CTL(pipe);
2751                 temp = I915_READ(reg);
2752                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2753                 temp &= ~FDI_TX_ENABLE;
2754                 I915_WRITE(reg, temp);
2755
2756                 reg = FDI_RX_CTL(pipe);
2757                 temp = I915_READ(reg);
2758                 temp &= ~FDI_LINK_TRAIN_AUTO;
2759                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2760                 temp &= ~FDI_RX_ENABLE;
2761                 I915_WRITE(reg, temp);
2762
2763                 /* enable CPU FDI TX and PCH FDI RX */
2764                 reg = FDI_TX_CTL(pipe);
2765                 temp = I915_READ(reg);
2766                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2767                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2768                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2769                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2770                 temp |= snb_b_fdi_train_param[j/2];
2771                 temp |= FDI_COMPOSITE_SYNC;
2772                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2773
2774                 I915_WRITE(FDI_RX_MISC(pipe),
2775                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2776
2777                 reg = FDI_RX_CTL(pipe);
2778                 temp = I915_READ(reg);
2779                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2780                 temp |= FDI_COMPOSITE_SYNC;
2781                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2782
2783                 POSTING_READ(reg);
2784                 udelay(1); /* should be 0.5us */
2785
2786                 for (i = 0; i < 4; i++) {
2787                         reg = FDI_RX_IIR(pipe);
2788                         temp = I915_READ(reg);
2789                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2790
2791                         if (temp & FDI_RX_BIT_LOCK ||
2792                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2793                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2794                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2795                                               i);
2796                                 break;
2797                         }
2798                         udelay(1); /* should be 0.5us */
2799                 }
2800                 if (i == 4) {
2801                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2802                         continue;
2803                 }
2804
2805                 /* Train 2 */
2806                 reg = FDI_TX_CTL(pipe);
2807                 temp = I915_READ(reg);
2808                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2809                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2810                 I915_WRITE(reg, temp);
2811
2812                 reg = FDI_RX_CTL(pipe);
2813                 temp = I915_READ(reg);
2814                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2815                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2816                 I915_WRITE(reg, temp);
2817
2818                 POSTING_READ(reg);
2819                 udelay(2); /* should be 1.5us */
2820
2821                 for (i = 0; i < 4; i++) {
2822                         reg = FDI_RX_IIR(pipe);
2823                         temp = I915_READ(reg);
2824                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2825
2826                         if (temp & FDI_RX_SYMBOL_LOCK ||
2827                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2828                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2829                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2830                                               i);
2831                                 goto train_done;
2832                         }
2833                         udelay(2); /* should be 1.5us */
2834                 }
2835                 if (i == 4)
2836                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2837         }
2838
2839 train_done:
2840         DRM_DEBUG_KMS("FDI train done.\n");
2841 }
2842
2843 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2844 {
2845         struct drm_device *dev = intel_crtc->base.dev;
2846         struct drm_i915_private *dev_priv = dev->dev_private;
2847         int pipe = intel_crtc->pipe;
2848         u32 reg, temp;
2849
2850
2851         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2852         reg = FDI_RX_CTL(pipe);
2853         temp = I915_READ(reg);
2854         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2855         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2856         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2857         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2858
2859         POSTING_READ(reg);
2860         udelay(200);
2861
2862         /* Switch from Rawclk to PCDclk */
2863         temp = I915_READ(reg);
2864         I915_WRITE(reg, temp | FDI_PCDCLK);
2865
2866         POSTING_READ(reg);
2867         udelay(200);
2868
2869         /* Enable CPU FDI TX PLL, always on for Ironlake */
2870         reg = FDI_TX_CTL(pipe);
2871         temp = I915_READ(reg);
2872         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2873                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2874
2875                 POSTING_READ(reg);
2876                 udelay(100);
2877         }
2878 }
2879
2880 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2881 {
2882         struct drm_device *dev = intel_crtc->base.dev;
2883         struct drm_i915_private *dev_priv = dev->dev_private;
2884         int pipe = intel_crtc->pipe;
2885         u32 reg, temp;
2886
2887         /* Switch from PCDclk to Rawclk */
2888         reg = FDI_RX_CTL(pipe);
2889         temp = I915_READ(reg);
2890         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2891
2892         /* Disable CPU FDI TX PLL */
2893         reg = FDI_TX_CTL(pipe);
2894         temp = I915_READ(reg);
2895         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2896
2897         POSTING_READ(reg);
2898         udelay(100);
2899
2900         reg = FDI_RX_CTL(pipe);
2901         temp = I915_READ(reg);
2902         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2903
2904         /* Wait for the clocks to turn off. */
2905         POSTING_READ(reg);
2906         udelay(100);
2907 }
2908
2909 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2910 {
2911         struct drm_device *dev = crtc->dev;
2912         struct drm_i915_private *dev_priv = dev->dev_private;
2913         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2914         int pipe = intel_crtc->pipe;
2915         u32 reg, temp;
2916
2917         /* disable CPU FDI tx and PCH FDI rx */
2918         reg = FDI_TX_CTL(pipe);
2919         temp = I915_READ(reg);
2920         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2921         POSTING_READ(reg);
2922
2923         reg = FDI_RX_CTL(pipe);
2924         temp = I915_READ(reg);
2925         temp &= ~(0x7 << 16);
2926         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2927         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2928
2929         POSTING_READ(reg);
2930         udelay(100);
2931
2932         /* Ironlake workaround, disable clock pointer after downing FDI */
2933         if (HAS_PCH_IBX(dev)) {
2934                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2935         }
2936
2937         /* still set train pattern 1 */
2938         reg = FDI_TX_CTL(pipe);
2939         temp = I915_READ(reg);
2940         temp &= ~FDI_LINK_TRAIN_NONE;
2941         temp |= FDI_LINK_TRAIN_PATTERN_1;
2942         I915_WRITE(reg, temp);
2943
2944         reg = FDI_RX_CTL(pipe);
2945         temp = I915_READ(reg);
2946         if (HAS_PCH_CPT(dev)) {
2947                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2948                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2949         } else {
2950                 temp &= ~FDI_LINK_TRAIN_NONE;
2951                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2952         }
2953         /* BPC in FDI rx is consistent with that in PIPECONF */
2954         temp &= ~(0x07 << 16);
2955         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2956         I915_WRITE(reg, temp);
2957
2958         POSTING_READ(reg);
2959         udelay(100);
2960 }
2961
2962 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2963 {
2964         struct drm_device *dev = crtc->dev;
2965         struct drm_i915_private *dev_priv = dev->dev_private;
2966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2967         unsigned long flags;
2968         bool pending;
2969
2970         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2971             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2972                 return false;
2973
2974         spin_lock_irqsave(&dev->event_lock, flags);
2975         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2976         spin_unlock_irqrestore(&dev->event_lock, flags);
2977
2978         return pending;
2979 }
2980
2981 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2982 {
2983         struct drm_device *dev = crtc->dev;
2984         struct drm_i915_private *dev_priv = dev->dev_private;
2985
2986         if (crtc->fb == NULL)
2987                 return;
2988
2989         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2990
2991         wait_event(dev_priv->pending_flip_queue,
2992                    !intel_crtc_has_pending_flip(crtc));
2993
2994         mutex_lock(&dev->struct_mutex);
2995         intel_finish_fb(crtc->fb);
2996         mutex_unlock(&dev->struct_mutex);
2997 }
2998
2999 /* Program iCLKIP clock to the desired frequency */
3000 static void lpt_program_iclkip(struct drm_crtc *crtc)
3001 {
3002         struct drm_device *dev = crtc->dev;
3003         struct drm_i915_private *dev_priv = dev->dev_private;
3004         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3005         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3006         u32 temp;
3007
3008         mutex_lock(&dev_priv->dpio_lock);
3009
3010         /* It is necessary to ungate the pixclk gate prior to programming
3011          * the divisors, and gate it back when it is done.
3012          */
3013         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3014
3015         /* Disable SSCCTL */
3016         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3017                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3018                                 SBI_SSCCTL_DISABLE,
3019                         SBI_ICLK);
3020
3021         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3022         if (clock == 20000) {
3023                 auxdiv = 1;
3024                 divsel = 0x41;
3025                 phaseinc = 0x20;
3026         } else {
3027                 /* The iCLK virtual clock root frequency is in MHz,
3028                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3029                  * divisors, it is necessary to divide one by another, so we
3030                  * convert the virtual clock precision to KHz here for higher
3031                  * precision.
3032                  */
3033                 u32 iclk_virtual_root_freq = 172800 * 1000;
3034                 u32 iclk_pi_range = 64;
3035                 u32 desired_divisor, msb_divisor_value, pi_value;
3036
3037                 desired_divisor = (iclk_virtual_root_freq / clock);
3038                 msb_divisor_value = desired_divisor / iclk_pi_range;
3039                 pi_value = desired_divisor % iclk_pi_range;
3040
3041                 auxdiv = 0;
3042                 divsel = msb_divisor_value - 2;
3043                 phaseinc = pi_value;
3044         }
3045
3046         /* This should not happen with any sane values */
3047         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3048                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3049         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3050                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3051
3052         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3053                         clock,
3054                         auxdiv,
3055                         divsel,
3056                         phasedir,
3057                         phaseinc);
3058
3059         /* Program SSCDIVINTPHASE6 */
3060         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3061         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3062         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3063         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3064         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3065         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3066         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3067         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3068
3069         /* Program SSCAUXDIV */
3070         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3071         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3072         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3073         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3074
3075         /* Enable modulator and associated divider */
3076         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3077         temp &= ~SBI_SSCCTL_DISABLE;
3078         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3079
3080         /* Wait for initialization time */
3081         udelay(24);
3082
3083         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3084
3085         mutex_unlock(&dev_priv->dpio_lock);
3086 }
3087
3088 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3089                                                 enum pipe pch_transcoder)
3090 {
3091         struct drm_device *dev = crtc->base.dev;
3092         struct drm_i915_private *dev_priv = dev->dev_private;
3093         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3094
3095         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3096                    I915_READ(HTOTAL(cpu_transcoder)));
3097         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3098                    I915_READ(HBLANK(cpu_transcoder)));
3099         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3100                    I915_READ(HSYNC(cpu_transcoder)));
3101
3102         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3103                    I915_READ(VTOTAL(cpu_transcoder)));
3104         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3105                    I915_READ(VBLANK(cpu_transcoder)));
3106         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3107                    I915_READ(VSYNC(cpu_transcoder)));
3108         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3109                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3110 }
3111
3112 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3113 {
3114         struct drm_i915_private *dev_priv = dev->dev_private;
3115         uint32_t temp;
3116
3117         temp = I915_READ(SOUTH_CHICKEN1);
3118         if (temp & FDI_BC_BIFURCATION_SELECT)
3119                 return;
3120
3121         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3122         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3123
3124         temp |= FDI_BC_BIFURCATION_SELECT;
3125         DRM_DEBUG_KMS("enabling fdi C rx\n");
3126         I915_WRITE(SOUTH_CHICKEN1, temp);
3127         POSTING_READ(SOUTH_CHICKEN1);
3128 }
3129
3130 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3131 {
3132         struct drm_device *dev = intel_crtc->base.dev;
3133         struct drm_i915_private *dev_priv = dev->dev_private;
3134
3135         switch (intel_crtc->pipe) {
3136         case PIPE_A:
3137                 break;
3138         case PIPE_B:
3139                 if (intel_crtc->config.fdi_lanes > 2)
3140                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3141                 else
3142                         cpt_enable_fdi_bc_bifurcation(dev);
3143
3144                 break;
3145         case PIPE_C:
3146                 cpt_enable_fdi_bc_bifurcation(dev);
3147
3148                 break;
3149         default:
3150                 BUG();
3151         }
3152 }
3153
3154 /*
3155  * Enable PCH resources required for PCH ports:
3156  *   - PCH PLLs
3157  *   - FDI training & RX/TX
3158  *   - update transcoder timings
3159  *   - DP transcoding bits
3160  *   - transcoder
3161  */
3162 static void ironlake_pch_enable(struct drm_crtc *crtc)
3163 {
3164         struct drm_device *dev = crtc->dev;
3165         struct drm_i915_private *dev_priv = dev->dev_private;
3166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167         int pipe = intel_crtc->pipe;
3168         u32 reg, temp;
3169
3170         assert_pch_transcoder_disabled(dev_priv, pipe);
3171
3172         if (IS_IVYBRIDGE(dev))
3173                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3174
3175         /* Write the TU size bits before fdi link training, so that error
3176          * detection works. */
3177         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3178                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3179
3180         /* For PCH output, training FDI link */
3181         dev_priv->display.fdi_link_train(crtc);
3182
3183         /* We need to program the right clock selection before writing the pixel
3184          * mutliplier into the DPLL. */
3185         if (HAS_PCH_CPT(dev)) {
3186                 u32 sel;
3187
3188                 temp = I915_READ(PCH_DPLL_SEL);
3189                 temp |= TRANS_DPLL_ENABLE(pipe);
3190                 sel = TRANS_DPLLB_SEL(pipe);
3191                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3192                         temp |= sel;
3193                 else
3194                         temp &= ~sel;
3195                 I915_WRITE(PCH_DPLL_SEL, temp);
3196         }
3197
3198         /* XXX: pch pll's can be enabled any time before we enable the PCH
3199          * transcoder, and we actually should do this to not upset any PCH
3200          * transcoder that already use the clock when we share it.
3201          *
3202          * Note that enable_shared_dpll tries to do the right thing, but
3203          * get_shared_dpll unconditionally resets the pll - we need that to have
3204          * the right LVDS enable sequence. */
3205         ironlake_enable_shared_dpll(intel_crtc);
3206
3207         /* set transcoder timing, panel must allow it */
3208         assert_panel_unlocked(dev_priv, pipe);
3209         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3210
3211         intel_fdi_normal_train(crtc);
3212
3213         /* For PCH DP, enable TRANS_DP_CTL */
3214         if (HAS_PCH_CPT(dev) &&
3215             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3216              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3217                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3218                 reg = TRANS_DP_CTL(pipe);
3219                 temp = I915_READ(reg);
3220                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3221                           TRANS_DP_SYNC_MASK |
3222                           TRANS_DP_BPC_MASK);
3223                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3224                          TRANS_DP_ENH_FRAMING);
3225                 temp |= bpc << 9; /* same format but at 11:9 */
3226
3227                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3228                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3229                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3230                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3231
3232                 switch (intel_trans_dp_port_sel(crtc)) {
3233                 case PCH_DP_B:
3234                         temp |= TRANS_DP_PORT_SEL_B;
3235                         break;
3236                 case PCH_DP_C:
3237                         temp |= TRANS_DP_PORT_SEL_C;
3238                         break;
3239                 case PCH_DP_D:
3240                         temp |= TRANS_DP_PORT_SEL_D;
3241                         break;
3242                 default:
3243                         BUG();
3244                 }
3245
3246                 I915_WRITE(reg, temp);
3247         }
3248
3249         ironlake_enable_pch_transcoder(dev_priv, pipe);
3250 }
3251
3252 static void lpt_pch_enable(struct drm_crtc *crtc)
3253 {
3254         struct drm_device *dev = crtc->dev;
3255         struct drm_i915_private *dev_priv = dev->dev_private;
3256         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3257         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3258
3259         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3260
3261         lpt_program_iclkip(crtc);
3262
3263         /* Set transcoder timing. */
3264         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3265
3266         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3267 }
3268
3269 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3270 {
3271         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3272
3273         if (pll == NULL)
3274                 return;
3275
3276         if (pll->refcount == 0) {
3277                 WARN(1, "bad %s refcount\n", pll->name);
3278                 return;
3279         }
3280
3281         if (--pll->refcount == 0) {
3282                 WARN_ON(pll->on);
3283                 WARN_ON(pll->active);
3284         }
3285
3286         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3287 }
3288
3289 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3290 {
3291         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3292         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3293         enum intel_dpll_id i;
3294
3295         if (pll) {
3296                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3297                               crtc->base.base.id, pll->name);
3298                 intel_put_shared_dpll(crtc);
3299         }
3300
3301         if (HAS_PCH_IBX(dev_priv->dev)) {
3302                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3303                 i = (enum intel_dpll_id) crtc->pipe;
3304                 pll = &dev_priv->shared_dplls[i];
3305
3306                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3307                               crtc->base.base.id, pll->name);
3308
3309                 goto found;
3310         }
3311
3312         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3313                 pll = &dev_priv->shared_dplls[i];
3314
3315                 /* Only want to check enabled timings first */
3316                 if (pll->refcount == 0)
3317                         continue;
3318
3319                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3320                            sizeof(pll->hw_state)) == 0) {
3321                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3322                                       crtc->base.base.id,
3323                                       pll->name, pll->refcount, pll->active);
3324
3325                         goto found;
3326                 }
3327         }
3328
3329         /* Ok no matching timings, maybe there's a free one? */
3330         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3331                 pll = &dev_priv->shared_dplls[i];
3332                 if (pll->refcount == 0) {
3333                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3334                                       crtc->base.base.id, pll->name);
3335                         goto found;
3336                 }
3337         }
3338
3339         return NULL;
3340
3341 found:
3342         crtc->config.shared_dpll = i;
3343         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3344                          pipe_name(crtc->pipe));
3345
3346         if (pll->active == 0) {
3347                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3348                        sizeof(pll->hw_state));
3349
3350                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3351                 WARN_ON(pll->on);
3352                 assert_shared_dpll_disabled(dev_priv, pll);
3353
3354                 pll->mode_set(dev_priv, pll);
3355         }
3356         pll->refcount++;
3357
3358         return pll;
3359 }
3360
3361 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3362 {
3363         struct drm_i915_private *dev_priv = dev->dev_private;
3364         int dslreg = PIPEDSL(pipe);
3365         u32 temp;
3366
3367         temp = I915_READ(dslreg);
3368         udelay(500);
3369         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3370                 if (wait_for(I915_READ(dslreg) != temp, 5))
3371                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3372         }
3373 }
3374
3375 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3376 {
3377         struct drm_device *dev = crtc->base.dev;
3378         struct drm_i915_private *dev_priv = dev->dev_private;
3379         int pipe = crtc->pipe;
3380
3381         if (crtc->config.pch_pfit.enabled) {
3382                 /* Force use of hard-coded filter coefficients
3383                  * as some pre-programmed values are broken,
3384                  * e.g. x201.
3385                  */
3386                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3387                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3388                                                  PF_PIPE_SEL_IVB(pipe));
3389                 else
3390                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3391                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3392                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3393         }
3394 }
3395
3396 static void intel_enable_planes(struct drm_crtc *crtc)
3397 {
3398         struct drm_device *dev = crtc->dev;
3399         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3400         struct intel_plane *intel_plane;
3401
3402         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3403                 if (intel_plane->pipe == pipe)
3404                         intel_plane_restore(&intel_plane->base);
3405 }
3406
3407 static void intel_disable_planes(struct drm_crtc *crtc)
3408 {
3409         struct drm_device *dev = crtc->dev;
3410         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3411         struct intel_plane *intel_plane;
3412
3413         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3414                 if (intel_plane->pipe == pipe)
3415                         intel_plane_disable(&intel_plane->base);
3416 }
3417
3418 void hsw_enable_ips(struct intel_crtc *crtc)
3419 {
3420         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3421
3422         if (!crtc->config.ips_enabled)
3423                 return;
3424
3425         /* We can only enable IPS after we enable a plane and wait for a vblank.
3426          * We guarantee that the plane is enabled by calling intel_enable_ips
3427          * only after intel_enable_plane. And intel_enable_plane already waits
3428          * for a vblank, so all we need to do here is to enable the IPS bit. */
3429         assert_plane_enabled(dev_priv, crtc->plane);
3430         if (IS_BROADWELL(crtc->base.dev)) {
3431                 mutex_lock(&dev_priv->rps.hw_lock);
3432                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3433                 mutex_unlock(&dev_priv->rps.hw_lock);
3434                 /* Quoting Art Runyan: "its not safe to expect any particular
3435                  * value in IPS_CTL bit 31 after enabling IPS through the
3436                  * mailbox." Therefore we need to defer waiting on the state
3437                  * change.
3438                  * TODO: need to fix this for state checker
3439                  */
3440         } else {
3441                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3442                 /* The bit only becomes 1 in the next vblank, so this wait here
3443                  * is essentially intel_wait_for_vblank. If we don't have this
3444                  * and don't wait for vblanks until the end of crtc_enable, then
3445                  * the HW state readout code will complain that the expected
3446                  * IPS_CTL value is not the one we read. */
3447                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3448                         DRM_ERROR("Timed out waiting for IPS enable\n");
3449         }
3450 }
3451
3452 void hsw_disable_ips(struct intel_crtc *crtc)
3453 {
3454         struct drm_device *dev = crtc->base.dev;
3455         struct drm_i915_private *dev_priv = dev->dev_private;
3456
3457         if (!crtc->config.ips_enabled)
3458                 return;
3459
3460         assert_plane_enabled(dev_priv, crtc->plane);
3461         if (IS_BROADWELL(crtc->base.dev)) {
3462                 mutex_lock(&dev_priv->rps.hw_lock);
3463                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3464                 mutex_unlock(&dev_priv->rps.hw_lock);
3465         } else
3466                 I915_WRITE(IPS_CTL, 0);
3467         POSTING_READ(IPS_CTL);
3468
3469         /* We need to wait for a vblank before we can disable the plane. */
3470         intel_wait_for_vblank(dev, crtc->pipe);
3471 }
3472
3473 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3474 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3475 {
3476         struct drm_device *dev = crtc->dev;
3477         struct drm_i915_private *dev_priv = dev->dev_private;
3478         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3479         enum pipe pipe = intel_crtc->pipe;
3480         int palreg = PALETTE(pipe);
3481         int i;
3482         bool reenable_ips = false;
3483
3484         /* The clocks have to be on to load the palette. */
3485         if (!crtc->enabled || !intel_crtc->active)
3486                 return;
3487
3488         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3489                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3490                         assert_dsi_pll_enabled(dev_priv);
3491                 else
3492                         assert_pll_enabled(dev_priv, pipe);
3493         }
3494
3495         /* use legacy palette for Ironlake */
3496         if (HAS_PCH_SPLIT(dev))
3497                 palreg = LGC_PALETTE(pipe);
3498
3499         /* Workaround : Do not read or write the pipe palette/gamma data while
3500          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3501          */
3502         if (intel_crtc->config.ips_enabled &&
3503             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3504              GAMMA_MODE_MODE_SPLIT)) {
3505                 hsw_disable_ips(intel_crtc);
3506                 reenable_ips = true;
3507         }
3508
3509         for (i = 0; i < 256; i++) {
3510                 I915_WRITE(palreg + 4 * i,
3511                            (intel_crtc->lut_r[i] << 16) |
3512                            (intel_crtc->lut_g[i] << 8) |
3513                            intel_crtc->lut_b[i]);
3514         }
3515
3516         if (reenable_ips)
3517                 hsw_enable_ips(intel_crtc);
3518 }
3519
3520 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3521 {
3522         struct drm_device *dev = crtc->dev;
3523         struct drm_i915_private *dev_priv = dev->dev_private;
3524         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3525         struct intel_encoder *encoder;
3526         int pipe = intel_crtc->pipe;
3527         int plane = intel_crtc->plane;
3528
3529         WARN_ON(!crtc->enabled);
3530
3531         if (intel_crtc->active)
3532                 return;
3533
3534         intel_crtc->active = true;
3535
3536         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3537         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3538
3539         for_each_encoder_on_crtc(dev, crtc, encoder)
3540                 if (encoder->pre_enable)
3541                         encoder->pre_enable(encoder);
3542
3543         if (intel_crtc->config.has_pch_encoder) {
3544                 /* Note: FDI PLL enabling _must_ be done before we enable the
3545                  * cpu pipes, hence this is separate from all the other fdi/pch
3546                  * enabling. */
3547                 ironlake_fdi_pll_enable(intel_crtc);
3548         } else {
3549                 assert_fdi_tx_disabled(dev_priv, pipe);
3550                 assert_fdi_rx_disabled(dev_priv, pipe);
3551         }
3552
3553         ironlake_pfit_enable(intel_crtc);
3554
3555         /*
3556          * On ILK+ LUT must be loaded before the pipe is running but with
3557          * clocks enabled
3558          */
3559         intel_crtc_load_lut(crtc);
3560
3561         intel_update_watermarks(crtc);
3562         intel_enable_pipe(dev_priv, pipe,
3563                           intel_crtc->config.has_pch_encoder, false);
3564         intel_enable_primary_plane(dev_priv, plane, pipe);
3565         intel_enable_planes(crtc);
3566         intel_crtc_update_cursor(crtc, true);
3567
3568         if (intel_crtc->config.has_pch_encoder)
3569                 ironlake_pch_enable(crtc);
3570
3571         mutex_lock(&dev->struct_mutex);
3572         intel_update_fbc(dev);
3573         mutex_unlock(&dev->struct_mutex);
3574
3575         for_each_encoder_on_crtc(dev, crtc, encoder)
3576                 encoder->enable(encoder);
3577
3578         if (HAS_PCH_CPT(dev))
3579                 cpt_verify_modeset(dev, intel_crtc->pipe);
3580
3581         /*
3582          * There seems to be a race in PCH platform hw (at least on some
3583          * outputs) where an enabled pipe still completes any pageflip right
3584          * away (as if the pipe is off) instead of waiting for vblank. As soon
3585          * as the first vblank happend, everything works as expected. Hence just
3586          * wait for one vblank before returning to avoid strange things
3587          * happening.
3588          */
3589         intel_wait_for_vblank(dev, intel_crtc->pipe);
3590 }
3591
3592 /* IPS only exists on ULT machines and is tied to pipe A. */
3593 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3594 {
3595         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3596 }
3597
3598 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3599 {
3600         struct drm_device *dev = crtc->dev;
3601         struct drm_i915_private *dev_priv = dev->dev_private;
3602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3603         int pipe = intel_crtc->pipe;
3604         int plane = intel_crtc->plane;
3605
3606         intel_enable_primary_plane(dev_priv, plane, pipe);
3607         intel_enable_planes(crtc);
3608         intel_crtc_update_cursor(crtc, true);
3609
3610         hsw_enable_ips(intel_crtc);
3611
3612         mutex_lock(&dev->struct_mutex);
3613         intel_update_fbc(dev);
3614         mutex_unlock(&dev->struct_mutex);
3615 }
3616
3617 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3618 {
3619         struct drm_device *dev = crtc->dev;
3620         struct drm_i915_private *dev_priv = dev->dev_private;
3621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3622         int pipe = intel_crtc->pipe;
3623         int plane = intel_crtc->plane;
3624
3625         intel_crtc_wait_for_pending_flips(crtc);
3626         drm_vblank_off(dev, pipe);
3627
3628         /* FBC must be disabled before disabling the plane on HSW. */
3629         if (dev_priv->fbc.plane == plane)
3630                 intel_disable_fbc(dev);
3631
3632         hsw_disable_ips(intel_crtc);
3633
3634         intel_crtc_update_cursor(crtc, false);
3635         intel_disable_planes(crtc);
3636         intel_disable_primary_plane(dev_priv, plane, pipe);
3637 }
3638
3639 /*
3640  * This implements the workaround described in the "notes" section of the mode
3641  * set sequence documentation. When going from no pipes or single pipe to
3642  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3643  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3644  */
3645 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3646 {
3647         struct drm_device *dev = crtc->base.dev;
3648         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3649
3650         /* We want to get the other_active_crtc only if there's only 1 other
3651          * active crtc. */
3652         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3653                 if (!crtc_it->active || crtc_it == crtc)
3654                         continue;
3655
3656                 if (other_active_crtc)
3657                         return;
3658
3659                 other_active_crtc = crtc_it;
3660         }
3661         if (!other_active_crtc)
3662                 return;
3663
3664         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3665         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3666 }
3667
3668 static void haswell_crtc_enable(struct drm_crtc *crtc)
3669 {
3670         struct drm_device *dev = crtc->dev;
3671         struct drm_i915_private *dev_priv = dev->dev_private;
3672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3673         struct intel_encoder *encoder;
3674         int pipe = intel_crtc->pipe;
3675
3676         WARN_ON(!crtc->enabled);
3677
3678         if (intel_crtc->active)
3679                 return;
3680
3681         intel_crtc->active = true;
3682
3683         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3684         if (intel_crtc->config.has_pch_encoder)
3685                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3686
3687         if (intel_crtc->config.has_pch_encoder)
3688                 dev_priv->display.fdi_link_train(crtc);
3689
3690         for_each_encoder_on_crtc(dev, crtc, encoder)
3691                 if (encoder->pre_enable)
3692                         encoder->pre_enable(encoder);
3693
3694         intel_ddi_enable_pipe_clock(intel_crtc);
3695
3696         ironlake_pfit_enable(intel_crtc);
3697
3698         /*
3699          * On ILK+ LUT must be loaded before the pipe is running but with
3700          * clocks enabled
3701          */
3702         intel_crtc_load_lut(crtc);
3703
3704         intel_ddi_set_pipe_settings(crtc);
3705         intel_ddi_enable_transcoder_func(crtc);
3706
3707         intel_update_watermarks(crtc);
3708         intel_enable_pipe(dev_priv, pipe,
3709                           intel_crtc->config.has_pch_encoder, false);
3710
3711         if (intel_crtc->config.has_pch_encoder)
3712                 lpt_pch_enable(crtc);
3713
3714         for_each_encoder_on_crtc(dev, crtc, encoder) {
3715                 encoder->enable(encoder);
3716                 intel_opregion_notify_encoder(encoder, true);
3717         }
3718
3719         /* If we change the relative order between pipe/planes enabling, we need
3720          * to change the workaround. */
3721         haswell_mode_set_planes_workaround(intel_crtc);
3722         haswell_crtc_enable_planes(crtc);
3723
3724         /*
3725          * There seems to be a race in PCH platform hw (at least on some
3726          * outputs) where an enabled pipe still completes any pageflip right
3727          * away (as if the pipe is off) instead of waiting for vblank. As soon
3728          * as the first vblank happend, everything works as expected. Hence just
3729          * wait for one vblank before returning to avoid strange things
3730          * happening.
3731          */
3732         intel_wait_for_vblank(dev, intel_crtc->pipe);
3733 }
3734
3735 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3736 {
3737         struct drm_device *dev = crtc->base.dev;
3738         struct drm_i915_private *dev_priv = dev->dev_private;
3739         int pipe = crtc->pipe;
3740
3741         /* To avoid upsetting the power well on haswell only disable the pfit if
3742          * it's in use. The hw state code will make sure we get this right. */
3743         if (crtc->config.pch_pfit.enabled) {
3744                 I915_WRITE(PF_CTL(pipe), 0);
3745                 I915_WRITE(PF_WIN_POS(pipe), 0);
3746                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3747         }
3748 }
3749
3750 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3751 {
3752         struct drm_device *dev = crtc->dev;
3753         struct drm_i915_private *dev_priv = dev->dev_private;
3754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3755         struct intel_encoder *encoder;
3756         int pipe = intel_crtc->pipe;
3757         int plane = intel_crtc->plane;
3758         u32 reg, temp;
3759
3760
3761         if (!intel_crtc->active)
3762                 return;
3763
3764         for_each_encoder_on_crtc(dev, crtc, encoder)
3765                 encoder->disable(encoder);
3766
3767         intel_crtc_wait_for_pending_flips(crtc);
3768         drm_vblank_off(dev, pipe);
3769
3770         if (dev_priv->fbc.plane == plane)
3771                 intel_disable_fbc(dev);
3772
3773         intel_crtc_update_cursor(crtc, false);
3774         intel_disable_planes(crtc);
3775         intel_disable_primary_plane(dev_priv, plane, pipe);
3776
3777         if (intel_crtc->config.has_pch_encoder)
3778                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3779
3780         intel_disable_pipe(dev_priv, pipe);
3781
3782         ironlake_pfit_disable(intel_crtc);
3783
3784         for_each_encoder_on_crtc(dev, crtc, encoder)
3785                 if (encoder->post_disable)
3786                         encoder->post_disable(encoder);
3787
3788         if (intel_crtc->config.has_pch_encoder) {
3789                 ironlake_fdi_disable(crtc);
3790
3791                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3792                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3793
3794                 if (HAS_PCH_CPT(dev)) {
3795                         /* disable TRANS_DP_CTL */
3796                         reg = TRANS_DP_CTL(pipe);
3797                         temp = I915_READ(reg);
3798                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3799                                   TRANS_DP_PORT_SEL_MASK);
3800                         temp |= TRANS_DP_PORT_SEL_NONE;
3801                         I915_WRITE(reg, temp);
3802
3803                         /* disable DPLL_SEL */
3804                         temp = I915_READ(PCH_DPLL_SEL);
3805                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3806                         I915_WRITE(PCH_DPLL_SEL, temp);
3807                 }
3808
3809                 /* disable PCH DPLL */
3810                 intel_disable_shared_dpll(intel_crtc);
3811
3812                 ironlake_fdi_pll_disable(intel_crtc);
3813         }
3814
3815         intel_crtc->active = false;
3816         intel_update_watermarks(crtc);
3817
3818         mutex_lock(&dev->struct_mutex);
3819         intel_update_fbc(dev);
3820         mutex_unlock(&dev->struct_mutex);
3821 }
3822
3823 static void haswell_crtc_disable(struct drm_crtc *crtc)
3824 {
3825         struct drm_device *dev = crtc->dev;
3826         struct drm_i915_private *dev_priv = dev->dev_private;
3827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3828         struct intel_encoder *encoder;
3829         int pipe = intel_crtc->pipe;
3830         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3831
3832         if (!intel_crtc->active)
3833                 return;
3834
3835         haswell_crtc_disable_planes(crtc);
3836
3837         for_each_encoder_on_crtc(dev, crtc, encoder) {
3838                 intel_opregion_notify_encoder(encoder, false);
3839                 encoder->disable(encoder);
3840         }
3841
3842         if (intel_crtc->config.has_pch_encoder)
3843                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3844         intel_disable_pipe(dev_priv, pipe);
3845
3846         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3847
3848         ironlake_pfit_disable(intel_crtc);
3849
3850         intel_ddi_disable_pipe_clock(intel_crtc);
3851
3852         for_each_encoder_on_crtc(dev, crtc, encoder)
3853                 if (encoder->post_disable)
3854                         encoder->post_disable(encoder);
3855
3856         if (intel_crtc->config.has_pch_encoder) {
3857                 lpt_disable_pch_transcoder(dev_priv);
3858                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3859                 intel_ddi_fdi_disable(crtc);
3860         }
3861
3862         intel_crtc->active = false;
3863         intel_update_watermarks(crtc);
3864
3865         mutex_lock(&dev->struct_mutex);
3866         intel_update_fbc(dev);
3867         mutex_unlock(&dev->struct_mutex);
3868 }
3869
3870 static void ironlake_crtc_off(struct drm_crtc *crtc)
3871 {
3872         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3873         intel_put_shared_dpll(intel_crtc);
3874 }
3875
3876 static void haswell_crtc_off(struct drm_crtc *crtc)
3877 {
3878         intel_ddi_put_crtc_pll(crtc);
3879 }
3880
3881 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3882 {
3883         if (!enable && intel_crtc->overlay) {
3884                 struct drm_device *dev = intel_crtc->base.dev;
3885                 struct drm_i915_private *dev_priv = dev->dev_private;
3886
3887                 mutex_lock(&dev->struct_mutex);
3888                 dev_priv->mm.interruptible = false;
3889                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3890                 dev_priv->mm.interruptible = true;
3891                 mutex_unlock(&dev->struct_mutex);
3892         }
3893
3894         /* Let userspace switch the overlay on again. In most cases userspace
3895          * has to recompute where to put it anyway.
3896          */
3897 }
3898
3899 /**
3900  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3901  * cursor plane briefly if not already running after enabling the display
3902  * plane.
3903  * This workaround avoids occasional blank screens when self refresh is
3904  * enabled.
3905  */
3906 static void
3907 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3908 {
3909         u32 cntl = I915_READ(CURCNTR(pipe));
3910
3911         if ((cntl & CURSOR_MODE) == 0) {
3912                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3913
3914                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3915                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3916                 intel_wait_for_vblank(dev_priv->dev, pipe);
3917                 I915_WRITE(CURCNTR(pipe), cntl);
3918                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3919                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3920         }
3921 }
3922
3923 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3924 {
3925         struct drm_device *dev = crtc->base.dev;
3926         struct drm_i915_private *dev_priv = dev->dev_private;
3927         struct intel_crtc_config *pipe_config = &crtc->config;
3928
3929         if (!crtc->config.gmch_pfit.control)
3930                 return;
3931
3932         /*
3933          * The panel fitter should only be adjusted whilst the pipe is disabled,
3934          * according to register description and PRM.
3935          */
3936         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3937         assert_pipe_disabled(dev_priv, crtc->pipe);
3938
3939         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3940         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3941
3942         /* Border color in case we don't scale up to the full screen. Black by
3943          * default, change to something else for debugging. */
3944         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3945 }
3946
3947 int valleyview_get_vco(struct drm_i915_private *dev_priv)
3948 {
3949         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
3950
3951         /* Obtain SKU information */
3952         mutex_lock(&dev_priv->dpio_lock);
3953         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3954                 CCK_FUSE_HPLL_FREQ_MASK;
3955         mutex_unlock(&dev_priv->dpio_lock);
3956
3957         return vco_freq[hpll_freq];
3958 }
3959
3960 /* Adjust CDclk dividers to allow high res or save power if possible */
3961 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3962 {
3963         struct drm_i915_private *dev_priv = dev->dev_private;
3964         u32 val, cmd;
3965
3966         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3967                 cmd = 2;
3968         else if (cdclk == 266)
3969                 cmd = 1;
3970         else
3971                 cmd = 0;
3972
3973         mutex_lock(&dev_priv->rps.hw_lock);
3974         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3975         val &= ~DSPFREQGUAR_MASK;
3976         val |= (cmd << DSPFREQGUAR_SHIFT);
3977         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
3978         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
3979                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
3980                      50)) {
3981                 DRM_ERROR("timed out waiting for CDclk change\n");
3982         }
3983         mutex_unlock(&dev_priv->rps.hw_lock);
3984
3985         if (cdclk == 400) {
3986                 u32 divider, vco;
3987
3988                 vco = valleyview_get_vco(dev_priv);
3989                 divider = ((vco << 1) / cdclk) - 1;
3990
3991                 mutex_lock(&dev_priv->dpio_lock);
3992                 /* adjust cdclk divider */
3993                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
3994                 val &= ~0xf;
3995                 val |= divider;
3996                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
3997                 mutex_unlock(&dev_priv->dpio_lock);
3998         }
3999
4000         mutex_lock(&dev_priv->dpio_lock);
4001         /* adjust self-refresh exit latency value */
4002         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4003         val &= ~0x7f;
4004
4005         /*
4006          * For high bandwidth configs, we set a higher latency in the bunit
4007          * so that the core display fetch happens in time to avoid underruns.
4008          */
4009         if (cdclk == 400)
4010                 val |= 4500 / 250; /* 4.5 usec */
4011         else
4012                 val |= 3000 / 250; /* 3.0 usec */
4013         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4014         mutex_unlock(&dev_priv->dpio_lock);
4015
4016         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4017         intel_i2c_reset(dev);
4018 }
4019
4020 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4021 {
4022         int cur_cdclk, vco;
4023         int divider;
4024
4025         vco = valleyview_get_vco(dev_priv);
4026
4027         mutex_lock(&dev_priv->dpio_lock);
4028         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4029         mutex_unlock(&dev_priv->dpio_lock);
4030
4031         divider &= 0xf;
4032
4033         cur_cdclk = (vco << 1) / (divider + 1);
4034
4035         return cur_cdclk;
4036 }
4037
4038 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4039                                  int max_pixclk)
4040 {
4041         int cur_cdclk;
4042
4043         cur_cdclk = valleyview_cur_cdclk(dev_priv);
4044
4045         /*
4046          * Really only a few cases to deal with, as only 4 CDclks are supported:
4047          *   200MHz
4048          *   267MHz
4049          *   320MHz
4050          *   400MHz
4051          * So we check to see whether we're above 90% of the lower bin and
4052          * adjust if needed.
4053          */
4054         if (max_pixclk > 288000) {
4055                 return 400;
4056         } else if (max_pixclk > 240000) {
4057                 return 320;
4058         } else
4059                 return 266;
4060         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4061 }
4062
4063 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
4064                                  unsigned modeset_pipes,
4065                                  struct intel_crtc_config *pipe_config)
4066 {
4067         struct drm_device *dev = dev_priv->dev;
4068         struct intel_crtc *intel_crtc;
4069         int max_pixclk = 0;
4070
4071         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4072                             base.head) {
4073                 if (modeset_pipes & (1 << intel_crtc->pipe))
4074                         max_pixclk = max(max_pixclk,
4075                                          pipe_config->adjusted_mode.crtc_clock);
4076                 else if (intel_crtc->base.enabled)
4077                         max_pixclk = max(max_pixclk,
4078                                          intel_crtc->config.adjusted_mode.crtc_clock);
4079         }
4080
4081         return max_pixclk;
4082 }
4083
4084 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4085                                             unsigned *prepare_pipes,
4086                                             unsigned modeset_pipes,
4087                                             struct intel_crtc_config *pipe_config)
4088 {
4089         struct drm_i915_private *dev_priv = dev->dev_private;
4090         struct intel_crtc *intel_crtc;
4091         int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes,
4092                                                pipe_config);
4093         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4094
4095         if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4096                 return;
4097
4098         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4099                             base.head)
4100                 if (intel_crtc->base.enabled)
4101                         *prepare_pipes |= (1 << intel_crtc->pipe);
4102 }
4103
4104 static void valleyview_modeset_global_resources(struct drm_device *dev)
4105 {
4106         struct drm_i915_private *dev_priv = dev->dev_private;
4107         int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL);
4108         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4109         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4110
4111         if (req_cdclk != cur_cdclk)
4112                 valleyview_set_cdclk(dev, req_cdclk);
4113 }
4114
4115 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4116 {
4117         struct drm_device *dev = crtc->dev;
4118         struct drm_i915_private *dev_priv = dev->dev_private;
4119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4120         struct intel_encoder *encoder;
4121         int pipe = intel_crtc->pipe;
4122         int plane = intel_crtc->plane;
4123         bool is_dsi;
4124
4125         WARN_ON(!crtc->enabled);
4126
4127         if (intel_crtc->active)
4128                 return;
4129
4130         intel_crtc->active = true;
4131
4132         for_each_encoder_on_crtc(dev, crtc, encoder)
4133                 if (encoder->pre_pll_enable)
4134                         encoder->pre_pll_enable(encoder);
4135
4136         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4137
4138         if (!is_dsi)
4139                 vlv_enable_pll(intel_crtc);
4140
4141         for_each_encoder_on_crtc(dev, crtc, encoder)
4142                 if (encoder->pre_enable)
4143                         encoder->pre_enable(encoder);
4144
4145         i9xx_pfit_enable(intel_crtc);
4146
4147         intel_crtc_load_lut(crtc);
4148
4149         intel_update_watermarks(crtc);
4150         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
4151         intel_enable_primary_plane(dev_priv, plane, pipe);
4152         intel_enable_planes(crtc);
4153         intel_crtc_update_cursor(crtc, true);
4154
4155         intel_update_fbc(dev);
4156
4157         for_each_encoder_on_crtc(dev, crtc, encoder)
4158                 encoder->enable(encoder);
4159 }
4160
4161 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4162 {
4163         struct drm_device *dev = crtc->dev;
4164         struct drm_i915_private *dev_priv = dev->dev_private;
4165         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4166         struct intel_encoder *encoder;
4167         int pipe = intel_crtc->pipe;
4168         int plane = intel_crtc->plane;
4169
4170         WARN_ON(!crtc->enabled);
4171
4172         if (intel_crtc->active)
4173                 return;
4174
4175         intel_crtc->active = true;
4176
4177         for_each_encoder_on_crtc(dev, crtc, encoder)
4178                 if (encoder->pre_enable)
4179                         encoder->pre_enable(encoder);
4180
4181         i9xx_enable_pll(intel_crtc);
4182
4183         i9xx_pfit_enable(intel_crtc);
4184
4185         intel_crtc_load_lut(crtc);
4186
4187         intel_update_watermarks(crtc);
4188         intel_enable_pipe(dev_priv, pipe, false, false);
4189         intel_enable_primary_plane(dev_priv, plane, pipe);
4190         intel_enable_planes(crtc);
4191         /* The fixup needs to happen before cursor is enabled */
4192         if (IS_G4X(dev))
4193                 g4x_fixup_plane(dev_priv, pipe);
4194         intel_crtc_update_cursor(crtc, true);
4195
4196         /* Give the overlay scaler a chance to enable if it's on this pipe */
4197         intel_crtc_dpms_overlay(intel_crtc, true);
4198
4199         intel_update_fbc(dev);
4200
4201         for_each_encoder_on_crtc(dev, crtc, encoder)
4202                 encoder->enable(encoder);
4203 }
4204
4205 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4206 {
4207         struct drm_device *dev = crtc->base.dev;
4208         struct drm_i915_private *dev_priv = dev->dev_private;
4209
4210         if (!crtc->config.gmch_pfit.control)
4211                 return;
4212
4213         assert_pipe_disabled(dev_priv, crtc->pipe);
4214
4215         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4216                          I915_READ(PFIT_CONTROL));
4217         I915_WRITE(PFIT_CONTROL, 0);
4218 }
4219
4220 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4221 {
4222         struct drm_device *dev = crtc->dev;
4223         struct drm_i915_private *dev_priv = dev->dev_private;
4224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4225         struct intel_encoder *encoder;
4226         int pipe = intel_crtc->pipe;
4227         int plane = intel_crtc->plane;
4228
4229         if (!intel_crtc->active)
4230                 return;
4231
4232         for_each_encoder_on_crtc(dev, crtc, encoder)
4233                 encoder->disable(encoder);
4234
4235         /* Give the overlay scaler a chance to disable if it's on this pipe */
4236         intel_crtc_wait_for_pending_flips(crtc);
4237         drm_vblank_off(dev, pipe);
4238
4239         if (dev_priv->fbc.plane == plane)
4240                 intel_disable_fbc(dev);
4241
4242         intel_crtc_dpms_overlay(intel_crtc, false);
4243         intel_crtc_update_cursor(crtc, false);
4244         intel_disable_planes(crtc);
4245         intel_disable_primary_plane(dev_priv, plane, pipe);
4246
4247         intel_disable_pipe(dev_priv, pipe);
4248
4249         i9xx_pfit_disable(intel_crtc);
4250
4251         for_each_encoder_on_crtc(dev, crtc, encoder)
4252                 if (encoder->post_disable)
4253                         encoder->post_disable(encoder);
4254
4255         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4256                 vlv_disable_pll(dev_priv, pipe);
4257         else if (!IS_VALLEYVIEW(dev))
4258                 i9xx_disable_pll(dev_priv, pipe);
4259
4260         intel_crtc->active = false;
4261         intel_update_watermarks(crtc);
4262
4263         intel_update_fbc(dev);
4264 }
4265
4266 static void i9xx_crtc_off(struct drm_crtc *crtc)
4267 {
4268 }
4269
4270 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4271                                     bool enabled)
4272 {
4273         struct drm_device *dev = crtc->dev;
4274         struct drm_i915_master_private *master_priv;
4275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4276         int pipe = intel_crtc->pipe;
4277
4278         if (!dev->primary->master)
4279                 return;
4280
4281         master_priv = dev->primary->master->driver_priv;
4282         if (!master_priv->sarea_priv)
4283                 return;
4284
4285         switch (pipe) {
4286         case 0:
4287                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4288                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4289                 break;
4290         case 1:
4291                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4292                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4293                 break;
4294         default:
4295                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4296                 break;
4297         }
4298 }
4299
4300 /**
4301  * Sets the power management mode of the pipe and plane.
4302  */
4303 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4304 {
4305         struct drm_device *dev = crtc->dev;
4306         struct drm_i915_private *dev_priv = dev->dev_private;
4307         struct intel_encoder *intel_encoder;
4308         bool enable = false;
4309
4310         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4311                 enable |= intel_encoder->connectors_active;
4312
4313         if (enable)
4314                 dev_priv->display.crtc_enable(crtc);
4315         else
4316                 dev_priv->display.crtc_disable(crtc);
4317
4318         intel_crtc_update_sarea(crtc, enable);
4319 }
4320
4321 static void intel_crtc_disable(struct drm_crtc *crtc)
4322 {
4323         struct drm_device *dev = crtc->dev;
4324         struct drm_connector *connector;
4325         struct drm_i915_private *dev_priv = dev->dev_private;
4326         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4327
4328         /* crtc should still be enabled when we disable it. */
4329         WARN_ON(!crtc->enabled);
4330
4331         dev_priv->display.crtc_disable(crtc);
4332         intel_crtc->eld_vld = false;
4333         intel_crtc_update_sarea(crtc, false);
4334         dev_priv->display.off(crtc);
4335
4336         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4337         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4338         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4339
4340         if (crtc->fb) {
4341                 mutex_lock(&dev->struct_mutex);
4342                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4343                 mutex_unlock(&dev->struct_mutex);
4344                 crtc->fb = NULL;
4345         }
4346
4347         /* Update computed state. */
4348         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4349                 if (!connector->encoder || !connector->encoder->crtc)
4350                         continue;
4351
4352                 if (connector->encoder->crtc != crtc)
4353                         continue;
4354
4355                 connector->dpms = DRM_MODE_DPMS_OFF;
4356                 to_intel_encoder(connector->encoder)->connectors_active = false;
4357         }
4358 }
4359
4360 void intel_encoder_destroy(struct drm_encoder *encoder)
4361 {
4362         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4363
4364         drm_encoder_cleanup(encoder);
4365         kfree(intel_encoder);
4366 }
4367
4368 /* Simple dpms helper for encoders with just one connector, no cloning and only
4369  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4370  * state of the entire output pipe. */
4371 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4372 {
4373         if (mode == DRM_MODE_DPMS_ON) {
4374                 encoder->connectors_active = true;
4375
4376                 intel_crtc_update_dpms(encoder->base.crtc);
4377         } else {
4378                 encoder->connectors_active = false;
4379
4380                 intel_crtc_update_dpms(encoder->base.crtc);
4381         }
4382 }
4383
4384 /* Cross check the actual hw state with our own modeset state tracking (and it's
4385  * internal consistency). */
4386 static void intel_connector_check_state(struct intel_connector *connector)
4387 {
4388         if (connector->get_hw_state(connector)) {
4389                 struct intel_encoder *encoder = connector->encoder;
4390                 struct drm_crtc *crtc;
4391                 bool encoder_enabled;
4392                 enum pipe pipe;
4393
4394                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4395                               connector->base.base.id,
4396                               drm_get_connector_name(&connector->base));
4397
4398                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4399                      "wrong connector dpms state\n");
4400                 WARN(connector->base.encoder != &encoder->base,
4401                      "active connector not linked to encoder\n");
4402                 WARN(!encoder->connectors_active,
4403                      "encoder->connectors_active not set\n");
4404
4405                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4406                 WARN(!encoder_enabled, "encoder not enabled\n");
4407                 if (WARN_ON(!encoder->base.crtc))
4408                         return;
4409
4410                 crtc = encoder->base.crtc;
4411
4412                 WARN(!crtc->enabled, "crtc not enabled\n");
4413                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4414                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4415                      "encoder active on the wrong pipe\n");
4416         }
4417 }
4418
4419 /* Even simpler default implementation, if there's really no special case to
4420  * consider. */
4421 void intel_connector_dpms(struct drm_connector *connector, int mode)
4422 {
4423         /* All the simple cases only support two dpms states. */
4424         if (mode != DRM_MODE_DPMS_ON)
4425                 mode = DRM_MODE_DPMS_OFF;
4426
4427         if (mode == connector->dpms)
4428                 return;
4429
4430         connector->dpms = mode;
4431
4432         /* Only need to change hw state when actually enabled */
4433         if (connector->encoder)
4434                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4435
4436         intel_modeset_check_state(connector->dev);
4437 }
4438
4439 /* Simple connector->get_hw_state implementation for encoders that support only
4440  * one connector and no cloning and hence the encoder state determines the state
4441  * of the connector. */
4442 bool intel_connector_get_hw_state(struct intel_connector *connector)
4443 {
4444         enum pipe pipe = 0;
4445         struct intel_encoder *encoder = connector->encoder;
4446
4447         return encoder->get_hw_state(encoder, &pipe);
4448 }
4449
4450 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4451                                      struct intel_crtc_config *pipe_config)
4452 {
4453         struct drm_i915_private *dev_priv = dev->dev_private;
4454         struct intel_crtc *pipe_B_crtc =
4455                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4456
4457         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4458                       pipe_name(pipe), pipe_config->fdi_lanes);
4459         if (pipe_config->fdi_lanes > 4) {
4460                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4461                               pipe_name(pipe), pipe_config->fdi_lanes);
4462                 return false;
4463         }
4464
4465         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4466                 if (pipe_config->fdi_lanes > 2) {
4467                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4468                                       pipe_config->fdi_lanes);
4469                         return false;
4470                 } else {
4471                         return true;
4472                 }
4473         }
4474
4475         if (INTEL_INFO(dev)->num_pipes == 2)
4476                 return true;
4477
4478         /* Ivybridge 3 pipe is really complicated */
4479         switch (pipe) {
4480         case PIPE_A:
4481                 return true;
4482         case PIPE_B:
4483                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4484                     pipe_config->fdi_lanes > 2) {
4485                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4486                                       pipe_name(pipe), pipe_config->fdi_lanes);
4487                         return false;
4488                 }
4489                 return true;
4490         case PIPE_C:
4491                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4492                     pipe_B_crtc->config.fdi_lanes <= 2) {
4493                         if (pipe_config->fdi_lanes > 2) {
4494                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4495                                               pipe_name(pipe), pipe_config->fdi_lanes);
4496                                 return false;
4497                         }
4498                 } else {
4499                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4500                         return false;
4501                 }
4502                 return true;
4503         default:
4504                 BUG();
4505         }
4506 }
4507
4508 #define RETRY 1
4509 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4510                                        struct intel_crtc_config *pipe_config)
4511 {
4512         struct drm_device *dev = intel_crtc->base.dev;
4513         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4514         int lane, link_bw, fdi_dotclock;
4515         bool setup_ok, needs_recompute = false;
4516
4517 retry:
4518         /* FDI is a binary signal running at ~2.7GHz, encoding
4519          * each output octet as 10 bits. The actual frequency
4520          * is stored as a divider into a 100MHz clock, and the
4521          * mode pixel clock is stored in units of 1KHz.
4522          * Hence the bw of each lane in terms of the mode signal
4523          * is:
4524          */
4525         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4526
4527         fdi_dotclock = adjusted_mode->crtc_clock;
4528
4529         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4530                                            pipe_config->pipe_bpp);
4531
4532         pipe_config->fdi_lanes = lane;
4533
4534         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4535                                link_bw, &pipe_config->fdi_m_n);
4536
4537         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4538                                             intel_crtc->pipe, pipe_config);
4539         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4540                 pipe_config->pipe_bpp -= 2*3;
4541                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4542                               pipe_config->pipe_bpp);
4543                 needs_recompute = true;
4544                 pipe_config->bw_constrained = true;
4545
4546                 goto retry;
4547         }
4548
4549         if (needs_recompute)
4550                 return RETRY;
4551
4552         return setup_ok ? 0 : -EINVAL;
4553 }
4554
4555 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4556                                    struct intel_crtc_config *pipe_config)
4557 {
4558         pipe_config->ips_enabled = i915_enable_ips &&
4559                                    hsw_crtc_supports_ips(crtc) &&
4560                                    pipe_config->pipe_bpp <= 24;
4561 }
4562
4563 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4564                                      struct intel_crtc_config *pipe_config)
4565 {
4566         struct drm_device *dev = crtc->base.dev;
4567         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4568
4569         /* FIXME should check pixel clock limits on all platforms */
4570         if (INTEL_INFO(dev)->gen < 4) {
4571                 struct drm_i915_private *dev_priv = dev->dev_private;
4572                 int clock_limit =
4573                         dev_priv->display.get_display_clock_speed(dev);
4574
4575                 /*
4576                  * Enable pixel doubling when the dot clock
4577                  * is > 90% of the (display) core speed.
4578                  *
4579                  * GDG double wide on either pipe,
4580                  * otherwise pipe A only.
4581                  */
4582                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4583                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4584                         clock_limit *= 2;
4585                         pipe_config->double_wide = true;
4586                 }
4587
4588                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4589                         return -EINVAL;
4590         }
4591
4592         /*
4593          * Pipe horizontal size must be even in:
4594          * - DVO ganged mode
4595          * - LVDS dual channel mode
4596          * - Double wide pipe
4597          */
4598         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4599              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4600                 pipe_config->pipe_src_w &= ~1;
4601
4602         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4603          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4604          */
4605         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4606                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4607                 return -EINVAL;
4608
4609         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4610                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4611         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4612                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4613                  * for lvds. */
4614                 pipe_config->pipe_bpp = 8*3;
4615         }
4616
4617         if (HAS_IPS(dev))
4618                 hsw_compute_ips_config(crtc, pipe_config);
4619
4620         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4621          * clock survives for now. */
4622         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4623                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4624
4625         if (pipe_config->has_pch_encoder)
4626                 return ironlake_fdi_compute_config(crtc, pipe_config);
4627
4628         return 0;
4629 }
4630
4631 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4632 {
4633         return 400000; /* FIXME */
4634 }
4635
4636 static int i945_get_display_clock_speed(struct drm_device *dev)
4637 {
4638         return 400000;
4639 }
4640
4641 static int i915_get_display_clock_speed(struct drm_device *dev)
4642 {
4643         return 333000;
4644 }
4645
4646 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4647 {
4648         return 200000;
4649 }
4650
4651 static int pnv_get_display_clock_speed(struct drm_device *dev)
4652 {
4653         u16 gcfgc = 0;
4654
4655         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4656
4657         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4658         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4659                 return 267000;
4660         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4661                 return 333000;
4662         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4663                 return 444000;
4664         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4665                 return 200000;
4666         default:
4667                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4668         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4669                 return 133000;
4670         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4671                 return 167000;
4672         }
4673 }
4674
4675 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4676 {
4677         u16 gcfgc = 0;
4678
4679         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4680
4681         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4682                 return 133000;
4683         else {
4684                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4685                 case GC_DISPLAY_CLOCK_333_MHZ:
4686                         return 333000;
4687                 default:
4688                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4689                         return 190000;
4690                 }
4691         }
4692 }
4693
4694 static int i865_get_display_clock_speed(struct drm_device *dev)
4695 {
4696         return 266000;
4697 }
4698
4699 static int i855_get_display_clock_speed(struct drm_device *dev)
4700 {
4701         u16 hpllcc = 0;
4702         /* Assume that the hardware is in the high speed state.  This
4703          * should be the default.
4704          */
4705         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4706         case GC_CLOCK_133_200:
4707         case GC_CLOCK_100_200:
4708                 return 200000;
4709         case GC_CLOCK_166_250:
4710                 return 250000;
4711         case GC_CLOCK_100_133:
4712                 return 133000;
4713         }
4714
4715         /* Shouldn't happen */
4716         return 0;
4717 }
4718
4719 static int i830_get_display_clock_speed(struct drm_device *dev)
4720 {
4721         return 133000;
4722 }
4723
4724 static void
4725 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4726 {
4727         while (*num > DATA_LINK_M_N_MASK ||
4728                *den > DATA_LINK_M_N_MASK) {
4729                 *num >>= 1;
4730                 *den >>= 1;
4731         }
4732 }
4733
4734 static void compute_m_n(unsigned int m, unsigned int n,
4735                         uint32_t *ret_m, uint32_t *ret_n)
4736 {
4737         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4738         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4739         intel_reduce_m_n_ratio(ret_m, ret_n);
4740 }
4741
4742 void
4743 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4744                        int pixel_clock, int link_clock,
4745                        struct intel_link_m_n *m_n)
4746 {
4747         m_n->tu = 64;
4748
4749         compute_m_n(bits_per_pixel * pixel_clock,
4750                     link_clock * nlanes * 8,
4751                     &m_n->gmch_m, &m_n->gmch_n);
4752
4753         compute_m_n(pixel_clock, link_clock,
4754                     &m_n->link_m, &m_n->link_n);
4755 }
4756
4757 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4758 {
4759         if (i915_panel_use_ssc >= 0)
4760                 return i915_panel_use_ssc != 0;
4761         return dev_priv->vbt.lvds_use_ssc
4762                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4763 }
4764
4765 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4766 {
4767         struct drm_device *dev = crtc->dev;
4768         struct drm_i915_private *dev_priv = dev->dev_private;
4769         int refclk;
4770
4771         if (IS_VALLEYVIEW(dev)) {
4772                 refclk = 100000;
4773         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4774             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4775                 refclk = dev_priv->vbt.lvds_ssc_freq;
4776                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4777         } else if (!IS_GEN2(dev)) {
4778                 refclk = 96000;
4779         } else {
4780                 refclk = 48000;
4781         }
4782
4783         return refclk;
4784 }
4785
4786 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4787 {
4788         return (1 << dpll->n) << 16 | dpll->m2;
4789 }
4790
4791 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4792 {
4793         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4794 }
4795
4796 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4797                                      intel_clock_t *reduced_clock)
4798 {
4799         struct drm_device *dev = crtc->base.dev;
4800         struct drm_i915_private *dev_priv = dev->dev_private;
4801         int pipe = crtc->pipe;
4802         u32 fp, fp2 = 0;
4803
4804         if (IS_PINEVIEW(dev)) {
4805                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4806                 if (reduced_clock)
4807                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4808         } else {
4809                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4810                 if (reduced_clock)
4811                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4812         }
4813
4814         I915_WRITE(FP0(pipe), fp);
4815         crtc->config.dpll_hw_state.fp0 = fp;
4816
4817         crtc->lowfreq_avail = false;
4818         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4819             reduced_clock && i915_powersave) {
4820                 I915_WRITE(FP1(pipe), fp2);
4821                 crtc->config.dpll_hw_state.fp1 = fp2;
4822                 crtc->lowfreq_avail = true;
4823         } else {
4824                 I915_WRITE(FP1(pipe), fp);
4825                 crtc->config.dpll_hw_state.fp1 = fp;
4826         }
4827 }
4828
4829 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4830                 pipe)
4831 {
4832         u32 reg_val;
4833
4834         /*
4835          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4836          * and set it to a reasonable value instead.
4837          */
4838         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4839         reg_val &= 0xffffff00;
4840         reg_val |= 0x00000030;
4841         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4842
4843         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4844         reg_val &= 0x8cffffff;
4845         reg_val = 0x8c000000;
4846         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4847
4848         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4849         reg_val &= 0xffffff00;
4850         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4851
4852         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4853         reg_val &= 0x00ffffff;
4854         reg_val |= 0xb0000000;
4855         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4856 }
4857
4858 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4859                                          struct intel_link_m_n *m_n)
4860 {
4861         struct drm_device *dev = crtc->base.dev;
4862         struct drm_i915_private *dev_priv = dev->dev_private;
4863         int pipe = crtc->pipe;
4864
4865         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4866         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4867         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4868         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4869 }
4870
4871 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4872                                          struct intel_link_m_n *m_n)
4873 {
4874         struct drm_device *dev = crtc->base.dev;
4875         struct drm_i915_private *dev_priv = dev->dev_private;
4876         int pipe = crtc->pipe;
4877         enum transcoder transcoder = crtc->config.cpu_transcoder;
4878
4879         if (INTEL_INFO(dev)->gen >= 5) {
4880                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4881                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4882                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4883                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4884         } else {
4885                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4886                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4887                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4888                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4889         }
4890 }
4891
4892 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4893 {
4894         if (crtc->config.has_pch_encoder)
4895                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4896         else
4897                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4898 }
4899
4900 static void vlv_update_pll(struct intel_crtc *crtc)
4901 {
4902         struct drm_device *dev = crtc->base.dev;
4903         struct drm_i915_private *dev_priv = dev->dev_private;
4904         int pipe = crtc->pipe;
4905         u32 dpll, mdiv;
4906         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4907         u32 coreclk, reg_val, dpll_md;
4908
4909         mutex_lock(&dev_priv->dpio_lock);
4910
4911         bestn = crtc->config.dpll.n;
4912         bestm1 = crtc->config.dpll.m1;
4913         bestm2 = crtc->config.dpll.m2;
4914         bestp1 = crtc->config.dpll.p1;
4915         bestp2 = crtc->config.dpll.p2;
4916
4917         /* See eDP HDMI DPIO driver vbios notes doc */
4918
4919         /* PLL B needs special handling */
4920         if (pipe)
4921                 vlv_pllb_recal_opamp(dev_priv, pipe);
4922
4923         /* Set up Tx target for periodic Rcomp update */
4924         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4925
4926         /* Disable target IRef on PLL */
4927         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4928         reg_val &= 0x00ffffff;
4929         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4930
4931         /* Disable fast lock */
4932         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4933
4934         /* Set idtafcrecal before PLL is enabled */
4935         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4936         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4937         mdiv |= ((bestn << DPIO_N_SHIFT));
4938         mdiv |= (1 << DPIO_K_SHIFT);
4939
4940         /*
4941          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4942          * but we don't support that).
4943          * Note: don't use the DAC post divider as it seems unstable.
4944          */
4945         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4946         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4947
4948         mdiv |= DPIO_ENABLE_CALIBRATION;
4949         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4950
4951         /* Set HBR and RBR LPF coefficients */
4952         if (crtc->config.port_clock == 162000 ||
4953             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4954             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4955                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4956                                  0x009f0003);
4957         else
4958                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4959                                  0x00d0000f);
4960
4961         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4962             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4963                 /* Use SSC source */
4964                 if (!pipe)
4965                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4966                                          0x0df40000);
4967                 else
4968                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4969                                          0x0df70000);
4970         } else { /* HDMI or VGA */
4971                 /* Use bend source */
4972                 if (!pipe)
4973                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4974                                          0x0df70000);
4975                 else
4976                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4977                                          0x0df40000);
4978         }
4979
4980         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
4981         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4982         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4983             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4984                 coreclk |= 0x01000000;
4985         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
4986
4987         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
4988
4989         /* Enable DPIO clock input */
4990         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4991                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4992         /* We should never disable this, set it here for state tracking */
4993         if (pipe == PIPE_B)
4994                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4995         dpll |= DPLL_VCO_ENABLE;
4996         crtc->config.dpll_hw_state.dpll = dpll;
4997
4998         dpll_md = (crtc->config.pixel_multiplier - 1)
4999                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5000         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5001
5002         if (crtc->config.has_dp_encoder)
5003                 intel_dp_set_m_n(crtc);
5004
5005         mutex_unlock(&dev_priv->dpio_lock);
5006 }
5007
5008 static void i9xx_update_pll(struct intel_crtc *crtc,
5009                             intel_clock_t *reduced_clock,
5010                             int num_connectors)
5011 {
5012         struct drm_device *dev = crtc->base.dev;
5013         struct drm_i915_private *dev_priv = dev->dev_private;
5014         u32 dpll;
5015         bool is_sdvo;
5016         struct dpll *clock = &crtc->config.dpll;
5017
5018         i9xx_update_pll_dividers(crtc, reduced_clock);
5019
5020         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5021                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5022
5023         dpll = DPLL_VGA_MODE_DIS;
5024
5025         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5026                 dpll |= DPLLB_MODE_LVDS;
5027         else
5028                 dpll |= DPLLB_MODE_DAC_SERIAL;
5029
5030         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5031                 dpll |= (crtc->config.pixel_multiplier - 1)
5032                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5033         }
5034
5035         if (is_sdvo)
5036                 dpll |= DPLL_SDVO_HIGH_SPEED;
5037
5038         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5039                 dpll |= DPLL_SDVO_HIGH_SPEED;
5040
5041         /* compute bitmask from p1 value */
5042         if (IS_PINEVIEW(dev))
5043                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5044         else {
5045                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5046                 if (IS_G4X(dev) && reduced_clock)
5047                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5048         }
5049         switch (clock->p2) {
5050         case 5:
5051                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5052                 break;
5053         case 7:
5054                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5055                 break;
5056         case 10:
5057                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5058                 break;
5059         case 14:
5060                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5061                 break;
5062         }
5063         if (INTEL_INFO(dev)->gen >= 4)
5064                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5065
5066         if (crtc->config.sdvo_tv_clock)
5067                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5068         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5069                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5070                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5071         else
5072                 dpll |= PLL_REF_INPUT_DREFCLK;
5073
5074         dpll |= DPLL_VCO_ENABLE;
5075         crtc->config.dpll_hw_state.dpll = dpll;
5076
5077         if (INTEL_INFO(dev)->gen >= 4) {
5078                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5079                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5080                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5081         }
5082
5083         if (crtc->config.has_dp_encoder)
5084                 intel_dp_set_m_n(crtc);
5085 }
5086
5087 static void i8xx_update_pll(struct intel_crtc *crtc,
5088                             intel_clock_t *reduced_clock,
5089                             int num_connectors)
5090 {
5091         struct drm_device *dev = crtc->base.dev;
5092         struct drm_i915_private *dev_priv = dev->dev_private;
5093         u32 dpll;
5094         struct dpll *clock = &crtc->config.dpll;
5095
5096         i9xx_update_pll_dividers(crtc, reduced_clock);
5097
5098         dpll = DPLL_VGA_MODE_DIS;
5099
5100         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5101                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5102         } else {
5103                 if (clock->p1 == 2)
5104                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5105                 else
5106                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5107                 if (clock->p2 == 4)
5108                         dpll |= PLL_P2_DIVIDE_BY_4;
5109         }
5110
5111         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5112                 dpll |= DPLL_DVO_2X_MODE;
5113
5114         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5115                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5116                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5117         else
5118                 dpll |= PLL_REF_INPUT_DREFCLK;
5119
5120         dpll |= DPLL_VCO_ENABLE;
5121         crtc->config.dpll_hw_state.dpll = dpll;
5122 }
5123
5124 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5125 {
5126         struct drm_device *dev = intel_crtc->base.dev;
5127         struct drm_i915_private *dev_priv = dev->dev_private;
5128         enum pipe pipe = intel_crtc->pipe;
5129         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5130         struct drm_display_mode *adjusted_mode =
5131                 &intel_crtc->config.adjusted_mode;
5132         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5133
5134         /* We need to be careful not to changed the adjusted mode, for otherwise
5135          * the hw state checker will get angry at the mismatch. */
5136         crtc_vtotal = adjusted_mode->crtc_vtotal;
5137         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5138
5139         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5140                 /* the chip adds 2 halflines automatically */
5141                 crtc_vtotal -= 1;
5142                 crtc_vblank_end -= 1;
5143                 vsyncshift = adjusted_mode->crtc_hsync_start
5144                              - adjusted_mode->crtc_htotal / 2;
5145         } else {
5146                 vsyncshift = 0;
5147         }
5148
5149         if (INTEL_INFO(dev)->gen > 3)
5150                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5151
5152         I915_WRITE(HTOTAL(cpu_transcoder),
5153                    (adjusted_mode->crtc_hdisplay - 1) |
5154                    ((adjusted_mode->crtc_htotal - 1) << 16));
5155         I915_WRITE(HBLANK(cpu_transcoder),
5156                    (adjusted_mode->crtc_hblank_start - 1) |
5157                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5158         I915_WRITE(HSYNC(cpu_transcoder),
5159                    (adjusted_mode->crtc_hsync_start - 1) |
5160                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5161
5162         I915_WRITE(VTOTAL(cpu_transcoder),
5163                    (adjusted_mode->crtc_vdisplay - 1) |
5164                    ((crtc_vtotal - 1) << 16));
5165         I915_WRITE(VBLANK(cpu_transcoder),
5166                    (adjusted_mode->crtc_vblank_start - 1) |
5167                    ((crtc_vblank_end - 1) << 16));
5168         I915_WRITE(VSYNC(cpu_transcoder),
5169                    (adjusted_mode->crtc_vsync_start - 1) |
5170                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5171
5172         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5173          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5174          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5175          * bits. */
5176         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5177             (pipe == PIPE_B || pipe == PIPE_C))
5178                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5179
5180         /* pipesrc controls the size that is scaled from, which should
5181          * always be the user's requested size.
5182          */
5183         I915_WRITE(PIPESRC(pipe),
5184                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5185                    (intel_crtc->config.pipe_src_h - 1));
5186 }
5187
5188 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5189                                    struct intel_crtc_config *pipe_config)
5190 {
5191         struct drm_device *dev = crtc->base.dev;
5192         struct drm_i915_private *dev_priv = dev->dev_private;
5193         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5194         uint32_t tmp;
5195
5196         tmp = I915_READ(HTOTAL(cpu_transcoder));
5197         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5198         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5199         tmp = I915_READ(HBLANK(cpu_transcoder));
5200         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5201         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5202         tmp = I915_READ(HSYNC(cpu_transcoder));
5203         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5204         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5205
5206         tmp = I915_READ(VTOTAL(cpu_transcoder));
5207         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5208         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5209         tmp = I915_READ(VBLANK(cpu_transcoder));
5210         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5211         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5212         tmp = I915_READ(VSYNC(cpu_transcoder));
5213         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5214         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5215
5216         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5217                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5218                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5219                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5220         }
5221
5222         tmp = I915_READ(PIPESRC(crtc->pipe));
5223         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5224         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5225
5226         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5227         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5228 }
5229
5230 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5231                                              struct intel_crtc_config *pipe_config)
5232 {
5233         struct drm_crtc *crtc = &intel_crtc->base;
5234
5235         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5236         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5237         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5238         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5239
5240         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5241         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5242         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5243         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5244
5245         crtc->mode.flags = pipe_config->adjusted_mode.flags;
5246
5247         crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5248         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5249 }
5250
5251 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5252 {
5253         struct drm_device *dev = intel_crtc->base.dev;
5254         struct drm_i915_private *dev_priv = dev->dev_private;
5255         uint32_t pipeconf;
5256
5257         pipeconf = 0;
5258
5259         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5260             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5261                 pipeconf |= PIPECONF_ENABLE;
5262
5263         if (intel_crtc->config.double_wide)
5264                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5265
5266         /* only g4x and later have fancy bpc/dither controls */
5267         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5268                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5269                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5270                         pipeconf |= PIPECONF_DITHER_EN |
5271                                     PIPECONF_DITHER_TYPE_SP;
5272
5273                 switch (intel_crtc->config.pipe_bpp) {
5274                 case 18:
5275                         pipeconf |= PIPECONF_6BPC;
5276                         break;
5277                 case 24:
5278                         pipeconf |= PIPECONF_8BPC;
5279                         break;
5280                 case 30:
5281                         pipeconf |= PIPECONF_10BPC;
5282                         break;
5283                 default:
5284                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5285                         BUG();
5286                 }
5287         }
5288
5289         if (HAS_PIPE_CXSR(dev)) {
5290                 if (intel_crtc->lowfreq_avail) {
5291                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5292                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5293                 } else {
5294                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5295                 }
5296         }
5297
5298         if (!IS_GEN2(dev) &&
5299             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5300                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5301         else
5302                 pipeconf |= PIPECONF_PROGRESSIVE;
5303
5304         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5305                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5306
5307         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5308         POSTING_READ(PIPECONF(intel_crtc->pipe));
5309 }
5310
5311 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5312                               int x, int y,
5313                               struct drm_framebuffer *fb)
5314 {
5315         struct drm_device *dev = crtc->dev;
5316         struct drm_i915_private *dev_priv = dev->dev_private;
5317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5318         int pipe = intel_crtc->pipe;
5319         int plane = intel_crtc->plane;
5320         int refclk, num_connectors = 0;
5321         intel_clock_t clock, reduced_clock;
5322         u32 dspcntr;
5323         bool ok, has_reduced_clock = false;
5324         bool is_lvds = false, is_dsi = false;
5325         struct intel_encoder *encoder;
5326         const intel_limit_t *limit;
5327         int ret;
5328
5329         for_each_encoder_on_crtc(dev, crtc, encoder) {
5330                 switch (encoder->type) {
5331                 case INTEL_OUTPUT_LVDS:
5332                         is_lvds = true;
5333                         break;
5334                 case INTEL_OUTPUT_DSI:
5335                         is_dsi = true;
5336                         break;
5337                 }
5338
5339                 num_connectors++;
5340         }
5341
5342         if (is_dsi)
5343                 goto skip_dpll;
5344
5345         if (!intel_crtc->config.clock_set) {
5346                 refclk = i9xx_get_refclk(crtc, num_connectors);
5347
5348                 /*
5349                  * Returns a set of divisors for the desired target clock with
5350                  * the given refclk, or FALSE.  The returned values represent
5351                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5352                  * 2) / p1 / p2.
5353                  */
5354                 limit = intel_limit(crtc, refclk);
5355                 ok = dev_priv->display.find_dpll(limit, crtc,
5356                                                  intel_crtc->config.port_clock,
5357                                                  refclk, NULL, &clock);
5358                 if (!ok) {
5359                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5360                         return -EINVAL;
5361                 }
5362
5363                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5364                         /*
5365                          * Ensure we match the reduced clock's P to the target
5366                          * clock.  If the clocks don't match, we can't switch
5367                          * the display clock by using the FP0/FP1. In such case
5368                          * we will disable the LVDS downclock feature.
5369                          */
5370                         has_reduced_clock =
5371                                 dev_priv->display.find_dpll(limit, crtc,
5372                                                             dev_priv->lvds_downclock,
5373                                                             refclk, &clock,
5374                                                             &reduced_clock);
5375                 }
5376                 /* Compat-code for transition, will disappear. */
5377                 intel_crtc->config.dpll.n = clock.n;
5378                 intel_crtc->config.dpll.m1 = clock.m1;
5379                 intel_crtc->config.dpll.m2 = clock.m2;
5380                 intel_crtc->config.dpll.p1 = clock.p1;
5381                 intel_crtc->config.dpll.p2 = clock.p2;
5382         }
5383
5384         if (IS_GEN2(dev)) {
5385                 i8xx_update_pll(intel_crtc,
5386                                 has_reduced_clock ? &reduced_clock : NULL,
5387                                 num_connectors);
5388         } else if (IS_VALLEYVIEW(dev)) {
5389                 vlv_update_pll(intel_crtc);
5390         } else {
5391                 i9xx_update_pll(intel_crtc,
5392                                 has_reduced_clock ? &reduced_clock : NULL,
5393                                 num_connectors);
5394         }
5395
5396 skip_dpll:
5397         /* Set up the display plane register */
5398         dspcntr = DISPPLANE_GAMMA_ENABLE;
5399
5400         if (!IS_VALLEYVIEW(dev)) {
5401                 if (pipe == 0)
5402                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5403                 else
5404                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5405         }
5406
5407         intel_set_pipe_timings(intel_crtc);
5408
5409         /* pipesrc and dspsize control the size that is scaled from,
5410          * which should always be the user's requested size.
5411          */
5412         I915_WRITE(DSPSIZE(plane),
5413                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5414                    (intel_crtc->config.pipe_src_w - 1));
5415         I915_WRITE(DSPPOS(plane), 0);
5416
5417         i9xx_set_pipeconf(intel_crtc);
5418
5419         I915_WRITE(DSPCNTR(plane), dspcntr);
5420         POSTING_READ(DSPCNTR(plane));
5421
5422         ret = intel_pipe_set_base(crtc, x, y, fb);
5423
5424         return ret;
5425 }
5426
5427 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5428                                  struct intel_crtc_config *pipe_config)
5429 {
5430         struct drm_device *dev = crtc->base.dev;
5431         struct drm_i915_private *dev_priv = dev->dev_private;
5432         uint32_t tmp;
5433
5434         tmp = I915_READ(PFIT_CONTROL);
5435         if (!(tmp & PFIT_ENABLE))
5436                 return;
5437
5438         /* Check whether the pfit is attached to our pipe. */
5439         if (INTEL_INFO(dev)->gen < 4) {
5440                 if (crtc->pipe != PIPE_B)
5441                         return;
5442         } else {
5443                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5444                         return;
5445         }
5446
5447         pipe_config->gmch_pfit.control = tmp;
5448         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5449         if (INTEL_INFO(dev)->gen < 5)
5450                 pipe_config->gmch_pfit.lvds_border_bits =
5451                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5452 }
5453
5454 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5455                                struct intel_crtc_config *pipe_config)
5456 {
5457         struct drm_device *dev = crtc->base.dev;
5458         struct drm_i915_private *dev_priv = dev->dev_private;
5459         int pipe = pipe_config->cpu_transcoder;
5460         intel_clock_t clock;
5461         u32 mdiv;
5462         int refclk = 100000;
5463
5464         mutex_lock(&dev_priv->dpio_lock);
5465         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5466         mutex_unlock(&dev_priv->dpio_lock);
5467
5468         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5469         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5470         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5471         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5472         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5473
5474         vlv_clock(refclk, &clock);
5475
5476         /* clock.dot is the fast clock */
5477         pipe_config->port_clock = clock.dot / 5;
5478 }
5479
5480 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5481                                  struct intel_crtc_config *pipe_config)
5482 {
5483         struct drm_device *dev = crtc->base.dev;
5484         struct drm_i915_private *dev_priv = dev->dev_private;
5485         uint32_t tmp;
5486
5487         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5488         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5489
5490         tmp = I915_READ(PIPECONF(crtc->pipe));
5491         if (!(tmp & PIPECONF_ENABLE))
5492                 return false;
5493
5494         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5495                 switch (tmp & PIPECONF_BPC_MASK) {
5496                 case PIPECONF_6BPC:
5497                         pipe_config->pipe_bpp = 18;
5498                         break;
5499                 case PIPECONF_8BPC:
5500                         pipe_config->pipe_bpp = 24;
5501                         break;
5502                 case PIPECONF_10BPC:
5503                         pipe_config->pipe_bpp = 30;
5504                         break;
5505                 default:
5506                         break;
5507                 }
5508         }
5509
5510         if (INTEL_INFO(dev)->gen < 4)
5511                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5512
5513         intel_get_pipe_timings(crtc, pipe_config);
5514
5515         i9xx_get_pfit_config(crtc, pipe_config);
5516
5517         if (INTEL_INFO(dev)->gen >= 4) {
5518                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5519                 pipe_config->pixel_multiplier =
5520                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5521                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5522                 pipe_config->dpll_hw_state.dpll_md = tmp;
5523         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5524                 tmp = I915_READ(DPLL(crtc->pipe));
5525                 pipe_config->pixel_multiplier =
5526                         ((tmp & SDVO_MULTIPLIER_MASK)
5527                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5528         } else {
5529                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5530                  * port and will be fixed up in the encoder->get_config
5531                  * function. */
5532                 pipe_config->pixel_multiplier = 1;
5533         }
5534         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5535         if (!IS_VALLEYVIEW(dev)) {
5536                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5537                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5538         } else {
5539                 /* Mask out read-only status bits. */
5540                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5541                                                      DPLL_PORTC_READY_MASK |
5542                                                      DPLL_PORTB_READY_MASK);
5543         }
5544
5545         if (IS_VALLEYVIEW(dev))
5546                 vlv_crtc_clock_get(crtc, pipe_config);
5547         else
5548                 i9xx_crtc_clock_get(crtc, pipe_config);
5549
5550         return true;
5551 }
5552
5553 static void ironlake_init_pch_refclk(struct drm_device *dev)
5554 {
5555         struct drm_i915_private *dev_priv = dev->dev_private;
5556         struct drm_mode_config *mode_config = &dev->mode_config;
5557         struct intel_encoder *encoder;
5558         u32 val, final;
5559         bool has_lvds = false;
5560         bool has_cpu_edp = false;
5561         bool has_panel = false;
5562         bool has_ck505 = false;
5563         bool can_ssc = false;
5564
5565         /* We need to take the global config into account */
5566         list_for_each_entry(encoder, &mode_config->encoder_list,
5567                             base.head) {
5568                 switch (encoder->type) {
5569                 case INTEL_OUTPUT_LVDS:
5570                         has_panel = true;
5571                         has_lvds = true;
5572                         break;
5573                 case INTEL_OUTPUT_EDP:
5574                         has_panel = true;
5575                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5576                                 has_cpu_edp = true;
5577                         break;
5578                 }
5579         }
5580
5581         if (HAS_PCH_IBX(dev)) {
5582                 has_ck505 = dev_priv->vbt.display_clock_mode;
5583                 can_ssc = has_ck505;
5584         } else {
5585                 has_ck505 = false;
5586                 can_ssc = true;
5587         }
5588
5589         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5590                       has_panel, has_lvds, has_ck505);
5591
5592         /* Ironlake: try to setup display ref clock before DPLL
5593          * enabling. This is only under driver's control after
5594          * PCH B stepping, previous chipset stepping should be
5595          * ignoring this setting.
5596          */
5597         val = I915_READ(PCH_DREF_CONTROL);
5598
5599         /* As we must carefully and slowly disable/enable each source in turn,
5600          * compute the final state we want first and check if we need to
5601          * make any changes at all.
5602          */
5603         final = val;
5604         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5605         if (has_ck505)
5606                 final |= DREF_NONSPREAD_CK505_ENABLE;
5607         else
5608                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5609
5610         final &= ~DREF_SSC_SOURCE_MASK;
5611         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5612         final &= ~DREF_SSC1_ENABLE;
5613
5614         if (has_panel) {
5615                 final |= DREF_SSC_SOURCE_ENABLE;
5616
5617                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5618                         final |= DREF_SSC1_ENABLE;
5619
5620                 if (has_cpu_edp) {
5621                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5622                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5623                         else
5624                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5625                 } else
5626                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5627         } else {
5628                 final |= DREF_SSC_SOURCE_DISABLE;
5629                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5630         }
5631
5632         if (final == val)
5633                 return;
5634
5635         /* Always enable nonspread source */
5636         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5637
5638         if (has_ck505)
5639                 val |= DREF_NONSPREAD_CK505_ENABLE;
5640         else
5641                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5642
5643         if (has_panel) {
5644                 val &= ~DREF_SSC_SOURCE_MASK;
5645                 val |= DREF_SSC_SOURCE_ENABLE;
5646
5647                 /* SSC must be turned on before enabling the CPU output  */
5648                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5649                         DRM_DEBUG_KMS("Using SSC on panel\n");
5650                         val |= DREF_SSC1_ENABLE;
5651                 } else
5652                         val &= ~DREF_SSC1_ENABLE;
5653
5654                 /* Get SSC going before enabling the outputs */
5655                 I915_WRITE(PCH_DREF_CONTROL, val);
5656                 POSTING_READ(PCH_DREF_CONTROL);
5657                 udelay(200);
5658
5659                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5660
5661                 /* Enable CPU source on CPU attached eDP */
5662                 if (has_cpu_edp) {
5663                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5664                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5665                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5666                         }
5667                         else
5668                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5669                 } else
5670                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5671
5672                 I915_WRITE(PCH_DREF_CONTROL, val);
5673                 POSTING_READ(PCH_DREF_CONTROL);
5674                 udelay(200);
5675         } else {
5676                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5677
5678                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5679
5680                 /* Turn off CPU output */
5681                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5682
5683                 I915_WRITE(PCH_DREF_CONTROL, val);
5684                 POSTING_READ(PCH_DREF_CONTROL);
5685                 udelay(200);
5686
5687                 /* Turn off the SSC source */
5688                 val &= ~DREF_SSC_SOURCE_MASK;
5689                 val |= DREF_SSC_SOURCE_DISABLE;
5690
5691                 /* Turn off SSC1 */
5692                 val &= ~DREF_SSC1_ENABLE;
5693
5694                 I915_WRITE(PCH_DREF_CONTROL, val);
5695                 POSTING_READ(PCH_DREF_CONTROL);
5696                 udelay(200);
5697         }
5698
5699         BUG_ON(val != final);
5700 }
5701
5702 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5703 {
5704         uint32_t tmp;
5705
5706         tmp = I915_READ(SOUTH_CHICKEN2);
5707         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5708         I915_WRITE(SOUTH_CHICKEN2, tmp);
5709
5710         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5711                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5712                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5713
5714         tmp = I915_READ(SOUTH_CHICKEN2);
5715         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5716         I915_WRITE(SOUTH_CHICKEN2, tmp);
5717
5718         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5719                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5720                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5721 }
5722
5723 /* WaMPhyProgramming:hsw */
5724 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5725 {
5726         uint32_t tmp;
5727
5728         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5729         tmp &= ~(0xFF << 24);
5730         tmp |= (0x12 << 24);
5731         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5732
5733         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5734         tmp |= (1 << 11);
5735         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5736
5737         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5738         tmp |= (1 << 11);
5739         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5740
5741         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5742         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5743         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5744
5745         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5746         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5747         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5748
5749         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5750         tmp &= ~(7 << 13);
5751         tmp |= (5 << 13);
5752         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5753
5754         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5755         tmp &= ~(7 << 13);
5756         tmp |= (5 << 13);
5757         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5758
5759         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5760         tmp &= ~0xFF;
5761         tmp |= 0x1C;
5762         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5763
5764         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5765         tmp &= ~0xFF;
5766         tmp |= 0x1C;
5767         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5768
5769         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5770         tmp &= ~(0xFF << 16);
5771         tmp |= (0x1C << 16);
5772         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5773
5774         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5775         tmp &= ~(0xFF << 16);
5776         tmp |= (0x1C << 16);
5777         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5778
5779         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5780         tmp |= (1 << 27);
5781         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5782
5783         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5784         tmp |= (1 << 27);
5785         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5786
5787         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5788         tmp &= ~(0xF << 28);
5789         tmp |= (4 << 28);
5790         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5791
5792         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5793         tmp &= ~(0xF << 28);
5794         tmp |= (4 << 28);
5795         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5796 }
5797
5798 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5799  * Programming" based on the parameters passed:
5800  * - Sequence to enable CLKOUT_DP
5801  * - Sequence to enable CLKOUT_DP without spread
5802  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5803  */
5804 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5805                                  bool with_fdi)
5806 {
5807         struct drm_i915_private *dev_priv = dev->dev_private;
5808         uint32_t reg, tmp;
5809
5810         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5811                 with_spread = true;
5812         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5813                  with_fdi, "LP PCH doesn't have FDI\n"))
5814                 with_fdi = false;
5815
5816         mutex_lock(&dev_priv->dpio_lock);
5817
5818         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5819         tmp &= ~SBI_SSCCTL_DISABLE;
5820         tmp |= SBI_SSCCTL_PATHALT;
5821         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5822
5823         udelay(24);
5824
5825         if (with_spread) {
5826                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5827                 tmp &= ~SBI_SSCCTL_PATHALT;
5828                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5829
5830                 if (with_fdi) {
5831                         lpt_reset_fdi_mphy(dev_priv);
5832                         lpt_program_fdi_mphy(dev_priv);
5833                 }
5834         }
5835
5836         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5837                SBI_GEN0 : SBI_DBUFF0;
5838         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5839         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5840         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5841
5842         mutex_unlock(&dev_priv->dpio_lock);
5843 }
5844
5845 /* Sequence to disable CLKOUT_DP */
5846 static void lpt_disable_clkout_dp(struct drm_device *dev)
5847 {
5848         struct drm_i915_private *dev_priv = dev->dev_private;
5849         uint32_t reg, tmp;
5850
5851         mutex_lock(&dev_priv->dpio_lock);
5852
5853         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5854                SBI_GEN0 : SBI_DBUFF0;
5855         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5856         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5857         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5858
5859         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5860         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5861                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5862                         tmp |= SBI_SSCCTL_PATHALT;
5863                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5864                         udelay(32);
5865                 }
5866                 tmp |= SBI_SSCCTL_DISABLE;
5867                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5868         }
5869
5870         mutex_unlock(&dev_priv->dpio_lock);
5871 }
5872
5873 static void lpt_init_pch_refclk(struct drm_device *dev)
5874 {
5875         struct drm_mode_config *mode_config = &dev->mode_config;
5876         struct intel_encoder *encoder;
5877         bool has_vga = false;
5878
5879         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5880                 switch (encoder->type) {
5881                 case INTEL_OUTPUT_ANALOG:
5882                         has_vga = true;
5883                         break;
5884                 }
5885         }
5886
5887         if (has_vga)
5888                 lpt_enable_clkout_dp(dev, true, true);
5889         else
5890                 lpt_disable_clkout_dp(dev);
5891 }
5892
5893 /*
5894  * Initialize reference clocks when the driver loads
5895  */
5896 void intel_init_pch_refclk(struct drm_device *dev)
5897 {
5898         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5899                 ironlake_init_pch_refclk(dev);
5900         else if (HAS_PCH_LPT(dev))
5901                 lpt_init_pch_refclk(dev);
5902 }
5903
5904 static int ironlake_get_refclk(struct drm_crtc *crtc)
5905 {
5906         struct drm_device *dev = crtc->dev;
5907         struct drm_i915_private *dev_priv = dev->dev_private;
5908         struct intel_encoder *encoder;
5909         int num_connectors = 0;
5910         bool is_lvds = false;
5911
5912         for_each_encoder_on_crtc(dev, crtc, encoder) {
5913                 switch (encoder->type) {
5914                 case INTEL_OUTPUT_LVDS:
5915                         is_lvds = true;
5916                         break;
5917                 }
5918                 num_connectors++;
5919         }
5920
5921         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5922                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
5923                               dev_priv->vbt.lvds_ssc_freq);
5924                 return dev_priv->vbt.lvds_ssc_freq;
5925         }
5926
5927         return 120000;
5928 }
5929
5930 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5931 {
5932         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5933         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5934         int pipe = intel_crtc->pipe;
5935         uint32_t val;
5936
5937         val = 0;
5938
5939         switch (intel_crtc->config.pipe_bpp) {
5940         case 18:
5941                 val |= PIPECONF_6BPC;
5942                 break;
5943         case 24:
5944                 val |= PIPECONF_8BPC;
5945                 break;
5946         case 30:
5947                 val |= PIPECONF_10BPC;
5948                 break;
5949         case 36:
5950                 val |= PIPECONF_12BPC;
5951                 break;
5952         default:
5953                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5954                 BUG();
5955         }
5956
5957         if (intel_crtc->config.dither)
5958                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5959
5960         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5961                 val |= PIPECONF_INTERLACED_ILK;
5962         else
5963                 val |= PIPECONF_PROGRESSIVE;
5964
5965         if (intel_crtc->config.limited_color_range)
5966                 val |= PIPECONF_COLOR_RANGE_SELECT;
5967
5968         I915_WRITE(PIPECONF(pipe), val);
5969         POSTING_READ(PIPECONF(pipe));
5970 }
5971
5972 /*
5973  * Set up the pipe CSC unit.
5974  *
5975  * Currently only full range RGB to limited range RGB conversion
5976  * is supported, but eventually this should handle various
5977  * RGB<->YCbCr scenarios as well.
5978  */
5979 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5980 {
5981         struct drm_device *dev = crtc->dev;
5982         struct drm_i915_private *dev_priv = dev->dev_private;
5983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5984         int pipe = intel_crtc->pipe;
5985         uint16_t coeff = 0x7800; /* 1.0 */
5986
5987         /*
5988          * TODO: Check what kind of values actually come out of the pipe
5989          * with these coeff/postoff values and adjust to get the best
5990          * accuracy. Perhaps we even need to take the bpc value into
5991          * consideration.
5992          */
5993
5994         if (intel_crtc->config.limited_color_range)
5995                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5996
5997         /*
5998          * GY/GU and RY/RU should be the other way around according
5999          * to BSpec, but reality doesn't agree. Just set them up in
6000          * a way that results in the correct picture.
6001          */
6002         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6003         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6004
6005         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6006         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6007
6008         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6009         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6010
6011         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6012         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6013         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6014
6015         if (INTEL_INFO(dev)->gen > 6) {
6016                 uint16_t postoff = 0;
6017
6018                 if (intel_crtc->config.limited_color_range)
6019                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
6020
6021                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6022                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6023                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6024
6025                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6026         } else {
6027                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6028
6029                 if (intel_crtc->config.limited_color_range)
6030                         mode |= CSC_BLACK_SCREEN_OFFSET;
6031
6032                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6033         }
6034 }
6035
6036 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6037 {
6038         struct drm_device *dev = crtc->dev;
6039         struct drm_i915_private *dev_priv = dev->dev_private;
6040         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6041         enum pipe pipe = intel_crtc->pipe;
6042         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6043         uint32_t val;
6044
6045         val = 0;
6046
6047         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6048                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6049
6050         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6051                 val |= PIPECONF_INTERLACED_ILK;
6052         else
6053                 val |= PIPECONF_PROGRESSIVE;
6054
6055         I915_WRITE(PIPECONF(cpu_transcoder), val);
6056         POSTING_READ(PIPECONF(cpu_transcoder));
6057
6058         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6059         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6060
6061         if (IS_BROADWELL(dev)) {
6062                 val = 0;
6063
6064                 switch (intel_crtc->config.pipe_bpp) {
6065                 case 18:
6066                         val |= PIPEMISC_DITHER_6_BPC;
6067                         break;
6068                 case 24:
6069                         val |= PIPEMISC_DITHER_8_BPC;
6070                         break;
6071                 case 30:
6072                         val |= PIPEMISC_DITHER_10_BPC;
6073                         break;
6074                 case 36:
6075                         val |= PIPEMISC_DITHER_12_BPC;
6076                         break;
6077                 default:
6078                         /* Case prevented by pipe_config_set_bpp. */
6079                         BUG();
6080                 }
6081
6082                 if (intel_crtc->config.dither)
6083                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6084
6085                 I915_WRITE(PIPEMISC(pipe), val);
6086         }
6087 }
6088
6089 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6090                                     intel_clock_t *clock,
6091                                     bool *has_reduced_clock,
6092                                     intel_clock_t *reduced_clock)
6093 {
6094         struct drm_device *dev = crtc->dev;
6095         struct drm_i915_private *dev_priv = dev->dev_private;
6096         struct intel_encoder *intel_encoder;
6097         int refclk;
6098         const intel_limit_t *limit;
6099         bool ret, is_lvds = false;
6100
6101         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6102                 switch (intel_encoder->type) {
6103                 case INTEL_OUTPUT_LVDS:
6104                         is_lvds = true;
6105                         break;
6106                 }
6107         }
6108
6109         refclk = ironlake_get_refclk(crtc);
6110
6111         /*
6112          * Returns a set of divisors for the desired target clock with the given
6113          * refclk, or FALSE.  The returned values represent the clock equation:
6114          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6115          */
6116         limit = intel_limit(crtc, refclk);
6117         ret = dev_priv->display.find_dpll(limit, crtc,
6118                                           to_intel_crtc(crtc)->config.port_clock,
6119                                           refclk, NULL, clock);
6120         if (!ret)
6121                 return false;
6122
6123         if (is_lvds && dev_priv->lvds_downclock_avail) {
6124                 /*
6125                  * Ensure we match the reduced clock's P to the target clock.
6126                  * If the clocks don't match, we can't switch the display clock
6127                  * by using the FP0/FP1. In such case we will disable the LVDS
6128                  * downclock feature.
6129                 */
6130                 *has_reduced_clock =
6131                         dev_priv->display.find_dpll(limit, crtc,
6132                                                     dev_priv->lvds_downclock,
6133                                                     refclk, clock,
6134                                                     reduced_clock);
6135         }
6136
6137         return true;
6138 }
6139
6140 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6141 {
6142         /*
6143          * Account for spread spectrum to avoid
6144          * oversubscribing the link. Max center spread
6145          * is 2.5%; use 5% for safety's sake.
6146          */
6147         u32 bps = target_clock * bpp * 21 / 20;
6148         return bps / (link_bw * 8) + 1;
6149 }
6150
6151 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6152 {
6153         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6154 }
6155
6156 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6157                                       u32 *fp,
6158                                       intel_clock_t *reduced_clock, u32 *fp2)
6159 {
6160         struct drm_crtc *crtc = &intel_crtc->base;
6161         struct drm_device *dev = crtc->dev;
6162         struct drm_i915_private *dev_priv = dev->dev_private;
6163         struct intel_encoder *intel_encoder;
6164         uint32_t dpll;
6165         int factor, num_connectors = 0;
6166         bool is_lvds = false, is_sdvo = false;
6167
6168         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6169                 switch (intel_encoder->type) {
6170                 case INTEL_OUTPUT_LVDS:
6171                         is_lvds = true;
6172                         break;
6173                 case INTEL_OUTPUT_SDVO:
6174                 case INTEL_OUTPUT_HDMI:
6175                         is_sdvo = true;
6176                         break;
6177                 }
6178
6179                 num_connectors++;
6180         }
6181
6182         /* Enable autotuning of the PLL clock (if permissible) */
6183         factor = 21;
6184         if (is_lvds) {
6185                 if ((intel_panel_use_ssc(dev_priv) &&
6186                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6187                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6188                         factor = 25;
6189         } else if (intel_crtc->config.sdvo_tv_clock)
6190                 factor = 20;
6191
6192         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6193                 *fp |= FP_CB_TUNE;
6194
6195         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6196                 *fp2 |= FP_CB_TUNE;
6197
6198         dpll = 0;
6199
6200         if (is_lvds)
6201                 dpll |= DPLLB_MODE_LVDS;
6202         else
6203                 dpll |= DPLLB_MODE_DAC_SERIAL;
6204
6205         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6206                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6207
6208         if (is_sdvo)
6209                 dpll |= DPLL_SDVO_HIGH_SPEED;
6210         if (intel_crtc->config.has_dp_encoder)
6211                 dpll |= DPLL_SDVO_HIGH_SPEED;
6212
6213         /* compute bitmask from p1 value */
6214         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6215         /* also FPA1 */
6216         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6217
6218         switch (intel_crtc->config.dpll.p2) {
6219         case 5:
6220                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6221                 break;
6222         case 7:
6223                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6224                 break;
6225         case 10:
6226                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6227                 break;
6228         case 14:
6229                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6230                 break;
6231         }
6232
6233         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6234                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6235         else
6236                 dpll |= PLL_REF_INPUT_DREFCLK;
6237
6238         return dpll | DPLL_VCO_ENABLE;
6239 }
6240
6241 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6242                                   int x, int y,
6243                                   struct drm_framebuffer *fb)
6244 {
6245         struct drm_device *dev = crtc->dev;
6246         struct drm_i915_private *dev_priv = dev->dev_private;
6247         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6248         int pipe = intel_crtc->pipe;
6249         int plane = intel_crtc->plane;
6250         int num_connectors = 0;
6251         intel_clock_t clock, reduced_clock;
6252         u32 dpll = 0, fp = 0, fp2 = 0;
6253         bool ok, has_reduced_clock = false;
6254         bool is_lvds = false;
6255         struct intel_encoder *encoder;
6256         struct intel_shared_dpll *pll;
6257         int ret;
6258
6259         for_each_encoder_on_crtc(dev, crtc, encoder) {
6260                 switch (encoder->type) {
6261                 case INTEL_OUTPUT_LVDS:
6262                         is_lvds = true;
6263                         break;
6264                 }
6265
6266                 num_connectors++;
6267         }
6268
6269         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6270              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6271
6272         ok = ironlake_compute_clocks(crtc, &clock,
6273                                      &has_reduced_clock, &reduced_clock);
6274         if (!ok && !intel_crtc->config.clock_set) {
6275                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6276                 return -EINVAL;
6277         }
6278         /* Compat-code for transition, will disappear. */
6279         if (!intel_crtc->config.clock_set) {
6280                 intel_crtc->config.dpll.n = clock.n;
6281                 intel_crtc->config.dpll.m1 = clock.m1;
6282                 intel_crtc->config.dpll.m2 = clock.m2;
6283                 intel_crtc->config.dpll.p1 = clock.p1;
6284                 intel_crtc->config.dpll.p2 = clock.p2;
6285         }
6286
6287         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6288         if (intel_crtc->config.has_pch_encoder) {
6289                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6290                 if (has_reduced_clock)
6291                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6292
6293                 dpll = ironlake_compute_dpll(intel_crtc,
6294                                              &fp, &reduced_clock,
6295                                              has_reduced_clock ? &fp2 : NULL);
6296
6297                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6298                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6299                 if (has_reduced_clock)
6300                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6301                 else
6302                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6303
6304                 pll = intel_get_shared_dpll(intel_crtc);
6305                 if (pll == NULL) {
6306                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6307                                          pipe_name(pipe));
6308                         return -EINVAL;
6309                 }
6310         } else
6311                 intel_put_shared_dpll(intel_crtc);
6312
6313         if (intel_crtc->config.has_dp_encoder)
6314                 intel_dp_set_m_n(intel_crtc);
6315
6316         if (is_lvds && has_reduced_clock && i915_powersave)
6317                 intel_crtc->lowfreq_avail = true;
6318         else
6319                 intel_crtc->lowfreq_avail = false;
6320
6321         intel_set_pipe_timings(intel_crtc);
6322
6323         if (intel_crtc->config.has_pch_encoder) {
6324                 intel_cpu_transcoder_set_m_n(intel_crtc,
6325                                              &intel_crtc->config.fdi_m_n);
6326         }
6327
6328         ironlake_set_pipeconf(crtc);
6329
6330         /* Set up the display plane register */
6331         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6332         POSTING_READ(DSPCNTR(plane));
6333
6334         ret = intel_pipe_set_base(crtc, x, y, fb);
6335
6336         return ret;
6337 }
6338
6339 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6340                                          struct intel_link_m_n *m_n)
6341 {
6342         struct drm_device *dev = crtc->base.dev;
6343         struct drm_i915_private *dev_priv = dev->dev_private;
6344         enum pipe pipe = crtc->pipe;
6345
6346         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6347         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6348         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6349                 & ~TU_SIZE_MASK;
6350         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6351         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6352                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6353 }
6354
6355 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6356                                          enum transcoder transcoder,
6357                                          struct intel_link_m_n *m_n)
6358 {
6359         struct drm_device *dev = crtc->base.dev;
6360         struct drm_i915_private *dev_priv = dev->dev_private;
6361         enum pipe pipe = crtc->pipe;
6362
6363         if (INTEL_INFO(dev)->gen >= 5) {
6364                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6365                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6366                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6367                         & ~TU_SIZE_MASK;
6368                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6369                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6370                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6371         } else {
6372                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6373                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6374                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6375                         & ~TU_SIZE_MASK;
6376                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6377                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6378                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6379         }
6380 }
6381
6382 void intel_dp_get_m_n(struct intel_crtc *crtc,
6383                       struct intel_crtc_config *pipe_config)
6384 {
6385         if (crtc->config.has_pch_encoder)
6386                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6387         else
6388                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6389                                              &pipe_config->dp_m_n);
6390 }
6391
6392 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6393                                         struct intel_crtc_config *pipe_config)
6394 {
6395         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6396                                      &pipe_config->fdi_m_n);
6397 }
6398
6399 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6400                                      struct intel_crtc_config *pipe_config)
6401 {
6402         struct drm_device *dev = crtc->base.dev;
6403         struct drm_i915_private *dev_priv = dev->dev_private;
6404         uint32_t tmp;
6405
6406         tmp = I915_READ(PF_CTL(crtc->pipe));
6407
6408         if (tmp & PF_ENABLE) {
6409                 pipe_config->pch_pfit.enabled = true;
6410                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6411                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6412
6413                 /* We currently do not free assignements of panel fitters on
6414                  * ivb/hsw (since we don't use the higher upscaling modes which
6415                  * differentiates them) so just WARN about this case for now. */
6416                 if (IS_GEN7(dev)) {
6417                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6418                                 PF_PIPE_SEL_IVB(crtc->pipe));
6419                 }
6420         }
6421 }
6422
6423 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6424                                      struct intel_crtc_config *pipe_config)
6425 {
6426         struct drm_device *dev = crtc->base.dev;
6427         struct drm_i915_private *dev_priv = dev->dev_private;
6428         uint32_t tmp;
6429
6430         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6431         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6432
6433         tmp = I915_READ(PIPECONF(crtc->pipe));
6434         if (!(tmp & PIPECONF_ENABLE))
6435                 return false;
6436
6437         switch (tmp & PIPECONF_BPC_MASK) {
6438         case PIPECONF_6BPC:
6439                 pipe_config->pipe_bpp = 18;
6440                 break;
6441         case PIPECONF_8BPC:
6442                 pipe_config->pipe_bpp = 24;
6443                 break;
6444         case PIPECONF_10BPC:
6445                 pipe_config->pipe_bpp = 30;
6446                 break;
6447         case PIPECONF_12BPC:
6448                 pipe_config->pipe_bpp = 36;
6449                 break;
6450         default:
6451                 break;
6452         }
6453
6454         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6455                 struct intel_shared_dpll *pll;
6456
6457                 pipe_config->has_pch_encoder = true;
6458
6459                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6460                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6461                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6462
6463                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6464
6465                 if (HAS_PCH_IBX(dev_priv->dev)) {
6466                         pipe_config->shared_dpll =
6467                                 (enum intel_dpll_id) crtc->pipe;
6468                 } else {
6469                         tmp = I915_READ(PCH_DPLL_SEL);
6470                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6471                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6472                         else
6473                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6474                 }
6475
6476                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6477
6478                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6479                                            &pipe_config->dpll_hw_state));
6480
6481                 tmp = pipe_config->dpll_hw_state.dpll;
6482                 pipe_config->pixel_multiplier =
6483                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6484                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6485
6486                 ironlake_pch_clock_get(crtc, pipe_config);
6487         } else {
6488                 pipe_config->pixel_multiplier = 1;
6489         }
6490
6491         intel_get_pipe_timings(crtc, pipe_config);
6492
6493         ironlake_get_pfit_config(crtc, pipe_config);
6494
6495         return true;
6496 }
6497
6498 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6499 {
6500         struct drm_device *dev = dev_priv->dev;
6501         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6502         struct intel_crtc *crtc;
6503         unsigned long irqflags;
6504         uint32_t val;
6505
6506         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6507                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6508                      pipe_name(crtc->pipe));
6509
6510         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6511         WARN(plls->spll_refcount, "SPLL enabled\n");
6512         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6513         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6514         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6515         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6516              "CPU PWM1 enabled\n");
6517         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6518              "CPU PWM2 enabled\n");
6519         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6520              "PCH PWM1 enabled\n");
6521         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6522              "Utility pin enabled\n");
6523         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6524
6525         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6526         val = I915_READ(DEIMR);
6527         WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
6528              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6529         val = I915_READ(SDEIMR);
6530         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6531              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6532         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6533 }
6534
6535 /*
6536  * This function implements pieces of two sequences from BSpec:
6537  * - Sequence for display software to disable LCPLL
6538  * - Sequence for display software to allow package C8+
6539  * The steps implemented here are just the steps that actually touch the LCPLL
6540  * register. Callers should take care of disabling all the display engine
6541  * functions, doing the mode unset, fixing interrupts, etc.
6542  */
6543 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6544                               bool switch_to_fclk, bool allow_power_down)
6545 {
6546         uint32_t val;
6547
6548         assert_can_disable_lcpll(dev_priv);
6549
6550         val = I915_READ(LCPLL_CTL);
6551
6552         if (switch_to_fclk) {
6553                 val |= LCPLL_CD_SOURCE_FCLK;
6554                 I915_WRITE(LCPLL_CTL, val);
6555
6556                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6557                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6558                         DRM_ERROR("Switching to FCLK failed\n");
6559
6560                 val = I915_READ(LCPLL_CTL);
6561         }
6562
6563         val |= LCPLL_PLL_DISABLE;
6564         I915_WRITE(LCPLL_CTL, val);
6565         POSTING_READ(LCPLL_CTL);
6566
6567         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6568                 DRM_ERROR("LCPLL still locked\n");
6569
6570         val = I915_READ(D_COMP);
6571         val |= D_COMP_COMP_DISABLE;
6572         mutex_lock(&dev_priv->rps.hw_lock);
6573         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6574                 DRM_ERROR("Failed to disable D_COMP\n");
6575         mutex_unlock(&dev_priv->rps.hw_lock);
6576         POSTING_READ(D_COMP);
6577         ndelay(100);
6578
6579         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6580                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6581
6582         if (allow_power_down) {
6583                 val = I915_READ(LCPLL_CTL);
6584                 val |= LCPLL_POWER_DOWN_ALLOW;
6585                 I915_WRITE(LCPLL_CTL, val);
6586                 POSTING_READ(LCPLL_CTL);
6587         }
6588 }
6589
6590 /*
6591  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6592  * source.
6593  */
6594 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6595 {
6596         uint32_t val;
6597
6598         val = I915_READ(LCPLL_CTL);
6599
6600         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6601                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6602                 return;
6603
6604         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6605          * we'll hang the machine! */
6606         dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
6607
6608         if (val & LCPLL_POWER_DOWN_ALLOW) {
6609                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6610                 I915_WRITE(LCPLL_CTL, val);
6611                 POSTING_READ(LCPLL_CTL);
6612         }
6613
6614         val = I915_READ(D_COMP);
6615         val |= D_COMP_COMP_FORCE;
6616         val &= ~D_COMP_COMP_DISABLE;
6617         mutex_lock(&dev_priv->rps.hw_lock);
6618         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6619                 DRM_ERROR("Failed to enable D_COMP\n");
6620         mutex_unlock(&dev_priv->rps.hw_lock);
6621         POSTING_READ(D_COMP);
6622
6623         val = I915_READ(LCPLL_CTL);
6624         val &= ~LCPLL_PLL_DISABLE;
6625         I915_WRITE(LCPLL_CTL, val);
6626
6627         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6628                 DRM_ERROR("LCPLL not locked yet\n");
6629
6630         if (val & LCPLL_CD_SOURCE_FCLK) {
6631                 val = I915_READ(LCPLL_CTL);
6632                 val &= ~LCPLL_CD_SOURCE_FCLK;
6633                 I915_WRITE(LCPLL_CTL, val);
6634
6635                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6636                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6637                         DRM_ERROR("Switching back to LCPLL failed\n");
6638         }
6639
6640         dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
6641 }
6642
6643 void hsw_enable_pc8_work(struct work_struct *__work)
6644 {
6645         struct drm_i915_private *dev_priv =
6646                 container_of(to_delayed_work(__work), struct drm_i915_private,
6647                              pc8.enable_work);
6648         struct drm_device *dev = dev_priv->dev;
6649         uint32_t val;
6650
6651         WARN_ON(!HAS_PC8(dev));
6652
6653         if (dev_priv->pc8.enabled)
6654                 return;
6655
6656         DRM_DEBUG_KMS("Enabling package C8+\n");
6657
6658         dev_priv->pc8.enabled = true;
6659
6660         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6661                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6662                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6663                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6664         }
6665
6666         lpt_disable_clkout_dp(dev);
6667         hsw_pc8_disable_interrupts(dev);
6668         hsw_disable_lcpll(dev_priv, true, true);
6669
6670         intel_runtime_pm_put(dev_priv);
6671 }
6672
6673 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6674 {
6675         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6676         WARN(dev_priv->pc8.disable_count < 1,
6677              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6678
6679         dev_priv->pc8.disable_count--;
6680         if (dev_priv->pc8.disable_count != 0)
6681                 return;
6682
6683         schedule_delayed_work(&dev_priv->pc8.enable_work,
6684                               msecs_to_jiffies(i915_pc8_timeout));
6685 }
6686
6687 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6688 {
6689         struct drm_device *dev = dev_priv->dev;
6690         uint32_t val;
6691
6692         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6693         WARN(dev_priv->pc8.disable_count < 0,
6694              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6695
6696         dev_priv->pc8.disable_count++;
6697         if (dev_priv->pc8.disable_count != 1)
6698                 return;
6699
6700         WARN_ON(!HAS_PC8(dev));
6701
6702         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6703         if (!dev_priv->pc8.enabled)
6704                 return;
6705
6706         DRM_DEBUG_KMS("Disabling package C8+\n");
6707
6708         intel_runtime_pm_get(dev_priv);
6709
6710         hsw_restore_lcpll(dev_priv);
6711         hsw_pc8_restore_interrupts(dev);
6712         lpt_init_pch_refclk(dev);
6713
6714         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6715                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6716                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6717                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6718         }
6719
6720         intel_prepare_ddi(dev);
6721         i915_gem_init_swizzling(dev);
6722         mutex_lock(&dev_priv->rps.hw_lock);
6723         gen6_update_ring_freq(dev);
6724         mutex_unlock(&dev_priv->rps.hw_lock);
6725         dev_priv->pc8.enabled = false;
6726 }
6727
6728 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6729 {
6730         if (!HAS_PC8(dev_priv->dev))
6731                 return;
6732
6733         mutex_lock(&dev_priv->pc8.lock);
6734         __hsw_enable_package_c8(dev_priv);
6735         mutex_unlock(&dev_priv->pc8.lock);
6736 }
6737
6738 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6739 {
6740         if (!HAS_PC8(dev_priv->dev))
6741                 return;
6742
6743         mutex_lock(&dev_priv->pc8.lock);
6744         __hsw_disable_package_c8(dev_priv);
6745         mutex_unlock(&dev_priv->pc8.lock);
6746 }
6747
6748 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6749 {
6750         struct drm_device *dev = dev_priv->dev;
6751         struct intel_crtc *crtc;
6752         uint32_t val;
6753
6754         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6755                 if (crtc->base.enabled)
6756                         return false;
6757
6758         /* This case is still possible since we have the i915.disable_power_well
6759          * parameter and also the KVMr or something else might be requesting the
6760          * power well. */
6761         val = I915_READ(HSW_PWR_WELL_DRIVER);
6762         if (val != 0) {
6763                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6764                 return false;
6765         }
6766
6767         return true;
6768 }
6769
6770 /* Since we're called from modeset_global_resources there's no way to
6771  * symmetrically increase and decrease the refcount, so we use
6772  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6773  * or not.
6774  */
6775 static void hsw_update_package_c8(struct drm_device *dev)
6776 {
6777         struct drm_i915_private *dev_priv = dev->dev_private;
6778         bool allow;
6779
6780         if (!HAS_PC8(dev_priv->dev))
6781                 return;
6782
6783         if (!i915_enable_pc8)
6784                 return;
6785
6786         mutex_lock(&dev_priv->pc8.lock);
6787
6788         allow = hsw_can_enable_package_c8(dev_priv);
6789
6790         if (allow == dev_priv->pc8.requirements_met)
6791                 goto done;
6792
6793         dev_priv->pc8.requirements_met = allow;
6794
6795         if (allow)
6796                 __hsw_enable_package_c8(dev_priv);
6797         else
6798                 __hsw_disable_package_c8(dev_priv);
6799
6800 done:
6801         mutex_unlock(&dev_priv->pc8.lock);
6802 }
6803
6804 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6805 {
6806         if (!HAS_PC8(dev_priv->dev))
6807                 return;
6808
6809         mutex_lock(&dev_priv->pc8.lock);
6810         if (!dev_priv->pc8.gpu_idle) {
6811                 dev_priv->pc8.gpu_idle = true;
6812                 __hsw_enable_package_c8(dev_priv);
6813         }
6814         mutex_unlock(&dev_priv->pc8.lock);
6815 }
6816
6817 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6818 {
6819         if (!HAS_PC8(dev_priv->dev))
6820                 return;
6821
6822         mutex_lock(&dev_priv->pc8.lock);
6823         if (dev_priv->pc8.gpu_idle) {
6824                 dev_priv->pc8.gpu_idle = false;
6825                 __hsw_disable_package_c8(dev_priv);
6826         }
6827         mutex_unlock(&dev_priv->pc8.lock);
6828 }
6829
6830 #define for_each_power_domain(domain, mask)                             \
6831         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
6832                 if ((1 << (domain)) & (mask))
6833
6834 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6835                                             enum pipe pipe, bool pfit_enabled)
6836 {
6837         unsigned long mask;
6838         enum transcoder transcoder;
6839
6840         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6841
6842         mask = BIT(POWER_DOMAIN_PIPE(pipe));
6843         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6844         if (pfit_enabled)
6845                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6846
6847         return mask;
6848 }
6849
6850 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6851 {
6852         struct drm_i915_private *dev_priv = dev->dev_private;
6853
6854         if (dev_priv->power_domains.init_power_on == enable)
6855                 return;
6856
6857         if (enable)
6858                 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6859         else
6860                 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6861
6862         dev_priv->power_domains.init_power_on = enable;
6863 }
6864
6865 static void modeset_update_power_wells(struct drm_device *dev)
6866 {
6867         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6868         struct intel_crtc *crtc;
6869
6870         /*
6871          * First get all needed power domains, then put all unneeded, to avoid
6872          * any unnecessary toggling of the power wells.
6873          */
6874         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6875                 enum intel_display_power_domain domain;
6876
6877                 if (!crtc->base.enabled)
6878                         continue;
6879
6880                 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6881                                                 crtc->pipe,
6882                                                 crtc->config.pch_pfit.enabled);
6883
6884                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6885                         intel_display_power_get(dev, domain);
6886         }
6887
6888         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6889                 enum intel_display_power_domain domain;
6890
6891                 for_each_power_domain(domain, crtc->enabled_power_domains)
6892                         intel_display_power_put(dev, domain);
6893
6894                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6895         }
6896
6897         intel_display_set_init_power(dev, false);
6898 }
6899
6900 static void haswell_modeset_global_resources(struct drm_device *dev)
6901 {
6902         modeset_update_power_wells(dev);
6903         hsw_update_package_c8(dev);
6904 }
6905
6906 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6907                                  int x, int y,
6908                                  struct drm_framebuffer *fb)
6909 {
6910         struct drm_device *dev = crtc->dev;
6911         struct drm_i915_private *dev_priv = dev->dev_private;
6912         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6913         int plane = intel_crtc->plane;
6914         int ret;
6915
6916         if (!intel_ddi_pll_select(intel_crtc))
6917                 return -EINVAL;
6918         intel_ddi_pll_enable(intel_crtc);
6919
6920         if (intel_crtc->config.has_dp_encoder)
6921                 intel_dp_set_m_n(intel_crtc);
6922
6923         intel_crtc->lowfreq_avail = false;
6924
6925         intel_set_pipe_timings(intel_crtc);
6926
6927         if (intel_crtc->config.has_pch_encoder) {
6928                 intel_cpu_transcoder_set_m_n(intel_crtc,
6929                                              &intel_crtc->config.fdi_m_n);
6930         }
6931
6932         haswell_set_pipeconf(crtc);
6933
6934         intel_set_pipe_csc(crtc);
6935
6936         /* Set up the display plane register */
6937         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6938         POSTING_READ(DSPCNTR(plane));
6939
6940         ret = intel_pipe_set_base(crtc, x, y, fb);
6941
6942         return ret;
6943 }
6944
6945 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6946                                     struct intel_crtc_config *pipe_config)
6947 {
6948         struct drm_device *dev = crtc->base.dev;
6949         struct drm_i915_private *dev_priv = dev->dev_private;
6950         enum intel_display_power_domain pfit_domain;
6951         uint32_t tmp;
6952
6953         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6954         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6955
6956         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6957         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6958                 enum pipe trans_edp_pipe;
6959                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6960                 default:
6961                         WARN(1, "unknown pipe linked to edp transcoder\n");
6962                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6963                 case TRANS_DDI_EDP_INPUT_A_ON:
6964                         trans_edp_pipe = PIPE_A;
6965                         break;
6966                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6967                         trans_edp_pipe = PIPE_B;
6968                         break;
6969                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6970                         trans_edp_pipe = PIPE_C;
6971                         break;
6972                 }
6973
6974                 if (trans_edp_pipe == crtc->pipe)
6975                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6976         }
6977
6978         if (!intel_display_power_enabled(dev,
6979                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6980                 return false;
6981
6982         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6983         if (!(tmp & PIPECONF_ENABLE))
6984                 return false;
6985
6986         /*
6987          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6988          * DDI E. So just check whether this pipe is wired to DDI E and whether
6989          * the PCH transcoder is on.
6990          */
6991         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6992         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6993             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6994                 pipe_config->has_pch_encoder = true;
6995
6996                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6997                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6998                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6999
7000                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7001         }
7002
7003         intel_get_pipe_timings(crtc, pipe_config);
7004
7005         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7006         if (intel_display_power_enabled(dev, pfit_domain))
7007                 ironlake_get_pfit_config(crtc, pipe_config);
7008
7009         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7010                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
7011
7012         pipe_config->pixel_multiplier = 1;
7013
7014         return true;
7015 }
7016
7017 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7018                                int x, int y,
7019                                struct drm_framebuffer *fb)
7020 {
7021         struct drm_device *dev = crtc->dev;
7022         struct drm_i915_private *dev_priv = dev->dev_private;
7023         struct intel_encoder *encoder;
7024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7025         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7026         int pipe = intel_crtc->pipe;
7027         int ret;
7028
7029         drm_vblank_pre_modeset(dev, pipe);
7030
7031         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7032
7033         drm_vblank_post_modeset(dev, pipe);
7034
7035         if (ret != 0)
7036                 return ret;
7037
7038         for_each_encoder_on_crtc(dev, crtc, encoder) {
7039                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7040                         encoder->base.base.id,
7041                         drm_get_encoder_name(&encoder->base),
7042                         mode->base.id, mode->name);
7043                 encoder->mode_set(encoder);
7044         }
7045
7046         return 0;
7047 }
7048
7049 static struct {
7050         int clock;
7051         u32 config;
7052 } hdmi_audio_clock[] = {
7053         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7054         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7055         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7056         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7057         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7058         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7059         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7060         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7061         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7062         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7063 };
7064
7065 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7066 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7067 {
7068         int i;
7069
7070         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7071                 if (mode->clock == hdmi_audio_clock[i].clock)
7072                         break;
7073         }
7074
7075         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7076                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7077                 i = 1;
7078         }
7079
7080         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7081                       hdmi_audio_clock[i].clock,
7082                       hdmi_audio_clock[i].config);
7083
7084         return hdmi_audio_clock[i].config;
7085 }
7086
7087 static bool intel_eld_uptodate(struct drm_connector *connector,
7088                                int reg_eldv, uint32_t bits_eldv,
7089                                int reg_elda, uint32_t bits_elda,
7090                                int reg_edid)
7091 {
7092         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7093         uint8_t *eld = connector->eld;
7094         uint32_t i;
7095
7096         i = I915_READ(reg_eldv);
7097         i &= bits_eldv;
7098
7099         if (!eld[0])
7100                 return !i;
7101
7102         if (!i)
7103                 return false;
7104
7105         i = I915_READ(reg_elda);
7106         i &= ~bits_elda;
7107         I915_WRITE(reg_elda, i);
7108
7109         for (i = 0; i < eld[2]; i++)
7110                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7111                         return false;
7112
7113         return true;
7114 }
7115
7116 static void g4x_write_eld(struct drm_connector *connector,
7117                           struct drm_crtc *crtc,
7118                           struct drm_display_mode *mode)
7119 {
7120         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7121         uint8_t *eld = connector->eld;
7122         uint32_t eldv;
7123         uint32_t len;
7124         uint32_t i;
7125
7126         i = I915_READ(G4X_AUD_VID_DID);
7127
7128         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7129                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7130         else
7131                 eldv = G4X_ELDV_DEVCTG;
7132
7133         if (intel_eld_uptodate(connector,
7134                                G4X_AUD_CNTL_ST, eldv,
7135                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7136                                G4X_HDMIW_HDMIEDID))
7137                 return;
7138
7139         i = I915_READ(G4X_AUD_CNTL_ST);
7140         i &= ~(eldv | G4X_ELD_ADDR);
7141         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7142         I915_WRITE(G4X_AUD_CNTL_ST, i);
7143
7144         if (!eld[0])
7145                 return;
7146
7147         len = min_t(uint8_t, eld[2], len);
7148         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7149         for (i = 0; i < len; i++)
7150                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7151
7152         i = I915_READ(G4X_AUD_CNTL_ST);
7153         i |= eldv;
7154         I915_WRITE(G4X_AUD_CNTL_ST, i);
7155 }
7156
7157 static void haswell_write_eld(struct drm_connector *connector,
7158                               struct drm_crtc *crtc,
7159                               struct drm_display_mode *mode)
7160 {
7161         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7162         uint8_t *eld = connector->eld;
7163         struct drm_device *dev = crtc->dev;
7164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7165         uint32_t eldv;
7166         uint32_t i;
7167         int len;
7168         int pipe = to_intel_crtc(crtc)->pipe;
7169         int tmp;
7170
7171         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7172         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7173         int aud_config = HSW_AUD_CFG(pipe);
7174         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7175
7176
7177         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7178
7179         /* Audio output enable */
7180         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7181         tmp = I915_READ(aud_cntrl_st2);
7182         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7183         I915_WRITE(aud_cntrl_st2, tmp);
7184
7185         /* Wait for 1 vertical blank */
7186         intel_wait_for_vblank(dev, pipe);
7187
7188         /* Set ELD valid state */
7189         tmp = I915_READ(aud_cntrl_st2);
7190         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7191         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7192         I915_WRITE(aud_cntrl_st2, tmp);
7193         tmp = I915_READ(aud_cntrl_st2);
7194         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7195
7196         /* Enable HDMI mode */
7197         tmp = I915_READ(aud_config);
7198         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7199         /* clear N_programing_enable and N_value_index */
7200         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7201         I915_WRITE(aud_config, tmp);
7202
7203         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7204
7205         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7206         intel_crtc->eld_vld = true;
7207
7208         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7209                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7210                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7211                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7212         } else {
7213                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7214         }
7215
7216         if (intel_eld_uptodate(connector,
7217                                aud_cntrl_st2, eldv,
7218                                aud_cntl_st, IBX_ELD_ADDRESS,
7219                                hdmiw_hdmiedid))
7220                 return;
7221
7222         i = I915_READ(aud_cntrl_st2);
7223         i &= ~eldv;
7224         I915_WRITE(aud_cntrl_st2, i);
7225
7226         if (!eld[0])
7227                 return;
7228
7229         i = I915_READ(aud_cntl_st);
7230         i &= ~IBX_ELD_ADDRESS;
7231         I915_WRITE(aud_cntl_st, i);
7232         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7233         DRM_DEBUG_DRIVER("port num:%d\n", i);
7234
7235         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7236         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7237         for (i = 0; i < len; i++)
7238                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7239
7240         i = I915_READ(aud_cntrl_st2);
7241         i |= eldv;
7242         I915_WRITE(aud_cntrl_st2, i);
7243
7244 }
7245
7246 static void ironlake_write_eld(struct drm_connector *connector,
7247                                struct drm_crtc *crtc,
7248                                struct drm_display_mode *mode)
7249 {
7250         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7251         uint8_t *eld = connector->eld;
7252         uint32_t eldv;
7253         uint32_t i;
7254         int len;
7255         int hdmiw_hdmiedid;
7256         int aud_config;
7257         int aud_cntl_st;
7258         int aud_cntrl_st2;
7259         int pipe = to_intel_crtc(crtc)->pipe;
7260
7261         if (HAS_PCH_IBX(connector->dev)) {
7262                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7263                 aud_config = IBX_AUD_CFG(pipe);
7264                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7265                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7266         } else if (IS_VALLEYVIEW(connector->dev)) {
7267                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7268                 aud_config = VLV_AUD_CFG(pipe);
7269                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7270                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7271         } else {
7272                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7273                 aud_config = CPT_AUD_CFG(pipe);
7274                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7275                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7276         }
7277
7278         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7279
7280         if (IS_VALLEYVIEW(connector->dev))  {
7281                 struct intel_encoder *intel_encoder;
7282                 struct intel_digital_port *intel_dig_port;
7283
7284                 intel_encoder = intel_attached_encoder(connector);
7285                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7286                 i = intel_dig_port->port;
7287         } else {
7288                 i = I915_READ(aud_cntl_st);
7289                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7290                 /* DIP_Port_Select, 0x1 = PortB */
7291         }
7292
7293         if (!i) {
7294                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7295                 /* operate blindly on all ports */
7296                 eldv = IBX_ELD_VALIDB;
7297                 eldv |= IBX_ELD_VALIDB << 4;
7298                 eldv |= IBX_ELD_VALIDB << 8;
7299         } else {
7300                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7301                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7302         }
7303
7304         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7305                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7306                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7307                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7308         } else {
7309                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7310         }
7311
7312         if (intel_eld_uptodate(connector,
7313                                aud_cntrl_st2, eldv,
7314                                aud_cntl_st, IBX_ELD_ADDRESS,
7315                                hdmiw_hdmiedid))
7316                 return;
7317
7318         i = I915_READ(aud_cntrl_st2);
7319         i &= ~eldv;
7320         I915_WRITE(aud_cntrl_st2, i);
7321
7322         if (!eld[0])
7323                 return;
7324
7325         i = I915_READ(aud_cntl_st);
7326         i &= ~IBX_ELD_ADDRESS;
7327         I915_WRITE(aud_cntl_st, i);
7328
7329         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7330         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7331         for (i = 0; i < len; i++)
7332                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7333
7334         i = I915_READ(aud_cntrl_st2);
7335         i |= eldv;
7336         I915_WRITE(aud_cntrl_st2, i);
7337 }
7338
7339 void intel_write_eld(struct drm_encoder *encoder,
7340                      struct drm_display_mode *mode)
7341 {
7342         struct drm_crtc *crtc = encoder->crtc;
7343         struct drm_connector *connector;
7344         struct drm_device *dev = encoder->dev;
7345         struct drm_i915_private *dev_priv = dev->dev_private;
7346
7347         connector = drm_select_eld(encoder, mode);
7348         if (!connector)
7349                 return;
7350
7351         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7352                          connector->base.id,
7353                          drm_get_connector_name(connector),
7354                          connector->encoder->base.id,
7355                          drm_get_encoder_name(connector->encoder));
7356
7357         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7358
7359         if (dev_priv->display.write_eld)
7360                 dev_priv->display.write_eld(connector, crtc, mode);
7361 }
7362
7363 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7364 {
7365         struct drm_device *dev = crtc->dev;
7366         struct drm_i915_private *dev_priv = dev->dev_private;
7367         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7368         bool visible = base != 0;
7369         u32 cntl;
7370
7371         if (intel_crtc->cursor_visible == visible)
7372                 return;
7373
7374         cntl = I915_READ(_CURACNTR);
7375         if (visible) {
7376                 /* On these chipsets we can only modify the base whilst
7377                  * the cursor is disabled.
7378                  */
7379                 I915_WRITE(_CURABASE, base);
7380
7381                 cntl &= ~(CURSOR_FORMAT_MASK);
7382                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7383                 cntl |= CURSOR_ENABLE |
7384                         CURSOR_GAMMA_ENABLE |
7385                         CURSOR_FORMAT_ARGB;
7386         } else
7387                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7388         I915_WRITE(_CURACNTR, cntl);
7389
7390         intel_crtc->cursor_visible = visible;
7391 }
7392
7393 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7394 {
7395         struct drm_device *dev = crtc->dev;
7396         struct drm_i915_private *dev_priv = dev->dev_private;
7397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7398         int pipe = intel_crtc->pipe;
7399         bool visible = base != 0;
7400
7401         if (intel_crtc->cursor_visible != visible) {
7402                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7403                 if (base) {
7404                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7405                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7406                         cntl |= pipe << 28; /* Connect to correct pipe */
7407                 } else {
7408                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7409                         cntl |= CURSOR_MODE_DISABLE;
7410                 }
7411                 I915_WRITE(CURCNTR(pipe), cntl);
7412
7413                 intel_crtc->cursor_visible = visible;
7414         }
7415         /* and commit changes on next vblank */
7416         POSTING_READ(CURCNTR(pipe));
7417         I915_WRITE(CURBASE(pipe), base);
7418         POSTING_READ(CURBASE(pipe));
7419 }
7420
7421 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7422 {
7423         struct drm_device *dev = crtc->dev;
7424         struct drm_i915_private *dev_priv = dev->dev_private;
7425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7426         int pipe = intel_crtc->pipe;
7427         bool visible = base != 0;
7428
7429         if (intel_crtc->cursor_visible != visible) {
7430                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7431                 if (base) {
7432                         cntl &= ~CURSOR_MODE;
7433                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7434                 } else {
7435                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7436                         cntl |= CURSOR_MODE_DISABLE;
7437                 }
7438                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7439                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7440                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7441                 }
7442                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7443
7444                 intel_crtc->cursor_visible = visible;
7445         }
7446         /* and commit changes on next vblank */
7447         POSTING_READ(CURCNTR_IVB(pipe));
7448         I915_WRITE(CURBASE_IVB(pipe), base);
7449         POSTING_READ(CURBASE_IVB(pipe));
7450 }
7451
7452 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7453 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7454                                      bool on)
7455 {
7456         struct drm_device *dev = crtc->dev;
7457         struct drm_i915_private *dev_priv = dev->dev_private;
7458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7459         int pipe = intel_crtc->pipe;
7460         int x = intel_crtc->cursor_x;
7461         int y = intel_crtc->cursor_y;
7462         u32 base = 0, pos = 0;
7463         bool visible;
7464
7465         if (on)
7466                 base = intel_crtc->cursor_addr;
7467
7468         if (x >= intel_crtc->config.pipe_src_w)
7469                 base = 0;
7470
7471         if (y >= intel_crtc->config.pipe_src_h)
7472                 base = 0;
7473
7474         if (x < 0) {
7475                 if (x + intel_crtc->cursor_width <= 0)
7476                         base = 0;
7477
7478                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7479                 x = -x;
7480         }
7481         pos |= x << CURSOR_X_SHIFT;
7482
7483         if (y < 0) {
7484                 if (y + intel_crtc->cursor_height <= 0)
7485                         base = 0;
7486
7487                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7488                 y = -y;
7489         }
7490         pos |= y << CURSOR_Y_SHIFT;
7491
7492         visible = base != 0;
7493         if (!visible && !intel_crtc->cursor_visible)
7494                 return;
7495
7496         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7497                 I915_WRITE(CURPOS_IVB(pipe), pos);
7498                 ivb_update_cursor(crtc, base);
7499         } else {
7500                 I915_WRITE(CURPOS(pipe), pos);
7501                 if (IS_845G(dev) || IS_I865G(dev))
7502                         i845_update_cursor(crtc, base);
7503                 else
7504                         i9xx_update_cursor(crtc, base);
7505         }
7506 }
7507
7508 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7509                                  struct drm_file *file,
7510                                  uint32_t handle,
7511                                  uint32_t width, uint32_t height)
7512 {
7513         struct drm_device *dev = crtc->dev;
7514         struct drm_i915_private *dev_priv = dev->dev_private;
7515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7516         struct drm_i915_gem_object *obj;
7517         uint32_t addr;
7518         int ret;
7519
7520         /* if we want to turn off the cursor ignore width and height */
7521         if (!handle) {
7522                 DRM_DEBUG_KMS("cursor off\n");
7523                 addr = 0;
7524                 obj = NULL;
7525                 mutex_lock(&dev->struct_mutex);
7526                 goto finish;
7527         }
7528
7529         /* Currently we only support 64x64 cursors */
7530         if (width != 64 || height != 64) {
7531                 DRM_ERROR("we currently only support 64x64 cursors\n");
7532                 return -EINVAL;
7533         }
7534
7535         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7536         if (&obj->base == NULL)
7537                 return -ENOENT;
7538
7539         if (obj->base.size < width * height * 4) {
7540                 DRM_ERROR("buffer is to small\n");
7541                 ret = -ENOMEM;
7542                 goto fail;
7543         }
7544
7545         /* we only need to pin inside GTT if cursor is non-phy */
7546         mutex_lock(&dev->struct_mutex);
7547         if (!dev_priv->info->cursor_needs_physical) {
7548                 unsigned alignment;
7549
7550                 if (obj->tiling_mode) {
7551                         DRM_ERROR("cursor cannot be tiled\n");
7552                         ret = -EINVAL;
7553                         goto fail_locked;
7554                 }
7555
7556                 /* Note that the w/a also requires 2 PTE of padding following
7557                  * the bo. We currently fill all unused PTE with the shadow
7558                  * page and so we should always have valid PTE following the
7559                  * cursor preventing the VT-d warning.
7560                  */
7561                 alignment = 0;
7562                 if (need_vtd_wa(dev))
7563                         alignment = 64*1024;
7564
7565                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7566                 if (ret) {
7567                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7568                         goto fail_locked;
7569                 }
7570
7571                 ret = i915_gem_object_put_fence(obj);
7572                 if (ret) {
7573                         DRM_ERROR("failed to release fence for cursor");
7574                         goto fail_unpin;
7575                 }
7576
7577                 addr = i915_gem_obj_ggtt_offset(obj);
7578         } else {
7579                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7580                 ret = i915_gem_attach_phys_object(dev, obj,
7581                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7582                                                   align);
7583                 if (ret) {
7584                         DRM_ERROR("failed to attach phys object\n");
7585                         goto fail_locked;
7586                 }
7587                 addr = obj->phys_obj->handle->busaddr;
7588         }
7589
7590         if (IS_GEN2(dev))
7591                 I915_WRITE(CURSIZE, (height << 12) | width);
7592
7593  finish:
7594         if (intel_crtc->cursor_bo) {
7595                 if (dev_priv->info->cursor_needs_physical) {
7596                         if (intel_crtc->cursor_bo != obj)
7597                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7598                 } else
7599                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7600                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7601         }
7602
7603         mutex_unlock(&dev->struct_mutex);
7604
7605         intel_crtc->cursor_addr = addr;
7606         intel_crtc->cursor_bo = obj;
7607         intel_crtc->cursor_width = width;
7608         intel_crtc->cursor_height = height;
7609
7610         if (intel_crtc->active)
7611                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7612
7613         return 0;
7614 fail_unpin:
7615         i915_gem_object_unpin_from_display_plane(obj);
7616 fail_locked:
7617         mutex_unlock(&dev->struct_mutex);
7618 fail:
7619         drm_gem_object_unreference_unlocked(&obj->base);
7620         return ret;
7621 }
7622
7623 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7624 {
7625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7626
7627         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7628         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7629
7630         if (intel_crtc->active)
7631                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7632
7633         return 0;
7634 }
7635
7636 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7637                                  u16 *blue, uint32_t start, uint32_t size)
7638 {
7639         int end = (start + size > 256) ? 256 : start + size, i;
7640         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7641
7642         for (i = start; i < end; i++) {
7643                 intel_crtc->lut_r[i] = red[i] >> 8;
7644                 intel_crtc->lut_g[i] = green[i] >> 8;
7645                 intel_crtc->lut_b[i] = blue[i] >> 8;
7646         }
7647
7648         intel_crtc_load_lut(crtc);
7649 }
7650
7651 /* VESA 640x480x72Hz mode to set on the pipe */
7652 static struct drm_display_mode load_detect_mode = {
7653         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7654                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7655 };
7656
7657 static struct drm_framebuffer *
7658 intel_framebuffer_create(struct drm_device *dev,
7659                          struct drm_mode_fb_cmd2 *mode_cmd,
7660                          struct drm_i915_gem_object *obj)
7661 {
7662         struct intel_framebuffer *intel_fb;
7663         int ret;
7664
7665         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7666         if (!intel_fb) {
7667                 drm_gem_object_unreference_unlocked(&obj->base);
7668                 return ERR_PTR(-ENOMEM);
7669         }
7670
7671         ret = i915_mutex_lock_interruptible(dev);
7672         if (ret)
7673                 goto err;
7674
7675         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7676         mutex_unlock(&dev->struct_mutex);
7677         if (ret)
7678                 goto err;
7679
7680         return &intel_fb->base;
7681 err:
7682         drm_gem_object_unreference_unlocked(&obj->base);
7683         kfree(intel_fb);
7684
7685         return ERR_PTR(ret);
7686 }
7687
7688 static u32
7689 intel_framebuffer_pitch_for_width(int width, int bpp)
7690 {
7691         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7692         return ALIGN(pitch, 64);
7693 }
7694
7695 static u32
7696 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7697 {
7698         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7699         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7700 }
7701
7702 static struct drm_framebuffer *
7703 intel_framebuffer_create_for_mode(struct drm_device *dev,
7704                                   struct drm_display_mode *mode,
7705                                   int depth, int bpp)
7706 {
7707         struct drm_i915_gem_object *obj;
7708         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7709
7710         obj = i915_gem_alloc_object(dev,
7711                                     intel_framebuffer_size_for_mode(mode, bpp));
7712         if (obj == NULL)
7713                 return ERR_PTR(-ENOMEM);
7714
7715         mode_cmd.width = mode->hdisplay;
7716         mode_cmd.height = mode->vdisplay;
7717         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7718                                                                 bpp);
7719         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7720
7721         return intel_framebuffer_create(dev, &mode_cmd, obj);
7722 }
7723
7724 static struct drm_framebuffer *
7725 mode_fits_in_fbdev(struct drm_device *dev,
7726                    struct drm_display_mode *mode)
7727 {
7728 #ifdef CONFIG_DRM_I915_FBDEV
7729         struct drm_i915_private *dev_priv = dev->dev_private;
7730         struct drm_i915_gem_object *obj;
7731         struct drm_framebuffer *fb;
7732
7733         if (dev_priv->fbdev == NULL)
7734                 return NULL;
7735
7736         obj = dev_priv->fbdev->ifb.obj;
7737         if (obj == NULL)
7738                 return NULL;
7739
7740         fb = &dev_priv->fbdev->ifb.base;
7741         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7742                                                                fb->bits_per_pixel))
7743                 return NULL;
7744
7745         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7746                 return NULL;
7747
7748         return fb;
7749 #else
7750         return NULL;
7751 #endif
7752 }
7753
7754 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7755                                 struct drm_display_mode *mode,
7756                                 struct intel_load_detect_pipe *old)
7757 {
7758         struct intel_crtc *intel_crtc;
7759         struct intel_encoder *intel_encoder =
7760                 intel_attached_encoder(connector);
7761         struct drm_crtc *possible_crtc;
7762         struct drm_encoder *encoder = &intel_encoder->base;
7763         struct drm_crtc *crtc = NULL;
7764         struct drm_device *dev = encoder->dev;
7765         struct drm_framebuffer *fb;
7766         int i = -1;
7767
7768         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7769                       connector->base.id, drm_get_connector_name(connector),
7770                       encoder->base.id, drm_get_encoder_name(encoder));
7771
7772         /*
7773          * Algorithm gets a little messy:
7774          *
7775          *   - if the connector already has an assigned crtc, use it (but make
7776          *     sure it's on first)
7777          *
7778          *   - try to find the first unused crtc that can drive this connector,
7779          *     and use that if we find one
7780          */
7781
7782         /* See if we already have a CRTC for this connector */
7783         if (encoder->crtc) {
7784                 crtc = encoder->crtc;
7785
7786                 mutex_lock(&crtc->mutex);
7787
7788                 old->dpms_mode = connector->dpms;
7789                 old->load_detect_temp = false;
7790
7791                 /* Make sure the crtc and connector are running */
7792                 if (connector->dpms != DRM_MODE_DPMS_ON)
7793                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7794
7795                 return true;
7796         }
7797
7798         /* Find an unused one (if possible) */
7799         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7800                 i++;
7801                 if (!(encoder->possible_crtcs & (1 << i)))
7802                         continue;
7803                 if (!possible_crtc->enabled) {
7804                         crtc = possible_crtc;
7805                         break;
7806                 }
7807         }
7808
7809         /*
7810          * If we didn't find an unused CRTC, don't use any.
7811          */
7812         if (!crtc) {
7813                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7814                 return false;
7815         }
7816
7817         mutex_lock(&crtc->mutex);
7818         intel_encoder->new_crtc = to_intel_crtc(crtc);
7819         to_intel_connector(connector)->new_encoder = intel_encoder;
7820
7821         intel_crtc = to_intel_crtc(crtc);
7822         old->dpms_mode = connector->dpms;
7823         old->load_detect_temp = true;
7824         old->release_fb = NULL;
7825
7826         if (!mode)
7827                 mode = &load_detect_mode;
7828
7829         /* We need a framebuffer large enough to accommodate all accesses
7830          * that the plane may generate whilst we perform load detection.
7831          * We can not rely on the fbcon either being present (we get called
7832          * during its initialisation to detect all boot displays, or it may
7833          * not even exist) or that it is large enough to satisfy the
7834          * requested mode.
7835          */
7836         fb = mode_fits_in_fbdev(dev, mode);
7837         if (fb == NULL) {
7838                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7839                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7840                 old->release_fb = fb;
7841         } else
7842                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7843         if (IS_ERR(fb)) {
7844                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7845                 mutex_unlock(&crtc->mutex);
7846                 return false;
7847         }
7848
7849         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7850                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7851                 if (old->release_fb)
7852                         old->release_fb->funcs->destroy(old->release_fb);
7853                 mutex_unlock(&crtc->mutex);
7854                 return false;
7855         }
7856
7857         /* let the connector get through one full cycle before testing */
7858         intel_wait_for_vblank(dev, intel_crtc->pipe);
7859         return true;
7860 }
7861
7862 void intel_release_load_detect_pipe(struct drm_connector *connector,
7863                                     struct intel_load_detect_pipe *old)
7864 {
7865         struct intel_encoder *intel_encoder =
7866                 intel_attached_encoder(connector);
7867         struct drm_encoder *encoder = &intel_encoder->base;
7868         struct drm_crtc *crtc = encoder->crtc;
7869
7870         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7871                       connector->base.id, drm_get_connector_name(connector),
7872                       encoder->base.id, drm_get_encoder_name(encoder));
7873
7874         if (old->load_detect_temp) {
7875                 to_intel_connector(connector)->new_encoder = NULL;
7876                 intel_encoder->new_crtc = NULL;
7877                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7878
7879                 if (old->release_fb) {
7880                         drm_framebuffer_unregister_private(old->release_fb);
7881                         drm_framebuffer_unreference(old->release_fb);
7882                 }
7883
7884                 mutex_unlock(&crtc->mutex);
7885                 return;
7886         }
7887
7888         /* Switch crtc and encoder back off if necessary */
7889         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7890                 connector->funcs->dpms(connector, old->dpms_mode);
7891
7892         mutex_unlock(&crtc->mutex);
7893 }
7894
7895 static int i9xx_pll_refclk(struct drm_device *dev,
7896                            const struct intel_crtc_config *pipe_config)
7897 {
7898         struct drm_i915_private *dev_priv = dev->dev_private;
7899         u32 dpll = pipe_config->dpll_hw_state.dpll;
7900
7901         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7902                 return dev_priv->vbt.lvds_ssc_freq;
7903         else if (HAS_PCH_SPLIT(dev))
7904                 return 120000;
7905         else if (!IS_GEN2(dev))
7906                 return 96000;
7907         else
7908                 return 48000;
7909 }
7910
7911 /* Returns the clock of the currently programmed mode of the given pipe. */
7912 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7913                                 struct intel_crtc_config *pipe_config)
7914 {
7915         struct drm_device *dev = crtc->base.dev;
7916         struct drm_i915_private *dev_priv = dev->dev_private;
7917         int pipe = pipe_config->cpu_transcoder;
7918         u32 dpll = pipe_config->dpll_hw_state.dpll;
7919         u32 fp;
7920         intel_clock_t clock;
7921         int refclk = i9xx_pll_refclk(dev, pipe_config);
7922
7923         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7924                 fp = pipe_config->dpll_hw_state.fp0;
7925         else
7926                 fp = pipe_config->dpll_hw_state.fp1;
7927
7928         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7929         if (IS_PINEVIEW(dev)) {
7930                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7931                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7932         } else {
7933                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7934                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7935         }
7936
7937         if (!IS_GEN2(dev)) {
7938                 if (IS_PINEVIEW(dev))
7939                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7940                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7941                 else
7942                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7943                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7944
7945                 switch (dpll & DPLL_MODE_MASK) {
7946                 case DPLLB_MODE_DAC_SERIAL:
7947                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7948                                 5 : 10;
7949                         break;
7950                 case DPLLB_MODE_LVDS:
7951                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7952                                 7 : 14;
7953                         break;
7954                 default:
7955                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7956                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7957                         return;
7958                 }
7959
7960                 if (IS_PINEVIEW(dev))
7961                         pineview_clock(refclk, &clock);
7962                 else
7963                         i9xx_clock(refclk, &clock);
7964         } else {
7965                 u32 lvds = I915_READ(LVDS);
7966                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
7967
7968                 if (is_lvds) {
7969                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7970                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7971
7972                         if (lvds & LVDS_CLKB_POWER_UP)
7973                                 clock.p2 = 7;
7974                         else
7975                                 clock.p2 = 14;
7976                 } else {
7977                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7978                                 clock.p1 = 2;
7979                         else {
7980                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7981                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7982                         }
7983                         if (dpll & PLL_P2_DIVIDE_BY_4)
7984                                 clock.p2 = 4;
7985                         else
7986                                 clock.p2 = 2;
7987                 }
7988
7989                 i9xx_clock(refclk, &clock);
7990         }
7991
7992         /*
7993          * This value includes pixel_multiplier. We will use
7994          * port_clock to compute adjusted_mode.crtc_clock in the
7995          * encoder's get_config() function.
7996          */
7997         pipe_config->port_clock = clock.dot;
7998 }
7999
8000 int intel_dotclock_calculate(int link_freq,
8001                              const struct intel_link_m_n *m_n)
8002 {
8003         /*
8004          * The calculation for the data clock is:
8005          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8006          * But we want to avoid losing precison if possible, so:
8007          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8008          *
8009          * and the link clock is simpler:
8010          * link_clock = (m * link_clock) / n
8011          */
8012
8013         if (!m_n->link_n)
8014                 return 0;
8015
8016         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8017 }
8018
8019 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8020                                    struct intel_crtc_config *pipe_config)
8021 {
8022         struct drm_device *dev = crtc->base.dev;
8023
8024         /* read out port_clock from the DPLL */
8025         i9xx_crtc_clock_get(crtc, pipe_config);
8026
8027         /*
8028          * This value does not include pixel_multiplier.
8029          * We will check that port_clock and adjusted_mode.crtc_clock
8030          * agree once we know their relationship in the encoder's
8031          * get_config() function.
8032          */
8033         pipe_config->adjusted_mode.crtc_clock =
8034                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8035                                          &pipe_config->fdi_m_n);
8036 }
8037
8038 /** Returns the currently programmed mode of the given pipe. */
8039 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8040                                              struct drm_crtc *crtc)
8041 {
8042         struct drm_i915_private *dev_priv = dev->dev_private;
8043         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8044         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8045         struct drm_display_mode *mode;
8046         struct intel_crtc_config pipe_config;
8047         int htot = I915_READ(HTOTAL(cpu_transcoder));
8048         int hsync = I915_READ(HSYNC(cpu_transcoder));
8049         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8050         int vsync = I915_READ(VSYNC(cpu_transcoder));
8051         enum pipe pipe = intel_crtc->pipe;
8052
8053         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8054         if (!mode)
8055                 return NULL;
8056
8057         /*
8058          * Construct a pipe_config sufficient for getting the clock info
8059          * back out of crtc_clock_get.
8060          *
8061          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8062          * to use a real value here instead.
8063          */
8064         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8065         pipe_config.pixel_multiplier = 1;
8066         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8067         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8068         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8069         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8070
8071         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8072         mode->hdisplay = (htot & 0xffff) + 1;
8073         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8074         mode->hsync_start = (hsync & 0xffff) + 1;
8075         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8076         mode->vdisplay = (vtot & 0xffff) + 1;
8077         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8078         mode->vsync_start = (vsync & 0xffff) + 1;
8079         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8080
8081         drm_mode_set_name(mode);
8082
8083         return mode;
8084 }
8085
8086 static void intel_increase_pllclock(struct drm_crtc *crtc)
8087 {
8088         struct drm_device *dev = crtc->dev;
8089         drm_i915_private_t *dev_priv = dev->dev_private;
8090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8091         int pipe = intel_crtc->pipe;
8092         int dpll_reg = DPLL(pipe);
8093         int dpll;
8094
8095         if (HAS_PCH_SPLIT(dev))
8096                 return;
8097
8098         if (!dev_priv->lvds_downclock_avail)
8099                 return;
8100
8101         dpll = I915_READ(dpll_reg);
8102         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8103                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8104
8105                 assert_panel_unlocked(dev_priv, pipe);
8106
8107                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8108                 I915_WRITE(dpll_reg, dpll);
8109                 intel_wait_for_vblank(dev, pipe);
8110
8111                 dpll = I915_READ(dpll_reg);
8112                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8113                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8114         }
8115 }
8116
8117 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8118 {
8119         struct drm_device *dev = crtc->dev;
8120         drm_i915_private_t *dev_priv = dev->dev_private;
8121         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8122
8123         if (HAS_PCH_SPLIT(dev))
8124                 return;
8125
8126         if (!dev_priv->lvds_downclock_avail)
8127                 return;
8128
8129         /*
8130          * Since this is called by a timer, we should never get here in
8131          * the manual case.
8132          */
8133         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8134                 int pipe = intel_crtc->pipe;
8135                 int dpll_reg = DPLL(pipe);
8136                 int dpll;
8137
8138                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8139
8140                 assert_panel_unlocked(dev_priv, pipe);
8141
8142                 dpll = I915_READ(dpll_reg);
8143                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8144                 I915_WRITE(dpll_reg, dpll);
8145                 intel_wait_for_vblank(dev, pipe);
8146                 dpll = I915_READ(dpll_reg);
8147                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8148                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8149         }
8150
8151 }
8152
8153 void intel_mark_busy(struct drm_device *dev)
8154 {
8155         struct drm_i915_private *dev_priv = dev->dev_private;
8156
8157         hsw_package_c8_gpu_busy(dev_priv);
8158         i915_update_gfx_val(dev_priv);
8159 }
8160
8161 void intel_mark_idle(struct drm_device *dev)
8162 {
8163         struct drm_i915_private *dev_priv = dev->dev_private;
8164         struct drm_crtc *crtc;
8165
8166         hsw_package_c8_gpu_idle(dev_priv);
8167
8168         if (!i915_powersave)
8169                 return;
8170
8171         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8172                 if (!crtc->fb)
8173                         continue;
8174
8175                 intel_decrease_pllclock(crtc);
8176         }
8177
8178         if (dev_priv->info->gen >= 6)
8179                 gen6_rps_idle(dev->dev_private);
8180 }
8181
8182 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8183                         struct intel_ring_buffer *ring)
8184 {
8185         struct drm_device *dev = obj->base.dev;
8186         struct drm_crtc *crtc;
8187
8188         if (!i915_powersave)
8189                 return;
8190
8191         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8192                 if (!crtc->fb)
8193                         continue;
8194
8195                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8196                         continue;
8197
8198                 intel_increase_pllclock(crtc);
8199                 if (ring && intel_fbc_enabled(dev))
8200                         ring->fbc_dirty = true;
8201         }
8202 }
8203
8204 static void intel_crtc_destroy(struct drm_crtc *crtc)
8205 {
8206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8207         struct drm_device *dev = crtc->dev;
8208         struct intel_unpin_work *work;
8209         unsigned long flags;
8210
8211         spin_lock_irqsave(&dev->event_lock, flags);
8212         work = intel_crtc->unpin_work;
8213         intel_crtc->unpin_work = NULL;
8214         spin_unlock_irqrestore(&dev->event_lock, flags);
8215
8216         if (work) {
8217                 cancel_work_sync(&work->work);
8218                 kfree(work);
8219         }
8220
8221         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8222
8223         drm_crtc_cleanup(crtc);
8224
8225         kfree(intel_crtc);
8226 }
8227
8228 static void intel_unpin_work_fn(struct work_struct *__work)
8229 {
8230         struct intel_unpin_work *work =
8231                 container_of(__work, struct intel_unpin_work, work);
8232         struct drm_device *dev = work->crtc->dev;
8233
8234         mutex_lock(&dev->struct_mutex);
8235         intel_unpin_fb_obj(work->old_fb_obj);
8236         drm_gem_object_unreference(&work->pending_flip_obj->base);
8237         drm_gem_object_unreference(&work->old_fb_obj->base);
8238
8239         intel_update_fbc(dev);
8240         mutex_unlock(&dev->struct_mutex);
8241
8242         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8243         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8244
8245         kfree(work);
8246 }
8247
8248 static void do_intel_finish_page_flip(struct drm_device *dev,
8249                                       struct drm_crtc *crtc)
8250 {
8251         drm_i915_private_t *dev_priv = dev->dev_private;
8252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8253         struct intel_unpin_work *work;
8254         unsigned long flags;
8255
8256         /* Ignore early vblank irqs */
8257         if (intel_crtc == NULL)
8258                 return;
8259
8260         spin_lock_irqsave(&dev->event_lock, flags);
8261         work = intel_crtc->unpin_work;
8262
8263         /* Ensure we don't miss a work->pending update ... */
8264         smp_rmb();
8265
8266         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8267                 spin_unlock_irqrestore(&dev->event_lock, flags);
8268                 return;
8269         }
8270
8271         /* and that the unpin work is consistent wrt ->pending. */
8272         smp_rmb();
8273
8274         intel_crtc->unpin_work = NULL;
8275
8276         if (work->event)
8277                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8278
8279         drm_vblank_put(dev, intel_crtc->pipe);
8280
8281         spin_unlock_irqrestore(&dev->event_lock, flags);
8282
8283         wake_up_all(&dev_priv->pending_flip_queue);
8284
8285         queue_work(dev_priv->wq, &work->work);
8286
8287         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8288 }
8289
8290 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8291 {
8292         drm_i915_private_t *dev_priv = dev->dev_private;
8293         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8294
8295         do_intel_finish_page_flip(dev, crtc);
8296 }
8297
8298 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8299 {
8300         drm_i915_private_t *dev_priv = dev->dev_private;
8301         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8302
8303         do_intel_finish_page_flip(dev, crtc);
8304 }
8305
8306 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8307 {
8308         drm_i915_private_t *dev_priv = dev->dev_private;
8309         struct intel_crtc *intel_crtc =
8310                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8311         unsigned long flags;
8312
8313         /* NB: An MMIO update of the plane base pointer will also
8314          * generate a page-flip completion irq, i.e. every modeset
8315          * is also accompanied by a spurious intel_prepare_page_flip().
8316          */
8317         spin_lock_irqsave(&dev->event_lock, flags);
8318         if (intel_crtc->unpin_work)
8319                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8320         spin_unlock_irqrestore(&dev->event_lock, flags);
8321 }
8322
8323 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8324 {
8325         /* Ensure that the work item is consistent when activating it ... */
8326         smp_wmb();
8327         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8328         /* and that it is marked active as soon as the irq could fire. */
8329         smp_wmb();
8330 }
8331
8332 static int intel_gen2_queue_flip(struct drm_device *dev,
8333                                  struct drm_crtc *crtc,
8334                                  struct drm_framebuffer *fb,
8335                                  struct drm_i915_gem_object *obj,
8336                                  uint32_t flags)
8337 {
8338         struct drm_i915_private *dev_priv = dev->dev_private;
8339         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8340         u32 flip_mask;
8341         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8342         int ret;
8343
8344         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8345         if (ret)
8346                 goto err;
8347
8348         ret = intel_ring_begin(ring, 6);
8349         if (ret)
8350                 goto err_unpin;
8351
8352         /* Can't queue multiple flips, so wait for the previous
8353          * one to finish before executing the next.
8354          */
8355         if (intel_crtc->plane)
8356                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8357         else
8358                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8359         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8360         intel_ring_emit(ring, MI_NOOP);
8361         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8362                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8363         intel_ring_emit(ring, fb->pitches[0]);
8364         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8365         intel_ring_emit(ring, 0); /* aux display base address, unused */
8366
8367         intel_mark_page_flip_active(intel_crtc);
8368         __intel_ring_advance(ring);
8369         return 0;
8370
8371 err_unpin:
8372         intel_unpin_fb_obj(obj);
8373 err:
8374         return ret;
8375 }
8376
8377 static int intel_gen3_queue_flip(struct drm_device *dev,
8378                                  struct drm_crtc *crtc,
8379                                  struct drm_framebuffer *fb,
8380                                  struct drm_i915_gem_object *obj,
8381                                  uint32_t flags)
8382 {
8383         struct drm_i915_private *dev_priv = dev->dev_private;
8384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8385         u32 flip_mask;
8386         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8387         int ret;
8388
8389         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8390         if (ret)
8391                 goto err;
8392
8393         ret = intel_ring_begin(ring, 6);
8394         if (ret)
8395                 goto err_unpin;
8396
8397         if (intel_crtc->plane)
8398                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8399         else
8400                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8401         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8402         intel_ring_emit(ring, MI_NOOP);
8403         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8404                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8405         intel_ring_emit(ring, fb->pitches[0]);
8406         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8407         intel_ring_emit(ring, MI_NOOP);
8408
8409         intel_mark_page_flip_active(intel_crtc);
8410         __intel_ring_advance(ring);
8411         return 0;
8412
8413 err_unpin:
8414         intel_unpin_fb_obj(obj);
8415 err:
8416         return ret;
8417 }
8418
8419 static int intel_gen4_queue_flip(struct drm_device *dev,
8420                                  struct drm_crtc *crtc,
8421                                  struct drm_framebuffer *fb,
8422                                  struct drm_i915_gem_object *obj,
8423                                  uint32_t flags)
8424 {
8425         struct drm_i915_private *dev_priv = dev->dev_private;
8426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8427         uint32_t pf, pipesrc;
8428         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8429         int ret;
8430
8431         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8432         if (ret)
8433                 goto err;
8434
8435         ret = intel_ring_begin(ring, 4);
8436         if (ret)
8437                 goto err_unpin;
8438
8439         /* i965+ uses the linear or tiled offsets from the
8440          * Display Registers (which do not change across a page-flip)
8441          * so we need only reprogram the base address.
8442          */
8443         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8444                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8445         intel_ring_emit(ring, fb->pitches[0]);
8446         intel_ring_emit(ring,
8447                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8448                         obj->tiling_mode);
8449
8450         /* XXX Enabling the panel-fitter across page-flip is so far
8451          * untested on non-native modes, so ignore it for now.
8452          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8453          */
8454         pf = 0;
8455         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8456         intel_ring_emit(ring, pf | pipesrc);
8457
8458         intel_mark_page_flip_active(intel_crtc);
8459         __intel_ring_advance(ring);
8460         return 0;
8461
8462 err_unpin:
8463         intel_unpin_fb_obj(obj);
8464 err:
8465         return ret;
8466 }
8467
8468 static int intel_gen6_queue_flip(struct drm_device *dev,
8469                                  struct drm_crtc *crtc,
8470                                  struct drm_framebuffer *fb,
8471                                  struct drm_i915_gem_object *obj,
8472                                  uint32_t flags)
8473 {
8474         struct drm_i915_private *dev_priv = dev->dev_private;
8475         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8476         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8477         uint32_t pf, pipesrc;
8478         int ret;
8479
8480         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8481         if (ret)
8482                 goto err;
8483
8484         ret = intel_ring_begin(ring, 4);
8485         if (ret)
8486                 goto err_unpin;
8487
8488         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8489                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8490         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8491         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8492
8493         /* Contrary to the suggestions in the documentation,
8494          * "Enable Panel Fitter" does not seem to be required when page
8495          * flipping with a non-native mode, and worse causes a normal
8496          * modeset to fail.
8497          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8498          */
8499         pf = 0;
8500         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8501         intel_ring_emit(ring, pf | pipesrc);
8502
8503         intel_mark_page_flip_active(intel_crtc);
8504         __intel_ring_advance(ring);
8505         return 0;
8506
8507 err_unpin:
8508         intel_unpin_fb_obj(obj);
8509 err:
8510         return ret;
8511 }
8512
8513 static int intel_gen7_queue_flip(struct drm_device *dev,
8514                                  struct drm_crtc *crtc,
8515                                  struct drm_framebuffer *fb,
8516                                  struct drm_i915_gem_object *obj,
8517                                  uint32_t flags)
8518 {
8519         struct drm_i915_private *dev_priv = dev->dev_private;
8520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8521         struct intel_ring_buffer *ring;
8522         uint32_t plane_bit = 0;
8523         int len, ret;
8524
8525         ring = obj->ring;
8526         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8527                 ring = &dev_priv->ring[BCS];
8528
8529         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8530         if (ret)
8531                 goto err;
8532
8533         switch(intel_crtc->plane) {
8534         case PLANE_A:
8535                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8536                 break;
8537         case PLANE_B:
8538                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8539                 break;
8540         case PLANE_C:
8541                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8542                 break;
8543         default:
8544                 WARN_ONCE(1, "unknown plane in flip command\n");
8545                 ret = -ENODEV;
8546                 goto err_unpin;
8547         }
8548
8549         len = 4;
8550         if (ring->id == RCS)
8551                 len += 6;
8552
8553         ret = intel_ring_begin(ring, len);
8554         if (ret)
8555                 goto err_unpin;
8556
8557         /* Unmask the flip-done completion message. Note that the bspec says that
8558          * we should do this for both the BCS and RCS, and that we must not unmask
8559          * more than one flip event at any time (or ensure that one flip message
8560          * can be sent by waiting for flip-done prior to queueing new flips).
8561          * Experimentation says that BCS works despite DERRMR masking all
8562          * flip-done completion events and that unmasking all planes at once
8563          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8564          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8565          */
8566         if (ring->id == RCS) {
8567                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8568                 intel_ring_emit(ring, DERRMR);
8569                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8570                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8571                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8572                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8573                 intel_ring_emit(ring, DERRMR);
8574                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8575         }
8576
8577         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8578         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8579         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8580         intel_ring_emit(ring, (MI_NOOP));
8581
8582         intel_mark_page_flip_active(intel_crtc);
8583         __intel_ring_advance(ring);
8584         return 0;
8585
8586 err_unpin:
8587         intel_unpin_fb_obj(obj);
8588 err:
8589         return ret;
8590 }
8591
8592 static int intel_default_queue_flip(struct drm_device *dev,
8593                                     struct drm_crtc *crtc,
8594                                     struct drm_framebuffer *fb,
8595                                     struct drm_i915_gem_object *obj,
8596                                     uint32_t flags)
8597 {
8598         return -ENODEV;
8599 }
8600
8601 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8602                                 struct drm_framebuffer *fb,
8603                                 struct drm_pending_vblank_event *event,
8604                                 uint32_t page_flip_flags)
8605 {
8606         struct drm_device *dev = crtc->dev;
8607         struct drm_i915_private *dev_priv = dev->dev_private;
8608         struct drm_framebuffer *old_fb = crtc->fb;
8609         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8610         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8611         struct intel_unpin_work *work;
8612         unsigned long flags;
8613         int ret;
8614
8615         /* Can't change pixel format via MI display flips. */
8616         if (fb->pixel_format != crtc->fb->pixel_format)
8617                 return -EINVAL;
8618
8619         /*
8620          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8621          * Note that pitch changes could also affect these register.
8622          */
8623         if (INTEL_INFO(dev)->gen > 3 &&
8624             (fb->offsets[0] != crtc->fb->offsets[0] ||
8625              fb->pitches[0] != crtc->fb->pitches[0]))
8626                 return -EINVAL;
8627
8628         work = kzalloc(sizeof(*work), GFP_KERNEL);
8629         if (work == NULL)
8630                 return -ENOMEM;
8631
8632         work->event = event;
8633         work->crtc = crtc;
8634         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8635         INIT_WORK(&work->work, intel_unpin_work_fn);
8636
8637         ret = drm_vblank_get(dev, intel_crtc->pipe);
8638         if (ret)
8639                 goto free_work;
8640
8641         /* We borrow the event spin lock for protecting unpin_work */
8642         spin_lock_irqsave(&dev->event_lock, flags);
8643         if (intel_crtc->unpin_work) {
8644                 spin_unlock_irqrestore(&dev->event_lock, flags);
8645                 kfree(work);
8646                 drm_vblank_put(dev, intel_crtc->pipe);
8647
8648                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8649                 return -EBUSY;
8650         }
8651         intel_crtc->unpin_work = work;
8652         spin_unlock_irqrestore(&dev->event_lock, flags);
8653
8654         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8655                 flush_workqueue(dev_priv->wq);
8656
8657         ret = i915_mutex_lock_interruptible(dev);
8658         if (ret)
8659                 goto cleanup;
8660
8661         /* Reference the objects for the scheduled work. */
8662         drm_gem_object_reference(&work->old_fb_obj->base);
8663         drm_gem_object_reference(&obj->base);
8664
8665         crtc->fb = fb;
8666
8667         work->pending_flip_obj = obj;
8668
8669         work->enable_stall_check = true;
8670
8671         atomic_inc(&intel_crtc->unpin_work_count);
8672         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8673
8674         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8675         if (ret)
8676                 goto cleanup_pending;
8677
8678         intel_disable_fbc(dev);
8679         intel_mark_fb_busy(obj, NULL);
8680         mutex_unlock(&dev->struct_mutex);
8681
8682         trace_i915_flip_request(intel_crtc->plane, obj);
8683
8684         return 0;
8685
8686 cleanup_pending:
8687         atomic_dec(&intel_crtc->unpin_work_count);
8688         crtc->fb = old_fb;
8689         drm_gem_object_unreference(&work->old_fb_obj->base);
8690         drm_gem_object_unreference(&obj->base);
8691         mutex_unlock(&dev->struct_mutex);
8692
8693 cleanup:
8694         spin_lock_irqsave(&dev->event_lock, flags);
8695         intel_crtc->unpin_work = NULL;
8696         spin_unlock_irqrestore(&dev->event_lock, flags);
8697
8698         drm_vblank_put(dev, intel_crtc->pipe);
8699 free_work:
8700         kfree(work);
8701
8702         return ret;
8703 }
8704
8705 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8706         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8707         .load_lut = intel_crtc_load_lut,
8708 };
8709
8710 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8711                                   struct drm_crtc *crtc)
8712 {
8713         struct drm_device *dev;
8714         struct drm_crtc *tmp;
8715         int crtc_mask = 1;
8716
8717         WARN(!crtc, "checking null crtc?\n");
8718
8719         dev = crtc->dev;
8720
8721         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8722                 if (tmp == crtc)
8723                         break;
8724                 crtc_mask <<= 1;
8725         }
8726
8727         if (encoder->possible_crtcs & crtc_mask)
8728                 return true;
8729         return false;
8730 }
8731
8732 /**
8733  * intel_modeset_update_staged_output_state
8734  *
8735  * Updates the staged output configuration state, e.g. after we've read out the
8736  * current hw state.
8737  */
8738 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8739 {
8740         struct intel_encoder *encoder;
8741         struct intel_connector *connector;
8742
8743         list_for_each_entry(connector, &dev->mode_config.connector_list,
8744                             base.head) {
8745                 connector->new_encoder =
8746                         to_intel_encoder(connector->base.encoder);
8747         }
8748
8749         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8750                             base.head) {
8751                 encoder->new_crtc =
8752                         to_intel_crtc(encoder->base.crtc);
8753         }
8754 }
8755
8756 /**
8757  * intel_modeset_commit_output_state
8758  *
8759  * This function copies the stage display pipe configuration to the real one.
8760  */
8761 static void intel_modeset_commit_output_state(struct drm_device *dev)
8762 {
8763         struct intel_encoder *encoder;
8764         struct intel_connector *connector;
8765
8766         list_for_each_entry(connector, &dev->mode_config.connector_list,
8767                             base.head) {
8768                 connector->base.encoder = &connector->new_encoder->base;
8769         }
8770
8771         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8772                             base.head) {
8773                 encoder->base.crtc = &encoder->new_crtc->base;
8774         }
8775 }
8776
8777 static void
8778 connected_sink_compute_bpp(struct intel_connector * connector,
8779                            struct intel_crtc_config *pipe_config)
8780 {
8781         int bpp = pipe_config->pipe_bpp;
8782
8783         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8784                 connector->base.base.id,
8785                 drm_get_connector_name(&connector->base));
8786
8787         /* Don't use an invalid EDID bpc value */
8788         if (connector->base.display_info.bpc &&
8789             connector->base.display_info.bpc * 3 < bpp) {
8790                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8791                               bpp, connector->base.display_info.bpc*3);
8792                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8793         }
8794
8795         /* Clamp bpp to 8 on screens without EDID 1.4 */
8796         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8797                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8798                               bpp);
8799                 pipe_config->pipe_bpp = 24;
8800         }
8801 }
8802
8803 static int
8804 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8805                           struct drm_framebuffer *fb,
8806                           struct intel_crtc_config *pipe_config)
8807 {
8808         struct drm_device *dev = crtc->base.dev;
8809         struct intel_connector *connector;
8810         int bpp;
8811
8812         switch (fb->pixel_format) {
8813         case DRM_FORMAT_C8:
8814                 bpp = 8*3; /* since we go through a colormap */
8815                 break;
8816         case DRM_FORMAT_XRGB1555:
8817         case DRM_FORMAT_ARGB1555:
8818                 /* checked in intel_framebuffer_init already */
8819                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8820                         return -EINVAL;
8821         case DRM_FORMAT_RGB565:
8822                 bpp = 6*3; /* min is 18bpp */
8823                 break;
8824         case DRM_FORMAT_XBGR8888:
8825         case DRM_FORMAT_ABGR8888:
8826                 /* checked in intel_framebuffer_init already */
8827                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8828                         return -EINVAL;
8829         case DRM_FORMAT_XRGB8888:
8830         case DRM_FORMAT_ARGB8888:
8831                 bpp = 8*3;
8832                 break;
8833         case DRM_FORMAT_XRGB2101010:
8834         case DRM_FORMAT_ARGB2101010:
8835         case DRM_FORMAT_XBGR2101010:
8836         case DRM_FORMAT_ABGR2101010:
8837                 /* checked in intel_framebuffer_init already */
8838                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8839                         return -EINVAL;
8840                 bpp = 10*3;
8841                 break;
8842         /* TODO: gen4+ supports 16 bpc floating point, too. */
8843         default:
8844                 DRM_DEBUG_KMS("unsupported depth\n");
8845                 return -EINVAL;
8846         }
8847
8848         pipe_config->pipe_bpp = bpp;
8849
8850         /* Clamp display bpp to EDID value */
8851         list_for_each_entry(connector, &dev->mode_config.connector_list,
8852                             base.head) {
8853                 if (!connector->new_encoder ||
8854                     connector->new_encoder->new_crtc != crtc)
8855                         continue;
8856
8857                 connected_sink_compute_bpp(connector, pipe_config);
8858         }
8859
8860         return bpp;
8861 }
8862
8863 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8864 {
8865         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8866                         "type: 0x%x flags: 0x%x\n",
8867                 mode->crtc_clock,
8868                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8869                 mode->crtc_hsync_end, mode->crtc_htotal,
8870                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8871                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8872 }
8873
8874 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8875                                    struct intel_crtc_config *pipe_config,
8876                                    const char *context)
8877 {
8878         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8879                       context, pipe_name(crtc->pipe));
8880
8881         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8882         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8883                       pipe_config->pipe_bpp, pipe_config->dither);
8884         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8885                       pipe_config->has_pch_encoder,
8886                       pipe_config->fdi_lanes,
8887                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8888                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8889                       pipe_config->fdi_m_n.tu);
8890         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8891                       pipe_config->has_dp_encoder,
8892                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8893                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8894                       pipe_config->dp_m_n.tu);
8895         DRM_DEBUG_KMS("requested mode:\n");
8896         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8897         DRM_DEBUG_KMS("adjusted mode:\n");
8898         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8899         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8900         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8901         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8902                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8903         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8904                       pipe_config->gmch_pfit.control,
8905                       pipe_config->gmch_pfit.pgm_ratios,
8906                       pipe_config->gmch_pfit.lvds_border_bits);
8907         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8908                       pipe_config->pch_pfit.pos,
8909                       pipe_config->pch_pfit.size,
8910                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8911         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8912         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8913 }
8914
8915 static bool check_encoder_cloning(struct drm_crtc *crtc)
8916 {
8917         int num_encoders = 0;
8918         bool uncloneable_encoders = false;
8919         struct intel_encoder *encoder;
8920
8921         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8922                             base.head) {
8923                 if (&encoder->new_crtc->base != crtc)
8924                         continue;
8925
8926                 num_encoders++;
8927                 if (!encoder->cloneable)
8928                         uncloneable_encoders = true;
8929         }
8930
8931         return !(num_encoders > 1 && uncloneable_encoders);
8932 }
8933
8934 static struct intel_crtc_config *
8935 intel_modeset_pipe_config(struct drm_crtc *crtc,
8936                           struct drm_framebuffer *fb,
8937                           struct drm_display_mode *mode)
8938 {
8939         struct drm_device *dev = crtc->dev;
8940         struct intel_encoder *encoder;
8941         struct intel_crtc_config *pipe_config;
8942         int plane_bpp, ret = -EINVAL;
8943         bool retry = true;
8944
8945         if (!check_encoder_cloning(crtc)) {
8946                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8947                 return ERR_PTR(-EINVAL);
8948         }
8949
8950         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8951         if (!pipe_config)
8952                 return ERR_PTR(-ENOMEM);
8953
8954         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8955         drm_mode_copy(&pipe_config->requested_mode, mode);
8956
8957         pipe_config->cpu_transcoder =
8958                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8959         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8960
8961         /*
8962          * Sanitize sync polarity flags based on requested ones. If neither
8963          * positive or negative polarity is requested, treat this as meaning
8964          * negative polarity.
8965          */
8966         if (!(pipe_config->adjusted_mode.flags &
8967               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8968                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8969
8970         if (!(pipe_config->adjusted_mode.flags &
8971               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8972                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8973
8974         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8975          * plane pixel format and any sink constraints into account. Returns the
8976          * source plane bpp so that dithering can be selected on mismatches
8977          * after encoders and crtc also have had their say. */
8978         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8979                                               fb, pipe_config);
8980         if (plane_bpp < 0)
8981                 goto fail;
8982
8983         /*
8984          * Determine the real pipe dimensions. Note that stereo modes can
8985          * increase the actual pipe size due to the frame doubling and
8986          * insertion of additional space for blanks between the frame. This
8987          * is stored in the crtc timings. We use the requested mode to do this
8988          * computation to clearly distinguish it from the adjusted mode, which
8989          * can be changed by the connectors in the below retry loop.
8990          */
8991         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8992         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8993         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8994
8995 encoder_retry:
8996         /* Ensure the port clock defaults are reset when retrying. */
8997         pipe_config->port_clock = 0;
8998         pipe_config->pixel_multiplier = 1;
8999
9000         /* Fill in default crtc timings, allow encoders to overwrite them. */
9001         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9002
9003         /* Pass our mode to the connectors and the CRTC to give them a chance to
9004          * adjust it according to limitations or connector properties, and also
9005          * a chance to reject the mode entirely.
9006          */
9007         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9008                             base.head) {
9009
9010                 if (&encoder->new_crtc->base != crtc)
9011                         continue;
9012
9013                 if (!(encoder->compute_config(encoder, pipe_config))) {
9014                         DRM_DEBUG_KMS("Encoder config failure\n");
9015                         goto fail;
9016                 }
9017         }
9018
9019         /* Set default port clock if not overwritten by the encoder. Needs to be
9020          * done afterwards in case the encoder adjusts the mode. */
9021         if (!pipe_config->port_clock)
9022                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9023                         * pipe_config->pixel_multiplier;
9024
9025         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9026         if (ret < 0) {
9027                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9028                 goto fail;
9029         }
9030
9031         if (ret == RETRY) {
9032                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9033                         ret = -EINVAL;
9034                         goto fail;
9035                 }
9036
9037                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9038                 retry = false;
9039                 goto encoder_retry;
9040         }
9041
9042         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9043         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9044                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9045
9046         return pipe_config;
9047 fail:
9048         kfree(pipe_config);
9049         return ERR_PTR(ret);
9050 }
9051
9052 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9053  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9054 static void
9055 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9056                              unsigned *prepare_pipes, unsigned *disable_pipes)
9057 {
9058         struct intel_crtc *intel_crtc;
9059         struct drm_device *dev = crtc->dev;
9060         struct intel_encoder *encoder;
9061         struct intel_connector *connector;
9062         struct drm_crtc *tmp_crtc;
9063
9064         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9065
9066         /* Check which crtcs have changed outputs connected to them, these need
9067          * to be part of the prepare_pipes mask. We don't (yet) support global
9068          * modeset across multiple crtcs, so modeset_pipes will only have one
9069          * bit set at most. */
9070         list_for_each_entry(connector, &dev->mode_config.connector_list,
9071                             base.head) {
9072                 if (connector->base.encoder == &connector->new_encoder->base)
9073                         continue;
9074
9075                 if (connector->base.encoder) {
9076                         tmp_crtc = connector->base.encoder->crtc;
9077
9078                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9079                 }
9080
9081                 if (connector->new_encoder)
9082                         *prepare_pipes |=
9083                                 1 << connector->new_encoder->new_crtc->pipe;
9084         }
9085
9086         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9087                             base.head) {
9088                 if (encoder->base.crtc == &encoder->new_crtc->base)
9089                         continue;
9090
9091                 if (encoder->base.crtc) {
9092                         tmp_crtc = encoder->base.crtc;
9093
9094                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9095                 }
9096
9097                 if (encoder->new_crtc)
9098                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9099         }
9100
9101         /* Check for any pipes that will be fully disabled ... */
9102         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9103                             base.head) {
9104                 bool used = false;
9105
9106                 /* Don't try to disable disabled crtcs. */
9107                 if (!intel_crtc->base.enabled)
9108                         continue;
9109
9110                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9111                                     base.head) {
9112                         if (encoder->new_crtc == intel_crtc)
9113                                 used = true;
9114                 }
9115
9116                 if (!used)
9117                         *disable_pipes |= 1 << intel_crtc->pipe;
9118         }
9119
9120
9121         /* set_mode is also used to update properties on life display pipes. */
9122         intel_crtc = to_intel_crtc(crtc);
9123         if (crtc->enabled)
9124                 *prepare_pipes |= 1 << intel_crtc->pipe;
9125
9126         /*
9127          * For simplicity do a full modeset on any pipe where the output routing
9128          * changed. We could be more clever, but that would require us to be
9129          * more careful with calling the relevant encoder->mode_set functions.
9130          */
9131         if (*prepare_pipes)
9132                 *modeset_pipes = *prepare_pipes;
9133
9134         /* ... and mask these out. */
9135         *modeset_pipes &= ~(*disable_pipes);
9136         *prepare_pipes &= ~(*disable_pipes);
9137
9138         /*
9139          * HACK: We don't (yet) fully support global modesets. intel_set_config
9140          * obies this rule, but the modeset restore mode of
9141          * intel_modeset_setup_hw_state does not.
9142          */
9143         *modeset_pipes &= 1 << intel_crtc->pipe;
9144         *prepare_pipes &= 1 << intel_crtc->pipe;
9145
9146         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9147                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9148 }
9149
9150 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9151 {
9152         struct drm_encoder *encoder;
9153         struct drm_device *dev = crtc->dev;
9154
9155         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9156                 if (encoder->crtc == crtc)
9157                         return true;
9158
9159         return false;
9160 }
9161
9162 static void
9163 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9164 {
9165         struct intel_encoder *intel_encoder;
9166         struct intel_crtc *intel_crtc;
9167         struct drm_connector *connector;
9168
9169         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9170                             base.head) {
9171                 if (!intel_encoder->base.crtc)
9172                         continue;
9173
9174                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9175
9176                 if (prepare_pipes & (1 << intel_crtc->pipe))
9177                         intel_encoder->connectors_active = false;
9178         }
9179
9180         intel_modeset_commit_output_state(dev);
9181
9182         /* Update computed state. */
9183         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9184                             base.head) {
9185                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
9186         }
9187
9188         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9189                 if (!connector->encoder || !connector->encoder->crtc)
9190                         continue;
9191
9192                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9193
9194                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9195                         struct drm_property *dpms_property =
9196                                 dev->mode_config.dpms_property;
9197
9198                         connector->dpms = DRM_MODE_DPMS_ON;
9199                         drm_object_property_set_value(&connector->base,
9200                                                          dpms_property,
9201                                                          DRM_MODE_DPMS_ON);
9202
9203                         intel_encoder = to_intel_encoder(connector->encoder);
9204                         intel_encoder->connectors_active = true;
9205                 }
9206         }
9207
9208 }
9209
9210 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9211 {
9212         int diff;
9213
9214         if (clock1 == clock2)
9215                 return true;
9216
9217         if (!clock1 || !clock2)
9218                 return false;
9219
9220         diff = abs(clock1 - clock2);
9221
9222         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9223                 return true;
9224
9225         return false;
9226 }
9227
9228 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9229         list_for_each_entry((intel_crtc), \
9230                             &(dev)->mode_config.crtc_list, \
9231                             base.head) \
9232                 if (mask & (1 <<(intel_crtc)->pipe))
9233
9234 static bool
9235 intel_pipe_config_compare(struct drm_device *dev,
9236                           struct intel_crtc_config *current_config,
9237                           struct intel_crtc_config *pipe_config)
9238 {
9239 #define PIPE_CONF_CHECK_X(name) \
9240         if (current_config->name != pipe_config->name) { \
9241                 DRM_ERROR("mismatch in " #name " " \
9242                           "(expected 0x%08x, found 0x%08x)\n", \
9243                           current_config->name, \
9244                           pipe_config->name); \
9245                 return false; \
9246         }
9247
9248 #define PIPE_CONF_CHECK_I(name) \
9249         if (current_config->name != pipe_config->name) { \
9250                 DRM_ERROR("mismatch in " #name " " \
9251                           "(expected %i, found %i)\n", \
9252                           current_config->name, \
9253                           pipe_config->name); \
9254                 return false; \
9255         }
9256
9257 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9258         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9259                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9260                           "(expected %i, found %i)\n", \
9261                           current_config->name & (mask), \
9262                           pipe_config->name & (mask)); \
9263                 return false; \
9264         }
9265
9266 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9267         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9268                 DRM_ERROR("mismatch in " #name " " \
9269                           "(expected %i, found %i)\n", \
9270                           current_config->name, \
9271                           pipe_config->name); \
9272                 return false; \
9273         }
9274
9275 #define PIPE_CONF_QUIRK(quirk)  \
9276         ((current_config->quirks | pipe_config->quirks) & (quirk))
9277
9278         PIPE_CONF_CHECK_I(cpu_transcoder);
9279
9280         PIPE_CONF_CHECK_I(has_pch_encoder);
9281         PIPE_CONF_CHECK_I(fdi_lanes);
9282         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9283         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9284         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9285         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9286         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9287
9288         PIPE_CONF_CHECK_I(has_dp_encoder);
9289         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9290         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9291         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9292         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9293         PIPE_CONF_CHECK_I(dp_m_n.tu);
9294
9295         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9296         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9297         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9298         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9299         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9300         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9301
9302         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9303         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9304         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9305         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9306         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9307         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9308
9309         PIPE_CONF_CHECK_I(pixel_multiplier);
9310
9311         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9312                               DRM_MODE_FLAG_INTERLACE);
9313
9314         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9315                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9316                                       DRM_MODE_FLAG_PHSYNC);
9317                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9318                                       DRM_MODE_FLAG_NHSYNC);
9319                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9320                                       DRM_MODE_FLAG_PVSYNC);
9321                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9322                                       DRM_MODE_FLAG_NVSYNC);
9323         }
9324
9325         PIPE_CONF_CHECK_I(pipe_src_w);
9326         PIPE_CONF_CHECK_I(pipe_src_h);
9327
9328         PIPE_CONF_CHECK_I(gmch_pfit.control);
9329         /* pfit ratios are autocomputed by the hw on gen4+ */
9330         if (INTEL_INFO(dev)->gen < 4)
9331                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9332         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9333         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9334         if (current_config->pch_pfit.enabled) {
9335                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9336                 PIPE_CONF_CHECK_I(pch_pfit.size);
9337         }
9338
9339         PIPE_CONF_CHECK_I(ips_enabled);
9340
9341         PIPE_CONF_CHECK_I(double_wide);
9342
9343         PIPE_CONF_CHECK_I(shared_dpll);
9344         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9345         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9346         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9347         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9348
9349         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9350                 PIPE_CONF_CHECK_I(pipe_bpp);
9351
9352         if (!IS_HASWELL(dev)) {
9353                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9354                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9355         }
9356
9357 #undef PIPE_CONF_CHECK_X
9358 #undef PIPE_CONF_CHECK_I
9359 #undef PIPE_CONF_CHECK_FLAGS
9360 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9361 #undef PIPE_CONF_QUIRK
9362
9363         return true;
9364 }
9365
9366 static void
9367 check_connector_state(struct drm_device *dev)
9368 {
9369         struct intel_connector *connector;
9370
9371         list_for_each_entry(connector, &dev->mode_config.connector_list,
9372                             base.head) {
9373                 /* This also checks the encoder/connector hw state with the
9374                  * ->get_hw_state callbacks. */
9375                 intel_connector_check_state(connector);
9376
9377                 WARN(&connector->new_encoder->base != connector->base.encoder,
9378                      "connector's staged encoder doesn't match current encoder\n");
9379         }
9380 }
9381
9382 static void
9383 check_encoder_state(struct drm_device *dev)
9384 {
9385         struct intel_encoder *encoder;
9386         struct intel_connector *connector;
9387
9388         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9389                             base.head) {
9390                 bool enabled = false;
9391                 bool active = false;
9392                 enum pipe pipe, tracked_pipe;
9393
9394                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9395                               encoder->base.base.id,
9396                               drm_get_encoder_name(&encoder->base));
9397
9398                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9399                      "encoder's stage crtc doesn't match current crtc\n");
9400                 WARN(encoder->connectors_active && !encoder->base.crtc,
9401                      "encoder's active_connectors set, but no crtc\n");
9402
9403                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9404                                     base.head) {
9405                         if (connector->base.encoder != &encoder->base)
9406                                 continue;
9407                         enabled = true;
9408                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9409                                 active = true;
9410                 }
9411                 WARN(!!encoder->base.crtc != enabled,
9412                      "encoder's enabled state mismatch "
9413                      "(expected %i, found %i)\n",
9414                      !!encoder->base.crtc, enabled);
9415                 WARN(active && !encoder->base.crtc,
9416                      "active encoder with no crtc\n");
9417
9418                 WARN(encoder->connectors_active != active,
9419                      "encoder's computed active state doesn't match tracked active state "
9420                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9421
9422                 active = encoder->get_hw_state(encoder, &pipe);
9423                 WARN(active != encoder->connectors_active,
9424                      "encoder's hw state doesn't match sw tracking "
9425                      "(expected %i, found %i)\n",
9426                      encoder->connectors_active, active);
9427
9428                 if (!encoder->base.crtc)
9429                         continue;
9430
9431                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9432                 WARN(active && pipe != tracked_pipe,
9433                      "active encoder's pipe doesn't match"
9434                      "(expected %i, found %i)\n",
9435                      tracked_pipe, pipe);
9436
9437         }
9438 }
9439
9440 static void
9441 check_crtc_state(struct drm_device *dev)
9442 {
9443         drm_i915_private_t *dev_priv = dev->dev_private;
9444         struct intel_crtc *crtc;
9445         struct intel_encoder *encoder;
9446         struct intel_crtc_config pipe_config;
9447
9448         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9449                             base.head) {
9450                 bool enabled = false;
9451                 bool active = false;
9452
9453                 memset(&pipe_config, 0, sizeof(pipe_config));
9454
9455                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9456                               crtc->base.base.id);
9457
9458                 WARN(crtc->active && !crtc->base.enabled,
9459                      "active crtc, but not enabled in sw tracking\n");
9460
9461                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9462                                     base.head) {
9463                         if (encoder->base.crtc != &crtc->base)
9464                                 continue;
9465                         enabled = true;
9466                         if (encoder->connectors_active)
9467                                 active = true;
9468                 }
9469
9470                 WARN(active != crtc->active,
9471                      "crtc's computed active state doesn't match tracked active state "
9472                      "(expected %i, found %i)\n", active, crtc->active);
9473                 WARN(enabled != crtc->base.enabled,
9474                      "crtc's computed enabled state doesn't match tracked enabled state "
9475                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9476
9477                 active = dev_priv->display.get_pipe_config(crtc,
9478                                                            &pipe_config);
9479
9480                 /* hw state is inconsistent with the pipe A quirk */
9481                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9482                         active = crtc->active;
9483
9484                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9485                                     base.head) {
9486                         enum pipe pipe;
9487                         if (encoder->base.crtc != &crtc->base)
9488                                 continue;
9489                         if (encoder->get_hw_state(encoder, &pipe))
9490                                 encoder->get_config(encoder, &pipe_config);
9491                 }
9492
9493                 WARN(crtc->active != active,
9494                      "crtc active state doesn't match with hw state "
9495                      "(expected %i, found %i)\n", crtc->active, active);
9496
9497                 if (active &&
9498                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9499                         WARN(1, "pipe state doesn't match!\n");
9500                         intel_dump_pipe_config(crtc, &pipe_config,
9501                                                "[hw state]");
9502                         intel_dump_pipe_config(crtc, &crtc->config,
9503                                                "[sw state]");
9504                 }
9505         }
9506 }
9507
9508 static void
9509 check_shared_dpll_state(struct drm_device *dev)
9510 {
9511         drm_i915_private_t *dev_priv = dev->dev_private;
9512         struct intel_crtc *crtc;
9513         struct intel_dpll_hw_state dpll_hw_state;
9514         int i;
9515
9516         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9517                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9518                 int enabled_crtcs = 0, active_crtcs = 0;
9519                 bool active;
9520
9521                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9522
9523                 DRM_DEBUG_KMS("%s\n", pll->name);
9524
9525                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9526
9527                 WARN(pll->active > pll->refcount,
9528                      "more active pll users than references: %i vs %i\n",
9529                      pll->active, pll->refcount);
9530                 WARN(pll->active && !pll->on,
9531                      "pll in active use but not on in sw tracking\n");
9532                 WARN(pll->on && !pll->active,
9533                      "pll in on but not on in use in sw tracking\n");
9534                 WARN(pll->on != active,
9535                      "pll on state mismatch (expected %i, found %i)\n",
9536                      pll->on, active);
9537
9538                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9539                                     base.head) {
9540                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9541                                 enabled_crtcs++;
9542                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9543                                 active_crtcs++;
9544                 }
9545                 WARN(pll->active != active_crtcs,
9546                      "pll active crtcs mismatch (expected %i, found %i)\n",
9547                      pll->active, active_crtcs);
9548                 WARN(pll->refcount != enabled_crtcs,
9549                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9550                      pll->refcount, enabled_crtcs);
9551
9552                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9553                                        sizeof(dpll_hw_state)),
9554                      "pll hw state mismatch\n");
9555         }
9556 }
9557
9558 void
9559 intel_modeset_check_state(struct drm_device *dev)
9560 {
9561         check_connector_state(dev);
9562         check_encoder_state(dev);
9563         check_crtc_state(dev);
9564         check_shared_dpll_state(dev);
9565 }
9566
9567 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9568                                      int dotclock)
9569 {
9570         /*
9571          * FDI already provided one idea for the dotclock.
9572          * Yell if the encoder disagrees.
9573          */
9574         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9575              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9576              pipe_config->adjusted_mode.crtc_clock, dotclock);
9577 }
9578
9579 static int __intel_set_mode(struct drm_crtc *crtc,
9580                             struct drm_display_mode *mode,
9581                             int x, int y, struct drm_framebuffer *fb)
9582 {
9583         struct drm_device *dev = crtc->dev;
9584         drm_i915_private_t *dev_priv = dev->dev_private;
9585         struct drm_display_mode *saved_mode, *saved_hwmode;
9586         struct intel_crtc_config *pipe_config = NULL;
9587         struct intel_crtc *intel_crtc;
9588         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9589         int ret = 0;
9590
9591         saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9592         if (!saved_mode)
9593                 return -ENOMEM;
9594         saved_hwmode = saved_mode + 1;
9595
9596         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9597                                      &prepare_pipes, &disable_pipes);
9598
9599         *saved_hwmode = crtc->hwmode;
9600         *saved_mode = crtc->mode;
9601
9602         /* Hack: Because we don't (yet) support global modeset on multiple
9603          * crtcs, we don't keep track of the new mode for more than one crtc.
9604          * Hence simply check whether any bit is set in modeset_pipes in all the
9605          * pieces of code that are not yet converted to deal with mutliple crtcs
9606          * changing their mode at the same time. */
9607         if (modeset_pipes) {
9608                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9609                 if (IS_ERR(pipe_config)) {
9610                         ret = PTR_ERR(pipe_config);
9611                         pipe_config = NULL;
9612
9613                         goto out;
9614                 }
9615                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9616                                        "[modeset]");
9617         }
9618
9619         /*
9620          * See if the config requires any additional preparation, e.g.
9621          * to adjust global state with pipes off.  We need to do this
9622          * here so we can get the modeset_pipe updated config for the new
9623          * mode set on this crtc.  For other crtcs we need to use the
9624          * adjusted_mode bits in the crtc directly.
9625          */
9626         if (IS_VALLEYVIEW(dev)) {
9627                 valleyview_modeset_global_pipes(dev, &prepare_pipes,
9628                                                 modeset_pipes, pipe_config);
9629
9630                 /* may have added more to prepare_pipes than we should */
9631                 prepare_pipes &= ~disable_pipes;
9632         }
9633
9634         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9635                 intel_crtc_disable(&intel_crtc->base);
9636
9637         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9638                 if (intel_crtc->base.enabled)
9639                         dev_priv->display.crtc_disable(&intel_crtc->base);
9640         }
9641
9642         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9643          * to set it here already despite that we pass it down the callchain.
9644          */
9645         if (modeset_pipes) {
9646                 crtc->mode = *mode;
9647                 /* mode_set/enable/disable functions rely on a correct pipe
9648                  * config. */
9649                 to_intel_crtc(crtc)->config = *pipe_config;
9650         }
9651
9652         /* Only after disabling all output pipelines that will be changed can we
9653          * update the the output configuration. */
9654         intel_modeset_update_state(dev, prepare_pipes);
9655
9656         if (dev_priv->display.modeset_global_resources)
9657                 dev_priv->display.modeset_global_resources(dev);
9658
9659         /* Set up the DPLL and any encoders state that needs to adjust or depend
9660          * on the DPLL.
9661          */
9662         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9663                 ret = intel_crtc_mode_set(&intel_crtc->base,
9664                                           x, y, fb);
9665                 if (ret)
9666                         goto done;
9667         }
9668
9669         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9670         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9671                 dev_priv->display.crtc_enable(&intel_crtc->base);
9672
9673         if (modeset_pipes) {
9674                 /* Store real post-adjustment hardware mode. */
9675                 crtc->hwmode = pipe_config->adjusted_mode;
9676
9677                 /* Calculate and store various constants which
9678                  * are later needed by vblank and swap-completion
9679                  * timestamping. They are derived from true hwmode.
9680                  */
9681                 drm_calc_timestamping_constants(crtc);
9682         }
9683
9684         /* FIXME: add subpixel order */
9685 done:
9686         if (ret && crtc->enabled) {
9687                 crtc->hwmode = *saved_hwmode;
9688                 crtc->mode = *saved_mode;
9689         }
9690
9691 out:
9692         kfree(pipe_config);
9693         kfree(saved_mode);
9694         return ret;
9695 }
9696
9697 static int intel_set_mode(struct drm_crtc *crtc,
9698                           struct drm_display_mode *mode,
9699                           int x, int y, struct drm_framebuffer *fb)
9700 {
9701         int ret;
9702
9703         ret = __intel_set_mode(crtc, mode, x, y, fb);
9704
9705         if (ret == 0)
9706                 intel_modeset_check_state(crtc->dev);
9707
9708         return ret;
9709 }
9710
9711 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9712 {
9713         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9714 }
9715
9716 #undef for_each_intel_crtc_masked
9717
9718 static void intel_set_config_free(struct intel_set_config *config)
9719 {
9720         if (!config)
9721                 return;
9722
9723         kfree(config->save_connector_encoders);
9724         kfree(config->save_encoder_crtcs);
9725         kfree(config);
9726 }
9727
9728 static int intel_set_config_save_state(struct drm_device *dev,
9729                                        struct intel_set_config *config)
9730 {
9731         struct drm_encoder *encoder;
9732         struct drm_connector *connector;
9733         int count;
9734
9735         config->save_encoder_crtcs =
9736                 kcalloc(dev->mode_config.num_encoder,
9737                         sizeof(struct drm_crtc *), GFP_KERNEL);
9738         if (!config->save_encoder_crtcs)
9739                 return -ENOMEM;
9740
9741         config->save_connector_encoders =
9742                 kcalloc(dev->mode_config.num_connector,
9743                         sizeof(struct drm_encoder *), GFP_KERNEL);
9744         if (!config->save_connector_encoders)
9745                 return -ENOMEM;
9746
9747         /* Copy data. Note that driver private data is not affected.
9748          * Should anything bad happen only the expected state is
9749          * restored, not the drivers personal bookkeeping.
9750          */
9751         count = 0;
9752         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9753                 config->save_encoder_crtcs[count++] = encoder->crtc;
9754         }
9755
9756         count = 0;
9757         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9758                 config->save_connector_encoders[count++] = connector->encoder;
9759         }
9760
9761         return 0;
9762 }
9763
9764 static void intel_set_config_restore_state(struct drm_device *dev,
9765                                            struct intel_set_config *config)
9766 {
9767         struct intel_encoder *encoder;
9768         struct intel_connector *connector;
9769         int count;
9770
9771         count = 0;
9772         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9773                 encoder->new_crtc =
9774                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9775         }
9776
9777         count = 0;
9778         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9779                 connector->new_encoder =
9780                         to_intel_encoder(config->save_connector_encoders[count++]);
9781         }
9782 }
9783
9784 static bool
9785 is_crtc_connector_off(struct drm_mode_set *set)
9786 {
9787         int i;
9788
9789         if (set->num_connectors == 0)
9790                 return false;
9791
9792         if (WARN_ON(set->connectors == NULL))
9793                 return false;
9794
9795         for (i = 0; i < set->num_connectors; i++)
9796                 if (set->connectors[i]->encoder &&
9797                     set->connectors[i]->encoder->crtc == set->crtc &&
9798                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9799                         return true;
9800
9801         return false;
9802 }
9803
9804 static void
9805 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9806                                       struct intel_set_config *config)
9807 {
9808
9809         /* We should be able to check here if the fb has the same properties
9810          * and then just flip_or_move it */
9811         if (is_crtc_connector_off(set)) {
9812                 config->mode_changed = true;
9813         } else if (set->crtc->fb != set->fb) {
9814                 /* If we have no fb then treat it as a full mode set */
9815                 if (set->crtc->fb == NULL) {
9816                         struct intel_crtc *intel_crtc =
9817                                 to_intel_crtc(set->crtc);
9818
9819                         if (intel_crtc->active && i915_fastboot) {
9820                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9821                                 config->fb_changed = true;
9822                         } else {
9823                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9824                                 config->mode_changed = true;
9825                         }
9826                 } else if (set->fb == NULL) {
9827                         config->mode_changed = true;
9828                 } else if (set->fb->pixel_format !=
9829                            set->crtc->fb->pixel_format) {
9830                         config->mode_changed = true;
9831                 } else {
9832                         config->fb_changed = true;
9833                 }
9834         }
9835
9836         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9837                 config->fb_changed = true;
9838
9839         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9840                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9841                 drm_mode_debug_printmodeline(&set->crtc->mode);
9842                 drm_mode_debug_printmodeline(set->mode);
9843                 config->mode_changed = true;
9844         }
9845
9846         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9847                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9848 }
9849
9850 static int
9851 intel_modeset_stage_output_state(struct drm_device *dev,
9852                                  struct drm_mode_set *set,
9853                                  struct intel_set_config *config)
9854 {
9855         struct drm_crtc *new_crtc;
9856         struct intel_connector *connector;
9857         struct intel_encoder *encoder;
9858         int ro;
9859
9860         /* The upper layers ensure that we either disable a crtc or have a list
9861          * of connectors. For paranoia, double-check this. */
9862         WARN_ON(!set->fb && (set->num_connectors != 0));
9863         WARN_ON(set->fb && (set->num_connectors == 0));
9864
9865         list_for_each_entry(connector, &dev->mode_config.connector_list,
9866                             base.head) {
9867                 /* Otherwise traverse passed in connector list and get encoders
9868                  * for them. */
9869                 for (ro = 0; ro < set->num_connectors; ro++) {
9870                         if (set->connectors[ro] == &connector->base) {
9871                                 connector->new_encoder = connector->encoder;
9872                                 break;
9873                         }
9874                 }
9875
9876                 /* If we disable the crtc, disable all its connectors. Also, if
9877                  * the connector is on the changing crtc but not on the new
9878                  * connector list, disable it. */
9879                 if ((!set->fb || ro == set->num_connectors) &&
9880                     connector->base.encoder &&
9881                     connector->base.encoder->crtc == set->crtc) {
9882                         connector->new_encoder = NULL;
9883
9884                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9885                                 connector->base.base.id,
9886                                 drm_get_connector_name(&connector->base));
9887                 }
9888
9889
9890                 if (&connector->new_encoder->base != connector->base.encoder) {
9891                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9892                         config->mode_changed = true;
9893                 }
9894         }
9895         /* connector->new_encoder is now updated for all connectors. */
9896
9897         /* Update crtc of enabled connectors. */
9898         list_for_each_entry(connector, &dev->mode_config.connector_list,
9899                             base.head) {
9900                 if (!connector->new_encoder)
9901                         continue;
9902
9903                 new_crtc = connector->new_encoder->base.crtc;
9904
9905                 for (ro = 0; ro < set->num_connectors; ro++) {
9906                         if (set->connectors[ro] == &connector->base)
9907                                 new_crtc = set->crtc;
9908                 }
9909
9910                 /* Make sure the new CRTC will work with the encoder */
9911                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9912                                            new_crtc)) {
9913                         return -EINVAL;
9914                 }
9915                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9916
9917                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9918                         connector->base.base.id,
9919                         drm_get_connector_name(&connector->base),
9920                         new_crtc->base.id);
9921         }
9922
9923         /* Check for any encoders that needs to be disabled. */
9924         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9925                             base.head) {
9926                 list_for_each_entry(connector,
9927                                     &dev->mode_config.connector_list,
9928                                     base.head) {
9929                         if (connector->new_encoder == encoder) {
9930                                 WARN_ON(!connector->new_encoder->new_crtc);
9931
9932                                 goto next_encoder;
9933                         }
9934                 }
9935                 encoder->new_crtc = NULL;
9936 next_encoder:
9937                 /* Only now check for crtc changes so we don't miss encoders
9938                  * that will be disabled. */
9939                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9940                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9941                         config->mode_changed = true;
9942                 }
9943         }
9944         /* Now we've also updated encoder->new_crtc for all encoders. */
9945
9946         return 0;
9947 }
9948
9949 static int intel_crtc_set_config(struct drm_mode_set *set)
9950 {
9951         struct drm_device *dev;
9952         struct drm_mode_set save_set;
9953         struct intel_set_config *config;
9954         int ret;
9955
9956         BUG_ON(!set);
9957         BUG_ON(!set->crtc);
9958         BUG_ON(!set->crtc->helper_private);
9959
9960         /* Enforce sane interface api - has been abused by the fb helper. */
9961         BUG_ON(!set->mode && set->fb);
9962         BUG_ON(set->fb && set->num_connectors == 0);
9963
9964         if (set->fb) {
9965                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9966                                 set->crtc->base.id, set->fb->base.id,
9967                                 (int)set->num_connectors, set->x, set->y);
9968         } else {
9969                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9970         }
9971
9972         dev = set->crtc->dev;
9973
9974         ret = -ENOMEM;
9975         config = kzalloc(sizeof(*config), GFP_KERNEL);
9976         if (!config)
9977                 goto out_config;
9978
9979         ret = intel_set_config_save_state(dev, config);
9980         if (ret)
9981                 goto out_config;
9982
9983         save_set.crtc = set->crtc;
9984         save_set.mode = &set->crtc->mode;
9985         save_set.x = set->crtc->x;
9986         save_set.y = set->crtc->y;
9987         save_set.fb = set->crtc->fb;
9988
9989         /* Compute whether we need a full modeset, only an fb base update or no
9990          * change at all. In the future we might also check whether only the
9991          * mode changed, e.g. for LVDS where we only change the panel fitter in
9992          * such cases. */
9993         intel_set_config_compute_mode_changes(set, config);
9994
9995         ret = intel_modeset_stage_output_state(dev, set, config);
9996         if (ret)
9997                 goto fail;
9998
9999         if (config->mode_changed) {
10000                 ret = intel_set_mode(set->crtc, set->mode,
10001                                      set->x, set->y, set->fb);
10002         } else if (config->fb_changed) {
10003                 intel_crtc_wait_for_pending_flips(set->crtc);
10004
10005                 ret = intel_pipe_set_base(set->crtc,
10006                                           set->x, set->y, set->fb);
10007                 /*
10008                  * In the fastboot case this may be our only check of the
10009                  * state after boot.  It would be better to only do it on
10010                  * the first update, but we don't have a nice way of doing that
10011                  * (and really, set_config isn't used much for high freq page
10012                  * flipping, so increasing its cost here shouldn't be a big
10013                  * deal).
10014                  */
10015                 if (i915_fastboot && ret == 0)
10016                         intel_modeset_check_state(set->crtc->dev);
10017         }
10018
10019         if (ret) {
10020                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10021                               set->crtc->base.id, ret);
10022 fail:
10023                 intel_set_config_restore_state(dev, config);
10024
10025                 /* Try to restore the config */
10026                 if (config->mode_changed &&
10027                     intel_set_mode(save_set.crtc, save_set.mode,
10028                                    save_set.x, save_set.y, save_set.fb))
10029                         DRM_ERROR("failed to restore config after modeset failure\n");
10030         }
10031
10032 out_config:
10033         intel_set_config_free(config);
10034         return ret;
10035 }
10036
10037 static const struct drm_crtc_funcs intel_crtc_funcs = {
10038         .cursor_set = intel_crtc_cursor_set,
10039         .cursor_move = intel_crtc_cursor_move,
10040         .gamma_set = intel_crtc_gamma_set,
10041         .set_config = intel_crtc_set_config,
10042         .destroy = intel_crtc_destroy,
10043         .page_flip = intel_crtc_page_flip,
10044 };
10045
10046 static void intel_cpu_pll_init(struct drm_device *dev)
10047 {
10048         if (HAS_DDI(dev))
10049                 intel_ddi_pll_init(dev);
10050 }
10051
10052 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10053                                       struct intel_shared_dpll *pll,
10054                                       struct intel_dpll_hw_state *hw_state)
10055 {
10056         uint32_t val;
10057
10058         val = I915_READ(PCH_DPLL(pll->id));
10059         hw_state->dpll = val;
10060         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10061         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10062
10063         return val & DPLL_VCO_ENABLE;
10064 }
10065
10066 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10067                                   struct intel_shared_dpll *pll)
10068 {
10069         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10070         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10071 }
10072
10073 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10074                                 struct intel_shared_dpll *pll)
10075 {
10076         /* PCH refclock must be enabled first */
10077         assert_pch_refclk_enabled(dev_priv);
10078
10079         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10080
10081         /* Wait for the clocks to stabilize. */
10082         POSTING_READ(PCH_DPLL(pll->id));
10083         udelay(150);
10084
10085         /* The pixel multiplier can only be updated once the
10086          * DPLL is enabled and the clocks are stable.
10087          *
10088          * So write it again.
10089          */
10090         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10091         POSTING_READ(PCH_DPLL(pll->id));
10092         udelay(200);
10093 }
10094
10095 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10096                                  struct intel_shared_dpll *pll)
10097 {
10098         struct drm_device *dev = dev_priv->dev;
10099         struct intel_crtc *crtc;
10100
10101         /* Make sure no transcoder isn't still depending on us. */
10102         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10103                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10104                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10105         }
10106
10107         I915_WRITE(PCH_DPLL(pll->id), 0);
10108         POSTING_READ(PCH_DPLL(pll->id));
10109         udelay(200);
10110 }
10111
10112 static char *ibx_pch_dpll_names[] = {
10113         "PCH DPLL A",
10114         "PCH DPLL B",
10115 };
10116
10117 static void ibx_pch_dpll_init(struct drm_device *dev)
10118 {
10119         struct drm_i915_private *dev_priv = dev->dev_private;
10120         int i;
10121
10122         dev_priv->num_shared_dpll = 2;
10123
10124         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10125                 dev_priv->shared_dplls[i].id = i;
10126                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10127                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10128                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10129                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10130                 dev_priv->shared_dplls[i].get_hw_state =
10131                         ibx_pch_dpll_get_hw_state;
10132         }
10133 }
10134
10135 static void intel_shared_dpll_init(struct drm_device *dev)
10136 {
10137         struct drm_i915_private *dev_priv = dev->dev_private;
10138
10139         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10140                 ibx_pch_dpll_init(dev);
10141         else
10142                 dev_priv->num_shared_dpll = 0;
10143
10144         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10145         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
10146                       dev_priv->num_shared_dpll);
10147 }
10148
10149 static void intel_crtc_init(struct drm_device *dev, int pipe)
10150 {
10151         drm_i915_private_t *dev_priv = dev->dev_private;
10152         struct intel_crtc *intel_crtc;
10153         int i;
10154
10155         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10156         if (intel_crtc == NULL)
10157                 return;
10158
10159         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10160
10161         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10162         for (i = 0; i < 256; i++) {
10163                 intel_crtc->lut_r[i] = i;
10164                 intel_crtc->lut_g[i] = i;
10165                 intel_crtc->lut_b[i] = i;
10166         }
10167
10168         /*
10169          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10170          * is hooked to plane B. Hence we want plane A feeding pipe B.
10171          */
10172         intel_crtc->pipe = pipe;
10173         intel_crtc->plane = pipe;
10174         if (IS_MOBILE(dev) && INTEL_INFO(dev)->gen < 4) {
10175                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10176                 intel_crtc->plane = !pipe;
10177         }
10178
10179         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10180                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10181         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10182         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10183
10184         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10185 }
10186
10187 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10188 {
10189         struct drm_encoder *encoder = connector->base.encoder;
10190
10191         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10192
10193         if (!encoder)
10194                 return INVALID_PIPE;
10195
10196         return to_intel_crtc(encoder->crtc)->pipe;
10197 }
10198
10199 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10200                                 struct drm_file *file)
10201 {
10202         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10203         struct drm_mode_object *drmmode_obj;
10204         struct intel_crtc *crtc;
10205
10206         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10207                 return -ENODEV;
10208
10209         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10210                         DRM_MODE_OBJECT_CRTC);
10211
10212         if (!drmmode_obj) {
10213                 DRM_ERROR("no such CRTC id\n");
10214                 return -ENOENT;
10215         }
10216
10217         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10218         pipe_from_crtc_id->pipe = crtc->pipe;
10219
10220         return 0;
10221 }
10222
10223 static int intel_encoder_clones(struct intel_encoder *encoder)
10224 {
10225         struct drm_device *dev = encoder->base.dev;
10226         struct intel_encoder *source_encoder;
10227         int index_mask = 0;
10228         int entry = 0;
10229
10230         list_for_each_entry(source_encoder,
10231                             &dev->mode_config.encoder_list, base.head) {
10232
10233                 if (encoder == source_encoder)
10234                         index_mask |= (1 << entry);
10235
10236                 /* Intel hw has only one MUX where enocoders could be cloned. */
10237                 if (encoder->cloneable && source_encoder->cloneable)
10238                         index_mask |= (1 << entry);
10239
10240                 entry++;
10241         }
10242
10243         return index_mask;
10244 }
10245
10246 static bool has_edp_a(struct drm_device *dev)
10247 {
10248         struct drm_i915_private *dev_priv = dev->dev_private;
10249
10250         if (!IS_MOBILE(dev))
10251                 return false;
10252
10253         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10254                 return false;
10255
10256         if (IS_GEN5(dev) &&
10257             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
10258                 return false;
10259
10260         return true;
10261 }
10262
10263 static void intel_setup_outputs(struct drm_device *dev)
10264 {
10265         struct drm_i915_private *dev_priv = dev->dev_private;
10266         struct intel_encoder *encoder;
10267         bool dpd_is_edp = false;
10268
10269         intel_lvds_init(dev);
10270
10271         if (!IS_ULT(dev))
10272                 intel_crt_init(dev);
10273
10274         if (HAS_DDI(dev)) {
10275                 int found;
10276
10277                 /* Haswell uses DDI functions to detect digital outputs */
10278                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10279                 /* DDI A only supports eDP */
10280                 if (found)
10281                         intel_ddi_init(dev, PORT_A);
10282
10283                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10284                  * register */
10285                 found = I915_READ(SFUSE_STRAP);
10286
10287                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10288                         intel_ddi_init(dev, PORT_B);
10289                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10290                         intel_ddi_init(dev, PORT_C);
10291                 if (found & SFUSE_STRAP_DDID_DETECTED)
10292                         intel_ddi_init(dev, PORT_D);
10293         } else if (HAS_PCH_SPLIT(dev)) {
10294                 int found;
10295                 dpd_is_edp = intel_dpd_is_edp(dev);
10296
10297                 if (has_edp_a(dev))
10298                         intel_dp_init(dev, DP_A, PORT_A);
10299
10300                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10301                         /* PCH SDVOB multiplex with HDMIB */
10302                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10303                         if (!found)
10304                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10305                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10306                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10307                 }
10308
10309                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10310                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10311
10312                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10313                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10314
10315                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10316                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10317
10318                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10319                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10320         } else if (IS_VALLEYVIEW(dev)) {
10321                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10322                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10323                                         PORT_B);
10324                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10325                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10326                 }
10327
10328                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10329                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10330                                         PORT_C);
10331                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10332                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
10333                                               PORT_C);
10334                 }
10335
10336                 intel_dsi_init(dev);
10337         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10338                 bool found = false;
10339
10340                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10341                         DRM_DEBUG_KMS("probing SDVOB\n");
10342                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10343                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10344                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10345                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10346                         }
10347
10348                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10349                                 intel_dp_init(dev, DP_B, PORT_B);
10350                 }
10351
10352                 /* Before G4X SDVOC doesn't have its own detect register */
10353
10354                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10355                         DRM_DEBUG_KMS("probing SDVOC\n");
10356                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10357                 }
10358
10359                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10360
10361                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10362                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10363                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10364                         }
10365                         if (SUPPORTS_INTEGRATED_DP(dev))
10366                                 intel_dp_init(dev, DP_C, PORT_C);
10367                 }
10368
10369                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10370                     (I915_READ(DP_D) & DP_DETECTED))
10371                         intel_dp_init(dev, DP_D, PORT_D);
10372         } else if (IS_GEN2(dev))
10373                 intel_dvo_init(dev);
10374
10375         if (SUPPORTS_TV(dev))
10376                 intel_tv_init(dev);
10377
10378         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10379                 encoder->base.possible_crtcs = encoder->crtc_mask;
10380                 encoder->base.possible_clones =
10381                         intel_encoder_clones(encoder);
10382         }
10383
10384         intel_init_pch_refclk(dev);
10385
10386         drm_helper_move_panel_connectors_to_head(dev);
10387 }
10388
10389 void intel_framebuffer_fini(struct intel_framebuffer *fb)
10390 {
10391         drm_framebuffer_cleanup(&fb->base);
10392         WARN_ON(!fb->obj->framebuffer_references--);
10393         drm_gem_object_unreference_unlocked(&fb->obj->base);
10394 }
10395
10396 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10397 {
10398         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10399
10400         intel_framebuffer_fini(intel_fb);
10401         kfree(intel_fb);
10402 }
10403
10404 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10405                                                 struct drm_file *file,
10406                                                 unsigned int *handle)
10407 {
10408         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10409         struct drm_i915_gem_object *obj = intel_fb->obj;
10410
10411         return drm_gem_handle_create(file, &obj->base, handle);
10412 }
10413
10414 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10415         .destroy = intel_user_framebuffer_destroy,
10416         .create_handle = intel_user_framebuffer_create_handle,
10417 };
10418
10419 int intel_framebuffer_init(struct drm_device *dev,
10420                            struct intel_framebuffer *intel_fb,
10421                            struct drm_mode_fb_cmd2 *mode_cmd,
10422                            struct drm_i915_gem_object *obj)
10423 {
10424         int aligned_height, tile_height;
10425         int pitch_limit;
10426         int ret;
10427
10428         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10429
10430         if (obj->tiling_mode == I915_TILING_Y) {
10431                 DRM_DEBUG("hardware does not support tiling Y\n");
10432                 return -EINVAL;
10433         }
10434
10435         if (mode_cmd->pitches[0] & 63) {
10436                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10437                           mode_cmd->pitches[0]);
10438                 return -EINVAL;
10439         }
10440
10441         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10442                 pitch_limit = 32*1024;
10443         } else if (INTEL_INFO(dev)->gen >= 4) {
10444                 if (obj->tiling_mode)
10445                         pitch_limit = 16*1024;
10446                 else
10447                         pitch_limit = 32*1024;
10448         } else if (INTEL_INFO(dev)->gen >= 3) {
10449                 if (obj->tiling_mode)
10450                         pitch_limit = 8*1024;
10451                 else
10452                         pitch_limit = 16*1024;
10453         } else
10454                 /* XXX DSPC is limited to 4k tiled */
10455                 pitch_limit = 8*1024;
10456
10457         if (mode_cmd->pitches[0] > pitch_limit) {
10458                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10459                           obj->tiling_mode ? "tiled" : "linear",
10460                           mode_cmd->pitches[0], pitch_limit);
10461                 return -EINVAL;
10462         }
10463
10464         if (obj->tiling_mode != I915_TILING_NONE &&
10465             mode_cmd->pitches[0] != obj->stride) {
10466                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10467                           mode_cmd->pitches[0], obj->stride);
10468                 return -EINVAL;
10469         }
10470
10471         /* Reject formats not supported by any plane early. */
10472         switch (mode_cmd->pixel_format) {
10473         case DRM_FORMAT_C8:
10474         case DRM_FORMAT_RGB565:
10475         case DRM_FORMAT_XRGB8888:
10476         case DRM_FORMAT_ARGB8888:
10477                 break;
10478         case DRM_FORMAT_XRGB1555:
10479         case DRM_FORMAT_ARGB1555:
10480                 if (INTEL_INFO(dev)->gen > 3) {
10481                         DRM_DEBUG("unsupported pixel format: %s\n",
10482                                   drm_get_format_name(mode_cmd->pixel_format));
10483                         return -EINVAL;
10484                 }
10485                 break;
10486         case DRM_FORMAT_XBGR8888:
10487         case DRM_FORMAT_ABGR8888:
10488         case DRM_FORMAT_XRGB2101010:
10489         case DRM_FORMAT_ARGB2101010:
10490         case DRM_FORMAT_XBGR2101010:
10491         case DRM_FORMAT_ABGR2101010:
10492                 if (INTEL_INFO(dev)->gen < 4) {
10493                         DRM_DEBUG("unsupported pixel format: %s\n",
10494                                   drm_get_format_name(mode_cmd->pixel_format));
10495                         return -EINVAL;
10496                 }
10497                 break;
10498         case DRM_FORMAT_YUYV:
10499         case DRM_FORMAT_UYVY:
10500         case DRM_FORMAT_YVYU:
10501         case DRM_FORMAT_VYUY:
10502                 if (INTEL_INFO(dev)->gen < 5) {
10503                         DRM_DEBUG("unsupported pixel format: %s\n",
10504                                   drm_get_format_name(mode_cmd->pixel_format));
10505                         return -EINVAL;
10506                 }
10507                 break;
10508         default:
10509                 DRM_DEBUG("unsupported pixel format: %s\n",
10510                           drm_get_format_name(mode_cmd->pixel_format));
10511                 return -EINVAL;
10512         }
10513
10514         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10515         if (mode_cmd->offsets[0] != 0)
10516                 return -EINVAL;
10517
10518         tile_height = IS_GEN2(dev) ? 16 : 8;
10519         aligned_height = ALIGN(mode_cmd->height,
10520                                obj->tiling_mode ? tile_height : 1);
10521         /* FIXME drm helper for size checks (especially planar formats)? */
10522         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10523                 return -EINVAL;
10524
10525         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10526         intel_fb->obj = obj;
10527         intel_fb->obj->framebuffer_references++;
10528
10529         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10530         if (ret) {
10531                 DRM_ERROR("framebuffer init failed %d\n", ret);
10532                 return ret;
10533         }
10534
10535         return 0;
10536 }
10537
10538 static struct drm_framebuffer *
10539 intel_user_framebuffer_create(struct drm_device *dev,
10540                               struct drm_file *filp,
10541                               struct drm_mode_fb_cmd2 *mode_cmd)
10542 {
10543         struct drm_i915_gem_object *obj;
10544
10545         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10546                                                 mode_cmd->handles[0]));
10547         if (&obj->base == NULL)
10548                 return ERR_PTR(-ENOENT);
10549
10550         return intel_framebuffer_create(dev, mode_cmd, obj);
10551 }
10552
10553 #ifndef CONFIG_DRM_I915_FBDEV
10554 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10555 {
10556 }
10557 #endif
10558
10559 static const struct drm_mode_config_funcs intel_mode_funcs = {
10560         .fb_create = intel_user_framebuffer_create,
10561         .output_poll_changed = intel_fbdev_output_poll_changed,
10562 };
10563
10564 /* Set up chip specific display functions */
10565 static void intel_init_display(struct drm_device *dev)
10566 {
10567         struct drm_i915_private *dev_priv = dev->dev_private;
10568
10569         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10570                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10571         else if (IS_VALLEYVIEW(dev))
10572                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10573         else if (IS_PINEVIEW(dev))
10574                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10575         else
10576                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10577
10578         if (HAS_DDI(dev)) {
10579                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10580                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10581                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10582                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10583                 dev_priv->display.off = haswell_crtc_off;
10584                 dev_priv->display.update_plane = ironlake_update_plane;
10585         } else if (HAS_PCH_SPLIT(dev)) {
10586                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10587                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10588                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10589                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10590                 dev_priv->display.off = ironlake_crtc_off;
10591                 dev_priv->display.update_plane = ironlake_update_plane;
10592         } else if (IS_VALLEYVIEW(dev)) {
10593                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10594                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10595                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10596                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10597                 dev_priv->display.off = i9xx_crtc_off;
10598                 dev_priv->display.update_plane = i9xx_update_plane;
10599         } else {
10600                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10601                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10602                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10603                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10604                 dev_priv->display.off = i9xx_crtc_off;
10605                 dev_priv->display.update_plane = i9xx_update_plane;
10606         }
10607
10608         /* Returns the core display clock speed */
10609         if (IS_VALLEYVIEW(dev))
10610                 dev_priv->display.get_display_clock_speed =
10611                         valleyview_get_display_clock_speed;
10612         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10613                 dev_priv->display.get_display_clock_speed =
10614                         i945_get_display_clock_speed;
10615         else if (IS_I915G(dev))
10616                 dev_priv->display.get_display_clock_speed =
10617                         i915_get_display_clock_speed;
10618         else if (IS_I945GM(dev) || IS_845G(dev))
10619                 dev_priv->display.get_display_clock_speed =
10620                         i9xx_misc_get_display_clock_speed;
10621         else if (IS_PINEVIEW(dev))
10622                 dev_priv->display.get_display_clock_speed =
10623                         pnv_get_display_clock_speed;
10624         else if (IS_I915GM(dev))
10625                 dev_priv->display.get_display_clock_speed =
10626                         i915gm_get_display_clock_speed;
10627         else if (IS_I865G(dev))
10628                 dev_priv->display.get_display_clock_speed =
10629                         i865_get_display_clock_speed;
10630         else if (IS_I85X(dev))
10631                 dev_priv->display.get_display_clock_speed =
10632                         i855_get_display_clock_speed;
10633         else /* 852, 830 */
10634                 dev_priv->display.get_display_clock_speed =
10635                         i830_get_display_clock_speed;
10636
10637         if (HAS_PCH_SPLIT(dev)) {
10638                 if (IS_GEN5(dev)) {
10639                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10640                         dev_priv->display.write_eld = ironlake_write_eld;
10641                 } else if (IS_GEN6(dev)) {
10642                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10643                         dev_priv->display.write_eld = ironlake_write_eld;
10644                 } else if (IS_IVYBRIDGE(dev)) {
10645                         /* FIXME: detect B0+ stepping and use auto training */
10646                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10647                         dev_priv->display.write_eld = ironlake_write_eld;
10648                         dev_priv->display.modeset_global_resources =
10649                                 ivb_modeset_global_resources;
10650                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10651                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10652                         dev_priv->display.write_eld = haswell_write_eld;
10653                         dev_priv->display.modeset_global_resources =
10654                                 haswell_modeset_global_resources;
10655                 }
10656         } else if (IS_G4X(dev)) {
10657                 dev_priv->display.write_eld = g4x_write_eld;
10658         } else if (IS_VALLEYVIEW(dev)) {
10659                 dev_priv->display.modeset_global_resources =
10660                         valleyview_modeset_global_resources;
10661                 dev_priv->display.write_eld = ironlake_write_eld;
10662         }
10663
10664         /* Default just returns -ENODEV to indicate unsupported */
10665         dev_priv->display.queue_flip = intel_default_queue_flip;
10666
10667         switch (INTEL_INFO(dev)->gen) {
10668         case 2:
10669                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10670                 break;
10671
10672         case 3:
10673                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10674                 break;
10675
10676         case 4:
10677         case 5:
10678                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10679                 break;
10680
10681         case 6:
10682                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10683                 break;
10684         case 7:
10685         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10686                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10687                 break;
10688         }
10689
10690         intel_panel_init_backlight_funcs(dev);
10691 }
10692
10693 /*
10694  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10695  * resume, or other times.  This quirk makes sure that's the case for
10696  * affected systems.
10697  */
10698 static void quirk_pipea_force(struct drm_device *dev)
10699 {
10700         struct drm_i915_private *dev_priv = dev->dev_private;
10701
10702         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10703         DRM_INFO("applying pipe a force quirk\n");
10704 }
10705
10706 /*
10707  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10708  */
10709 static void quirk_ssc_force_disable(struct drm_device *dev)
10710 {
10711         struct drm_i915_private *dev_priv = dev->dev_private;
10712         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10713         DRM_INFO("applying lvds SSC disable quirk\n");
10714 }
10715
10716 /*
10717  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10718  * brightness value
10719  */
10720 static void quirk_invert_brightness(struct drm_device *dev)
10721 {
10722         struct drm_i915_private *dev_priv = dev->dev_private;
10723         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10724         DRM_INFO("applying inverted panel brightness quirk\n");
10725 }
10726
10727 struct intel_quirk {
10728         int device;
10729         int subsystem_vendor;
10730         int subsystem_device;
10731         void (*hook)(struct drm_device *dev);
10732 };
10733
10734 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10735 struct intel_dmi_quirk {
10736         void (*hook)(struct drm_device *dev);
10737         const struct dmi_system_id (*dmi_id_list)[];
10738 };
10739
10740 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10741 {
10742         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10743         return 1;
10744 }
10745
10746 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10747         {
10748                 .dmi_id_list = &(const struct dmi_system_id[]) {
10749                         {
10750                                 .callback = intel_dmi_reverse_brightness,
10751                                 .ident = "NCR Corporation",
10752                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10753                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10754                                 },
10755                         },
10756                         { }  /* terminating entry */
10757                 },
10758                 .hook = quirk_invert_brightness,
10759         },
10760 };
10761
10762 static struct intel_quirk intel_quirks[] = {
10763         /* HP Mini needs pipe A force quirk (LP: #322104) */
10764         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10765
10766         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10767         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10768
10769         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10770         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10771
10772         /* 830 needs to leave pipe A & dpll A up */
10773         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10774
10775         /* Lenovo U160 cannot use SSC on LVDS */
10776         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10777
10778         /* Sony Vaio Y cannot use SSC on LVDS */
10779         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10780
10781         /*
10782          * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10783          * seem to use inverted backlight PWM.
10784          */
10785         { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10786 };
10787
10788 static void intel_init_quirks(struct drm_device *dev)
10789 {
10790         struct pci_dev *d = dev->pdev;
10791         int i;
10792
10793         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10794                 struct intel_quirk *q = &intel_quirks[i];
10795
10796                 if (d->device == q->device &&
10797                     (d->subsystem_vendor == q->subsystem_vendor ||
10798                      q->subsystem_vendor == PCI_ANY_ID) &&
10799                     (d->subsystem_device == q->subsystem_device ||
10800                      q->subsystem_device == PCI_ANY_ID))
10801                         q->hook(dev);
10802         }
10803         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10804                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10805                         intel_dmi_quirks[i].hook(dev);
10806         }
10807 }
10808
10809 /* Disable the VGA plane that we never use */
10810 static void i915_disable_vga(struct drm_device *dev)
10811 {
10812         struct drm_i915_private *dev_priv = dev->dev_private;
10813         u8 sr1;
10814         u32 vga_reg = i915_vgacntrl_reg(dev);
10815
10816         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10817         outb(SR01, VGA_SR_INDEX);
10818         sr1 = inb(VGA_SR_DATA);
10819         outb(sr1 | 1<<5, VGA_SR_DATA);
10820         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10821         udelay(300);
10822
10823         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10824         POSTING_READ(vga_reg);
10825 }
10826
10827 void intel_modeset_init_hw(struct drm_device *dev)
10828 {
10829         intel_prepare_ddi(dev);
10830
10831         intel_init_clock_gating(dev);
10832
10833         intel_reset_dpio(dev);
10834
10835         mutex_lock(&dev->struct_mutex);
10836         intel_enable_gt_powersave(dev);
10837         mutex_unlock(&dev->struct_mutex);
10838 }
10839
10840 void intel_modeset_suspend_hw(struct drm_device *dev)
10841 {
10842         intel_suspend_hw(dev);
10843 }
10844
10845 void intel_modeset_init(struct drm_device *dev)
10846 {
10847         struct drm_i915_private *dev_priv = dev->dev_private;
10848         int i, j, ret;
10849
10850         drm_mode_config_init(dev);
10851
10852         dev->mode_config.min_width = 0;
10853         dev->mode_config.min_height = 0;
10854
10855         dev->mode_config.preferred_depth = 24;
10856         dev->mode_config.prefer_shadow = 1;
10857
10858         dev->mode_config.funcs = &intel_mode_funcs;
10859
10860         intel_init_quirks(dev);
10861
10862         intel_init_pm(dev);
10863
10864         if (INTEL_INFO(dev)->num_pipes == 0)
10865                 return;
10866
10867         intel_init_display(dev);
10868
10869         if (IS_GEN2(dev)) {
10870                 dev->mode_config.max_width = 2048;
10871                 dev->mode_config.max_height = 2048;
10872         } else if (IS_GEN3(dev)) {
10873                 dev->mode_config.max_width = 4096;
10874                 dev->mode_config.max_height = 4096;
10875         } else {
10876                 dev->mode_config.max_width = 8192;
10877                 dev->mode_config.max_height = 8192;
10878         }
10879         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10880
10881         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10882                       INTEL_INFO(dev)->num_pipes,
10883                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10884
10885         for_each_pipe(i) {
10886                 intel_crtc_init(dev, i);
10887                 for (j = 0; j < dev_priv->num_plane; j++) {
10888                         ret = intel_plane_init(dev, i, j);
10889                         if (ret)
10890                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10891                                               pipe_name(i), sprite_name(i, j), ret);
10892                 }
10893         }
10894
10895         intel_init_dpio(dev);
10896         intel_reset_dpio(dev);
10897
10898         intel_cpu_pll_init(dev);
10899         intel_shared_dpll_init(dev);
10900
10901         /* Just disable it once at startup */
10902         i915_disable_vga(dev);
10903         intel_setup_outputs(dev);
10904
10905         /* Just in case the BIOS is doing something questionable. */
10906         intel_disable_fbc(dev);
10907 }
10908
10909 static void
10910 intel_connector_break_all_links(struct intel_connector *connector)
10911 {
10912         connector->base.dpms = DRM_MODE_DPMS_OFF;
10913         connector->base.encoder = NULL;
10914         connector->encoder->connectors_active = false;
10915         connector->encoder->base.crtc = NULL;
10916 }
10917
10918 static void intel_enable_pipe_a(struct drm_device *dev)
10919 {
10920         struct intel_connector *connector;
10921         struct drm_connector *crt = NULL;
10922         struct intel_load_detect_pipe load_detect_temp;
10923
10924         /* We can't just switch on the pipe A, we need to set things up with a
10925          * proper mode and output configuration. As a gross hack, enable pipe A
10926          * by enabling the load detect pipe once. */
10927         list_for_each_entry(connector,
10928                             &dev->mode_config.connector_list,
10929                             base.head) {
10930                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10931                         crt = &connector->base;
10932                         break;
10933                 }
10934         }
10935
10936         if (!crt)
10937                 return;
10938
10939         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10940                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10941
10942
10943 }
10944
10945 static bool
10946 intel_check_plane_mapping(struct intel_crtc *crtc)
10947 {
10948         struct drm_device *dev = crtc->base.dev;
10949         struct drm_i915_private *dev_priv = dev->dev_private;
10950         u32 reg, val;
10951
10952         if (INTEL_INFO(dev)->num_pipes == 1)
10953                 return true;
10954
10955         reg = DSPCNTR(!crtc->plane);
10956         val = I915_READ(reg);
10957
10958         if ((val & DISPLAY_PLANE_ENABLE) &&
10959             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10960                 return false;
10961
10962         return true;
10963 }
10964
10965 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10966 {
10967         struct drm_device *dev = crtc->base.dev;
10968         struct drm_i915_private *dev_priv = dev->dev_private;
10969         u32 reg;
10970
10971         /* Clear any frame start delays used for debugging left by the BIOS */
10972         reg = PIPECONF(crtc->config.cpu_transcoder);
10973         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10974
10975         /* We need to sanitize the plane -> pipe mapping first because this will
10976          * disable the crtc (and hence change the state) if it is wrong. Note
10977          * that gen4+ has a fixed plane -> pipe mapping.  */
10978         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10979                 struct intel_connector *connector;
10980                 bool plane;
10981
10982                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10983                               crtc->base.base.id);
10984
10985                 /* Pipe has the wrong plane attached and the plane is active.
10986                  * Temporarily change the plane mapping and disable everything
10987                  * ...  */
10988                 plane = crtc->plane;
10989                 crtc->plane = !plane;
10990                 dev_priv->display.crtc_disable(&crtc->base);
10991                 crtc->plane = plane;
10992
10993                 /* ... and break all links. */
10994                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10995                                     base.head) {
10996                         if (connector->encoder->base.crtc != &crtc->base)
10997                                 continue;
10998
10999                         intel_connector_break_all_links(connector);
11000                 }
11001
11002                 WARN_ON(crtc->active);
11003                 crtc->base.enabled = false;
11004         }
11005
11006         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11007             crtc->pipe == PIPE_A && !crtc->active) {
11008                 /* BIOS forgot to enable pipe A, this mostly happens after
11009                  * resume. Force-enable the pipe to fix this, the update_dpms
11010                  * call below we restore the pipe to the right state, but leave
11011                  * the required bits on. */
11012                 intel_enable_pipe_a(dev);
11013         }
11014
11015         /* Adjust the state of the output pipe according to whether we
11016          * have active connectors/encoders. */
11017         intel_crtc_update_dpms(&crtc->base);
11018
11019         if (crtc->active != crtc->base.enabled) {
11020                 struct intel_encoder *encoder;
11021
11022                 /* This can happen either due to bugs in the get_hw_state
11023                  * functions or because the pipe is force-enabled due to the
11024                  * pipe A quirk. */
11025                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11026                               crtc->base.base.id,
11027                               crtc->base.enabled ? "enabled" : "disabled",
11028                               crtc->active ? "enabled" : "disabled");
11029
11030                 crtc->base.enabled = crtc->active;
11031
11032                 /* Because we only establish the connector -> encoder ->
11033                  * crtc links if something is active, this means the
11034                  * crtc is now deactivated. Break the links. connector
11035                  * -> encoder links are only establish when things are
11036                  *  actually up, hence no need to break them. */
11037                 WARN_ON(crtc->active);
11038
11039                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11040                         WARN_ON(encoder->connectors_active);
11041                         encoder->base.crtc = NULL;
11042                 }
11043         }
11044 }
11045
11046 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11047 {
11048         struct intel_connector *connector;
11049         struct drm_device *dev = encoder->base.dev;
11050
11051         /* We need to check both for a crtc link (meaning that the
11052          * encoder is active and trying to read from a pipe) and the
11053          * pipe itself being active. */
11054         bool has_active_crtc = encoder->base.crtc &&
11055                 to_intel_crtc(encoder->base.crtc)->active;
11056
11057         if (encoder->connectors_active && !has_active_crtc) {
11058                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11059                               encoder->base.base.id,
11060                               drm_get_encoder_name(&encoder->base));
11061
11062                 /* Connector is active, but has no active pipe. This is
11063                  * fallout from our resume register restoring. Disable
11064                  * the encoder manually again. */
11065                 if (encoder->base.crtc) {
11066                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11067                                       encoder->base.base.id,
11068                                       drm_get_encoder_name(&encoder->base));
11069                         encoder->disable(encoder);
11070                 }
11071
11072                 /* Inconsistent output/port/pipe state happens presumably due to
11073                  * a bug in one of the get_hw_state functions. Or someplace else
11074                  * in our code, like the register restore mess on resume. Clamp
11075                  * things to off as a safer default. */
11076                 list_for_each_entry(connector,
11077                                     &dev->mode_config.connector_list,
11078                                     base.head) {
11079                         if (connector->encoder != encoder)
11080                                 continue;
11081
11082                         intel_connector_break_all_links(connector);
11083                 }
11084         }
11085         /* Enabled encoders without active connectors will be fixed in
11086          * the crtc fixup. */
11087 }
11088
11089 void i915_redisable_vga(struct drm_device *dev)
11090 {
11091         struct drm_i915_private *dev_priv = dev->dev_private;
11092         u32 vga_reg = i915_vgacntrl_reg(dev);
11093
11094         /* This function can be called both from intel_modeset_setup_hw_state or
11095          * at a very early point in our resume sequence, where the power well
11096          * structures are not yet restored. Since this function is at a very
11097          * paranoid "someone might have enabled VGA while we were not looking"
11098          * level, just check if the power well is enabled instead of trying to
11099          * follow the "don't touch the power well if we don't need it" policy
11100          * the rest of the driver uses. */
11101         if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
11102             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
11103                 return;
11104
11105         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11106                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11107                 i915_disable_vga(dev);
11108         }
11109 }
11110
11111 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11112 {
11113         struct drm_i915_private *dev_priv = dev->dev_private;
11114         enum pipe pipe;
11115         struct intel_crtc *crtc;
11116         struct intel_encoder *encoder;
11117         struct intel_connector *connector;
11118         int i;
11119
11120         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11121                             base.head) {
11122                 memset(&crtc->config, 0, sizeof(crtc->config));
11123
11124                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11125                                                                  &crtc->config);
11126
11127                 crtc->base.enabled = crtc->active;
11128                 crtc->primary_enabled = crtc->active;
11129
11130                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11131                               crtc->base.base.id,
11132                               crtc->active ? "enabled" : "disabled");
11133         }
11134
11135         /* FIXME: Smash this into the new shared dpll infrastructure. */
11136         if (HAS_DDI(dev))
11137                 intel_ddi_setup_hw_pll_state(dev);
11138
11139         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11140                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11141
11142                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11143                 pll->active = 0;
11144                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11145                                     base.head) {
11146                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11147                                 pll->active++;
11148                 }
11149                 pll->refcount = pll->active;
11150
11151                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11152                               pll->name, pll->refcount, pll->on);
11153         }
11154
11155         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11156                             base.head) {
11157                 pipe = 0;
11158
11159                 if (encoder->get_hw_state(encoder, &pipe)) {
11160                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11161                         encoder->base.crtc = &crtc->base;
11162                         encoder->get_config(encoder, &crtc->config);
11163                 } else {
11164                         encoder->base.crtc = NULL;
11165                 }
11166
11167                 encoder->connectors_active = false;
11168                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11169                               encoder->base.base.id,
11170                               drm_get_encoder_name(&encoder->base),
11171                               encoder->base.crtc ? "enabled" : "disabled",
11172                               pipe_name(pipe));
11173         }
11174
11175         list_for_each_entry(connector, &dev->mode_config.connector_list,
11176                             base.head) {
11177                 if (connector->get_hw_state(connector)) {
11178                         connector->base.dpms = DRM_MODE_DPMS_ON;
11179                         connector->encoder->connectors_active = true;
11180                         connector->base.encoder = &connector->encoder->base;
11181                 } else {
11182                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11183                         connector->base.encoder = NULL;
11184                 }
11185                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11186                               connector->base.base.id,
11187                               drm_get_connector_name(&connector->base),
11188                               connector->base.encoder ? "enabled" : "disabled");
11189         }
11190 }
11191
11192 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11193  * and i915 state tracking structures. */
11194 void intel_modeset_setup_hw_state(struct drm_device *dev,
11195                                   bool force_restore)
11196 {
11197         struct drm_i915_private *dev_priv = dev->dev_private;
11198         enum pipe pipe;
11199         struct intel_crtc *crtc;
11200         struct intel_encoder *encoder;
11201         int i;
11202
11203         intel_modeset_readout_hw_state(dev);
11204
11205         /*
11206          * Now that we have the config, copy it to each CRTC struct
11207          * Note that this could go away if we move to using crtc_config
11208          * checking everywhere.
11209          */
11210         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11211                             base.head) {
11212                 if (crtc->active && i915_fastboot) {
11213                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
11214
11215                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11216                                       crtc->base.base.id);
11217                         drm_mode_debug_printmodeline(&crtc->base.mode);
11218                 }
11219         }
11220
11221         /* HW state is read out, now we need to sanitize this mess. */
11222         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11223                             base.head) {
11224                 intel_sanitize_encoder(encoder);
11225         }
11226
11227         for_each_pipe(pipe) {
11228                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11229                 intel_sanitize_crtc(crtc);
11230                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11231         }
11232
11233         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11234                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11235
11236                 if (!pll->on || pll->active)
11237                         continue;
11238
11239                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11240
11241                 pll->disable(dev_priv, pll);
11242                 pll->on = false;
11243         }
11244
11245         if (HAS_PCH_SPLIT(dev))
11246                 ilk_wm_get_hw_state(dev);
11247
11248         if (force_restore) {
11249                 i915_redisable_vga(dev);
11250
11251                 /*
11252                  * We need to use raw interfaces for restoring state to avoid
11253                  * checking (bogus) intermediate states.
11254                  */
11255                 for_each_pipe(pipe) {
11256                         struct drm_crtc *crtc =
11257                                 dev_priv->pipe_to_crtc_mapping[pipe];
11258
11259                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11260                                          crtc->fb);
11261                 }
11262         } else {
11263                 intel_modeset_update_staged_output_state(dev);
11264         }
11265
11266         intel_modeset_check_state(dev);
11267
11268         drm_mode_config_reset(dev);
11269 }
11270
11271 void intel_modeset_gem_init(struct drm_device *dev)
11272 {
11273         intel_modeset_init_hw(dev);
11274
11275         intel_setup_overlay(dev);
11276
11277         intel_modeset_setup_hw_state(dev, false);
11278 }
11279
11280 void intel_modeset_cleanup(struct drm_device *dev)
11281 {
11282         struct drm_i915_private *dev_priv = dev->dev_private;
11283         struct drm_crtc *crtc;
11284         struct drm_connector *connector;
11285
11286         /*
11287          * Interrupts and polling as the first thing to avoid creating havoc.
11288          * Too much stuff here (turning of rps, connectors, ...) would
11289          * experience fancy races otherwise.
11290          */
11291         drm_irq_uninstall(dev);
11292         cancel_work_sync(&dev_priv->hotplug_work);
11293         /*
11294          * Due to the hpd irq storm handling the hotplug work can re-arm the
11295          * poll handlers. Hence disable polling after hpd handling is shut down.
11296          */
11297         drm_kms_helper_poll_fini(dev);
11298
11299         mutex_lock(&dev->struct_mutex);
11300
11301         intel_unregister_dsm_handler();
11302
11303         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11304                 /* Skip inactive CRTCs */
11305                 if (!crtc->fb)
11306                         continue;
11307
11308                 intel_increase_pllclock(crtc);
11309         }
11310
11311         intel_disable_fbc(dev);
11312
11313         intel_disable_gt_powersave(dev);
11314
11315         ironlake_teardown_rc6(dev);
11316
11317         mutex_unlock(&dev->struct_mutex);
11318
11319         /* flush any delayed tasks or pending work */
11320         flush_scheduled_work();
11321
11322         /* destroy the backlight and sysfs files before encoders/connectors */
11323         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11324                 intel_panel_destroy_backlight(connector);
11325                 drm_sysfs_connector_remove(connector);
11326         }
11327
11328         drm_mode_config_cleanup(dev);
11329
11330         intel_cleanup_overlay(dev);
11331 }
11332
11333 /*
11334  * Return which encoder is currently attached for connector.
11335  */
11336 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11337 {
11338         return &intel_attached_encoder(connector)->base;
11339 }
11340
11341 void intel_connector_attach_encoder(struct intel_connector *connector,
11342                                     struct intel_encoder *encoder)
11343 {
11344         connector->encoder = encoder;
11345         drm_mode_connector_attach_encoder(&connector->base,
11346                                           &encoder->base);
11347 }
11348
11349 /*
11350  * set vga decode state - true == enable VGA decode
11351  */
11352 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11353 {
11354         struct drm_i915_private *dev_priv = dev->dev_private;
11355         u16 gmch_ctrl;
11356
11357         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11358         if (state)
11359                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11360         else
11361                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11362         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11363         return 0;
11364 }
11365
11366 struct intel_display_error_state {
11367
11368         u32 power_well_driver;
11369
11370         int num_transcoders;
11371
11372         struct intel_cursor_error_state {
11373                 u32 control;
11374                 u32 position;
11375                 u32 base;
11376                 u32 size;
11377         } cursor[I915_MAX_PIPES];
11378
11379         struct intel_pipe_error_state {
11380                 bool power_domain_on;
11381                 u32 source;
11382         } pipe[I915_MAX_PIPES];
11383
11384         struct intel_plane_error_state {
11385                 u32 control;
11386                 u32 stride;
11387                 u32 size;
11388                 u32 pos;
11389                 u32 addr;
11390                 u32 surface;
11391                 u32 tile_offset;
11392         } plane[I915_MAX_PIPES];
11393
11394         struct intel_transcoder_error_state {
11395                 bool power_domain_on;
11396                 enum transcoder cpu_transcoder;
11397
11398                 u32 conf;
11399
11400                 u32 htotal;
11401                 u32 hblank;
11402                 u32 hsync;
11403                 u32 vtotal;
11404                 u32 vblank;
11405                 u32 vsync;
11406         } transcoder[4];
11407 };
11408
11409 struct intel_display_error_state *
11410 intel_display_capture_error_state(struct drm_device *dev)
11411 {
11412         drm_i915_private_t *dev_priv = dev->dev_private;
11413         struct intel_display_error_state *error;
11414         int transcoders[] = {
11415                 TRANSCODER_A,
11416                 TRANSCODER_B,
11417                 TRANSCODER_C,
11418                 TRANSCODER_EDP,
11419         };
11420         int i;
11421
11422         if (INTEL_INFO(dev)->num_pipes == 0)
11423                 return NULL;
11424
11425         error = kzalloc(sizeof(*error), GFP_ATOMIC);
11426         if (error == NULL)
11427                 return NULL;
11428
11429         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11430                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11431
11432         for_each_pipe(i) {
11433                 error->pipe[i].power_domain_on =
11434                         intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11435                 if (!error->pipe[i].power_domain_on)
11436                         continue;
11437
11438                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11439                         error->cursor[i].control = I915_READ(CURCNTR(i));
11440                         error->cursor[i].position = I915_READ(CURPOS(i));
11441                         error->cursor[i].base = I915_READ(CURBASE(i));
11442                 } else {
11443                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11444                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11445                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11446                 }
11447
11448                 error->plane[i].control = I915_READ(DSPCNTR(i));
11449                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11450                 if (INTEL_INFO(dev)->gen <= 3) {
11451                         error->plane[i].size = I915_READ(DSPSIZE(i));
11452                         error->plane[i].pos = I915_READ(DSPPOS(i));
11453                 }
11454                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11455                         error->plane[i].addr = I915_READ(DSPADDR(i));
11456                 if (INTEL_INFO(dev)->gen >= 4) {
11457                         error->plane[i].surface = I915_READ(DSPSURF(i));
11458                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11459                 }
11460
11461                 error->pipe[i].source = I915_READ(PIPESRC(i));
11462         }
11463
11464         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11465         if (HAS_DDI(dev_priv->dev))
11466                 error->num_transcoders++; /* Account for eDP. */
11467
11468         for (i = 0; i < error->num_transcoders; i++) {
11469                 enum transcoder cpu_transcoder = transcoders[i];
11470
11471                 error->transcoder[i].power_domain_on =
11472                         intel_display_power_enabled_sw(dev,
11473                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
11474                 if (!error->transcoder[i].power_domain_on)
11475                         continue;
11476
11477                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11478
11479                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11480                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11481                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11482                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11483                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11484                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11485                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11486         }
11487
11488         return error;
11489 }
11490
11491 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11492
11493 void
11494 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11495                                 struct drm_device *dev,
11496                                 struct intel_display_error_state *error)
11497 {
11498         int i;
11499
11500         if (!error)
11501                 return;
11502
11503         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11504         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11505                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11506                            error->power_well_driver);
11507         for_each_pipe(i) {
11508                 err_printf(m, "Pipe [%d]:\n", i);
11509                 err_printf(m, "  Power: %s\n",
11510                            error->pipe[i].power_domain_on ? "on" : "off");
11511                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11512
11513                 err_printf(m, "Plane [%d]:\n", i);
11514                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11515                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11516                 if (INTEL_INFO(dev)->gen <= 3) {
11517                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11518                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11519                 }
11520                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11521                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11522                 if (INTEL_INFO(dev)->gen >= 4) {
11523                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11524                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11525                 }
11526
11527                 err_printf(m, "Cursor [%d]:\n", i);
11528                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11529                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11530                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11531         }
11532
11533         for (i = 0; i < error->num_transcoders; i++) {
11534                 err_printf(m, "CPU transcoder: %c\n",
11535                            transcoder_name(error->transcoder[i].cpu_transcoder));
11536                 err_printf(m, "  Power: %s\n",
11537                            error->transcoder[i].power_domain_on ? "on" : "off");
11538                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11539                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11540                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11541                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11542                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11543                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11544                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11545         }
11546 }