drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  49                                 struct intel_crtc_config *pipe_config);
  50 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  51                                    struct intel_crtc_config *pipe_config);
  52
  53 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  54                           int x, int y, struct drm_framebuffer *old_fb);
  55
  56
  57 typedef struct {
  58         int     min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62         int     dot_limit;
  63         int     p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 typedef struct intel_limit intel_limit_t;
  67 struct intel_limit {
  68         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  69         intel_p2_t          p2;
  70 };
  71
  72 int
  73 intel_pch_rawclk(struct drm_device *dev)
  74 {
  75         struct drm_i915_private *dev_priv = dev->dev_private;
  76
  77         WARN_ON(!HAS_PCH_SPLIT(dev));
  78
  79         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  80 }
  81
  82 static inline u32 /* units of 100MHz */
  83 intel_fdi_link_freq(struct drm_device *dev)
  84 {
  85         if (IS_GEN5(dev)) {
  86                 struct drm_i915_private *dev_priv = dev->dev_private;
  87                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  88         } else
  89                 return 27;
  90 }
  91
  92 static const intel_limit_t intel_limits_i8xx_dac = {
  93         .dot = { .min = 25000, .max = 350000 },
  94         .vco = { .min = 930000, .max = 1400000 },
  95         .n = { .min = 3, .max = 16 },
  96         .m = { .min = 96, .max = 140 },
  97         .m1 = { .min = 18, .max = 26 },
  98         .m2 = { .min = 6, .max = 16 },
  99         .p = { .min = 4, .max = 128 },
 100         .p1 = { .min = 2, .max = 33 },
 101         .p2 = { .dot_limit = 165000,
 102                 .p2_slow = 4, .p2_fast = 2 },
 103 };
 104
 105 static const intel_limit_t intel_limits_i8xx_dvo = {
 106         .dot = { .min = 25000, .max = 350000 },
 107         .vco = { .min = 930000, .max = 1400000 },
 108         .n = { .min = 3, .max = 16 },
 109         .m = { .min = 96, .max = 140 },
 110         .m1 = { .min = 18, .max = 26 },
 111         .m2 = { .min = 6, .max = 16 },
 112         .p = { .min = 4, .max = 128 },
 113         .p1 = { .min = 2, .max = 33 },
 114         .p2 = { .dot_limit = 165000,
 115                 .p2_slow = 4, .p2_fast = 4 },
 116 };
 117
 118 static const intel_limit_t intel_limits_i8xx_lvds = {
 119         .dot = { .min = 25000, .max = 350000 },
 120         .vco = { .min = 930000, .max = 1400000 },
 121         .n = { .min = 3, .max = 16 },
 122         .m = { .min = 96, .max = 140 },
 123         .m1 = { .min = 18, .max = 26 },
 124         .m2 = { .min = 6, .max = 16 },
 125         .p = { .min = 4, .max = 128 },
 126         .p1 = { .min = 1, .max = 6 },
 127         .p2 = { .dot_limit = 165000,
 128                 .p2_slow = 14, .p2_fast = 7 },
 129 };
 130
 131 static const intel_limit_t intel_limits_i9xx_sdvo = {
 132         .dot = { .min = 20000, .max = 400000 },
 133         .vco = { .min = 1400000, .max = 2800000 },
 134         .n = { .min = 1, .max = 6 },
 135         .m = { .min = 70, .max = 120 },
 136         .m1 = { .min = 8, .max = 18 },
 137         .m2 = { .min = 3, .max = 7 },
 138         .p = { .min = 5, .max = 80 },
 139         .p1 = { .min = 1, .max = 8 },
 140         .p2 = { .dot_limit = 200000,
 141                 .p2_slow = 10, .p2_fast = 5 },
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_lvds = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 8, .max = 18 },
 150         .m2 = { .min = 3, .max = 7 },
 151         .p = { .min = 7, .max = 98 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 112000,
 154                 .p2_slow = 14, .p2_fast = 7 },
 155 };
 156
 157
 158 static const intel_limit_t intel_limits_g4x_sdvo = {
 159         .dot = { .min = 25000, .max = 270000 },
 160         .vco = { .min = 1750000, .max = 3500000},
 161         .n = { .min = 1, .max = 4 },
 162         .m = { .min = 104, .max = 138 },
 163         .m1 = { .min = 17, .max = 23 },
 164         .m2 = { .min = 5, .max = 11 },
 165         .p = { .min = 10, .max = 30 },
 166         .p1 = { .min = 1, .max = 3},
 167         .p2 = { .dot_limit = 270000,
 168                 .p2_slow = 10,
 169                 .p2_fast = 10
 170         },
 171 };
 172
 173 static const intel_limit_t intel_limits_g4x_hdmi = {
 174         .dot = { .min = 22000, .max = 400000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 16, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 5, .max = 80 },
 181         .p1 = { .min = 1, .max = 8},
 182         .p2 = { .dot_limit = 165000,
 183                 .p2_slow = 10, .p2_fast = 5 },
 184 };
 185
 186 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 187         .dot = { .min = 20000, .max = 115000 },
 188         .vco = { .min = 1750000, .max = 3500000 },
 189         .n = { .min = 1, .max = 3 },
 190         .m = { .min = 104, .max = 138 },
 191         .m1 = { .min = 17, .max = 23 },
 192         .m2 = { .min = 5, .max = 11 },
 193         .p = { .min = 28, .max = 112 },
 194         .p1 = { .min = 2, .max = 8 },
 195         .p2 = { .dot_limit = 0,
 196                 .p2_slow = 14, .p2_fast = 14
 197         },
 198 };
 199
 200 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 201         .dot = { .min = 80000, .max = 224000 },
 202         .vco = { .min = 1750000, .max = 3500000 },
 203         .n = { .min = 1, .max = 3 },
 204         .m = { .min = 104, .max = 138 },
 205         .m1 = { .min = 17, .max = 23 },
 206         .m2 = { .min = 5, .max = 11 },
 207         .p = { .min = 14, .max = 42 },
 208         .p1 = { .min = 2, .max = 6 },
 209         .p2 = { .dot_limit = 0,
 210                 .p2_slow = 7, .p2_fast = 7
 211         },
 212 };
 213
 214 static const intel_limit_t intel_limits_pineview_sdvo = {
 215         .dot = { .min = 20000, .max = 400000},
 216         .vco = { .min = 1700000, .max = 3500000 },
 217         /* Pineview's Ncounter is a ring counter */
 218         .n = { .min = 3, .max = 6 },
 219         .m = { .min = 2, .max = 256 },
 220         /* Pineview only has one combined m divider, which we treat as m2. */
 221         .m1 = { .min = 0, .max = 0 },
 222         .m2 = { .min = 0, .max = 254 },
 223         .p = { .min = 5, .max = 80 },
 224         .p1 = { .min = 1, .max = 8 },
 225         .p2 = { .dot_limit = 200000,
 226                 .p2_slow = 10, .p2_fast = 5 },
 227 };
 228
 229 static const intel_limit_t intel_limits_pineview_lvds = {
 230         .dot = { .min = 20000, .max = 400000 },
 231         .vco = { .min = 1700000, .max = 3500000 },
 232         .n = { .min = 3, .max = 6 },
 233         .m = { .min = 2, .max = 256 },
 234         .m1 = { .min = 0, .max = 0 },
 235         .m2 = { .min = 0, .max = 254 },
 236         .p = { .min = 7, .max = 112 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 112000,
 239                 .p2_slow = 14, .p2_fast = 14 },
 240 };
 241
 242 /* Ironlake / Sandybridge
 243  *
 244  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 245  * the range value for them is (actual_value - 2).
 246  */
 247 static const intel_limit_t intel_limits_ironlake_dac = {
 248         .dot = { .min = 25000, .max = 350000 },
 249         .vco = { .min = 1760000, .max = 3510000 },
 250         .n = { .min = 1, .max = 5 },
 251         .m = { .min = 79, .max = 127 },
 252         .m1 = { .min = 12, .max = 22 },
 253         .m2 = { .min = 5, .max = 9 },
 254         .p = { .min = 5, .max = 80 },
 255         .p1 = { .min = 1, .max = 8 },
 256         .p2 = { .dot_limit = 225000,
 257                 .p2_slow = 10, .p2_fast = 5 },
 258 };
 259
 260 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 261         .dot = { .min = 25000, .max = 350000 },
 262         .vco = { .min = 1760000, .max = 3510000 },
 263         .n = { .min = 1, .max = 3 },
 264         .m = { .min = 79, .max = 118 },
 265         .m1 = { .min = 12, .max = 22 },
 266         .m2 = { .min = 5, .max = 9 },
 267         .p = { .min = 28, .max = 112 },
 268         .p1 = { .min = 2, .max = 8 },
 269         .p2 = { .dot_limit = 225000,
 270                 .p2_slow = 14, .p2_fast = 14 },
 271 };
 272
 273 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 274         .dot = { .min = 25000, .max = 350000 },
 275         .vco = { .min = 1760000, .max = 3510000 },
 276         .n = { .min = 1, .max = 3 },
 277         .m = { .min = 79, .max = 127 },
 278         .m1 = { .min = 12, .max = 22 },
 279         .m2 = { .min = 5, .max = 9 },
 280         .p = { .min = 14, .max = 56 },
 281         .p1 = { .min = 2, .max = 8 },
 282         .p2 = { .dot_limit = 225000,
 283                 .p2_slow = 7, .p2_fast = 7 },
 284 };
 285
 286 /* LVDS 100mhz refclk limits. */
 287 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 2 },
 291         .m = { .min = 79, .max = 126 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 28, .max = 112 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298 };
 299
 300 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 3 },
 304         .m = { .min = 79, .max = 126 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 14, .max = 42 },
 308         .p1 = { .min = 2, .max = 6 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 7, .p2_fast = 7 },
 311 };
 312
 313 static const intel_limit_t intel_limits_vlv_dac = {
 314         .dot = { .min = 25000, .max = 270000 },
 315         .vco = { .min = 4000000, .max = 6000000 },
 316         .n = { .min = 1, .max = 7 },
 317         .m = { .min = 22, .max = 450 }, /* guess */
 318         .m1 = { .min = 2, .max = 3 },
 319         .m2 = { .min = 11, .max = 156 },
 320         .p = { .min = 10, .max = 30 },
 321         .p1 = { .min = 1, .max = 3 },
 322         .p2 = { .dot_limit = 270000,
 323                 .p2_slow = 2, .p2_fast = 20 },
 324 };
 325
 326 static const intel_limit_t intel_limits_vlv_hdmi = {
 327         .dot = { .min = 25000, .max = 270000 },
 328         .vco = { .min = 4000000, .max = 6000000 },
 329         .n = { .min = 1, .max = 7 },
 330         .m = { .min = 60, .max = 300 }, /* guess */
 331         .m1 = { .min = 2, .max = 3 },
 332         .m2 = { .min = 11, .max = 156 },
 333         .p = { .min = 10, .max = 30 },
 334         .p1 = { .min = 2, .max = 3 },
 335         .p2 = { .dot_limit = 270000,
 336                 .p2_slow = 2, .p2_fast = 20 },
 337 };
 338
 339 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 340                                                 int refclk)
 341 {
 342         struct drm_device *dev = crtc->dev;
 343         const intel_limit_t *limit;
 344
 345         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 346                 if (intel_is_dual_link_lvds(dev)) {
 347                         if (refclk == 100000)
 348                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 349                         else
 350                                 limit = &intel_limits_ironlake_dual_lvds;
 351                 } else {
 352                         if (refclk == 100000)
 353                                 limit = &intel_limits_ironlake_single_lvds_100m;
 354                         else
 355                                 limit = &intel_limits_ironlake_single_lvds;
 356                 }
 357         } else
 358                 limit = &intel_limits_ironlake_dac;
 359
 360         return limit;
 361 }
 362
 363 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 364 {
 365         struct drm_device *dev = crtc->dev;
 366         const intel_limit_t *limit;
 367
 368         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 369                 if (intel_is_dual_link_lvds(dev))
 370                         limit = &intel_limits_g4x_dual_channel_lvds;
 371                 else
 372                         limit = &intel_limits_g4x_single_channel_lvds;
 373         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 374                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 375                 limit = &intel_limits_g4x_hdmi;
 376         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 377                 limit = &intel_limits_g4x_sdvo;
 378         } else /* The option is for other outputs */
 379                 limit = &intel_limits_i9xx_sdvo;
 380
 381         return limit;
 382 }
 383
 384 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 385 {
 386         struct drm_device *dev = crtc->dev;
 387         const intel_limit_t *limit;
 388
 389         if (HAS_PCH_SPLIT(dev))
 390                 limit = intel_ironlake_limit(crtc, refclk);
 391         else if (IS_G4X(dev)) {
 392                 limit = intel_g4x_limit(crtc);
 393         } else if (IS_PINEVIEW(dev)) {
 394                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 395                         limit = &intel_limits_pineview_lvds;
 396                 else
 397                         limit = &intel_limits_pineview_sdvo;
 398         } else if (IS_VALLEYVIEW(dev)) {
 399                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 400                         limit = &intel_limits_vlv_dac;
 401                 else
 402                         limit = &intel_limits_vlv_hdmi;
 403         } else if (!IS_GEN2(dev)) {
 404                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 405                         limit = &intel_limits_i9xx_lvds;
 406                 else
 407                         limit = &intel_limits_i9xx_sdvo;
 408         } else {
 409                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 410                         limit = &intel_limits_i8xx_lvds;
 411                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 412                         limit = &intel_limits_i8xx_dvo;
 413                 else
 414                         limit = &intel_limits_i8xx_dac;
 415         }
 416         return limit;
 417 }
 418
 419 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 420 static void pineview_clock(int refclk, intel_clock_t *clock)
 421 {
 422         clock->m = clock->m2 + 2;
 423         clock->p = clock->p1 * clock->p2;
 424         clock->vco = refclk * clock->m / clock->n;
 425         clock->dot = clock->vco / clock->p;
 426 }
 427
 428 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 429 {
 430         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 431 }
 432
 433 static void i9xx_clock(int refclk, intel_clock_t *clock)
 434 {
 435         clock->m = i9xx_dpll_compute_m(clock);
 436         clock->p = clock->p1 * clock->p2;
 437         clock->vco = refclk * clock->m / (clock->n + 2);
 438         clock->dot = clock->vco / clock->p;
 439 }
 440
 441 /**
 442  * Returns whether any output on the specified pipe is of the specified type
 443  */
 444 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 445 {
 446         struct drm_device *dev = crtc->dev;
 447         struct intel_encoder *encoder;
 448
 449         for_each_encoder_on_crtc(dev, crtc, encoder)
 450                 if (encoder->type == type)
 451                         return true;
 452
 453         return false;
 454 }
 455
 456 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 457 /**
 458  * Returns whether the given set of divisors are valid for a given refclk with
 459  * the given connectors.
 460  */
 461
 462 static bool intel_PLL_is_valid(struct drm_device *dev,
 463                                const intel_limit_t *limit,
 464                                const intel_clock_t *clock)
 465 {
 466         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 467                 INTELPllInvalid("p1 out of range\n");
 468         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 469                 INTELPllInvalid("p out of range\n");
 470         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 471                 INTELPllInvalid("m2 out of range\n");
 472         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 473                 INTELPllInvalid("m1 out of range\n");
 474         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 475                 INTELPllInvalid("m1 <= m2\n");
 476         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 477                 INTELPllInvalid("m out of range\n");
 478         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 479                 INTELPllInvalid("n out of range\n");
 480         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 481                 INTELPllInvalid("vco out of range\n");
 482         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 483          * connector, etc., rather than just a single range.
 484          */
 485         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 486                 INTELPllInvalid("dot out of range\n");
 487
 488         return true;
 489 }
 490
 491 static bool
 492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 493                     int target, int refclk, intel_clock_t *match_clock,
 494                     intel_clock_t *best_clock)
 495 {
 496         struct drm_device *dev = crtc->dev;
 497         intel_clock_t clock;
 498         int err = target;
 499
 500         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 501                 /*
 502                  * For LVDS just rely on its current settings for dual-channel.
 503                  * We haven't figured out how to reliably set up different
 504                  * single/dual channel state, if we even can.
 505                  */
 506                 if (intel_is_dual_link_lvds(dev))
 507                         clock.p2 = limit->p2.p2_fast;
 508                 else
 509                         clock.p2 = limit->p2.p2_slow;
 510         } else {
 511                 if (target < limit->p2.dot_limit)
 512                         clock.p2 = limit->p2.p2_slow;
 513                 else
 514                         clock.p2 = limit->p2.p2_fast;
 515         }
 516
 517         memset(best_clock, 0, sizeof(*best_clock));
 518
 519         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 520              clock.m1++) {
 521                 for (clock.m2 = limit->m2.min;
 522                      clock.m2 <= limit->m2.max; clock.m2++) {
 523                         if (clock.m2 >= clock.m1)
 524                                 break;
 525                         for (clock.n = limit->n.min;
 526                              clock.n <= limit->n.max; clock.n++) {
 527                                 for (clock.p1 = limit->p1.min;
 528                                         clock.p1 <= limit->p1.max; clock.p1++) {
 529                                         int this_err;
 530
 531                                         i9xx_clock(refclk, &clock);
 532                                         if (!intel_PLL_is_valid(dev, limit,
 533                                                                 &clock))
 534                                                 continue;
 535                                         if (match_clock &&
 536                                             clock.p != match_clock->p)
 537                                                 continue;
 538
 539                                         this_err = abs(clock.dot - target);
 540                                         if (this_err < err) {
 541                                                 *best_clock = clock;
 542                                                 err = this_err;
 543                                         }
 544                                 }
 545                         }
 546                 }
 547         }
 548
 549         return (err != target);
 550 }
 551
 552 static bool
 553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 554                    int target, int refclk, intel_clock_t *match_clock,
 555                    intel_clock_t *best_clock)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         intel_clock_t clock;
 559         int err = target;
 560
 561         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 562                 /*
 563                  * For LVDS just rely on its current settings for dual-channel.
 564                  * We haven't figured out how to reliably set up different
 565                  * single/dual channel state, if we even can.
 566                  */
 567                 if (intel_is_dual_link_lvds(dev))
 568                         clock.p2 = limit->p2.p2_fast;
 569                 else
 570                         clock.p2 = limit->p2.p2_slow;
 571         } else {
 572                 if (target < limit->p2.dot_limit)
 573                         clock.p2 = limit->p2.p2_slow;
 574                 else
 575                         clock.p2 = limit->p2.p2_fast;
 576         }
 577
 578         memset(best_clock, 0, sizeof(*best_clock));
 579
 580         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 581              clock.m1++) {
 582                 for (clock.m2 = limit->m2.min;
 583                      clock.m2 <= limit->m2.max; clock.m2++) {
 584                         for (clock.n = limit->n.min;
 585                              clock.n <= limit->n.max; clock.n++) {
 586                                 for (clock.p1 = limit->p1.min;
 587                                         clock.p1 <= limit->p1.max; clock.p1++) {
 588                                         int this_err;
 589
 590                                         pineview_clock(refclk, &clock);
 591                                         if (!intel_PLL_is_valid(dev, limit,
 592                                                                 &clock))
 593                                                 continue;
 594                                         if (match_clock &&
 595                                             clock.p != match_clock->p)
 596                                                 continue;
 597
 598                                         this_err = abs(clock.dot - target);
 599                                         if (this_err < err) {
 600                                                 *best_clock = clock;
 601                                                 err = this_err;
 602                                         }
 603                                 }
 604                         }
 605                 }
 606         }
 607
 608         return (err != target);
 609 }
 610
 611 static bool
 612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 613                    int target, int refclk, intel_clock_t *match_clock,
 614                    intel_clock_t *best_clock)
 615 {
 616         struct drm_device *dev = crtc->dev;
 617         intel_clock_t clock;
 618         int max_n;
 619         bool found;
 620         /* approximately equals target * 0.00585 */
 621         int err_most = (target >> 8) + (target >> 9);
 622         found = false;
 623
 624         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 625                 if (intel_is_dual_link_lvds(dev))
 626                         clock.p2 = limit->p2.p2_fast;
 627                 else
 628                         clock.p2 = limit->p2.p2_slow;
 629         } else {
 630                 if (target < limit->p2.dot_limit)
 631                         clock.p2 = limit->p2.p2_slow;
 632                 else
 633                         clock.p2 = limit->p2.p2_fast;
 634         }
 635
 636         memset(best_clock, 0, sizeof(*best_clock));
 637         max_n = limit->n.max;
 638         /* based on hardware requirement, prefer smaller n to precision */
 639         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 640                 /* based on hardware requirement, prefere larger m1,m2 */
 641                 for (clock.m1 = limit->m1.max;
 642                      clock.m1 >= limit->m1.min; clock.m1--) {
 643                         for (clock.m2 = limit->m2.max;
 644                              clock.m2 >= limit->m2.min; clock.m2--) {
 645                                 for (clock.p1 = limit->p1.max;
 646                                      clock.p1 >= limit->p1.min; clock.p1--) {
 647                                         int this_err;
 648
 649                                         i9xx_clock(refclk, &clock);
 650                                         if (!intel_PLL_is_valid(dev, limit,
 651                                                                 &clock))
 652                                                 continue;
 653
 654                                         this_err = abs(clock.dot - target);
 655                                         if (this_err < err_most) {
 656                                                 *best_clock = clock;
 657                                                 err_most = this_err;
 658                                                 max_n = clock.n;
 659                                                 found = true;
 660                                         }
 661                                 }
 662                         }
 663                 }
 664         }
 665         return found;
 666 }
 667
 668 static bool
 669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                    int target, int refclk, intel_clock_t *match_clock,
 671                    intel_clock_t *best_clock)
 672 {
 673         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 674         u32 m, n, fastclk;
 675         u32 updrate, minupdate, p;
 676         unsigned long bestppm, ppm, absppm;
 677         int dotclk, flag;
 678
 679         flag = 0;
 680         dotclk = target * 1000;
 681         bestppm = 1000000;
 682         ppm = absppm = 0;
 683         fastclk = dotclk / (2*100);
 684         updrate = 0;
 685         minupdate = 19200;
 686         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 687         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 688
 689         /* based on hardware requirement, prefer smaller n to precision */
 690         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 691                 updrate = refclk / n;
 692                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 693                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 694                                 if (p2 > 10)
 695                                         p2 = p2 - 1;
 696                                 p = p1 * p2;
 697                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 698                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 699                                         m2 = (((2*(fastclk * p * n / m1 )) +
 700                                                refclk) / (2*refclk));
 701                                         m = m1 * m2;
 702                                         vco = updrate * m;
 703                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 704                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 705                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 706                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 707                                                         bestppm = 0;
 708                                                         flag = 1;
 709                                                 }
 710                                                 if (absppm < bestppm - 10) {
 711                                                         bestppm = absppm;
 712                                                         flag = 1;
 713                                                 }
 714                                                 if (flag) {
 715                                                         bestn = n;
 716                                                         bestm1 = m1;
 717                                                         bestm2 = m2;
 718                                                         bestp1 = p1;
 719                                                         bestp2 = p2;
 720                                                         flag = 0;
 721                                                 }
 722                                         }
 723                                 }
 724                         }
 725                 }
 726         }
 727         best_clock->n = bestn;
 728         best_clock->m1 = bestm1;
 729         best_clock->m2 = bestm2;
 730         best_clock->p1 = bestp1;
 731         best_clock->p2 = bestp2;
 732
 733         return true;
 734 }
 735
 736 bool intel_crtc_active(struct drm_crtc *crtc)
 737 {
 738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 739
 740         /* Be paranoid as we can arrive here with only partial
 741          * state retrieved from the hardware during setup.
 742          *
 743          * We can ditch the adjusted_mode.clock check as soon
 744          * as Haswell has gained clock readout/fastboot support.
 745          *
 746          * We can ditch the crtc->fb check as soon as we can
 747          * properly reconstruct framebuffers.
 748          */
 749         return intel_crtc->active && crtc->fb &&
 750                 intel_crtc->config.adjusted_mode.clock;
 751 }
 752
 753 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 754                                              enum pipe pipe)
 755 {
 756         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 758
 759         return intel_crtc->config.cpu_transcoder;
 760 }
 761
 762 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 763 {
 764         struct drm_i915_private *dev_priv = dev->dev_private;
 765         u32 frame, frame_reg = PIPEFRAME(pipe);
 766
 767         frame = I915_READ(frame_reg);
 768
 769         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 770                 DRM_DEBUG_KMS("vblank wait timed out\n");
 771 }
 772
 773 /**
 774  * intel_wait_for_vblank - wait for vblank on a given pipe
 775  * @dev: drm device
 776  * @pipe: pipe to wait for
 777  *
 778  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 779  * mode setting code.
 780  */
 781 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 782 {
 783         struct drm_i915_private *dev_priv = dev->dev_private;
 784         int pipestat_reg = PIPESTAT(pipe);
 785
 786         if (INTEL_INFO(dev)->gen >= 5) {
 787                 ironlake_wait_for_vblank(dev, pipe);
 788                 return;
 789         }
 790
 791         /* Clear existing vblank status. Note this will clear any other
 792          * sticky status fields as well.
 793          *
 794          * This races with i915_driver_irq_handler() with the result
 795          * that either function could miss a vblank event.  Here it is not
 796          * fatal, as we will either wait upon the next vblank interrupt or
 797          * timeout.  Generally speaking intel_wait_for_vblank() is only
 798          * called during modeset at which time the GPU should be idle and
 799          * should *not* be performing page flips and thus not waiting on
 800          * vblanks...
 801          * Currently, the result of us stealing a vblank from the irq
 802          * handler is that a single frame will be skipped during swapbuffers.
 803          */
 804         I915_WRITE(pipestat_reg,
 805                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 806
 807         /* Wait for vblank interrupt bit to set */
 808         if (wait_for(I915_READ(pipestat_reg) &
 809                      PIPE_VBLANK_INTERRUPT_STATUS,
 810                      50))
 811                 DRM_DEBUG_KMS("vblank wait timed out\n");
 812 }
 813
 814 /*
 815  * intel_wait_for_pipe_off - wait for pipe to turn off
 816  * @dev: drm device
 817  * @pipe: pipe to wait for
 818  *
 819  * After disabling a pipe, we can't wait for vblank in the usual way,
 820  * spinning on the vblank interrupt status bit, since we won't actually
 821  * see an interrupt when the pipe is disabled.
 822  *
 823  * On Gen4 and above:
 824  *   wait for the pipe register state bit to turn off
 825  *
 826  * Otherwise:
 827  *   wait for the display line value to settle (it usually
 828  *   ends up stopping at the start of the next frame).
 829  *
 830  */
 831 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 832 {
 833         struct drm_i915_private *dev_priv = dev->dev_private;
 834         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 835                                                                       pipe);
 836
 837         if (INTEL_INFO(dev)->gen >= 4) {
 838                 int reg = PIPECONF(cpu_transcoder);
 839
 840                 /* Wait for the Pipe State to go off */
 841                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 842                              100))
 843                         WARN(1, "pipe_off wait timed out\n");
 844         } else {
 845                 u32 last_line, line_mask;
 846                 int reg = PIPEDSL(pipe);
 847                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 848
 849                 if (IS_GEN2(dev))
 850                         line_mask = DSL_LINEMASK_GEN2;
 851                 else
 852                         line_mask = DSL_LINEMASK_GEN3;
 853
 854                 /* Wait for the display line to settle */
 855                 do {
 856                         last_line = I915_READ(reg) & line_mask;
 857                         mdelay(5);
 858                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 859                          time_after(timeout, jiffies));
 860                 if (time_after(jiffies, timeout))
 861                         WARN(1, "pipe_off wait timed out\n");
 862         }
 863 }
 864
 865 /*
 866  * ibx_digital_port_connected - is the specified port connected?
 867  * @dev_priv: i915 private structure
 868  * @port: the port to test
 869  *
 870  * Returns true if @port is connected, false otherwise.
 871  */
 872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 873                                 struct intel_digital_port *port)
 874 {
 875         u32 bit;
 876
 877         if (HAS_PCH_IBX(dev_priv->dev)) {
 878                 switch(port->port) {
 879                 case PORT_B:
 880                         bit = SDE_PORTB_HOTPLUG;
 881                         break;
 882                 case PORT_C:
 883                         bit = SDE_PORTC_HOTPLUG;
 884                         break;
 885                 case PORT_D:
 886                         bit = SDE_PORTD_HOTPLUG;
 887                         break;
 888                 default:
 889                         return true;
 890                 }
 891         } else {
 892                 switch(port->port) {
 893                 case PORT_B:
 894                         bit = SDE_PORTB_HOTPLUG_CPT;
 895                         break;
 896                 case PORT_C:
 897                         bit = SDE_PORTC_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_D:
 900                         bit = SDE_PORTD_HOTPLUG_CPT;
 901                         break;
 902                 default:
 903                         return true;
 904                 }
 905         }
 906
 907         return I915_READ(SDEISR) & bit;
 908 }
 909
 910 static const char *state_string(bool enabled)
 911 {
 912         return enabled ? "on" : "off";
 913 }
 914
 915 /* Only for pre-ILK configs */
 916 void assert_pll(struct drm_i915_private *dev_priv,
 917                 enum pipe pipe, bool state)
 918 {
 919         int reg;
 920         u32 val;
 921         bool cur_state;
 922
 923         reg = DPLL(pipe);
 924         val = I915_READ(reg);
 925         cur_state = !!(val & DPLL_VCO_ENABLE);
 926         WARN(cur_state != state,
 927              "PLL state assertion failure (expected %s, current %s)\n",
 928              state_string(state), state_string(cur_state));
 929 }
 930
 931 /* XXX: the dsi pll is shared between MIPI DSI ports */
 932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 933 {
 934         u32 val;
 935         bool cur_state;
 936
 937         mutex_lock(&dev_priv->dpio_lock);
 938         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 939         mutex_unlock(&dev_priv->dpio_lock);
 940
 941         cur_state = val & DSI_PLL_VCO_EN;
 942         WARN(cur_state != state,
 943              "DSI PLL state assertion failure (expected %s, current %s)\n",
 944              state_string(state), state_string(cur_state));
 945 }
 946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 948
 949 struct intel_shared_dpll *
 950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 951 {
 952         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 953
 954         if (crtc->config.shared_dpll < 0)
 955                 return NULL;
 956
 957         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 958 }
 959
 960 /* For ILK+ */
 961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 962                         struct intel_shared_dpll *pll,
 963                         bool state)
 964 {
 965         bool cur_state;
 966         struct intel_dpll_hw_state hw_state;
 967
 968         if (HAS_PCH_LPT(dev_priv->dev)) {
 969                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 970                 return;
 971         }
 972
 973         if (WARN (!pll,
 974                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 975                 return;
 976
 977         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 978         WARN(cur_state != state,
 979              "%s assertion failure (expected %s, current %s)\n",
 980              pll->name, state_string(state), state_string(cur_state));
 981 }
 982
 983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 984                           enum pipe pipe, bool state)
 985 {
 986         int reg;
 987         u32 val;
 988         bool cur_state;
 989         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 990                                                                       pipe);
 991
 992         if (HAS_DDI(dev_priv->dev)) {
 993                 /* DDI does not have a specific FDI_TX register */
 994                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 995                 val = I915_READ(reg);
 996                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 997         } else {
 998                 reg = FDI_TX_CTL(pipe);
 999                 val = I915_READ(reg);
1000                 cur_state = !!(val & FDI_TX_ENABLE);
1001         }
1002         WARN(cur_state != state,
1003              "FDI TX state assertion failure (expected %s, current %s)\n",
1004              state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010                           enum pipe pipe, bool state)
1011 {
1012         int reg;
1013         u32 val;
1014         bool cur_state;
1015
1016         reg = FDI_RX_CTL(pipe);
1017         val = I915_READ(reg);
1018         cur_state = !!(val & FDI_RX_ENABLE);
1019         WARN(cur_state != state,
1020              "FDI RX state assertion failure (expected %s, current %s)\n",
1021              state_string(state), state_string(cur_state));
1022 }
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027                                       enum pipe pipe)
1028 {
1029         int reg;
1030         u32 val;
1031
1032         /* ILK FDI PLL is always enabled */
1033         if (dev_priv->info->gen == 5)
1034                 return;
1035
1036         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037         if (HAS_DDI(dev_priv->dev))
1038                 return;
1039
1040         reg = FDI_TX_CTL(pipe);
1041         val = I915_READ(reg);
1042         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043 }
1044
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046                        enum pipe pipe, bool state)
1047 {
1048         int reg;
1049         u32 val;
1050         bool cur_state;
1051
1052         reg = FDI_RX_CTL(pipe);
1053         val = I915_READ(reg);
1054         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055         WARN(cur_state != state,
1056              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057              state_string(state), state_string(cur_state));
1058 }
1059
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061                                   enum pipe pipe)
1062 {
1063         int pp_reg, lvds_reg;
1064         u32 val;
1065         enum pipe panel_pipe = PIPE_A;
1066         bool locked = true;
1067
1068         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069                 pp_reg = PCH_PP_CONTROL;
1070                 lvds_reg = PCH_LVDS;
1071         } else {
1072                 pp_reg = PP_CONTROL;
1073                 lvds_reg = LVDS;
1074         }
1075
1076         val = I915_READ(pp_reg);
1077         if (!(val & PANEL_POWER_ON) ||
1078             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079                 locked = false;
1080
1081         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082                 panel_pipe = PIPE_B;
1083
1084         WARN(panel_pipe == pipe && locked,
1085              "panel assertion failure, pipe %c regs locked\n",
1086              pipe_name(pipe));
1087 }
1088
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090                           enum pipe pipe, bool state)
1091 {
1092         struct drm_device *dev = dev_priv->dev;
1093         bool cur_state;
1094
1095         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097         else if (IS_845G(dev) || IS_I865G(dev))
1098                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099         else
1100                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102         WARN(cur_state != state,
1103              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104              pipe_name(pipe), state_string(state), state_string(cur_state));
1105 }
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110                  enum pipe pipe, bool state)
1111 {
1112         int reg;
1113         u32 val;
1114         bool cur_state;
1115         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116                                                                       pipe);
1117
1118         /* if we need the pipe A quirk it must be always on */
1119         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120                 state = true;
1121
1122         if (!intel_display_power_enabled(dev_priv->dev,
1123                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1124                 cur_state = false;
1125         } else {
1126                 reg = PIPECONF(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & PIPECONF_ENABLE);
1129         }
1130
1131         WARN(cur_state != state,
1132              "pipe %c assertion failure (expected %s, current %s)\n",
1133              pipe_name(pipe), state_string(state), state_string(cur_state));
1134 }
1135
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137                          enum plane plane, bool state)
1138 {
1139         int reg;
1140         u32 val;
1141         bool cur_state;
1142
1143         reg = DSPCNTR(plane);
1144         val = I915_READ(reg);
1145         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146         WARN(cur_state != state,
1147              "plane %c assertion failure (expected %s, current %s)\n",
1148              plane_name(plane), state_string(state), state_string(cur_state));
1149 }
1150
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155                                    enum pipe pipe)
1156 {
1157         struct drm_device *dev = dev_priv->dev;
1158         int reg, i;
1159         u32 val;
1160         int cur_pipe;
1161
1162         /* Primary planes are fixed to pipes on gen4+ */
1163         if (INTEL_INFO(dev)->gen >= 4) {
1164                 reg = DSPCNTR(pipe);
1165                 val = I915_READ(reg);
1166                 WARN((val & DISPLAY_PLANE_ENABLE),
1167                      "plane %c assertion failure, should be disabled but not\n",
1168                      plane_name(pipe));
1169                 return;
1170         }
1171
1172         /* Need to check both planes against the pipe */
1173         for_each_pipe(i) {
1174                 reg = DSPCNTR(i);
1175                 val = I915_READ(reg);
1176                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177                         DISPPLANE_SEL_PIPE_SHIFT;
1178                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180                      plane_name(i), pipe_name(pipe));
1181         }
1182 }
1183
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185                                     enum pipe pipe)
1186 {
1187         struct drm_device *dev = dev_priv->dev;
1188         int reg, i;
1189         u32 val;
1190
1191         if (IS_VALLEYVIEW(dev)) {
1192                 for (i = 0; i < dev_priv->num_plane; i++) {
1193                         reg = SPCNTR(pipe, i);
1194                         val = I915_READ(reg);
1195                         WARN((val & SP_ENABLE),
1196                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197                              sprite_name(pipe, i), pipe_name(pipe));
1198                 }
1199         } else if (INTEL_INFO(dev)->gen >= 7) {
1200                 reg = SPRCTL(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & SPRITE_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         } else if (INTEL_INFO(dev)->gen >= 5) {
1206                 reg = DVSCNTR(pipe);
1207                 val = I915_READ(reg);
1208                 WARN((val & DVS_ENABLE),
1209                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210                      plane_name(pipe), pipe_name(pipe));
1211         }
1212 }
1213
1214 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215 {
1216         u32 val;
1217         bool enabled;
1218
1219         if (HAS_PCH_LPT(dev_priv->dev)) {
1220                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221                 return;
1222         }
1223
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void vlv_enable_pll(struct intel_crtc *crtc)
1364 {
1365         struct drm_device *dev = crtc->base.dev;
1366         struct drm_i915_private *dev_priv = dev->dev_private;
1367         int reg = DPLL(crtc->pipe);
1368         u32 dpll = crtc->config.dpll_hw_state.dpll;
1369
1370         assert_pipe_disabled(dev_priv, crtc->pipe);
1371
1372         /* No really, not for ILK+ */
1373         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1374
1375         /* PLL is protected by panel, make sure we can write it */
1376         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1377                 assert_panel_unlocked(dev_priv, crtc->pipe);
1378
1379         I915_WRITE(reg, dpll);
1380         POSTING_READ(reg);
1381         udelay(150);
1382
1383         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1384                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1385
1386         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1387         POSTING_READ(DPLL_MD(crtc->pipe));
1388
1389         /* We do this three times for luck */
1390         I915_WRITE(reg, dpll);
1391         POSTING_READ(reg);
1392         udelay(150); /* wait for warmup */
1393         I915_WRITE(reg, dpll);
1394         POSTING_READ(reg);
1395         udelay(150); /* wait for warmup */
1396         I915_WRITE(reg, dpll);
1397         POSTING_READ(reg);
1398         udelay(150); /* wait for warmup */
1399 }
1400
1401 static void i9xx_enable_pll(struct intel_crtc *crtc)
1402 {
1403         struct drm_device *dev = crtc->base.dev;
1404         struct drm_i915_private *dev_priv = dev->dev_private;
1405         int reg = DPLL(crtc->pipe);
1406         u32 dpll = crtc->config.dpll_hw_state.dpll;
1407
1408         assert_pipe_disabled(dev_priv, crtc->pipe);
1409
1410         /* No really, not for ILK+ */
1411         BUG_ON(dev_priv->info->gen >= 5);
1412
1413         /* PLL is protected by panel, make sure we can write it */
1414         if (IS_MOBILE(dev) && !IS_I830(dev))
1415                 assert_panel_unlocked(dev_priv, crtc->pipe);
1416
1417         I915_WRITE(reg, dpll);
1418
1419         /* Wait for the clocks to stabilize. */
1420         POSTING_READ(reg);
1421         udelay(150);
1422
1423         if (INTEL_INFO(dev)->gen >= 4) {
1424                 I915_WRITE(DPLL_MD(crtc->pipe),
1425                            crtc->config.dpll_hw_state.dpll_md);
1426         } else {
1427                 /* The pixel multiplier can only be updated once the
1428                  * DPLL is enabled and the clocks are stable.
1429                  *
1430                  * So write it again.
1431                  */
1432                 I915_WRITE(reg, dpll);
1433         }
1434
1435         /* We do this three times for luck */
1436         I915_WRITE(reg, dpll);
1437         POSTING_READ(reg);
1438         udelay(150); /* wait for warmup */
1439         I915_WRITE(reg, dpll);
1440         POSTING_READ(reg);
1441         udelay(150); /* wait for warmup */
1442         I915_WRITE(reg, dpll);
1443         POSTING_READ(reg);
1444         udelay(150); /* wait for warmup */
1445 }
1446
1447 /**
1448  * i9xx_disable_pll - disable a PLL
1449  * @dev_priv: i915 private structure
1450  * @pipe: pipe PLL to disable
1451  *
1452  * Disable the PLL for @pipe, making sure the pipe is off first.
1453  *
1454  * Note!  This is for pre-ILK only.
1455  */
1456 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1457 {
1458         /* Don't disable pipe A or pipe A PLLs if needed */
1459         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1460                 return;
1461
1462         /* Make sure the pipe isn't still relying on us */
1463         assert_pipe_disabled(dev_priv, pipe);
1464
1465         I915_WRITE(DPLL(pipe), 0);
1466         POSTING_READ(DPLL(pipe));
1467 }
1468
1469 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1470 {
1471         u32 port_mask;
1472
1473         if (!port)
1474                 port_mask = DPLL_PORTB_READY_MASK;
1475         else
1476                 port_mask = DPLL_PORTC_READY_MASK;
1477
1478         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1479                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1480                      'B' + port, I915_READ(DPLL(0)));
1481 }
1482
1483 /**
1484  * ironlake_enable_shared_dpll - enable PCH PLL
1485  * @dev_priv: i915 private structure
1486  * @pipe: pipe PLL to enable
1487  *
1488  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1489  * drives the transcoder clock.
1490  */
1491 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1492 {
1493         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1494         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1495
1496         /* PCH PLLs only available on ILK, SNB and IVB */
1497         BUG_ON(dev_priv->info->gen < 5);
1498         if (WARN_ON(pll == NULL))
1499                 return;
1500
1501         if (WARN_ON(pll->refcount == 0))
1502                 return;
1503
1504         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1505                       pll->name, pll->active, pll->on,
1506                       crtc->base.base.id);
1507
1508         if (pll->active++) {
1509                 WARN_ON(!pll->on);
1510                 assert_shared_dpll_enabled(dev_priv, pll);
1511                 return;
1512         }
1513         WARN_ON(pll->on);
1514
1515         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1516         pll->enable(dev_priv, pll);
1517         pll->on = true;
1518 }
1519
1520 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1521 {
1522         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1523         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1524
1525         /* PCH only available on ILK+ */
1526         BUG_ON(dev_priv->info->gen < 5);
1527         if (WARN_ON(pll == NULL))
1528                return;
1529
1530         if (WARN_ON(pll->refcount == 0))
1531                 return;
1532
1533         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1534                       pll->name, pll->active, pll->on,
1535                       crtc->base.base.id);
1536
1537         if (WARN_ON(pll->active == 0)) {
1538                 assert_shared_dpll_disabled(dev_priv, pll);
1539                 return;
1540         }
1541
1542         assert_shared_dpll_enabled(dev_priv, pll);
1543         WARN_ON(!pll->on);
1544         if (--pll->active)
1545                 return;
1546
1547         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1548         pll->disable(dev_priv, pll);
1549         pll->on = false;
1550 }
1551
1552 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1553                                            enum pipe pipe)
1554 {
1555         struct drm_device *dev = dev_priv->dev;
1556         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1558         uint32_t reg, val, pipeconf_val;
1559
1560         /* PCH only available on ILK+ */
1561         BUG_ON(dev_priv->info->gen < 5);
1562
1563         /* Make sure PCH DPLL is enabled */
1564         assert_shared_dpll_enabled(dev_priv,
1565                                    intel_crtc_to_shared_dpll(intel_crtc));
1566
1567         /* FDI must be feeding us bits for PCH ports */
1568         assert_fdi_tx_enabled(dev_priv, pipe);
1569         assert_fdi_rx_enabled(dev_priv, pipe);
1570
1571         if (HAS_PCH_CPT(dev)) {
1572                 /* Workaround: Set the timing override bit before enabling the
1573                  * pch transcoder. */
1574                 reg = TRANS_CHICKEN2(pipe);
1575                 val = I915_READ(reg);
1576                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1577                 I915_WRITE(reg, val);
1578         }
1579
1580         reg = PCH_TRANSCONF(pipe);
1581         val = I915_READ(reg);
1582         pipeconf_val = I915_READ(PIPECONF(pipe));
1583
1584         if (HAS_PCH_IBX(dev_priv->dev)) {
1585                 /*
1586                  * make the BPC in transcoder be consistent with
1587                  * that in pipeconf reg.
1588                  */
1589                 val &= ~PIPECONF_BPC_MASK;
1590                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1591         }
1592
1593         val &= ~TRANS_INTERLACE_MASK;
1594         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1595                 if (HAS_PCH_IBX(dev_priv->dev) &&
1596                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1597                         val |= TRANS_LEGACY_INTERLACED_ILK;
1598                 else
1599                         val |= TRANS_INTERLACED;
1600         else
1601                 val |= TRANS_PROGRESSIVE;
1602
1603         I915_WRITE(reg, val | TRANS_ENABLE);
1604         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1605                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1606 }
1607
1608 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1609                                       enum transcoder cpu_transcoder)
1610 {
1611         u32 val, pipeconf_val;
1612
1613         /* PCH only available on ILK+ */
1614         BUG_ON(dev_priv->info->gen < 5);
1615
1616         /* FDI must be feeding us bits for PCH ports */
1617         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1618         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1619
1620         /* Workaround: set timing override bit. */
1621         val = I915_READ(_TRANSA_CHICKEN2);
1622         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1623         I915_WRITE(_TRANSA_CHICKEN2, val);
1624
1625         val = TRANS_ENABLE;
1626         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1627
1628         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1629             PIPECONF_INTERLACED_ILK)
1630                 val |= TRANS_INTERLACED;
1631         else
1632                 val |= TRANS_PROGRESSIVE;
1633
1634         I915_WRITE(LPT_TRANSCONF, val);
1635         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1636                 DRM_ERROR("Failed to enable PCH transcoder\n");
1637 }
1638
1639 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1640                                             enum pipe pipe)
1641 {
1642         struct drm_device *dev = dev_priv->dev;
1643         uint32_t reg, val;
1644
1645         /* FDI relies on the transcoder */
1646         assert_fdi_tx_disabled(dev_priv, pipe);
1647         assert_fdi_rx_disabled(dev_priv, pipe);
1648
1649         /* Ports must be off as well */
1650         assert_pch_ports_disabled(dev_priv, pipe);
1651
1652         reg = PCH_TRANSCONF(pipe);
1653         val = I915_READ(reg);
1654         val &= ~TRANS_ENABLE;
1655         I915_WRITE(reg, val);
1656         /* wait for PCH transcoder off, transcoder state */
1657         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1658                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1659
1660         if (!HAS_PCH_IBX(dev)) {
1661                 /* Workaround: Clear the timing override chicken bit again. */
1662                 reg = TRANS_CHICKEN2(pipe);
1663                 val = I915_READ(reg);
1664                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1665                 I915_WRITE(reg, val);
1666         }
1667 }
1668
1669 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1670 {
1671         u32 val;
1672
1673         val = I915_READ(LPT_TRANSCONF);
1674         val &= ~TRANS_ENABLE;
1675         I915_WRITE(LPT_TRANSCONF, val);
1676         /* wait for PCH transcoder off, transcoder state */
1677         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1678                 DRM_ERROR("Failed to disable PCH transcoder\n");
1679
1680         /* Workaround: clear timing override bit. */
1681         val = I915_READ(_TRANSA_CHICKEN2);
1682         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1683         I915_WRITE(_TRANSA_CHICKEN2, val);
1684 }
1685
1686 /**
1687  * intel_enable_pipe - enable a pipe, asserting requirements
1688  * @dev_priv: i915 private structure
1689  * @pipe: pipe to enable
1690  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1691  *
1692  * Enable @pipe, making sure that various hardware specific requirements
1693  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1694  *
1695  * @pipe should be %PIPE_A or %PIPE_B.
1696  *
1697  * Will wait until the pipe is actually running (i.e. first vblank) before
1698  * returning.
1699  */
1700 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1701                               bool pch_port, bool dsi)
1702 {
1703         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1704                                                                       pipe);
1705         enum pipe pch_transcoder;
1706         int reg;
1707         u32 val;
1708
1709         assert_planes_disabled(dev_priv, pipe);
1710         assert_cursor_disabled(dev_priv, pipe);
1711         assert_sprites_disabled(dev_priv, pipe);
1712
1713         if (HAS_PCH_LPT(dev_priv->dev))
1714                 pch_transcoder = TRANSCODER_A;
1715         else
1716                 pch_transcoder = pipe;
1717
1718         /*
1719          * A pipe without a PLL won't actually be able to drive bits from
1720          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1721          * need the check.
1722          */
1723         if (!HAS_PCH_SPLIT(dev_priv->dev))
1724                 if (dsi)
1725                         assert_dsi_pll_enabled(dev_priv);
1726                 else
1727                         assert_pll_enabled(dev_priv, pipe);
1728         else {
1729                 if (pch_port) {
1730                         /* if driving the PCH, we need FDI enabled */
1731                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1732                         assert_fdi_tx_pll_enabled(dev_priv,
1733                                                   (enum pipe) cpu_transcoder);
1734                 }
1735                 /* FIXME: assert CPU port conditions for SNB+ */
1736         }
1737
1738         reg = PIPECONF(cpu_transcoder);
1739         val = I915_READ(reg);
1740         if (val & PIPECONF_ENABLE)
1741                 return;
1742
1743         I915_WRITE(reg, val | PIPECONF_ENABLE);
1744         intel_wait_for_vblank(dev_priv->dev, pipe);
1745 }
1746
1747 /**
1748  * intel_disable_pipe - disable a pipe, asserting requirements
1749  * @dev_priv: i915 private structure
1750  * @pipe: pipe to disable
1751  *
1752  * Disable @pipe, making sure that various hardware specific requirements
1753  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1754  *
1755  * @pipe should be %PIPE_A or %PIPE_B.
1756  *
1757  * Will wait until the pipe has shut down before returning.
1758  */
1759 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1760                                enum pipe pipe)
1761 {
1762         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763                                                                       pipe);
1764         int reg;
1765         u32 val;
1766
1767         /*
1768          * Make sure planes won't keep trying to pump pixels to us,
1769          * or we might hang the display.
1770          */
1771         assert_planes_disabled(dev_priv, pipe);
1772         assert_cursor_disabled(dev_priv, pipe);
1773         assert_sprites_disabled(dev_priv, pipe);
1774
1775         /* Don't disable pipe A or pipe A PLLs if needed */
1776         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1777                 return;
1778
1779         reg = PIPECONF(cpu_transcoder);
1780         val = I915_READ(reg);
1781         if ((val & PIPECONF_ENABLE) == 0)
1782                 return;
1783
1784         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1785         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1786 }
1787
1788 /*
1789  * Plane regs are double buffered, going from enabled->disabled needs a
1790  * trigger in order to latch.  The display address reg provides this.
1791  */
1792 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1793                                       enum plane plane)
1794 {
1795         if (dev_priv->info->gen >= 4)
1796                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1797         else
1798                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1799 }
1800
1801 /**
1802  * intel_enable_plane - enable a display plane on a given pipe
1803  * @dev_priv: i915 private structure
1804  * @plane: plane to enable
1805  * @pipe: pipe being fed
1806  *
1807  * Enable @plane on @pipe, making sure that @pipe is running first.
1808  */
1809 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1810                                enum plane plane, enum pipe pipe)
1811 {
1812         int reg;
1813         u32 val;
1814
1815         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1816         assert_pipe_enabled(dev_priv, pipe);
1817
1818         reg = DSPCNTR(plane);
1819         val = I915_READ(reg);
1820         if (val & DISPLAY_PLANE_ENABLE)
1821                 return;
1822
1823         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1824         intel_flush_display_plane(dev_priv, plane);
1825         intel_wait_for_vblank(dev_priv->dev, pipe);
1826 }
1827
1828 /**
1829  * intel_disable_plane - disable a display plane
1830  * @dev_priv: i915 private structure
1831  * @plane: plane to disable
1832  * @pipe: pipe consuming the data
1833  *
1834  * Disable @plane; should be an independent operation.
1835  */
1836 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1837                                 enum plane plane, enum pipe pipe)
1838 {
1839         int reg;
1840         u32 val;
1841
1842         reg = DSPCNTR(plane);
1843         val = I915_READ(reg);
1844         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1845                 return;
1846
1847         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1848         intel_flush_display_plane(dev_priv, plane);
1849         intel_wait_for_vblank(dev_priv->dev, pipe);
1850 }
1851
1852 static bool need_vtd_wa(struct drm_device *dev)
1853 {
1854 #ifdef CONFIG_INTEL_IOMMU
1855         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1856                 return true;
1857 #endif
1858         return false;
1859 }
1860
1861 int
1862 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1863                            struct drm_i915_gem_object *obj,
1864                            struct intel_ring_buffer *pipelined)
1865 {
1866         struct drm_i915_private *dev_priv = dev->dev_private;
1867         u32 alignment;
1868         int ret;
1869
1870         switch (obj->tiling_mode) {
1871         case I915_TILING_NONE:
1872                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1873                         alignment = 128 * 1024;
1874                 else if (INTEL_INFO(dev)->gen >= 4)
1875                         alignment = 4 * 1024;
1876                 else
1877                         alignment = 64 * 1024;
1878                 break;
1879         case I915_TILING_X:
1880                 /* pin() will align the object as required by fence */
1881                 alignment = 0;
1882                 break;
1883         case I915_TILING_Y:
1884                 /* Despite that we check this in framebuffer_init userspace can
1885                  * screw us over and change the tiling after the fact. Only
1886                  * pinned buffers can't change their tiling. */
1887                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1888                 return -EINVAL;
1889         default:
1890                 BUG();
1891         }
1892
1893         /* Note that the w/a also requires 64 PTE of padding following the
1894          * bo. We currently fill all unused PTE with the shadow page and so
1895          * we should always have valid PTE following the scanout preventing
1896          * the VT-d warning.
1897          */
1898         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1899                 alignment = 256 * 1024;
1900
1901         dev_priv->mm.interruptible = false;
1902         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1903         if (ret)
1904                 goto err_interruptible;
1905
1906         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1907          * fence, whereas 965+ only requires a fence if using
1908          * framebuffer compression.  For simplicity, we always install
1909          * a fence as the cost is not that onerous.
1910          */
1911         ret = i915_gem_object_get_fence(obj);
1912         if (ret)
1913                 goto err_unpin;
1914
1915         i915_gem_object_pin_fence(obj);
1916
1917         dev_priv->mm.interruptible = true;
1918         return 0;
1919
1920 err_unpin:
1921         i915_gem_object_unpin_from_display_plane(obj);
1922 err_interruptible:
1923         dev_priv->mm.interruptible = true;
1924         return ret;
1925 }
1926
1927 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1928 {
1929         i915_gem_object_unpin_fence(obj);
1930         i915_gem_object_unpin_from_display_plane(obj);
1931 }
1932
1933 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1934  * is assumed to be a power-of-two. */
1935 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1936                                              unsigned int tiling_mode,
1937                                              unsigned int cpp,
1938                                              unsigned int pitch)
1939 {
1940         if (tiling_mode != I915_TILING_NONE) {
1941                 unsigned int tile_rows, tiles;
1942
1943                 tile_rows = *y / 8;
1944                 *y %= 8;
1945
1946                 tiles = *x / (512/cpp);
1947                 *x %= 512/cpp;
1948
1949                 return tile_rows * pitch * 8 + tiles * 4096;
1950         } else {
1951                 unsigned int offset;
1952
1953                 offset = *y * pitch + *x * cpp;
1954                 *y = 0;
1955                 *x = (offset & 4095) / cpp;
1956                 return offset & -4096;
1957         }
1958 }
1959
1960 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1961                              int x, int y)
1962 {
1963         struct drm_device *dev = crtc->dev;
1964         struct drm_i915_private *dev_priv = dev->dev_private;
1965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966         struct intel_framebuffer *intel_fb;
1967         struct drm_i915_gem_object *obj;
1968         int plane = intel_crtc->plane;
1969         unsigned long linear_offset;
1970         u32 dspcntr;
1971         u32 reg;
1972
1973         switch (plane) {
1974         case 0:
1975         case 1:
1976                 break;
1977         default:
1978                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1979                 return -EINVAL;
1980         }
1981
1982         intel_fb = to_intel_framebuffer(fb);
1983         obj = intel_fb->obj;
1984
1985         reg = DSPCNTR(plane);
1986         dspcntr = I915_READ(reg);
1987         /* Mask out pixel format bits in case we change it */
1988         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1989         switch (fb->pixel_format) {
1990         case DRM_FORMAT_C8:
1991                 dspcntr |= DISPPLANE_8BPP;
1992                 break;
1993         case DRM_FORMAT_XRGB1555:
1994         case DRM_FORMAT_ARGB1555:
1995                 dspcntr |= DISPPLANE_BGRX555;
1996                 break;
1997         case DRM_FORMAT_RGB565:
1998                 dspcntr |= DISPPLANE_BGRX565;
1999                 break;
2000         case DRM_FORMAT_XRGB8888:
2001         case DRM_FORMAT_ARGB8888:
2002                 dspcntr |= DISPPLANE_BGRX888;
2003                 break;
2004         case DRM_FORMAT_XBGR8888:
2005         case DRM_FORMAT_ABGR8888:
2006                 dspcntr |= DISPPLANE_RGBX888;
2007                 break;
2008         case DRM_FORMAT_XRGB2101010:
2009         case DRM_FORMAT_ARGB2101010:
2010                 dspcntr |= DISPPLANE_BGRX101010;
2011                 break;
2012         case DRM_FORMAT_XBGR2101010:
2013         case DRM_FORMAT_ABGR2101010:
2014                 dspcntr |= DISPPLANE_RGBX101010;
2015                 break;
2016         default:
2017                 BUG();
2018         }
2019
2020         if (INTEL_INFO(dev)->gen >= 4) {
2021                 if (obj->tiling_mode != I915_TILING_NONE)
2022                         dspcntr |= DISPPLANE_TILED;
2023                 else
2024                         dspcntr &= ~DISPPLANE_TILED;
2025         }
2026
2027         if (IS_G4X(dev))
2028                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2029
2030         I915_WRITE(reg, dspcntr);
2031
2032         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2033
2034         if (INTEL_INFO(dev)->gen >= 4) {
2035                 intel_crtc->dspaddr_offset =
2036                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2037                                                        fb->bits_per_pixel / 8,
2038                                                        fb->pitches[0]);
2039                 linear_offset -= intel_crtc->dspaddr_offset;
2040         } else {
2041                 intel_crtc->dspaddr_offset = linear_offset;
2042         }
2043
2044         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2045                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2046                       fb->pitches[0]);
2047         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2048         if (INTEL_INFO(dev)->gen >= 4) {
2049                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2050                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2051                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2052                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2053         } else
2054                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2055         POSTING_READ(reg);
2056
2057         return 0;
2058 }
2059
2060 static int ironlake_update_plane(struct drm_crtc *crtc,
2061                                  struct drm_framebuffer *fb, int x, int y)
2062 {
2063         struct drm_device *dev = crtc->dev;
2064         struct drm_i915_private *dev_priv = dev->dev_private;
2065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2066         struct intel_framebuffer *intel_fb;
2067         struct drm_i915_gem_object *obj;
2068         int plane = intel_crtc->plane;
2069         unsigned long linear_offset;
2070         u32 dspcntr;
2071         u32 reg;
2072
2073         switch (plane) {
2074         case 0:
2075         case 1:
2076         case 2:
2077                 break;
2078         default:
2079                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2080                 return -EINVAL;
2081         }
2082
2083         intel_fb = to_intel_framebuffer(fb);
2084         obj = intel_fb->obj;
2085
2086         reg = DSPCNTR(plane);
2087         dspcntr = I915_READ(reg);
2088         /* Mask out pixel format bits in case we change it */
2089         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2090         switch (fb->pixel_format) {
2091         case DRM_FORMAT_C8:
2092                 dspcntr |= DISPPLANE_8BPP;
2093                 break;
2094         case DRM_FORMAT_RGB565:
2095                 dspcntr |= DISPPLANE_BGRX565;
2096                 break;
2097         case DRM_FORMAT_XRGB8888:
2098         case DRM_FORMAT_ARGB8888:
2099                 dspcntr |= DISPPLANE_BGRX888;
2100                 break;
2101         case DRM_FORMAT_XBGR8888:
2102         case DRM_FORMAT_ABGR8888:
2103                 dspcntr |= DISPPLANE_RGBX888;
2104                 break;
2105         case DRM_FORMAT_XRGB2101010:
2106         case DRM_FORMAT_ARGB2101010:
2107                 dspcntr |= DISPPLANE_BGRX101010;
2108                 break;
2109         case DRM_FORMAT_XBGR2101010:
2110         case DRM_FORMAT_ABGR2101010:
2111                 dspcntr |= DISPPLANE_RGBX101010;
2112                 break;
2113         default:
2114                 BUG();
2115         }
2116
2117         if (obj->tiling_mode != I915_TILING_NONE)
2118                 dspcntr |= DISPPLANE_TILED;
2119         else
2120                 dspcntr &= ~DISPPLANE_TILED;
2121
2122         if (IS_HASWELL(dev))
2123                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2124         else
2125                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2126
2127         I915_WRITE(reg, dspcntr);
2128
2129         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2130         intel_crtc->dspaddr_offset =
2131                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2132                                                fb->bits_per_pixel / 8,
2133                                                fb->pitches[0]);
2134         linear_offset -= intel_crtc->dspaddr_offset;
2135
2136         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2138                       fb->pitches[0]);
2139         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2140         I915_MODIFY_DISPBASE(DSPSURF(plane),
2141                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2142         if (IS_HASWELL(dev)) {
2143                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2144         } else {
2145                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2146                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2147         }
2148         POSTING_READ(reg);
2149
2150         return 0;
2151 }
2152
2153 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2154 static int
2155 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2156                            int x, int y, enum mode_set_atomic state)
2157 {
2158         struct drm_device *dev = crtc->dev;
2159         struct drm_i915_private *dev_priv = dev->dev_private;
2160
2161         if (dev_priv->display.disable_fbc)
2162                 dev_priv->display.disable_fbc(dev);
2163         intel_increase_pllclock(crtc);
2164
2165         return dev_priv->display.update_plane(crtc, fb, x, y);
2166 }
2167
2168 void intel_display_handle_reset(struct drm_device *dev)
2169 {
2170         struct drm_i915_private *dev_priv = dev->dev_private;
2171         struct drm_crtc *crtc;
2172
2173         /*
2174          * Flips in the rings have been nuked by the reset,
2175          * so complete all pending flips so that user space
2176          * will get its events and not get stuck.
2177          *
2178          * Also update the base address of all primary
2179          * planes to the the last fb to make sure we're
2180          * showing the correct fb after a reset.
2181          *
2182          * Need to make two loops over the crtcs so that we
2183          * don't try to grab a crtc mutex before the
2184          * pending_flip_queue really got woken up.
2185          */
2186
2187         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2188                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2189                 enum plane plane = intel_crtc->plane;
2190
2191                 intel_prepare_page_flip(dev, plane);
2192                 intel_finish_page_flip_plane(dev, plane);
2193         }
2194
2195         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2196                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2197
2198                 mutex_lock(&crtc->mutex);
2199                 if (intel_crtc->active)
2200                         dev_priv->display.update_plane(crtc, crtc->fb,
2201                                                        crtc->x, crtc->y);
2202                 mutex_unlock(&crtc->mutex);
2203         }
2204 }
2205
2206 static int
2207 intel_finish_fb(struct drm_framebuffer *old_fb)
2208 {
2209         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2210         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2211         bool was_interruptible = dev_priv->mm.interruptible;
2212         int ret;
2213
2214         /* Big Hammer, we also need to ensure that any pending
2215          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2216          * current scanout is retired before unpinning the old
2217          * framebuffer.
2218          *
2219          * This should only fail upon a hung GPU, in which case we
2220          * can safely continue.
2221          */
2222         dev_priv->mm.interruptible = false;
2223         ret = i915_gem_object_finish_gpu(obj);
2224         dev_priv->mm.interruptible = was_interruptible;
2225
2226         return ret;
2227 }
2228
2229 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2230 {
2231         struct drm_device *dev = crtc->dev;
2232         struct drm_i915_master_private *master_priv;
2233         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235         if (!dev->primary->master)
2236                 return;
2237
2238         master_priv = dev->primary->master->driver_priv;
2239         if (!master_priv->sarea_priv)
2240                 return;
2241
2242         switch (intel_crtc->pipe) {
2243         case 0:
2244                 master_priv->sarea_priv->pipeA_x = x;
2245                 master_priv->sarea_priv->pipeA_y = y;
2246                 break;
2247         case 1:
2248                 master_priv->sarea_priv->pipeB_x = x;
2249                 master_priv->sarea_priv->pipeB_y = y;
2250                 break;
2251         default:
2252                 break;
2253         }
2254 }
2255
2256 static int
2257 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2258                     struct drm_framebuffer *fb)
2259 {
2260         struct drm_device *dev = crtc->dev;
2261         struct drm_i915_private *dev_priv = dev->dev_private;
2262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2263         struct drm_framebuffer *old_fb;
2264         int ret;
2265
2266         /* no fb bound */
2267         if (!fb) {
2268                 DRM_ERROR("No FB bound\n");
2269                 return 0;
2270         }
2271
2272         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2273                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2274                           plane_name(intel_crtc->plane),
2275                           INTEL_INFO(dev)->num_pipes);
2276                 return -EINVAL;
2277         }
2278
2279         mutex_lock(&dev->struct_mutex);
2280         ret = intel_pin_and_fence_fb_obj(dev,
2281                                          to_intel_framebuffer(fb)->obj,
2282                                          NULL);
2283         if (ret != 0) {
2284                 mutex_unlock(&dev->struct_mutex);
2285                 DRM_ERROR("pin & fence failed\n");
2286                 return ret;
2287         }
2288
2289         /* Update pipe size and adjust fitter if needed */
2290         if (i915_fastboot) {
2291                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2292                            ((crtc->mode.hdisplay - 1) << 16) |
2293                            (crtc->mode.vdisplay - 1));
2294                 if (!intel_crtc->config.pch_pfit.size &&
2295                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2296                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2297                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2298                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2299                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2300                 }
2301         }
2302
2303         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2304         if (ret) {
2305                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2306                 mutex_unlock(&dev->struct_mutex);
2307                 DRM_ERROR("failed to update base address\n");
2308                 return ret;
2309         }
2310
2311         old_fb = crtc->fb;
2312         crtc->fb = fb;
2313         crtc->x = x;
2314         crtc->y = y;
2315
2316         if (old_fb) {
2317                 if (intel_crtc->active && old_fb != fb)
2318                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2319                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2320         }
2321
2322         intel_update_fbc(dev);
2323         intel_edp_psr_update(dev);
2324         mutex_unlock(&dev->struct_mutex);
2325
2326         intel_crtc_update_sarea_pos(crtc, x, y);
2327
2328         return 0;
2329 }
2330
2331 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332 {
2333         struct drm_device *dev = crtc->dev;
2334         struct drm_i915_private *dev_priv = dev->dev_private;
2335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336         int pipe = intel_crtc->pipe;
2337         u32 reg, temp;
2338
2339         /* enable normal train */
2340         reg = FDI_TX_CTL(pipe);
2341         temp = I915_READ(reg);
2342         if (IS_IVYBRIDGE(dev)) {
2343                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2345         } else {
2346                 temp &= ~FDI_LINK_TRAIN_NONE;
2347                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2348         }
2349         I915_WRITE(reg, temp);
2350
2351         reg = FDI_RX_CTL(pipe);
2352         temp = I915_READ(reg);
2353         if (HAS_PCH_CPT(dev)) {
2354                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356         } else {
2357                 temp &= ~FDI_LINK_TRAIN_NONE;
2358                 temp |= FDI_LINK_TRAIN_NONE;
2359         }
2360         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362         /* wait one idle pattern time */
2363         POSTING_READ(reg);
2364         udelay(1000);
2365
2366         /* IVB wants error correction enabled */
2367         if (IS_IVYBRIDGE(dev))
2368                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369                            FDI_FE_ERRC_ENABLE);
2370 }
2371
2372 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373 {
2374         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375 }
2376
2377 static void ivb_modeset_global_resources(struct drm_device *dev)
2378 {
2379         struct drm_i915_private *dev_priv = dev->dev_private;
2380         struct intel_crtc *pipe_B_crtc =
2381                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382         struct intel_crtc *pipe_C_crtc =
2383                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384         uint32_t temp;
2385
2386         /*
2387          * When everything is off disable fdi C so that we could enable fdi B
2388          * with all lanes. Note that we don't care about enabled pipes without
2389          * an enabled pch encoder.
2390          */
2391         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392             !pipe_has_enabled_pch(pipe_C_crtc)) {
2393                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396                 temp = I915_READ(SOUTH_CHICKEN1);
2397                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399                 I915_WRITE(SOUTH_CHICKEN1, temp);
2400         }
2401 }
2402
2403 /* The FDI link training functions for ILK/Ibexpeak. */
2404 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405 {
2406         struct drm_device *dev = crtc->dev;
2407         struct drm_i915_private *dev_priv = dev->dev_private;
2408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409         int pipe = intel_crtc->pipe;
2410         int plane = intel_crtc->plane;
2411         u32 reg, temp, tries;
2412
2413         /* FDI needs bits from pipe & plane first */
2414         assert_pipe_enabled(dev_priv, pipe);
2415         assert_plane_enabled(dev_priv, plane);
2416
2417         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418            for train result */
2419         reg = FDI_RX_IMR(pipe);
2420         temp = I915_READ(reg);
2421         temp &= ~FDI_RX_SYMBOL_LOCK;
2422         temp &= ~FDI_RX_BIT_LOCK;
2423         I915_WRITE(reg, temp);
2424         I915_READ(reg);
2425         udelay(150);
2426
2427         /* enable CPU FDI TX and PCH FDI RX */
2428         reg = FDI_TX_CTL(pipe);
2429         temp = I915_READ(reg);
2430         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2432         temp &= ~FDI_LINK_TRAIN_NONE;
2433         temp |= FDI_LINK_TRAIN_PATTERN_1;
2434         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2435
2436         reg = FDI_RX_CTL(pipe);
2437         temp = I915_READ(reg);
2438         temp &= ~FDI_LINK_TRAIN_NONE;
2439         temp |= FDI_LINK_TRAIN_PATTERN_1;
2440         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442         POSTING_READ(reg);
2443         udelay(150);
2444
2445         /* Ironlake workaround, enable clock pointer after FDI enable*/
2446         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448                    FDI_RX_PHASE_SYNC_POINTER_EN);
2449
2450         reg = FDI_RX_IIR(pipe);
2451         for (tries = 0; tries < 5; tries++) {
2452                 temp = I915_READ(reg);
2453                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455                 if ((temp & FDI_RX_BIT_LOCK)) {
2456                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2457                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2458                         break;
2459                 }
2460         }
2461         if (tries == 5)
2462                 DRM_ERROR("FDI train 1 fail!\n");
2463
2464         /* Train 2 */
2465         reg = FDI_TX_CTL(pipe);
2466         temp = I915_READ(reg);
2467         temp &= ~FDI_LINK_TRAIN_NONE;
2468         temp |= FDI_LINK_TRAIN_PATTERN_2;
2469         I915_WRITE(reg, temp);
2470
2471         reg = FDI_RX_CTL(pipe);
2472         temp = I915_READ(reg);
2473         temp &= ~FDI_LINK_TRAIN_NONE;
2474         temp |= FDI_LINK_TRAIN_PATTERN_2;
2475         I915_WRITE(reg, temp);
2476
2477         POSTING_READ(reg);
2478         udelay(150);
2479
2480         reg = FDI_RX_IIR(pipe);
2481         for (tries = 0; tries < 5; tries++) {
2482                 temp = I915_READ(reg);
2483                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485                 if (temp & FDI_RX_SYMBOL_LOCK) {
2486                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2487                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2488                         break;
2489                 }
2490         }
2491         if (tries == 5)
2492                 DRM_ERROR("FDI train 2 fail!\n");
2493
2494         DRM_DEBUG_KMS("FDI train done\n");
2495
2496 }
2497
2498 static const int snb_b_fdi_train_param[] = {
2499         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503 };
2504
2505 /* The FDI link training functions for SNB/Cougarpoint. */
2506 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507 {
2508         struct drm_device *dev = crtc->dev;
2509         struct drm_i915_private *dev_priv = dev->dev_private;
2510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511         int pipe = intel_crtc->pipe;
2512         u32 reg, temp, i, retry;
2513
2514         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515            for train result */
2516         reg = FDI_RX_IMR(pipe);
2517         temp = I915_READ(reg);
2518         temp &= ~FDI_RX_SYMBOL_LOCK;
2519         temp &= ~FDI_RX_BIT_LOCK;
2520         I915_WRITE(reg, temp);
2521
2522         POSTING_READ(reg);
2523         udelay(150);
2524
2525         /* enable CPU FDI TX and PCH FDI RX */
2526         reg = FDI_TX_CTL(pipe);
2527         temp = I915_READ(reg);
2528         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2530         temp &= ~FDI_LINK_TRAIN_NONE;
2531         temp |= FDI_LINK_TRAIN_PATTERN_1;
2532         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533         /* SNB-B */
2534         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2535         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2536
2537         I915_WRITE(FDI_RX_MISC(pipe),
2538                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
2540         reg = FDI_RX_CTL(pipe);
2541         temp = I915_READ(reg);
2542         if (HAS_PCH_CPT(dev)) {
2543                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545         } else {
2546                 temp &= ~FDI_LINK_TRAIN_NONE;
2547                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548         }
2549         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551         POSTING_READ(reg);
2552         udelay(150);
2553
2554         for (i = 0; i < 4; i++) {
2555                 reg = FDI_TX_CTL(pipe);
2556                 temp = I915_READ(reg);
2557                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558                 temp |= snb_b_fdi_train_param[i];
2559                 I915_WRITE(reg, temp);
2560
2561                 POSTING_READ(reg);
2562                 udelay(500);
2563
2564                 for (retry = 0; retry < 5; retry++) {
2565                         reg = FDI_RX_IIR(pipe);
2566                         temp = I915_READ(reg);
2567                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568                         if (temp & FDI_RX_BIT_LOCK) {
2569                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571                                 break;
2572                         }
2573                         udelay(50);
2574                 }
2575                 if (retry < 5)
2576                         break;
2577         }
2578         if (i == 4)
2579                 DRM_ERROR("FDI train 1 fail!\n");
2580
2581         /* Train 2 */
2582         reg = FDI_TX_CTL(pipe);
2583         temp = I915_READ(reg);
2584         temp &= ~FDI_LINK_TRAIN_NONE;
2585         temp |= FDI_LINK_TRAIN_PATTERN_2;
2586         if (IS_GEN6(dev)) {
2587                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588                 /* SNB-B */
2589                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590         }
2591         I915_WRITE(reg, temp);
2592
2593         reg = FDI_RX_CTL(pipe);
2594         temp = I915_READ(reg);
2595         if (HAS_PCH_CPT(dev)) {
2596                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598         } else {
2599                 temp &= ~FDI_LINK_TRAIN_NONE;
2600                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601         }
2602         I915_WRITE(reg, temp);
2603
2604         POSTING_READ(reg);
2605         udelay(150);
2606
2607         for (i = 0; i < 4; i++) {
2608                 reg = FDI_TX_CTL(pipe);
2609                 temp = I915_READ(reg);
2610                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611                 temp |= snb_b_fdi_train_param[i];
2612                 I915_WRITE(reg, temp);
2613
2614                 POSTING_READ(reg);
2615                 udelay(500);
2616
2617                 for (retry = 0; retry < 5; retry++) {
2618                         reg = FDI_RX_IIR(pipe);
2619                         temp = I915_READ(reg);
2620                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621                         if (temp & FDI_RX_SYMBOL_LOCK) {
2622                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624                                 break;
2625                         }
2626                         udelay(50);
2627                 }
2628                 if (retry < 5)
2629                         break;
2630         }
2631         if (i == 4)
2632                 DRM_ERROR("FDI train 2 fail!\n");
2633
2634         DRM_DEBUG_KMS("FDI train done.\n");
2635 }
2636
2637 /* Manual link training for Ivy Bridge A0 parts */
2638 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639 {
2640         struct drm_device *dev = crtc->dev;
2641         struct drm_i915_private *dev_priv = dev->dev_private;
2642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643         int pipe = intel_crtc->pipe;
2644         u32 reg, temp, i, j;
2645
2646         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647            for train result */
2648         reg = FDI_RX_IMR(pipe);
2649         temp = I915_READ(reg);
2650         temp &= ~FDI_RX_SYMBOL_LOCK;
2651         temp &= ~FDI_RX_BIT_LOCK;
2652         I915_WRITE(reg, temp);
2653
2654         POSTING_READ(reg);
2655         udelay(150);
2656
2657         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658                       I915_READ(FDI_RX_IIR(pipe)));
2659
2660         /* Try each vswing and preemphasis setting twice before moving on */
2661         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2662                 /* disable first in case we need to retry */
2663                 reg = FDI_TX_CTL(pipe);
2664                 temp = I915_READ(reg);
2665                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666                 temp &= ~FDI_TX_ENABLE;
2667                 I915_WRITE(reg, temp);
2668
2669                 reg = FDI_RX_CTL(pipe);
2670                 temp = I915_READ(reg);
2671                 temp &= ~FDI_LINK_TRAIN_AUTO;
2672                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673                 temp &= ~FDI_RX_ENABLE;
2674                 I915_WRITE(reg, temp);
2675
2676                 /* enable CPU FDI TX and PCH FDI RX */
2677                 reg = FDI_TX_CTL(pipe);
2678                 temp = I915_READ(reg);
2679                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2680                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2681                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2682                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2683                 temp |= snb_b_fdi_train_param[j/2];
2684                 temp |= FDI_COMPOSITE_SYNC;
2685                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2686
2687                 I915_WRITE(FDI_RX_MISC(pipe),
2688                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2689
2690                 reg = FDI_RX_CTL(pipe);
2691                 temp = I915_READ(reg);
2692                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2693                 temp |= FDI_COMPOSITE_SYNC;
2694                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2695
2696                 POSTING_READ(reg);
2697                 udelay(1); /* should be 0.5us */
2698
2699                 for (i = 0; i < 4; i++) {
2700                         reg = FDI_RX_IIR(pipe);
2701                         temp = I915_READ(reg);
2702                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2703
2704                         if (temp & FDI_RX_BIT_LOCK ||
2705                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2706                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2707                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2708                                               i);
2709                                 break;
2710                         }
2711                         udelay(1); /* should be 0.5us */
2712                 }
2713                 if (i == 4) {
2714                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2715                         continue;
2716                 }
2717
2718                 /* Train 2 */
2719                 reg = FDI_TX_CTL(pipe);
2720                 temp = I915_READ(reg);
2721                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2722                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2723                 I915_WRITE(reg, temp);
2724
2725                 reg = FDI_RX_CTL(pipe);
2726                 temp = I915_READ(reg);
2727                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2728                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2729                 I915_WRITE(reg, temp);
2730
2731                 POSTING_READ(reg);
2732                 udelay(2); /* should be 1.5us */
2733
2734                 for (i = 0; i < 4; i++) {
2735                         reg = FDI_RX_IIR(pipe);
2736                         temp = I915_READ(reg);
2737                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2738
2739                         if (temp & FDI_RX_SYMBOL_LOCK ||
2740                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2741                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2742                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2743                                               i);
2744                                 goto train_done;
2745                         }
2746                         udelay(2); /* should be 1.5us */
2747                 }
2748                 if (i == 4)
2749                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2750         }
2751
2752 train_done:
2753         DRM_DEBUG_KMS("FDI train done.\n");
2754 }
2755
2756 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2757 {
2758         struct drm_device *dev = intel_crtc->base.dev;
2759         struct drm_i915_private *dev_priv = dev->dev_private;
2760         int pipe = intel_crtc->pipe;
2761         u32 reg, temp;
2762
2763
2764         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2765         reg = FDI_RX_CTL(pipe);
2766         temp = I915_READ(reg);
2767         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2768         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2769         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2770         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2771
2772         POSTING_READ(reg);
2773         udelay(200);
2774
2775         /* Switch from Rawclk to PCDclk */
2776         temp = I915_READ(reg);
2777         I915_WRITE(reg, temp | FDI_PCDCLK);
2778
2779         POSTING_READ(reg);
2780         udelay(200);
2781
2782         /* Enable CPU FDI TX PLL, always on for Ironlake */
2783         reg = FDI_TX_CTL(pipe);
2784         temp = I915_READ(reg);
2785         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2786                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2787
2788                 POSTING_READ(reg);
2789                 udelay(100);
2790         }
2791 }
2792
2793 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2794 {
2795         struct drm_device *dev = intel_crtc->base.dev;
2796         struct drm_i915_private *dev_priv = dev->dev_private;
2797         int pipe = intel_crtc->pipe;
2798         u32 reg, temp;
2799
2800         /* Switch from PCDclk to Rawclk */
2801         reg = FDI_RX_CTL(pipe);
2802         temp = I915_READ(reg);
2803         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2804
2805         /* Disable CPU FDI TX PLL */
2806         reg = FDI_TX_CTL(pipe);
2807         temp = I915_READ(reg);
2808         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2809
2810         POSTING_READ(reg);
2811         udelay(100);
2812
2813         reg = FDI_RX_CTL(pipe);
2814         temp = I915_READ(reg);
2815         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2816
2817         /* Wait for the clocks to turn off. */
2818         POSTING_READ(reg);
2819         udelay(100);
2820 }
2821
2822 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2823 {
2824         struct drm_device *dev = crtc->dev;
2825         struct drm_i915_private *dev_priv = dev->dev_private;
2826         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2827         int pipe = intel_crtc->pipe;
2828         u32 reg, temp;
2829
2830         /* disable CPU FDI tx and PCH FDI rx */
2831         reg = FDI_TX_CTL(pipe);
2832         temp = I915_READ(reg);
2833         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2834         POSTING_READ(reg);
2835
2836         reg = FDI_RX_CTL(pipe);
2837         temp = I915_READ(reg);
2838         temp &= ~(0x7 << 16);
2839         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2840         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2841
2842         POSTING_READ(reg);
2843         udelay(100);
2844
2845         /* Ironlake workaround, disable clock pointer after downing FDI */
2846         if (HAS_PCH_IBX(dev)) {
2847                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2848         }
2849
2850         /* still set train pattern 1 */
2851         reg = FDI_TX_CTL(pipe);
2852         temp = I915_READ(reg);
2853         temp &= ~FDI_LINK_TRAIN_NONE;
2854         temp |= FDI_LINK_TRAIN_PATTERN_1;
2855         I915_WRITE(reg, temp);
2856
2857         reg = FDI_RX_CTL(pipe);
2858         temp = I915_READ(reg);
2859         if (HAS_PCH_CPT(dev)) {
2860                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2861                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2862         } else {
2863                 temp &= ~FDI_LINK_TRAIN_NONE;
2864                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2865         }
2866         /* BPC in FDI rx is consistent with that in PIPECONF */
2867         temp &= ~(0x07 << 16);
2868         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2869         I915_WRITE(reg, temp);
2870
2871         POSTING_READ(reg);
2872         udelay(100);
2873 }
2874
2875 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2876 {
2877         struct drm_device *dev = crtc->dev;
2878         struct drm_i915_private *dev_priv = dev->dev_private;
2879         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880         unsigned long flags;
2881         bool pending;
2882
2883         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2884             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2885                 return false;
2886
2887         spin_lock_irqsave(&dev->event_lock, flags);
2888         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2889         spin_unlock_irqrestore(&dev->event_lock, flags);
2890
2891         return pending;
2892 }
2893
2894 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2895 {
2896         struct drm_device *dev = crtc->dev;
2897         struct drm_i915_private *dev_priv = dev->dev_private;
2898
2899         if (crtc->fb == NULL)
2900                 return;
2901
2902         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2903
2904         wait_event(dev_priv->pending_flip_queue,
2905                    !intel_crtc_has_pending_flip(crtc));
2906
2907         mutex_lock(&dev->struct_mutex);
2908         intel_finish_fb(crtc->fb);
2909         mutex_unlock(&dev->struct_mutex);
2910 }
2911
2912 /* Program iCLKIP clock to the desired frequency */
2913 static void lpt_program_iclkip(struct drm_crtc *crtc)
2914 {
2915         struct drm_device *dev = crtc->dev;
2916         struct drm_i915_private *dev_priv = dev->dev_private;
2917         int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
2918         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2919         u32 temp;
2920
2921         mutex_lock(&dev_priv->dpio_lock);
2922
2923         /* It is necessary to ungate the pixclk gate prior to programming
2924          * the divisors, and gate it back when it is done.
2925          */
2926         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2927
2928         /* Disable SSCCTL */
2929         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2930                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2931                                 SBI_SSCCTL_DISABLE,
2932                         SBI_ICLK);
2933
2934         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2935         if (clock == 20000) {
2936                 auxdiv = 1;
2937                 divsel = 0x41;
2938                 phaseinc = 0x20;
2939         } else {
2940                 /* The iCLK virtual clock root frequency is in MHz,
2941                  * but the adjusted_mode->clock in in KHz. To get the divisors,
2942                  * it is necessary to divide one by another, so we
2943                  * convert the virtual clock precision to KHz here for higher
2944                  * precision.
2945                  */
2946                 u32 iclk_virtual_root_freq = 172800 * 1000;
2947                 u32 iclk_pi_range = 64;
2948                 u32 desired_divisor, msb_divisor_value, pi_value;
2949
2950                 desired_divisor = (iclk_virtual_root_freq / clock);
2951                 msb_divisor_value = desired_divisor / iclk_pi_range;
2952                 pi_value = desired_divisor % iclk_pi_range;
2953
2954                 auxdiv = 0;
2955                 divsel = msb_divisor_value - 2;
2956                 phaseinc = pi_value;
2957         }
2958
2959         /* This should not happen with any sane values */
2960         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2961                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2962         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2963                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2964
2965         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2966                         clock,
2967                         auxdiv,
2968                         divsel,
2969                         phasedir,
2970                         phaseinc);
2971
2972         /* Program SSCDIVINTPHASE6 */
2973         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2974         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2975         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2976         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2977         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2978         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2979         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2980         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2981
2982         /* Program SSCAUXDIV */
2983         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2984         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2985         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2986         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2987
2988         /* Enable modulator and associated divider */
2989         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2990         temp &= ~SBI_SSCCTL_DISABLE;
2991         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2992
2993         /* Wait for initialization time */
2994         udelay(24);
2995
2996         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2997
2998         mutex_unlock(&dev_priv->dpio_lock);
2999 }
3000
3001 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3002                                                 enum pipe pch_transcoder)
3003 {
3004         struct drm_device *dev = crtc->base.dev;
3005         struct drm_i915_private *dev_priv = dev->dev_private;
3006         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3007
3008         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3009                    I915_READ(HTOTAL(cpu_transcoder)));
3010         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3011                    I915_READ(HBLANK(cpu_transcoder)));
3012         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3013                    I915_READ(HSYNC(cpu_transcoder)));
3014
3015         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3016                    I915_READ(VTOTAL(cpu_transcoder)));
3017         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3018                    I915_READ(VBLANK(cpu_transcoder)));
3019         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3020                    I915_READ(VSYNC(cpu_transcoder)));
3021         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3022                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3023 }
3024
3025 /*
3026  * Enable PCH resources required for PCH ports:
3027  *   - PCH PLLs
3028  *   - FDI training & RX/TX
3029  *   - update transcoder timings
3030  *   - DP transcoding bits
3031  *   - transcoder
3032  */
3033 static void ironlake_pch_enable(struct drm_crtc *crtc)
3034 {
3035         struct drm_device *dev = crtc->dev;
3036         struct drm_i915_private *dev_priv = dev->dev_private;
3037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038         int pipe = intel_crtc->pipe;
3039         u32 reg, temp;
3040
3041         assert_pch_transcoder_disabled(dev_priv, pipe);
3042
3043         /* Write the TU size bits before fdi link training, so that error
3044          * detection works. */
3045         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3046                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3047
3048         /* For PCH output, training FDI link */
3049         dev_priv->display.fdi_link_train(crtc);
3050
3051         /* We need to program the right clock selection before writing the pixel
3052          * mutliplier into the DPLL. */
3053         if (HAS_PCH_CPT(dev)) {
3054                 u32 sel;
3055
3056                 temp = I915_READ(PCH_DPLL_SEL);
3057                 temp |= TRANS_DPLL_ENABLE(pipe);
3058                 sel = TRANS_DPLLB_SEL(pipe);
3059                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3060                         temp |= sel;
3061                 else
3062                         temp &= ~sel;
3063                 I915_WRITE(PCH_DPLL_SEL, temp);
3064         }
3065
3066         /* XXX: pch pll's can be enabled any time before we enable the PCH
3067          * transcoder, and we actually should do this to not upset any PCH
3068          * transcoder that already use the clock when we share it.
3069          *
3070          * Note that enable_shared_dpll tries to do the right thing, but
3071          * get_shared_dpll unconditionally resets the pll - we need that to have
3072          * the right LVDS enable sequence. */
3073         ironlake_enable_shared_dpll(intel_crtc);
3074
3075         /* set transcoder timing, panel must allow it */
3076         assert_panel_unlocked(dev_priv, pipe);
3077         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3078
3079         intel_fdi_normal_train(crtc);
3080
3081         /* For PCH DP, enable TRANS_DP_CTL */
3082         if (HAS_PCH_CPT(dev) &&
3083             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3084              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3085                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3086                 reg = TRANS_DP_CTL(pipe);
3087                 temp = I915_READ(reg);
3088                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3089                           TRANS_DP_SYNC_MASK |
3090                           TRANS_DP_BPC_MASK);
3091                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3092                          TRANS_DP_ENH_FRAMING);
3093                 temp |= bpc << 9; /* same format but at 11:9 */
3094
3095                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3096                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3097                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3098                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3099
3100                 switch (intel_trans_dp_port_sel(crtc)) {
3101                 case PCH_DP_B:
3102                         temp |= TRANS_DP_PORT_SEL_B;
3103                         break;
3104                 case PCH_DP_C:
3105                         temp |= TRANS_DP_PORT_SEL_C;
3106                         break;
3107                 case PCH_DP_D:
3108                         temp |= TRANS_DP_PORT_SEL_D;
3109                         break;
3110                 default:
3111                         BUG();
3112                 }
3113
3114                 I915_WRITE(reg, temp);
3115         }
3116
3117         ironlake_enable_pch_transcoder(dev_priv, pipe);
3118 }
3119
3120 static void lpt_pch_enable(struct drm_crtc *crtc)
3121 {
3122         struct drm_device *dev = crtc->dev;
3123         struct drm_i915_private *dev_priv = dev->dev_private;
3124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3125         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3126
3127         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3128
3129         lpt_program_iclkip(crtc);
3130
3131         /* Set transcoder timing. */
3132         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3133
3134         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3135 }
3136
3137 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3138 {
3139         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3140
3141         if (pll == NULL)
3142                 return;
3143
3144         if (pll->refcount == 0) {
3145                 WARN(1, "bad %s refcount\n", pll->name);
3146                 return;
3147         }
3148
3149         if (--pll->refcount == 0) {
3150                 WARN_ON(pll->on);
3151                 WARN_ON(pll->active);
3152         }
3153
3154         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3155 }
3156
3157 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3158 {
3159         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3160         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3161         enum intel_dpll_id i;
3162
3163         if (pll) {
3164                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3165                               crtc->base.base.id, pll->name);
3166                 intel_put_shared_dpll(crtc);
3167         }
3168
3169         if (HAS_PCH_IBX(dev_priv->dev)) {
3170                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3171                 i = (enum intel_dpll_id) crtc->pipe;
3172                 pll = &dev_priv->shared_dplls[i];
3173
3174                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3175                               crtc->base.base.id, pll->name);
3176
3177                 goto found;
3178         }
3179
3180         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3181                 pll = &dev_priv->shared_dplls[i];
3182
3183                 /* Only want to check enabled timings first */
3184                 if (pll->refcount == 0)
3185                         continue;
3186
3187                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3188                            sizeof(pll->hw_state)) == 0) {
3189                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3190                                       crtc->base.base.id,
3191                                       pll->name, pll->refcount, pll->active);
3192
3193                         goto found;
3194                 }
3195         }
3196
3197         /* Ok no matching timings, maybe there's a free one? */
3198         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3199                 pll = &dev_priv->shared_dplls[i];
3200                 if (pll->refcount == 0) {
3201                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3202                                       crtc->base.base.id, pll->name);
3203                         goto found;
3204                 }
3205         }
3206
3207         return NULL;
3208
3209 found:
3210         crtc->config.shared_dpll = i;
3211         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3212                          pipe_name(crtc->pipe));
3213
3214         if (pll->active == 0) {
3215                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3216                        sizeof(pll->hw_state));
3217
3218                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3219                 WARN_ON(pll->on);
3220                 assert_shared_dpll_disabled(dev_priv, pll);
3221
3222                 pll->mode_set(dev_priv, pll);
3223         }
3224         pll->refcount++;
3225
3226         return pll;
3227 }
3228
3229 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3230 {
3231         struct drm_i915_private *dev_priv = dev->dev_private;
3232         int dslreg = PIPEDSL(pipe);
3233         u32 temp;
3234
3235         temp = I915_READ(dslreg);
3236         udelay(500);
3237         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3238                 if (wait_for(I915_READ(dslreg) != temp, 5))
3239                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3240         }
3241 }
3242
3243 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3244 {
3245         struct drm_device *dev = crtc->base.dev;
3246         struct drm_i915_private *dev_priv = dev->dev_private;
3247         int pipe = crtc->pipe;
3248
3249         if (crtc->config.pch_pfit.size) {
3250                 /* Force use of hard-coded filter coefficients
3251                  * as some pre-programmed values are broken,
3252                  * e.g. x201.
3253                  */
3254                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3255                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3256                                                  PF_PIPE_SEL_IVB(pipe));
3257                 else
3258                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3259                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3260                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3261         }
3262 }
3263
3264 static void intel_enable_planes(struct drm_crtc *crtc)
3265 {
3266         struct drm_device *dev = crtc->dev;
3267         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3268         struct intel_plane *intel_plane;
3269
3270         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3271                 if (intel_plane->pipe == pipe)
3272                         intel_plane_restore(&intel_plane->base);
3273 }
3274
3275 static void intel_disable_planes(struct drm_crtc *crtc)
3276 {
3277         struct drm_device *dev = crtc->dev;
3278         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3279         struct intel_plane *intel_plane;
3280
3281         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3282                 if (intel_plane->pipe == pipe)
3283                         intel_plane_disable(&intel_plane->base);
3284 }
3285
3286 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3287 {
3288         struct drm_device *dev = crtc->dev;
3289         struct drm_i915_private *dev_priv = dev->dev_private;
3290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3291         struct intel_encoder *encoder;
3292         int pipe = intel_crtc->pipe;
3293         int plane = intel_crtc->plane;
3294
3295         WARN_ON(!crtc->enabled);
3296
3297         if (intel_crtc->active)
3298                 return;
3299
3300         intel_crtc->active = true;
3301
3302         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3303         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3304
3305         for_each_encoder_on_crtc(dev, crtc, encoder)
3306                 if (encoder->pre_enable)
3307                         encoder->pre_enable(encoder);
3308
3309         if (intel_crtc->config.has_pch_encoder) {
3310                 /* Note: FDI PLL enabling _must_ be done before we enable the
3311                  * cpu pipes, hence this is separate from all the other fdi/pch
3312                  * enabling. */
3313                 ironlake_fdi_pll_enable(intel_crtc);
3314         } else {
3315                 assert_fdi_tx_disabled(dev_priv, pipe);
3316                 assert_fdi_rx_disabled(dev_priv, pipe);
3317         }
3318
3319         ironlake_pfit_enable(intel_crtc);
3320
3321         /*
3322          * On ILK+ LUT must be loaded before the pipe is running but with
3323          * clocks enabled
3324          */
3325         intel_crtc_load_lut(crtc);
3326
3327         intel_update_watermarks(crtc);
3328         intel_enable_pipe(dev_priv, pipe,
3329                           intel_crtc->config.has_pch_encoder, false);
3330         intel_enable_plane(dev_priv, plane, pipe);
3331         intel_enable_planes(crtc);
3332         intel_crtc_update_cursor(crtc, true);
3333
3334         if (intel_crtc->config.has_pch_encoder)
3335                 ironlake_pch_enable(crtc);
3336
3337         mutex_lock(&dev->struct_mutex);
3338         intel_update_fbc(dev);
3339         mutex_unlock(&dev->struct_mutex);
3340
3341         for_each_encoder_on_crtc(dev, crtc, encoder)
3342                 encoder->enable(encoder);
3343
3344         if (HAS_PCH_CPT(dev))
3345                 cpt_verify_modeset(dev, intel_crtc->pipe);
3346
3347         /*
3348          * There seems to be a race in PCH platform hw (at least on some
3349          * outputs) where an enabled pipe still completes any pageflip right
3350          * away (as if the pipe is off) instead of waiting for vblank. As soon
3351          * as the first vblank happend, everything works as expected. Hence just
3352          * wait for one vblank before returning to avoid strange things
3353          * happening.
3354          */
3355         intel_wait_for_vblank(dev, intel_crtc->pipe);
3356 }
3357
3358 /* IPS only exists on ULT machines and is tied to pipe A. */
3359 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3360 {
3361         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3362 }
3363
3364 static void hsw_enable_ips(struct intel_crtc *crtc)
3365 {
3366         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3367
3368         if (!crtc->config.ips_enabled)
3369                 return;
3370
3371         /* We can only enable IPS after we enable a plane and wait for a vblank.
3372          * We guarantee that the plane is enabled by calling intel_enable_ips
3373          * only after intel_enable_plane. And intel_enable_plane already waits
3374          * for a vblank, so all we need to do here is to enable the IPS bit. */
3375         assert_plane_enabled(dev_priv, crtc->plane);
3376         I915_WRITE(IPS_CTL, IPS_ENABLE);
3377 }
3378
3379 static void hsw_disable_ips(struct intel_crtc *crtc)
3380 {
3381         struct drm_device *dev = crtc->base.dev;
3382         struct drm_i915_private *dev_priv = dev->dev_private;
3383
3384         if (!crtc->config.ips_enabled)
3385                 return;
3386
3387         assert_plane_enabled(dev_priv, crtc->plane);
3388         I915_WRITE(IPS_CTL, 0);
3389
3390         /* We need to wait for a vblank before we can disable the plane. */
3391         intel_wait_for_vblank(dev, crtc->pipe);
3392 }
3393
3394 static void haswell_crtc_enable(struct drm_crtc *crtc)
3395 {
3396         struct drm_device *dev = crtc->dev;
3397         struct drm_i915_private *dev_priv = dev->dev_private;
3398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399         struct intel_encoder *encoder;
3400         int pipe = intel_crtc->pipe;
3401         int plane = intel_crtc->plane;
3402
3403         WARN_ON(!crtc->enabled);
3404
3405         if (intel_crtc->active)
3406                 return;
3407
3408         intel_crtc->active = true;
3409
3410         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3411         if (intel_crtc->config.has_pch_encoder)
3412                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3413
3414         if (intel_crtc->config.has_pch_encoder)
3415                 dev_priv->display.fdi_link_train(crtc);
3416
3417         for_each_encoder_on_crtc(dev, crtc, encoder)
3418                 if (encoder->pre_enable)
3419                         encoder->pre_enable(encoder);
3420
3421         intel_ddi_enable_pipe_clock(intel_crtc);
3422
3423         ironlake_pfit_enable(intel_crtc);
3424
3425         /*
3426          * On ILK+ LUT must be loaded before the pipe is running but with
3427          * clocks enabled
3428          */
3429         intel_crtc_load_lut(crtc);
3430
3431         intel_ddi_set_pipe_settings(crtc);
3432         intel_ddi_enable_transcoder_func(crtc);
3433
3434         intel_update_watermarks(crtc);
3435         intel_enable_pipe(dev_priv, pipe,
3436                           intel_crtc->config.has_pch_encoder, false);
3437         intel_enable_plane(dev_priv, plane, pipe);
3438         intel_enable_planes(crtc);
3439         intel_crtc_update_cursor(crtc, true);
3440
3441         hsw_enable_ips(intel_crtc);
3442
3443         if (intel_crtc->config.has_pch_encoder)
3444                 lpt_pch_enable(crtc);
3445
3446         mutex_lock(&dev->struct_mutex);
3447         intel_update_fbc(dev);
3448         mutex_unlock(&dev->struct_mutex);
3449
3450         for_each_encoder_on_crtc(dev, crtc, encoder) {
3451                 encoder->enable(encoder);
3452                 intel_opregion_notify_encoder(encoder, true);
3453         }
3454
3455         /*
3456          * There seems to be a race in PCH platform hw (at least on some
3457          * outputs) where an enabled pipe still completes any pageflip right
3458          * away (as if the pipe is off) instead of waiting for vblank. As soon
3459          * as the first vblank happend, everything works as expected. Hence just
3460          * wait for one vblank before returning to avoid strange things
3461          * happening.
3462          */
3463         intel_wait_for_vblank(dev, intel_crtc->pipe);
3464 }
3465
3466 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3467 {
3468         struct drm_device *dev = crtc->base.dev;
3469         struct drm_i915_private *dev_priv = dev->dev_private;
3470         int pipe = crtc->pipe;
3471
3472         /* To avoid upsetting the power well on haswell only disable the pfit if
3473          * it's in use. The hw state code will make sure we get this right. */
3474         if (crtc->config.pch_pfit.size) {
3475                 I915_WRITE(PF_CTL(pipe), 0);
3476                 I915_WRITE(PF_WIN_POS(pipe), 0);
3477                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3478         }
3479 }
3480
3481 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3482 {
3483         struct drm_device *dev = crtc->dev;
3484         struct drm_i915_private *dev_priv = dev->dev_private;
3485         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3486         struct intel_encoder *encoder;
3487         int pipe = intel_crtc->pipe;
3488         int plane = intel_crtc->plane;
3489         u32 reg, temp;
3490
3491
3492         if (!intel_crtc->active)
3493                 return;
3494
3495         for_each_encoder_on_crtc(dev, crtc, encoder)
3496                 encoder->disable(encoder);
3497
3498         intel_crtc_wait_for_pending_flips(crtc);
3499         drm_vblank_off(dev, pipe);
3500
3501         if (dev_priv->fbc.plane == plane)
3502                 intel_disable_fbc(dev);
3503
3504         intel_crtc_update_cursor(crtc, false);
3505         intel_disable_planes(crtc);
3506         intel_disable_plane(dev_priv, plane, pipe);
3507
3508         if (intel_crtc->config.has_pch_encoder)
3509                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3510
3511         intel_disable_pipe(dev_priv, pipe);
3512
3513         ironlake_pfit_disable(intel_crtc);
3514
3515         for_each_encoder_on_crtc(dev, crtc, encoder)
3516                 if (encoder->post_disable)
3517                         encoder->post_disable(encoder);
3518
3519         if (intel_crtc->config.has_pch_encoder) {
3520                 ironlake_fdi_disable(crtc);
3521
3522                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3523                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3524
3525                 if (HAS_PCH_CPT(dev)) {
3526                         /* disable TRANS_DP_CTL */
3527                         reg = TRANS_DP_CTL(pipe);
3528                         temp = I915_READ(reg);
3529                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3530                                   TRANS_DP_PORT_SEL_MASK);
3531                         temp |= TRANS_DP_PORT_SEL_NONE;
3532                         I915_WRITE(reg, temp);
3533
3534                         /* disable DPLL_SEL */
3535                         temp = I915_READ(PCH_DPLL_SEL);
3536                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3537                         I915_WRITE(PCH_DPLL_SEL, temp);
3538                 }
3539
3540                 /* disable PCH DPLL */
3541                 intel_disable_shared_dpll(intel_crtc);
3542
3543                 ironlake_fdi_pll_disable(intel_crtc);
3544         }
3545
3546         intel_crtc->active = false;
3547         intel_update_watermarks(crtc);
3548
3549         mutex_lock(&dev->struct_mutex);
3550         intel_update_fbc(dev);
3551         mutex_unlock(&dev->struct_mutex);
3552 }
3553
3554 static void haswell_crtc_disable(struct drm_crtc *crtc)
3555 {
3556         struct drm_device *dev = crtc->dev;
3557         struct drm_i915_private *dev_priv = dev->dev_private;
3558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3559         struct intel_encoder *encoder;
3560         int pipe = intel_crtc->pipe;
3561         int plane = intel_crtc->plane;
3562         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3563
3564         if (!intel_crtc->active)
3565                 return;
3566
3567         for_each_encoder_on_crtc(dev, crtc, encoder) {
3568                 intel_opregion_notify_encoder(encoder, false);
3569                 encoder->disable(encoder);
3570         }
3571
3572         intel_crtc_wait_for_pending_flips(crtc);
3573         drm_vblank_off(dev, pipe);
3574
3575         /* FBC must be disabled before disabling the plane on HSW. */
3576         if (dev_priv->fbc.plane == plane)
3577                 intel_disable_fbc(dev);
3578
3579         hsw_disable_ips(intel_crtc);
3580
3581         intel_crtc_update_cursor(crtc, false);
3582         intel_disable_planes(crtc);
3583         intel_disable_plane(dev_priv, plane, pipe);
3584
3585         if (intel_crtc->config.has_pch_encoder)
3586                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3587         intel_disable_pipe(dev_priv, pipe);
3588
3589         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3590
3591         ironlake_pfit_disable(intel_crtc);
3592
3593         intel_ddi_disable_pipe_clock(intel_crtc);
3594
3595         for_each_encoder_on_crtc(dev, crtc, encoder)
3596                 if (encoder->post_disable)
3597                         encoder->post_disable(encoder);
3598
3599         if (intel_crtc->config.has_pch_encoder) {
3600                 lpt_disable_pch_transcoder(dev_priv);
3601                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3602                 intel_ddi_fdi_disable(crtc);
3603         }
3604
3605         intel_crtc->active = false;
3606         intel_update_watermarks(crtc);
3607
3608         mutex_lock(&dev->struct_mutex);
3609         intel_update_fbc(dev);
3610         mutex_unlock(&dev->struct_mutex);
3611 }
3612
3613 static void ironlake_crtc_off(struct drm_crtc *crtc)
3614 {
3615         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3616         intel_put_shared_dpll(intel_crtc);
3617 }
3618
3619 static void haswell_crtc_off(struct drm_crtc *crtc)
3620 {
3621         intel_ddi_put_crtc_pll(crtc);
3622 }
3623
3624 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3625 {
3626         if (!enable && intel_crtc->overlay) {
3627                 struct drm_device *dev = intel_crtc->base.dev;
3628                 struct drm_i915_private *dev_priv = dev->dev_private;
3629
3630                 mutex_lock(&dev->struct_mutex);
3631                 dev_priv->mm.interruptible = false;
3632                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3633                 dev_priv->mm.interruptible = true;
3634                 mutex_unlock(&dev->struct_mutex);
3635         }
3636
3637         /* Let userspace switch the overlay on again. In most cases userspace
3638          * has to recompute where to put it anyway.
3639          */
3640 }
3641
3642 /**
3643  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3644  * cursor plane briefly if not already running after enabling the display
3645  * plane.
3646  * This workaround avoids occasional blank screens when self refresh is
3647  * enabled.
3648  */
3649 static void
3650 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3651 {
3652         u32 cntl = I915_READ(CURCNTR(pipe));
3653
3654         if ((cntl & CURSOR_MODE) == 0) {
3655                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3656
3657                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3658                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3659                 intel_wait_for_vblank(dev_priv->dev, pipe);
3660                 I915_WRITE(CURCNTR(pipe), cntl);
3661                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3662                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3663         }
3664 }
3665
3666 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3667 {
3668         struct drm_device *dev = crtc->base.dev;
3669         struct drm_i915_private *dev_priv = dev->dev_private;
3670         struct intel_crtc_config *pipe_config = &crtc->config;
3671
3672         if (!crtc->config.gmch_pfit.control)
3673                 return;
3674
3675         /*
3676          * The panel fitter should only be adjusted whilst the pipe is disabled,
3677          * according to register description and PRM.
3678          */
3679         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3680         assert_pipe_disabled(dev_priv, crtc->pipe);
3681
3682         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3683         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3684
3685         /* Border color in case we don't scale up to the full screen. Black by
3686          * default, change to something else for debugging. */
3687         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3688 }
3689
3690 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3691 {
3692         struct drm_device *dev = crtc->dev;
3693         struct drm_i915_private *dev_priv = dev->dev_private;
3694         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3695         struct intel_encoder *encoder;
3696         int pipe = intel_crtc->pipe;
3697         int plane = intel_crtc->plane;
3698         bool is_dsi;
3699
3700         WARN_ON(!crtc->enabled);
3701
3702         if (intel_crtc->active)
3703                 return;
3704
3705         intel_crtc->active = true;
3706
3707         for_each_encoder_on_crtc(dev, crtc, encoder)
3708                 if (encoder->pre_pll_enable)
3709                         encoder->pre_pll_enable(encoder);
3710
3711         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3712
3713         if (!is_dsi)
3714                 vlv_enable_pll(intel_crtc);
3715
3716         for_each_encoder_on_crtc(dev, crtc, encoder)
3717                 if (encoder->pre_enable)
3718                         encoder->pre_enable(encoder);
3719
3720         i9xx_pfit_enable(intel_crtc);
3721
3722         intel_crtc_load_lut(crtc);
3723
3724         intel_update_watermarks(crtc);
3725         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3726         intel_enable_plane(dev_priv, plane, pipe);
3727         intel_enable_planes(crtc);
3728         intel_crtc_update_cursor(crtc, true);
3729
3730         intel_update_fbc(dev);
3731
3732         for_each_encoder_on_crtc(dev, crtc, encoder)
3733                 encoder->enable(encoder);
3734 }
3735
3736 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3737 {
3738         struct drm_device *dev = crtc->dev;
3739         struct drm_i915_private *dev_priv = dev->dev_private;
3740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741         struct intel_encoder *encoder;
3742         int pipe = intel_crtc->pipe;
3743         int plane = intel_crtc->plane;
3744
3745         WARN_ON(!crtc->enabled);
3746
3747         if (intel_crtc->active)
3748                 return;
3749
3750         intel_crtc->active = true;
3751
3752         for_each_encoder_on_crtc(dev, crtc, encoder)
3753                 if (encoder->pre_enable)
3754                         encoder->pre_enable(encoder);
3755
3756         i9xx_enable_pll(intel_crtc);
3757
3758         i9xx_pfit_enable(intel_crtc);
3759
3760         intel_crtc_load_lut(crtc);
3761
3762         intel_update_watermarks(crtc);
3763         intel_enable_pipe(dev_priv, pipe, false, false);
3764         intel_enable_plane(dev_priv, plane, pipe);
3765         intel_enable_planes(crtc);
3766         /* The fixup needs to happen before cursor is enabled */
3767         if (IS_G4X(dev))
3768                 g4x_fixup_plane(dev_priv, pipe);
3769         intel_crtc_update_cursor(crtc, true);
3770
3771         /* Give the overlay scaler a chance to enable if it's on this pipe */
3772         intel_crtc_dpms_overlay(intel_crtc, true);
3773
3774         intel_update_fbc(dev);
3775
3776         for_each_encoder_on_crtc(dev, crtc, encoder)
3777                 encoder->enable(encoder);
3778 }
3779
3780 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3781 {
3782         struct drm_device *dev = crtc->base.dev;
3783         struct drm_i915_private *dev_priv = dev->dev_private;
3784
3785         if (!crtc->config.gmch_pfit.control)
3786                 return;
3787
3788         assert_pipe_disabled(dev_priv, crtc->pipe);
3789
3790         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3791                          I915_READ(PFIT_CONTROL));
3792         I915_WRITE(PFIT_CONTROL, 0);
3793 }
3794
3795 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3796 {
3797         struct drm_device *dev = crtc->dev;
3798         struct drm_i915_private *dev_priv = dev->dev_private;
3799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3800         struct intel_encoder *encoder;
3801         int pipe = intel_crtc->pipe;
3802         int plane = intel_crtc->plane;
3803
3804         if (!intel_crtc->active)
3805                 return;
3806
3807         for_each_encoder_on_crtc(dev, crtc, encoder)
3808                 encoder->disable(encoder);
3809
3810         /* Give the overlay scaler a chance to disable if it's on this pipe */
3811         intel_crtc_wait_for_pending_flips(crtc);
3812         drm_vblank_off(dev, pipe);
3813
3814         if (dev_priv->fbc.plane == plane)
3815                 intel_disable_fbc(dev);
3816
3817         intel_crtc_dpms_overlay(intel_crtc, false);
3818         intel_crtc_update_cursor(crtc, false);
3819         intel_disable_planes(crtc);
3820         intel_disable_plane(dev_priv, plane, pipe);
3821
3822         intel_disable_pipe(dev_priv, pipe);
3823
3824         i9xx_pfit_disable(intel_crtc);
3825
3826         for_each_encoder_on_crtc(dev, crtc, encoder)
3827                 if (encoder->post_disable)
3828                         encoder->post_disable(encoder);
3829
3830         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3831                 i9xx_disable_pll(dev_priv, pipe);
3832
3833         intel_crtc->active = false;
3834         intel_update_watermarks(crtc);
3835
3836         intel_update_fbc(dev);
3837 }
3838
3839 static void i9xx_crtc_off(struct drm_crtc *crtc)
3840 {
3841 }
3842
3843 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3844                                     bool enabled)
3845 {
3846         struct drm_device *dev = crtc->dev;
3847         struct drm_i915_master_private *master_priv;
3848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849         int pipe = intel_crtc->pipe;
3850
3851         if (!dev->primary->master)
3852                 return;
3853
3854         master_priv = dev->primary->master->driver_priv;
3855         if (!master_priv->sarea_priv)
3856                 return;
3857
3858         switch (pipe) {
3859         case 0:
3860                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3861                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3862                 break;
3863         case 1:
3864                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3865                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3866                 break;
3867         default:
3868                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3869                 break;
3870         }
3871 }
3872
3873 /**
3874  * Sets the power management mode of the pipe and plane.
3875  */
3876 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3877 {
3878         struct drm_device *dev = crtc->dev;
3879         struct drm_i915_private *dev_priv = dev->dev_private;
3880         struct intel_encoder *intel_encoder;
3881         bool enable = false;
3882
3883         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3884                 enable |= intel_encoder->connectors_active;
3885
3886         if (enable)
3887                 dev_priv->display.crtc_enable(crtc);
3888         else
3889                 dev_priv->display.crtc_disable(crtc);
3890
3891         intel_crtc_update_sarea(crtc, enable);
3892 }
3893
3894 static void intel_crtc_disable(struct drm_crtc *crtc)
3895 {
3896         struct drm_device *dev = crtc->dev;
3897         struct drm_connector *connector;
3898         struct drm_i915_private *dev_priv = dev->dev_private;
3899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3900
3901         /* crtc should still be enabled when we disable it. */
3902         WARN_ON(!crtc->enabled);
3903
3904         dev_priv->display.crtc_disable(crtc);
3905         intel_crtc->eld_vld = false;
3906         intel_crtc_update_sarea(crtc, false);
3907         dev_priv->display.off(crtc);
3908
3909         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3910         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
3911         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3912
3913         if (crtc->fb) {
3914                 mutex_lock(&dev->struct_mutex);
3915                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3916                 mutex_unlock(&dev->struct_mutex);
3917                 crtc->fb = NULL;
3918         }
3919
3920         /* Update computed state. */
3921         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3922                 if (!connector->encoder || !connector->encoder->crtc)
3923                         continue;
3924
3925                 if (connector->encoder->crtc != crtc)
3926                         continue;
3927
3928                 connector->dpms = DRM_MODE_DPMS_OFF;
3929                 to_intel_encoder(connector->encoder)->connectors_active = false;
3930         }
3931 }
3932
3933 void intel_encoder_destroy(struct drm_encoder *encoder)
3934 {
3935         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3936
3937         drm_encoder_cleanup(encoder);
3938         kfree(intel_encoder);
3939 }
3940
3941 /* Simple dpms helper for encoders with just one connector, no cloning and only
3942  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3943  * state of the entire output pipe. */
3944 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3945 {
3946         if (mode == DRM_MODE_DPMS_ON) {
3947                 encoder->connectors_active = true;
3948
3949                 intel_crtc_update_dpms(encoder->base.crtc);
3950         } else {
3951                 encoder->connectors_active = false;
3952
3953                 intel_crtc_update_dpms(encoder->base.crtc);
3954         }
3955 }
3956
3957 /* Cross check the actual hw state with our own modeset state tracking (and it's
3958  * internal consistency). */
3959 static void intel_connector_check_state(struct intel_connector *connector)
3960 {
3961         if (connector->get_hw_state(connector)) {
3962                 struct intel_encoder *encoder = connector->encoder;
3963                 struct drm_crtc *crtc;
3964                 bool encoder_enabled;
3965                 enum pipe pipe;
3966
3967                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3968                               connector->base.base.id,
3969                               drm_get_connector_name(&connector->base));
3970
3971                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3972                      "wrong connector dpms state\n");
3973                 WARN(connector->base.encoder != &encoder->base,
3974                      "active connector not linked to encoder\n");
3975                 WARN(!encoder->connectors_active,
3976                      "encoder->connectors_active not set\n");
3977
3978                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3979                 WARN(!encoder_enabled, "encoder not enabled\n");
3980                 if (WARN_ON(!encoder->base.crtc))
3981                         return;
3982
3983                 crtc = encoder->base.crtc;
3984
3985                 WARN(!crtc->enabled, "crtc not enabled\n");
3986                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3987                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3988                      "encoder active on the wrong pipe\n");
3989         }
3990 }
3991
3992 /* Even simpler default implementation, if there's really no special case to
3993  * consider. */
3994 void intel_connector_dpms(struct drm_connector *connector, int mode)
3995 {
3996         struct intel_encoder *encoder = intel_attached_encoder(connector);
3997
3998         /* All the simple cases only support two dpms states. */
3999         if (mode != DRM_MODE_DPMS_ON)
4000                 mode = DRM_MODE_DPMS_OFF;
4001
4002         if (mode == connector->dpms)
4003                 return;
4004
4005         connector->dpms = mode;
4006
4007         /* Only need to change hw state when actually enabled */
4008         if (encoder->base.crtc)
4009                 intel_encoder_dpms(encoder, mode);
4010         else
4011                 WARN_ON(encoder->connectors_active != false);
4012
4013         intel_modeset_check_state(connector->dev);
4014 }
4015
4016 /* Simple connector->get_hw_state implementation for encoders that support only
4017  * one connector and no cloning and hence the encoder state determines the state
4018  * of the connector. */
4019 bool intel_connector_get_hw_state(struct intel_connector *connector)
4020 {
4021         enum pipe pipe = 0;
4022         struct intel_encoder *encoder = connector->encoder;
4023
4024         return encoder->get_hw_state(encoder, &pipe);
4025 }
4026
4027 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4028                                      struct intel_crtc_config *pipe_config)
4029 {
4030         struct drm_i915_private *dev_priv = dev->dev_private;
4031         struct intel_crtc *pipe_B_crtc =
4032                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4033
4034         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4035                       pipe_name(pipe), pipe_config->fdi_lanes);
4036         if (pipe_config->fdi_lanes > 4) {
4037                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4038                               pipe_name(pipe), pipe_config->fdi_lanes);
4039                 return false;
4040         }
4041
4042         if (IS_HASWELL(dev)) {
4043                 if (pipe_config->fdi_lanes > 2) {
4044                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4045                                       pipe_config->fdi_lanes);
4046                         return false;
4047                 } else {
4048                         return true;
4049                 }
4050         }
4051
4052         if (INTEL_INFO(dev)->num_pipes == 2)
4053                 return true;
4054
4055         /* Ivybridge 3 pipe is really complicated */
4056         switch (pipe) {
4057         case PIPE_A:
4058                 return true;
4059         case PIPE_B:
4060                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4061                     pipe_config->fdi_lanes > 2) {
4062                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4063                                       pipe_name(pipe), pipe_config->fdi_lanes);
4064                         return false;
4065                 }
4066                 return true;
4067         case PIPE_C:
4068                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4069                     pipe_B_crtc->config.fdi_lanes <= 2) {
4070                         if (pipe_config->fdi_lanes > 2) {
4071                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4072                                               pipe_name(pipe), pipe_config->fdi_lanes);
4073                                 return false;
4074                         }
4075                 } else {
4076                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4077                         return false;
4078                 }
4079                 return true;
4080         default:
4081                 BUG();
4082         }
4083 }
4084
4085 #define RETRY 1
4086 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4087                                        struct intel_crtc_config *pipe_config)
4088 {
4089         struct drm_device *dev = intel_crtc->base.dev;
4090         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4091         int lane, link_bw, fdi_dotclock;
4092         bool setup_ok, needs_recompute = false;
4093
4094 retry:
4095         /* FDI is a binary signal running at ~2.7GHz, encoding
4096          * each output octet as 10 bits. The actual frequency
4097          * is stored as a divider into a 100MHz clock, and the
4098          * mode pixel clock is stored in units of 1KHz.
4099          * Hence the bw of each lane in terms of the mode signal
4100          * is:
4101          */
4102         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4103
4104         fdi_dotclock = adjusted_mode->clock;
4105
4106         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4107                                            pipe_config->pipe_bpp);
4108
4109         pipe_config->fdi_lanes = lane;
4110
4111         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4112                                link_bw, &pipe_config->fdi_m_n);
4113
4114         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4115                                             intel_crtc->pipe, pipe_config);
4116         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4117                 pipe_config->pipe_bpp -= 2*3;
4118                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4119                               pipe_config->pipe_bpp);
4120                 needs_recompute = true;
4121                 pipe_config->bw_constrained = true;
4122
4123                 goto retry;
4124         }
4125
4126         if (needs_recompute)
4127                 return RETRY;
4128
4129         return setup_ok ? 0 : -EINVAL;
4130 }
4131
4132 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4133                                    struct intel_crtc_config *pipe_config)
4134 {
4135         pipe_config->ips_enabled = i915_enable_ips &&
4136                                    hsw_crtc_supports_ips(crtc) &&
4137                                    pipe_config->pipe_bpp <= 24;
4138 }
4139
4140 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4141                                      struct intel_crtc_config *pipe_config)
4142 {
4143         struct drm_device *dev = crtc->base.dev;
4144         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4145
4146         if (INTEL_INFO(dev)->gen < 4) {
4147                 struct drm_i915_private *dev_priv = dev->dev_private;
4148                 int clock_limit =
4149                         dev_priv->display.get_display_clock_speed(dev);
4150
4151                 /*
4152                  * Enable pixel doubling when the dot clock
4153                  * is > 90% of the (display) core speed.
4154                  *
4155                  * XXX: No double-wide on 915GM pipe B. Is that
4156                  * the only reason for the pipe == PIPE_A check?
4157                  */
4158                 if (crtc->pipe == PIPE_A &&
4159                     adjusted_mode->clock > clock_limit * 9 / 10)
4160                         pipe_config->double_wide = true;
4161         }
4162
4163         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4164          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4165          */
4166         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4167                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4168                 return -EINVAL;
4169
4170         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4171                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4172         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4173                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4174                  * for lvds. */
4175                 pipe_config->pipe_bpp = 8*3;
4176         }
4177
4178         if (HAS_IPS(dev))
4179                 hsw_compute_ips_config(crtc, pipe_config);
4180
4181         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4182          * clock survives for now. */
4183         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4184                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4185
4186         if (pipe_config->has_pch_encoder)
4187                 return ironlake_fdi_compute_config(crtc, pipe_config);
4188
4189         return 0;
4190 }
4191
4192 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4193 {
4194         return 400000; /* FIXME */
4195 }
4196
4197 static int i945_get_display_clock_speed(struct drm_device *dev)
4198 {
4199         return 400000;
4200 }
4201
4202 static int i915_get_display_clock_speed(struct drm_device *dev)
4203 {
4204         return 333000;
4205 }
4206
4207 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4208 {
4209         return 200000;
4210 }
4211
4212 static int pnv_get_display_clock_speed(struct drm_device *dev)
4213 {
4214         u16 gcfgc = 0;
4215
4216         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4217
4218         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4219         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4220                 return 267000;
4221         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4222                 return 333000;
4223         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4224                 return 444000;
4225         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4226                 return 200000;
4227         default:
4228                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4229         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4230                 return 133000;
4231         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4232                 return 167000;
4233         }
4234 }
4235
4236 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4237 {
4238         u16 gcfgc = 0;
4239
4240         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4241
4242         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4243                 return 133000;
4244         else {
4245                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4246                 case GC_DISPLAY_CLOCK_333_MHZ:
4247                         return 333000;
4248                 default:
4249                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4250                         return 190000;
4251                 }
4252         }
4253 }
4254
4255 static int i865_get_display_clock_speed(struct drm_device *dev)
4256 {
4257         return 266000;
4258 }
4259
4260 static int i855_get_display_clock_speed(struct drm_device *dev)
4261 {
4262         u16 hpllcc = 0;
4263         /* Assume that the hardware is in the high speed state.  This
4264          * should be the default.
4265          */
4266         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4267         case GC_CLOCK_133_200:
4268         case GC_CLOCK_100_200:
4269                 return 200000;
4270         case GC_CLOCK_166_250:
4271                 return 250000;
4272         case GC_CLOCK_100_133:
4273                 return 133000;
4274         }
4275
4276         /* Shouldn't happen */
4277         return 0;
4278 }
4279
4280 static int i830_get_display_clock_speed(struct drm_device *dev)
4281 {
4282         return 133000;
4283 }
4284
4285 static void
4286 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4287 {
4288         while (*num > DATA_LINK_M_N_MASK ||
4289                *den > DATA_LINK_M_N_MASK) {
4290                 *num >>= 1;
4291                 *den >>= 1;
4292         }
4293 }
4294
4295 static void compute_m_n(unsigned int m, unsigned int n,
4296                         uint32_t *ret_m, uint32_t *ret_n)
4297 {
4298         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4299         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4300         intel_reduce_m_n_ratio(ret_m, ret_n);
4301 }
4302
4303 void
4304 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4305                        int pixel_clock, int link_clock,
4306                        struct intel_link_m_n *m_n)
4307 {
4308         m_n->tu = 64;
4309
4310         compute_m_n(bits_per_pixel * pixel_clock,
4311                     link_clock * nlanes * 8,
4312                     &m_n->gmch_m, &m_n->gmch_n);
4313
4314         compute_m_n(pixel_clock, link_clock,
4315                     &m_n->link_m, &m_n->link_n);
4316 }
4317
4318 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4319 {
4320         if (i915_panel_use_ssc >= 0)
4321                 return i915_panel_use_ssc != 0;
4322         return dev_priv->vbt.lvds_use_ssc
4323                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4324 }
4325
4326 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4327 {
4328         struct drm_device *dev = crtc->dev;
4329         struct drm_i915_private *dev_priv = dev->dev_private;
4330         int refclk;
4331
4332         if (IS_VALLEYVIEW(dev)) {
4333                 refclk = 100000;
4334         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4335             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4336                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4337                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4338                               refclk / 1000);
4339         } else if (!IS_GEN2(dev)) {
4340                 refclk = 96000;
4341         } else {
4342                 refclk = 48000;
4343         }
4344
4345         return refclk;
4346 }
4347
4348 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4349 {
4350         return (1 << dpll->n) << 16 | dpll->m2;
4351 }
4352
4353 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4354 {
4355         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4356 }
4357
4358 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4359                                      intel_clock_t *reduced_clock)
4360 {
4361         struct drm_device *dev = crtc->base.dev;
4362         struct drm_i915_private *dev_priv = dev->dev_private;
4363         int pipe = crtc->pipe;
4364         u32 fp, fp2 = 0;
4365
4366         if (IS_PINEVIEW(dev)) {
4367                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4368                 if (reduced_clock)
4369                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4370         } else {
4371                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4372                 if (reduced_clock)
4373                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4374         }
4375
4376         I915_WRITE(FP0(pipe), fp);
4377         crtc->config.dpll_hw_state.fp0 = fp;
4378
4379         crtc->lowfreq_avail = false;
4380         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4381             reduced_clock && i915_powersave) {
4382                 I915_WRITE(FP1(pipe), fp2);
4383                 crtc->config.dpll_hw_state.fp1 = fp2;
4384                 crtc->lowfreq_avail = true;
4385         } else {
4386                 I915_WRITE(FP1(pipe), fp);
4387                 crtc->config.dpll_hw_state.fp1 = fp;
4388         }
4389 }
4390
4391 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4392                 pipe)
4393 {
4394         u32 reg_val;
4395
4396         /*
4397          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4398          * and set it to a reasonable value instead.
4399          */
4400         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4401         reg_val &= 0xffffff00;
4402         reg_val |= 0x00000030;
4403         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4404
4405         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4406         reg_val &= 0x8cffffff;
4407         reg_val = 0x8c000000;
4408         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4409
4410         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4411         reg_val &= 0xffffff00;
4412         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4413
4414         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4415         reg_val &= 0x00ffffff;
4416         reg_val |= 0xb0000000;
4417         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4418 }
4419
4420 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4421                                          struct intel_link_m_n *m_n)
4422 {
4423         struct drm_device *dev = crtc->base.dev;
4424         struct drm_i915_private *dev_priv = dev->dev_private;
4425         int pipe = crtc->pipe;
4426
4427         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4428         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4429         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4430         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4431 }
4432
4433 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4434                                          struct intel_link_m_n *m_n)
4435 {
4436         struct drm_device *dev = crtc->base.dev;
4437         struct drm_i915_private *dev_priv = dev->dev_private;
4438         int pipe = crtc->pipe;
4439         enum transcoder transcoder = crtc->config.cpu_transcoder;
4440
4441         if (INTEL_INFO(dev)->gen >= 5) {
4442                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4443                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4444                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4445                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4446         } else {
4447                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4448                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4449                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4450                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4451         }
4452 }
4453
4454 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4455 {
4456         if (crtc->config.has_pch_encoder)
4457                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4458         else
4459                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4460 }
4461
4462 static void vlv_update_pll(struct intel_crtc *crtc)
4463 {
4464         struct drm_device *dev = crtc->base.dev;
4465         struct drm_i915_private *dev_priv = dev->dev_private;
4466         int pipe = crtc->pipe;
4467         u32 dpll, mdiv;
4468         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4469         u32 coreclk, reg_val, dpll_md;
4470
4471         mutex_lock(&dev_priv->dpio_lock);
4472
4473         bestn = crtc->config.dpll.n;
4474         bestm1 = crtc->config.dpll.m1;
4475         bestm2 = crtc->config.dpll.m2;
4476         bestp1 = crtc->config.dpll.p1;
4477         bestp2 = crtc->config.dpll.p2;
4478
4479         /* See eDP HDMI DPIO driver vbios notes doc */
4480
4481         /* PLL B needs special handling */
4482         if (pipe)
4483                 vlv_pllb_recal_opamp(dev_priv, pipe);
4484
4485         /* Set up Tx target for periodic Rcomp update */
4486         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4487
4488         /* Disable target IRef on PLL */
4489         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4490         reg_val &= 0x00ffffff;
4491         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4492
4493         /* Disable fast lock */
4494         vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4495
4496         /* Set idtafcrecal before PLL is enabled */
4497         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4498         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4499         mdiv |= ((bestn << DPIO_N_SHIFT));
4500         mdiv |= (1 << DPIO_K_SHIFT);
4501
4502         /*
4503          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4504          * but we don't support that).
4505          * Note: don't use the DAC post divider as it seems unstable.
4506          */
4507         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4508         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4509
4510         mdiv |= DPIO_ENABLE_CALIBRATION;
4511         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4512
4513         /* Set HBR and RBR LPF coefficients */
4514         if (crtc->config.port_clock == 162000 ||
4515             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4516             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4517                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4518                                  0x009f0003);
4519         else
4520                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4521                                  0x00d0000f);
4522
4523         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4524             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4525                 /* Use SSC source */
4526                 if (!pipe)
4527                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4528                                          0x0df40000);
4529                 else
4530                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4531                                          0x0df70000);
4532         } else { /* HDMI or VGA */
4533                 /* Use bend source */
4534                 if (!pipe)
4535                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4536                                          0x0df70000);
4537                 else
4538                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4539                                          0x0df40000);
4540         }
4541
4542         coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4543         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4544         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4545             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4546                 coreclk |= 0x01000000;
4547         vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4548
4549         vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4550
4551         /* Enable DPIO clock input */
4552         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4553                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4554         if (pipe)
4555                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4556
4557         dpll |= DPLL_VCO_ENABLE;
4558         crtc->config.dpll_hw_state.dpll = dpll;
4559
4560         dpll_md = (crtc->config.pixel_multiplier - 1)
4561                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4562         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4563
4564         if (crtc->config.has_dp_encoder)
4565                 intel_dp_set_m_n(crtc);
4566
4567         mutex_unlock(&dev_priv->dpio_lock);
4568 }
4569
4570 static void i9xx_update_pll(struct intel_crtc *crtc,
4571                             intel_clock_t *reduced_clock,
4572                             int num_connectors)
4573 {
4574         struct drm_device *dev = crtc->base.dev;
4575         struct drm_i915_private *dev_priv = dev->dev_private;
4576         u32 dpll;
4577         bool is_sdvo;
4578         struct dpll *clock = &crtc->config.dpll;
4579
4580         i9xx_update_pll_dividers(crtc, reduced_clock);
4581
4582         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4583                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4584
4585         dpll = DPLL_VGA_MODE_DIS;
4586
4587         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4588                 dpll |= DPLLB_MODE_LVDS;
4589         else
4590                 dpll |= DPLLB_MODE_DAC_SERIAL;
4591
4592         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4593                 dpll |= (crtc->config.pixel_multiplier - 1)
4594                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4595         }
4596
4597         if (is_sdvo)
4598                 dpll |= DPLL_SDVO_HIGH_SPEED;
4599
4600         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4601                 dpll |= DPLL_SDVO_HIGH_SPEED;
4602
4603         /* compute bitmask from p1 value */
4604         if (IS_PINEVIEW(dev))
4605                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4606         else {
4607                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4608                 if (IS_G4X(dev) && reduced_clock)
4609                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4610         }
4611         switch (clock->p2) {
4612         case 5:
4613                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4614                 break;
4615         case 7:
4616                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4617                 break;
4618         case 10:
4619                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4620                 break;
4621         case 14:
4622                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4623                 break;
4624         }
4625         if (INTEL_INFO(dev)->gen >= 4)
4626                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4627
4628         if (crtc->config.sdvo_tv_clock)
4629                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4630         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4631                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4632                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4633         else
4634                 dpll |= PLL_REF_INPUT_DREFCLK;
4635
4636         dpll |= DPLL_VCO_ENABLE;
4637         crtc->config.dpll_hw_state.dpll = dpll;
4638
4639         if (INTEL_INFO(dev)->gen >= 4) {
4640                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4641                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4642                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4643         }
4644
4645         if (crtc->config.has_dp_encoder)
4646                 intel_dp_set_m_n(crtc);
4647 }
4648
4649 static void i8xx_update_pll(struct intel_crtc *crtc,
4650                             intel_clock_t *reduced_clock,
4651                             int num_connectors)
4652 {
4653         struct drm_device *dev = crtc->base.dev;
4654         struct drm_i915_private *dev_priv = dev->dev_private;
4655         u32 dpll;
4656         struct dpll *clock = &crtc->config.dpll;
4657
4658         i9xx_update_pll_dividers(crtc, reduced_clock);
4659
4660         dpll = DPLL_VGA_MODE_DIS;
4661
4662         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4663                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4664         } else {
4665                 if (clock->p1 == 2)
4666                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4667                 else
4668                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4669                 if (clock->p2 == 4)
4670                         dpll |= PLL_P2_DIVIDE_BY_4;
4671         }
4672
4673         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4674                 dpll |= DPLL_DVO_2X_MODE;
4675
4676         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4677                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4678                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4679         else
4680                 dpll |= PLL_REF_INPUT_DREFCLK;
4681
4682         dpll |= DPLL_VCO_ENABLE;
4683         crtc->config.dpll_hw_state.dpll = dpll;
4684 }
4685
4686 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4687 {
4688         struct drm_device *dev = intel_crtc->base.dev;
4689         struct drm_i915_private *dev_priv = dev->dev_private;
4690         enum pipe pipe = intel_crtc->pipe;
4691         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4692         struct drm_display_mode *adjusted_mode =
4693                 &intel_crtc->config.adjusted_mode;
4694         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4695
4696         /* We need to be careful not to changed the adjusted mode, for otherwise
4697          * the hw state checker will get angry at the mismatch. */
4698         crtc_vtotal = adjusted_mode->crtc_vtotal;
4699         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4700
4701         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4702                 /* the chip adds 2 halflines automatically */
4703                 crtc_vtotal -= 1;
4704                 crtc_vblank_end -= 1;
4705                 vsyncshift = adjusted_mode->crtc_hsync_start
4706                              - adjusted_mode->crtc_htotal / 2;
4707         } else {
4708                 vsyncshift = 0;
4709         }
4710
4711         if (INTEL_INFO(dev)->gen > 3)
4712                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4713
4714         I915_WRITE(HTOTAL(cpu_transcoder),
4715                    (adjusted_mode->crtc_hdisplay - 1) |
4716                    ((adjusted_mode->crtc_htotal - 1) << 16));
4717         I915_WRITE(HBLANK(cpu_transcoder),
4718                    (adjusted_mode->crtc_hblank_start - 1) |
4719                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4720         I915_WRITE(HSYNC(cpu_transcoder),
4721                    (adjusted_mode->crtc_hsync_start - 1) |
4722                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4723
4724         I915_WRITE(VTOTAL(cpu_transcoder),
4725                    (adjusted_mode->crtc_vdisplay - 1) |
4726                    ((crtc_vtotal - 1) << 16));
4727         I915_WRITE(VBLANK(cpu_transcoder),
4728                    (adjusted_mode->crtc_vblank_start - 1) |
4729                    ((crtc_vblank_end - 1) << 16));
4730         I915_WRITE(VSYNC(cpu_transcoder),
4731                    (adjusted_mode->crtc_vsync_start - 1) |
4732                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4733
4734         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4735          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4736          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4737          * bits. */
4738         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4739             (pipe == PIPE_B || pipe == PIPE_C))
4740                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4741
4742         /* pipesrc controls the size that is scaled from, which should
4743          * always be the user's requested size.
4744          */
4745         I915_WRITE(PIPESRC(pipe),
4746                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
4747                    (intel_crtc->config.pipe_src_h - 1));
4748 }
4749
4750 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4751                                    struct intel_crtc_config *pipe_config)
4752 {
4753         struct drm_device *dev = crtc->base.dev;
4754         struct drm_i915_private *dev_priv = dev->dev_private;
4755         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4756         uint32_t tmp;
4757
4758         tmp = I915_READ(HTOTAL(cpu_transcoder));
4759         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4760         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4761         tmp = I915_READ(HBLANK(cpu_transcoder));
4762         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4763         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4764         tmp = I915_READ(HSYNC(cpu_transcoder));
4765         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4766         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4767
4768         tmp = I915_READ(VTOTAL(cpu_transcoder));
4769         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4770         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4771         tmp = I915_READ(VBLANK(cpu_transcoder));
4772         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4773         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4774         tmp = I915_READ(VSYNC(cpu_transcoder));
4775         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4776         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4777
4778         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4779                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4780                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4781                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4782         }
4783
4784         tmp = I915_READ(PIPESRC(crtc->pipe));
4785         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4786         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4787
4788         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4789         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
4790 }
4791
4792 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4793                                              struct intel_crtc_config *pipe_config)
4794 {
4795         struct drm_crtc *crtc = &intel_crtc->base;
4796
4797         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4798         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4799         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4800         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4801
4802         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4803         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4804         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4805         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4806
4807         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4808
4809         crtc->mode.clock = pipe_config->adjusted_mode.clock;
4810         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4811 }
4812
4813 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4814 {
4815         struct drm_device *dev = intel_crtc->base.dev;
4816         struct drm_i915_private *dev_priv = dev->dev_private;
4817         uint32_t pipeconf;
4818
4819         pipeconf = 0;
4820
4821         if (intel_crtc->config.double_wide)
4822                 pipeconf |= PIPECONF_DOUBLE_WIDE;
4823
4824         /* only g4x and later have fancy bpc/dither controls */
4825         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4826                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4827                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4828                         pipeconf |= PIPECONF_DITHER_EN |
4829                                     PIPECONF_DITHER_TYPE_SP;
4830
4831                 switch (intel_crtc->config.pipe_bpp) {
4832                 case 18:
4833                         pipeconf |= PIPECONF_6BPC;
4834                         break;
4835                 case 24:
4836                         pipeconf |= PIPECONF_8BPC;
4837                         break;
4838                 case 30:
4839                         pipeconf |= PIPECONF_10BPC;
4840                         break;
4841                 default:
4842                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4843                         BUG();
4844                 }
4845         }
4846
4847         if (HAS_PIPE_CXSR(dev)) {
4848                 if (intel_crtc->lowfreq_avail) {
4849                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4850                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4851                 } else {
4852                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4853                 }
4854         }
4855
4856         if (!IS_GEN2(dev) &&
4857             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4858                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4859         else
4860                 pipeconf |= PIPECONF_PROGRESSIVE;
4861
4862         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4863                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4864
4865         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4866         POSTING_READ(PIPECONF(intel_crtc->pipe));
4867 }
4868
4869 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4870                               int x, int y,
4871                               struct drm_framebuffer *fb)
4872 {
4873         struct drm_device *dev = crtc->dev;
4874         struct drm_i915_private *dev_priv = dev->dev_private;
4875         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4876         int pipe = intel_crtc->pipe;
4877         int plane = intel_crtc->plane;
4878         int refclk, num_connectors = 0;
4879         intel_clock_t clock, reduced_clock;
4880         u32 dspcntr;
4881         bool ok, has_reduced_clock = false;
4882         bool is_lvds = false, is_dsi = false;
4883         struct intel_encoder *encoder;
4884         const intel_limit_t *limit;
4885         int ret;
4886
4887         for_each_encoder_on_crtc(dev, crtc, encoder) {
4888                 switch (encoder->type) {
4889                 case INTEL_OUTPUT_LVDS:
4890                         is_lvds = true;
4891                         break;
4892                 case INTEL_OUTPUT_DSI:
4893                         is_dsi = true;
4894                         break;
4895                 }
4896
4897                 num_connectors++;
4898         }
4899
4900         refclk = i9xx_get_refclk(crtc, num_connectors);
4901
4902         if (!is_dsi && !intel_crtc->config.clock_set) {
4903                 /*
4904                  * Returns a set of divisors for the desired target clock with
4905                  * the given refclk, or FALSE.  The returned values represent
4906                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4907                  * 2) / p1 / p2.
4908                  */
4909                 limit = intel_limit(crtc, refclk);
4910                 ok = dev_priv->display.find_dpll(limit, crtc,
4911                                                  intel_crtc->config.port_clock,
4912                                                  refclk, NULL, &clock);
4913                 if (!ok && !intel_crtc->config.clock_set) {
4914                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
4915                         return -EINVAL;
4916                 }
4917         }
4918
4919         /* Ensure that the cursor is valid for the new mode before changing... */
4920         intel_crtc_update_cursor(crtc, true);
4921
4922         if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
4923                 /*
4924                  * Ensure we match the reduced clock's P to the target clock.
4925                  * If the clocks don't match, we can't switch the display clock
4926                  * by using the FP0/FP1. In such case we will disable the LVDS
4927                  * downclock feature.
4928                 */
4929                 limit = intel_limit(crtc, refclk);
4930                 has_reduced_clock =
4931                         dev_priv->display.find_dpll(limit, crtc,
4932                                                     dev_priv->lvds_downclock,
4933                                                     refclk, &clock,
4934                                                     &reduced_clock);
4935         }
4936         /* Compat-code for transition, will disappear. */
4937         if (!intel_crtc->config.clock_set) {
4938                 intel_crtc->config.dpll.n = clock.n;
4939                 intel_crtc->config.dpll.m1 = clock.m1;
4940                 intel_crtc->config.dpll.m2 = clock.m2;
4941                 intel_crtc->config.dpll.p1 = clock.p1;
4942                 intel_crtc->config.dpll.p2 = clock.p2;
4943         }
4944
4945         if (IS_GEN2(dev)) {
4946                 i8xx_update_pll(intel_crtc,
4947                                 has_reduced_clock ? &reduced_clock : NULL,
4948                                 num_connectors);
4949         } else if (IS_VALLEYVIEW(dev)) {
4950                 if (!is_dsi)
4951                         vlv_update_pll(intel_crtc);
4952         } else {
4953                 i9xx_update_pll(intel_crtc,
4954                                 has_reduced_clock ? &reduced_clock : NULL,
4955                                 num_connectors);
4956         }
4957
4958         /* Set up the display plane register */
4959         dspcntr = DISPPLANE_GAMMA_ENABLE;
4960
4961         if (!IS_VALLEYVIEW(dev)) {
4962                 if (pipe == 0)
4963                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4964                 else
4965                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4966         }
4967
4968         intel_set_pipe_timings(intel_crtc);
4969
4970         /* pipesrc and dspsize control the size that is scaled from,
4971          * which should always be the user's requested size.
4972          */
4973         I915_WRITE(DSPSIZE(plane),
4974                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4975                    (intel_crtc->config.pipe_src_w - 1));
4976         I915_WRITE(DSPPOS(plane), 0);
4977
4978         i9xx_set_pipeconf(intel_crtc);
4979
4980         I915_WRITE(DSPCNTR(plane), dspcntr);
4981         POSTING_READ(DSPCNTR(plane));
4982
4983         ret = intel_pipe_set_base(crtc, x, y, fb);
4984
4985         return ret;
4986 }
4987
4988 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4989                                  struct intel_crtc_config *pipe_config)
4990 {
4991         struct drm_device *dev = crtc->base.dev;
4992         struct drm_i915_private *dev_priv = dev->dev_private;
4993         uint32_t tmp;
4994
4995         tmp = I915_READ(PFIT_CONTROL);
4996         if (!(tmp & PFIT_ENABLE))
4997                 return;
4998
4999         /* Check whether the pfit is attached to our pipe. */
5000         if (INTEL_INFO(dev)->gen < 4) {
5001                 if (crtc->pipe != PIPE_B)
5002                         return;
5003         } else {
5004                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5005                         return;
5006         }
5007
5008         pipe_config->gmch_pfit.control = tmp;
5009         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5010         if (INTEL_INFO(dev)->gen < 5)
5011                 pipe_config->gmch_pfit.lvds_border_bits =
5012                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5013 }
5014
5015 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5016                                  struct intel_crtc_config *pipe_config)
5017 {
5018         struct drm_device *dev = crtc->base.dev;
5019         struct drm_i915_private *dev_priv = dev->dev_private;
5020         uint32_t tmp;
5021
5022         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5023         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5024
5025         tmp = I915_READ(PIPECONF(crtc->pipe));
5026         if (!(tmp & PIPECONF_ENABLE))
5027                 return false;
5028
5029         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5030                 switch (tmp & PIPECONF_BPC_MASK) {
5031                 case PIPECONF_6BPC:
5032                         pipe_config->pipe_bpp = 18;
5033                         break;
5034                 case PIPECONF_8BPC:
5035                         pipe_config->pipe_bpp = 24;
5036                         break;
5037                 case PIPECONF_10BPC:
5038                         pipe_config->pipe_bpp = 30;
5039                         break;
5040                 default:
5041                         break;
5042                 }
5043         }
5044
5045         if (INTEL_INFO(dev)->gen < 4)
5046                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5047
5048         intel_get_pipe_timings(crtc, pipe_config);
5049
5050         i9xx_get_pfit_config(crtc, pipe_config);
5051
5052         if (INTEL_INFO(dev)->gen >= 4) {
5053                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5054                 pipe_config->pixel_multiplier =
5055                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5056                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5057                 pipe_config->dpll_hw_state.dpll_md = tmp;
5058         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5059                 tmp = I915_READ(DPLL(crtc->pipe));
5060                 pipe_config->pixel_multiplier =
5061                         ((tmp & SDVO_MULTIPLIER_MASK)
5062                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5063         } else {
5064                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5065                  * port and will be fixed up in the encoder->get_config
5066                  * function. */
5067                 pipe_config->pixel_multiplier = 1;
5068         }
5069         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5070         if (!IS_VALLEYVIEW(dev)) {
5071                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5072                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5073         } else {
5074                 /* Mask out read-only status bits. */
5075                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5076                                                      DPLL_PORTC_READY_MASK |
5077                                                      DPLL_PORTB_READY_MASK);
5078         }
5079
5080         i9xx_crtc_clock_get(crtc, pipe_config);
5081
5082         return true;
5083 }
5084
5085 static void ironlake_init_pch_refclk(struct drm_device *dev)
5086 {
5087         struct drm_i915_private *dev_priv = dev->dev_private;
5088         struct drm_mode_config *mode_config = &dev->mode_config;
5089         struct intel_encoder *encoder;
5090         u32 val, final;
5091         bool has_lvds = false;
5092         bool has_cpu_edp = false;
5093         bool has_panel = false;
5094         bool has_ck505 = false;
5095         bool can_ssc = false;
5096
5097         /* We need to take the global config into account */
5098         list_for_each_entry(encoder, &mode_config->encoder_list,
5099                             base.head) {
5100                 switch (encoder->type) {
5101                 case INTEL_OUTPUT_LVDS:
5102                         has_panel = true;
5103                         has_lvds = true;
5104                         break;
5105                 case INTEL_OUTPUT_EDP:
5106                         has_panel = true;
5107                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5108                                 has_cpu_edp = true;
5109                         break;
5110                 }
5111         }
5112
5113         if (HAS_PCH_IBX(dev)) {
5114                 has_ck505 = dev_priv->vbt.display_clock_mode;
5115                 can_ssc = has_ck505;
5116         } else {
5117                 has_ck505 = false;
5118                 can_ssc = true;
5119         }
5120
5121         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5122                       has_panel, has_lvds, has_ck505);
5123
5124         /* Ironlake: try to setup display ref clock before DPLL
5125          * enabling. This is only under driver's control after
5126          * PCH B stepping, previous chipset stepping should be
5127          * ignoring this setting.
5128          */
5129         val = I915_READ(PCH_DREF_CONTROL);
5130
5131         /* As we must carefully and slowly disable/enable each source in turn,
5132          * compute the final state we want first and check if we need to
5133          * make any changes at all.
5134          */
5135         final = val;
5136         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5137         if (has_ck505)
5138                 final |= DREF_NONSPREAD_CK505_ENABLE;
5139         else
5140                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5141
5142         final &= ~DREF_SSC_SOURCE_MASK;
5143         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5144         final &= ~DREF_SSC1_ENABLE;
5145
5146         if (has_panel) {
5147                 final |= DREF_SSC_SOURCE_ENABLE;
5148
5149                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5150                         final |= DREF_SSC1_ENABLE;
5151
5152                 if (has_cpu_edp) {
5153                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5154                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5155                         else
5156                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5157                 } else
5158                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5159         } else {
5160                 final |= DREF_SSC_SOURCE_DISABLE;
5161                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5162         }
5163
5164         if (final == val)
5165                 return;
5166
5167         /* Always enable nonspread source */
5168         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5169
5170         if (has_ck505)
5171                 val |= DREF_NONSPREAD_CK505_ENABLE;
5172         else
5173                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5174
5175         if (has_panel) {
5176                 val &= ~DREF_SSC_SOURCE_MASK;
5177                 val |= DREF_SSC_SOURCE_ENABLE;
5178
5179                 /* SSC must be turned on before enabling the CPU output  */
5180                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5181                         DRM_DEBUG_KMS("Using SSC on panel\n");
5182                         val |= DREF_SSC1_ENABLE;
5183                 } else
5184                         val &= ~DREF_SSC1_ENABLE;
5185
5186                 /* Get SSC going before enabling the outputs */
5187                 I915_WRITE(PCH_DREF_CONTROL, val);
5188                 POSTING_READ(PCH_DREF_CONTROL);
5189                 udelay(200);
5190
5191                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5192
5193                 /* Enable CPU source on CPU attached eDP */
5194                 if (has_cpu_edp) {
5195                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5196                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5197                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5198                         }
5199                         else
5200                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5201                 } else
5202                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5203
5204                 I915_WRITE(PCH_DREF_CONTROL, val);
5205                 POSTING_READ(PCH_DREF_CONTROL);
5206                 udelay(200);
5207         } else {
5208                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5209
5210                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5211
5212                 /* Turn off CPU output */
5213                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5214
5215                 I915_WRITE(PCH_DREF_CONTROL, val);
5216                 POSTING_READ(PCH_DREF_CONTROL);
5217                 udelay(200);
5218
5219                 /* Turn off the SSC source */
5220                 val &= ~DREF_SSC_SOURCE_MASK;
5221                 val |= DREF_SSC_SOURCE_DISABLE;
5222
5223                 /* Turn off SSC1 */
5224                 val &= ~DREF_SSC1_ENABLE;
5225
5226                 I915_WRITE(PCH_DREF_CONTROL, val);
5227                 POSTING_READ(PCH_DREF_CONTROL);
5228                 udelay(200);
5229         }
5230
5231         BUG_ON(val != final);
5232 }
5233
5234 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5235 {
5236         uint32_t tmp;
5237
5238         tmp = I915_READ(SOUTH_CHICKEN2);
5239         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5240         I915_WRITE(SOUTH_CHICKEN2, tmp);
5241
5242         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5243                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5244                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5245
5246         tmp = I915_READ(SOUTH_CHICKEN2);
5247         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5248         I915_WRITE(SOUTH_CHICKEN2, tmp);
5249
5250         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5251                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5252                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5253 }
5254
5255 /* WaMPhyProgramming:hsw */
5256 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5257 {
5258         uint32_t tmp;
5259
5260         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5261         tmp &= ~(0xFF << 24);
5262         tmp |= (0x12 << 24);
5263         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5264
5265         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5266         tmp |= (1 << 11);
5267         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5268
5269         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5270         tmp |= (1 << 11);
5271         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5272
5273         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5274         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5275         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5276
5277         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5278         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5279         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5280
5281         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5282         tmp &= ~(7 << 13);
5283         tmp |= (5 << 13);
5284         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5285
5286         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5287         tmp &= ~(7 << 13);
5288         tmp |= (5 << 13);
5289         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5290
5291         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5292         tmp &= ~0xFF;
5293         tmp |= 0x1C;
5294         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5295
5296         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5297         tmp &= ~0xFF;
5298         tmp |= 0x1C;
5299         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5300
5301         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5302         tmp &= ~(0xFF << 16);
5303         tmp |= (0x1C << 16);
5304         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5305
5306         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5307         tmp &= ~(0xFF << 16);
5308         tmp |= (0x1C << 16);
5309         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5310
5311         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5312         tmp |= (1 << 27);
5313         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5314
5315         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5316         tmp |= (1 << 27);
5317         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5318
5319         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5320         tmp &= ~(0xF << 28);
5321         tmp |= (4 << 28);
5322         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5323
5324         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5325         tmp &= ~(0xF << 28);
5326         tmp |= (4 << 28);
5327         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5328 }
5329
5330 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5331  * Programming" based on the parameters passed:
5332  * - Sequence to enable CLKOUT_DP
5333  * - Sequence to enable CLKOUT_DP without spread
5334  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5335  */
5336 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5337                                  bool with_fdi)
5338 {
5339         struct drm_i915_private *dev_priv = dev->dev_private;
5340         uint32_t reg, tmp;
5341
5342         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5343                 with_spread = true;
5344         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5345                  with_fdi, "LP PCH doesn't have FDI\n"))
5346                 with_fdi = false;
5347
5348         mutex_lock(&dev_priv->dpio_lock);
5349
5350         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5351         tmp &= ~SBI_SSCCTL_DISABLE;
5352         tmp |= SBI_SSCCTL_PATHALT;
5353         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5354
5355         udelay(24);
5356
5357         if (with_spread) {
5358                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5359                 tmp &= ~SBI_SSCCTL_PATHALT;
5360                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5361
5362                 if (with_fdi) {
5363                         lpt_reset_fdi_mphy(dev_priv);
5364                         lpt_program_fdi_mphy(dev_priv);
5365                 }
5366         }
5367
5368         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5369                SBI_GEN0 : SBI_DBUFF0;
5370         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5371         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5372         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5373
5374         mutex_unlock(&dev_priv->dpio_lock);
5375 }
5376
5377 /* Sequence to disable CLKOUT_DP */
5378 static void lpt_disable_clkout_dp(struct drm_device *dev)
5379 {
5380         struct drm_i915_private *dev_priv = dev->dev_private;
5381         uint32_t reg, tmp;
5382
5383         mutex_lock(&dev_priv->dpio_lock);
5384
5385         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5386                SBI_GEN0 : SBI_DBUFF0;
5387         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5388         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5389         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5390
5391         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5392         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5393                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5394                         tmp |= SBI_SSCCTL_PATHALT;
5395                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5396                         udelay(32);
5397                 }
5398                 tmp |= SBI_SSCCTL_DISABLE;
5399                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5400         }
5401
5402         mutex_unlock(&dev_priv->dpio_lock);
5403 }
5404
5405 static void lpt_init_pch_refclk(struct drm_device *dev)
5406 {
5407         struct drm_mode_config *mode_config = &dev->mode_config;
5408         struct intel_encoder *encoder;
5409         bool has_vga = false;
5410
5411         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5412                 switch (encoder->type) {
5413                 case INTEL_OUTPUT_ANALOG:
5414                         has_vga = true;
5415                         break;
5416                 }
5417         }
5418
5419         if (has_vga)
5420                 lpt_enable_clkout_dp(dev, true, true);
5421         else
5422                 lpt_disable_clkout_dp(dev);
5423 }
5424
5425 /*
5426  * Initialize reference clocks when the driver loads
5427  */
5428 void intel_init_pch_refclk(struct drm_device *dev)
5429 {
5430         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5431                 ironlake_init_pch_refclk(dev);
5432         else if (HAS_PCH_LPT(dev))
5433                 lpt_init_pch_refclk(dev);
5434 }
5435
5436 static int ironlake_get_refclk(struct drm_crtc *crtc)
5437 {
5438         struct drm_device *dev = crtc->dev;
5439         struct drm_i915_private *dev_priv = dev->dev_private;
5440         struct intel_encoder *encoder;
5441         int num_connectors = 0;
5442         bool is_lvds = false;
5443
5444         for_each_encoder_on_crtc(dev, crtc, encoder) {
5445                 switch (encoder->type) {
5446                 case INTEL_OUTPUT_LVDS:
5447                         is_lvds = true;
5448                         break;
5449                 }
5450                 num_connectors++;
5451         }
5452
5453         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5454                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5455                               dev_priv->vbt.lvds_ssc_freq);
5456                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5457         }
5458
5459         return 120000;
5460 }
5461
5462 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5463 {
5464         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5466         int pipe = intel_crtc->pipe;
5467         uint32_t val;
5468
5469         val = 0;
5470
5471         switch (intel_crtc->config.pipe_bpp) {
5472         case 18:
5473                 val |= PIPECONF_6BPC;
5474                 break;
5475         case 24:
5476                 val |= PIPECONF_8BPC;
5477                 break;
5478         case 30:
5479                 val |= PIPECONF_10BPC;
5480                 break;
5481         case 36:
5482                 val |= PIPECONF_12BPC;
5483                 break;
5484         default:
5485                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5486                 BUG();
5487         }
5488
5489         if (intel_crtc->config.dither)
5490                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5491
5492         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5493                 val |= PIPECONF_INTERLACED_ILK;
5494         else
5495                 val |= PIPECONF_PROGRESSIVE;
5496
5497         if (intel_crtc->config.limited_color_range)
5498                 val |= PIPECONF_COLOR_RANGE_SELECT;
5499
5500         I915_WRITE(PIPECONF(pipe), val);
5501         POSTING_READ(PIPECONF(pipe));
5502 }
5503
5504 /*
5505  * Set up the pipe CSC unit.
5506  *
5507  * Currently only full range RGB to limited range RGB conversion
5508  * is supported, but eventually this should handle various
5509  * RGB<->YCbCr scenarios as well.
5510  */
5511 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5512 {
5513         struct drm_device *dev = crtc->dev;
5514         struct drm_i915_private *dev_priv = dev->dev_private;
5515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5516         int pipe = intel_crtc->pipe;
5517         uint16_t coeff = 0x7800; /* 1.0 */
5518
5519         /*
5520          * TODO: Check what kind of values actually come out of the pipe
5521          * with these coeff/postoff values and adjust to get the best
5522          * accuracy. Perhaps we even need to take the bpc value into
5523          * consideration.
5524          */
5525
5526         if (intel_crtc->config.limited_color_range)
5527                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5528
5529         /*
5530          * GY/GU and RY/RU should be the other way around according
5531          * to BSpec, but reality doesn't agree. Just set them up in
5532          * a way that results in the correct picture.
5533          */
5534         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5535         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5536
5537         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5538         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5539
5540         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5541         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5542
5543         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5544         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5545         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5546
5547         if (INTEL_INFO(dev)->gen > 6) {
5548                 uint16_t postoff = 0;
5549
5550                 if (intel_crtc->config.limited_color_range)
5551                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5552
5553                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5554                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5555                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5556
5557                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5558         } else {
5559                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5560
5561                 if (intel_crtc->config.limited_color_range)
5562                         mode |= CSC_BLACK_SCREEN_OFFSET;
5563
5564                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5565         }
5566 }
5567
5568 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5569 {
5570         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5571         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5572         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5573         uint32_t val;
5574
5575         val = 0;
5576
5577         if (intel_crtc->config.dither)
5578                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5579
5580         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5581                 val |= PIPECONF_INTERLACED_ILK;
5582         else
5583                 val |= PIPECONF_PROGRESSIVE;
5584
5585         I915_WRITE(PIPECONF(cpu_transcoder), val);
5586         POSTING_READ(PIPECONF(cpu_transcoder));
5587
5588         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5589         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5590 }
5591
5592 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5593                                     intel_clock_t *clock,
5594                                     bool *has_reduced_clock,
5595                                     intel_clock_t *reduced_clock)
5596 {
5597         struct drm_device *dev = crtc->dev;
5598         struct drm_i915_private *dev_priv = dev->dev_private;
5599         struct intel_encoder *intel_encoder;
5600         int refclk;
5601         const intel_limit_t *limit;
5602         bool ret, is_lvds = false;
5603
5604         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5605                 switch (intel_encoder->type) {
5606                 case INTEL_OUTPUT_LVDS:
5607                         is_lvds = true;
5608                         break;
5609                 }
5610         }
5611
5612         refclk = ironlake_get_refclk(crtc);
5613
5614         /*
5615          * Returns a set of divisors for the desired target clock with the given
5616          * refclk, or FALSE.  The returned values represent the clock equation:
5617          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5618          */
5619         limit = intel_limit(crtc, refclk);
5620         ret = dev_priv->display.find_dpll(limit, crtc,
5621                                           to_intel_crtc(crtc)->config.port_clock,
5622                                           refclk, NULL, clock);
5623         if (!ret)
5624                 return false;
5625
5626         if (is_lvds && dev_priv->lvds_downclock_avail) {
5627                 /*
5628                  * Ensure we match the reduced clock's P to the target clock.
5629                  * If the clocks don't match, we can't switch the display clock
5630                  * by using the FP0/FP1. In such case we will disable the LVDS
5631                  * downclock feature.
5632                 */
5633                 *has_reduced_clock =
5634                         dev_priv->display.find_dpll(limit, crtc,
5635                                                     dev_priv->lvds_downclock,
5636                                                     refclk, clock,
5637                                                     reduced_clock);
5638         }
5639
5640         return true;
5641 }
5642
5643 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5644 {
5645         struct drm_i915_private *dev_priv = dev->dev_private;
5646         uint32_t temp;
5647
5648         temp = I915_READ(SOUTH_CHICKEN1);
5649         if (temp & FDI_BC_BIFURCATION_SELECT)
5650                 return;
5651
5652         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5653         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5654
5655         temp |= FDI_BC_BIFURCATION_SELECT;
5656         DRM_DEBUG_KMS("enabling fdi C rx\n");
5657         I915_WRITE(SOUTH_CHICKEN1, temp);
5658         POSTING_READ(SOUTH_CHICKEN1);
5659 }
5660
5661 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5662 {
5663         struct drm_device *dev = intel_crtc->base.dev;
5664         struct drm_i915_private *dev_priv = dev->dev_private;
5665
5666         switch (intel_crtc->pipe) {
5667         case PIPE_A:
5668                 break;
5669         case PIPE_B:
5670                 if (intel_crtc->config.fdi_lanes > 2)
5671                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5672                 else
5673                         cpt_enable_fdi_bc_bifurcation(dev);
5674
5675                 break;
5676         case PIPE_C:
5677                 cpt_enable_fdi_bc_bifurcation(dev);
5678
5679                 break;
5680         default:
5681                 BUG();
5682         }
5683 }
5684
5685 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5686 {
5687         /*
5688          * Account for spread spectrum to avoid
5689          * oversubscribing the link. Max center spread
5690          * is 2.5%; use 5% for safety's sake.
5691          */
5692         u32 bps = target_clock * bpp * 21 / 20;
5693         return bps / (link_bw * 8) + 1;
5694 }
5695
5696 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5697 {
5698         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5699 }
5700
5701 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5702                                       u32 *fp,
5703                                       intel_clock_t *reduced_clock, u32 *fp2)
5704 {
5705         struct drm_crtc *crtc = &intel_crtc->base;
5706         struct drm_device *dev = crtc->dev;
5707         struct drm_i915_private *dev_priv = dev->dev_private;
5708         struct intel_encoder *intel_encoder;
5709         uint32_t dpll;
5710         int factor, num_connectors = 0;
5711         bool is_lvds = false, is_sdvo = false;
5712
5713         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5714                 switch (intel_encoder->type) {
5715                 case INTEL_OUTPUT_LVDS:
5716                         is_lvds = true;
5717                         break;
5718                 case INTEL_OUTPUT_SDVO:
5719                 case INTEL_OUTPUT_HDMI:
5720                         is_sdvo = true;
5721                         break;
5722                 }
5723
5724                 num_connectors++;
5725         }
5726
5727         /* Enable autotuning of the PLL clock (if permissible) */
5728         factor = 21;
5729         if (is_lvds) {
5730                 if ((intel_panel_use_ssc(dev_priv) &&
5731                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5732                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5733                         factor = 25;
5734         } else if (intel_crtc->config.sdvo_tv_clock)
5735                 factor = 20;
5736
5737         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5738                 *fp |= FP_CB_TUNE;
5739
5740         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5741                 *fp2 |= FP_CB_TUNE;
5742
5743         dpll = 0;
5744
5745         if (is_lvds)
5746                 dpll |= DPLLB_MODE_LVDS;
5747         else
5748                 dpll |= DPLLB_MODE_DAC_SERIAL;
5749
5750         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5751                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5752
5753         if (is_sdvo)
5754                 dpll |= DPLL_SDVO_HIGH_SPEED;
5755         if (intel_crtc->config.has_dp_encoder)
5756                 dpll |= DPLL_SDVO_HIGH_SPEED;
5757
5758         /* compute bitmask from p1 value */
5759         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5760         /* also FPA1 */
5761         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5762
5763         switch (intel_crtc->config.dpll.p2) {
5764         case 5:
5765                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5766                 break;
5767         case 7:
5768                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5769                 break;
5770         case 10:
5771                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5772                 break;
5773         case 14:
5774                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5775                 break;
5776         }
5777
5778         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5779                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5780         else
5781                 dpll |= PLL_REF_INPUT_DREFCLK;
5782
5783         return dpll | DPLL_VCO_ENABLE;
5784 }
5785
5786 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5787                                   int x, int y,
5788                                   struct drm_framebuffer *fb)
5789 {
5790         struct drm_device *dev = crtc->dev;
5791         struct drm_i915_private *dev_priv = dev->dev_private;
5792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5793         int pipe = intel_crtc->pipe;
5794         int plane = intel_crtc->plane;
5795         int num_connectors = 0;
5796         intel_clock_t clock, reduced_clock;
5797         u32 dpll = 0, fp = 0, fp2 = 0;
5798         bool ok, has_reduced_clock = false;
5799         bool is_lvds = false;
5800         struct intel_encoder *encoder;
5801         struct intel_shared_dpll *pll;
5802         int ret;
5803
5804         for_each_encoder_on_crtc(dev, crtc, encoder) {
5805                 switch (encoder->type) {
5806                 case INTEL_OUTPUT_LVDS:
5807                         is_lvds = true;
5808                         break;
5809                 }
5810
5811                 num_connectors++;
5812         }
5813
5814         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5815              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5816
5817         ok = ironlake_compute_clocks(crtc, &clock,
5818                                      &has_reduced_clock, &reduced_clock);
5819         if (!ok && !intel_crtc->config.clock_set) {
5820                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5821                 return -EINVAL;
5822         }
5823         /* Compat-code for transition, will disappear. */
5824         if (!intel_crtc->config.clock_set) {
5825                 intel_crtc->config.dpll.n = clock.n;
5826                 intel_crtc->config.dpll.m1 = clock.m1;
5827                 intel_crtc->config.dpll.m2 = clock.m2;
5828                 intel_crtc->config.dpll.p1 = clock.p1;
5829                 intel_crtc->config.dpll.p2 = clock.p2;
5830         }
5831
5832         /* Ensure that the cursor is valid for the new mode before changing... */
5833         intel_crtc_update_cursor(crtc, true);
5834
5835         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5836         if (intel_crtc->config.has_pch_encoder) {
5837                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5838                 if (has_reduced_clock)
5839                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5840
5841                 dpll = ironlake_compute_dpll(intel_crtc,
5842                                              &fp, &reduced_clock,
5843                                              has_reduced_clock ? &fp2 : NULL);
5844
5845                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5846                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5847                 if (has_reduced_clock)
5848                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5849                 else
5850                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5851
5852                 pll = intel_get_shared_dpll(intel_crtc);
5853                 if (pll == NULL) {
5854                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5855                                          pipe_name(pipe));
5856                         return -EINVAL;
5857                 }
5858         } else
5859                 intel_put_shared_dpll(intel_crtc);
5860
5861         if (intel_crtc->config.has_dp_encoder)
5862                 intel_dp_set_m_n(intel_crtc);
5863
5864         if (is_lvds && has_reduced_clock && i915_powersave)
5865                 intel_crtc->lowfreq_avail = true;
5866         else
5867                 intel_crtc->lowfreq_avail = false;
5868
5869         if (intel_crtc->config.has_pch_encoder) {
5870                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5871
5872         }
5873
5874         intel_set_pipe_timings(intel_crtc);
5875
5876         if (intel_crtc->config.has_pch_encoder) {
5877                 intel_cpu_transcoder_set_m_n(intel_crtc,
5878                                              &intel_crtc->config.fdi_m_n);
5879         }
5880
5881         if (IS_IVYBRIDGE(dev))
5882                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5883
5884         ironlake_set_pipeconf(crtc);
5885
5886         /* Set up the display plane register */
5887         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5888         POSTING_READ(DSPCNTR(plane));
5889
5890         ret = intel_pipe_set_base(crtc, x, y, fb);
5891
5892         return ret;
5893 }
5894
5895 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5896                                          struct intel_link_m_n *m_n)
5897 {
5898         struct drm_device *dev = crtc->base.dev;
5899         struct drm_i915_private *dev_priv = dev->dev_private;
5900         enum pipe pipe = crtc->pipe;
5901
5902         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5903         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5904         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5905                 & ~TU_SIZE_MASK;
5906         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5907         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
5908                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5909 }
5910
5911 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5912                                          enum transcoder transcoder,
5913                                          struct intel_link_m_n *m_n)
5914 {
5915         struct drm_device *dev = crtc->base.dev;
5916         struct drm_i915_private *dev_priv = dev->dev_private;
5917         enum pipe pipe = crtc->pipe;
5918
5919         if (INTEL_INFO(dev)->gen >= 5) {
5920                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
5921                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
5922                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5923                         & ~TU_SIZE_MASK;
5924                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5925                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5926                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5927         } else {
5928                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
5929                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
5930                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
5931                         & ~TU_SIZE_MASK;
5932                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
5933                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
5934                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5935         }
5936 }
5937
5938 void intel_dp_get_m_n(struct intel_crtc *crtc,
5939                       struct intel_crtc_config *pipe_config)
5940 {
5941         if (crtc->config.has_pch_encoder)
5942                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5943         else
5944                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5945                                              &pipe_config->dp_m_n);
5946 }
5947
5948 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5949                                         struct intel_crtc_config *pipe_config)
5950 {
5951         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5952                                      &pipe_config->fdi_m_n);
5953 }
5954
5955 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5956                                      struct intel_crtc_config *pipe_config)
5957 {
5958         struct drm_device *dev = crtc->base.dev;
5959         struct drm_i915_private *dev_priv = dev->dev_private;
5960         uint32_t tmp;
5961
5962         tmp = I915_READ(PF_CTL(crtc->pipe));
5963
5964         if (tmp & PF_ENABLE) {
5965                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5966                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5967
5968                 /* We currently do not free assignements of panel fitters on
5969                  * ivb/hsw (since we don't use the higher upscaling modes which
5970                  * differentiates them) so just WARN about this case for now. */
5971                 if (IS_GEN7(dev)) {
5972                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5973                                 PF_PIPE_SEL_IVB(crtc->pipe));
5974                 }
5975         }
5976 }
5977
5978 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5979                                      struct intel_crtc_config *pipe_config)
5980 {
5981         struct drm_device *dev = crtc->base.dev;
5982         struct drm_i915_private *dev_priv = dev->dev_private;
5983         uint32_t tmp;
5984
5985         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5986         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5987
5988         tmp = I915_READ(PIPECONF(crtc->pipe));
5989         if (!(tmp & PIPECONF_ENABLE))
5990                 return false;
5991
5992         switch (tmp & PIPECONF_BPC_MASK) {
5993         case PIPECONF_6BPC:
5994                 pipe_config->pipe_bpp = 18;
5995                 break;
5996         case PIPECONF_8BPC:
5997                 pipe_config->pipe_bpp = 24;
5998                 break;
5999         case PIPECONF_10BPC:
6000                 pipe_config->pipe_bpp = 30;
6001                 break;
6002         case PIPECONF_12BPC:
6003                 pipe_config->pipe_bpp = 36;
6004                 break;
6005         default:
6006                 break;
6007         }
6008
6009         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6010                 struct intel_shared_dpll *pll;
6011
6012                 pipe_config->has_pch_encoder = true;
6013
6014                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6015                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6016                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6017
6018                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6019
6020                 if (HAS_PCH_IBX(dev_priv->dev)) {
6021                         pipe_config->shared_dpll =
6022                                 (enum intel_dpll_id) crtc->pipe;
6023                 } else {
6024                         tmp = I915_READ(PCH_DPLL_SEL);
6025                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6026                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6027                         else
6028                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6029                 }
6030
6031                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6032
6033                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6034                                            &pipe_config->dpll_hw_state));
6035
6036                 tmp = pipe_config->dpll_hw_state.dpll;
6037                 pipe_config->pixel_multiplier =
6038                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6039                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6040
6041                 ironlake_pch_clock_get(crtc, pipe_config);
6042         } else {
6043                 pipe_config->pixel_multiplier = 1;
6044         }
6045
6046         intel_get_pipe_timings(crtc, pipe_config);
6047
6048         ironlake_get_pfit_config(crtc, pipe_config);
6049
6050         return true;
6051 }
6052
6053 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6054 {
6055         struct drm_device *dev = dev_priv->dev;
6056         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6057         struct intel_crtc *crtc;
6058         unsigned long irqflags;
6059         uint32_t val;
6060
6061         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6062                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6063                      pipe_name(crtc->pipe));
6064
6065         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6066         WARN(plls->spll_refcount, "SPLL enabled\n");
6067         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6068         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6069         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6070         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6071              "CPU PWM1 enabled\n");
6072         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6073              "CPU PWM2 enabled\n");
6074         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6075              "PCH PWM1 enabled\n");
6076         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6077              "Utility pin enabled\n");
6078         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6079
6080         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6081         val = I915_READ(DEIMR);
6082         WARN((val & ~DE_PCH_EVENT_IVB) != val,
6083              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6084         val = I915_READ(SDEIMR);
6085         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6086              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6087         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6088 }
6089
6090 /*
6091  * This function implements pieces of two sequences from BSpec:
6092  * - Sequence for display software to disable LCPLL
6093  * - Sequence for display software to allow package C8+
6094  * The steps implemented here are just the steps that actually touch the LCPLL
6095  * register. Callers should take care of disabling all the display engine
6096  * functions, doing the mode unset, fixing interrupts, etc.
6097  */
6098 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6099                        bool switch_to_fclk, bool allow_power_down)
6100 {
6101         uint32_t val;
6102
6103         assert_can_disable_lcpll(dev_priv);
6104
6105         val = I915_READ(LCPLL_CTL);
6106
6107         if (switch_to_fclk) {
6108                 val |= LCPLL_CD_SOURCE_FCLK;
6109                 I915_WRITE(LCPLL_CTL, val);
6110
6111                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6112                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6113                         DRM_ERROR("Switching to FCLK failed\n");
6114
6115                 val = I915_READ(LCPLL_CTL);
6116         }
6117
6118         val |= LCPLL_PLL_DISABLE;
6119         I915_WRITE(LCPLL_CTL, val);
6120         POSTING_READ(LCPLL_CTL);
6121
6122         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6123                 DRM_ERROR("LCPLL still locked\n");
6124
6125         val = I915_READ(D_COMP);
6126         val |= D_COMP_COMP_DISABLE;
6127         I915_WRITE(D_COMP, val);
6128         POSTING_READ(D_COMP);
6129         ndelay(100);
6130
6131         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6132                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6133
6134         if (allow_power_down) {
6135                 val = I915_READ(LCPLL_CTL);
6136                 val |= LCPLL_POWER_DOWN_ALLOW;
6137                 I915_WRITE(LCPLL_CTL, val);
6138                 POSTING_READ(LCPLL_CTL);
6139         }
6140 }
6141
6142 /*
6143  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6144  * source.
6145  */
6146 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6147 {
6148         uint32_t val;
6149
6150         val = I915_READ(LCPLL_CTL);
6151
6152         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6153                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6154                 return;
6155
6156         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6157          * we'll hang the machine! */
6158         dev_priv->uncore.funcs.force_wake_get(dev_priv);
6159
6160         if (val & LCPLL_POWER_DOWN_ALLOW) {
6161                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6162                 I915_WRITE(LCPLL_CTL, val);
6163                 POSTING_READ(LCPLL_CTL);
6164         }
6165
6166         val = I915_READ(D_COMP);
6167         val |= D_COMP_COMP_FORCE;
6168         val &= ~D_COMP_COMP_DISABLE;
6169         I915_WRITE(D_COMP, val);
6170         POSTING_READ(D_COMP);
6171
6172         val = I915_READ(LCPLL_CTL);
6173         val &= ~LCPLL_PLL_DISABLE;
6174         I915_WRITE(LCPLL_CTL, val);
6175
6176         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6177                 DRM_ERROR("LCPLL not locked yet\n");
6178
6179         if (val & LCPLL_CD_SOURCE_FCLK) {
6180                 val = I915_READ(LCPLL_CTL);
6181                 val &= ~LCPLL_CD_SOURCE_FCLK;
6182                 I915_WRITE(LCPLL_CTL, val);
6183
6184                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6185                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6186                         DRM_ERROR("Switching back to LCPLL failed\n");
6187         }
6188
6189         dev_priv->uncore.funcs.force_wake_put(dev_priv);
6190 }
6191
6192 void hsw_enable_pc8_work(struct work_struct *__work)
6193 {
6194         struct drm_i915_private *dev_priv =
6195                 container_of(to_delayed_work(__work), struct drm_i915_private,
6196                              pc8.enable_work);
6197         struct drm_device *dev = dev_priv->dev;
6198         uint32_t val;
6199
6200         if (dev_priv->pc8.enabled)
6201                 return;
6202
6203         DRM_DEBUG_KMS("Enabling package C8+\n");
6204
6205         dev_priv->pc8.enabled = true;
6206
6207         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6208                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6209                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6210                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6211         }
6212
6213         lpt_disable_clkout_dp(dev);
6214         hsw_pc8_disable_interrupts(dev);
6215         hsw_disable_lcpll(dev_priv, true, true);
6216 }
6217
6218 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6219 {
6220         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6221         WARN(dev_priv->pc8.disable_count < 1,
6222              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6223
6224         dev_priv->pc8.disable_count--;
6225         if (dev_priv->pc8.disable_count != 0)
6226                 return;
6227
6228         schedule_delayed_work(&dev_priv->pc8.enable_work,
6229                               msecs_to_jiffies(i915_pc8_timeout));
6230 }
6231
6232 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6233 {
6234         struct drm_device *dev = dev_priv->dev;
6235         uint32_t val;
6236
6237         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6238         WARN(dev_priv->pc8.disable_count < 0,
6239              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6240
6241         dev_priv->pc8.disable_count++;
6242         if (dev_priv->pc8.disable_count != 1)
6243                 return;
6244
6245         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6246         if (!dev_priv->pc8.enabled)
6247                 return;
6248
6249         DRM_DEBUG_KMS("Disabling package C8+\n");
6250
6251         hsw_restore_lcpll(dev_priv);
6252         hsw_pc8_restore_interrupts(dev);
6253         lpt_init_pch_refclk(dev);
6254
6255         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6256                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6257                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6258                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6259         }
6260
6261         intel_prepare_ddi(dev);
6262         i915_gem_init_swizzling(dev);
6263         mutex_lock(&dev_priv->rps.hw_lock);
6264         gen6_update_ring_freq(dev);
6265         mutex_unlock(&dev_priv->rps.hw_lock);
6266         dev_priv->pc8.enabled = false;
6267 }
6268
6269 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6270 {
6271         mutex_lock(&dev_priv->pc8.lock);
6272         __hsw_enable_package_c8(dev_priv);
6273         mutex_unlock(&dev_priv->pc8.lock);
6274 }
6275
6276 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6277 {
6278         mutex_lock(&dev_priv->pc8.lock);
6279         __hsw_disable_package_c8(dev_priv);
6280         mutex_unlock(&dev_priv->pc8.lock);
6281 }
6282
6283 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6284 {
6285         struct drm_device *dev = dev_priv->dev;
6286         struct intel_crtc *crtc;
6287         uint32_t val;
6288
6289         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6290                 if (crtc->base.enabled)
6291                         return false;
6292
6293         /* This case is still possible since we have the i915.disable_power_well
6294          * parameter and also the KVMr or something else might be requesting the
6295          * power well. */
6296         val = I915_READ(HSW_PWR_WELL_DRIVER);
6297         if (val != 0) {
6298                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6299                 return false;
6300         }
6301
6302         return true;
6303 }
6304
6305 /* Since we're called from modeset_global_resources there's no way to
6306  * symmetrically increase and decrease the refcount, so we use
6307  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6308  * or not.
6309  */
6310 static void hsw_update_package_c8(struct drm_device *dev)
6311 {
6312         struct drm_i915_private *dev_priv = dev->dev_private;
6313         bool allow;
6314
6315         if (!i915_enable_pc8)
6316                 return;
6317
6318         mutex_lock(&dev_priv->pc8.lock);
6319
6320         allow = hsw_can_enable_package_c8(dev_priv);
6321
6322         if (allow == dev_priv->pc8.requirements_met)
6323                 goto done;
6324
6325         dev_priv->pc8.requirements_met = allow;
6326
6327         if (allow)
6328                 __hsw_enable_package_c8(dev_priv);
6329         else
6330                 __hsw_disable_package_c8(dev_priv);
6331
6332 done:
6333         mutex_unlock(&dev_priv->pc8.lock);
6334 }
6335
6336 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6337 {
6338         if (!dev_priv->pc8.gpu_idle) {
6339                 dev_priv->pc8.gpu_idle = true;
6340                 hsw_enable_package_c8(dev_priv);
6341         }
6342 }
6343
6344 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6345 {
6346         if (dev_priv->pc8.gpu_idle) {
6347                 dev_priv->pc8.gpu_idle = false;
6348                 hsw_disable_package_c8(dev_priv);
6349         }
6350 }
6351
6352 static void haswell_modeset_global_resources(struct drm_device *dev)
6353 {
6354         bool enable = false;
6355         struct intel_crtc *crtc;
6356
6357         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6358                 if (!crtc->base.enabled)
6359                         continue;
6360
6361                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6362                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6363                         enable = true;
6364         }
6365
6366         intel_set_power_well(dev, enable);
6367
6368         hsw_update_package_c8(dev);
6369 }
6370
6371 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6372                                  int x, int y,
6373                                  struct drm_framebuffer *fb)
6374 {
6375         struct drm_device *dev = crtc->dev;
6376         struct drm_i915_private *dev_priv = dev->dev_private;
6377         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6378         int plane = intel_crtc->plane;
6379         int ret;
6380
6381         if (!intel_ddi_pll_mode_set(crtc))
6382                 return -EINVAL;
6383
6384         /* Ensure that the cursor is valid for the new mode before changing... */
6385         intel_crtc_update_cursor(crtc, true);
6386
6387         if (intel_crtc->config.has_dp_encoder)
6388                 intel_dp_set_m_n(intel_crtc);
6389
6390         intel_crtc->lowfreq_avail = false;
6391
6392         intel_set_pipe_timings(intel_crtc);
6393
6394         if (intel_crtc->config.has_pch_encoder) {
6395                 intel_cpu_transcoder_set_m_n(intel_crtc,
6396                                              &intel_crtc->config.fdi_m_n);
6397         }
6398
6399         haswell_set_pipeconf(crtc);
6400
6401         intel_set_pipe_csc(crtc);
6402
6403         /* Set up the display plane register */
6404         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6405         POSTING_READ(DSPCNTR(plane));
6406
6407         ret = intel_pipe_set_base(crtc, x, y, fb);
6408
6409         return ret;
6410 }
6411
6412 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6413                                     struct intel_crtc_config *pipe_config)
6414 {
6415         struct drm_device *dev = crtc->base.dev;
6416         struct drm_i915_private *dev_priv = dev->dev_private;
6417         enum intel_display_power_domain pfit_domain;
6418         uint32_t tmp;
6419
6420         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6421         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6422
6423         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6424         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6425                 enum pipe trans_edp_pipe;
6426                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6427                 default:
6428                         WARN(1, "unknown pipe linked to edp transcoder\n");
6429                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6430                 case TRANS_DDI_EDP_INPUT_A_ON:
6431                         trans_edp_pipe = PIPE_A;
6432                         break;
6433                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6434                         trans_edp_pipe = PIPE_B;
6435                         break;
6436                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6437                         trans_edp_pipe = PIPE_C;
6438                         break;
6439                 }
6440
6441                 if (trans_edp_pipe == crtc->pipe)
6442                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6443         }
6444
6445         if (!intel_display_power_enabled(dev,
6446                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6447                 return false;
6448
6449         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6450         if (!(tmp & PIPECONF_ENABLE))
6451                 return false;
6452
6453         /*
6454          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6455          * DDI E. So just check whether this pipe is wired to DDI E and whether
6456          * the PCH transcoder is on.
6457          */
6458         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6459         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6460             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6461                 pipe_config->has_pch_encoder = true;
6462
6463                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6464                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6465                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6466
6467                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6468         }
6469
6470         intel_get_pipe_timings(crtc, pipe_config);
6471
6472         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6473         if (intel_display_power_enabled(dev, pfit_domain))
6474                 ironlake_get_pfit_config(crtc, pipe_config);
6475
6476         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6477                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6478
6479         pipe_config->pixel_multiplier = 1;
6480
6481         return true;
6482 }
6483
6484 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6485                                int x, int y,
6486                                struct drm_framebuffer *fb)
6487 {
6488         struct drm_device *dev = crtc->dev;
6489         struct drm_i915_private *dev_priv = dev->dev_private;
6490         struct intel_encoder *encoder;
6491         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6492         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6493         int pipe = intel_crtc->pipe;
6494         int ret;
6495
6496         drm_vblank_pre_modeset(dev, pipe);
6497
6498         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6499
6500         drm_vblank_post_modeset(dev, pipe);
6501
6502         if (ret != 0)
6503                 return ret;
6504
6505         for_each_encoder_on_crtc(dev, crtc, encoder) {
6506                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6507                         encoder->base.base.id,
6508                         drm_get_encoder_name(&encoder->base),
6509                         mode->base.id, mode->name);
6510                 encoder->mode_set(encoder);
6511         }
6512
6513         return 0;
6514 }
6515
6516 static bool intel_eld_uptodate(struct drm_connector *connector,
6517                                int reg_eldv, uint32_t bits_eldv,
6518                                int reg_elda, uint32_t bits_elda,
6519                                int reg_edid)
6520 {
6521         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6522         uint8_t *eld = connector->eld;
6523         uint32_t i;
6524
6525         i = I915_READ(reg_eldv);
6526         i &= bits_eldv;
6527
6528         if (!eld[0])
6529                 return !i;
6530
6531         if (!i)
6532                 return false;
6533
6534         i = I915_READ(reg_elda);
6535         i &= ~bits_elda;
6536         I915_WRITE(reg_elda, i);
6537
6538         for (i = 0; i < eld[2]; i++)
6539                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6540                         return false;
6541
6542         return true;
6543 }
6544
6545 static void g4x_write_eld(struct drm_connector *connector,
6546                           struct drm_crtc *crtc)
6547 {
6548         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6549         uint8_t *eld = connector->eld;
6550         uint32_t eldv;
6551         uint32_t len;
6552         uint32_t i;
6553
6554         i = I915_READ(G4X_AUD_VID_DID);
6555
6556         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6557                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6558         else
6559                 eldv = G4X_ELDV_DEVCTG;
6560
6561         if (intel_eld_uptodate(connector,
6562                                G4X_AUD_CNTL_ST, eldv,
6563                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6564                                G4X_HDMIW_HDMIEDID))
6565                 return;
6566
6567         i = I915_READ(G4X_AUD_CNTL_ST);
6568         i &= ~(eldv | G4X_ELD_ADDR);
6569         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6570         I915_WRITE(G4X_AUD_CNTL_ST, i);
6571
6572         if (!eld[0])
6573                 return;
6574
6575         len = min_t(uint8_t, eld[2], len);
6576         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6577         for (i = 0; i < len; i++)
6578                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6579
6580         i = I915_READ(G4X_AUD_CNTL_ST);
6581         i |= eldv;
6582         I915_WRITE(G4X_AUD_CNTL_ST, i);
6583 }
6584
6585 static void haswell_write_eld(struct drm_connector *connector,
6586                                      struct drm_crtc *crtc)
6587 {
6588         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6589         uint8_t *eld = connector->eld;
6590         struct drm_device *dev = crtc->dev;
6591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6592         uint32_t eldv;
6593         uint32_t i;
6594         int len;
6595         int pipe = to_intel_crtc(crtc)->pipe;
6596         int tmp;
6597
6598         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6599         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6600         int aud_config = HSW_AUD_CFG(pipe);
6601         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6602
6603
6604         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6605
6606         /* Audio output enable */
6607         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6608         tmp = I915_READ(aud_cntrl_st2);
6609         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6610         I915_WRITE(aud_cntrl_st2, tmp);
6611
6612         /* Wait for 1 vertical blank */
6613         intel_wait_for_vblank(dev, pipe);
6614
6615         /* Set ELD valid state */
6616         tmp = I915_READ(aud_cntrl_st2);
6617         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6618         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6619         I915_WRITE(aud_cntrl_st2, tmp);
6620         tmp = I915_READ(aud_cntrl_st2);
6621         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6622
6623         /* Enable HDMI mode */
6624         tmp = I915_READ(aud_config);
6625         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6626         /* clear N_programing_enable and N_value_index */
6627         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6628         I915_WRITE(aud_config, tmp);
6629
6630         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6631
6632         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6633         intel_crtc->eld_vld = true;
6634
6635         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6636                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6637                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6638                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6639         } else
6640                 I915_WRITE(aud_config, 0);
6641
6642         if (intel_eld_uptodate(connector,
6643                                aud_cntrl_st2, eldv,
6644                                aud_cntl_st, IBX_ELD_ADDRESS,
6645                                hdmiw_hdmiedid))
6646                 return;
6647
6648         i = I915_READ(aud_cntrl_st2);
6649         i &= ~eldv;
6650         I915_WRITE(aud_cntrl_st2, i);
6651
6652         if (!eld[0])
6653                 return;
6654
6655         i = I915_READ(aud_cntl_st);
6656         i &= ~IBX_ELD_ADDRESS;
6657         I915_WRITE(aud_cntl_st, i);
6658         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6659         DRM_DEBUG_DRIVER("port num:%d\n", i);
6660
6661         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6662         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6663         for (i = 0; i < len; i++)
6664                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6665
6666         i = I915_READ(aud_cntrl_st2);
6667         i |= eldv;
6668         I915_WRITE(aud_cntrl_st2, i);
6669
6670 }
6671
6672 static void ironlake_write_eld(struct drm_connector *connector,
6673                                      struct drm_crtc *crtc)
6674 {
6675         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6676         uint8_t *eld = connector->eld;
6677         uint32_t eldv;
6678         uint32_t i;
6679         int len;
6680         int hdmiw_hdmiedid;
6681         int aud_config;
6682         int aud_cntl_st;
6683         int aud_cntrl_st2;
6684         int pipe = to_intel_crtc(crtc)->pipe;
6685
6686         if (HAS_PCH_IBX(connector->dev)) {
6687                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6688                 aud_config = IBX_AUD_CFG(pipe);
6689                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6690                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6691         } else {
6692                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6693                 aud_config = CPT_AUD_CFG(pipe);
6694                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6695                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6696         }
6697
6698         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6699
6700         i = I915_READ(aud_cntl_st);
6701         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6702         if (!i) {
6703                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6704                 /* operate blindly on all ports */
6705                 eldv = IBX_ELD_VALIDB;
6706                 eldv |= IBX_ELD_VALIDB << 4;
6707                 eldv |= IBX_ELD_VALIDB << 8;
6708         } else {
6709                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6710                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6711         }
6712
6713         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6714                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6715                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6716                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6717         } else
6718                 I915_WRITE(aud_config, 0);
6719
6720         if (intel_eld_uptodate(connector,
6721                                aud_cntrl_st2, eldv,
6722                                aud_cntl_st, IBX_ELD_ADDRESS,
6723                                hdmiw_hdmiedid))
6724                 return;
6725
6726         i = I915_READ(aud_cntrl_st2);
6727         i &= ~eldv;
6728         I915_WRITE(aud_cntrl_st2, i);
6729
6730         if (!eld[0])
6731                 return;
6732
6733         i = I915_READ(aud_cntl_st);
6734         i &= ~IBX_ELD_ADDRESS;
6735         I915_WRITE(aud_cntl_st, i);
6736
6737         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6738         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6739         for (i = 0; i < len; i++)
6740                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6741
6742         i = I915_READ(aud_cntrl_st2);
6743         i |= eldv;
6744         I915_WRITE(aud_cntrl_st2, i);
6745 }
6746
6747 void intel_write_eld(struct drm_encoder *encoder,
6748                      struct drm_display_mode *mode)
6749 {
6750         struct drm_crtc *crtc = encoder->crtc;
6751         struct drm_connector *connector;
6752         struct drm_device *dev = encoder->dev;
6753         struct drm_i915_private *dev_priv = dev->dev_private;
6754
6755         connector = drm_select_eld(encoder, mode);
6756         if (!connector)
6757                 return;
6758
6759         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6760                          connector->base.id,
6761                          drm_get_connector_name(connector),
6762                          connector->encoder->base.id,
6763                          drm_get_encoder_name(connector->encoder));
6764
6765         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6766
6767         if (dev_priv->display.write_eld)
6768                 dev_priv->display.write_eld(connector, crtc);
6769 }
6770
6771 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6772 void intel_crtc_load_lut(struct drm_crtc *crtc)
6773 {
6774         struct drm_device *dev = crtc->dev;
6775         struct drm_i915_private *dev_priv = dev->dev_private;
6776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6777         enum pipe pipe = intel_crtc->pipe;
6778         int palreg = PALETTE(pipe);
6779         int i;
6780         bool reenable_ips = false;
6781
6782         /* The clocks have to be on to load the palette. */
6783         if (!crtc->enabled || !intel_crtc->active)
6784                 return;
6785
6786         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6787                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6788                         assert_dsi_pll_enabled(dev_priv);
6789                 else
6790                         assert_pll_enabled(dev_priv, pipe);
6791         }
6792
6793         /* use legacy palette for Ironlake */
6794         if (HAS_PCH_SPLIT(dev))
6795                 palreg = LGC_PALETTE(pipe);
6796
6797         /* Workaround : Do not read or write the pipe palette/gamma data while
6798          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6799          */
6800         if (intel_crtc->config.ips_enabled &&
6801             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6802              GAMMA_MODE_MODE_SPLIT)) {
6803                 hsw_disable_ips(intel_crtc);
6804                 reenable_ips = true;
6805         }
6806
6807         for (i = 0; i < 256; i++) {
6808                 I915_WRITE(palreg + 4 * i,
6809                            (intel_crtc->lut_r[i] << 16) |
6810                            (intel_crtc->lut_g[i] << 8) |
6811                            intel_crtc->lut_b[i]);
6812         }
6813
6814         if (reenable_ips)
6815                 hsw_enable_ips(intel_crtc);
6816 }
6817
6818 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6819 {
6820         struct drm_device *dev = crtc->dev;
6821         struct drm_i915_private *dev_priv = dev->dev_private;
6822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6823         bool visible = base != 0;
6824         u32 cntl;
6825
6826         if (intel_crtc->cursor_visible == visible)
6827                 return;
6828
6829         cntl = I915_READ(_CURACNTR);
6830         if (visible) {
6831                 /* On these chipsets we can only modify the base whilst
6832                  * the cursor is disabled.
6833                  */
6834                 I915_WRITE(_CURABASE, base);
6835
6836                 cntl &= ~(CURSOR_FORMAT_MASK);
6837                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6838                 cntl |= CURSOR_ENABLE |
6839                         CURSOR_GAMMA_ENABLE |
6840                         CURSOR_FORMAT_ARGB;
6841         } else
6842                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6843         I915_WRITE(_CURACNTR, cntl);
6844
6845         intel_crtc->cursor_visible = visible;
6846 }
6847
6848 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6849 {
6850         struct drm_device *dev = crtc->dev;
6851         struct drm_i915_private *dev_priv = dev->dev_private;
6852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6853         int pipe = intel_crtc->pipe;
6854         bool visible = base != 0;
6855
6856         if (intel_crtc->cursor_visible != visible) {
6857                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6858                 if (base) {
6859                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6860                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6861                         cntl |= pipe << 28; /* Connect to correct pipe */
6862                 } else {
6863                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6864                         cntl |= CURSOR_MODE_DISABLE;
6865                 }
6866                 I915_WRITE(CURCNTR(pipe), cntl);
6867
6868                 intel_crtc->cursor_visible = visible;
6869         }
6870         /* and commit changes on next vblank */
6871         I915_WRITE(CURBASE(pipe), base);
6872 }
6873
6874 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6875 {
6876         struct drm_device *dev = crtc->dev;
6877         struct drm_i915_private *dev_priv = dev->dev_private;
6878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6879         int pipe = intel_crtc->pipe;
6880         bool visible = base != 0;
6881
6882         if (intel_crtc->cursor_visible != visible) {
6883                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6884                 if (base) {
6885                         cntl &= ~CURSOR_MODE;
6886                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6887                 } else {
6888                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6889                         cntl |= CURSOR_MODE_DISABLE;
6890                 }
6891                 if (IS_HASWELL(dev)) {
6892                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6893                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6894                 }
6895                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6896
6897                 intel_crtc->cursor_visible = visible;
6898         }
6899         /* and commit changes on next vblank */
6900         I915_WRITE(CURBASE_IVB(pipe), base);
6901 }
6902
6903 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6904 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6905                                      bool on)
6906 {
6907         struct drm_device *dev = crtc->dev;
6908         struct drm_i915_private *dev_priv = dev->dev_private;
6909         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6910         int pipe = intel_crtc->pipe;
6911         int x = intel_crtc->cursor_x;
6912         int y = intel_crtc->cursor_y;
6913         u32 base = 0, pos = 0;
6914         bool visible;
6915
6916         if (on)
6917                 base = intel_crtc->cursor_addr;
6918
6919         if (x >= intel_crtc->config.pipe_src_w)
6920                 base = 0;
6921
6922         if (y >= intel_crtc->config.pipe_src_h)
6923                 base = 0;
6924
6925         if (x < 0) {
6926                 if (x + intel_crtc->cursor_width <= 0)
6927                         base = 0;
6928
6929                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6930                 x = -x;
6931         }
6932         pos |= x << CURSOR_X_SHIFT;
6933
6934         if (y < 0) {
6935                 if (y + intel_crtc->cursor_height <= 0)
6936                         base = 0;
6937
6938                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6939                 y = -y;
6940         }
6941         pos |= y << CURSOR_Y_SHIFT;
6942
6943         visible = base != 0;
6944         if (!visible && !intel_crtc->cursor_visible)
6945                 return;
6946
6947         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6948                 I915_WRITE(CURPOS_IVB(pipe), pos);
6949                 ivb_update_cursor(crtc, base);
6950         } else {
6951                 I915_WRITE(CURPOS(pipe), pos);
6952                 if (IS_845G(dev) || IS_I865G(dev))
6953                         i845_update_cursor(crtc, base);
6954                 else
6955                         i9xx_update_cursor(crtc, base);
6956         }
6957 }
6958
6959 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6960                                  struct drm_file *file,
6961                                  uint32_t handle,
6962                                  uint32_t width, uint32_t height)
6963 {
6964         struct drm_device *dev = crtc->dev;
6965         struct drm_i915_private *dev_priv = dev->dev_private;
6966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6967         struct drm_i915_gem_object *obj;
6968         uint32_t addr;
6969         int ret;
6970
6971         /* if we want to turn off the cursor ignore width and height */
6972         if (!handle) {
6973                 DRM_DEBUG_KMS("cursor off\n");
6974                 addr = 0;
6975                 obj = NULL;
6976                 mutex_lock(&dev->struct_mutex);
6977                 goto finish;
6978         }
6979
6980         /* Currently we only support 64x64 cursors */
6981         if (width != 64 || height != 64) {
6982                 DRM_ERROR("we currently only support 64x64 cursors\n");
6983                 return -EINVAL;
6984         }
6985
6986         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6987         if (&obj->base == NULL)
6988                 return -ENOENT;
6989
6990         if (obj->base.size < width * height * 4) {
6991                 DRM_ERROR("buffer is to small\n");
6992                 ret = -ENOMEM;
6993                 goto fail;
6994         }
6995
6996         /* we only need to pin inside GTT if cursor is non-phy */
6997         mutex_lock(&dev->struct_mutex);
6998         if (!dev_priv->info->cursor_needs_physical) {
6999                 unsigned alignment;
7000
7001                 if (obj->tiling_mode) {
7002                         DRM_ERROR("cursor cannot be tiled\n");
7003                         ret = -EINVAL;
7004                         goto fail_locked;
7005                 }
7006
7007                 /* Note that the w/a also requires 2 PTE of padding following
7008                  * the bo. We currently fill all unused PTE with the shadow
7009                  * page and so we should always have valid PTE following the
7010                  * cursor preventing the VT-d warning.
7011                  */
7012                 alignment = 0;
7013                 if (need_vtd_wa(dev))
7014                         alignment = 64*1024;
7015
7016                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7017                 if (ret) {
7018                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7019                         goto fail_locked;
7020                 }
7021
7022                 ret = i915_gem_object_put_fence(obj);
7023                 if (ret) {
7024                         DRM_ERROR("failed to release fence for cursor");
7025                         goto fail_unpin;
7026                 }
7027
7028                 addr = i915_gem_obj_ggtt_offset(obj);
7029         } else {
7030                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7031                 ret = i915_gem_attach_phys_object(dev, obj,
7032                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7033                                                   align);
7034                 if (ret) {
7035                         DRM_ERROR("failed to attach phys object\n");
7036                         goto fail_locked;
7037                 }
7038                 addr = obj->phys_obj->handle->busaddr;
7039         }
7040
7041         if (IS_GEN2(dev))
7042                 I915_WRITE(CURSIZE, (height << 12) | width);
7043
7044  finish:
7045         if (intel_crtc->cursor_bo) {
7046                 if (dev_priv->info->cursor_needs_physical) {
7047                         if (intel_crtc->cursor_bo != obj)
7048                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7049                 } else
7050                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7051                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7052         }
7053
7054         mutex_unlock(&dev->struct_mutex);
7055
7056         intel_crtc->cursor_addr = addr;
7057         intel_crtc->cursor_bo = obj;
7058         intel_crtc->cursor_width = width;
7059         intel_crtc->cursor_height = height;
7060
7061         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7062
7063         return 0;
7064 fail_unpin:
7065         i915_gem_object_unpin_from_display_plane(obj);
7066 fail_locked:
7067         mutex_unlock(&dev->struct_mutex);
7068 fail:
7069         drm_gem_object_unreference_unlocked(&obj->base);
7070         return ret;
7071 }
7072
7073 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7074 {
7075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7076
7077         intel_crtc->cursor_x = x;
7078         intel_crtc->cursor_y = y;
7079
7080         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7081
7082         return 0;
7083 }
7084
7085 /** Sets the color ramps on behalf of RandR */
7086 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7087                                  u16 blue, int regno)
7088 {
7089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7090
7091         intel_crtc->lut_r[regno] = red >> 8;
7092         intel_crtc->lut_g[regno] = green >> 8;
7093         intel_crtc->lut_b[regno] = blue >> 8;
7094 }
7095
7096 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7097                              u16 *blue, int regno)
7098 {
7099         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7100
7101         *red = intel_crtc->lut_r[regno] << 8;
7102         *green = intel_crtc->lut_g[regno] << 8;
7103         *blue = intel_crtc->lut_b[regno] << 8;
7104 }
7105
7106 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7107                                  u16 *blue, uint32_t start, uint32_t size)
7108 {
7109         int end = (start + size > 256) ? 256 : start + size, i;
7110         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7111
7112         for (i = start; i < end; i++) {
7113                 intel_crtc->lut_r[i] = red[i] >> 8;
7114                 intel_crtc->lut_g[i] = green[i] >> 8;
7115                 intel_crtc->lut_b[i] = blue[i] >> 8;
7116         }
7117
7118         intel_crtc_load_lut(crtc);
7119 }
7120
7121 /* VESA 640x480x72Hz mode to set on the pipe */
7122 static struct drm_display_mode load_detect_mode = {
7123         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7124                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7125 };
7126
7127 static struct drm_framebuffer *
7128 intel_framebuffer_create(struct drm_device *dev,
7129                          struct drm_mode_fb_cmd2 *mode_cmd,
7130                          struct drm_i915_gem_object *obj)
7131 {
7132         struct intel_framebuffer *intel_fb;
7133         int ret;
7134
7135         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7136         if (!intel_fb) {
7137                 drm_gem_object_unreference_unlocked(&obj->base);
7138                 return ERR_PTR(-ENOMEM);
7139         }
7140
7141         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7142         if (ret) {
7143                 drm_gem_object_unreference_unlocked(&obj->base);
7144                 kfree(intel_fb);
7145                 return ERR_PTR(ret);
7146         }
7147
7148         return &intel_fb->base;
7149 }
7150
7151 static u32
7152 intel_framebuffer_pitch_for_width(int width, int bpp)
7153 {
7154         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7155         return ALIGN(pitch, 64);
7156 }
7157
7158 static u32
7159 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7160 {
7161         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7162         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7163 }
7164
7165 static struct drm_framebuffer *
7166 intel_framebuffer_create_for_mode(struct drm_device *dev,
7167                                   struct drm_display_mode *mode,
7168                                   int depth, int bpp)
7169 {
7170         struct drm_i915_gem_object *obj;
7171         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7172
7173         obj = i915_gem_alloc_object(dev,
7174                                     intel_framebuffer_size_for_mode(mode, bpp));
7175         if (obj == NULL)
7176                 return ERR_PTR(-ENOMEM);
7177
7178         mode_cmd.width = mode->hdisplay;
7179         mode_cmd.height = mode->vdisplay;
7180         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7181                                                                 bpp);
7182         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7183
7184         return intel_framebuffer_create(dev, &mode_cmd, obj);
7185 }
7186
7187 static struct drm_framebuffer *
7188 mode_fits_in_fbdev(struct drm_device *dev,
7189                    struct drm_display_mode *mode)
7190 {
7191         struct drm_i915_private *dev_priv = dev->dev_private;
7192         struct drm_i915_gem_object *obj;
7193         struct drm_framebuffer *fb;
7194
7195         if (dev_priv->fbdev == NULL)
7196                 return NULL;
7197
7198         obj = dev_priv->fbdev->ifb.obj;
7199         if (obj == NULL)
7200                 return NULL;
7201
7202         fb = &dev_priv->fbdev->ifb.base;
7203         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7204                                                                fb->bits_per_pixel))
7205                 return NULL;
7206
7207         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7208                 return NULL;
7209
7210         return fb;
7211 }
7212
7213 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7214                                 struct drm_display_mode *mode,
7215                                 struct intel_load_detect_pipe *old)
7216 {
7217         struct intel_crtc *intel_crtc;
7218         struct intel_encoder *intel_encoder =
7219                 intel_attached_encoder(connector);
7220         struct drm_crtc *possible_crtc;
7221         struct drm_encoder *encoder = &intel_encoder->base;
7222         struct drm_crtc *crtc = NULL;
7223         struct drm_device *dev = encoder->dev;
7224         struct drm_framebuffer *fb;
7225         int i = -1;
7226
7227         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7228                       connector->base.id, drm_get_connector_name(connector),
7229                       encoder->base.id, drm_get_encoder_name(encoder));
7230
7231         /*
7232          * Algorithm gets a little messy:
7233          *
7234          *   - if the connector already has an assigned crtc, use it (but make
7235          *     sure it's on first)
7236          *
7237          *   - try to find the first unused crtc that can drive this connector,
7238          *     and use that if we find one
7239          */
7240
7241         /* See if we already have a CRTC for this connector */
7242         if (encoder->crtc) {
7243                 crtc = encoder->crtc;
7244
7245                 mutex_lock(&crtc->mutex);
7246
7247                 old->dpms_mode = connector->dpms;
7248                 old->load_detect_temp = false;
7249
7250                 /* Make sure the crtc and connector are running */
7251                 if (connector->dpms != DRM_MODE_DPMS_ON)
7252                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7253
7254                 return true;
7255         }
7256
7257         /* Find an unused one (if possible) */
7258         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7259                 i++;
7260                 if (!(encoder->possible_crtcs & (1 << i)))
7261                         continue;
7262                 if (!possible_crtc->enabled) {
7263                         crtc = possible_crtc;
7264                         break;
7265                 }
7266         }
7267
7268         /*
7269          * If we didn't find an unused CRTC, don't use any.
7270          */
7271         if (!crtc) {
7272                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7273                 return false;
7274         }
7275
7276         mutex_lock(&crtc->mutex);
7277         intel_encoder->new_crtc = to_intel_crtc(crtc);
7278         to_intel_connector(connector)->new_encoder = intel_encoder;
7279
7280         intel_crtc = to_intel_crtc(crtc);
7281         old->dpms_mode = connector->dpms;
7282         old->load_detect_temp = true;
7283         old->release_fb = NULL;
7284
7285         if (!mode)
7286                 mode = &load_detect_mode;
7287
7288         /* We need a framebuffer large enough to accommodate all accesses
7289          * that the plane may generate whilst we perform load detection.
7290          * We can not rely on the fbcon either being present (we get called
7291          * during its initialisation to detect all boot displays, or it may
7292          * not even exist) or that it is large enough to satisfy the
7293          * requested mode.
7294          */
7295         fb = mode_fits_in_fbdev(dev, mode);
7296         if (fb == NULL) {
7297                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7298                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7299                 old->release_fb = fb;
7300         } else
7301                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7302         if (IS_ERR(fb)) {
7303                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7304                 mutex_unlock(&crtc->mutex);
7305                 return false;
7306         }
7307
7308         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7309                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7310                 if (old->release_fb)
7311                         old->release_fb->funcs->destroy(old->release_fb);
7312                 mutex_unlock(&crtc->mutex);
7313                 return false;
7314         }
7315
7316         /* let the connector get through one full cycle before testing */
7317         intel_wait_for_vblank(dev, intel_crtc->pipe);
7318         return true;
7319 }
7320
7321 void intel_release_load_detect_pipe(struct drm_connector *connector,
7322                                     struct intel_load_detect_pipe *old)
7323 {
7324         struct intel_encoder *intel_encoder =
7325                 intel_attached_encoder(connector);
7326         struct drm_encoder *encoder = &intel_encoder->base;
7327         struct drm_crtc *crtc = encoder->crtc;
7328
7329         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7330                       connector->base.id, drm_get_connector_name(connector),
7331                       encoder->base.id, drm_get_encoder_name(encoder));
7332
7333         if (old->load_detect_temp) {
7334                 to_intel_connector(connector)->new_encoder = NULL;
7335                 intel_encoder->new_crtc = NULL;
7336                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7337
7338                 if (old->release_fb) {
7339                         drm_framebuffer_unregister_private(old->release_fb);
7340                         drm_framebuffer_unreference(old->release_fb);
7341                 }
7342
7343                 mutex_unlock(&crtc->mutex);
7344                 return;
7345         }
7346
7347         /* Switch crtc and encoder back off if necessary */
7348         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7349                 connector->funcs->dpms(connector, old->dpms_mode);
7350
7351         mutex_unlock(&crtc->mutex);
7352 }
7353
7354 static int i9xx_pll_refclk(struct drm_device *dev,
7355                            const struct intel_crtc_config *pipe_config)
7356 {
7357         struct drm_i915_private *dev_priv = dev->dev_private;
7358         u32 dpll = pipe_config->dpll_hw_state.dpll;
7359
7360         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7361                 return dev_priv->vbt.lvds_ssc_freq * 1000;
7362         else if (HAS_PCH_SPLIT(dev))
7363                 return 120000;
7364         else if (!IS_GEN2(dev))
7365                 return 96000;
7366         else
7367                 return 48000;
7368 }
7369
7370 /* Returns the clock of the currently programmed mode of the given pipe. */
7371 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7372                                 struct intel_crtc_config *pipe_config)
7373 {
7374         struct drm_device *dev = crtc->base.dev;
7375         struct drm_i915_private *dev_priv = dev->dev_private;
7376         int pipe = pipe_config->cpu_transcoder;
7377         u32 dpll = pipe_config->dpll_hw_state.dpll;
7378         u32 fp;
7379         intel_clock_t clock;
7380         int refclk = i9xx_pll_refclk(dev, pipe_config);
7381
7382         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7383                 fp = pipe_config->dpll_hw_state.fp0;
7384         else
7385                 fp = pipe_config->dpll_hw_state.fp1;
7386
7387         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7388         if (IS_PINEVIEW(dev)) {
7389                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7390                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7391         } else {
7392                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7393                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7394         }
7395
7396         if (!IS_GEN2(dev)) {
7397                 if (IS_PINEVIEW(dev))
7398                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7399                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7400                 else
7401                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7402                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7403
7404                 switch (dpll & DPLL_MODE_MASK) {
7405                 case DPLLB_MODE_DAC_SERIAL:
7406                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7407                                 5 : 10;
7408                         break;
7409                 case DPLLB_MODE_LVDS:
7410                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7411                                 7 : 14;
7412                         break;
7413                 default:
7414                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7415                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7416                         return;
7417                 }
7418
7419                 if (IS_PINEVIEW(dev))
7420                         pineview_clock(refclk, &clock);
7421                 else
7422                         i9xx_clock(refclk, &clock);
7423         } else {
7424                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7425
7426                 if (is_lvds) {
7427                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7428                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7429                         clock.p2 = 14;
7430                 } else {
7431                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7432                                 clock.p1 = 2;
7433                         else {
7434                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7435                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7436                         }
7437                         if (dpll & PLL_P2_DIVIDE_BY_4)
7438                                 clock.p2 = 4;
7439                         else
7440                                 clock.p2 = 2;
7441                 }
7442
7443                 i9xx_clock(refclk, &clock);
7444         }
7445
7446         /*
7447          * This value includes pixel_multiplier. We will use
7448          * port_clock to compute adjusted_mode.clock in the
7449          * encoder's get_config() function.
7450          */
7451         pipe_config->port_clock = clock.dot;
7452 }
7453
7454 int intel_dotclock_calculate(int link_freq,
7455                              const struct intel_link_m_n *m_n)
7456 {
7457         /*
7458          * The calculation for the data clock is:
7459          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7460          * But we want to avoid losing precison if possible, so:
7461          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7462          *
7463          * and the link clock is simpler:
7464          * link_clock = (m * link_clock) / n
7465          */
7466
7467         if (!m_n->link_n)
7468                 return 0;
7469
7470         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7471 }
7472
7473 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7474                                    struct intel_crtc_config *pipe_config)
7475 {
7476         struct drm_device *dev = crtc->base.dev;
7477
7478         /* read out port_clock from the DPLL */
7479         i9xx_crtc_clock_get(crtc, pipe_config);
7480
7481         /*
7482          * This value does not include pixel_multiplier.
7483          * We will check that port_clock and adjusted_mode.clock
7484          * agree once we know their relationship in the encoder's
7485          * get_config() function.
7486          */
7487         pipe_config->adjusted_mode.clock =
7488                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7489                                          &pipe_config->fdi_m_n);
7490 }
7491
7492 /** Returns the currently programmed mode of the given pipe. */
7493 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7494                                              struct drm_crtc *crtc)
7495 {
7496         struct drm_i915_private *dev_priv = dev->dev_private;
7497         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7498         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7499         struct drm_display_mode *mode;
7500         struct intel_crtc_config pipe_config;
7501         int htot = I915_READ(HTOTAL(cpu_transcoder));
7502         int hsync = I915_READ(HSYNC(cpu_transcoder));
7503         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7504         int vsync = I915_READ(VSYNC(cpu_transcoder));
7505         enum pipe pipe = intel_crtc->pipe;
7506
7507         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7508         if (!mode)
7509                 return NULL;
7510
7511         /*
7512          * Construct a pipe_config sufficient for getting the clock info
7513          * back out of crtc_clock_get.
7514          *
7515          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7516          * to use a real value here instead.
7517          */
7518         pipe_config.cpu_transcoder = (enum transcoder) pipe;
7519         pipe_config.pixel_multiplier = 1;
7520         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7521         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7522         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7523         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7524
7525         mode->clock = pipe_config.adjusted_mode.clock;
7526         mode->hdisplay = (htot & 0xffff) + 1;
7527         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7528         mode->hsync_start = (hsync & 0xffff) + 1;
7529         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7530         mode->vdisplay = (vtot & 0xffff) + 1;
7531         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7532         mode->vsync_start = (vsync & 0xffff) + 1;
7533         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7534
7535         drm_mode_set_name(mode);
7536
7537         return mode;
7538 }
7539
7540 static void intel_increase_pllclock(struct drm_crtc *crtc)
7541 {
7542         struct drm_device *dev = crtc->dev;
7543         drm_i915_private_t *dev_priv = dev->dev_private;
7544         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7545         int pipe = intel_crtc->pipe;
7546         int dpll_reg = DPLL(pipe);
7547         int dpll;
7548
7549         if (HAS_PCH_SPLIT(dev))
7550                 return;
7551
7552         if (!dev_priv->lvds_downclock_avail)
7553                 return;
7554
7555         dpll = I915_READ(dpll_reg);
7556         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7557                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7558
7559                 assert_panel_unlocked(dev_priv, pipe);
7560
7561                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7562                 I915_WRITE(dpll_reg, dpll);
7563                 intel_wait_for_vblank(dev, pipe);
7564
7565                 dpll = I915_READ(dpll_reg);
7566                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7567                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7568         }
7569 }
7570
7571 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7572 {
7573         struct drm_device *dev = crtc->dev;
7574         drm_i915_private_t *dev_priv = dev->dev_private;
7575         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7576
7577         if (HAS_PCH_SPLIT(dev))
7578                 return;
7579
7580         if (!dev_priv->lvds_downclock_avail)
7581                 return;
7582
7583         /*
7584          * Since this is called by a timer, we should never get here in
7585          * the manual case.
7586          */
7587         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7588                 int pipe = intel_crtc->pipe;
7589                 int dpll_reg = DPLL(pipe);
7590                 int dpll;
7591
7592                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7593
7594                 assert_panel_unlocked(dev_priv, pipe);
7595
7596                 dpll = I915_READ(dpll_reg);
7597                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7598                 I915_WRITE(dpll_reg, dpll);
7599                 intel_wait_for_vblank(dev, pipe);
7600                 dpll = I915_READ(dpll_reg);
7601                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7602                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7603         }
7604
7605 }
7606
7607 void intel_mark_busy(struct drm_device *dev)
7608 {
7609         struct drm_i915_private *dev_priv = dev->dev_private;
7610
7611         hsw_package_c8_gpu_busy(dev_priv);
7612         i915_update_gfx_val(dev_priv);
7613 }
7614
7615 void intel_mark_idle(struct drm_device *dev)
7616 {
7617         struct drm_i915_private *dev_priv = dev->dev_private;
7618         struct drm_crtc *crtc;
7619
7620         hsw_package_c8_gpu_idle(dev_priv);
7621
7622         if (!i915_powersave)
7623                 return;
7624
7625         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7626                 if (!crtc->fb)
7627                         continue;
7628
7629                 intel_decrease_pllclock(crtc);
7630         }
7631 }
7632
7633 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7634                         struct intel_ring_buffer *ring)
7635 {
7636         struct drm_device *dev = obj->base.dev;
7637         struct drm_crtc *crtc;
7638
7639         if (!i915_powersave)
7640                 return;
7641
7642         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7643                 if (!crtc->fb)
7644                         continue;
7645
7646                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7647                         continue;
7648
7649                 intel_increase_pllclock(crtc);
7650                 if (ring && intel_fbc_enabled(dev))
7651                         ring->fbc_dirty = true;
7652         }
7653 }
7654
7655 static void intel_crtc_destroy(struct drm_crtc *crtc)
7656 {
7657         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7658         struct drm_device *dev = crtc->dev;
7659         struct intel_unpin_work *work;
7660         unsigned long flags;
7661
7662         spin_lock_irqsave(&dev->event_lock, flags);
7663         work = intel_crtc->unpin_work;
7664         intel_crtc->unpin_work = NULL;
7665         spin_unlock_irqrestore(&dev->event_lock, flags);
7666
7667         if (work) {
7668                 cancel_work_sync(&work->work);
7669                 kfree(work);
7670         }
7671
7672         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7673
7674         drm_crtc_cleanup(crtc);
7675
7676         kfree(intel_crtc);
7677 }
7678
7679 static void intel_unpin_work_fn(struct work_struct *__work)
7680 {
7681         struct intel_unpin_work *work =
7682                 container_of(__work, struct intel_unpin_work, work);
7683         struct drm_device *dev = work->crtc->dev;
7684
7685         mutex_lock(&dev->struct_mutex);
7686         intel_unpin_fb_obj(work->old_fb_obj);
7687         drm_gem_object_unreference(&work->pending_flip_obj->base);
7688         drm_gem_object_unreference(&work->old_fb_obj->base);
7689
7690         intel_update_fbc(dev);
7691         mutex_unlock(&dev->struct_mutex);
7692
7693         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7694         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7695
7696         kfree(work);
7697 }
7698
7699 static void do_intel_finish_page_flip(struct drm_device *dev,
7700                                       struct drm_crtc *crtc)
7701 {
7702         drm_i915_private_t *dev_priv = dev->dev_private;
7703         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7704         struct intel_unpin_work *work;
7705         unsigned long flags;
7706
7707         /* Ignore early vblank irqs */
7708         if (intel_crtc == NULL)
7709                 return;
7710
7711         spin_lock_irqsave(&dev->event_lock, flags);
7712         work = intel_crtc->unpin_work;
7713
7714         /* Ensure we don't miss a work->pending update ... */
7715         smp_rmb();
7716
7717         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7718                 spin_unlock_irqrestore(&dev->event_lock, flags);
7719                 return;
7720         }
7721
7722         /* and that the unpin work is consistent wrt ->pending. */
7723         smp_rmb();
7724
7725         intel_crtc->unpin_work = NULL;
7726
7727         if (work->event)
7728                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7729
7730         drm_vblank_put(dev, intel_crtc->pipe);
7731
7732         spin_unlock_irqrestore(&dev->event_lock, flags);
7733
7734         wake_up_all(&dev_priv->pending_flip_queue);
7735
7736         queue_work(dev_priv->wq, &work->work);
7737
7738         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7739 }
7740
7741 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7742 {
7743         drm_i915_private_t *dev_priv = dev->dev_private;
7744         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7745
7746         do_intel_finish_page_flip(dev, crtc);
7747 }
7748
7749 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7750 {
7751         drm_i915_private_t *dev_priv = dev->dev_private;
7752         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7753
7754         do_intel_finish_page_flip(dev, crtc);
7755 }
7756
7757 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7758 {
7759         drm_i915_private_t *dev_priv = dev->dev_private;
7760         struct intel_crtc *intel_crtc =
7761                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7762         unsigned long flags;
7763
7764         /* NB: An MMIO update of the plane base pointer will also
7765          * generate a page-flip completion irq, i.e. every modeset
7766          * is also accompanied by a spurious intel_prepare_page_flip().
7767          */
7768         spin_lock_irqsave(&dev->event_lock, flags);
7769         if (intel_crtc->unpin_work)
7770                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7771         spin_unlock_irqrestore(&dev->event_lock, flags);
7772 }
7773
7774 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7775 {
7776         /* Ensure that the work item is consistent when activating it ... */
7777         smp_wmb();
7778         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7779         /* and that it is marked active as soon as the irq could fire. */
7780         smp_wmb();
7781 }
7782
7783 static int intel_gen2_queue_flip(struct drm_device *dev,
7784                                  struct drm_crtc *crtc,
7785                                  struct drm_framebuffer *fb,
7786                                  struct drm_i915_gem_object *obj,
7787                                  uint32_t flags)
7788 {
7789         struct drm_i915_private *dev_priv = dev->dev_private;
7790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7791         u32 flip_mask;
7792         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7793         int ret;
7794
7795         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7796         if (ret)
7797                 goto err;
7798
7799         ret = intel_ring_begin(ring, 6);
7800         if (ret)
7801                 goto err_unpin;
7802
7803         /* Can't queue multiple flips, so wait for the previous
7804          * one to finish before executing the next.
7805          */
7806         if (intel_crtc->plane)
7807                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7808         else
7809                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7810         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7811         intel_ring_emit(ring, MI_NOOP);
7812         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7813                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7814         intel_ring_emit(ring, fb->pitches[0]);
7815         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7816         intel_ring_emit(ring, 0); /* aux display base address, unused */
7817
7818         intel_mark_page_flip_active(intel_crtc);
7819         __intel_ring_advance(ring);
7820         return 0;
7821
7822 err_unpin:
7823         intel_unpin_fb_obj(obj);
7824 err:
7825         return ret;
7826 }
7827
7828 static int intel_gen3_queue_flip(struct drm_device *dev,
7829                                  struct drm_crtc *crtc,
7830                                  struct drm_framebuffer *fb,
7831                                  struct drm_i915_gem_object *obj,
7832                                  uint32_t flags)
7833 {
7834         struct drm_i915_private *dev_priv = dev->dev_private;
7835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7836         u32 flip_mask;
7837         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7838         int ret;
7839
7840         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7841         if (ret)
7842                 goto err;
7843
7844         ret = intel_ring_begin(ring, 6);
7845         if (ret)
7846                 goto err_unpin;
7847
7848         if (intel_crtc->plane)
7849                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7850         else
7851                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7852         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7853         intel_ring_emit(ring, MI_NOOP);
7854         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7855                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7856         intel_ring_emit(ring, fb->pitches[0]);
7857         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7858         intel_ring_emit(ring, MI_NOOP);
7859
7860         intel_mark_page_flip_active(intel_crtc);
7861         __intel_ring_advance(ring);
7862         return 0;
7863
7864 err_unpin:
7865         intel_unpin_fb_obj(obj);
7866 err:
7867         return ret;
7868 }
7869
7870 static int intel_gen4_queue_flip(struct drm_device *dev,
7871                                  struct drm_crtc *crtc,
7872                                  struct drm_framebuffer *fb,
7873                                  struct drm_i915_gem_object *obj,
7874                                  uint32_t flags)
7875 {
7876         struct drm_i915_private *dev_priv = dev->dev_private;
7877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7878         uint32_t pf, pipesrc;
7879         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7880         int ret;
7881
7882         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7883         if (ret)
7884                 goto err;
7885
7886         ret = intel_ring_begin(ring, 4);
7887         if (ret)
7888                 goto err_unpin;
7889
7890         /* i965+ uses the linear or tiled offsets from the
7891          * Display Registers (which do not change across a page-flip)
7892          * so we need only reprogram the base address.
7893          */
7894         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7895                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7896         intel_ring_emit(ring, fb->pitches[0]);
7897         intel_ring_emit(ring,
7898                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7899                         obj->tiling_mode);
7900
7901         /* XXX Enabling the panel-fitter across page-flip is so far
7902          * untested on non-native modes, so ignore it for now.
7903          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7904          */
7905         pf = 0;
7906         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7907         intel_ring_emit(ring, pf | pipesrc);
7908
7909         intel_mark_page_flip_active(intel_crtc);
7910         __intel_ring_advance(ring);
7911         return 0;
7912
7913 err_unpin:
7914         intel_unpin_fb_obj(obj);
7915 err:
7916         return ret;
7917 }
7918
7919 static int intel_gen6_queue_flip(struct drm_device *dev,
7920                                  struct drm_crtc *crtc,
7921                                  struct drm_framebuffer *fb,
7922                                  struct drm_i915_gem_object *obj,
7923                                  uint32_t flags)
7924 {
7925         struct drm_i915_private *dev_priv = dev->dev_private;
7926         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7927         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7928         uint32_t pf, pipesrc;
7929         int ret;
7930
7931         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7932         if (ret)
7933                 goto err;
7934
7935         ret = intel_ring_begin(ring, 4);
7936         if (ret)
7937                 goto err_unpin;
7938
7939         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7940                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7941         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7942         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7943
7944         /* Contrary to the suggestions in the documentation,
7945          * "Enable Panel Fitter" does not seem to be required when page
7946          * flipping with a non-native mode, and worse causes a normal
7947          * modeset to fail.
7948          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7949          */
7950         pf = 0;
7951         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7952         intel_ring_emit(ring, pf | pipesrc);
7953
7954         intel_mark_page_flip_active(intel_crtc);
7955         __intel_ring_advance(ring);
7956         return 0;
7957
7958 err_unpin:
7959         intel_unpin_fb_obj(obj);
7960 err:
7961         return ret;
7962 }
7963
7964 static int intel_gen7_queue_flip(struct drm_device *dev,
7965                                  struct drm_crtc *crtc,
7966                                  struct drm_framebuffer *fb,
7967                                  struct drm_i915_gem_object *obj,
7968                                  uint32_t flags)
7969 {
7970         struct drm_i915_private *dev_priv = dev->dev_private;
7971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7972         struct intel_ring_buffer *ring;
7973         uint32_t plane_bit = 0;
7974         int len, ret;
7975
7976         ring = obj->ring;
7977         if (ring == NULL || ring->id != RCS)
7978                 ring = &dev_priv->ring[BCS];
7979
7980         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7981         if (ret)
7982                 goto err;
7983
7984         switch(intel_crtc->plane) {
7985         case PLANE_A:
7986                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7987                 break;
7988         case PLANE_B:
7989                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7990                 break;
7991         case PLANE_C:
7992                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7993                 break;
7994         default:
7995                 WARN_ONCE(1, "unknown plane in flip command\n");
7996                 ret = -ENODEV;
7997                 goto err_unpin;
7998         }
7999
8000         len = 4;
8001         if (ring->id == RCS)
8002                 len += 6;
8003
8004         ret = intel_ring_begin(ring, len);
8005         if (ret)
8006                 goto err_unpin;
8007
8008         /* Unmask the flip-done completion message. Note that the bspec says that
8009          * we should do this for both the BCS and RCS, and that we must not unmask
8010          * more than one flip event at any time (or ensure that one flip message
8011          * can be sent by waiting for flip-done prior to queueing new flips).
8012          * Experimentation says that BCS works despite DERRMR masking all
8013          * flip-done completion events and that unmasking all planes at once
8014          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8015          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8016          */
8017         if (ring->id == RCS) {
8018                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8019                 intel_ring_emit(ring, DERRMR);
8020                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8021                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8022                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8023                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8024                 intel_ring_emit(ring, DERRMR);
8025                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8026         }
8027
8028         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8029         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8030         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8031         intel_ring_emit(ring, (MI_NOOP));
8032
8033         intel_mark_page_flip_active(intel_crtc);
8034         __intel_ring_advance(ring);
8035         return 0;
8036
8037 err_unpin:
8038         intel_unpin_fb_obj(obj);
8039 err:
8040         return ret;
8041 }
8042
8043 static int intel_default_queue_flip(struct drm_device *dev,
8044                                     struct drm_crtc *crtc,
8045                                     struct drm_framebuffer *fb,
8046                                     struct drm_i915_gem_object *obj,
8047                                     uint32_t flags)
8048 {
8049         return -ENODEV;
8050 }
8051
8052 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8053                                 struct drm_framebuffer *fb,
8054                                 struct drm_pending_vblank_event *event,
8055                                 uint32_t page_flip_flags)
8056 {
8057         struct drm_device *dev = crtc->dev;
8058         struct drm_i915_private *dev_priv = dev->dev_private;
8059         struct drm_framebuffer *old_fb = crtc->fb;
8060         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8062         struct intel_unpin_work *work;
8063         unsigned long flags;
8064         int ret;
8065
8066         /* Can't change pixel format via MI display flips. */
8067         if (fb->pixel_format != crtc->fb->pixel_format)
8068                 return -EINVAL;
8069
8070         /*
8071          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8072          * Note that pitch changes could also affect these register.
8073          */
8074         if (INTEL_INFO(dev)->gen > 3 &&
8075             (fb->offsets[0] != crtc->fb->offsets[0] ||
8076              fb->pitches[0] != crtc->fb->pitches[0]))
8077                 return -EINVAL;
8078
8079         work = kzalloc(sizeof *work, GFP_KERNEL);
8080         if (work == NULL)
8081                 return -ENOMEM;
8082
8083         work->event = event;
8084         work->crtc = crtc;
8085         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8086         INIT_WORK(&work->work, intel_unpin_work_fn);
8087
8088         ret = drm_vblank_get(dev, intel_crtc->pipe);
8089         if (ret)
8090                 goto free_work;
8091
8092         /* We borrow the event spin lock for protecting unpin_work */
8093         spin_lock_irqsave(&dev->event_lock, flags);
8094         if (intel_crtc->unpin_work) {
8095                 spin_unlock_irqrestore(&dev->event_lock, flags);
8096                 kfree(work);
8097                 drm_vblank_put(dev, intel_crtc->pipe);
8098
8099                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8100                 return -EBUSY;
8101         }
8102         intel_crtc->unpin_work = work;
8103         spin_unlock_irqrestore(&dev->event_lock, flags);
8104
8105         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8106                 flush_workqueue(dev_priv->wq);
8107
8108         ret = i915_mutex_lock_interruptible(dev);
8109         if (ret)
8110                 goto cleanup;
8111
8112         /* Reference the objects for the scheduled work. */
8113         drm_gem_object_reference(&work->old_fb_obj->base);
8114         drm_gem_object_reference(&obj->base);
8115
8116         crtc->fb = fb;
8117
8118         work->pending_flip_obj = obj;
8119
8120         work->enable_stall_check = true;
8121
8122         atomic_inc(&intel_crtc->unpin_work_count);
8123         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8124
8125         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8126         if (ret)
8127                 goto cleanup_pending;
8128
8129         intel_disable_fbc(dev);
8130         intel_mark_fb_busy(obj, NULL);
8131         mutex_unlock(&dev->struct_mutex);
8132
8133         trace_i915_flip_request(intel_crtc->plane, obj);
8134
8135         return 0;
8136
8137 cleanup_pending:
8138         atomic_dec(&intel_crtc->unpin_work_count);
8139         crtc->fb = old_fb;
8140         drm_gem_object_unreference(&work->old_fb_obj->base);
8141         drm_gem_object_unreference(&obj->base);
8142         mutex_unlock(&dev->struct_mutex);
8143
8144 cleanup:
8145         spin_lock_irqsave(&dev->event_lock, flags);
8146         intel_crtc->unpin_work = NULL;
8147         spin_unlock_irqrestore(&dev->event_lock, flags);
8148
8149         drm_vblank_put(dev, intel_crtc->pipe);
8150 free_work:
8151         kfree(work);
8152
8153         return ret;
8154 }
8155
8156 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8157         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8158         .load_lut = intel_crtc_load_lut,
8159 };
8160
8161 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8162                                   struct drm_crtc *crtc)
8163 {
8164         struct drm_device *dev;
8165         struct drm_crtc *tmp;
8166         int crtc_mask = 1;
8167
8168         WARN(!crtc, "checking null crtc?\n");
8169
8170         dev = crtc->dev;
8171
8172         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8173                 if (tmp == crtc)
8174                         break;
8175                 crtc_mask <<= 1;
8176         }
8177
8178         if (encoder->possible_crtcs & crtc_mask)
8179                 return true;
8180         return false;
8181 }
8182
8183 /**
8184  * intel_modeset_update_staged_output_state
8185  *
8186  * Updates the staged output configuration state, e.g. after we've read out the
8187  * current hw state.
8188  */
8189 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8190 {
8191         struct intel_encoder *encoder;
8192         struct intel_connector *connector;
8193
8194         list_for_each_entry(connector, &dev->mode_config.connector_list,
8195                             base.head) {
8196                 connector->new_encoder =
8197                         to_intel_encoder(connector->base.encoder);
8198         }
8199
8200         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8201                             base.head) {
8202                 encoder->new_crtc =
8203                         to_intel_crtc(encoder->base.crtc);
8204         }
8205 }
8206
8207 /**
8208  * intel_modeset_commit_output_state
8209  *
8210  * This function copies the stage display pipe configuration to the real one.
8211  */
8212 static void intel_modeset_commit_output_state(struct drm_device *dev)
8213 {
8214         struct intel_encoder *encoder;
8215         struct intel_connector *connector;
8216
8217         list_for_each_entry(connector, &dev->mode_config.connector_list,
8218                             base.head) {
8219                 connector->base.encoder = &connector->new_encoder->base;
8220         }
8221
8222         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8223                             base.head) {
8224                 encoder->base.crtc = &encoder->new_crtc->base;
8225         }
8226 }
8227
8228 static void
8229 connected_sink_compute_bpp(struct intel_connector * connector,
8230                            struct intel_crtc_config *pipe_config)
8231 {
8232         int bpp = pipe_config->pipe_bpp;
8233
8234         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8235                 connector->base.base.id,
8236                 drm_get_connector_name(&connector->base));
8237
8238         /* Don't use an invalid EDID bpc value */
8239         if (connector->base.display_info.bpc &&
8240             connector->base.display_info.bpc * 3 < bpp) {
8241                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8242                               bpp, connector->base.display_info.bpc*3);
8243                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8244         }
8245
8246         /* Clamp bpp to 8 on screens without EDID 1.4 */
8247         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8248                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8249                               bpp);
8250                 pipe_config->pipe_bpp = 24;
8251         }
8252 }
8253
8254 static int
8255 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8256                           struct drm_framebuffer *fb,
8257                           struct intel_crtc_config *pipe_config)
8258 {
8259         struct drm_device *dev = crtc->base.dev;
8260         struct intel_connector *connector;
8261         int bpp;
8262
8263         switch (fb->pixel_format) {
8264         case DRM_FORMAT_C8:
8265                 bpp = 8*3; /* since we go through a colormap */
8266                 break;
8267         case DRM_FORMAT_XRGB1555:
8268         case DRM_FORMAT_ARGB1555:
8269                 /* checked in intel_framebuffer_init already */
8270                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8271                         return -EINVAL;
8272         case DRM_FORMAT_RGB565:
8273                 bpp = 6*3; /* min is 18bpp */
8274                 break;
8275         case DRM_FORMAT_XBGR8888:
8276         case DRM_FORMAT_ABGR8888:
8277                 /* checked in intel_framebuffer_init already */
8278                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8279                         return -EINVAL;
8280         case DRM_FORMAT_XRGB8888:
8281         case DRM_FORMAT_ARGB8888:
8282                 bpp = 8*3;
8283                 break;
8284         case DRM_FORMAT_XRGB2101010:
8285         case DRM_FORMAT_ARGB2101010:
8286         case DRM_FORMAT_XBGR2101010:
8287         case DRM_FORMAT_ABGR2101010:
8288                 /* checked in intel_framebuffer_init already */
8289                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8290                         return -EINVAL;
8291                 bpp = 10*3;
8292                 break;
8293         /* TODO: gen4+ supports 16 bpc floating point, too. */
8294         default:
8295                 DRM_DEBUG_KMS("unsupported depth\n");
8296                 return -EINVAL;
8297         }
8298
8299         pipe_config->pipe_bpp = bpp;
8300
8301         /* Clamp display bpp to EDID value */
8302         list_for_each_entry(connector, &dev->mode_config.connector_list,
8303                             base.head) {
8304                 if (!connector->new_encoder ||
8305                     connector->new_encoder->new_crtc != crtc)
8306                         continue;
8307
8308                 connected_sink_compute_bpp(connector, pipe_config);
8309         }
8310
8311         return bpp;
8312 }
8313
8314 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8315                                    struct intel_crtc_config *pipe_config,
8316                                    const char *context)
8317 {
8318         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8319                       context, pipe_name(crtc->pipe));
8320
8321         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8322         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8323                       pipe_config->pipe_bpp, pipe_config->dither);
8324         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8325                       pipe_config->has_pch_encoder,
8326                       pipe_config->fdi_lanes,
8327                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8328                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8329                       pipe_config->fdi_m_n.tu);
8330         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8331                       pipe_config->has_dp_encoder,
8332                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8333                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8334                       pipe_config->dp_m_n.tu);
8335         DRM_DEBUG_KMS("requested mode:\n");
8336         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8337         DRM_DEBUG_KMS("adjusted mode:\n");
8338         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8339         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8340         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8341                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8342         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8343                       pipe_config->gmch_pfit.control,
8344                       pipe_config->gmch_pfit.pgm_ratios,
8345                       pipe_config->gmch_pfit.lvds_border_bits);
8346         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8347                       pipe_config->pch_pfit.pos,
8348                       pipe_config->pch_pfit.size);
8349         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8350         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8351 }
8352
8353 static bool check_encoder_cloning(struct drm_crtc *crtc)
8354 {
8355         int num_encoders = 0;
8356         bool uncloneable_encoders = false;
8357         struct intel_encoder *encoder;
8358
8359         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8360                             base.head) {
8361                 if (&encoder->new_crtc->base != crtc)
8362                         continue;
8363
8364                 num_encoders++;
8365                 if (!encoder->cloneable)
8366                         uncloneable_encoders = true;
8367         }
8368
8369         return !(num_encoders > 1 && uncloneable_encoders);
8370 }
8371
8372 static struct intel_crtc_config *
8373 intel_modeset_pipe_config(struct drm_crtc *crtc,
8374                           struct drm_framebuffer *fb,
8375                           struct drm_display_mode *mode)
8376 {
8377         struct drm_device *dev = crtc->dev;
8378         struct intel_encoder *encoder;
8379         struct intel_crtc_config *pipe_config;
8380         int plane_bpp, ret = -EINVAL;
8381         bool retry = true;
8382
8383         if (!check_encoder_cloning(crtc)) {
8384                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8385                 return ERR_PTR(-EINVAL);
8386         }
8387
8388         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8389         if (!pipe_config)
8390                 return ERR_PTR(-ENOMEM);
8391
8392         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8393         drm_mode_copy(&pipe_config->requested_mode, mode);
8394
8395         pipe_config->pipe_src_w = mode->hdisplay;
8396         pipe_config->pipe_src_h = mode->vdisplay;
8397
8398         pipe_config->cpu_transcoder =
8399                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8400         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8401
8402         /*
8403          * Sanitize sync polarity flags based on requested ones. If neither
8404          * positive or negative polarity is requested, treat this as meaning
8405          * negative polarity.
8406          */
8407         if (!(pipe_config->adjusted_mode.flags &
8408               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8409                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8410
8411         if (!(pipe_config->adjusted_mode.flags &
8412               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8413                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8414
8415         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8416          * plane pixel format and any sink constraints into account. Returns the
8417          * source plane bpp so that dithering can be selected on mismatches
8418          * after encoders and crtc also have had their say. */
8419         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8420                                               fb, pipe_config);
8421         if (plane_bpp < 0)
8422                 goto fail;
8423
8424 encoder_retry:
8425         /* Ensure the port clock defaults are reset when retrying. */
8426         pipe_config->port_clock = 0;
8427         pipe_config->pixel_multiplier = 1;
8428
8429         /* Fill in default crtc timings, allow encoders to overwrite them. */
8430         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8431
8432         /* Pass our mode to the connectors and the CRTC to give them a chance to
8433          * adjust it according to limitations or connector properties, and also
8434          * a chance to reject the mode entirely.
8435          */
8436         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8437                             base.head) {
8438
8439                 if (&encoder->new_crtc->base != crtc)
8440                         continue;
8441
8442                 if (!(encoder->compute_config(encoder, pipe_config))) {
8443                         DRM_DEBUG_KMS("Encoder config failure\n");
8444                         goto fail;
8445                 }
8446         }
8447
8448         /* Set default port clock if not overwritten by the encoder. Needs to be
8449          * done afterwards in case the encoder adjusts the mode. */
8450         if (!pipe_config->port_clock)
8451                 pipe_config->port_clock = pipe_config->adjusted_mode.clock *
8452                         pipe_config->pixel_multiplier;
8453
8454         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8455         if (ret < 0) {
8456                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8457                 goto fail;
8458         }
8459
8460         if (ret == RETRY) {
8461                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8462                         ret = -EINVAL;
8463                         goto fail;
8464                 }
8465
8466                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8467                 retry = false;
8468                 goto encoder_retry;
8469         }
8470
8471         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8472         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8473                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8474
8475         return pipe_config;
8476 fail:
8477         kfree(pipe_config);
8478         return ERR_PTR(ret);
8479 }
8480
8481 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8482  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8483 static void
8484 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8485                              unsigned *prepare_pipes, unsigned *disable_pipes)
8486 {
8487         struct intel_crtc *intel_crtc;
8488         struct drm_device *dev = crtc->dev;
8489         struct intel_encoder *encoder;
8490         struct intel_connector *connector;
8491         struct drm_crtc *tmp_crtc;
8492
8493         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8494
8495         /* Check which crtcs have changed outputs connected to them, these need
8496          * to be part of the prepare_pipes mask. We don't (yet) support global
8497          * modeset across multiple crtcs, so modeset_pipes will only have one
8498          * bit set at most. */
8499         list_for_each_entry(connector, &dev->mode_config.connector_list,
8500                             base.head) {
8501                 if (connector->base.encoder == &connector->new_encoder->base)
8502                         continue;
8503
8504                 if (connector->base.encoder) {
8505                         tmp_crtc = connector->base.encoder->crtc;
8506
8507                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8508                 }
8509
8510                 if (connector->new_encoder)
8511                         *prepare_pipes |=
8512                                 1 << connector->new_encoder->new_crtc->pipe;
8513         }
8514
8515         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8516                             base.head) {
8517                 if (encoder->base.crtc == &encoder->new_crtc->base)
8518                         continue;
8519
8520                 if (encoder->base.crtc) {
8521                         tmp_crtc = encoder->base.crtc;
8522
8523                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8524                 }
8525
8526                 if (encoder->new_crtc)
8527                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8528         }
8529
8530         /* Check for any pipes that will be fully disabled ... */
8531         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8532                             base.head) {
8533                 bool used = false;
8534
8535                 /* Don't try to disable disabled crtcs. */
8536                 if (!intel_crtc->base.enabled)
8537                         continue;
8538
8539                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8540                                     base.head) {
8541                         if (encoder->new_crtc == intel_crtc)
8542                                 used = true;
8543                 }
8544
8545                 if (!used)
8546                         *disable_pipes |= 1 << intel_crtc->pipe;
8547         }
8548
8549
8550         /* set_mode is also used to update properties on life display pipes. */
8551         intel_crtc = to_intel_crtc(crtc);
8552         if (crtc->enabled)
8553                 *prepare_pipes |= 1 << intel_crtc->pipe;
8554
8555         /*
8556          * For simplicity do a full modeset on any pipe where the output routing
8557          * changed. We could be more clever, but that would require us to be
8558          * more careful with calling the relevant encoder->mode_set functions.
8559          */
8560         if (*prepare_pipes)
8561                 *modeset_pipes = *prepare_pipes;
8562
8563         /* ... and mask these out. */
8564         *modeset_pipes &= ~(*disable_pipes);
8565         *prepare_pipes &= ~(*disable_pipes);
8566
8567         /*
8568          * HACK: We don't (yet) fully support global modesets. intel_set_config
8569          * obies this rule, but the modeset restore mode of
8570          * intel_modeset_setup_hw_state does not.
8571          */
8572         *modeset_pipes &= 1 << intel_crtc->pipe;
8573         *prepare_pipes &= 1 << intel_crtc->pipe;
8574
8575         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8576                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8577 }
8578
8579 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8580 {
8581         struct drm_encoder *encoder;
8582         struct drm_device *dev = crtc->dev;
8583
8584         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8585                 if (encoder->crtc == crtc)
8586                         return true;
8587
8588         return false;
8589 }
8590
8591 static void
8592 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8593 {
8594         struct intel_encoder *intel_encoder;
8595         struct intel_crtc *intel_crtc;
8596         struct drm_connector *connector;
8597
8598         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8599                             base.head) {
8600                 if (!intel_encoder->base.crtc)
8601                         continue;
8602
8603                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8604
8605                 if (prepare_pipes & (1 << intel_crtc->pipe))
8606                         intel_encoder->connectors_active = false;
8607         }
8608
8609         intel_modeset_commit_output_state(dev);
8610
8611         /* Update computed state. */
8612         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8613                             base.head) {
8614                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8615         }
8616
8617         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8618                 if (!connector->encoder || !connector->encoder->crtc)
8619                         continue;
8620
8621                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8622
8623                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8624                         struct drm_property *dpms_property =
8625                                 dev->mode_config.dpms_property;
8626
8627                         connector->dpms = DRM_MODE_DPMS_ON;
8628                         drm_object_property_set_value(&connector->base,
8629                                                          dpms_property,
8630                                                          DRM_MODE_DPMS_ON);
8631
8632                         intel_encoder = to_intel_encoder(connector->encoder);
8633                         intel_encoder->connectors_active = true;
8634                 }
8635         }
8636
8637 }
8638
8639 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8640 {
8641         int diff;
8642
8643         if (clock1 == clock2)
8644                 return true;
8645
8646         if (!clock1 || !clock2)
8647                 return false;
8648
8649         diff = abs(clock1 - clock2);
8650
8651         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8652                 return true;
8653
8654         return false;
8655 }
8656
8657 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8658         list_for_each_entry((intel_crtc), \
8659                             &(dev)->mode_config.crtc_list, \
8660                             base.head) \
8661                 if (mask & (1 <<(intel_crtc)->pipe))
8662
8663 static bool
8664 intel_pipe_config_compare(struct drm_device *dev,
8665                           struct intel_crtc_config *current_config,
8666                           struct intel_crtc_config *pipe_config)
8667 {
8668 #define PIPE_CONF_CHECK_X(name) \
8669         if (current_config->name != pipe_config->name) { \
8670                 DRM_ERROR("mismatch in " #name " " \
8671                           "(expected 0x%08x, found 0x%08x)\n", \
8672                           current_config->name, \
8673                           pipe_config->name); \
8674                 return false; \
8675         }
8676
8677 #define PIPE_CONF_CHECK_I(name) \
8678         if (current_config->name != pipe_config->name) { \
8679                 DRM_ERROR("mismatch in " #name " " \
8680                           "(expected %i, found %i)\n", \
8681                           current_config->name, \
8682                           pipe_config->name); \
8683                 return false; \
8684         }
8685
8686 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8687         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8688                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8689                           "(expected %i, found %i)\n", \
8690                           current_config->name & (mask), \
8691                           pipe_config->name & (mask)); \
8692                 return false; \
8693         }
8694
8695 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8696         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8697                 DRM_ERROR("mismatch in " #name " " \
8698                           "(expected %i, found %i)\n", \
8699                           current_config->name, \
8700                           pipe_config->name); \
8701                 return false; \
8702         }
8703
8704 #define PIPE_CONF_QUIRK(quirk)  \
8705         ((current_config->quirks | pipe_config->quirks) & (quirk))
8706
8707         PIPE_CONF_CHECK_I(cpu_transcoder);
8708
8709         PIPE_CONF_CHECK_I(has_pch_encoder);
8710         PIPE_CONF_CHECK_I(fdi_lanes);
8711         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8712         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8713         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8714         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8715         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8716
8717         PIPE_CONF_CHECK_I(has_dp_encoder);
8718         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8719         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8720         PIPE_CONF_CHECK_I(dp_m_n.link_m);
8721         PIPE_CONF_CHECK_I(dp_m_n.link_n);
8722         PIPE_CONF_CHECK_I(dp_m_n.tu);
8723
8724         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8725         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8726         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8727         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8728         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8729         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8730
8731         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8732         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8733         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8734         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8735         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8736         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8737
8738         PIPE_CONF_CHECK_I(pixel_multiplier);
8739
8740         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8741                               DRM_MODE_FLAG_INTERLACE);
8742
8743         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8744                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8745                                       DRM_MODE_FLAG_PHSYNC);
8746                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8747                                       DRM_MODE_FLAG_NHSYNC);
8748                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8749                                       DRM_MODE_FLAG_PVSYNC);
8750                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8751                                       DRM_MODE_FLAG_NVSYNC);
8752         }
8753
8754         PIPE_CONF_CHECK_I(pipe_src_w);
8755         PIPE_CONF_CHECK_I(pipe_src_h);
8756
8757         PIPE_CONF_CHECK_I(gmch_pfit.control);
8758         /* pfit ratios are autocomputed by the hw on gen4+ */
8759         if (INTEL_INFO(dev)->gen < 4)
8760                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8761         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8762         PIPE_CONF_CHECK_I(pch_pfit.pos);
8763         PIPE_CONF_CHECK_I(pch_pfit.size);
8764
8765         PIPE_CONF_CHECK_I(ips_enabled);
8766
8767         PIPE_CONF_CHECK_I(double_wide);
8768
8769         PIPE_CONF_CHECK_I(shared_dpll);
8770         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8771         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8772         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8773         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8774
8775         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8776                 PIPE_CONF_CHECK_I(pipe_bpp);
8777
8778         if (!IS_HASWELL(dev)) {
8779                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock);
8780                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8781         }
8782
8783 #undef PIPE_CONF_CHECK_X
8784 #undef PIPE_CONF_CHECK_I
8785 #undef PIPE_CONF_CHECK_FLAGS
8786 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8787 #undef PIPE_CONF_QUIRK
8788
8789         return true;
8790 }
8791
8792 static void
8793 check_connector_state(struct drm_device *dev)
8794 {
8795         struct intel_connector *connector;
8796
8797         list_for_each_entry(connector, &dev->mode_config.connector_list,
8798                             base.head) {
8799                 /* This also checks the encoder/connector hw state with the
8800                  * ->get_hw_state callbacks. */
8801                 intel_connector_check_state(connector);
8802
8803                 WARN(&connector->new_encoder->base != connector->base.encoder,
8804                      "connector's staged encoder doesn't match current encoder\n");
8805         }
8806 }
8807
8808 static void
8809 check_encoder_state(struct drm_device *dev)
8810 {
8811         struct intel_encoder *encoder;
8812         struct intel_connector *connector;
8813
8814         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8815                             base.head) {
8816                 bool enabled = false;
8817                 bool active = false;
8818                 enum pipe pipe, tracked_pipe;
8819
8820                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8821                               encoder->base.base.id,
8822                               drm_get_encoder_name(&encoder->base));
8823
8824                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8825                      "encoder's stage crtc doesn't match current crtc\n");
8826                 WARN(encoder->connectors_active && !encoder->base.crtc,
8827                      "encoder's active_connectors set, but no crtc\n");
8828
8829                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8830                                     base.head) {
8831                         if (connector->base.encoder != &encoder->base)
8832                                 continue;
8833                         enabled = true;
8834                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8835                                 active = true;
8836                 }
8837                 WARN(!!encoder->base.crtc != enabled,
8838                      "encoder's enabled state mismatch "
8839                      "(expected %i, found %i)\n",
8840                      !!encoder->base.crtc, enabled);
8841                 WARN(active && !encoder->base.crtc,
8842                      "active encoder with no crtc\n");
8843
8844                 WARN(encoder->connectors_active != active,
8845                      "encoder's computed active state doesn't match tracked active state "
8846                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8847
8848                 active = encoder->get_hw_state(encoder, &pipe);
8849                 WARN(active != encoder->connectors_active,
8850                      "encoder's hw state doesn't match sw tracking "
8851                      "(expected %i, found %i)\n",
8852                      encoder->connectors_active, active);
8853
8854                 if (!encoder->base.crtc)
8855                         continue;
8856
8857                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8858                 WARN(active && pipe != tracked_pipe,
8859                      "active encoder's pipe doesn't match"
8860                      "(expected %i, found %i)\n",
8861                      tracked_pipe, pipe);
8862
8863         }
8864 }
8865
8866 static void
8867 check_crtc_state(struct drm_device *dev)
8868 {
8869         drm_i915_private_t *dev_priv = dev->dev_private;
8870         struct intel_crtc *crtc;
8871         struct intel_encoder *encoder;
8872         struct intel_crtc_config pipe_config;
8873
8874         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8875                             base.head) {
8876                 bool enabled = false;
8877                 bool active = false;
8878
8879                 memset(&pipe_config, 0, sizeof(pipe_config));
8880
8881                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8882                               crtc->base.base.id);
8883
8884                 WARN(crtc->active && !crtc->base.enabled,
8885                      "active crtc, but not enabled in sw tracking\n");
8886
8887                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8888                                     base.head) {
8889                         if (encoder->base.crtc != &crtc->base)
8890                                 continue;
8891                         enabled = true;
8892                         if (encoder->connectors_active)
8893                                 active = true;
8894                 }
8895
8896                 WARN(active != crtc->active,
8897                      "crtc's computed active state doesn't match tracked active state "
8898                      "(expected %i, found %i)\n", active, crtc->active);
8899                 WARN(enabled != crtc->base.enabled,
8900                      "crtc's computed enabled state doesn't match tracked enabled state "
8901                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8902
8903                 active = dev_priv->display.get_pipe_config(crtc,
8904                                                            &pipe_config);
8905
8906                 /* hw state is inconsistent with the pipe A quirk */
8907                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8908                         active = crtc->active;
8909
8910                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8911                                     base.head) {
8912                         enum pipe pipe;
8913                         if (encoder->base.crtc != &crtc->base)
8914                                 continue;
8915                         if (encoder->get_config &&
8916                             encoder->get_hw_state(encoder, &pipe))
8917                                 encoder->get_config(encoder, &pipe_config);
8918                 }
8919
8920                 WARN(crtc->active != active,
8921                      "crtc active state doesn't match with hw state "
8922                      "(expected %i, found %i)\n", crtc->active, active);
8923
8924                 if (active &&
8925                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8926                         WARN(1, "pipe state doesn't match!\n");
8927                         intel_dump_pipe_config(crtc, &pipe_config,
8928                                                "[hw state]");
8929                         intel_dump_pipe_config(crtc, &crtc->config,
8930                                                "[sw state]");
8931                 }
8932         }
8933 }
8934
8935 static void
8936 check_shared_dpll_state(struct drm_device *dev)
8937 {
8938         drm_i915_private_t *dev_priv = dev->dev_private;
8939         struct intel_crtc *crtc;
8940         struct intel_dpll_hw_state dpll_hw_state;
8941         int i;
8942
8943         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8944                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8945                 int enabled_crtcs = 0, active_crtcs = 0;
8946                 bool active;
8947
8948                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8949
8950                 DRM_DEBUG_KMS("%s\n", pll->name);
8951
8952                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8953
8954                 WARN(pll->active > pll->refcount,
8955                      "more active pll users than references: %i vs %i\n",
8956                      pll->active, pll->refcount);
8957                 WARN(pll->active && !pll->on,
8958                      "pll in active use but not on in sw tracking\n");
8959                 WARN(pll->on && !pll->active,
8960                      "pll in on but not on in use in sw tracking\n");
8961                 WARN(pll->on != active,
8962                      "pll on state mismatch (expected %i, found %i)\n",
8963                      pll->on, active);
8964
8965                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8966                                     base.head) {
8967                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8968                                 enabled_crtcs++;
8969                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8970                                 active_crtcs++;
8971                 }
8972                 WARN(pll->active != active_crtcs,
8973                      "pll active crtcs mismatch (expected %i, found %i)\n",
8974                      pll->active, active_crtcs);
8975                 WARN(pll->refcount != enabled_crtcs,
8976                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8977                      pll->refcount, enabled_crtcs);
8978
8979                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8980                                        sizeof(dpll_hw_state)),
8981                      "pll hw state mismatch\n");
8982         }
8983 }
8984
8985 void
8986 intel_modeset_check_state(struct drm_device *dev)
8987 {
8988         check_connector_state(dev);
8989         check_encoder_state(dev);
8990         check_crtc_state(dev);
8991         check_shared_dpll_state(dev);
8992 }
8993
8994 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
8995                                      int dotclock)
8996 {
8997         /*
8998          * FDI already provided one idea for the dotclock.
8999          * Yell if the encoder disagrees.
9000          */
9001         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.clock, dotclock),
9002              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9003              pipe_config->adjusted_mode.clock, dotclock);
9004 }
9005
9006 static int __intel_set_mode(struct drm_crtc *crtc,
9007                             struct drm_display_mode *mode,
9008                             int x, int y, struct drm_framebuffer *fb)
9009 {
9010         struct drm_device *dev = crtc->dev;
9011         drm_i915_private_t *dev_priv = dev->dev_private;
9012         struct drm_display_mode *saved_mode, *saved_hwmode;
9013         struct intel_crtc_config *pipe_config = NULL;
9014         struct intel_crtc *intel_crtc;
9015         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9016         int ret = 0;
9017
9018         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
9019         if (!saved_mode)
9020                 return -ENOMEM;
9021         saved_hwmode = saved_mode + 1;
9022
9023         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9024                                      &prepare_pipes, &disable_pipes);
9025
9026         *saved_hwmode = crtc->hwmode;
9027         *saved_mode = crtc->mode;
9028
9029         /* Hack: Because we don't (yet) support global modeset on multiple
9030          * crtcs, we don't keep track of the new mode for more than one crtc.
9031          * Hence simply check whether any bit is set in modeset_pipes in all the
9032          * pieces of code that are not yet converted to deal with mutliple crtcs
9033          * changing their mode at the same time. */
9034         if (modeset_pipes) {
9035                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9036                 if (IS_ERR(pipe_config)) {
9037                         ret = PTR_ERR(pipe_config);
9038                         pipe_config = NULL;
9039
9040                         goto out;
9041                 }
9042                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9043                                        "[modeset]");
9044         }
9045
9046         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9047                 intel_crtc_disable(&intel_crtc->base);
9048
9049         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9050                 if (intel_crtc->base.enabled)
9051                         dev_priv->display.crtc_disable(&intel_crtc->base);
9052         }
9053
9054         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9055          * to set it here already despite that we pass it down the callchain.
9056          */
9057         if (modeset_pipes) {
9058                 crtc->mode = *mode;
9059                 /* mode_set/enable/disable functions rely on a correct pipe
9060                  * config. */
9061                 to_intel_crtc(crtc)->config = *pipe_config;
9062         }
9063
9064         /* Only after disabling all output pipelines that will be changed can we
9065          * update the the output configuration. */
9066         intel_modeset_update_state(dev, prepare_pipes);
9067
9068         if (dev_priv->display.modeset_global_resources)
9069                 dev_priv->display.modeset_global_resources(dev);
9070
9071         /* Set up the DPLL and any encoders state that needs to adjust or depend
9072          * on the DPLL.
9073          */
9074         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9075                 ret = intel_crtc_mode_set(&intel_crtc->base,
9076                                           x, y, fb);
9077                 if (ret)
9078                         goto done;
9079         }
9080
9081         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9082         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9083                 dev_priv->display.crtc_enable(&intel_crtc->base);
9084
9085         if (modeset_pipes) {
9086                 /* Store real post-adjustment hardware mode. */
9087                 crtc->hwmode = pipe_config->adjusted_mode;
9088
9089                 /* Calculate and store various constants which
9090                  * are later needed by vblank and swap-completion
9091                  * timestamping. They are derived from true hwmode.
9092                  */
9093                 drm_calc_timestamping_constants(crtc);
9094         }
9095
9096         /* FIXME: add subpixel order */
9097 done:
9098         if (ret && crtc->enabled) {
9099                 crtc->hwmode = *saved_hwmode;
9100                 crtc->mode = *saved_mode;
9101         }
9102
9103 out:
9104         kfree(pipe_config);
9105         kfree(saved_mode);
9106         return ret;
9107 }
9108
9109 static int intel_set_mode(struct drm_crtc *crtc,
9110                           struct drm_display_mode *mode,
9111                           int x, int y, struct drm_framebuffer *fb)
9112 {
9113         int ret;
9114
9115         ret = __intel_set_mode(crtc, mode, x, y, fb);
9116
9117         if (ret == 0)
9118                 intel_modeset_check_state(crtc->dev);
9119
9120         return ret;
9121 }
9122
9123 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9124 {
9125         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9126 }
9127
9128 #undef for_each_intel_crtc_masked
9129
9130 static void intel_set_config_free(struct intel_set_config *config)
9131 {
9132         if (!config)
9133                 return;
9134
9135         kfree(config->save_connector_encoders);
9136         kfree(config->save_encoder_crtcs);
9137         kfree(config);
9138 }
9139
9140 static int intel_set_config_save_state(struct drm_device *dev,
9141                                        struct intel_set_config *config)
9142 {
9143         struct drm_encoder *encoder;
9144         struct drm_connector *connector;
9145         int count;
9146
9147         config->save_encoder_crtcs =
9148                 kcalloc(dev->mode_config.num_encoder,
9149                         sizeof(struct drm_crtc *), GFP_KERNEL);
9150         if (!config->save_encoder_crtcs)
9151                 return -ENOMEM;
9152
9153         config->save_connector_encoders =
9154                 kcalloc(dev->mode_config.num_connector,
9155                         sizeof(struct drm_encoder *), GFP_KERNEL);
9156         if (!config->save_connector_encoders)
9157                 return -ENOMEM;
9158
9159         /* Copy data. Note that driver private data is not affected.
9160          * Should anything bad happen only the expected state is
9161          * restored, not the drivers personal bookkeeping.
9162          */
9163         count = 0;
9164         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9165                 config->save_encoder_crtcs[count++] = encoder->crtc;
9166         }
9167
9168         count = 0;
9169         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9170                 config->save_connector_encoders[count++] = connector->encoder;
9171         }
9172
9173         return 0;
9174 }
9175
9176 static void intel_set_config_restore_state(struct drm_device *dev,
9177                                            struct intel_set_config *config)
9178 {
9179         struct intel_encoder *encoder;
9180         struct intel_connector *connector;
9181         int count;
9182
9183         count = 0;
9184         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9185                 encoder->new_crtc =
9186                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9187         }
9188
9189         count = 0;
9190         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9191                 connector->new_encoder =
9192                         to_intel_encoder(config->save_connector_encoders[count++]);
9193         }
9194 }
9195
9196 static bool
9197 is_crtc_connector_off(struct drm_mode_set *set)
9198 {
9199         int i;
9200
9201         if (set->num_connectors == 0)
9202                 return false;
9203
9204         if (WARN_ON(set->connectors == NULL))
9205                 return false;
9206
9207         for (i = 0; i < set->num_connectors; i++)
9208                 if (set->connectors[i]->encoder &&
9209                     set->connectors[i]->encoder->crtc == set->crtc &&
9210                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9211                         return true;
9212
9213         return false;
9214 }
9215
9216 static void
9217 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9218                                       struct intel_set_config *config)
9219 {
9220
9221         /* We should be able to check here if the fb has the same properties
9222          * and then just flip_or_move it */
9223         if (is_crtc_connector_off(set)) {
9224                 config->mode_changed = true;
9225         } else if (set->crtc->fb != set->fb) {
9226                 /* If we have no fb then treat it as a full mode set */
9227                 if (set->crtc->fb == NULL) {
9228                         struct intel_crtc *intel_crtc =
9229                                 to_intel_crtc(set->crtc);
9230
9231                         if (intel_crtc->active && i915_fastboot) {
9232                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9233                                 config->fb_changed = true;
9234                         } else {
9235                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9236                                 config->mode_changed = true;
9237                         }
9238                 } else if (set->fb == NULL) {
9239                         config->mode_changed = true;
9240                 } else if (set->fb->pixel_format !=
9241                            set->crtc->fb->pixel_format) {
9242                         config->mode_changed = true;
9243                 } else {
9244                         config->fb_changed = true;
9245                 }
9246         }
9247
9248         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9249                 config->fb_changed = true;
9250
9251         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9252                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9253                 drm_mode_debug_printmodeline(&set->crtc->mode);
9254                 drm_mode_debug_printmodeline(set->mode);
9255                 config->mode_changed = true;
9256         }
9257
9258         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9259                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9260 }
9261
9262 static int
9263 intel_modeset_stage_output_state(struct drm_device *dev,
9264                                  struct drm_mode_set *set,
9265                                  struct intel_set_config *config)
9266 {
9267         struct drm_crtc *new_crtc;
9268         struct intel_connector *connector;
9269         struct intel_encoder *encoder;
9270         int ro;
9271
9272         /* The upper layers ensure that we either disable a crtc or have a list
9273          * of connectors. For paranoia, double-check this. */
9274         WARN_ON(!set->fb && (set->num_connectors != 0));
9275         WARN_ON(set->fb && (set->num_connectors == 0));
9276
9277         list_for_each_entry(connector, &dev->mode_config.connector_list,
9278                             base.head) {
9279                 /* Otherwise traverse passed in connector list and get encoders
9280                  * for them. */
9281                 for (ro = 0; ro < set->num_connectors; ro++) {
9282                         if (set->connectors[ro] == &connector->base) {
9283                                 connector->new_encoder = connector->encoder;
9284                                 break;
9285                         }
9286                 }
9287
9288                 /* If we disable the crtc, disable all its connectors. Also, if
9289                  * the connector is on the changing crtc but not on the new
9290                  * connector list, disable it. */
9291                 if ((!set->fb || ro == set->num_connectors) &&
9292                     connector->base.encoder &&
9293                     connector->base.encoder->crtc == set->crtc) {
9294                         connector->new_encoder = NULL;
9295
9296                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9297                                 connector->base.base.id,
9298                                 drm_get_connector_name(&connector->base));
9299                 }
9300
9301
9302                 if (&connector->new_encoder->base != connector->base.encoder) {
9303                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9304                         config->mode_changed = true;
9305                 }
9306         }
9307         /* connector->new_encoder is now updated for all connectors. */
9308
9309         /* Update crtc of enabled connectors. */
9310         list_for_each_entry(connector, &dev->mode_config.connector_list,
9311                             base.head) {
9312                 if (!connector->new_encoder)
9313                         continue;
9314
9315                 new_crtc = connector->new_encoder->base.crtc;
9316
9317                 for (ro = 0; ro < set->num_connectors; ro++) {
9318                         if (set->connectors[ro] == &connector->base)
9319                                 new_crtc = set->crtc;
9320                 }
9321
9322                 /* Make sure the new CRTC will work with the encoder */
9323                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9324                                            new_crtc)) {
9325                         return -EINVAL;
9326                 }
9327                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9328
9329                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9330                         connector->base.base.id,
9331                         drm_get_connector_name(&connector->base),
9332                         new_crtc->base.id);
9333         }
9334
9335         /* Check for any encoders that needs to be disabled. */
9336         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9337                             base.head) {
9338                 list_for_each_entry(connector,
9339                                     &dev->mode_config.connector_list,
9340                                     base.head) {
9341                         if (connector->new_encoder == encoder) {
9342                                 WARN_ON(!connector->new_encoder->new_crtc);
9343
9344                                 goto next_encoder;
9345                         }
9346                 }
9347                 encoder->new_crtc = NULL;
9348 next_encoder:
9349                 /* Only now check for crtc changes so we don't miss encoders
9350                  * that will be disabled. */
9351                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9352                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9353                         config->mode_changed = true;
9354                 }
9355         }
9356         /* Now we've also updated encoder->new_crtc for all encoders. */
9357
9358         return 0;
9359 }
9360
9361 static int intel_crtc_set_config(struct drm_mode_set *set)
9362 {
9363         struct drm_device *dev;
9364         struct drm_mode_set save_set;
9365         struct intel_set_config *config;
9366         int ret;
9367
9368         BUG_ON(!set);
9369         BUG_ON(!set->crtc);
9370         BUG_ON(!set->crtc->helper_private);
9371
9372         /* Enforce sane interface api - has been abused by the fb helper. */
9373         BUG_ON(!set->mode && set->fb);
9374         BUG_ON(set->fb && set->num_connectors == 0);
9375
9376         if (set->fb) {
9377                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9378                                 set->crtc->base.id, set->fb->base.id,
9379                                 (int)set->num_connectors, set->x, set->y);
9380         } else {
9381                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9382         }
9383
9384         dev = set->crtc->dev;
9385
9386         ret = -ENOMEM;
9387         config = kzalloc(sizeof(*config), GFP_KERNEL);
9388         if (!config)
9389                 goto out_config;
9390
9391         ret = intel_set_config_save_state(dev, config);
9392         if (ret)
9393                 goto out_config;
9394
9395         save_set.crtc = set->crtc;
9396         save_set.mode = &set->crtc->mode;
9397         save_set.x = set->crtc->x;
9398         save_set.y = set->crtc->y;
9399         save_set.fb = set->crtc->fb;
9400
9401         /* Compute whether we need a full modeset, only an fb base update or no
9402          * change at all. In the future we might also check whether only the
9403          * mode changed, e.g. for LVDS where we only change the panel fitter in
9404          * such cases. */
9405         intel_set_config_compute_mode_changes(set, config);
9406
9407         ret = intel_modeset_stage_output_state(dev, set, config);
9408         if (ret)
9409                 goto fail;
9410
9411         if (config->mode_changed) {
9412                 ret = intel_set_mode(set->crtc, set->mode,
9413                                      set->x, set->y, set->fb);
9414         } else if (config->fb_changed) {
9415                 intel_crtc_wait_for_pending_flips(set->crtc);
9416
9417                 ret = intel_pipe_set_base(set->crtc,
9418                                           set->x, set->y, set->fb);
9419         }
9420
9421         if (ret) {
9422                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9423                               set->crtc->base.id, ret);
9424 fail:
9425                 intel_set_config_restore_state(dev, config);
9426
9427                 /* Try to restore the config */
9428                 if (config->mode_changed &&
9429                     intel_set_mode(save_set.crtc, save_set.mode,
9430                                    save_set.x, save_set.y, save_set.fb))
9431                         DRM_ERROR("failed to restore config after modeset failure\n");
9432         }
9433
9434 out_config:
9435         intel_set_config_free(config);
9436         return ret;
9437 }
9438
9439 static const struct drm_crtc_funcs intel_crtc_funcs = {
9440         .cursor_set = intel_crtc_cursor_set,
9441         .cursor_move = intel_crtc_cursor_move,
9442         .gamma_set = intel_crtc_gamma_set,
9443         .set_config = intel_crtc_set_config,
9444         .destroy = intel_crtc_destroy,
9445         .page_flip = intel_crtc_page_flip,
9446 };
9447
9448 static void intel_cpu_pll_init(struct drm_device *dev)
9449 {
9450         if (HAS_DDI(dev))
9451                 intel_ddi_pll_init(dev);
9452 }
9453
9454 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9455                                       struct intel_shared_dpll *pll,
9456                                       struct intel_dpll_hw_state *hw_state)
9457 {
9458         uint32_t val;
9459
9460         val = I915_READ(PCH_DPLL(pll->id));
9461         hw_state->dpll = val;
9462         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9463         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9464
9465         return val & DPLL_VCO_ENABLE;
9466 }
9467
9468 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9469                                   struct intel_shared_dpll *pll)
9470 {
9471         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9472         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9473 }
9474
9475 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9476                                 struct intel_shared_dpll *pll)
9477 {
9478         /* PCH refclock must be enabled first */
9479         assert_pch_refclk_enabled(dev_priv);
9480
9481         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9482
9483         /* Wait for the clocks to stabilize. */
9484         POSTING_READ(PCH_DPLL(pll->id));
9485         udelay(150);
9486
9487         /* The pixel multiplier can only be updated once the
9488          * DPLL is enabled and the clocks are stable.
9489          *
9490          * So write it again.
9491          */
9492         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9493         POSTING_READ(PCH_DPLL(pll->id));
9494         udelay(200);
9495 }
9496
9497 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9498                                  struct intel_shared_dpll *pll)
9499 {
9500         struct drm_device *dev = dev_priv->dev;
9501         struct intel_crtc *crtc;
9502
9503         /* Make sure no transcoder isn't still depending on us. */
9504         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9505                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9506                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9507         }
9508
9509         I915_WRITE(PCH_DPLL(pll->id), 0);
9510         POSTING_READ(PCH_DPLL(pll->id));
9511         udelay(200);
9512 }
9513
9514 static char *ibx_pch_dpll_names[] = {
9515         "PCH DPLL A",
9516         "PCH DPLL B",
9517 };
9518
9519 static void ibx_pch_dpll_init(struct drm_device *dev)
9520 {
9521         struct drm_i915_private *dev_priv = dev->dev_private;
9522         int i;
9523
9524         dev_priv->num_shared_dpll = 2;
9525
9526         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9527                 dev_priv->shared_dplls[i].id = i;
9528                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9529                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9530                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9531                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9532                 dev_priv->shared_dplls[i].get_hw_state =
9533                         ibx_pch_dpll_get_hw_state;
9534         }
9535 }
9536
9537 static void intel_shared_dpll_init(struct drm_device *dev)
9538 {
9539         struct drm_i915_private *dev_priv = dev->dev_private;
9540
9541         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9542                 ibx_pch_dpll_init(dev);
9543         else
9544                 dev_priv->num_shared_dpll = 0;
9545
9546         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9547         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9548                       dev_priv->num_shared_dpll);
9549 }
9550
9551 static void intel_crtc_init(struct drm_device *dev, int pipe)
9552 {
9553         drm_i915_private_t *dev_priv = dev->dev_private;
9554         struct intel_crtc *intel_crtc;
9555         int i;
9556
9557         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9558         if (intel_crtc == NULL)
9559                 return;
9560
9561         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9562
9563         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9564         for (i = 0; i < 256; i++) {
9565                 intel_crtc->lut_r[i] = i;
9566                 intel_crtc->lut_g[i] = i;
9567                 intel_crtc->lut_b[i] = i;
9568         }
9569
9570         /* Swap pipes & planes for FBC on pre-965 */
9571         intel_crtc->pipe = pipe;
9572         intel_crtc->plane = pipe;
9573         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9574                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9575                 intel_crtc->plane = !pipe;
9576         }
9577
9578         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9579                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9580         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9581         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9582
9583         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9584 }
9585
9586 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9587                                 struct drm_file *file)
9588 {
9589         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9590         struct drm_mode_object *drmmode_obj;
9591         struct intel_crtc *crtc;
9592
9593         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9594                 return -ENODEV;
9595
9596         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9597                         DRM_MODE_OBJECT_CRTC);
9598
9599         if (!drmmode_obj) {
9600                 DRM_ERROR("no such CRTC id\n");
9601                 return -EINVAL;
9602         }
9603
9604         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9605         pipe_from_crtc_id->pipe = crtc->pipe;
9606
9607         return 0;
9608 }
9609
9610 static int intel_encoder_clones(struct intel_encoder *encoder)
9611 {
9612         struct drm_device *dev = encoder->base.dev;
9613         struct intel_encoder *source_encoder;
9614         int index_mask = 0;
9615         int entry = 0;
9616
9617         list_for_each_entry(source_encoder,
9618                             &dev->mode_config.encoder_list, base.head) {
9619
9620                 if (encoder == source_encoder)
9621                         index_mask |= (1 << entry);
9622
9623                 /* Intel hw has only one MUX where enocoders could be cloned. */
9624                 if (encoder->cloneable && source_encoder->cloneable)
9625                         index_mask |= (1 << entry);
9626
9627                 entry++;
9628         }
9629
9630         return index_mask;
9631 }
9632
9633 static bool has_edp_a(struct drm_device *dev)
9634 {
9635         struct drm_i915_private *dev_priv = dev->dev_private;
9636
9637         if (!IS_MOBILE(dev))
9638                 return false;
9639
9640         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9641                 return false;
9642
9643         if (IS_GEN5(dev) &&
9644             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9645                 return false;
9646
9647         return true;
9648 }
9649
9650 static void intel_setup_outputs(struct drm_device *dev)
9651 {
9652         struct drm_i915_private *dev_priv = dev->dev_private;
9653         struct intel_encoder *encoder;
9654         bool dpd_is_edp = false;
9655
9656         intel_lvds_init(dev);
9657
9658         if (!IS_ULT(dev))
9659                 intel_crt_init(dev);
9660
9661         if (HAS_DDI(dev)) {
9662                 int found;
9663
9664                 /* Haswell uses DDI functions to detect digital outputs */
9665                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9666                 /* DDI A only supports eDP */
9667                 if (found)
9668                         intel_ddi_init(dev, PORT_A);
9669
9670                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9671                  * register */
9672                 found = I915_READ(SFUSE_STRAP);
9673
9674                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9675                         intel_ddi_init(dev, PORT_B);
9676                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9677                         intel_ddi_init(dev, PORT_C);
9678                 if (found & SFUSE_STRAP_DDID_DETECTED)
9679                         intel_ddi_init(dev, PORT_D);
9680         } else if (HAS_PCH_SPLIT(dev)) {
9681                 int found;
9682                 dpd_is_edp = intel_dpd_is_edp(dev);
9683
9684                 if (has_edp_a(dev))
9685                         intel_dp_init(dev, DP_A, PORT_A);
9686
9687                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9688                         /* PCH SDVOB multiplex with HDMIB */
9689                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9690                         if (!found)
9691                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9692                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9693                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9694                 }
9695
9696                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9697                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9698
9699                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9700                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9701
9702                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9703                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9704
9705                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9706                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9707         } else if (IS_VALLEYVIEW(dev)) {
9708                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9709                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9710                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9711                                         PORT_C);
9712                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9713                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9714                                               PORT_C);
9715                 }
9716
9717                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9718                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9719                                         PORT_B);
9720                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9721                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9722                 }
9723
9724                 intel_dsi_init(dev);
9725         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9726                 bool found = false;
9727
9728                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9729                         DRM_DEBUG_KMS("probing SDVOB\n");
9730                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9731                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9732                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9733                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9734                         }
9735
9736                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9737                                 intel_dp_init(dev, DP_B, PORT_B);
9738                 }
9739
9740                 /* Before G4X SDVOC doesn't have its own detect register */
9741
9742                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9743                         DRM_DEBUG_KMS("probing SDVOC\n");
9744                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9745                 }
9746
9747                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9748
9749                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9750                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9751                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9752                         }
9753                         if (SUPPORTS_INTEGRATED_DP(dev))
9754                                 intel_dp_init(dev, DP_C, PORT_C);
9755                 }
9756
9757                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9758                     (I915_READ(DP_D) & DP_DETECTED))
9759                         intel_dp_init(dev, DP_D, PORT_D);
9760         } else if (IS_GEN2(dev))
9761                 intel_dvo_init(dev);
9762
9763         if (SUPPORTS_TV(dev))
9764                 intel_tv_init(dev);
9765
9766         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9767                 encoder->base.possible_crtcs = encoder->crtc_mask;
9768                 encoder->base.possible_clones =
9769                         intel_encoder_clones(encoder);
9770         }
9771
9772         intel_init_pch_refclk(dev);
9773
9774         drm_helper_move_panel_connectors_to_head(dev);
9775 }
9776
9777 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9778 {
9779         drm_framebuffer_cleanup(&fb->base);
9780         drm_gem_object_unreference_unlocked(&fb->obj->base);
9781 }
9782
9783 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9784 {
9785         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9786
9787         intel_framebuffer_fini(intel_fb);
9788         kfree(intel_fb);
9789 }
9790
9791 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9792                                                 struct drm_file *file,
9793                                                 unsigned int *handle)
9794 {
9795         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9796         struct drm_i915_gem_object *obj = intel_fb->obj;
9797
9798         return drm_gem_handle_create(file, &obj->base, handle);
9799 }
9800
9801 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9802         .destroy = intel_user_framebuffer_destroy,
9803         .create_handle = intel_user_framebuffer_create_handle,
9804 };
9805
9806 int intel_framebuffer_init(struct drm_device *dev,
9807                            struct intel_framebuffer *intel_fb,
9808                            struct drm_mode_fb_cmd2 *mode_cmd,
9809                            struct drm_i915_gem_object *obj)
9810 {
9811         int pitch_limit;
9812         int ret;
9813
9814         if (obj->tiling_mode == I915_TILING_Y) {
9815                 DRM_DEBUG("hardware does not support tiling Y\n");
9816                 return -EINVAL;
9817         }
9818
9819         if (mode_cmd->pitches[0] & 63) {
9820                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9821                           mode_cmd->pitches[0]);
9822                 return -EINVAL;
9823         }
9824
9825         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9826                 pitch_limit = 32*1024;
9827         } else if (INTEL_INFO(dev)->gen >= 4) {
9828                 if (obj->tiling_mode)
9829                         pitch_limit = 16*1024;
9830                 else
9831                         pitch_limit = 32*1024;
9832         } else if (INTEL_INFO(dev)->gen >= 3) {
9833                 if (obj->tiling_mode)
9834                         pitch_limit = 8*1024;
9835                 else
9836                         pitch_limit = 16*1024;
9837         } else
9838                 /* XXX DSPC is limited to 4k tiled */
9839                 pitch_limit = 8*1024;
9840
9841         if (mode_cmd->pitches[0] > pitch_limit) {
9842                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9843                           obj->tiling_mode ? "tiled" : "linear",
9844                           mode_cmd->pitches[0], pitch_limit);
9845                 return -EINVAL;
9846         }
9847
9848         if (obj->tiling_mode != I915_TILING_NONE &&
9849             mode_cmd->pitches[0] != obj->stride) {
9850                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9851                           mode_cmd->pitches[0], obj->stride);
9852                 return -EINVAL;
9853         }
9854
9855         /* Reject formats not supported by any plane early. */
9856         switch (mode_cmd->pixel_format) {
9857         case DRM_FORMAT_C8:
9858         case DRM_FORMAT_RGB565:
9859         case DRM_FORMAT_XRGB8888:
9860         case DRM_FORMAT_ARGB8888:
9861                 break;
9862         case DRM_FORMAT_XRGB1555:
9863         case DRM_FORMAT_ARGB1555:
9864                 if (INTEL_INFO(dev)->gen > 3) {
9865                         DRM_DEBUG("unsupported pixel format: %s\n",
9866                                   drm_get_format_name(mode_cmd->pixel_format));
9867                         return -EINVAL;
9868                 }
9869                 break;
9870         case DRM_FORMAT_XBGR8888:
9871         case DRM_FORMAT_ABGR8888:
9872         case DRM_FORMAT_XRGB2101010:
9873         case DRM_FORMAT_ARGB2101010:
9874         case DRM_FORMAT_XBGR2101010:
9875         case DRM_FORMAT_ABGR2101010:
9876                 if (INTEL_INFO(dev)->gen < 4) {
9877                         DRM_DEBUG("unsupported pixel format: %s\n",
9878                                   drm_get_format_name(mode_cmd->pixel_format));
9879                         return -EINVAL;
9880                 }
9881                 break;
9882         case DRM_FORMAT_YUYV:
9883         case DRM_FORMAT_UYVY:
9884         case DRM_FORMAT_YVYU:
9885         case DRM_FORMAT_VYUY:
9886                 if (INTEL_INFO(dev)->gen < 5) {
9887                         DRM_DEBUG("unsupported pixel format: %s\n",
9888                                   drm_get_format_name(mode_cmd->pixel_format));
9889                         return -EINVAL;
9890                 }
9891                 break;
9892         default:
9893                 DRM_DEBUG("unsupported pixel format: %s\n",
9894                           drm_get_format_name(mode_cmd->pixel_format));
9895                 return -EINVAL;
9896         }
9897
9898         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9899         if (mode_cmd->offsets[0] != 0)
9900                 return -EINVAL;
9901
9902         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9903         intel_fb->obj = obj;
9904
9905         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9906         if (ret) {
9907                 DRM_ERROR("framebuffer init failed %d\n", ret);
9908                 return ret;
9909         }
9910
9911         return 0;
9912 }
9913
9914 static struct drm_framebuffer *
9915 intel_user_framebuffer_create(struct drm_device *dev,
9916                               struct drm_file *filp,
9917                               struct drm_mode_fb_cmd2 *mode_cmd)
9918 {
9919         struct drm_i915_gem_object *obj;
9920
9921         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9922                                                 mode_cmd->handles[0]));
9923         if (&obj->base == NULL)
9924                 return ERR_PTR(-ENOENT);
9925
9926         return intel_framebuffer_create(dev, mode_cmd, obj);
9927 }
9928
9929 static const struct drm_mode_config_funcs intel_mode_funcs = {
9930         .fb_create = intel_user_framebuffer_create,
9931         .output_poll_changed = intel_fb_output_poll_changed,
9932 };
9933
9934 /* Set up chip specific display functions */
9935 static void intel_init_display(struct drm_device *dev)
9936 {
9937         struct drm_i915_private *dev_priv = dev->dev_private;
9938
9939         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9940                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9941         else if (IS_VALLEYVIEW(dev))
9942                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9943         else if (IS_PINEVIEW(dev))
9944                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9945         else
9946                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9947
9948         if (HAS_DDI(dev)) {
9949                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9950                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9951                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9952                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9953                 dev_priv->display.off = haswell_crtc_off;
9954                 dev_priv->display.update_plane = ironlake_update_plane;
9955         } else if (HAS_PCH_SPLIT(dev)) {
9956                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9957                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9958                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9959                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9960                 dev_priv->display.off = ironlake_crtc_off;
9961                 dev_priv->display.update_plane = ironlake_update_plane;
9962         } else if (IS_VALLEYVIEW(dev)) {
9963                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9964                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9965                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9966                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9967                 dev_priv->display.off = i9xx_crtc_off;
9968                 dev_priv->display.update_plane = i9xx_update_plane;
9969         } else {
9970                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9971                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9972                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9973                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9974                 dev_priv->display.off = i9xx_crtc_off;
9975                 dev_priv->display.update_plane = i9xx_update_plane;
9976         }
9977
9978         /* Returns the core display clock speed */
9979         if (IS_VALLEYVIEW(dev))
9980                 dev_priv->display.get_display_clock_speed =
9981                         valleyview_get_display_clock_speed;
9982         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9983                 dev_priv->display.get_display_clock_speed =
9984                         i945_get_display_clock_speed;
9985         else if (IS_I915G(dev))
9986                 dev_priv->display.get_display_clock_speed =
9987                         i915_get_display_clock_speed;
9988         else if (IS_I945GM(dev) || IS_845G(dev))
9989                 dev_priv->display.get_display_clock_speed =
9990                         i9xx_misc_get_display_clock_speed;
9991         else if (IS_PINEVIEW(dev))
9992                 dev_priv->display.get_display_clock_speed =
9993                         pnv_get_display_clock_speed;
9994         else if (IS_I915GM(dev))
9995                 dev_priv->display.get_display_clock_speed =
9996                         i915gm_get_display_clock_speed;
9997         else if (IS_I865G(dev))
9998                 dev_priv->display.get_display_clock_speed =
9999                         i865_get_display_clock_speed;
10000         else if (IS_I85X(dev))
10001                 dev_priv->display.get_display_clock_speed =
10002                         i855_get_display_clock_speed;
10003         else /* 852, 830 */
10004                 dev_priv->display.get_display_clock_speed =
10005                         i830_get_display_clock_speed;
10006
10007         if (HAS_PCH_SPLIT(dev)) {
10008                 if (IS_GEN5(dev)) {
10009                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10010                         dev_priv->display.write_eld = ironlake_write_eld;
10011                 } else if (IS_GEN6(dev)) {
10012                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10013                         dev_priv->display.write_eld = ironlake_write_eld;
10014                 } else if (IS_IVYBRIDGE(dev)) {
10015                         /* FIXME: detect B0+ stepping and use auto training */
10016                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10017                         dev_priv->display.write_eld = ironlake_write_eld;
10018                         dev_priv->display.modeset_global_resources =
10019                                 ivb_modeset_global_resources;
10020                 } else if (IS_HASWELL(dev)) {
10021                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10022                         dev_priv->display.write_eld = haswell_write_eld;
10023                         dev_priv->display.modeset_global_resources =
10024                                 haswell_modeset_global_resources;
10025                 }
10026         } else if (IS_G4X(dev)) {
10027                 dev_priv->display.write_eld = g4x_write_eld;
10028         }
10029
10030         /* Default just returns -ENODEV to indicate unsupported */
10031         dev_priv->display.queue_flip = intel_default_queue_flip;
10032
10033         switch (INTEL_INFO(dev)->gen) {
10034         case 2:
10035                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10036                 break;
10037
10038         case 3:
10039                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10040                 break;
10041
10042         case 4:
10043         case 5:
10044                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10045                 break;
10046
10047         case 6:
10048                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10049                 break;
10050         case 7:
10051                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10052                 break;
10053         }
10054 }
10055
10056 /*
10057  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10058  * resume, or other times.  This quirk makes sure that's the case for
10059  * affected systems.
10060  */
10061 static void quirk_pipea_force(struct drm_device *dev)
10062 {
10063         struct drm_i915_private *dev_priv = dev->dev_private;
10064
10065         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10066         DRM_INFO("applying pipe a force quirk\n");
10067 }
10068
10069 /*
10070  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10071  */
10072 static void quirk_ssc_force_disable(struct drm_device *dev)
10073 {
10074         struct drm_i915_private *dev_priv = dev->dev_private;
10075         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10076         DRM_INFO("applying lvds SSC disable quirk\n");
10077 }
10078
10079 /*
10080  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10081  * brightness value
10082  */
10083 static void quirk_invert_brightness(struct drm_device *dev)
10084 {
10085         struct drm_i915_private *dev_priv = dev->dev_private;
10086         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10087         DRM_INFO("applying inverted panel brightness quirk\n");
10088 }
10089
10090 /*
10091  * Some machines (Dell XPS13) suffer broken backlight controls if
10092  * BLM_PCH_PWM_ENABLE is set.
10093  */
10094 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10095 {
10096         struct drm_i915_private *dev_priv = dev->dev_private;
10097         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10098         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10099 }
10100
10101 struct intel_quirk {
10102         int device;
10103         int subsystem_vendor;
10104         int subsystem_device;
10105         void (*hook)(struct drm_device *dev);
10106 };
10107
10108 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10109 struct intel_dmi_quirk {
10110         void (*hook)(struct drm_device *dev);
10111         const struct dmi_system_id (*dmi_id_list)[];
10112 };
10113
10114 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10115 {
10116         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10117         return 1;
10118 }
10119
10120 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10121         {
10122                 .dmi_id_list = &(const struct dmi_system_id[]) {
10123                         {
10124                                 .callback = intel_dmi_reverse_brightness,
10125                                 .ident = "NCR Corporation",
10126                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10127                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10128                                 },
10129                         },
10130                         { }  /* terminating entry */
10131                 },
10132                 .hook = quirk_invert_brightness,
10133         },
10134 };
10135
10136 static struct intel_quirk intel_quirks[] = {
10137         /* HP Mini needs pipe A force quirk (LP: #322104) */
10138         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10139
10140         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10141         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10142
10143         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10144         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10145
10146         /* 830/845 need to leave pipe A & dpll A up */
10147         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10148         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10149
10150         /* Lenovo U160 cannot use SSC on LVDS */
10151         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10152
10153         /* Sony Vaio Y cannot use SSC on LVDS */
10154         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10155
10156         /* Acer Aspire 5734Z must invert backlight brightness */
10157         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
10158
10159         /* Acer/eMachines G725 */
10160         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
10161
10162         /* Acer/eMachines e725 */
10163         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
10164
10165         /* Acer/Packard Bell NCL20 */
10166         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
10167
10168         /* Acer Aspire 4736Z */
10169         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
10170
10171         /* Dell XPS13 HD Sandy Bridge */
10172         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10173         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10174         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10175 };
10176
10177 static void intel_init_quirks(struct drm_device *dev)
10178 {
10179         struct pci_dev *d = dev->pdev;
10180         int i;
10181
10182         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10183                 struct intel_quirk *q = &intel_quirks[i];
10184
10185                 if (d->device == q->device &&
10186                     (d->subsystem_vendor == q->subsystem_vendor ||
10187                      q->subsystem_vendor == PCI_ANY_ID) &&
10188                     (d->subsystem_device == q->subsystem_device ||
10189                      q->subsystem_device == PCI_ANY_ID))
10190                         q->hook(dev);
10191         }
10192         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10193                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10194                         intel_dmi_quirks[i].hook(dev);
10195         }
10196 }
10197
10198 /* Disable the VGA plane that we never use */
10199 static void i915_disable_vga(struct drm_device *dev)
10200 {
10201         struct drm_i915_private *dev_priv = dev->dev_private;
10202         u8 sr1;
10203         u32 vga_reg = i915_vgacntrl_reg(dev);
10204
10205         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10206         outb(SR01, VGA_SR_INDEX);
10207         sr1 = inb(VGA_SR_DATA);
10208         outb(sr1 | 1<<5, VGA_SR_DATA);
10209
10210         /* Disable VGA memory on Intel HD */
10211         if (HAS_PCH_SPLIT(dev)) {
10212                 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10213                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10214                                                    VGA_RSRC_NORMAL_IO |
10215                                                    VGA_RSRC_NORMAL_MEM);
10216         }
10217
10218         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10219         udelay(300);
10220
10221         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10222         POSTING_READ(vga_reg);
10223 }
10224
10225 static void i915_enable_vga(struct drm_device *dev)
10226 {
10227         /* Enable VGA memory on Intel HD */
10228         if (HAS_PCH_SPLIT(dev)) {
10229                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10230                 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10231                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10232                                                    VGA_RSRC_LEGACY_MEM |
10233                                                    VGA_RSRC_NORMAL_IO |
10234                                                    VGA_RSRC_NORMAL_MEM);
10235                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10236         }
10237 }
10238
10239 void intel_modeset_init_hw(struct drm_device *dev)
10240 {
10241         intel_init_power_well(dev);
10242
10243         intel_prepare_ddi(dev);
10244
10245         intel_init_clock_gating(dev);
10246
10247         mutex_lock(&dev->struct_mutex);
10248         intel_enable_gt_powersave(dev);
10249         mutex_unlock(&dev->struct_mutex);
10250 }
10251
10252 void intel_modeset_suspend_hw(struct drm_device *dev)
10253 {
10254         intel_suspend_hw(dev);
10255 }
10256
10257 void intel_modeset_init(struct drm_device *dev)
10258 {
10259         struct drm_i915_private *dev_priv = dev->dev_private;
10260         int i, j, ret;
10261
10262         drm_mode_config_init(dev);
10263
10264         dev->mode_config.min_width = 0;
10265         dev->mode_config.min_height = 0;
10266
10267         dev->mode_config.preferred_depth = 24;
10268         dev->mode_config.prefer_shadow = 1;
10269
10270         dev->mode_config.funcs = &intel_mode_funcs;
10271
10272         intel_init_quirks(dev);
10273
10274         intel_init_pm(dev);
10275
10276         if (INTEL_INFO(dev)->num_pipes == 0)
10277                 return;
10278
10279         intel_init_display(dev);
10280
10281         if (IS_GEN2(dev)) {
10282                 dev->mode_config.max_width = 2048;
10283                 dev->mode_config.max_height = 2048;
10284         } else if (IS_GEN3(dev)) {
10285                 dev->mode_config.max_width = 4096;
10286                 dev->mode_config.max_height = 4096;
10287         } else {
10288                 dev->mode_config.max_width = 8192;
10289                 dev->mode_config.max_height = 8192;
10290         }
10291         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10292
10293         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10294                       INTEL_INFO(dev)->num_pipes,
10295                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10296
10297         for_each_pipe(i) {
10298                 intel_crtc_init(dev, i);
10299                 for (j = 0; j < dev_priv->num_plane; j++) {
10300                         ret = intel_plane_init(dev, i, j);
10301                         if (ret)
10302                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10303                                               pipe_name(i), sprite_name(i, j), ret);
10304                 }
10305         }
10306
10307         intel_cpu_pll_init(dev);
10308         intel_shared_dpll_init(dev);
10309
10310         /* Just disable it once at startup */
10311         i915_disable_vga(dev);
10312         intel_setup_outputs(dev);
10313
10314         /* Just in case the BIOS is doing something questionable. */
10315         intel_disable_fbc(dev);
10316 }
10317
10318 static void
10319 intel_connector_break_all_links(struct intel_connector *connector)
10320 {
10321         connector->base.dpms = DRM_MODE_DPMS_OFF;
10322         connector->base.encoder = NULL;
10323         connector->encoder->connectors_active = false;
10324         connector->encoder->base.crtc = NULL;
10325 }
10326
10327 static void intel_enable_pipe_a(struct drm_device *dev)
10328 {
10329         struct intel_connector *connector;
10330         struct drm_connector *crt = NULL;
10331         struct intel_load_detect_pipe load_detect_temp;
10332
10333         /* We can't just switch on the pipe A, we need to set things up with a
10334          * proper mode and output configuration. As a gross hack, enable pipe A
10335          * by enabling the load detect pipe once. */
10336         list_for_each_entry(connector,
10337                             &dev->mode_config.connector_list,
10338                             base.head) {
10339                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10340                         crt = &connector->base;
10341                         break;
10342                 }
10343         }
10344
10345         if (!crt)
10346                 return;
10347
10348         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10349                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10350
10351
10352 }
10353
10354 static bool
10355 intel_check_plane_mapping(struct intel_crtc *crtc)
10356 {
10357         struct drm_device *dev = crtc->base.dev;
10358         struct drm_i915_private *dev_priv = dev->dev_private;
10359         u32 reg, val;
10360
10361         if (INTEL_INFO(dev)->num_pipes == 1)
10362                 return true;
10363
10364         reg = DSPCNTR(!crtc->plane);
10365         val = I915_READ(reg);
10366
10367         if ((val & DISPLAY_PLANE_ENABLE) &&
10368             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10369                 return false;
10370
10371         return true;
10372 }
10373
10374 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10375 {
10376         struct drm_device *dev = crtc->base.dev;
10377         struct drm_i915_private *dev_priv = dev->dev_private;
10378         u32 reg;
10379
10380         /* Clear any frame start delays used for debugging left by the BIOS */
10381         reg = PIPECONF(crtc->config.cpu_transcoder);
10382         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10383
10384         /* We need to sanitize the plane -> pipe mapping first because this will
10385          * disable the crtc (and hence change the state) if it is wrong. Note
10386          * that gen4+ has a fixed plane -> pipe mapping.  */
10387         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10388                 struct intel_connector *connector;
10389                 bool plane;
10390
10391                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10392                               crtc->base.base.id);
10393
10394                 /* Pipe has the wrong plane attached and the plane is active.
10395                  * Temporarily change the plane mapping and disable everything
10396                  * ...  */
10397                 plane = crtc->plane;
10398                 crtc->plane = !plane;
10399                 dev_priv->display.crtc_disable(&crtc->base);
10400                 crtc->plane = plane;
10401
10402                 /* ... and break all links. */
10403                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10404                                     base.head) {
10405                         if (connector->encoder->base.crtc != &crtc->base)
10406                                 continue;
10407
10408                         intel_connector_break_all_links(connector);
10409                 }
10410
10411                 WARN_ON(crtc->active);
10412                 crtc->base.enabled = false;
10413         }
10414
10415         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10416             crtc->pipe == PIPE_A && !crtc->active) {
10417                 /* BIOS forgot to enable pipe A, this mostly happens after
10418                  * resume. Force-enable the pipe to fix this, the update_dpms
10419                  * call below we restore the pipe to the right state, but leave
10420                  * the required bits on. */
10421                 intel_enable_pipe_a(dev);
10422         }
10423
10424         /* Adjust the state of the output pipe according to whether we
10425          * have active connectors/encoders. */
10426         intel_crtc_update_dpms(&crtc->base);
10427
10428         if (crtc->active != crtc->base.enabled) {
10429                 struct intel_encoder *encoder;
10430
10431                 /* This can happen either due to bugs in the get_hw_state
10432                  * functions or because the pipe is force-enabled due to the
10433                  * pipe A quirk. */
10434                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10435                               crtc->base.base.id,
10436                               crtc->base.enabled ? "enabled" : "disabled",
10437                               crtc->active ? "enabled" : "disabled");
10438
10439                 crtc->base.enabled = crtc->active;
10440
10441                 /* Because we only establish the connector -> encoder ->
10442                  * crtc links if something is active, this means the
10443                  * crtc is now deactivated. Break the links. connector
10444                  * -> encoder links are only establish when things are
10445                  *  actually up, hence no need to break them. */
10446                 WARN_ON(crtc->active);
10447
10448                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10449                         WARN_ON(encoder->connectors_active);
10450                         encoder->base.crtc = NULL;
10451                 }
10452         }
10453 }
10454
10455 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10456 {
10457         struct intel_connector *connector;
10458         struct drm_device *dev = encoder->base.dev;
10459
10460         /* We need to check both for a crtc link (meaning that the
10461          * encoder is active and trying to read from a pipe) and the
10462          * pipe itself being active. */
10463         bool has_active_crtc = encoder->base.crtc &&
10464                 to_intel_crtc(encoder->base.crtc)->active;
10465
10466         if (encoder->connectors_active && !has_active_crtc) {
10467                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10468                               encoder->base.base.id,
10469                               drm_get_encoder_name(&encoder->base));
10470
10471                 /* Connector is active, but has no active pipe. This is
10472                  * fallout from our resume register restoring. Disable
10473                  * the encoder manually again. */
10474                 if (encoder->base.crtc) {
10475                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10476                                       encoder->base.base.id,
10477                                       drm_get_encoder_name(&encoder->base));
10478                         encoder->disable(encoder);
10479                 }
10480
10481                 /* Inconsistent output/port/pipe state happens presumably due to
10482                  * a bug in one of the get_hw_state functions. Or someplace else
10483                  * in our code, like the register restore mess on resume. Clamp
10484                  * things to off as a safer default. */
10485                 list_for_each_entry(connector,
10486                                     &dev->mode_config.connector_list,
10487                                     base.head) {
10488                         if (connector->encoder != encoder)
10489                                 continue;
10490
10491                         intel_connector_break_all_links(connector);
10492                 }
10493         }
10494         /* Enabled encoders without active connectors will be fixed in
10495          * the crtc fixup. */
10496 }
10497
10498 void i915_redisable_vga(struct drm_device *dev)
10499 {
10500         struct drm_i915_private *dev_priv = dev->dev_private;
10501         u32 vga_reg = i915_vgacntrl_reg(dev);
10502
10503         /* This function can be called both from intel_modeset_setup_hw_state or
10504          * at a very early point in our resume sequence, where the power well
10505          * structures are not yet restored. Since this function is at a very
10506          * paranoid "someone might have enabled VGA while we were not looking"
10507          * level, just check if the power well is enabled instead of trying to
10508          * follow the "don't touch the power well if we don't need it" policy
10509          * the rest of the driver uses. */
10510         if (HAS_POWER_WELL(dev) &&
10511             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10512                 return;
10513
10514         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10515                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10516                 i915_disable_vga(dev);
10517         }
10518 }
10519
10520 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10521 {
10522         struct drm_i915_private *dev_priv = dev->dev_private;
10523         enum pipe pipe;
10524         struct intel_crtc *crtc;
10525         struct intel_encoder *encoder;
10526         struct intel_connector *connector;
10527         int i;
10528
10529         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10530                             base.head) {
10531                 memset(&crtc->config, 0, sizeof(crtc->config));
10532
10533                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10534                                                                  &crtc->config);
10535
10536                 crtc->base.enabled = crtc->active;
10537
10538                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10539                               crtc->base.base.id,
10540                               crtc->active ? "enabled" : "disabled");
10541         }
10542
10543         /* FIXME: Smash this into the new shared dpll infrastructure. */
10544         if (HAS_DDI(dev))
10545                 intel_ddi_setup_hw_pll_state(dev);
10546
10547         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10548                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10549
10550                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10551                 pll->active = 0;
10552                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10553                                     base.head) {
10554                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10555                                 pll->active++;
10556                 }
10557                 pll->refcount = pll->active;
10558
10559                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10560                               pll->name, pll->refcount, pll->on);
10561         }
10562
10563         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10564                             base.head) {
10565                 pipe = 0;
10566
10567                 if (encoder->get_hw_state(encoder, &pipe)) {
10568                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10569                         encoder->base.crtc = &crtc->base;
10570                         if (encoder->get_config)
10571                                 encoder->get_config(encoder, &crtc->config);
10572                 } else {
10573                         encoder->base.crtc = NULL;
10574                 }
10575
10576                 encoder->connectors_active = false;
10577                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10578                               encoder->base.base.id,
10579                               drm_get_encoder_name(&encoder->base),
10580                               encoder->base.crtc ? "enabled" : "disabled",
10581                               pipe);
10582         }
10583
10584         list_for_each_entry(connector, &dev->mode_config.connector_list,
10585                             base.head) {
10586                 if (connector->get_hw_state(connector)) {
10587                         connector->base.dpms = DRM_MODE_DPMS_ON;
10588                         connector->encoder->connectors_active = true;
10589                         connector->base.encoder = &connector->encoder->base;
10590                 } else {
10591                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10592                         connector->base.encoder = NULL;
10593                 }
10594                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10595                               connector->base.base.id,
10596                               drm_get_connector_name(&connector->base),
10597                               connector->base.encoder ? "enabled" : "disabled");
10598         }
10599 }
10600
10601 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10602  * and i915 state tracking structures. */
10603 void intel_modeset_setup_hw_state(struct drm_device *dev,
10604                                   bool force_restore)
10605 {
10606         struct drm_i915_private *dev_priv = dev->dev_private;
10607         enum pipe pipe;
10608         struct drm_plane *plane;
10609         struct intel_crtc *crtc;
10610         struct intel_encoder *encoder;
10611         int i;
10612
10613         intel_modeset_readout_hw_state(dev);
10614
10615         /*
10616          * Now that we have the config, copy it to each CRTC struct
10617          * Note that this could go away if we move to using crtc_config
10618          * checking everywhere.
10619          */
10620         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10621                             base.head) {
10622                 if (crtc->active && i915_fastboot) {
10623                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10624
10625                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10626                                       crtc->base.base.id);
10627                         drm_mode_debug_printmodeline(&crtc->base.mode);
10628                 }
10629         }
10630
10631         /* HW state is read out, now we need to sanitize this mess. */
10632         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10633                             base.head) {
10634                 intel_sanitize_encoder(encoder);
10635         }
10636
10637         for_each_pipe(pipe) {
10638                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10639                 intel_sanitize_crtc(crtc);
10640                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10641         }
10642
10643         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10644                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10645
10646                 if (!pll->on || pll->active)
10647                         continue;
10648
10649                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10650
10651                 pll->disable(dev_priv, pll);
10652                 pll->on = false;
10653         }
10654
10655         if (force_restore) {
10656                 /*
10657                  * We need to use raw interfaces for restoring state to avoid
10658                  * checking (bogus) intermediate states.
10659                  */
10660                 for_each_pipe(pipe) {
10661                         struct drm_crtc *crtc =
10662                                 dev_priv->pipe_to_crtc_mapping[pipe];
10663
10664                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10665                                          crtc->fb);
10666                 }
10667                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10668                         intel_plane_restore(plane);
10669
10670                 i915_redisable_vga(dev);
10671         } else {
10672                 intel_modeset_update_staged_output_state(dev);
10673         }
10674
10675         intel_modeset_check_state(dev);
10676
10677         drm_mode_config_reset(dev);
10678 }
10679
10680 void intel_modeset_gem_init(struct drm_device *dev)
10681 {
10682         intel_modeset_init_hw(dev);
10683
10684         intel_setup_overlay(dev);
10685
10686         intel_modeset_setup_hw_state(dev, false);
10687 }
10688
10689 void intel_modeset_cleanup(struct drm_device *dev)
10690 {
10691         struct drm_i915_private *dev_priv = dev->dev_private;
10692         struct drm_crtc *crtc;
10693
10694         /*
10695          * Interrupts and polling as the first thing to avoid creating havoc.
10696          * Too much stuff here (turning of rps, connectors, ...) would
10697          * experience fancy races otherwise.
10698          */
10699         drm_irq_uninstall(dev);
10700         cancel_work_sync(&dev_priv->hotplug_work);
10701         /*
10702          * Due to the hpd irq storm handling the hotplug work can re-arm the
10703          * poll handlers. Hence disable polling after hpd handling is shut down.
10704          */
10705         drm_kms_helper_poll_fini(dev);
10706
10707         mutex_lock(&dev->struct_mutex);
10708
10709         intel_unregister_dsm_handler();
10710
10711         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10712                 /* Skip inactive CRTCs */
10713                 if (!crtc->fb)
10714                         continue;
10715
10716                 intel_increase_pllclock(crtc);
10717         }
10718
10719         intel_disable_fbc(dev);
10720
10721         i915_enable_vga(dev);
10722
10723         intel_disable_gt_powersave(dev);
10724
10725         ironlake_teardown_rc6(dev);
10726
10727         mutex_unlock(&dev->struct_mutex);
10728
10729         /* flush any delayed tasks or pending work */
10730         flush_scheduled_work();
10731
10732         /* destroy backlight, if any, before the connectors */
10733         intel_panel_destroy_backlight(dev);
10734
10735         drm_mode_config_cleanup(dev);
10736
10737         intel_cleanup_overlay(dev);
10738 }
10739
10740 /*
10741  * Return which encoder is currently attached for connector.
10742  */
10743 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10744 {
10745         return &intel_attached_encoder(connector)->base;
10746 }
10747
10748 void intel_connector_attach_encoder(struct intel_connector *connector,
10749                                     struct intel_encoder *encoder)
10750 {
10751         connector->encoder = encoder;
10752         drm_mode_connector_attach_encoder(&connector->base,
10753                                           &encoder->base);
10754 }
10755
10756 /*
10757  * set vga decode state - true == enable VGA decode
10758  */
10759 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10760 {
10761         struct drm_i915_private *dev_priv = dev->dev_private;
10762         u16 gmch_ctrl;
10763
10764         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10765         if (state)
10766                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10767         else
10768                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10769         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10770         return 0;
10771 }
10772
10773 struct intel_display_error_state {
10774
10775         u32 power_well_driver;
10776
10777         int num_transcoders;
10778
10779         struct intel_cursor_error_state {
10780                 u32 control;
10781                 u32 position;
10782                 u32 base;
10783                 u32 size;
10784         } cursor[I915_MAX_PIPES];
10785
10786         struct intel_pipe_error_state {
10787                 u32 source;
10788         } pipe[I915_MAX_PIPES];
10789
10790         struct intel_plane_error_state {
10791                 u32 control;
10792                 u32 stride;
10793                 u32 size;
10794                 u32 pos;
10795                 u32 addr;
10796                 u32 surface;
10797                 u32 tile_offset;
10798         } plane[I915_MAX_PIPES];
10799
10800         struct intel_transcoder_error_state {
10801                 enum transcoder cpu_transcoder;
10802
10803                 u32 conf;
10804
10805                 u32 htotal;
10806                 u32 hblank;
10807                 u32 hsync;
10808                 u32 vtotal;
10809                 u32 vblank;
10810                 u32 vsync;
10811         } transcoder[4];
10812 };
10813
10814 struct intel_display_error_state *
10815 intel_display_capture_error_state(struct drm_device *dev)
10816 {
10817         drm_i915_private_t *dev_priv = dev->dev_private;
10818         struct intel_display_error_state *error;
10819         int transcoders[] = {
10820                 TRANSCODER_A,
10821                 TRANSCODER_B,
10822                 TRANSCODER_C,
10823                 TRANSCODER_EDP,
10824         };
10825         int i;
10826
10827         if (INTEL_INFO(dev)->num_pipes == 0)
10828                 return NULL;
10829
10830         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10831         if (error == NULL)
10832                 return NULL;
10833
10834         if (HAS_POWER_WELL(dev))
10835                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10836
10837         for_each_pipe(i) {
10838                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10839                         error->cursor[i].control = I915_READ(CURCNTR(i));
10840                         error->cursor[i].position = I915_READ(CURPOS(i));
10841                         error->cursor[i].base = I915_READ(CURBASE(i));
10842                 } else {
10843                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10844                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10845                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10846                 }
10847
10848                 error->plane[i].control = I915_READ(DSPCNTR(i));
10849                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10850                 if (INTEL_INFO(dev)->gen <= 3) {
10851                         error->plane[i].size = I915_READ(DSPSIZE(i));
10852                         error->plane[i].pos = I915_READ(DSPPOS(i));
10853                 }
10854                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10855                         error->plane[i].addr = I915_READ(DSPADDR(i));
10856                 if (INTEL_INFO(dev)->gen >= 4) {
10857                         error->plane[i].surface = I915_READ(DSPSURF(i));
10858                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10859                 }
10860
10861                 error->pipe[i].source = I915_READ(PIPESRC(i));
10862         }
10863
10864         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10865         if (HAS_DDI(dev_priv->dev))
10866                 error->num_transcoders++; /* Account for eDP. */
10867
10868         for (i = 0; i < error->num_transcoders; i++) {
10869                 enum transcoder cpu_transcoder = transcoders[i];
10870
10871                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10872
10873                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10874                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10875                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10876                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10877                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10878                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10879                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10880         }
10881
10882         /* In the code above we read the registers without checking if the power
10883          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10884          * prevent the next I915_WRITE from detecting it and printing an error
10885          * message. */
10886         intel_uncore_clear_errors(dev);
10887
10888         return error;
10889 }
10890
10891 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10892
10893 void
10894 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10895                                 struct drm_device *dev,
10896                                 struct intel_display_error_state *error)
10897 {
10898         int i;
10899
10900         if (!error)
10901                 return;
10902
10903         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10904         if (HAS_POWER_WELL(dev))
10905                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10906                            error->power_well_driver);
10907         for_each_pipe(i) {
10908                 err_printf(m, "Pipe [%d]:\n", i);
10909                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10910
10911                 err_printf(m, "Plane [%d]:\n", i);
10912                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10913                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10914                 if (INTEL_INFO(dev)->gen <= 3) {
10915                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10916                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10917                 }
10918                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10919                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10920                 if (INTEL_INFO(dev)->gen >= 4) {
10921                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10922                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10923                 }
10924
10925                 err_printf(m, "Cursor [%d]:\n", i);
10926                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10927                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10928                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10929         }
10930
10931         for (i = 0; i < error->num_transcoders; i++) {
10932                 err_printf(m, "  CPU transcoder: %c\n",
10933                            transcoder_name(error->transcoder[i].cpu_transcoder));
10934                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
10935                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
10936                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
10937                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
10938                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
10939                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
10940                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
10941         }
10942 }