drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62         /**
  63          * find_pll() - Find the best values for the PLL
  64          * @limit: limits for the PLL
  65          * @crtc: current CRTC
  66          * @target: target frequency in kHz
  67          * @refclk: reference clock frequency in kHz
  68          * @match_clock: if provided, @best_clock P divider must
  69          *               match the P divider from @match_clock
  70          *               used for LVDS downclocking
  71          * @best_clock: best PLL values found
  72          *
  73          * Returns true on success, false on failure.
  74          */
  75         bool (*find_pll)(const intel_limit_t *limit,
  76                          struct drm_crtc *crtc,
  77                          int target, int refclk,
  78                          intel_clock_t *match_clock,
  79                          intel_clock_t *best_clock);
  80 };
  81
  82 /* FDI */
  83 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  84
  85 int
  86 intel_pch_rawclk(struct drm_device *dev)
  87 {
  88         struct drm_i915_private *dev_priv = dev->dev_private;
  89
  90         WARN_ON(!HAS_PCH_SPLIT(dev));
  91
  92         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  93 }
  94
  95 static bool
  96 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  97                     int target, int refclk, intel_clock_t *match_clock,
  98                     intel_clock_t *best_clock);
  99 static bool
 100 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 101                         int target, int refclk, intel_clock_t *match_clock,
 102                         intel_clock_t *best_clock);
 103
 104 static bool
 105 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 106                         int target, int refclk, intel_clock_t *match_clock,
 107                         intel_clock_t *best_clock);
 108
 109 static inline u32 /* units of 100MHz */
 110 intel_fdi_link_freq(struct drm_device *dev)
 111 {
 112         if (IS_GEN5(dev)) {
 113                 struct drm_i915_private *dev_priv = dev->dev_private;
 114                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 115         } else
 116                 return 27;
 117 }
 118
 119 static const intel_limit_t intel_limits_i8xx_dvo = {
 120         .dot = { .min = 25000, .max = 350000 },
 121         .vco = { .min = 930000, .max = 1400000 },
 122         .n = { .min = 3, .max = 16 },
 123         .m = { .min = 96, .max = 140 },
 124         .m1 = { .min = 18, .max = 26 },
 125         .m2 = { .min = 6, .max = 16 },
 126         .p = { .min = 4, .max = 128 },
 127         .p1 = { .min = 2, .max = 33 },
 128         .p2 = { .dot_limit = 165000,
 129                 .p2_slow = 4, .p2_fast = 2 },
 130         .find_pll = intel_find_best_PLL,
 131 };
 132
 133 static const intel_limit_t intel_limits_i8xx_lvds = {
 134         .dot = { .min = 25000, .max = 350000 },
 135         .vco = { .min = 930000, .max = 1400000 },
 136         .n = { .min = 3, .max = 16 },
 137         .m = { .min = 96, .max = 140 },
 138         .m1 = { .min = 18, .max = 26 },
 139         .m2 = { .min = 6, .max = 16 },
 140         .p = { .min = 4, .max = 128 },
 141         .p1 = { .min = 1, .max = 6 },
 142         .p2 = { .dot_limit = 165000,
 143                 .p2_slow = 14, .p2_fast = 7 },
 144         .find_pll = intel_find_best_PLL,
 145 };
 146
 147 static const intel_limit_t intel_limits_i9xx_sdvo = {
 148         .dot = { .min = 20000, .max = 400000 },
 149         .vco = { .min = 1400000, .max = 2800000 },
 150         .n = { .min = 1, .max = 6 },
 151         .m = { .min = 70, .max = 120 },
 152         .m1 = { .min = 8, .max = 18 },
 153         .m2 = { .min = 3, .max = 7 },
 154         .p = { .min = 5, .max = 80 },
 155         .p1 = { .min = 1, .max = 8 },
 156         .p2 = { .dot_limit = 200000,
 157                 .p2_slow = 10, .p2_fast = 5 },
 158         .find_pll = intel_find_best_PLL,
 159 };
 160
 161 static const intel_limit_t intel_limits_i9xx_lvds = {
 162         .dot = { .min = 20000, .max = 400000 },
 163         .vco = { .min = 1400000, .max = 2800000 },
 164         .n = { .min = 1, .max = 6 },
 165         .m = { .min = 70, .max = 120 },
 166         .m1 = { .min = 8, .max = 18 },
 167         .m2 = { .min = 3, .max = 7 },
 168         .p = { .min = 7, .max = 98 },
 169         .p1 = { .min = 1, .max = 8 },
 170         .p2 = { .dot_limit = 112000,
 171                 .p2_slow = 14, .p2_fast = 7 },
 172         .find_pll = intel_find_best_PLL,
 173 };
 174
 175
 176 static const intel_limit_t intel_limits_g4x_sdvo = {
 177         .dot = { .min = 25000, .max = 270000 },
 178         .vco = { .min = 1750000, .max = 3500000},
 179         .n = { .min = 1, .max = 4 },
 180         .m = { .min = 104, .max = 138 },
 181         .m1 = { .min = 17, .max = 23 },
 182         .m2 = { .min = 5, .max = 11 },
 183         .p = { .min = 10, .max = 30 },
 184         .p1 = { .min = 1, .max = 3},
 185         .p2 = { .dot_limit = 270000,
 186                 .p2_slow = 10,
 187                 .p2_fast = 10
 188         },
 189         .find_pll = intel_g4x_find_best_PLL,
 190 };
 191
 192 static const intel_limit_t intel_limits_g4x_hdmi = {
 193         .dot = { .min = 22000, .max = 400000 },
 194         .vco = { .min = 1750000, .max = 3500000},
 195         .n = { .min = 1, .max = 4 },
 196         .m = { .min = 104, .max = 138 },
 197         .m1 = { .min = 16, .max = 23 },
 198         .m2 = { .min = 5, .max = 11 },
 199         .p = { .min = 5, .max = 80 },
 200         .p1 = { .min = 1, .max = 8},
 201         .p2 = { .dot_limit = 165000,
 202                 .p2_slow = 10, .p2_fast = 5 },
 203         .find_pll = intel_g4x_find_best_PLL,
 204 };
 205
 206 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 207         .dot = { .min = 20000, .max = 115000 },
 208         .vco = { .min = 1750000, .max = 3500000 },
 209         .n = { .min = 1, .max = 3 },
 210         .m = { .min = 104, .max = 138 },
 211         .m1 = { .min = 17, .max = 23 },
 212         .m2 = { .min = 5, .max = 11 },
 213         .p = { .min = 28, .max = 112 },
 214         .p1 = { .min = 2, .max = 8 },
 215         .p2 = { .dot_limit = 0,
 216                 .p2_slow = 14, .p2_fast = 14
 217         },
 218         .find_pll = intel_g4x_find_best_PLL,
 219 };
 220
 221 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 222         .dot = { .min = 80000, .max = 224000 },
 223         .vco = { .min = 1750000, .max = 3500000 },
 224         .n = { .min = 1, .max = 3 },
 225         .m = { .min = 104, .max = 138 },
 226         .m1 = { .min = 17, .max = 23 },
 227         .m2 = { .min = 5, .max = 11 },
 228         .p = { .min = 14, .max = 42 },
 229         .p1 = { .min = 2, .max = 6 },
 230         .p2 = { .dot_limit = 0,
 231                 .p2_slow = 7, .p2_fast = 7
 232         },
 233         .find_pll = intel_g4x_find_best_PLL,
 234 };
 235
 236 static const intel_limit_t intel_limits_pineview_sdvo = {
 237         .dot = { .min = 20000, .max = 400000},
 238         .vco = { .min = 1700000, .max = 3500000 },
 239         /* Pineview's Ncounter is a ring counter */
 240         .n = { .min = 3, .max = 6 },
 241         .m = { .min = 2, .max = 256 },
 242         /* Pineview only has one combined m divider, which we treat as m2. */
 243         .m1 = { .min = 0, .max = 0 },
 244         .m2 = { .min = 0, .max = 254 },
 245         .p = { .min = 5, .max = 80 },
 246         .p1 = { .min = 1, .max = 8 },
 247         .p2 = { .dot_limit = 200000,
 248                 .p2_slow = 10, .p2_fast = 5 },
 249         .find_pll = intel_find_best_PLL,
 250 };
 251
 252 static const intel_limit_t intel_limits_pineview_lvds = {
 253         .dot = { .min = 20000, .max = 400000 },
 254         .vco = { .min = 1700000, .max = 3500000 },
 255         .n = { .min = 3, .max = 6 },
 256         .m = { .min = 2, .max = 256 },
 257         .m1 = { .min = 0, .max = 0 },
 258         .m2 = { .min = 0, .max = 254 },
 259         .p = { .min = 7, .max = 112 },
 260         .p1 = { .min = 1, .max = 8 },
 261         .p2 = { .dot_limit = 112000,
 262                 .p2_slow = 14, .p2_fast = 14 },
 263         .find_pll = intel_find_best_PLL,
 264 };
 265
 266 /* Ironlake / Sandybridge
 267  *
 268  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 269  * the range value for them is (actual_value - 2).
 270  */
 271 static const intel_limit_t intel_limits_ironlake_dac = {
 272         .dot = { .min = 25000, .max = 350000 },
 273         .vco = { .min = 1760000, .max = 3510000 },
 274         .n = { .min = 1, .max = 5 },
 275         .m = { .min = 79, .max = 127 },
 276         .m1 = { .min = 12, .max = 22 },
 277         .m2 = { .min = 5, .max = 9 },
 278         .p = { .min = 5, .max = 80 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 225000,
 281                 .p2_slow = 10, .p2_fast = 5 },
 282         .find_pll = intel_g4x_find_best_PLL,
 283 };
 284
 285 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 286         .dot = { .min = 25000, .max = 350000 },
 287         .vco = { .min = 1760000, .max = 3510000 },
 288         .n = { .min = 1, .max = 3 },
 289         .m = { .min = 79, .max = 118 },
 290         .m1 = { .min = 12, .max = 22 },
 291         .m2 = { .min = 5, .max = 9 },
 292         .p = { .min = 28, .max = 112 },
 293         .p1 = { .min = 2, .max = 8 },
 294         .p2 = { .dot_limit = 225000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296         .find_pll = intel_g4x_find_best_PLL,
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 127 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 56 },
 307         .p1 = { .min = 2, .max = 8 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310         .find_pll = intel_g4x_find_best_PLL,
 311 };
 312
 313 /* LVDS 100mhz refclk limits. */
 314 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 315         .dot = { .min = 25000, .max = 350000 },
 316         .vco = { .min = 1760000, .max = 3510000 },
 317         .n = { .min = 1, .max = 2 },
 318         .m = { .min = 79, .max = 126 },
 319         .m1 = { .min = 12, .max = 22 },
 320         .m2 = { .min = 5, .max = 9 },
 321         .p = { .min = 28, .max = 112 },
 322         .p1 = { .min = 2, .max = 8 },
 323         .p2 = { .dot_limit = 225000,
 324                 .p2_slow = 14, .p2_fast = 14 },
 325         .find_pll = intel_g4x_find_best_PLL,
 326 };
 327
 328 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 329         .dot = { .min = 25000, .max = 350000 },
 330         .vco = { .min = 1760000, .max = 3510000 },
 331         .n = { .min = 1, .max = 3 },
 332         .m = { .min = 79, .max = 126 },
 333         .m1 = { .min = 12, .max = 22 },
 334         .m2 = { .min = 5, .max = 9 },
 335         .p = { .min = 14, .max = 42 },
 336         .p1 = { .min = 2, .max = 6 },
 337         .p2 = { .dot_limit = 225000,
 338                 .p2_slow = 7, .p2_fast = 7 },
 339         .find_pll = intel_g4x_find_best_PLL,
 340 };
 341
 342 static const intel_limit_t intel_limits_vlv_dac = {
 343         .dot = { .min = 25000, .max = 270000 },
 344         .vco = { .min = 4000000, .max = 6000000 },
 345         .n = { .min = 1, .max = 7 },
 346         .m = { .min = 22, .max = 450 }, /* guess */
 347         .m1 = { .min = 2, .max = 3 },
 348         .m2 = { .min = 11, .max = 156 },
 349         .p = { .min = 10, .max = 30 },
 350         .p1 = { .min = 1, .max = 3 },
 351         .p2 = { .dot_limit = 270000,
 352                 .p2_slow = 2, .p2_fast = 20 },
 353         .find_pll = intel_vlv_find_best_pll,
 354 };
 355
 356 static const intel_limit_t intel_limits_vlv_hdmi = {
 357         .dot = { .min = 25000, .max = 270000 },
 358         .vco = { .min = 4000000, .max = 6000000 },
 359         .n = { .min = 1, .max = 7 },
 360         .m = { .min = 60, .max = 300 }, /* guess */
 361         .m1 = { .min = 2, .max = 3 },
 362         .m2 = { .min = 11, .max = 156 },
 363         .p = { .min = 10, .max = 30 },
 364         .p1 = { .min = 2, .max = 3 },
 365         .p2 = { .dot_limit = 270000,
 366                 .p2_slow = 2, .p2_fast = 20 },
 367         .find_pll = intel_vlv_find_best_pll,
 368 };
 369
 370 static const intel_limit_t intel_limits_vlv_dp = {
 371         .dot = { .min = 25000, .max = 270000 },
 372         .vco = { .min = 4000000, .max = 6000000 },
 373         .n = { .min = 1, .max = 7 },
 374         .m = { .min = 22, .max = 450 },
 375         .m1 = { .min = 2, .max = 3 },
 376         .m2 = { .min = 11, .max = 156 },
 377         .p = { .min = 10, .max = 30 },
 378         .p1 = { .min = 1, .max = 3 },
 379         .p2 = { .dot_limit = 270000,
 380                 .p2_slow = 2, .p2_fast = 20 },
 381         .find_pll = intel_vlv_find_best_pll,
 382 };
 383
 384 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 385 {
 386         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 387
 388         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 389                 DRM_ERROR("DPIO idle wait timed out\n");
 390                 return 0;
 391         }
 392
 393         I915_WRITE(DPIO_REG, reg);
 394         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 395                    DPIO_BYTE);
 396         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 397                 DRM_ERROR("DPIO read wait timed out\n");
 398                 return 0;
 399         }
 400
 401         return I915_READ(DPIO_DATA);
 402 }
 403
 404 void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
 405 {
 406         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 407
 408         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 409                 DRM_ERROR("DPIO idle wait timed out\n");
 410                 return;
 411         }
 412
 413         I915_WRITE(DPIO_DATA, val);
 414         I915_WRITE(DPIO_REG, reg);
 415         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 416                    DPIO_BYTE);
 417         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 418                 DRM_ERROR("DPIO write wait timed out\n");
 419 }
 420
 421 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 422                                                 int refclk)
 423 {
 424         struct drm_device *dev = crtc->dev;
 425         const intel_limit_t *limit;
 426
 427         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 428                 if (intel_is_dual_link_lvds(dev)) {
 429                         if (refclk == 100000)
 430                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 431                         else
 432                                 limit = &intel_limits_ironlake_dual_lvds;
 433                 } else {
 434                         if (refclk == 100000)
 435                                 limit = &intel_limits_ironlake_single_lvds_100m;
 436                         else
 437                                 limit = &intel_limits_ironlake_single_lvds;
 438                 }
 439         } else
 440                 limit = &intel_limits_ironlake_dac;
 441
 442         return limit;
 443 }
 444
 445 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 446 {
 447         struct drm_device *dev = crtc->dev;
 448         const intel_limit_t *limit;
 449
 450         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 451                 if (intel_is_dual_link_lvds(dev))
 452                         limit = &intel_limits_g4x_dual_channel_lvds;
 453                 else
 454                         limit = &intel_limits_g4x_single_channel_lvds;
 455         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 456                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 457                 limit = &intel_limits_g4x_hdmi;
 458         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 459                 limit = &intel_limits_g4x_sdvo;
 460         } else /* The option is for other outputs */
 461                 limit = &intel_limits_i9xx_sdvo;
 462
 463         return limit;
 464 }
 465
 466 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 467 {
 468         struct drm_device *dev = crtc->dev;
 469         const intel_limit_t *limit;
 470
 471         if (HAS_PCH_SPLIT(dev))
 472                 limit = intel_ironlake_limit(crtc, refclk);
 473         else if (IS_G4X(dev)) {
 474                 limit = intel_g4x_limit(crtc);
 475         } else if (IS_PINEVIEW(dev)) {
 476                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 477                         limit = &intel_limits_pineview_lvds;
 478                 else
 479                         limit = &intel_limits_pineview_sdvo;
 480         } else if (IS_VALLEYVIEW(dev)) {
 481                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 482                         limit = &intel_limits_vlv_dac;
 483                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 484                         limit = &intel_limits_vlv_hdmi;
 485                 else
 486                         limit = &intel_limits_vlv_dp;
 487         } else if (!IS_GEN2(dev)) {
 488                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 489                         limit = &intel_limits_i9xx_lvds;
 490                 else
 491                         limit = &intel_limits_i9xx_sdvo;
 492         } else {
 493                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 494                         limit = &intel_limits_i8xx_lvds;
 495                 else
 496                         limit = &intel_limits_i8xx_dvo;
 497         }
 498         return limit;
 499 }
 500
 501 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 502 static void pineview_clock(int refclk, intel_clock_t *clock)
 503 {
 504         clock->m = clock->m2 + 2;
 505         clock->p = clock->p1 * clock->p2;
 506         clock->vco = refclk * clock->m / clock->n;
 507         clock->dot = clock->vco / clock->p;
 508 }
 509
 510 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 511 {
 512         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 513 }
 514
 515 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 516 {
 517         if (IS_PINEVIEW(dev)) {
 518                 pineview_clock(refclk, clock);
 519                 return;
 520         }
 521         clock->m = i9xx_dpll_compute_m(clock);
 522         clock->p = clock->p1 * clock->p2;
 523         clock->vco = refclk * clock->m / (clock->n + 2);
 524         clock->dot = clock->vco / clock->p;
 525 }
 526
 527 /**
 528  * Returns whether any output on the specified pipe is of the specified type
 529  */
 530 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 531 {
 532         struct drm_device *dev = crtc->dev;
 533         struct intel_encoder *encoder;
 534
 535         for_each_encoder_on_crtc(dev, crtc, encoder)
 536                 if (encoder->type == type)
 537                         return true;
 538
 539         return false;
 540 }
 541
 542 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 543 /**
 544  * Returns whether the given set of divisors are valid for a given refclk with
 545  * the given connectors.
 546  */
 547
 548 static bool intel_PLL_is_valid(struct drm_device *dev,
 549                                const intel_limit_t *limit,
 550                                const intel_clock_t *clock)
 551 {
 552         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 553                 INTELPllInvalid("p1 out of range\n");
 554         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 555                 INTELPllInvalid("p out of range\n");
 556         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 557                 INTELPllInvalid("m2 out of range\n");
 558         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 559                 INTELPllInvalid("m1 out of range\n");
 560         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 561                 INTELPllInvalid("m1 <= m2\n");
 562         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 563                 INTELPllInvalid("m out of range\n");
 564         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 565                 INTELPllInvalid("n out of range\n");
 566         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 567                 INTELPllInvalid("vco out of range\n");
 568         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 569          * connector, etc., rather than just a single range.
 570          */
 571         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 572                 INTELPllInvalid("dot out of range\n");
 573
 574         return true;
 575 }
 576
 577 static bool
 578 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 579                     int target, int refclk, intel_clock_t *match_clock,
 580                     intel_clock_t *best_clock)
 581
 582 {
 583         struct drm_device *dev = crtc->dev;
 584         intel_clock_t clock;
 585         int err = target;
 586
 587         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 588                 /*
 589                  * For LVDS just rely on its current settings for dual-channel.
 590                  * We haven't figured out how to reliably set up different
 591                  * single/dual channel state, if we even can.
 592                  */
 593                 if (intel_is_dual_link_lvds(dev))
 594                         clock.p2 = limit->p2.p2_fast;
 595                 else
 596                         clock.p2 = limit->p2.p2_slow;
 597         } else {
 598                 if (target < limit->p2.dot_limit)
 599                         clock.p2 = limit->p2.p2_slow;
 600                 else
 601                         clock.p2 = limit->p2.p2_fast;
 602         }
 603
 604         memset(best_clock, 0, sizeof(*best_clock));
 605
 606         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 607              clock.m1++) {
 608                 for (clock.m2 = limit->m2.min;
 609                      clock.m2 <= limit->m2.max; clock.m2++) {
 610                         /* m1 is always 0 in Pineview */
 611                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 612                                 break;
 613                         for (clock.n = limit->n.min;
 614                              clock.n <= limit->n.max; clock.n++) {
 615                                 for (clock.p1 = limit->p1.min;
 616                                         clock.p1 <= limit->p1.max; clock.p1++) {
 617                                         int this_err;
 618
 619                                         intel_clock(dev, refclk, &clock);
 620                                         if (!intel_PLL_is_valid(dev, limit,
 621                                                                 &clock))
 622                                                 continue;
 623                                         if (match_clock &&
 624                                             clock.p != match_clock->p)
 625                                                 continue;
 626
 627                                         this_err = abs(clock.dot - target);
 628                                         if (this_err < err) {
 629                                                 *best_clock = clock;
 630                                                 err = this_err;
 631                                         }
 632                                 }
 633                         }
 634                 }
 635         }
 636
 637         return (err != target);
 638 }
 639
 640 static bool
 641 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 642                         int target, int refclk, intel_clock_t *match_clock,
 643                         intel_clock_t *best_clock)
 644 {
 645         struct drm_device *dev = crtc->dev;
 646         intel_clock_t clock;
 647         int max_n;
 648         bool found;
 649         /* approximately equals target * 0.00585 */
 650         int err_most = (target >> 8) + (target >> 9);
 651         found = false;
 652
 653         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 654                 int lvds_reg;
 655
 656                 if (HAS_PCH_SPLIT(dev))
 657                         lvds_reg = PCH_LVDS;
 658                 else
 659                         lvds_reg = LVDS;
 660                 if (intel_is_dual_link_lvds(dev))
 661                         clock.p2 = limit->p2.p2_fast;
 662                 else
 663                         clock.p2 = limit->p2.p2_slow;
 664         } else {
 665                 if (target < limit->p2.dot_limit)
 666                         clock.p2 = limit->p2.p2_slow;
 667                 else
 668                         clock.p2 = limit->p2.p2_fast;
 669         }
 670
 671         memset(best_clock, 0, sizeof(*best_clock));
 672         max_n = limit->n.max;
 673         /* based on hardware requirement, prefer smaller n to precision */
 674         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 675                 /* based on hardware requirement, prefere larger m1,m2 */
 676                 for (clock.m1 = limit->m1.max;
 677                      clock.m1 >= limit->m1.min; clock.m1--) {
 678                         for (clock.m2 = limit->m2.max;
 679                              clock.m2 >= limit->m2.min; clock.m2--) {
 680                                 for (clock.p1 = limit->p1.max;
 681                                      clock.p1 >= limit->p1.min; clock.p1--) {
 682                                         int this_err;
 683
 684                                         intel_clock(dev, refclk, &clock);
 685                                         if (!intel_PLL_is_valid(dev, limit,
 686                                                                 &clock))
 687                                                 continue;
 688
 689                                         this_err = abs(clock.dot - target);
 690                                         if (this_err < err_most) {
 691                                                 *best_clock = clock;
 692                                                 err_most = this_err;
 693                                                 max_n = clock.n;
 694                                                 found = true;
 695                                         }
 696                                 }
 697                         }
 698                 }
 699         }
 700         return found;
 701 }
 702
 703 static bool
 704 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 705                         int target, int refclk, intel_clock_t *match_clock,
 706                         intel_clock_t *best_clock)
 707 {
 708         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 709         u32 m, n, fastclk;
 710         u32 updrate, minupdate, fracbits, p;
 711         unsigned long bestppm, ppm, absppm;
 712         int dotclk, flag;
 713
 714         flag = 0;
 715         dotclk = target * 1000;
 716         bestppm = 1000000;
 717         ppm = absppm = 0;
 718         fastclk = dotclk / (2*100);
 719         updrate = 0;
 720         minupdate = 19200;
 721         fracbits = 1;
 722         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 723         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 724
 725         /* based on hardware requirement, prefer smaller n to precision */
 726         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 727                 updrate = refclk / n;
 728                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 729                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 730                                 if (p2 > 10)
 731                                         p2 = p2 - 1;
 732                                 p = p1 * p2;
 733                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 734                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 735                                         m2 = (((2*(fastclk * p * n / m1 )) +
 736                                                refclk) / (2*refclk));
 737                                         m = m1 * m2;
 738                                         vco = updrate * m;
 739                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 740                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 741                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 742                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 743                                                         bestppm = 0;
 744                                                         flag = 1;
 745                                                 }
 746                                                 if (absppm < bestppm - 10) {
 747                                                         bestppm = absppm;
 748                                                         flag = 1;
 749                                                 }
 750                                                 if (flag) {
 751                                                         bestn = n;
 752                                                         bestm1 = m1;
 753                                                         bestm2 = m2;
 754                                                         bestp1 = p1;
 755                                                         bestp2 = p2;
 756                                                         flag = 0;
 757                                                 }
 758                                         }
 759                                 }
 760                         }
 761                 }
 762         }
 763         best_clock->n = bestn;
 764         best_clock->m1 = bestm1;
 765         best_clock->m2 = bestm2;
 766         best_clock->p1 = bestp1;
 767         best_clock->p2 = bestp2;
 768
 769         return true;
 770 }
 771
 772 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 773                                              enum pipe pipe)
 774 {
 775         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 777
 778         return intel_crtc->config.cpu_transcoder;
 779 }
 780
 781 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 782 {
 783         struct drm_i915_private *dev_priv = dev->dev_private;
 784         u32 frame, frame_reg = PIPEFRAME(pipe);
 785
 786         frame = I915_READ(frame_reg);
 787
 788         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 789                 DRM_DEBUG_KMS("vblank wait timed out\n");
 790 }
 791
 792 /**
 793  * intel_wait_for_vblank - wait for vblank on a given pipe
 794  * @dev: drm device
 795  * @pipe: pipe to wait for
 796  *
 797  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 798  * mode setting code.
 799  */
 800 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 801 {
 802         struct drm_i915_private *dev_priv = dev->dev_private;
 803         int pipestat_reg = PIPESTAT(pipe);
 804
 805         if (INTEL_INFO(dev)->gen >= 5) {
 806                 ironlake_wait_for_vblank(dev, pipe);
 807                 return;
 808         }
 809
 810         /* Clear existing vblank status. Note this will clear any other
 811          * sticky status fields as well.
 812          *
 813          * This races with i915_driver_irq_handler() with the result
 814          * that either function could miss a vblank event.  Here it is not
 815          * fatal, as we will either wait upon the next vblank interrupt or
 816          * timeout.  Generally speaking intel_wait_for_vblank() is only
 817          * called during modeset at which time the GPU should be idle and
 818          * should *not* be performing page flips and thus not waiting on
 819          * vblanks...
 820          * Currently, the result of us stealing a vblank from the irq
 821          * handler is that a single frame will be skipped during swapbuffers.
 822          */
 823         I915_WRITE(pipestat_reg,
 824                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 825
 826         /* Wait for vblank interrupt bit to set */
 827         if (wait_for(I915_READ(pipestat_reg) &
 828                      PIPE_VBLANK_INTERRUPT_STATUS,
 829                      50))
 830                 DRM_DEBUG_KMS("vblank wait timed out\n");
 831 }
 832
 833 /*
 834  * intel_wait_for_pipe_off - wait for pipe to turn off
 835  * @dev: drm device
 836  * @pipe: pipe to wait for
 837  *
 838  * After disabling a pipe, we can't wait for vblank in the usual way,
 839  * spinning on the vblank interrupt status bit, since we won't actually
 840  * see an interrupt when the pipe is disabled.
 841  *
 842  * On Gen4 and above:
 843  *   wait for the pipe register state bit to turn off
 844  *
 845  * Otherwise:
 846  *   wait for the display line value to settle (it usually
 847  *   ends up stopping at the start of the next frame).
 848  *
 849  */
 850 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 851 {
 852         struct drm_i915_private *dev_priv = dev->dev_private;
 853         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 854                                                                       pipe);
 855
 856         if (INTEL_INFO(dev)->gen >= 4) {
 857                 int reg = PIPECONF(cpu_transcoder);
 858
 859                 /* Wait for the Pipe State to go off */
 860                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 861                              100))
 862                         WARN(1, "pipe_off wait timed out\n");
 863         } else {
 864                 u32 last_line, line_mask;
 865                 int reg = PIPEDSL(pipe);
 866                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 867
 868                 if (IS_GEN2(dev))
 869                         line_mask = DSL_LINEMASK_GEN2;
 870                 else
 871                         line_mask = DSL_LINEMASK_GEN3;
 872
 873                 /* Wait for the display line to settle */
 874                 do {
 875                         last_line = I915_READ(reg) & line_mask;
 876                         mdelay(5);
 877                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 878                          time_after(timeout, jiffies));
 879                 if (time_after(jiffies, timeout))
 880                         WARN(1, "pipe_off wait timed out\n");
 881         }
 882 }
 883
 884 /*
 885  * ibx_digital_port_connected - is the specified port connected?
 886  * @dev_priv: i915 private structure
 887  * @port: the port to test
 888  *
 889  * Returns true if @port is connected, false otherwise.
 890  */
 891 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 892                                 struct intel_digital_port *port)
 893 {
 894         u32 bit;
 895
 896         if (HAS_PCH_IBX(dev_priv->dev)) {
 897                 switch(port->port) {
 898                 case PORT_B:
 899                         bit = SDE_PORTB_HOTPLUG;
 900                         break;
 901                 case PORT_C:
 902                         bit = SDE_PORTC_HOTPLUG;
 903                         break;
 904                 case PORT_D:
 905                         bit = SDE_PORTD_HOTPLUG;
 906                         break;
 907                 default:
 908                         return true;
 909                 }
 910         } else {
 911                 switch(port->port) {
 912                 case PORT_B:
 913                         bit = SDE_PORTB_HOTPLUG_CPT;
 914                         break;
 915                 case PORT_C:
 916                         bit = SDE_PORTC_HOTPLUG_CPT;
 917                         break;
 918                 case PORT_D:
 919                         bit = SDE_PORTD_HOTPLUG_CPT;
 920                         break;
 921                 default:
 922                         return true;
 923                 }
 924         }
 925
 926         return I915_READ(SDEISR) & bit;
 927 }
 928
 929 static const char *state_string(bool enabled)
 930 {
 931         return enabled ? "on" : "off";
 932 }
 933
 934 /* Only for pre-ILK configs */
 935 static void assert_pll(struct drm_i915_private *dev_priv,
 936                        enum pipe pipe, bool state)
 937 {
 938         int reg;
 939         u32 val;
 940         bool cur_state;
 941
 942         reg = DPLL(pipe);
 943         val = I915_READ(reg);
 944         cur_state = !!(val & DPLL_VCO_ENABLE);
 945         WARN(cur_state != state,
 946              "PLL state assertion failure (expected %s, current %s)\n",
 947              state_string(state), state_string(cur_state));
 948 }
 949 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 950 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 951
 952 /* For ILK+ */
 953 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 954                            struct intel_pch_pll *pll,
 955                            struct intel_crtc *crtc,
 956                            bool state)
 957 {
 958         u32 val;
 959         bool cur_state;
 960
 961         if (HAS_PCH_LPT(dev_priv->dev)) {
 962                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 963                 return;
 964         }
 965
 966         if (WARN (!pll,
 967                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
 968                 return;
 969
 970         val = I915_READ(pll->pll_reg);
 971         cur_state = !!(val & DPLL_VCO_ENABLE);
 972         WARN(cur_state != state,
 973              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
 974              pll->pll_reg, state_string(state), state_string(cur_state), val);
 975
 976         /* Make sure the selected PLL is correctly attached to the transcoder */
 977         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
 978                 u32 pch_dpll;
 979
 980                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 981                 cur_state = pll->pll_reg == _PCH_DPLL_B;
 982                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
 983                           "PLL[%d] not attached to this transcoder %c: %08x\n",
 984                           cur_state, pipe_name(crtc->pipe), pch_dpll)) {
 985                         cur_state = !!(val >> (4*crtc->pipe + 3));
 986                         WARN(cur_state != state,
 987                              "PLL[%d] not %s on this transcoder %c: %08x\n",
 988                              pll->pll_reg == _PCH_DPLL_B,
 989                              state_string(state),
 990                              pipe_name(crtc->pipe),
 991                              val);
 992                 }
 993         }
 994 }
 995 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
 996 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
 997
 998 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 999                           enum pipe pipe, bool state)
1000 {
1001         int reg;
1002         u32 val;
1003         bool cur_state;
1004         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1005                                                                       pipe);
1006
1007         if (HAS_DDI(dev_priv->dev)) {
1008                 /* DDI does not have a specific FDI_TX register */
1009                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1010                 val = I915_READ(reg);
1011                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1012         } else {
1013                 reg = FDI_TX_CTL(pipe);
1014                 val = I915_READ(reg);
1015                 cur_state = !!(val & FDI_TX_ENABLE);
1016         }
1017         WARN(cur_state != state,
1018              "FDI TX state assertion failure (expected %s, current %s)\n",
1019              state_string(state), state_string(cur_state));
1020 }
1021 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1022 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1023
1024 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1025                           enum pipe pipe, bool state)
1026 {
1027         int reg;
1028         u32 val;
1029         bool cur_state;
1030
1031         reg = FDI_RX_CTL(pipe);
1032         val = I915_READ(reg);
1033         cur_state = !!(val & FDI_RX_ENABLE);
1034         WARN(cur_state != state,
1035              "FDI RX state assertion failure (expected %s, current %s)\n",
1036              state_string(state), state_string(cur_state));
1037 }
1038 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1039 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1040
1041 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1042                                       enum pipe pipe)
1043 {
1044         int reg;
1045         u32 val;
1046
1047         /* ILK FDI PLL is always enabled */
1048         if (dev_priv->info->gen == 5)
1049                 return;
1050
1051         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1052         if (HAS_DDI(dev_priv->dev))
1053                 return;
1054
1055         reg = FDI_TX_CTL(pipe);
1056         val = I915_READ(reg);
1057         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1058 }
1059
1060 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1061                                       enum pipe pipe)
1062 {
1063         int reg;
1064         u32 val;
1065
1066         reg = FDI_RX_CTL(pipe);
1067         val = I915_READ(reg);
1068         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1069 }
1070
1071 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1072                                   enum pipe pipe)
1073 {
1074         int pp_reg, lvds_reg;
1075         u32 val;
1076         enum pipe panel_pipe = PIPE_A;
1077         bool locked = true;
1078
1079         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080                 pp_reg = PCH_PP_CONTROL;
1081                 lvds_reg = PCH_LVDS;
1082         } else {
1083                 pp_reg = PP_CONTROL;
1084                 lvds_reg = LVDS;
1085         }
1086
1087         val = I915_READ(pp_reg);
1088         if (!(val & PANEL_POWER_ON) ||
1089             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1090                 locked = false;
1091
1092         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1093                 panel_pipe = PIPE_B;
1094
1095         WARN(panel_pipe == pipe && locked,
1096              "panel assertion failure, pipe %c regs locked\n",
1097              pipe_name(pipe));
1098 }
1099
1100 void assert_pipe(struct drm_i915_private *dev_priv,
1101                  enum pipe pipe, bool state)
1102 {
1103         int reg;
1104         u32 val;
1105         bool cur_state;
1106         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1107                                                                       pipe);
1108
1109         /* if we need the pipe A quirk it must be always on */
1110         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1111                 state = true;
1112
1113         if (!intel_display_power_enabled(dev_priv->dev,
1114                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1115                 cur_state = false;
1116         } else {
1117                 reg = PIPECONF(cpu_transcoder);
1118                 val = I915_READ(reg);
1119                 cur_state = !!(val & PIPECONF_ENABLE);
1120         }
1121
1122         WARN(cur_state != state,
1123              "pipe %c assertion failure (expected %s, current %s)\n",
1124              pipe_name(pipe), state_string(state), state_string(cur_state));
1125 }
1126
1127 static void assert_plane(struct drm_i915_private *dev_priv,
1128                          enum plane plane, bool state)
1129 {
1130         int reg;
1131         u32 val;
1132         bool cur_state;
1133
1134         reg = DSPCNTR(plane);
1135         val = I915_READ(reg);
1136         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1137         WARN(cur_state != state,
1138              "plane %c assertion failure (expected %s, current %s)\n",
1139              plane_name(plane), state_string(state), state_string(cur_state));
1140 }
1141
1142 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1143 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1144
1145 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1146                                    enum pipe pipe)
1147 {
1148         int reg, i;
1149         u32 val;
1150         int cur_pipe;
1151
1152         /* Planes are fixed to pipes on ILK+ */
1153         if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1154                 reg = DSPCNTR(pipe);
1155                 val = I915_READ(reg);
1156                 WARN((val & DISPLAY_PLANE_ENABLE),
1157                      "plane %c assertion failure, should be disabled but not\n",
1158                      plane_name(pipe));
1159                 return;
1160         }
1161
1162         /* Need to check both planes against the pipe */
1163         for (i = 0; i < 2; i++) {
1164                 reg = DSPCNTR(i);
1165                 val = I915_READ(reg);
1166                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1167                         DISPPLANE_SEL_PIPE_SHIFT;
1168                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1169                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1170                      plane_name(i), pipe_name(pipe));
1171         }
1172 }
1173
1174 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1175                                     enum pipe pipe)
1176 {
1177         int reg, i;
1178         u32 val;
1179
1180         if (!IS_VALLEYVIEW(dev_priv->dev))
1181                 return;
1182
1183         /* Need to check both planes against the pipe */
1184         for (i = 0; i < dev_priv->num_plane; i++) {
1185                 reg = SPCNTR(pipe, i);
1186                 val = I915_READ(reg);
1187                 WARN((val & SP_ENABLE),
1188                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1189                      sprite_name(pipe, i), pipe_name(pipe));
1190         }
1191 }
1192
1193 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1194 {
1195         u32 val;
1196         bool enabled;
1197
1198         if (HAS_PCH_LPT(dev_priv->dev)) {
1199                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1200                 return;
1201         }
1202
1203         val = I915_READ(PCH_DREF_CONTROL);
1204         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1205                             DREF_SUPERSPREAD_SOURCE_MASK));
1206         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1207 }
1208
1209 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1210                                            enum pipe pipe)
1211 {
1212         int reg;
1213         u32 val;
1214         bool enabled;
1215
1216         reg = PCH_TRANSCONF(pipe);
1217         val = I915_READ(reg);
1218         enabled = !!(val & TRANS_ENABLE);
1219         WARN(enabled,
1220              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1221              pipe_name(pipe));
1222 }
1223
1224 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1225                             enum pipe pipe, u32 port_sel, u32 val)
1226 {
1227         if ((val & DP_PORT_EN) == 0)
1228                 return false;
1229
1230         if (HAS_PCH_CPT(dev_priv->dev)) {
1231                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1232                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1233                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1234                         return false;
1235         } else {
1236                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1237                         return false;
1238         }
1239         return true;
1240 }
1241
1242 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1243                               enum pipe pipe, u32 val)
1244 {
1245         if ((val & SDVO_ENABLE) == 0)
1246                 return false;
1247
1248         if (HAS_PCH_CPT(dev_priv->dev)) {
1249                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1250                         return false;
1251         } else {
1252                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1253                         return false;
1254         }
1255         return true;
1256 }
1257
1258 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1259                               enum pipe pipe, u32 val)
1260 {
1261         if ((val & LVDS_PORT_EN) == 0)
1262                 return false;
1263
1264         if (HAS_PCH_CPT(dev_priv->dev)) {
1265                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1266                         return false;
1267         } else {
1268                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1269                         return false;
1270         }
1271         return true;
1272 }
1273
1274 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1275                               enum pipe pipe, u32 val)
1276 {
1277         if ((val & ADPA_DAC_ENABLE) == 0)
1278                 return false;
1279         if (HAS_PCH_CPT(dev_priv->dev)) {
1280                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281                         return false;
1282         } else {
1283                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1284                         return false;
1285         }
1286         return true;
1287 }
1288
1289 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1290                                    enum pipe pipe, int reg, u32 port_sel)
1291 {
1292         u32 val = I915_READ(reg);
1293         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1294              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1295              reg, pipe_name(pipe));
1296
1297         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1298              && (val & DP_PIPEB_SELECT),
1299              "IBX PCH dp port still using transcoder B\n");
1300 }
1301
1302 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1303                                      enum pipe pipe, int reg)
1304 {
1305         u32 val = I915_READ(reg);
1306         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1307              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1308              reg, pipe_name(pipe));
1309
1310         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1311              && (val & SDVO_PIPE_B_SELECT),
1312              "IBX PCH hdmi port still using transcoder B\n");
1313 }
1314
1315 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1316                                       enum pipe pipe)
1317 {
1318         int reg;
1319         u32 val;
1320
1321         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1322         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1323         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1324
1325         reg = PCH_ADPA;
1326         val = I915_READ(reg);
1327         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1328              "PCH VGA enabled on transcoder %c, should be disabled\n",
1329              pipe_name(pipe));
1330
1331         reg = PCH_LVDS;
1332         val = I915_READ(reg);
1333         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1334              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1335              pipe_name(pipe));
1336
1337         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1338         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1339         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1340 }
1341
1342 /**
1343  * intel_enable_pll - enable a PLL
1344  * @dev_priv: i915 private structure
1345  * @pipe: pipe PLL to enable
1346  *
1347  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1348  * make sure the PLL reg is writable first though, since the panel write
1349  * protect mechanism may be enabled.
1350  *
1351  * Note!  This is for pre-ILK only.
1352  *
1353  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1354  */
1355 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1356 {
1357         int reg;
1358         u32 val;
1359
1360         assert_pipe_disabled(dev_priv, pipe);
1361
1362         /* No really, not for ILK+ */
1363         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1364
1365         /* PLL is protected by panel, make sure we can write it */
1366         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1367                 assert_panel_unlocked(dev_priv, pipe);
1368
1369         reg = DPLL(pipe);
1370         val = I915_READ(reg);
1371         val |= DPLL_VCO_ENABLE;
1372
1373         /* We do this three times for luck */
1374         I915_WRITE(reg, val);
1375         POSTING_READ(reg);
1376         udelay(150); /* wait for warmup */
1377         I915_WRITE(reg, val);
1378         POSTING_READ(reg);
1379         udelay(150); /* wait for warmup */
1380         I915_WRITE(reg, val);
1381         POSTING_READ(reg);
1382         udelay(150); /* wait for warmup */
1383 }
1384
1385 /**
1386  * intel_disable_pll - disable a PLL
1387  * @dev_priv: i915 private structure
1388  * @pipe: pipe PLL to disable
1389  *
1390  * Disable the PLL for @pipe, making sure the pipe is off first.
1391  *
1392  * Note!  This is for pre-ILK only.
1393  */
1394 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395 {
1396         int reg;
1397         u32 val;
1398
1399         /* Don't disable pipe A or pipe A PLLs if needed */
1400         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401                 return;
1402
1403         /* Make sure the pipe isn't still relying on us */
1404         assert_pipe_disabled(dev_priv, pipe);
1405
1406         reg = DPLL(pipe);
1407         val = I915_READ(reg);
1408         val &= ~DPLL_VCO_ENABLE;
1409         I915_WRITE(reg, val);
1410         POSTING_READ(reg);
1411 }
1412
1413 /* SBI access */
1414 static void
1415 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1416                 enum intel_sbi_destination destination)
1417 {
1418         u32 tmp;
1419
1420         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1421
1422         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1423                                 100)) {
1424                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1425                 return;
1426         }
1427
1428         I915_WRITE(SBI_ADDR, (reg << 16));
1429         I915_WRITE(SBI_DATA, value);
1430
1431         if (destination == SBI_ICLK)
1432                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1433         else
1434                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1435         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1436
1437         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1438                                 100)) {
1439                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1440                 return;
1441         }
1442 }
1443
1444 static u32
1445 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1446                enum intel_sbi_destination destination)
1447 {
1448         u32 value = 0;
1449         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1450
1451         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1452                                 100)) {
1453                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1454                 return 0;
1455         }
1456
1457         I915_WRITE(SBI_ADDR, (reg << 16));
1458
1459         if (destination == SBI_ICLK)
1460                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1461         else
1462                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1463         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1464
1465         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1466                                 100)) {
1467                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1468                 return 0;
1469         }
1470
1471         return I915_READ(SBI_DATA);
1472 }
1473
1474 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1475 {
1476         u32 port_mask;
1477
1478         if (!port)
1479                 port_mask = DPLL_PORTB_READY_MASK;
1480         else
1481                 port_mask = DPLL_PORTC_READY_MASK;
1482
1483         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1484                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1485                      'B' + port, I915_READ(DPLL(0)));
1486 }
1487
1488 /**
1489  * ironlake_enable_pch_pll - enable PCH PLL
1490  * @dev_priv: i915 private structure
1491  * @pipe: pipe PLL to enable
1492  *
1493  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1494  * drives the transcoder clock.
1495  */
1496 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1497 {
1498         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1499         struct intel_pch_pll *pll;
1500         int reg;
1501         u32 val;
1502
1503         /* PCH PLLs only available on ILK, SNB and IVB */
1504         BUG_ON(dev_priv->info->gen < 5);
1505         pll = intel_crtc->pch_pll;
1506         if (pll == NULL)
1507                 return;
1508
1509         if (WARN_ON(pll->refcount == 0))
1510                 return;
1511
1512         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1513                       pll->pll_reg, pll->active, pll->on,
1514                       intel_crtc->base.base.id);
1515
1516         /* PCH refclock must be enabled first */
1517         assert_pch_refclk_enabled(dev_priv);
1518
1519         if (pll->active++ && pll->on) {
1520                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1521                 return;
1522         }
1523
1524         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1525
1526         reg = pll->pll_reg;
1527         val = I915_READ(reg);
1528         val |= DPLL_VCO_ENABLE;
1529         I915_WRITE(reg, val);
1530         POSTING_READ(reg);
1531         udelay(200);
1532
1533         pll->on = true;
1534 }
1535
1536 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1537 {
1538         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1539         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1540         int reg;
1541         u32 val;
1542
1543         /* PCH only available on ILK+ */
1544         BUG_ON(dev_priv->info->gen < 5);
1545         if (pll == NULL)
1546                return;
1547
1548         if (WARN_ON(pll->refcount == 0))
1549                 return;
1550
1551         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1552                       pll->pll_reg, pll->active, pll->on,
1553                       intel_crtc->base.base.id);
1554
1555         if (WARN_ON(pll->active == 0)) {
1556                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1557                 return;
1558         }
1559
1560         if (--pll->active) {
1561                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1562                 return;
1563         }
1564
1565         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1566
1567         /* Make sure transcoder isn't still depending on us */
1568         assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1569
1570         reg = pll->pll_reg;
1571         val = I915_READ(reg);
1572         val &= ~DPLL_VCO_ENABLE;
1573         I915_WRITE(reg, val);
1574         POSTING_READ(reg);
1575         udelay(200);
1576
1577         pll->on = false;
1578 }
1579
1580 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581                                            enum pipe pipe)
1582 {
1583         struct drm_device *dev = dev_priv->dev;
1584         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1585         uint32_t reg, val, pipeconf_val;
1586
1587         /* PCH only available on ILK+ */
1588         BUG_ON(dev_priv->info->gen < 5);
1589
1590         /* Make sure PCH DPLL is enabled */
1591         assert_pch_pll_enabled(dev_priv,
1592                                to_intel_crtc(crtc)->pch_pll,
1593                                to_intel_crtc(crtc));
1594
1595         /* FDI must be feeding us bits for PCH ports */
1596         assert_fdi_tx_enabled(dev_priv, pipe);
1597         assert_fdi_rx_enabled(dev_priv, pipe);
1598
1599         if (HAS_PCH_CPT(dev)) {
1600                 /* Workaround: Set the timing override bit before enabling the
1601                  * pch transcoder. */
1602                 reg = TRANS_CHICKEN2(pipe);
1603                 val = I915_READ(reg);
1604                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605                 I915_WRITE(reg, val);
1606         }
1607
1608         reg = PCH_TRANSCONF(pipe);
1609         val = I915_READ(reg);
1610         pipeconf_val = I915_READ(PIPECONF(pipe));
1611
1612         if (HAS_PCH_IBX(dev_priv->dev)) {
1613                 /*
1614                  * make the BPC in transcoder be consistent with
1615                  * that in pipeconf reg.
1616                  */
1617                 val &= ~PIPECONF_BPC_MASK;
1618                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1619         }
1620
1621         val &= ~TRANS_INTERLACE_MASK;
1622         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1623                 if (HAS_PCH_IBX(dev_priv->dev) &&
1624                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625                         val |= TRANS_LEGACY_INTERLACED_ILK;
1626                 else
1627                         val |= TRANS_INTERLACED;
1628         else
1629                 val |= TRANS_PROGRESSIVE;
1630
1631         I915_WRITE(reg, val | TRANS_ENABLE);
1632         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1633                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1634 }
1635
1636 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1637                                       enum transcoder cpu_transcoder)
1638 {
1639         u32 val, pipeconf_val;
1640
1641         /* PCH only available on ILK+ */
1642         BUG_ON(dev_priv->info->gen < 5);
1643
1644         /* FDI must be feeding us bits for PCH ports */
1645         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1646         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1647
1648         /* Workaround: set timing override bit. */
1649         val = I915_READ(_TRANSA_CHICKEN2);
1650         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1651         I915_WRITE(_TRANSA_CHICKEN2, val);
1652
1653         val = TRANS_ENABLE;
1654         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1655
1656         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657             PIPECONF_INTERLACED_ILK)
1658                 val |= TRANS_INTERLACED;
1659         else
1660                 val |= TRANS_PROGRESSIVE;
1661
1662         I915_WRITE(LPT_TRANSCONF, val);
1663         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1664                 DRM_ERROR("Failed to enable PCH transcoder\n");
1665 }
1666
1667 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668                                             enum pipe pipe)
1669 {
1670         struct drm_device *dev = dev_priv->dev;
1671         uint32_t reg, val;
1672
1673         /* FDI relies on the transcoder */
1674         assert_fdi_tx_disabled(dev_priv, pipe);
1675         assert_fdi_rx_disabled(dev_priv, pipe);
1676
1677         /* Ports must be off as well */
1678         assert_pch_ports_disabled(dev_priv, pipe);
1679
1680         reg = PCH_TRANSCONF(pipe);
1681         val = I915_READ(reg);
1682         val &= ~TRANS_ENABLE;
1683         I915_WRITE(reg, val);
1684         /* wait for PCH transcoder off, transcoder state */
1685         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1686                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1687
1688         if (!HAS_PCH_IBX(dev)) {
1689                 /* Workaround: Clear the timing override chicken bit again. */
1690                 reg = TRANS_CHICKEN2(pipe);
1691                 val = I915_READ(reg);
1692                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693                 I915_WRITE(reg, val);
1694         }
1695 }
1696
1697 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1698 {
1699         u32 val;
1700
1701         val = I915_READ(LPT_TRANSCONF);
1702         val &= ~TRANS_ENABLE;
1703         I915_WRITE(LPT_TRANSCONF, val);
1704         /* wait for PCH transcoder off, transcoder state */
1705         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1706                 DRM_ERROR("Failed to disable PCH transcoder\n");
1707
1708         /* Workaround: clear timing override bit. */
1709         val = I915_READ(_TRANSA_CHICKEN2);
1710         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1711         I915_WRITE(_TRANSA_CHICKEN2, val);
1712 }
1713
1714 /**
1715  * intel_enable_pipe - enable a pipe, asserting requirements
1716  * @dev_priv: i915 private structure
1717  * @pipe: pipe to enable
1718  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1719  *
1720  * Enable @pipe, making sure that various hardware specific requirements
1721  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722  *
1723  * @pipe should be %PIPE_A or %PIPE_B.
1724  *
1725  * Will wait until the pipe is actually running (i.e. first vblank) before
1726  * returning.
1727  */
1728 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729                               bool pch_port)
1730 {
1731         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732                                                                       pipe);
1733         enum pipe pch_transcoder;
1734         int reg;
1735         u32 val;
1736
1737         assert_planes_disabled(dev_priv, pipe);
1738         assert_sprites_disabled(dev_priv, pipe);
1739
1740         if (HAS_PCH_LPT(dev_priv->dev))
1741                 pch_transcoder = TRANSCODER_A;
1742         else
1743                 pch_transcoder = pipe;
1744
1745         /*
1746          * A pipe without a PLL won't actually be able to drive bits from
1747          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1748          * need the check.
1749          */
1750         if (!HAS_PCH_SPLIT(dev_priv->dev))
1751                 assert_pll_enabled(dev_priv, pipe);
1752         else {
1753                 if (pch_port) {
1754                         /* if driving the PCH, we need FDI enabled */
1755                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1756                         assert_fdi_tx_pll_enabled(dev_priv,
1757                                                   (enum pipe) cpu_transcoder);
1758                 }
1759                 /* FIXME: assert CPU port conditions for SNB+ */
1760         }
1761
1762         reg = PIPECONF(cpu_transcoder);
1763         val = I915_READ(reg);
1764         if (val & PIPECONF_ENABLE)
1765                 return;
1766
1767         I915_WRITE(reg, val | PIPECONF_ENABLE);
1768         intel_wait_for_vblank(dev_priv->dev, pipe);
1769 }
1770
1771 /**
1772  * intel_disable_pipe - disable a pipe, asserting requirements
1773  * @dev_priv: i915 private structure
1774  * @pipe: pipe to disable
1775  *
1776  * Disable @pipe, making sure that various hardware specific requirements
1777  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1778  *
1779  * @pipe should be %PIPE_A or %PIPE_B.
1780  *
1781  * Will wait until the pipe has shut down before returning.
1782  */
1783 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1784                                enum pipe pipe)
1785 {
1786         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1787                                                                       pipe);
1788         int reg;
1789         u32 val;
1790
1791         /*
1792          * Make sure planes won't keep trying to pump pixels to us,
1793          * or we might hang the display.
1794          */
1795         assert_planes_disabled(dev_priv, pipe);
1796         assert_sprites_disabled(dev_priv, pipe);
1797
1798         /* Don't disable pipe A or pipe A PLLs if needed */
1799         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1800                 return;
1801
1802         reg = PIPECONF(cpu_transcoder);
1803         val = I915_READ(reg);
1804         if ((val & PIPECONF_ENABLE) == 0)
1805                 return;
1806
1807         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1808         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1809 }
1810
1811 /*
1812  * Plane regs are double buffered, going from enabled->disabled needs a
1813  * trigger in order to latch.  The display address reg provides this.
1814  */
1815 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1816                                       enum plane plane)
1817 {
1818         if (dev_priv->info->gen >= 4)
1819                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1820         else
1821                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1822 }
1823
1824 /**
1825  * intel_enable_plane - enable a display plane on a given pipe
1826  * @dev_priv: i915 private structure
1827  * @plane: plane to enable
1828  * @pipe: pipe being fed
1829  *
1830  * Enable @plane on @pipe, making sure that @pipe is running first.
1831  */
1832 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833                                enum plane plane, enum pipe pipe)
1834 {
1835         int reg;
1836         u32 val;
1837
1838         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839         assert_pipe_enabled(dev_priv, pipe);
1840
1841         reg = DSPCNTR(plane);
1842         val = I915_READ(reg);
1843         if (val & DISPLAY_PLANE_ENABLE)
1844                 return;
1845
1846         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1847         intel_flush_display_plane(dev_priv, plane);
1848         intel_wait_for_vblank(dev_priv->dev, pipe);
1849 }
1850
1851 /**
1852  * intel_disable_plane - disable a display plane
1853  * @dev_priv: i915 private structure
1854  * @plane: plane to disable
1855  * @pipe: pipe consuming the data
1856  *
1857  * Disable @plane; should be an independent operation.
1858  */
1859 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860                                 enum plane plane, enum pipe pipe)
1861 {
1862         int reg;
1863         u32 val;
1864
1865         reg = DSPCNTR(plane);
1866         val = I915_READ(reg);
1867         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1868                 return;
1869
1870         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1871         intel_flush_display_plane(dev_priv, plane);
1872         intel_wait_for_vblank(dev_priv->dev, pipe);
1873 }
1874
1875 static bool need_vtd_wa(struct drm_device *dev)
1876 {
1877 #ifdef CONFIG_INTEL_IOMMU
1878         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1879                 return true;
1880 #endif
1881         return false;
1882 }
1883
1884 int
1885 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1886                            struct drm_i915_gem_object *obj,
1887                            struct intel_ring_buffer *pipelined)
1888 {
1889         struct drm_i915_private *dev_priv = dev->dev_private;
1890         u32 alignment;
1891         int ret;
1892
1893         switch (obj->tiling_mode) {
1894         case I915_TILING_NONE:
1895                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1896                         alignment = 128 * 1024;
1897                 else if (INTEL_INFO(dev)->gen >= 4)
1898                         alignment = 4 * 1024;
1899                 else
1900                         alignment = 64 * 1024;
1901                 break;
1902         case I915_TILING_X:
1903                 /* pin() will align the object as required by fence */
1904                 alignment = 0;
1905                 break;
1906         case I915_TILING_Y:
1907                 /* Despite that we check this in framebuffer_init userspace can
1908                  * screw us over and change the tiling after the fact. Only
1909                  * pinned buffers can't change their tiling. */
1910                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1911                 return -EINVAL;
1912         default:
1913                 BUG();
1914         }
1915
1916         /* Note that the w/a also requires 64 PTE of padding following the
1917          * bo. We currently fill all unused PTE with the shadow page and so
1918          * we should always have valid PTE following the scanout preventing
1919          * the VT-d warning.
1920          */
1921         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1922                 alignment = 256 * 1024;
1923
1924         dev_priv->mm.interruptible = false;
1925         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1926         if (ret)
1927                 goto err_interruptible;
1928
1929         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930          * fence, whereas 965+ only requires a fence if using
1931          * framebuffer compression.  For simplicity, we always install
1932          * a fence as the cost is not that onerous.
1933          */
1934         ret = i915_gem_object_get_fence(obj);
1935         if (ret)
1936                 goto err_unpin;
1937
1938         i915_gem_object_pin_fence(obj);
1939
1940         dev_priv->mm.interruptible = true;
1941         return 0;
1942
1943 err_unpin:
1944         i915_gem_object_unpin(obj);
1945 err_interruptible:
1946         dev_priv->mm.interruptible = true;
1947         return ret;
1948 }
1949
1950 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951 {
1952         i915_gem_object_unpin_fence(obj);
1953         i915_gem_object_unpin(obj);
1954 }
1955
1956 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957  * is assumed to be a power-of-two. */
1958 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1959                                              unsigned int tiling_mode,
1960                                              unsigned int cpp,
1961                                              unsigned int pitch)
1962 {
1963         if (tiling_mode != I915_TILING_NONE) {
1964                 unsigned int tile_rows, tiles;
1965
1966                 tile_rows = *y / 8;
1967                 *y %= 8;
1968
1969                 tiles = *x / (512/cpp);
1970                 *x %= 512/cpp;
1971
1972                 return tile_rows * pitch * 8 + tiles * 4096;
1973         } else {
1974                 unsigned int offset;
1975
1976                 offset = *y * pitch + *x * cpp;
1977                 *y = 0;
1978                 *x = (offset & 4095) / cpp;
1979                 return offset & -4096;
1980         }
1981 }
1982
1983 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1984                              int x, int y)
1985 {
1986         struct drm_device *dev = crtc->dev;
1987         struct drm_i915_private *dev_priv = dev->dev_private;
1988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1989         struct intel_framebuffer *intel_fb;
1990         struct drm_i915_gem_object *obj;
1991         int plane = intel_crtc->plane;
1992         unsigned long linear_offset;
1993         u32 dspcntr;
1994         u32 reg;
1995
1996         switch (plane) {
1997         case 0:
1998         case 1:
1999                 break;
2000         default:
2001                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2002                 return -EINVAL;
2003         }
2004
2005         intel_fb = to_intel_framebuffer(fb);
2006         obj = intel_fb->obj;
2007
2008         reg = DSPCNTR(plane);
2009         dspcntr = I915_READ(reg);
2010         /* Mask out pixel format bits in case we change it */
2011         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2012         switch (fb->pixel_format) {
2013         case DRM_FORMAT_C8:
2014                 dspcntr |= DISPPLANE_8BPP;
2015                 break;
2016         case DRM_FORMAT_XRGB1555:
2017         case DRM_FORMAT_ARGB1555:
2018                 dspcntr |= DISPPLANE_BGRX555;
2019                 break;
2020         case DRM_FORMAT_RGB565:
2021                 dspcntr |= DISPPLANE_BGRX565;
2022                 break;
2023         case DRM_FORMAT_XRGB8888:
2024         case DRM_FORMAT_ARGB8888:
2025                 dspcntr |= DISPPLANE_BGRX888;
2026                 break;
2027         case DRM_FORMAT_XBGR8888:
2028         case DRM_FORMAT_ABGR8888:
2029                 dspcntr |= DISPPLANE_RGBX888;
2030                 break;
2031         case DRM_FORMAT_XRGB2101010:
2032         case DRM_FORMAT_ARGB2101010:
2033                 dspcntr |= DISPPLANE_BGRX101010;
2034                 break;
2035         case DRM_FORMAT_XBGR2101010:
2036         case DRM_FORMAT_ABGR2101010:
2037                 dspcntr |= DISPPLANE_RGBX101010;
2038                 break;
2039         default:
2040                 BUG();
2041         }
2042
2043         if (INTEL_INFO(dev)->gen >= 4) {
2044                 if (obj->tiling_mode != I915_TILING_NONE)
2045                         dspcntr |= DISPPLANE_TILED;
2046                 else
2047                         dspcntr &= ~DISPPLANE_TILED;
2048         }
2049
2050         I915_WRITE(reg, dspcntr);
2051
2052         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2053
2054         if (INTEL_INFO(dev)->gen >= 4) {
2055                 intel_crtc->dspaddr_offset =
2056                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2057                                                        fb->bits_per_pixel / 8,
2058                                                        fb->pitches[0]);
2059                 linear_offset -= intel_crtc->dspaddr_offset;
2060         } else {
2061                 intel_crtc->dspaddr_offset = linear_offset;
2062         }
2063
2064         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2066         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2067         if (INTEL_INFO(dev)->gen >= 4) {
2068                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2069                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2070                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2071                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2072         } else
2073                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2074         POSTING_READ(reg);
2075
2076         return 0;
2077 }
2078
2079 static int ironlake_update_plane(struct drm_crtc *crtc,
2080                                  struct drm_framebuffer *fb, int x, int y)
2081 {
2082         struct drm_device *dev = crtc->dev;
2083         struct drm_i915_private *dev_priv = dev->dev_private;
2084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085         struct intel_framebuffer *intel_fb;
2086         struct drm_i915_gem_object *obj;
2087         int plane = intel_crtc->plane;
2088         unsigned long linear_offset;
2089         u32 dspcntr;
2090         u32 reg;
2091
2092         switch (plane) {
2093         case 0:
2094         case 1:
2095         case 2:
2096                 break;
2097         default:
2098                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2099                 return -EINVAL;
2100         }
2101
2102         intel_fb = to_intel_framebuffer(fb);
2103         obj = intel_fb->obj;
2104
2105         reg = DSPCNTR(plane);
2106         dspcntr = I915_READ(reg);
2107         /* Mask out pixel format bits in case we change it */
2108         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2109         switch (fb->pixel_format) {
2110         case DRM_FORMAT_C8:
2111                 dspcntr |= DISPPLANE_8BPP;
2112                 break;
2113         case DRM_FORMAT_RGB565:
2114                 dspcntr |= DISPPLANE_BGRX565;
2115                 break;
2116         case DRM_FORMAT_XRGB8888:
2117         case DRM_FORMAT_ARGB8888:
2118                 dspcntr |= DISPPLANE_BGRX888;
2119                 break;
2120         case DRM_FORMAT_XBGR8888:
2121         case DRM_FORMAT_ABGR8888:
2122                 dspcntr |= DISPPLANE_RGBX888;
2123                 break;
2124         case DRM_FORMAT_XRGB2101010:
2125         case DRM_FORMAT_ARGB2101010:
2126                 dspcntr |= DISPPLANE_BGRX101010;
2127                 break;
2128         case DRM_FORMAT_XBGR2101010:
2129         case DRM_FORMAT_ABGR2101010:
2130                 dspcntr |= DISPPLANE_RGBX101010;
2131                 break;
2132         default:
2133                 BUG();
2134         }
2135
2136         if (obj->tiling_mode != I915_TILING_NONE)
2137                 dspcntr |= DISPPLANE_TILED;
2138         else
2139                 dspcntr &= ~DISPPLANE_TILED;
2140
2141         /* must disable */
2142         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2143
2144         I915_WRITE(reg, dspcntr);
2145
2146         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2147         intel_crtc->dspaddr_offset =
2148                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2149                                                fb->bits_per_pixel / 8,
2150                                                fb->pitches[0]);
2151         linear_offset -= intel_crtc->dspaddr_offset;
2152
2153         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2154                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2155         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2156         I915_MODIFY_DISPBASE(DSPSURF(plane),
2157                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2158         if (IS_HASWELL(dev)) {
2159                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2160         } else {
2161                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2162                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2163         }
2164         POSTING_READ(reg);
2165
2166         return 0;
2167 }
2168
2169 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2170 static int
2171 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2172                            int x, int y, enum mode_set_atomic state)
2173 {
2174         struct drm_device *dev = crtc->dev;
2175         struct drm_i915_private *dev_priv = dev->dev_private;
2176
2177         if (dev_priv->display.disable_fbc)
2178                 dev_priv->display.disable_fbc(dev);
2179         intel_increase_pllclock(crtc);
2180
2181         return dev_priv->display.update_plane(crtc, fb, x, y);
2182 }
2183
2184 void intel_display_handle_reset(struct drm_device *dev)
2185 {
2186         struct drm_i915_private *dev_priv = dev->dev_private;
2187         struct drm_crtc *crtc;
2188
2189         /*
2190          * Flips in the rings have been nuked by the reset,
2191          * so complete all pending flips so that user space
2192          * will get its events and not get stuck.
2193          *
2194          * Also update the base address of all primary
2195          * planes to the the last fb to make sure we're
2196          * showing the correct fb after a reset.
2197          *
2198          * Need to make two loops over the crtcs so that we
2199          * don't try to grab a crtc mutex before the
2200          * pending_flip_queue really got woken up.
2201          */
2202
2203         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2204                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2205                 enum plane plane = intel_crtc->plane;
2206
2207                 intel_prepare_page_flip(dev, plane);
2208                 intel_finish_page_flip_plane(dev, plane);
2209         }
2210
2211         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2212                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214                 mutex_lock(&crtc->mutex);
2215                 if (intel_crtc->active)
2216                         dev_priv->display.update_plane(crtc, crtc->fb,
2217                                                        crtc->x, crtc->y);
2218                 mutex_unlock(&crtc->mutex);
2219         }
2220 }
2221
2222 static int
2223 intel_finish_fb(struct drm_framebuffer *old_fb)
2224 {
2225         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2226         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2227         bool was_interruptible = dev_priv->mm.interruptible;
2228         int ret;
2229
2230         /* Big Hammer, we also need to ensure that any pending
2231          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2232          * current scanout is retired before unpinning the old
2233          * framebuffer.
2234          *
2235          * This should only fail upon a hung GPU, in which case we
2236          * can safely continue.
2237          */
2238         dev_priv->mm.interruptible = false;
2239         ret = i915_gem_object_finish_gpu(obj);
2240         dev_priv->mm.interruptible = was_interruptible;
2241
2242         return ret;
2243 }
2244
2245 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2246 {
2247         struct drm_device *dev = crtc->dev;
2248         struct drm_i915_master_private *master_priv;
2249         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250
2251         if (!dev->primary->master)
2252                 return;
2253
2254         master_priv = dev->primary->master->driver_priv;
2255         if (!master_priv->sarea_priv)
2256                 return;
2257
2258         switch (intel_crtc->pipe) {
2259         case 0:
2260                 master_priv->sarea_priv->pipeA_x = x;
2261                 master_priv->sarea_priv->pipeA_y = y;
2262                 break;
2263         case 1:
2264                 master_priv->sarea_priv->pipeB_x = x;
2265                 master_priv->sarea_priv->pipeB_y = y;
2266                 break;
2267         default:
2268                 break;
2269         }
2270 }
2271
2272 static int
2273 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2274                     struct drm_framebuffer *fb)
2275 {
2276         struct drm_device *dev = crtc->dev;
2277         struct drm_i915_private *dev_priv = dev->dev_private;
2278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2279         struct drm_framebuffer *old_fb;
2280         int ret;
2281
2282         /* no fb bound */
2283         if (!fb) {
2284                 DRM_ERROR("No FB bound\n");
2285                 return 0;
2286         }
2287
2288         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2289                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2290                           plane_name(intel_crtc->plane),
2291                           INTEL_INFO(dev)->num_pipes);
2292                 return -EINVAL;
2293         }
2294
2295         mutex_lock(&dev->struct_mutex);
2296         ret = intel_pin_and_fence_fb_obj(dev,
2297                                          to_intel_framebuffer(fb)->obj,
2298                                          NULL);
2299         if (ret != 0) {
2300                 mutex_unlock(&dev->struct_mutex);
2301                 DRM_ERROR("pin & fence failed\n");
2302                 return ret;
2303         }
2304
2305         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2306         if (ret) {
2307                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2308                 mutex_unlock(&dev->struct_mutex);
2309                 DRM_ERROR("failed to update base address\n");
2310                 return ret;
2311         }
2312
2313         old_fb = crtc->fb;
2314         crtc->fb = fb;
2315         crtc->x = x;
2316         crtc->y = y;
2317
2318         if (old_fb) {
2319                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2320                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2321         }
2322
2323         intel_update_fbc(dev);
2324         mutex_unlock(&dev->struct_mutex);
2325
2326         intel_crtc_update_sarea_pos(crtc, x, y);
2327
2328         return 0;
2329 }
2330
2331 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332 {
2333         struct drm_device *dev = crtc->dev;
2334         struct drm_i915_private *dev_priv = dev->dev_private;
2335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336         int pipe = intel_crtc->pipe;
2337         u32 reg, temp;
2338
2339         /* enable normal train */
2340         reg = FDI_TX_CTL(pipe);
2341         temp = I915_READ(reg);
2342         if (IS_IVYBRIDGE(dev)) {
2343                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2345         } else {
2346                 temp &= ~FDI_LINK_TRAIN_NONE;
2347                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2348         }
2349         I915_WRITE(reg, temp);
2350
2351         reg = FDI_RX_CTL(pipe);
2352         temp = I915_READ(reg);
2353         if (HAS_PCH_CPT(dev)) {
2354                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356         } else {
2357                 temp &= ~FDI_LINK_TRAIN_NONE;
2358                 temp |= FDI_LINK_TRAIN_NONE;
2359         }
2360         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362         /* wait one idle pattern time */
2363         POSTING_READ(reg);
2364         udelay(1000);
2365
2366         /* IVB wants error correction enabled */
2367         if (IS_IVYBRIDGE(dev))
2368                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369                            FDI_FE_ERRC_ENABLE);
2370 }
2371
2372 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373 {
2374         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375 }
2376
2377 static void ivb_modeset_global_resources(struct drm_device *dev)
2378 {
2379         struct drm_i915_private *dev_priv = dev->dev_private;
2380         struct intel_crtc *pipe_B_crtc =
2381                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382         struct intel_crtc *pipe_C_crtc =
2383                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384         uint32_t temp;
2385
2386         /*
2387          * When everything is off disable fdi C so that we could enable fdi B
2388          * with all lanes. Note that we don't care about enabled pipes without
2389          * an enabled pch encoder.
2390          */
2391         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392             !pipe_has_enabled_pch(pipe_C_crtc)) {
2393                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396                 temp = I915_READ(SOUTH_CHICKEN1);
2397                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399                 I915_WRITE(SOUTH_CHICKEN1, temp);
2400         }
2401 }
2402
2403 /* The FDI link training functions for ILK/Ibexpeak. */
2404 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405 {
2406         struct drm_device *dev = crtc->dev;
2407         struct drm_i915_private *dev_priv = dev->dev_private;
2408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409         int pipe = intel_crtc->pipe;
2410         int plane = intel_crtc->plane;
2411         u32 reg, temp, tries;
2412
2413         /* FDI needs bits from pipe & plane first */
2414         assert_pipe_enabled(dev_priv, pipe);
2415         assert_plane_enabled(dev_priv, plane);
2416
2417         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418            for train result */
2419         reg = FDI_RX_IMR(pipe);
2420         temp = I915_READ(reg);
2421         temp &= ~FDI_RX_SYMBOL_LOCK;
2422         temp &= ~FDI_RX_BIT_LOCK;
2423         I915_WRITE(reg, temp);
2424         I915_READ(reg);
2425         udelay(150);
2426
2427         /* enable CPU FDI TX and PCH FDI RX */
2428         reg = FDI_TX_CTL(pipe);
2429         temp = I915_READ(reg);
2430         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2432         temp &= ~FDI_LINK_TRAIN_NONE;
2433         temp |= FDI_LINK_TRAIN_PATTERN_1;
2434         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2435
2436         reg = FDI_RX_CTL(pipe);
2437         temp = I915_READ(reg);
2438         temp &= ~FDI_LINK_TRAIN_NONE;
2439         temp |= FDI_LINK_TRAIN_PATTERN_1;
2440         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442         POSTING_READ(reg);
2443         udelay(150);
2444
2445         /* Ironlake workaround, enable clock pointer after FDI enable*/
2446         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448                    FDI_RX_PHASE_SYNC_POINTER_EN);
2449
2450         reg = FDI_RX_IIR(pipe);
2451         for (tries = 0; tries < 5; tries++) {
2452                 temp = I915_READ(reg);
2453                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455                 if ((temp & FDI_RX_BIT_LOCK)) {
2456                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2457                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2458                         break;
2459                 }
2460         }
2461         if (tries == 5)
2462                 DRM_ERROR("FDI train 1 fail!\n");
2463
2464         /* Train 2 */
2465         reg = FDI_TX_CTL(pipe);
2466         temp = I915_READ(reg);
2467         temp &= ~FDI_LINK_TRAIN_NONE;
2468         temp |= FDI_LINK_TRAIN_PATTERN_2;
2469         I915_WRITE(reg, temp);
2470
2471         reg = FDI_RX_CTL(pipe);
2472         temp = I915_READ(reg);
2473         temp &= ~FDI_LINK_TRAIN_NONE;
2474         temp |= FDI_LINK_TRAIN_PATTERN_2;
2475         I915_WRITE(reg, temp);
2476
2477         POSTING_READ(reg);
2478         udelay(150);
2479
2480         reg = FDI_RX_IIR(pipe);
2481         for (tries = 0; tries < 5; tries++) {
2482                 temp = I915_READ(reg);
2483                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485                 if (temp & FDI_RX_SYMBOL_LOCK) {
2486                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2487                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2488                         break;
2489                 }
2490         }
2491         if (tries == 5)
2492                 DRM_ERROR("FDI train 2 fail!\n");
2493
2494         DRM_DEBUG_KMS("FDI train done\n");
2495
2496 }
2497
2498 static const int snb_b_fdi_train_param[] = {
2499         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503 };
2504
2505 /* The FDI link training functions for SNB/Cougarpoint. */
2506 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507 {
2508         struct drm_device *dev = crtc->dev;
2509         struct drm_i915_private *dev_priv = dev->dev_private;
2510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511         int pipe = intel_crtc->pipe;
2512         u32 reg, temp, i, retry;
2513
2514         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515            for train result */
2516         reg = FDI_RX_IMR(pipe);
2517         temp = I915_READ(reg);
2518         temp &= ~FDI_RX_SYMBOL_LOCK;
2519         temp &= ~FDI_RX_BIT_LOCK;
2520         I915_WRITE(reg, temp);
2521
2522         POSTING_READ(reg);
2523         udelay(150);
2524
2525         /* enable CPU FDI TX and PCH FDI RX */
2526         reg = FDI_TX_CTL(pipe);
2527         temp = I915_READ(reg);
2528         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2530         temp &= ~FDI_LINK_TRAIN_NONE;
2531         temp |= FDI_LINK_TRAIN_PATTERN_1;
2532         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533         /* SNB-B */
2534         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2535         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2536
2537         I915_WRITE(FDI_RX_MISC(pipe),
2538                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
2540         reg = FDI_RX_CTL(pipe);
2541         temp = I915_READ(reg);
2542         if (HAS_PCH_CPT(dev)) {
2543                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545         } else {
2546                 temp &= ~FDI_LINK_TRAIN_NONE;
2547                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548         }
2549         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551         POSTING_READ(reg);
2552         udelay(150);
2553
2554         for (i = 0; i < 4; i++) {
2555                 reg = FDI_TX_CTL(pipe);
2556                 temp = I915_READ(reg);
2557                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558                 temp |= snb_b_fdi_train_param[i];
2559                 I915_WRITE(reg, temp);
2560
2561                 POSTING_READ(reg);
2562                 udelay(500);
2563
2564                 for (retry = 0; retry < 5; retry++) {
2565                         reg = FDI_RX_IIR(pipe);
2566                         temp = I915_READ(reg);
2567                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568                         if (temp & FDI_RX_BIT_LOCK) {
2569                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571                                 break;
2572                         }
2573                         udelay(50);
2574                 }
2575                 if (retry < 5)
2576                         break;
2577         }
2578         if (i == 4)
2579                 DRM_ERROR("FDI train 1 fail!\n");
2580
2581         /* Train 2 */
2582         reg = FDI_TX_CTL(pipe);
2583         temp = I915_READ(reg);
2584         temp &= ~FDI_LINK_TRAIN_NONE;
2585         temp |= FDI_LINK_TRAIN_PATTERN_2;
2586         if (IS_GEN6(dev)) {
2587                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588                 /* SNB-B */
2589                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590         }
2591         I915_WRITE(reg, temp);
2592
2593         reg = FDI_RX_CTL(pipe);
2594         temp = I915_READ(reg);
2595         if (HAS_PCH_CPT(dev)) {
2596                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598         } else {
2599                 temp &= ~FDI_LINK_TRAIN_NONE;
2600                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601         }
2602         I915_WRITE(reg, temp);
2603
2604         POSTING_READ(reg);
2605         udelay(150);
2606
2607         for (i = 0; i < 4; i++) {
2608                 reg = FDI_TX_CTL(pipe);
2609                 temp = I915_READ(reg);
2610                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611                 temp |= snb_b_fdi_train_param[i];
2612                 I915_WRITE(reg, temp);
2613
2614                 POSTING_READ(reg);
2615                 udelay(500);
2616
2617                 for (retry = 0; retry < 5; retry++) {
2618                         reg = FDI_RX_IIR(pipe);
2619                         temp = I915_READ(reg);
2620                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621                         if (temp & FDI_RX_SYMBOL_LOCK) {
2622                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624                                 break;
2625                         }
2626                         udelay(50);
2627                 }
2628                 if (retry < 5)
2629                         break;
2630         }
2631         if (i == 4)
2632                 DRM_ERROR("FDI train 2 fail!\n");
2633
2634         DRM_DEBUG_KMS("FDI train done.\n");
2635 }
2636
2637 /* Manual link training for Ivy Bridge A0 parts */
2638 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639 {
2640         struct drm_device *dev = crtc->dev;
2641         struct drm_i915_private *dev_priv = dev->dev_private;
2642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643         int pipe = intel_crtc->pipe;
2644         u32 reg, temp, i;
2645
2646         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647            for train result */
2648         reg = FDI_RX_IMR(pipe);
2649         temp = I915_READ(reg);
2650         temp &= ~FDI_RX_SYMBOL_LOCK;
2651         temp &= ~FDI_RX_BIT_LOCK;
2652         I915_WRITE(reg, temp);
2653
2654         POSTING_READ(reg);
2655         udelay(150);
2656
2657         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658                       I915_READ(FDI_RX_IIR(pipe)));
2659
2660         /* enable CPU FDI TX and PCH FDI RX */
2661         reg = FDI_TX_CTL(pipe);
2662         temp = I915_READ(reg);
2663         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2664         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2665         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2667         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2668         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2669         temp |= FDI_COMPOSITE_SYNC;
2670         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2671
2672         I915_WRITE(FDI_RX_MISC(pipe),
2673                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2674
2675         reg = FDI_RX_CTL(pipe);
2676         temp = I915_READ(reg);
2677         temp &= ~FDI_LINK_TRAIN_AUTO;
2678         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2679         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2680         temp |= FDI_COMPOSITE_SYNC;
2681         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2682
2683         POSTING_READ(reg);
2684         udelay(150);
2685
2686         for (i = 0; i < 4; i++) {
2687                 reg = FDI_TX_CTL(pipe);
2688                 temp = I915_READ(reg);
2689                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690                 temp |= snb_b_fdi_train_param[i];
2691                 I915_WRITE(reg, temp);
2692
2693                 POSTING_READ(reg);
2694                 udelay(500);
2695
2696                 reg = FDI_RX_IIR(pipe);
2697                 temp = I915_READ(reg);
2698                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700                 if (temp & FDI_RX_BIT_LOCK ||
2701                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2702                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2703                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2704                         break;
2705                 }
2706         }
2707         if (i == 4)
2708                 DRM_ERROR("FDI train 1 fail!\n");
2709
2710         /* Train 2 */
2711         reg = FDI_TX_CTL(pipe);
2712         temp = I915_READ(reg);
2713         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2714         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2715         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2716         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2717         I915_WRITE(reg, temp);
2718
2719         reg = FDI_RX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2722         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2723         I915_WRITE(reg, temp);
2724
2725         POSTING_READ(reg);
2726         udelay(150);
2727
2728         for (i = 0; i < 4; i++) {
2729                 reg = FDI_TX_CTL(pipe);
2730                 temp = I915_READ(reg);
2731                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732                 temp |= snb_b_fdi_train_param[i];
2733                 I915_WRITE(reg, temp);
2734
2735                 POSTING_READ(reg);
2736                 udelay(500);
2737
2738                 reg = FDI_RX_IIR(pipe);
2739                 temp = I915_READ(reg);
2740                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2741
2742                 if (temp & FDI_RX_SYMBOL_LOCK) {
2743                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2744                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2745                         break;
2746                 }
2747         }
2748         if (i == 4)
2749                 DRM_ERROR("FDI train 2 fail!\n");
2750
2751         DRM_DEBUG_KMS("FDI train done.\n");
2752 }
2753
2754 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2755 {
2756         struct drm_device *dev = intel_crtc->base.dev;
2757         struct drm_i915_private *dev_priv = dev->dev_private;
2758         int pipe = intel_crtc->pipe;
2759         u32 reg, temp;
2760
2761
2762         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2763         reg = FDI_RX_CTL(pipe);
2764         temp = I915_READ(reg);
2765         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2766         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2767         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2768         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2769
2770         POSTING_READ(reg);
2771         udelay(200);
2772
2773         /* Switch from Rawclk to PCDclk */
2774         temp = I915_READ(reg);
2775         I915_WRITE(reg, temp | FDI_PCDCLK);
2776
2777         POSTING_READ(reg);
2778         udelay(200);
2779
2780         /* Enable CPU FDI TX PLL, always on for Ironlake */
2781         reg = FDI_TX_CTL(pipe);
2782         temp = I915_READ(reg);
2783         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2784                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2785
2786                 POSTING_READ(reg);
2787                 udelay(100);
2788         }
2789 }
2790
2791 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2792 {
2793         struct drm_device *dev = intel_crtc->base.dev;
2794         struct drm_i915_private *dev_priv = dev->dev_private;
2795         int pipe = intel_crtc->pipe;
2796         u32 reg, temp;
2797
2798         /* Switch from PCDclk to Rawclk */
2799         reg = FDI_RX_CTL(pipe);
2800         temp = I915_READ(reg);
2801         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2802
2803         /* Disable CPU FDI TX PLL */
2804         reg = FDI_TX_CTL(pipe);
2805         temp = I915_READ(reg);
2806         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2807
2808         POSTING_READ(reg);
2809         udelay(100);
2810
2811         reg = FDI_RX_CTL(pipe);
2812         temp = I915_READ(reg);
2813         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2814
2815         /* Wait for the clocks to turn off. */
2816         POSTING_READ(reg);
2817         udelay(100);
2818 }
2819
2820 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2821 {
2822         struct drm_device *dev = crtc->dev;
2823         struct drm_i915_private *dev_priv = dev->dev_private;
2824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825         int pipe = intel_crtc->pipe;
2826         u32 reg, temp;
2827
2828         /* disable CPU FDI tx and PCH FDI rx */
2829         reg = FDI_TX_CTL(pipe);
2830         temp = I915_READ(reg);
2831         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2832         POSTING_READ(reg);
2833
2834         reg = FDI_RX_CTL(pipe);
2835         temp = I915_READ(reg);
2836         temp &= ~(0x7 << 16);
2837         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2838         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2839
2840         POSTING_READ(reg);
2841         udelay(100);
2842
2843         /* Ironlake workaround, disable clock pointer after downing FDI */
2844         if (HAS_PCH_IBX(dev)) {
2845                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2846         }
2847
2848         /* still set train pattern 1 */
2849         reg = FDI_TX_CTL(pipe);
2850         temp = I915_READ(reg);
2851         temp &= ~FDI_LINK_TRAIN_NONE;
2852         temp |= FDI_LINK_TRAIN_PATTERN_1;
2853         I915_WRITE(reg, temp);
2854
2855         reg = FDI_RX_CTL(pipe);
2856         temp = I915_READ(reg);
2857         if (HAS_PCH_CPT(dev)) {
2858                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2859                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2860         } else {
2861                 temp &= ~FDI_LINK_TRAIN_NONE;
2862                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2863         }
2864         /* BPC in FDI rx is consistent with that in PIPECONF */
2865         temp &= ~(0x07 << 16);
2866         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2867         I915_WRITE(reg, temp);
2868
2869         POSTING_READ(reg);
2870         udelay(100);
2871 }
2872
2873 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2874 {
2875         struct drm_device *dev = crtc->dev;
2876         struct drm_i915_private *dev_priv = dev->dev_private;
2877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2878         unsigned long flags;
2879         bool pending;
2880
2881         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2882             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2883                 return false;
2884
2885         spin_lock_irqsave(&dev->event_lock, flags);
2886         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2887         spin_unlock_irqrestore(&dev->event_lock, flags);
2888
2889         return pending;
2890 }
2891
2892 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2893 {
2894         struct drm_device *dev = crtc->dev;
2895         struct drm_i915_private *dev_priv = dev->dev_private;
2896
2897         if (crtc->fb == NULL)
2898                 return;
2899
2900         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2901
2902         wait_event(dev_priv->pending_flip_queue,
2903                    !intel_crtc_has_pending_flip(crtc));
2904
2905         mutex_lock(&dev->struct_mutex);
2906         intel_finish_fb(crtc->fb);
2907         mutex_unlock(&dev->struct_mutex);
2908 }
2909
2910 /* Program iCLKIP clock to the desired frequency */
2911 static void lpt_program_iclkip(struct drm_crtc *crtc)
2912 {
2913         struct drm_device *dev = crtc->dev;
2914         struct drm_i915_private *dev_priv = dev->dev_private;
2915         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2916         u32 temp;
2917
2918         mutex_lock(&dev_priv->dpio_lock);
2919
2920         /* It is necessary to ungate the pixclk gate prior to programming
2921          * the divisors, and gate it back when it is done.
2922          */
2923         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2924
2925         /* Disable SSCCTL */
2926         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2927                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2928                                 SBI_SSCCTL_DISABLE,
2929                         SBI_ICLK);
2930
2931         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2932         if (crtc->mode.clock == 20000) {
2933                 auxdiv = 1;
2934                 divsel = 0x41;
2935                 phaseinc = 0x20;
2936         } else {
2937                 /* The iCLK virtual clock root frequency is in MHz,
2938                  * but the crtc->mode.clock in in KHz. To get the divisors,
2939                  * it is necessary to divide one by another, so we
2940                  * convert the virtual clock precision to KHz here for higher
2941                  * precision.
2942                  */
2943                 u32 iclk_virtual_root_freq = 172800 * 1000;
2944                 u32 iclk_pi_range = 64;
2945                 u32 desired_divisor, msb_divisor_value, pi_value;
2946
2947                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2948                 msb_divisor_value = desired_divisor / iclk_pi_range;
2949                 pi_value = desired_divisor % iclk_pi_range;
2950
2951                 auxdiv = 0;
2952                 divsel = msb_divisor_value - 2;
2953                 phaseinc = pi_value;
2954         }
2955
2956         /* This should not happen with any sane values */
2957         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2958                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2959         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2960                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2961
2962         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2963                         crtc->mode.clock,
2964                         auxdiv,
2965                         divsel,
2966                         phasedir,
2967                         phaseinc);
2968
2969         /* Program SSCDIVINTPHASE6 */
2970         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2971         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2972         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2973         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2974         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2975         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2976         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2977         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2978
2979         /* Program SSCAUXDIV */
2980         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2981         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2982         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2983         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2984
2985         /* Enable modulator and associated divider */
2986         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2987         temp &= ~SBI_SSCCTL_DISABLE;
2988         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2989
2990         /* Wait for initialization time */
2991         udelay(24);
2992
2993         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2994
2995         mutex_unlock(&dev_priv->dpio_lock);
2996 }
2997
2998 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2999                                                 enum pipe pch_transcoder)
3000 {
3001         struct drm_device *dev = crtc->base.dev;
3002         struct drm_i915_private *dev_priv = dev->dev_private;
3003         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3004
3005         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3006                    I915_READ(HTOTAL(cpu_transcoder)));
3007         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3008                    I915_READ(HBLANK(cpu_transcoder)));
3009         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3010                    I915_READ(HSYNC(cpu_transcoder)));
3011
3012         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3013                    I915_READ(VTOTAL(cpu_transcoder)));
3014         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3015                    I915_READ(VBLANK(cpu_transcoder)));
3016         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3017                    I915_READ(VSYNC(cpu_transcoder)));
3018         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3019                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3020 }
3021
3022 /*
3023  * Enable PCH resources required for PCH ports:
3024  *   - PCH PLLs
3025  *   - FDI training & RX/TX
3026  *   - update transcoder timings
3027  *   - DP transcoding bits
3028  *   - transcoder
3029  */
3030 static void ironlake_pch_enable(struct drm_crtc *crtc)
3031 {
3032         struct drm_device *dev = crtc->dev;
3033         struct drm_i915_private *dev_priv = dev->dev_private;
3034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3035         int pipe = intel_crtc->pipe;
3036         u32 reg, temp;
3037
3038         assert_pch_transcoder_disabled(dev_priv, pipe);
3039
3040         /* Write the TU size bits before fdi link training, so that error
3041          * detection works. */
3042         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3043                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3044
3045         /* For PCH output, training FDI link */
3046         dev_priv->display.fdi_link_train(crtc);
3047
3048         /* XXX: pch pll's can be enabled any time before we enable the PCH
3049          * transcoder, and we actually should do this to not upset any PCH
3050          * transcoder that already use the clock when we share it.
3051          *
3052          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3053          * unconditionally resets the pll - we need that to have the right LVDS
3054          * enable sequence. */
3055         ironlake_enable_pch_pll(intel_crtc);
3056
3057         if (HAS_PCH_CPT(dev)) {
3058                 u32 sel;
3059
3060                 temp = I915_READ(PCH_DPLL_SEL);
3061                 switch (pipe) {
3062                 default:
3063                 case 0:
3064                         temp |= TRANSA_DPLL_ENABLE;
3065                         sel = TRANSA_DPLLB_SEL;
3066                         break;
3067                 case 1:
3068                         temp |= TRANSB_DPLL_ENABLE;
3069                         sel = TRANSB_DPLLB_SEL;
3070                         break;
3071                 case 2:
3072                         temp |= TRANSC_DPLL_ENABLE;
3073                         sel = TRANSC_DPLLB_SEL;
3074                         break;
3075                 }
3076                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3077                         temp |= sel;
3078                 else
3079                         temp &= ~sel;
3080                 I915_WRITE(PCH_DPLL_SEL, temp);
3081         }
3082
3083         /* set transcoder timing, panel must allow it */
3084         assert_panel_unlocked(dev_priv, pipe);
3085         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3086
3087         intel_fdi_normal_train(crtc);
3088
3089         /* For PCH DP, enable TRANS_DP_CTL */
3090         if (HAS_PCH_CPT(dev) &&
3091             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3092              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3093                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3094                 reg = TRANS_DP_CTL(pipe);
3095                 temp = I915_READ(reg);
3096                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3097                           TRANS_DP_SYNC_MASK |
3098                           TRANS_DP_BPC_MASK);
3099                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3100                          TRANS_DP_ENH_FRAMING);
3101                 temp |= bpc << 9; /* same format but at 11:9 */
3102
3103                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3104                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3105                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3106                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3107
3108                 switch (intel_trans_dp_port_sel(crtc)) {
3109                 case PCH_DP_B:
3110                         temp |= TRANS_DP_PORT_SEL_B;
3111                         break;
3112                 case PCH_DP_C:
3113                         temp |= TRANS_DP_PORT_SEL_C;
3114                         break;
3115                 case PCH_DP_D:
3116                         temp |= TRANS_DP_PORT_SEL_D;
3117                         break;
3118                 default:
3119                         BUG();
3120                 }
3121
3122                 I915_WRITE(reg, temp);
3123         }
3124
3125         ironlake_enable_pch_transcoder(dev_priv, pipe);
3126 }
3127
3128 static void lpt_pch_enable(struct drm_crtc *crtc)
3129 {
3130         struct drm_device *dev = crtc->dev;
3131         struct drm_i915_private *dev_priv = dev->dev_private;
3132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3133         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3134
3135         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3136
3137         lpt_program_iclkip(crtc);
3138
3139         /* Set transcoder timing. */
3140         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3141
3142         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3143 }
3144
3145 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3146 {
3147         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3148
3149         if (pll == NULL)
3150                 return;
3151
3152         if (pll->refcount == 0) {
3153                 WARN(1, "bad PCH PLL refcount\n");
3154                 return;
3155         }
3156
3157         --pll->refcount;
3158         intel_crtc->pch_pll = NULL;
3159 }
3160
3161 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3162 {
3163         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3164         struct intel_pch_pll *pll;
3165         int i;
3166
3167         pll = intel_crtc->pch_pll;
3168         if (pll) {
3169                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3170                               intel_crtc->base.base.id, pll->pll_reg);
3171                 goto prepare;
3172         }
3173
3174         if (HAS_PCH_IBX(dev_priv->dev)) {
3175                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3176                 i = intel_crtc->pipe;
3177                 pll = &dev_priv->pch_plls[i];
3178
3179                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3180                               intel_crtc->base.base.id, pll->pll_reg);
3181
3182                 goto found;
3183         }
3184
3185         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3186                 pll = &dev_priv->pch_plls[i];
3187
3188                 /* Only want to check enabled timings first */
3189                 if (pll->refcount == 0)
3190                         continue;
3191
3192                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3193                     fp == I915_READ(pll->fp0_reg)) {
3194                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3195                                       intel_crtc->base.base.id,
3196                                       pll->pll_reg, pll->refcount, pll->active);
3197
3198                         goto found;
3199                 }
3200         }
3201
3202         /* Ok no matching timings, maybe there's a free one? */
3203         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3204                 pll = &dev_priv->pch_plls[i];
3205                 if (pll->refcount == 0) {
3206                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3207                                       intel_crtc->base.base.id, pll->pll_reg);
3208                         goto found;
3209                 }
3210         }
3211
3212         return NULL;
3213
3214 found:
3215         intel_crtc->pch_pll = pll;
3216         pll->refcount++;
3217         DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3218 prepare: /* separate function? */
3219         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3220
3221         /* Wait for the clocks to stabilize before rewriting the regs */
3222         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3223         POSTING_READ(pll->pll_reg);
3224         udelay(150);
3225
3226         I915_WRITE(pll->fp0_reg, fp);
3227         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3228         pll->on = false;
3229         return pll;
3230 }
3231
3232 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3233 {
3234         struct drm_i915_private *dev_priv = dev->dev_private;
3235         int dslreg = PIPEDSL(pipe);
3236         u32 temp;
3237
3238         temp = I915_READ(dslreg);
3239         udelay(500);
3240         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3241                 if (wait_for(I915_READ(dslreg) != temp, 5))
3242                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3243         }
3244 }
3245
3246 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3247 {
3248         struct drm_device *dev = crtc->base.dev;
3249         struct drm_i915_private *dev_priv = dev->dev_private;
3250         int pipe = crtc->pipe;
3251
3252         if (crtc->config.pch_pfit.size) {
3253                 /* Force use of hard-coded filter coefficients
3254                  * as some pre-programmed values are broken,
3255                  * e.g. x201.
3256                  */
3257                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3258                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3259                                                  PF_PIPE_SEL_IVB(pipe));
3260                 else
3261                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3262                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3263                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3264         }
3265 }
3266
3267 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3268 {
3269         struct drm_device *dev = crtc->dev;
3270         struct drm_i915_private *dev_priv = dev->dev_private;
3271         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3272         struct intel_encoder *encoder;
3273         int pipe = intel_crtc->pipe;
3274         int plane = intel_crtc->plane;
3275         u32 temp;
3276
3277         WARN_ON(!crtc->enabled);
3278
3279         if (intel_crtc->active)
3280                 return;
3281
3282         intel_crtc->active = true;
3283
3284         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3285         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3286
3287         intel_update_watermarks(dev);
3288
3289         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3290                 temp = I915_READ(PCH_LVDS);
3291                 if ((temp & LVDS_PORT_EN) == 0)
3292                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3293         }
3294
3295
3296         if (intel_crtc->config.has_pch_encoder) {
3297                 /* Note: FDI PLL enabling _must_ be done before we enable the
3298                  * cpu pipes, hence this is separate from all the other fdi/pch
3299                  * enabling. */
3300                 ironlake_fdi_pll_enable(intel_crtc);
3301         } else {
3302                 assert_fdi_tx_disabled(dev_priv, pipe);
3303                 assert_fdi_rx_disabled(dev_priv, pipe);
3304         }
3305
3306         for_each_encoder_on_crtc(dev, crtc, encoder)
3307                 if (encoder->pre_enable)
3308                         encoder->pre_enable(encoder);
3309
3310         /* Enable panel fitting for LVDS */
3311         ironlake_pfit_enable(intel_crtc);
3312
3313         /*
3314          * On ILK+ LUT must be loaded before the pipe is running but with
3315          * clocks enabled
3316          */
3317         intel_crtc_load_lut(crtc);
3318
3319         intel_enable_pipe(dev_priv, pipe,
3320                           intel_crtc->config.has_pch_encoder);
3321         intel_enable_plane(dev_priv, plane, pipe);
3322
3323         if (intel_crtc->config.has_pch_encoder)
3324                 ironlake_pch_enable(crtc);
3325
3326         mutex_lock(&dev->struct_mutex);
3327         intel_update_fbc(dev);
3328         mutex_unlock(&dev->struct_mutex);
3329
3330         intel_crtc_update_cursor(crtc, true);
3331
3332         for_each_encoder_on_crtc(dev, crtc, encoder)
3333                 encoder->enable(encoder);
3334
3335         if (HAS_PCH_CPT(dev))
3336                 cpt_verify_modeset(dev, intel_crtc->pipe);
3337
3338         /*
3339          * There seems to be a race in PCH platform hw (at least on some
3340          * outputs) where an enabled pipe still completes any pageflip right
3341          * away (as if the pipe is off) instead of waiting for vblank. As soon
3342          * as the first vblank happend, everything works as expected. Hence just
3343          * wait for one vblank before returning to avoid strange things
3344          * happening.
3345          */
3346         intel_wait_for_vblank(dev, intel_crtc->pipe);
3347 }
3348
3349 static void haswell_crtc_enable(struct drm_crtc *crtc)
3350 {
3351         struct drm_device *dev = crtc->dev;
3352         struct drm_i915_private *dev_priv = dev->dev_private;
3353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354         struct intel_encoder *encoder;
3355         int pipe = intel_crtc->pipe;
3356         int plane = intel_crtc->plane;
3357
3358         WARN_ON(!crtc->enabled);
3359
3360         if (intel_crtc->active)
3361                 return;
3362
3363         intel_crtc->active = true;
3364
3365         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3366         if (intel_crtc->config.has_pch_encoder)
3367                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3368
3369         intel_update_watermarks(dev);
3370
3371         if (intel_crtc->config.has_pch_encoder)
3372                 dev_priv->display.fdi_link_train(crtc);
3373
3374         for_each_encoder_on_crtc(dev, crtc, encoder)
3375                 if (encoder->pre_enable)
3376                         encoder->pre_enable(encoder);
3377
3378         intel_ddi_enable_pipe_clock(intel_crtc);
3379
3380         /* Enable panel fitting for eDP */
3381         ironlake_pfit_enable(intel_crtc);
3382
3383         /*
3384          * On ILK+ LUT must be loaded before the pipe is running but with
3385          * clocks enabled
3386          */
3387         intel_crtc_load_lut(crtc);
3388
3389         intel_ddi_set_pipe_settings(crtc);
3390         intel_ddi_enable_transcoder_func(crtc);
3391
3392         intel_enable_pipe(dev_priv, pipe,
3393                           intel_crtc->config.has_pch_encoder);
3394         intel_enable_plane(dev_priv, plane, pipe);
3395
3396         if (intel_crtc->config.has_pch_encoder)
3397                 lpt_pch_enable(crtc);
3398
3399         mutex_lock(&dev->struct_mutex);
3400         intel_update_fbc(dev);
3401         mutex_unlock(&dev->struct_mutex);
3402
3403         intel_crtc_update_cursor(crtc, true);
3404
3405         for_each_encoder_on_crtc(dev, crtc, encoder)
3406                 encoder->enable(encoder);
3407
3408         /*
3409          * There seems to be a race in PCH platform hw (at least on some
3410          * outputs) where an enabled pipe still completes any pageflip right
3411          * away (as if the pipe is off) instead of waiting for vblank. As soon
3412          * as the first vblank happend, everything works as expected. Hence just
3413          * wait for one vblank before returning to avoid strange things
3414          * happening.
3415          */
3416         intel_wait_for_vblank(dev, intel_crtc->pipe);
3417 }
3418
3419 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3420 {
3421         struct drm_device *dev = crtc->dev;
3422         struct drm_i915_private *dev_priv = dev->dev_private;
3423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3424         struct intel_encoder *encoder;
3425         int pipe = intel_crtc->pipe;
3426         int plane = intel_crtc->plane;
3427         u32 reg, temp;
3428
3429
3430         if (!intel_crtc->active)
3431                 return;
3432
3433         for_each_encoder_on_crtc(dev, crtc, encoder)
3434                 encoder->disable(encoder);
3435
3436         intel_crtc_wait_for_pending_flips(crtc);
3437         drm_vblank_off(dev, pipe);
3438         intel_crtc_update_cursor(crtc, false);
3439
3440         intel_disable_plane(dev_priv, plane, pipe);
3441
3442         if (dev_priv->cfb_plane == plane)
3443                 intel_disable_fbc(dev);
3444
3445         intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3446         intel_disable_pipe(dev_priv, pipe);
3447
3448         /* Disable PF */
3449         I915_WRITE(PF_CTL(pipe), 0);
3450         I915_WRITE(PF_WIN_SZ(pipe), 0);
3451
3452         for_each_encoder_on_crtc(dev, crtc, encoder)
3453                 if (encoder->post_disable)
3454                         encoder->post_disable(encoder);
3455
3456         ironlake_fdi_disable(crtc);
3457
3458         ironlake_disable_pch_transcoder(dev_priv, pipe);
3459         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3460
3461         if (HAS_PCH_CPT(dev)) {
3462                 /* disable TRANS_DP_CTL */
3463                 reg = TRANS_DP_CTL(pipe);
3464                 temp = I915_READ(reg);
3465                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3466                 temp |= TRANS_DP_PORT_SEL_NONE;
3467                 I915_WRITE(reg, temp);
3468
3469                 /* disable DPLL_SEL */
3470                 temp = I915_READ(PCH_DPLL_SEL);
3471                 switch (pipe) {
3472                 case 0:
3473                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3474                         break;
3475                 case 1:
3476                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3477                         break;
3478                 case 2:
3479                         /* C shares PLL A or B */
3480                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3481                         break;
3482                 default:
3483                         BUG(); /* wtf */
3484                 }
3485                 I915_WRITE(PCH_DPLL_SEL, temp);
3486         }
3487
3488         /* disable PCH DPLL */
3489         intel_disable_pch_pll(intel_crtc);
3490
3491         ironlake_fdi_pll_disable(intel_crtc);
3492
3493         intel_crtc->active = false;
3494         intel_update_watermarks(dev);
3495
3496         mutex_lock(&dev->struct_mutex);
3497         intel_update_fbc(dev);
3498         mutex_unlock(&dev->struct_mutex);
3499 }
3500
3501 static void haswell_crtc_disable(struct drm_crtc *crtc)
3502 {
3503         struct drm_device *dev = crtc->dev;
3504         struct drm_i915_private *dev_priv = dev->dev_private;
3505         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3506         struct intel_encoder *encoder;
3507         int pipe = intel_crtc->pipe;
3508         int plane = intel_crtc->plane;
3509         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3510
3511         if (!intel_crtc->active)
3512                 return;
3513
3514         for_each_encoder_on_crtc(dev, crtc, encoder)
3515                 encoder->disable(encoder);
3516
3517         intel_crtc_wait_for_pending_flips(crtc);
3518         drm_vblank_off(dev, pipe);
3519         intel_crtc_update_cursor(crtc, false);
3520
3521         intel_disable_plane(dev_priv, plane, pipe);
3522
3523         if (dev_priv->cfb_plane == plane)
3524                 intel_disable_fbc(dev);
3525
3526         if (intel_crtc->config.has_pch_encoder)
3527                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3528         intel_disable_pipe(dev_priv, pipe);
3529
3530         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3531
3532         /* XXX: Once we have proper panel fitter state tracking implemented with
3533          * hardware state read/check support we should switch to only disable
3534          * the panel fitter when we know it's used. */
3535         if (intel_display_power_enabled(dev,
3536                                         POWER_DOMAIN_PIPE_PANEL_FITTER(pipe))) {
3537                 I915_WRITE(PF_CTL(pipe), 0);
3538                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3539         }
3540
3541         intel_ddi_disable_pipe_clock(intel_crtc);
3542
3543         for_each_encoder_on_crtc(dev, crtc, encoder)
3544                 if (encoder->post_disable)
3545                         encoder->post_disable(encoder);
3546
3547         if (intel_crtc->config.has_pch_encoder) {
3548                 lpt_disable_pch_transcoder(dev_priv);
3549                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3550                 intel_ddi_fdi_disable(crtc);
3551         }
3552
3553         intel_crtc->active = false;
3554         intel_update_watermarks(dev);
3555
3556         mutex_lock(&dev->struct_mutex);
3557         intel_update_fbc(dev);
3558         mutex_unlock(&dev->struct_mutex);
3559 }
3560
3561 static void ironlake_crtc_off(struct drm_crtc *crtc)
3562 {
3563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564         intel_put_pch_pll(intel_crtc);
3565 }
3566
3567 static void haswell_crtc_off(struct drm_crtc *crtc)
3568 {
3569         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3570
3571         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3572          * start using it. */
3573         intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3574
3575         intel_ddi_put_crtc_pll(crtc);
3576 }
3577
3578 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3579 {
3580         if (!enable && intel_crtc->overlay) {
3581                 struct drm_device *dev = intel_crtc->base.dev;
3582                 struct drm_i915_private *dev_priv = dev->dev_private;
3583
3584                 mutex_lock(&dev->struct_mutex);
3585                 dev_priv->mm.interruptible = false;
3586                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3587                 dev_priv->mm.interruptible = true;
3588                 mutex_unlock(&dev->struct_mutex);
3589         }
3590
3591         /* Let userspace switch the overlay on again. In most cases userspace
3592          * has to recompute where to put it anyway.
3593          */
3594 }
3595
3596 /**
3597  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3598  * cursor plane briefly if not already running after enabling the display
3599  * plane.
3600  * This workaround avoids occasional blank screens when self refresh is
3601  * enabled.
3602  */
3603 static void
3604 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3605 {
3606         u32 cntl = I915_READ(CURCNTR(pipe));
3607
3608         if ((cntl & CURSOR_MODE) == 0) {
3609                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3610
3611                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3612                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3613                 intel_wait_for_vblank(dev_priv->dev, pipe);
3614                 I915_WRITE(CURCNTR(pipe), cntl);
3615                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3616                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3617         }
3618 }
3619
3620 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3621 {
3622         struct drm_device *dev = crtc->base.dev;
3623         struct drm_i915_private *dev_priv = dev->dev_private;
3624         struct intel_crtc_config *pipe_config = &crtc->config;
3625
3626         if (!(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
3627               intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)))
3628                 return;
3629
3630         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3631         assert_pipe_disabled(dev_priv, crtc->pipe);
3632
3633         /*
3634          * Enable automatic panel scaling so that non-native modes
3635          * fill the screen.  The panel fitter should only be
3636          * adjusted whilst the pipe is disabled, according to
3637          * register description and PRM.
3638          */
3639         DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
3640                       pipe_config->gmch_pfit.control,
3641                       pipe_config->gmch_pfit.pgm_ratios);
3642
3643         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3644         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3645
3646         /* Border color in case we don't scale up to the full screen. Black by
3647          * default, change to something else for debugging. */
3648         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3649 }
3650
3651 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3652 {
3653         struct drm_device *dev = crtc->dev;
3654         struct drm_i915_private *dev_priv = dev->dev_private;
3655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656         struct intel_encoder *encoder;
3657         int pipe = intel_crtc->pipe;
3658         int plane = intel_crtc->plane;
3659
3660         WARN_ON(!crtc->enabled);
3661
3662         if (intel_crtc->active)
3663                 return;
3664
3665         intel_crtc->active = true;
3666         intel_update_watermarks(dev);
3667
3668         mutex_lock(&dev_priv->dpio_lock);
3669
3670         for_each_encoder_on_crtc(dev, crtc, encoder)
3671                 if (encoder->pre_pll_enable)
3672                         encoder->pre_pll_enable(encoder);
3673
3674         intel_enable_pll(dev_priv, pipe);
3675
3676         for_each_encoder_on_crtc(dev, crtc, encoder)
3677                 if (encoder->pre_enable)
3678                         encoder->pre_enable(encoder);
3679
3680         /* VLV wants encoder enabling _before_ the pipe is up. */
3681         for_each_encoder_on_crtc(dev, crtc, encoder)
3682                 encoder->enable(encoder);
3683
3684         /* Enable panel fitting for eDP */
3685         i9xx_pfit_enable(intel_crtc);
3686
3687         intel_enable_pipe(dev_priv, pipe, false);
3688         intel_enable_plane(dev_priv, plane, pipe);
3689
3690         intel_crtc_load_lut(crtc);
3691         intel_update_fbc(dev);
3692
3693         /* Give the overlay scaler a chance to enable if it's on this pipe */
3694         intel_crtc_dpms_overlay(intel_crtc, true);
3695         intel_crtc_update_cursor(crtc, true);
3696
3697         mutex_unlock(&dev_priv->dpio_lock);
3698 }
3699
3700 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3701 {
3702         struct drm_device *dev = crtc->dev;
3703         struct drm_i915_private *dev_priv = dev->dev_private;
3704         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3705         struct intel_encoder *encoder;
3706         int pipe = intel_crtc->pipe;
3707         int plane = intel_crtc->plane;
3708
3709         WARN_ON(!crtc->enabled);
3710
3711         if (intel_crtc->active)
3712                 return;
3713
3714         intel_crtc->active = true;
3715         intel_update_watermarks(dev);
3716
3717         intel_enable_pll(dev_priv, pipe);
3718
3719         for_each_encoder_on_crtc(dev, crtc, encoder)
3720                 if (encoder->pre_enable)
3721                         encoder->pre_enable(encoder);
3722
3723         /* Enable panel fitting for LVDS */
3724         i9xx_pfit_enable(intel_crtc);
3725
3726         intel_enable_pipe(dev_priv, pipe, false);
3727         intel_enable_plane(dev_priv, plane, pipe);
3728         if (IS_G4X(dev))
3729                 g4x_fixup_plane(dev_priv, pipe);
3730
3731         intel_crtc_load_lut(crtc);
3732         intel_update_fbc(dev);
3733
3734         /* Give the overlay scaler a chance to enable if it's on this pipe */
3735         intel_crtc_dpms_overlay(intel_crtc, true);
3736         intel_crtc_update_cursor(crtc, true);
3737
3738         for_each_encoder_on_crtc(dev, crtc, encoder)
3739                 encoder->enable(encoder);
3740 }
3741
3742 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3743 {
3744         struct drm_device *dev = crtc->base.dev;
3745         struct drm_i915_private *dev_priv = dev->dev_private;
3746         enum pipe pipe;
3747         uint32_t pctl = I915_READ(PFIT_CONTROL);
3748
3749         assert_pipe_disabled(dev_priv, crtc->pipe);
3750
3751         if (INTEL_INFO(dev)->gen >= 4)
3752                 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3753         else
3754                 pipe = PIPE_B;
3755
3756         if (pipe == crtc->pipe) {
3757                 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3758                 I915_WRITE(PFIT_CONTROL, 0);
3759         }
3760 }
3761
3762 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3763 {
3764         struct drm_device *dev = crtc->dev;
3765         struct drm_i915_private *dev_priv = dev->dev_private;
3766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3767         struct intel_encoder *encoder;
3768         int pipe = intel_crtc->pipe;
3769         int plane = intel_crtc->plane;
3770
3771         if (!intel_crtc->active)
3772                 return;
3773
3774         for_each_encoder_on_crtc(dev, crtc, encoder)
3775                 encoder->disable(encoder);
3776
3777         /* Give the overlay scaler a chance to disable if it's on this pipe */
3778         intel_crtc_wait_for_pending_flips(crtc);
3779         drm_vblank_off(dev, pipe);
3780         intel_crtc_dpms_overlay(intel_crtc, false);
3781         intel_crtc_update_cursor(crtc, false);
3782
3783         if (dev_priv->cfb_plane == plane)
3784                 intel_disable_fbc(dev);
3785
3786         intel_disable_plane(dev_priv, plane, pipe);
3787         intel_disable_pipe(dev_priv, pipe);
3788
3789         i9xx_pfit_disable(intel_crtc);
3790
3791         for_each_encoder_on_crtc(dev, crtc, encoder)
3792                 if (encoder->post_disable)
3793                         encoder->post_disable(encoder);
3794
3795         intel_disable_pll(dev_priv, pipe);
3796
3797         intel_crtc->active = false;
3798         intel_update_fbc(dev);
3799         intel_update_watermarks(dev);
3800 }
3801
3802 static void i9xx_crtc_off(struct drm_crtc *crtc)
3803 {
3804 }
3805
3806 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3807                                     bool enabled)
3808 {
3809         struct drm_device *dev = crtc->dev;
3810         struct drm_i915_master_private *master_priv;
3811         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3812         int pipe = intel_crtc->pipe;
3813
3814         if (!dev->primary->master)
3815                 return;
3816
3817         master_priv = dev->primary->master->driver_priv;
3818         if (!master_priv->sarea_priv)
3819                 return;
3820
3821         switch (pipe) {
3822         case 0:
3823                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3824                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3825                 break;
3826         case 1:
3827                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3828                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3829                 break;
3830         default:
3831                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3832                 break;
3833         }
3834 }
3835
3836 /**
3837  * Sets the power management mode of the pipe and plane.
3838  */
3839 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3840 {
3841         struct drm_device *dev = crtc->dev;
3842         struct drm_i915_private *dev_priv = dev->dev_private;
3843         struct intel_encoder *intel_encoder;
3844         bool enable = false;
3845
3846         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3847                 enable |= intel_encoder->connectors_active;
3848
3849         if (enable)
3850                 dev_priv->display.crtc_enable(crtc);
3851         else
3852                 dev_priv->display.crtc_disable(crtc);
3853
3854         intel_crtc_update_sarea(crtc, enable);
3855 }
3856
3857 static void intel_crtc_disable(struct drm_crtc *crtc)
3858 {
3859         struct drm_device *dev = crtc->dev;
3860         struct drm_connector *connector;
3861         struct drm_i915_private *dev_priv = dev->dev_private;
3862         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3863
3864         /* crtc should still be enabled when we disable it. */
3865         WARN_ON(!crtc->enabled);
3866
3867         dev_priv->display.crtc_disable(crtc);
3868         intel_crtc->eld_vld = false;
3869         intel_crtc_update_sarea(crtc, false);
3870         dev_priv->display.off(crtc);
3871
3872         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3873         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3874
3875         if (crtc->fb) {
3876                 mutex_lock(&dev->struct_mutex);
3877                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3878                 mutex_unlock(&dev->struct_mutex);
3879                 crtc->fb = NULL;
3880         }
3881
3882         /* Update computed state. */
3883         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3884                 if (!connector->encoder || !connector->encoder->crtc)
3885                         continue;
3886
3887                 if (connector->encoder->crtc != crtc)
3888                         continue;
3889
3890                 connector->dpms = DRM_MODE_DPMS_OFF;
3891                 to_intel_encoder(connector->encoder)->connectors_active = false;
3892         }
3893 }
3894
3895 void intel_modeset_disable(struct drm_device *dev)
3896 {
3897         struct drm_crtc *crtc;
3898
3899         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3900                 if (crtc->enabled)
3901                         intel_crtc_disable(crtc);
3902         }
3903 }
3904
3905 void intel_encoder_destroy(struct drm_encoder *encoder)
3906 {
3907         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3908
3909         drm_encoder_cleanup(encoder);
3910         kfree(intel_encoder);
3911 }
3912
3913 /* Simple dpms helper for encodres with just one connector, no cloning and only
3914  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3915  * state of the entire output pipe. */
3916 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3917 {
3918         if (mode == DRM_MODE_DPMS_ON) {
3919                 encoder->connectors_active = true;
3920
3921                 intel_crtc_update_dpms(encoder->base.crtc);
3922         } else {
3923                 encoder->connectors_active = false;
3924
3925                 intel_crtc_update_dpms(encoder->base.crtc);
3926         }
3927 }
3928
3929 /* Cross check the actual hw state with our own modeset state tracking (and it's
3930  * internal consistency). */
3931 static void intel_connector_check_state(struct intel_connector *connector)
3932 {
3933         if (connector->get_hw_state(connector)) {
3934                 struct intel_encoder *encoder = connector->encoder;
3935                 struct drm_crtc *crtc;
3936                 bool encoder_enabled;
3937                 enum pipe pipe;
3938
3939                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3940                               connector->base.base.id,
3941                               drm_get_connector_name(&connector->base));
3942
3943                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3944                      "wrong connector dpms state\n");
3945                 WARN(connector->base.encoder != &encoder->base,
3946                      "active connector not linked to encoder\n");
3947                 WARN(!encoder->connectors_active,
3948                      "encoder->connectors_active not set\n");
3949
3950                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3951                 WARN(!encoder_enabled, "encoder not enabled\n");
3952                 if (WARN_ON(!encoder->base.crtc))
3953                         return;
3954
3955                 crtc = encoder->base.crtc;
3956
3957                 WARN(!crtc->enabled, "crtc not enabled\n");
3958                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3959                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3960                      "encoder active on the wrong pipe\n");
3961         }
3962 }
3963
3964 /* Even simpler default implementation, if there's really no special case to
3965  * consider. */
3966 void intel_connector_dpms(struct drm_connector *connector, int mode)
3967 {
3968         struct intel_encoder *encoder = intel_attached_encoder(connector);
3969
3970         /* All the simple cases only support two dpms states. */
3971         if (mode != DRM_MODE_DPMS_ON)
3972                 mode = DRM_MODE_DPMS_OFF;
3973
3974         if (mode == connector->dpms)
3975                 return;
3976
3977         connector->dpms = mode;
3978
3979         /* Only need to change hw state when actually enabled */
3980         if (encoder->base.crtc)
3981                 intel_encoder_dpms(encoder, mode);
3982         else
3983                 WARN_ON(encoder->connectors_active != false);
3984
3985         intel_modeset_check_state(connector->dev);
3986 }
3987
3988 /* Simple connector->get_hw_state implementation for encoders that support only
3989  * one connector and no cloning and hence the encoder state determines the state
3990  * of the connector. */
3991 bool intel_connector_get_hw_state(struct intel_connector *connector)
3992 {
3993         enum pipe pipe = 0;
3994         struct intel_encoder *encoder = connector->encoder;
3995
3996         return encoder->get_hw_state(encoder, &pipe);
3997 }
3998
3999 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4000                                      struct intel_crtc_config *pipe_config)
4001 {
4002         struct drm_i915_private *dev_priv = dev->dev_private;
4003         struct intel_crtc *pipe_B_crtc =
4004                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4005
4006         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4007                       pipe_name(pipe), pipe_config->fdi_lanes);
4008         if (pipe_config->fdi_lanes > 4) {
4009                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4010                               pipe_name(pipe), pipe_config->fdi_lanes);
4011                 return false;
4012         }
4013
4014         if (IS_HASWELL(dev)) {
4015                 if (pipe_config->fdi_lanes > 2) {
4016                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4017                                       pipe_config->fdi_lanes);
4018                         return false;
4019                 } else {
4020                         return true;
4021                 }
4022         }
4023
4024         if (INTEL_INFO(dev)->num_pipes == 2)
4025                 return true;
4026
4027         /* Ivybridge 3 pipe is really complicated */
4028         switch (pipe) {
4029         case PIPE_A:
4030                 return true;
4031         case PIPE_B:
4032                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4033                     pipe_config->fdi_lanes > 2) {
4034                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4035                                       pipe_name(pipe), pipe_config->fdi_lanes);
4036                         return false;
4037                 }
4038                 return true;
4039         case PIPE_C:
4040                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4041                     pipe_B_crtc->config.fdi_lanes <= 2) {
4042                         if (pipe_config->fdi_lanes > 2) {
4043                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4044                                               pipe_name(pipe), pipe_config->fdi_lanes);
4045                                 return false;
4046                         }
4047                 } else {
4048                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4049                         return false;
4050                 }
4051                 return true;
4052         default:
4053                 BUG();
4054         }
4055 }
4056
4057 #define RETRY 1
4058 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4059                                        struct intel_crtc_config *pipe_config)
4060 {
4061         struct drm_device *dev = intel_crtc->base.dev;
4062         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4063         int target_clock, lane, link_bw;
4064         bool setup_ok, needs_recompute = false;
4065
4066 retry:
4067         /* FDI is a binary signal running at ~2.7GHz, encoding
4068          * each output octet as 10 bits. The actual frequency
4069          * is stored as a divider into a 100MHz clock, and the
4070          * mode pixel clock is stored in units of 1KHz.
4071          * Hence the bw of each lane in terms of the mode signal
4072          * is:
4073          */
4074         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4075
4076         if (pipe_config->pixel_target_clock)
4077                 target_clock = pipe_config->pixel_target_clock;
4078         else
4079                 target_clock = adjusted_mode->clock;
4080
4081         lane = ironlake_get_lanes_required(target_clock, link_bw,
4082                                            pipe_config->pipe_bpp);
4083
4084         pipe_config->fdi_lanes = lane;
4085
4086         if (pipe_config->pixel_multiplier > 1)
4087                 link_bw *= pipe_config->pixel_multiplier;
4088         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4089                                link_bw, &pipe_config->fdi_m_n);
4090
4091         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4092                                             intel_crtc->pipe, pipe_config);
4093         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4094                 pipe_config->pipe_bpp -= 2*3;
4095                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4096                               pipe_config->pipe_bpp);
4097                 needs_recompute = true;
4098                 pipe_config->bw_constrained = true;
4099
4100                 goto retry;
4101         }
4102
4103         if (needs_recompute)
4104                 return RETRY;
4105
4106         return setup_ok ? 0 : -EINVAL;
4107 }
4108
4109 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4110                                      struct intel_crtc_config *pipe_config)
4111 {
4112         struct drm_device *dev = crtc->dev;
4113         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4114
4115         if (HAS_PCH_SPLIT(dev)) {
4116                 /* FDI link clock is fixed at 2.7G */
4117                 if (pipe_config->requested_mode.clock * 3
4118                     > IRONLAKE_FDI_FREQ * 4)
4119                         return -EINVAL;
4120         }
4121
4122         /* All interlaced capable intel hw wants timings in frames. Note though
4123          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4124          * timings, so we need to be careful not to clobber these.*/
4125         if (!pipe_config->timings_set)
4126                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4127
4128         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4129          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4130          */
4131         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4132                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4133                 return -EINVAL;
4134
4135         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4136                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4137         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4138                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4139                  * for lvds. */
4140                 pipe_config->pipe_bpp = 8*3;
4141         }
4142
4143         if (pipe_config->has_pch_encoder)
4144                 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
4145
4146         return 0;
4147 }
4148
4149 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4150 {
4151         return 400000; /* FIXME */
4152 }
4153
4154 static int i945_get_display_clock_speed(struct drm_device *dev)
4155 {
4156         return 400000;
4157 }
4158
4159 static int i915_get_display_clock_speed(struct drm_device *dev)
4160 {
4161         return 333000;
4162 }
4163
4164 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4165 {
4166         return 200000;
4167 }
4168
4169 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4170 {
4171         u16 gcfgc = 0;
4172
4173         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4174
4175         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4176                 return 133000;
4177         else {
4178                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4179                 case GC_DISPLAY_CLOCK_333_MHZ:
4180                         return 333000;
4181                 default:
4182                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4183                         return 190000;
4184                 }
4185         }
4186 }
4187
4188 static int i865_get_display_clock_speed(struct drm_device *dev)
4189 {
4190         return 266000;
4191 }
4192
4193 static int i855_get_display_clock_speed(struct drm_device *dev)
4194 {
4195         u16 hpllcc = 0;
4196         /* Assume that the hardware is in the high speed state.  This
4197          * should be the default.
4198          */
4199         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4200         case GC_CLOCK_133_200:
4201         case GC_CLOCK_100_200:
4202                 return 200000;
4203         case GC_CLOCK_166_250:
4204                 return 250000;
4205         case GC_CLOCK_100_133:
4206                 return 133000;
4207         }
4208
4209         /* Shouldn't happen */
4210         return 0;
4211 }
4212
4213 static int i830_get_display_clock_speed(struct drm_device *dev)
4214 {
4215         return 133000;
4216 }
4217
4218 static void
4219 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4220 {
4221         while (*num > 0xffffff || *den > 0xffffff) {
4222                 *num >>= 1;
4223                 *den >>= 1;
4224         }
4225 }
4226
4227 void
4228 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4229                        int pixel_clock, int link_clock,
4230                        struct intel_link_m_n *m_n)
4231 {
4232         m_n->tu = 64;
4233         m_n->gmch_m = bits_per_pixel * pixel_clock;
4234         m_n->gmch_n = link_clock * nlanes * 8;
4235         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4236         m_n->link_m = pixel_clock;
4237         m_n->link_n = link_clock;
4238         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4239 }
4240
4241 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4242 {
4243         if (i915_panel_use_ssc >= 0)
4244                 return i915_panel_use_ssc != 0;
4245         return dev_priv->lvds_use_ssc
4246                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4247 }
4248
4249 static int vlv_get_refclk(struct drm_crtc *crtc)
4250 {
4251         struct drm_device *dev = crtc->dev;
4252         struct drm_i915_private *dev_priv = dev->dev_private;
4253         int refclk = 27000; /* for DP & HDMI */
4254
4255         return 100000; /* only one validated so far */
4256
4257         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4258                 refclk = 96000;
4259         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4260                 if (intel_panel_use_ssc(dev_priv))
4261                         refclk = 100000;
4262                 else
4263                         refclk = 96000;
4264         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4265                 refclk = 100000;
4266         }
4267
4268         return refclk;
4269 }
4270
4271 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4272 {
4273         struct drm_device *dev = crtc->dev;
4274         struct drm_i915_private *dev_priv = dev->dev_private;
4275         int refclk;
4276
4277         if (IS_VALLEYVIEW(dev)) {
4278                 refclk = vlv_get_refclk(crtc);
4279         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4280             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4281                 refclk = dev_priv->lvds_ssc_freq * 1000;
4282                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4283                               refclk / 1000);
4284         } else if (!IS_GEN2(dev)) {
4285                 refclk = 96000;
4286         } else {
4287                 refclk = 48000;
4288         }
4289
4290         return refclk;
4291 }
4292
4293 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
4294 {
4295         unsigned dotclock = crtc->config.adjusted_mode.clock;
4296         struct dpll *clock = &crtc->config.dpll;
4297
4298         /* SDVO TV has fixed PLL values depend on its clock range,
4299            this mirrors vbios setting. */
4300         if (dotclock >= 100000 && dotclock < 140500) {
4301                 clock->p1 = 2;
4302                 clock->p2 = 10;
4303                 clock->n = 3;
4304                 clock->m1 = 16;
4305                 clock->m2 = 8;
4306         } else if (dotclock >= 140500 && dotclock <= 200000) {
4307                 clock->p1 = 1;
4308                 clock->p2 = 10;
4309                 clock->n = 6;
4310                 clock->m1 = 12;
4311                 clock->m2 = 8;
4312         }
4313
4314         crtc->config.clock_set = true;
4315 }
4316
4317 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4318 {
4319         return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4320 }
4321
4322 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4323 {
4324         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4325 }
4326
4327 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4328                                      intel_clock_t *reduced_clock)
4329 {
4330         struct drm_device *dev = crtc->base.dev;
4331         struct drm_i915_private *dev_priv = dev->dev_private;
4332         int pipe = crtc->pipe;
4333         u32 fp, fp2 = 0;
4334
4335         if (IS_PINEVIEW(dev)) {
4336                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4337                 if (reduced_clock)
4338                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4339         } else {
4340                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4341                 if (reduced_clock)
4342                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4343         }
4344
4345         I915_WRITE(FP0(pipe), fp);
4346
4347         crtc->lowfreq_avail = false;
4348         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4349             reduced_clock && i915_powersave) {
4350                 I915_WRITE(FP1(pipe), fp2);
4351                 crtc->lowfreq_avail = true;
4352         } else {
4353                 I915_WRITE(FP1(pipe), fp);
4354         }
4355 }
4356
4357 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4358 {
4359         u32 reg_val;
4360
4361         /*
4362          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4363          * and set it to a reasonable value instead.
4364          */
4365         reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4366         reg_val &= 0xffffff00;
4367         reg_val |= 0x00000030;
4368         intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4369
4370         reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4371         reg_val &= 0x8cffffff;
4372         reg_val = 0x8c000000;
4373         intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4374
4375         reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4376         reg_val &= 0xffffff00;
4377         intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4378
4379         reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4380         reg_val &= 0x00ffffff;
4381         reg_val |= 0xb0000000;
4382         intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4383 }
4384
4385 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4386                                          struct intel_link_m_n *m_n)
4387 {
4388         struct drm_device *dev = crtc->base.dev;
4389         struct drm_i915_private *dev_priv = dev->dev_private;
4390         int pipe = crtc->pipe;
4391
4392         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4393         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4394         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4395         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4396 }
4397
4398 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4399                                          struct intel_link_m_n *m_n)
4400 {
4401         struct drm_device *dev = crtc->base.dev;
4402         struct drm_i915_private *dev_priv = dev->dev_private;
4403         int pipe = crtc->pipe;
4404         enum transcoder transcoder = crtc->config.cpu_transcoder;
4405
4406         if (INTEL_INFO(dev)->gen >= 5) {
4407                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4408                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4409                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4410                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4411         } else {
4412                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4413                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4414                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4415                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4416         }
4417 }
4418
4419 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4420 {
4421         if (crtc->config.has_pch_encoder)
4422                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4423         else
4424                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4425 }
4426
4427 static void vlv_update_pll(struct intel_crtc *crtc)
4428 {
4429         struct drm_device *dev = crtc->base.dev;
4430         struct drm_i915_private *dev_priv = dev->dev_private;
4431         struct drm_display_mode *adjusted_mode =
4432                 &crtc->config.adjusted_mode;
4433         struct intel_encoder *encoder;
4434         int pipe = crtc->pipe;
4435         u32 dpll, mdiv;
4436         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4437         bool is_hdmi;
4438         u32 coreclk, reg_val, dpll_md;
4439
4440         mutex_lock(&dev_priv->dpio_lock);
4441
4442         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4443
4444         bestn = crtc->config.dpll.n;
4445         bestm1 = crtc->config.dpll.m1;
4446         bestm2 = crtc->config.dpll.m2;
4447         bestp1 = crtc->config.dpll.p1;
4448         bestp2 = crtc->config.dpll.p2;
4449
4450         /* See eDP HDMI DPIO driver vbios notes doc */
4451
4452         /* PLL B needs special handling */
4453         if (pipe)
4454                 vlv_pllb_recal_opamp(dev_priv);
4455
4456         /* Set up Tx target for periodic Rcomp update */
4457         intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4458
4459         /* Disable target IRef on PLL */
4460         reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4461         reg_val &= 0x00ffffff;
4462         intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4463
4464         /* Disable fast lock */
4465         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4466
4467         /* Set idtafcrecal before PLL is enabled */
4468         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4469         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4470         mdiv |= ((bestn << DPIO_N_SHIFT));
4471         mdiv |= (1 << DPIO_K_SHIFT);
4472
4473         /*
4474          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4475          * but we don't support that).
4476          * Note: don't use the DAC post divider as it seems unstable.
4477          */
4478         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4479         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4480
4481         mdiv |= DPIO_ENABLE_CALIBRATION;
4482         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4483
4484         /* Set HBR and RBR LPF coefficients */
4485         if (adjusted_mode->clock == 162000 ||
4486             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4487                 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4488                                  0x005f0021);
4489         else
4490                 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4491                                  0x00d0000f);
4492
4493         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4494             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4495                 /* Use SSC source */
4496                 if (!pipe)
4497                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4498                                          0x0df40000);
4499                 else
4500                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4501                                          0x0df70000);
4502         } else { /* HDMI or VGA */
4503                 /* Use bend source */
4504                 if (!pipe)
4505                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4506                                          0x0df70000);
4507                 else
4508                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4509                                          0x0df40000);
4510         }
4511
4512         coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4513         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4514         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4515             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4516                 coreclk |= 0x01000000;
4517         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4518
4519         intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4520
4521         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4522                 if (encoder->pre_pll_enable)
4523                         encoder->pre_pll_enable(encoder);
4524
4525         /* Enable DPIO clock input */
4526         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4527                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4528         if (pipe)
4529                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4530
4531         dpll |= DPLL_VCO_ENABLE;
4532         I915_WRITE(DPLL(pipe), dpll);
4533         POSTING_READ(DPLL(pipe));
4534         udelay(150);
4535
4536         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4537                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4538
4539         dpll_md = 0;
4540         if (crtc->config.pixel_multiplier > 1) {
4541                 dpll_md = (crtc->config.pixel_multiplier - 1)
4542                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4543         }
4544         I915_WRITE(DPLL_MD(pipe), dpll_md);
4545         POSTING_READ(DPLL_MD(pipe));
4546
4547         if (crtc->config.has_dp_encoder)
4548                 intel_dp_set_m_n(crtc);
4549
4550         mutex_unlock(&dev_priv->dpio_lock);
4551 }
4552
4553 static void i9xx_update_pll(struct intel_crtc *crtc,
4554                             intel_clock_t *reduced_clock,
4555                             int num_connectors)
4556 {
4557         struct drm_device *dev = crtc->base.dev;
4558         struct drm_i915_private *dev_priv = dev->dev_private;
4559         struct intel_encoder *encoder;
4560         int pipe = crtc->pipe;
4561         u32 dpll;
4562         bool is_sdvo;
4563         struct dpll *clock = &crtc->config.dpll;
4564
4565         i9xx_update_pll_dividers(crtc, reduced_clock);
4566
4567         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4568                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4569
4570         dpll = DPLL_VGA_MODE_DIS;
4571
4572         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4573                 dpll |= DPLLB_MODE_LVDS;
4574         else
4575                 dpll |= DPLLB_MODE_DAC_SERIAL;
4576
4577         if ((crtc->config.pixel_multiplier > 1) &&
4578             (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4579                 dpll |= (crtc->config.pixel_multiplier - 1)
4580                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4581         }
4582
4583         if (is_sdvo)
4584                 dpll |= DPLL_DVO_HIGH_SPEED;
4585
4586         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4587                 dpll |= DPLL_DVO_HIGH_SPEED;
4588
4589         /* compute bitmask from p1 value */
4590         if (IS_PINEVIEW(dev))
4591                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4592         else {
4593                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4594                 if (IS_G4X(dev) && reduced_clock)
4595                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4596         }
4597         switch (clock->p2) {
4598         case 5:
4599                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4600                 break;
4601         case 7:
4602                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4603                 break;
4604         case 10:
4605                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4606                 break;
4607         case 14:
4608                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4609                 break;
4610         }
4611         if (INTEL_INFO(dev)->gen >= 4)
4612                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4613
4614         if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4615                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4616         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4617                 /* XXX: just matching BIOS for now */
4618                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4619                 dpll |= 3;
4620         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4621                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4622                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4623         else
4624                 dpll |= PLL_REF_INPUT_DREFCLK;
4625
4626         dpll |= DPLL_VCO_ENABLE;
4627         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4628         POSTING_READ(DPLL(pipe));
4629         udelay(150);
4630
4631         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4632                 if (encoder->pre_pll_enable)
4633                         encoder->pre_pll_enable(encoder);
4634
4635         if (crtc->config.has_dp_encoder)
4636                 intel_dp_set_m_n(crtc);
4637
4638         I915_WRITE(DPLL(pipe), dpll);
4639
4640         /* Wait for the clocks to stabilize. */
4641         POSTING_READ(DPLL(pipe));
4642         udelay(150);
4643
4644         if (INTEL_INFO(dev)->gen >= 4) {
4645                 u32 dpll_md = 0;
4646                 if (crtc->config.pixel_multiplier > 1) {
4647                         dpll_md = (crtc->config.pixel_multiplier - 1)
4648                                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4649                 }
4650                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4651         } else {
4652                 /* The pixel multiplier can only be updated once the
4653                  * DPLL is enabled and the clocks are stable.
4654                  *
4655                  * So write it again.
4656                  */
4657                 I915_WRITE(DPLL(pipe), dpll);
4658         }
4659 }
4660
4661 static void i8xx_update_pll(struct intel_crtc *crtc,
4662                             struct drm_display_mode *adjusted_mode,
4663                             intel_clock_t *reduced_clock,
4664                             int num_connectors)
4665 {
4666         struct drm_device *dev = crtc->base.dev;
4667         struct drm_i915_private *dev_priv = dev->dev_private;
4668         struct intel_encoder *encoder;
4669         int pipe = crtc->pipe;
4670         u32 dpll;
4671         struct dpll *clock = &crtc->config.dpll;
4672
4673         i9xx_update_pll_dividers(crtc, reduced_clock);
4674
4675         dpll = DPLL_VGA_MODE_DIS;
4676
4677         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4678                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4679         } else {
4680                 if (clock->p1 == 2)
4681                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4682                 else
4683                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4684                 if (clock->p2 == 4)
4685                         dpll |= PLL_P2_DIVIDE_BY_4;
4686         }
4687
4688         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4689                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4690                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4691         else
4692                 dpll |= PLL_REF_INPUT_DREFCLK;
4693
4694         dpll |= DPLL_VCO_ENABLE;
4695         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4696         POSTING_READ(DPLL(pipe));
4697         udelay(150);
4698
4699         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4700                 if (encoder->pre_pll_enable)
4701                         encoder->pre_pll_enable(encoder);
4702
4703         I915_WRITE(DPLL(pipe), dpll);
4704
4705         /* Wait for the clocks to stabilize. */
4706         POSTING_READ(DPLL(pipe));
4707         udelay(150);
4708
4709         /* The pixel multiplier can only be updated once the
4710          * DPLL is enabled and the clocks are stable.
4711          *
4712          * So write it again.
4713          */
4714         I915_WRITE(DPLL(pipe), dpll);
4715 }
4716
4717 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4718                                    struct drm_display_mode *mode,
4719                                    struct drm_display_mode *adjusted_mode)
4720 {
4721         struct drm_device *dev = intel_crtc->base.dev;
4722         struct drm_i915_private *dev_priv = dev->dev_private;
4723         enum pipe pipe = intel_crtc->pipe;
4724         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4725         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4726
4727         /* We need to be careful not to changed the adjusted mode, for otherwise
4728          * the hw state checker will get angry at the mismatch. */
4729         crtc_vtotal = adjusted_mode->crtc_vtotal;
4730         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4731
4732         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4733                 /* the chip adds 2 halflines automatically */
4734                 crtc_vtotal -= 1;
4735                 crtc_vblank_end -= 1;
4736                 vsyncshift = adjusted_mode->crtc_hsync_start
4737                              - adjusted_mode->crtc_htotal / 2;
4738         } else {
4739                 vsyncshift = 0;
4740         }
4741
4742         if (INTEL_INFO(dev)->gen > 3)
4743                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4744
4745         I915_WRITE(HTOTAL(cpu_transcoder),
4746                    (adjusted_mode->crtc_hdisplay - 1) |
4747                    ((adjusted_mode->crtc_htotal - 1) << 16));
4748         I915_WRITE(HBLANK(cpu_transcoder),
4749                    (adjusted_mode->crtc_hblank_start - 1) |
4750                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4751         I915_WRITE(HSYNC(cpu_transcoder),
4752                    (adjusted_mode->crtc_hsync_start - 1) |
4753                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4754
4755         I915_WRITE(VTOTAL(cpu_transcoder),
4756                    (adjusted_mode->crtc_vdisplay - 1) |
4757                    ((crtc_vtotal - 1) << 16));
4758         I915_WRITE(VBLANK(cpu_transcoder),
4759                    (adjusted_mode->crtc_vblank_start - 1) |
4760                    ((crtc_vblank_end - 1) << 16));
4761         I915_WRITE(VSYNC(cpu_transcoder),
4762                    (adjusted_mode->crtc_vsync_start - 1) |
4763                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4764
4765         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4766          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4767          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4768          * bits. */
4769         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4770             (pipe == PIPE_B || pipe == PIPE_C))
4771                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4772
4773         /* pipesrc controls the size that is scaled from, which should
4774          * always be the user's requested size.
4775          */
4776         I915_WRITE(PIPESRC(pipe),
4777                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4778 }
4779
4780 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4781                                    struct intel_crtc_config *pipe_config)
4782 {
4783         struct drm_device *dev = crtc->base.dev;
4784         struct drm_i915_private *dev_priv = dev->dev_private;
4785         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4786         uint32_t tmp;
4787
4788         tmp = I915_READ(HTOTAL(cpu_transcoder));
4789         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4790         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4791         tmp = I915_READ(HBLANK(cpu_transcoder));
4792         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4793         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4794         tmp = I915_READ(HSYNC(cpu_transcoder));
4795         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4796         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4797
4798         tmp = I915_READ(VTOTAL(cpu_transcoder));
4799         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4800         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4801         tmp = I915_READ(VBLANK(cpu_transcoder));
4802         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4803         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4804         tmp = I915_READ(VSYNC(cpu_transcoder));
4805         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4806         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4807
4808         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4809                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4810                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4811                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4812         }
4813
4814         tmp = I915_READ(PIPESRC(crtc->pipe));
4815         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4816         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4817 }
4818
4819 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4820 {
4821         struct drm_device *dev = intel_crtc->base.dev;
4822         struct drm_i915_private *dev_priv = dev->dev_private;
4823         uint32_t pipeconf;
4824
4825         pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4826
4827         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4828                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4829                  * core speed.
4830                  *
4831                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4832                  * pipe == 0 check?
4833                  */
4834                 if (intel_crtc->config.requested_mode.clock >
4835                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4836                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4837                 else
4838                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4839         }
4840
4841         /* only g4x and later have fancy bpc/dither controls */
4842         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4843                 pipeconf &= ~(PIPECONF_BPC_MASK |
4844                               PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4845
4846                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4847                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4848                         pipeconf |= PIPECONF_DITHER_EN |
4849                                     PIPECONF_DITHER_TYPE_SP;
4850
4851                 switch (intel_crtc->config.pipe_bpp) {
4852                 case 18:
4853                         pipeconf |= PIPECONF_6BPC;
4854                         break;
4855                 case 24:
4856                         pipeconf |= PIPECONF_8BPC;
4857                         break;
4858                 case 30:
4859                         pipeconf |= PIPECONF_10BPC;
4860                         break;
4861                 default:
4862                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4863                         BUG();
4864                 }
4865         }
4866
4867         if (HAS_PIPE_CXSR(dev)) {
4868                 if (intel_crtc->lowfreq_avail) {
4869                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4870                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4871                 } else {
4872                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4873                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4874                 }
4875         }
4876
4877         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4878         if (!IS_GEN2(dev) &&
4879             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4880                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4881         else
4882                 pipeconf |= PIPECONF_PROGRESSIVE;
4883
4884         if (IS_VALLEYVIEW(dev)) {
4885                 if (intel_crtc->config.limited_color_range)
4886                         pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4887                 else
4888                         pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4889         }
4890
4891         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4892         POSTING_READ(PIPECONF(intel_crtc->pipe));
4893 }
4894
4895 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4896                               int x, int y,
4897                               struct drm_framebuffer *fb)
4898 {
4899         struct drm_device *dev = crtc->dev;
4900         struct drm_i915_private *dev_priv = dev->dev_private;
4901         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4902         struct drm_display_mode *adjusted_mode =
4903                 &intel_crtc->config.adjusted_mode;
4904         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4905         int pipe = intel_crtc->pipe;
4906         int plane = intel_crtc->plane;
4907         int refclk, num_connectors = 0;
4908         intel_clock_t clock, reduced_clock;
4909         u32 dspcntr;
4910         bool ok, has_reduced_clock = false, is_sdvo = false;
4911         bool is_lvds = false, is_tv = false;
4912         struct intel_encoder *encoder;
4913         const intel_limit_t *limit;
4914         int ret;
4915
4916         for_each_encoder_on_crtc(dev, crtc, encoder) {
4917                 switch (encoder->type) {
4918                 case INTEL_OUTPUT_LVDS:
4919                         is_lvds = true;
4920                         break;
4921                 case INTEL_OUTPUT_SDVO:
4922                 case INTEL_OUTPUT_HDMI:
4923                         is_sdvo = true;
4924                         if (encoder->needs_tv_clock)
4925                                 is_tv = true;
4926                         break;
4927                 case INTEL_OUTPUT_TVOUT:
4928                         is_tv = true;
4929                         break;
4930                 }
4931
4932                 num_connectors++;
4933         }
4934
4935         refclk = i9xx_get_refclk(crtc, num_connectors);
4936
4937         /*
4938          * Returns a set of divisors for the desired target clock with the given
4939          * refclk, or FALSE.  The returned values represent the clock equation:
4940          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4941          */
4942         limit = intel_limit(crtc, refclk);
4943         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4944                              &clock);
4945         if (!ok) {
4946                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4947                 return -EINVAL;
4948         }
4949
4950         /* Ensure that the cursor is valid for the new mode before changing... */
4951         intel_crtc_update_cursor(crtc, true);
4952
4953         if (is_lvds && dev_priv->lvds_downclock_avail) {
4954                 /*
4955                  * Ensure we match the reduced clock's P to the target clock.
4956                  * If the clocks don't match, we can't switch the display clock
4957                  * by using the FP0/FP1. In such case we will disable the LVDS
4958                  * downclock feature.
4959                 */
4960                 has_reduced_clock = limit->find_pll(limit, crtc,
4961                                                     dev_priv->lvds_downclock,
4962                                                     refclk,
4963                                                     &clock,
4964                                                     &reduced_clock);
4965         }
4966         /* Compat-code for transition, will disappear. */
4967         if (!intel_crtc->config.clock_set) {
4968                 intel_crtc->config.dpll.n = clock.n;
4969                 intel_crtc->config.dpll.m1 = clock.m1;
4970                 intel_crtc->config.dpll.m2 = clock.m2;
4971                 intel_crtc->config.dpll.p1 = clock.p1;
4972                 intel_crtc->config.dpll.p2 = clock.p2;
4973         }
4974
4975         if (is_sdvo && is_tv)
4976                 i9xx_adjust_sdvo_tv_clock(intel_crtc);
4977
4978         if (IS_GEN2(dev))
4979                 i8xx_update_pll(intel_crtc, adjusted_mode,
4980                                 has_reduced_clock ? &reduced_clock : NULL,
4981                                 num_connectors);
4982         else if (IS_VALLEYVIEW(dev))
4983                 vlv_update_pll(intel_crtc);
4984         else
4985                 i9xx_update_pll(intel_crtc,
4986                                 has_reduced_clock ? &reduced_clock : NULL,
4987                                 num_connectors);
4988
4989         /* Set up the display plane register */
4990         dspcntr = DISPPLANE_GAMMA_ENABLE;
4991
4992         if (!IS_VALLEYVIEW(dev)) {
4993                 if (pipe == 0)
4994                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4995                 else
4996                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4997         }
4998
4999         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5000         drm_mode_debug_printmodeline(mode);
5001
5002         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5003
5004         /* pipesrc and dspsize control the size that is scaled from,
5005          * which should always be the user's requested size.
5006          */
5007         I915_WRITE(DSPSIZE(plane),
5008                    ((mode->vdisplay - 1) << 16) |
5009                    (mode->hdisplay - 1));
5010         I915_WRITE(DSPPOS(plane), 0);
5011
5012         i9xx_set_pipeconf(intel_crtc);
5013
5014         I915_WRITE(DSPCNTR(plane), dspcntr);
5015         POSTING_READ(DSPCNTR(plane));
5016
5017         ret = intel_pipe_set_base(crtc, x, y, fb);
5018
5019         intel_update_watermarks(dev);
5020
5021         return ret;
5022 }
5023
5024 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5025                                  struct intel_crtc_config *pipe_config)
5026 {
5027         struct drm_device *dev = crtc->base.dev;
5028         struct drm_i915_private *dev_priv = dev->dev_private;
5029         uint32_t tmp;
5030
5031         tmp = I915_READ(PIPECONF(crtc->pipe));
5032         if (!(tmp & PIPECONF_ENABLE))
5033                 return false;
5034
5035         intel_get_pipe_timings(crtc, pipe_config);
5036
5037         return true;
5038 }
5039
5040 static void ironlake_init_pch_refclk(struct drm_device *dev)
5041 {
5042         struct drm_i915_private *dev_priv = dev->dev_private;
5043         struct drm_mode_config *mode_config = &dev->mode_config;
5044         struct intel_encoder *encoder;
5045         u32 val, final;
5046         bool has_lvds = false;
5047         bool has_cpu_edp = false;
5048         bool has_panel = false;
5049         bool has_ck505 = false;
5050         bool can_ssc = false;
5051
5052         /* We need to take the global config into account */
5053         list_for_each_entry(encoder, &mode_config->encoder_list,
5054                             base.head) {
5055                 switch (encoder->type) {
5056                 case INTEL_OUTPUT_LVDS:
5057                         has_panel = true;
5058                         has_lvds = true;
5059                         break;
5060                 case INTEL_OUTPUT_EDP:
5061                         has_panel = true;
5062                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5063                                 has_cpu_edp = true;
5064                         break;
5065                 }
5066         }
5067
5068         if (HAS_PCH_IBX(dev)) {
5069                 has_ck505 = dev_priv->display_clock_mode;
5070                 can_ssc = has_ck505;
5071         } else {
5072                 has_ck505 = false;
5073                 can_ssc = true;
5074         }
5075
5076         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5077                       has_panel, has_lvds, has_ck505);
5078
5079         /* Ironlake: try to setup display ref clock before DPLL
5080          * enabling. This is only under driver's control after
5081          * PCH B stepping, previous chipset stepping should be
5082          * ignoring this setting.
5083          */
5084         val = I915_READ(PCH_DREF_CONTROL);
5085
5086         /* As we must carefully and slowly disable/enable each source in turn,
5087          * compute the final state we want first and check if we need to
5088          * make any changes at all.
5089          */
5090         final = val;
5091         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5092         if (has_ck505)
5093                 final |= DREF_NONSPREAD_CK505_ENABLE;
5094         else
5095                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5096
5097         final &= ~DREF_SSC_SOURCE_MASK;
5098         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5099         final &= ~DREF_SSC1_ENABLE;
5100
5101         if (has_panel) {
5102                 final |= DREF_SSC_SOURCE_ENABLE;
5103
5104                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5105                         final |= DREF_SSC1_ENABLE;
5106
5107                 if (has_cpu_edp) {
5108                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5109                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5110                         else
5111                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5112                 } else
5113                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5114         } else {
5115                 final |= DREF_SSC_SOURCE_DISABLE;
5116                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5117         }
5118
5119         if (final == val)
5120                 return;
5121
5122         /* Always enable nonspread source */
5123         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5124
5125         if (has_ck505)
5126                 val |= DREF_NONSPREAD_CK505_ENABLE;
5127         else
5128                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5129
5130         if (has_panel) {
5131                 val &= ~DREF_SSC_SOURCE_MASK;
5132                 val |= DREF_SSC_SOURCE_ENABLE;
5133
5134                 /* SSC must be turned on before enabling the CPU output  */
5135                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5136                         DRM_DEBUG_KMS("Using SSC on panel\n");
5137                         val |= DREF_SSC1_ENABLE;
5138                 } else
5139                         val &= ~DREF_SSC1_ENABLE;
5140
5141                 /* Get SSC going before enabling the outputs */
5142                 I915_WRITE(PCH_DREF_CONTROL, val);
5143                 POSTING_READ(PCH_DREF_CONTROL);
5144                 udelay(200);
5145
5146                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5147
5148                 /* Enable CPU source on CPU attached eDP */
5149                 if (has_cpu_edp) {
5150                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5151                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5152                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5153                         }
5154                         else
5155                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5156                 } else
5157                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5158
5159                 I915_WRITE(PCH_DREF_CONTROL, val);
5160                 POSTING_READ(PCH_DREF_CONTROL);
5161                 udelay(200);
5162         } else {
5163                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5164
5165                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5166
5167                 /* Turn off CPU output */
5168                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5169
5170                 I915_WRITE(PCH_DREF_CONTROL, val);
5171                 POSTING_READ(PCH_DREF_CONTROL);
5172                 udelay(200);
5173
5174                 /* Turn off the SSC source */
5175                 val &= ~DREF_SSC_SOURCE_MASK;
5176                 val |= DREF_SSC_SOURCE_DISABLE;
5177
5178                 /* Turn off SSC1 */
5179                 val &= ~DREF_SSC1_ENABLE;
5180
5181                 I915_WRITE(PCH_DREF_CONTROL, val);
5182                 POSTING_READ(PCH_DREF_CONTROL);
5183                 udelay(200);
5184         }
5185
5186         BUG_ON(val != final);
5187 }
5188
5189 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5190 static void lpt_init_pch_refclk(struct drm_device *dev)
5191 {
5192         struct drm_i915_private *dev_priv = dev->dev_private;
5193         struct drm_mode_config *mode_config = &dev->mode_config;
5194         struct intel_encoder *encoder;
5195         bool has_vga = false;
5196         bool is_sdv = false;
5197         u32 tmp;
5198
5199         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5200                 switch (encoder->type) {
5201                 case INTEL_OUTPUT_ANALOG:
5202                         has_vga = true;
5203                         break;
5204                 }
5205         }
5206
5207         if (!has_vga)
5208                 return;
5209
5210         mutex_lock(&dev_priv->dpio_lock);
5211
5212         /* XXX: Rip out SDV support once Haswell ships for real. */
5213         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5214                 is_sdv = true;
5215
5216         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5217         tmp &= ~SBI_SSCCTL_DISABLE;
5218         tmp |= SBI_SSCCTL_PATHALT;
5219         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5220
5221         udelay(24);
5222
5223         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5224         tmp &= ~SBI_SSCCTL_PATHALT;
5225         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5226
5227         if (!is_sdv) {
5228                 tmp = I915_READ(SOUTH_CHICKEN2);
5229                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5230                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5231
5232                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5233                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5234                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5235
5236                 tmp = I915_READ(SOUTH_CHICKEN2);
5237                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5238                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5239
5240                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5241                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5242                                        100))
5243                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5244         }
5245
5246         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5247         tmp &= ~(0xFF << 24);
5248         tmp |= (0x12 << 24);
5249         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5250
5251         if (is_sdv) {
5252                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5253                 tmp |= 0x7FFF;
5254                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5255         }
5256
5257         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5258         tmp |= (1 << 11);
5259         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5260
5261         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5262         tmp |= (1 << 11);
5263         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5264
5265         if (is_sdv) {
5266                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5267                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5268                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5269
5270                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5271                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5272                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5273
5274                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5275                 tmp |= (0x3F << 8);
5276                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5277
5278                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5279                 tmp |= (0x3F << 8);
5280                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5281         }
5282
5283         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5284         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5285         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5286
5287         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5288         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5289         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5290
5291         if (!is_sdv) {
5292                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5293                 tmp &= ~(7 << 13);
5294                 tmp |= (5 << 13);
5295                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5296
5297                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5298                 tmp &= ~(7 << 13);
5299                 tmp |= (5 << 13);
5300                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5301         }
5302
5303         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5304         tmp &= ~0xFF;
5305         tmp |= 0x1C;
5306         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5307
5308         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5309         tmp &= ~0xFF;
5310         tmp |= 0x1C;
5311         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5312
5313         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5314         tmp &= ~(0xFF << 16);
5315         tmp |= (0x1C << 16);
5316         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5317
5318         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5319         tmp &= ~(0xFF << 16);
5320         tmp |= (0x1C << 16);
5321         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5322
5323         if (!is_sdv) {
5324                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5325                 tmp |= (1 << 27);
5326                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5327
5328                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5329                 tmp |= (1 << 27);
5330                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5331
5332                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5333                 tmp &= ~(0xF << 28);
5334                 tmp |= (4 << 28);
5335                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5336
5337                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5338                 tmp &= ~(0xF << 28);
5339                 tmp |= (4 << 28);
5340                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5341         }
5342
5343         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5344         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5345         tmp |= SBI_DBUFF0_ENABLE;
5346         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5347
5348         mutex_unlock(&dev_priv->dpio_lock);
5349 }
5350
5351 /*
5352  * Initialize reference clocks when the driver loads
5353  */
5354 void intel_init_pch_refclk(struct drm_device *dev)
5355 {
5356         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5357                 ironlake_init_pch_refclk(dev);
5358         else if (HAS_PCH_LPT(dev))
5359                 lpt_init_pch_refclk(dev);
5360 }
5361
5362 static int ironlake_get_refclk(struct drm_crtc *crtc)
5363 {
5364         struct drm_device *dev = crtc->dev;
5365         struct drm_i915_private *dev_priv = dev->dev_private;
5366         struct intel_encoder *encoder;
5367         struct intel_encoder *edp_encoder = NULL;
5368         int num_connectors = 0;
5369         bool is_lvds = false;
5370
5371         for_each_encoder_on_crtc(dev, crtc, encoder) {
5372                 switch (encoder->type) {
5373                 case INTEL_OUTPUT_LVDS:
5374                         is_lvds = true;
5375                         break;
5376                 case INTEL_OUTPUT_EDP:
5377                         edp_encoder = encoder;
5378                         break;
5379                 }
5380                 num_connectors++;
5381         }
5382
5383         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5384                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5385                               dev_priv->lvds_ssc_freq);
5386                 return dev_priv->lvds_ssc_freq * 1000;
5387         }
5388
5389         return 120000;
5390 }
5391
5392 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5393 {
5394         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5396         int pipe = intel_crtc->pipe;
5397         uint32_t val;
5398
5399         val = I915_READ(PIPECONF(pipe));
5400
5401         val &= ~PIPECONF_BPC_MASK;
5402         switch (intel_crtc->config.pipe_bpp) {
5403         case 18:
5404                 val |= PIPECONF_6BPC;
5405                 break;
5406         case 24:
5407                 val |= PIPECONF_8BPC;
5408                 break;
5409         case 30:
5410                 val |= PIPECONF_10BPC;
5411                 break;
5412         case 36:
5413                 val |= PIPECONF_12BPC;
5414                 break;
5415         default:
5416                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5417                 BUG();
5418         }
5419
5420         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5421         if (intel_crtc->config.dither)
5422                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5423
5424         val &= ~PIPECONF_INTERLACE_MASK;
5425         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5426                 val |= PIPECONF_INTERLACED_ILK;
5427         else
5428                 val |= PIPECONF_PROGRESSIVE;
5429
5430         if (intel_crtc->config.limited_color_range)
5431                 val |= PIPECONF_COLOR_RANGE_SELECT;
5432         else
5433                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5434
5435         I915_WRITE(PIPECONF(pipe), val);
5436         POSTING_READ(PIPECONF(pipe));
5437 }
5438
5439 /*
5440  * Set up the pipe CSC unit.
5441  *
5442  * Currently only full range RGB to limited range RGB conversion
5443  * is supported, but eventually this should handle various
5444  * RGB<->YCbCr scenarios as well.
5445  */
5446 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5447 {
5448         struct drm_device *dev = crtc->dev;
5449         struct drm_i915_private *dev_priv = dev->dev_private;
5450         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5451         int pipe = intel_crtc->pipe;
5452         uint16_t coeff = 0x7800; /* 1.0 */
5453
5454         /*
5455          * TODO: Check what kind of values actually come out of the pipe
5456          * with these coeff/postoff values and adjust to get the best
5457          * accuracy. Perhaps we even need to take the bpc value into
5458          * consideration.
5459          */
5460
5461         if (intel_crtc->config.limited_color_range)
5462                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5463
5464         /*
5465          * GY/GU and RY/RU should be the other way around according
5466          * to BSpec, but reality doesn't agree. Just set them up in
5467          * a way that results in the correct picture.
5468          */
5469         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5470         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5471
5472         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5473         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5474
5475         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5476         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5477
5478         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5479         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5480         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5481
5482         if (INTEL_INFO(dev)->gen > 6) {
5483                 uint16_t postoff = 0;
5484
5485                 if (intel_crtc->config.limited_color_range)
5486                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5487
5488                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5489                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5490                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5491
5492                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5493         } else {
5494                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5495
5496                 if (intel_crtc->config.limited_color_range)
5497                         mode |= CSC_BLACK_SCREEN_OFFSET;
5498
5499                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5500         }
5501 }
5502
5503 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5504 {
5505         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5507         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5508         uint32_t val;
5509
5510         val = I915_READ(PIPECONF(cpu_transcoder));
5511
5512         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5513         if (intel_crtc->config.dither)
5514                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5515
5516         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5517         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5518                 val |= PIPECONF_INTERLACED_ILK;
5519         else
5520                 val |= PIPECONF_PROGRESSIVE;
5521
5522         I915_WRITE(PIPECONF(cpu_transcoder), val);
5523         POSTING_READ(PIPECONF(cpu_transcoder));
5524 }
5525
5526 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5527                                     struct drm_display_mode *adjusted_mode,
5528                                     intel_clock_t *clock,
5529                                     bool *has_reduced_clock,
5530                                     intel_clock_t *reduced_clock)
5531 {
5532         struct drm_device *dev = crtc->dev;
5533         struct drm_i915_private *dev_priv = dev->dev_private;
5534         struct intel_encoder *intel_encoder;
5535         int refclk;
5536         const intel_limit_t *limit;
5537         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5538
5539         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5540                 switch (intel_encoder->type) {
5541                 case INTEL_OUTPUT_LVDS:
5542                         is_lvds = true;
5543                         break;
5544                 case INTEL_OUTPUT_SDVO:
5545                 case INTEL_OUTPUT_HDMI:
5546                         is_sdvo = true;
5547                         if (intel_encoder->needs_tv_clock)
5548                                 is_tv = true;
5549                         break;
5550                 case INTEL_OUTPUT_TVOUT:
5551                         is_tv = true;
5552                         break;
5553                 }
5554         }
5555
5556         refclk = ironlake_get_refclk(crtc);
5557
5558         /*
5559          * Returns a set of divisors for the desired target clock with the given
5560          * refclk, or FALSE.  The returned values represent the clock equation:
5561          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5562          */
5563         limit = intel_limit(crtc, refclk);
5564         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5565                               clock);
5566         if (!ret)
5567                 return false;
5568
5569         if (is_lvds && dev_priv->lvds_downclock_avail) {
5570                 /*
5571                  * Ensure we match the reduced clock's P to the target clock.
5572                  * If the clocks don't match, we can't switch the display clock
5573                  * by using the FP0/FP1. In such case we will disable the LVDS
5574                  * downclock feature.
5575                 */
5576                 *has_reduced_clock = limit->find_pll(limit, crtc,
5577                                                      dev_priv->lvds_downclock,
5578                                                      refclk,
5579                                                      clock,
5580                                                      reduced_clock);
5581         }
5582
5583         if (is_sdvo && is_tv)
5584                 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
5585
5586         return true;
5587 }
5588
5589 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5590 {
5591         struct drm_i915_private *dev_priv = dev->dev_private;
5592         uint32_t temp;
5593
5594         temp = I915_READ(SOUTH_CHICKEN1);
5595         if (temp & FDI_BC_BIFURCATION_SELECT)
5596                 return;
5597
5598         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5599         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5600
5601         temp |= FDI_BC_BIFURCATION_SELECT;
5602         DRM_DEBUG_KMS("enabling fdi C rx\n");
5603         I915_WRITE(SOUTH_CHICKEN1, temp);
5604         POSTING_READ(SOUTH_CHICKEN1);
5605 }
5606
5607 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5608 {
5609         struct drm_device *dev = intel_crtc->base.dev;
5610         struct drm_i915_private *dev_priv = dev->dev_private;
5611
5612         switch (intel_crtc->pipe) {
5613         case PIPE_A:
5614                 break;
5615         case PIPE_B:
5616                 if (intel_crtc->config.fdi_lanes > 2)
5617                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5618                 else
5619                         cpt_enable_fdi_bc_bifurcation(dev);
5620
5621                 break;
5622         case PIPE_C:
5623                 cpt_enable_fdi_bc_bifurcation(dev);
5624
5625                 break;
5626         default:
5627                 BUG();
5628         }
5629 }
5630
5631 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5632 {
5633         /*
5634          * Account for spread spectrum to avoid
5635          * oversubscribing the link. Max center spread
5636          * is 2.5%; use 5% for safety's sake.
5637          */
5638         u32 bps = target_clock * bpp * 21 / 20;
5639         return bps / (link_bw * 8) + 1;
5640 }
5641
5642 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5643 {
5644         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5645 }
5646
5647 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5648                                       u32 *fp,
5649                                       intel_clock_t *reduced_clock, u32 *fp2)
5650 {
5651         struct drm_crtc *crtc = &intel_crtc->base;
5652         struct drm_device *dev = crtc->dev;
5653         struct drm_i915_private *dev_priv = dev->dev_private;
5654         struct intel_encoder *intel_encoder;
5655         uint32_t dpll;
5656         int factor, num_connectors = 0;
5657         bool is_lvds = false, is_sdvo = false, is_tv = false;
5658
5659         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5660                 switch (intel_encoder->type) {
5661                 case INTEL_OUTPUT_LVDS:
5662                         is_lvds = true;
5663                         break;
5664                 case INTEL_OUTPUT_SDVO:
5665                 case INTEL_OUTPUT_HDMI:
5666                         is_sdvo = true;
5667                         if (intel_encoder->needs_tv_clock)
5668                                 is_tv = true;
5669                         break;
5670                 case INTEL_OUTPUT_TVOUT:
5671                         is_tv = true;
5672                         break;
5673                 }
5674
5675                 num_connectors++;
5676         }
5677
5678         /* Enable autotuning of the PLL clock (if permissible) */
5679         factor = 21;
5680         if (is_lvds) {
5681                 if ((intel_panel_use_ssc(dev_priv) &&
5682                      dev_priv->lvds_ssc_freq == 100) ||
5683                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5684                         factor = 25;
5685         } else if (is_sdvo && is_tv)
5686                 factor = 20;
5687
5688         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5689                 *fp |= FP_CB_TUNE;
5690
5691         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5692                 *fp2 |= FP_CB_TUNE;
5693
5694         dpll = 0;
5695
5696         if (is_lvds)
5697                 dpll |= DPLLB_MODE_LVDS;
5698         else
5699                 dpll |= DPLLB_MODE_DAC_SERIAL;
5700
5701         if (intel_crtc->config.pixel_multiplier > 1) {
5702                 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5703                         << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5704         }
5705
5706         if (is_sdvo)
5707                 dpll |= DPLL_DVO_HIGH_SPEED;
5708         if (intel_crtc->config.has_dp_encoder)
5709                 dpll |= DPLL_DVO_HIGH_SPEED;
5710
5711         /* compute bitmask from p1 value */
5712         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5713         /* also FPA1 */
5714         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5715
5716         switch (intel_crtc->config.dpll.p2) {
5717         case 5:
5718                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5719                 break;
5720         case 7:
5721                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5722                 break;
5723         case 10:
5724                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5725                 break;
5726         case 14:
5727                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5728                 break;
5729         }
5730
5731         if (is_sdvo && is_tv)
5732                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5733         else if (is_tv)
5734                 /* XXX: just matching BIOS for now */
5735                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5736                 dpll |= 3;
5737         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5738                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5739         else
5740                 dpll |= PLL_REF_INPUT_DREFCLK;
5741
5742         return dpll;
5743 }
5744
5745 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5746                                   int x, int y,
5747                                   struct drm_framebuffer *fb)
5748 {
5749         struct drm_device *dev = crtc->dev;
5750         struct drm_i915_private *dev_priv = dev->dev_private;
5751         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5752         struct drm_display_mode *adjusted_mode =
5753                 &intel_crtc->config.adjusted_mode;
5754         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5755         int pipe = intel_crtc->pipe;
5756         int plane = intel_crtc->plane;
5757         int num_connectors = 0;
5758         intel_clock_t clock, reduced_clock;
5759         u32 dpll = 0, fp = 0, fp2 = 0;
5760         bool ok, has_reduced_clock = false;
5761         bool is_lvds = false;
5762         struct intel_encoder *encoder;
5763         int ret;
5764
5765         for_each_encoder_on_crtc(dev, crtc, encoder) {
5766                 switch (encoder->type) {
5767                 case INTEL_OUTPUT_LVDS:
5768                         is_lvds = true;
5769                         break;
5770                 }
5771
5772                 num_connectors++;
5773         }
5774
5775         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5776              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5777
5778         intel_crtc->config.cpu_transcoder = pipe;
5779
5780         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5781                                      &has_reduced_clock, &reduced_clock);
5782         if (!ok) {
5783                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5784                 return -EINVAL;
5785         }
5786         /* Compat-code for transition, will disappear. */
5787         if (!intel_crtc->config.clock_set) {
5788                 intel_crtc->config.dpll.n = clock.n;
5789                 intel_crtc->config.dpll.m1 = clock.m1;
5790                 intel_crtc->config.dpll.m2 = clock.m2;
5791                 intel_crtc->config.dpll.p1 = clock.p1;
5792                 intel_crtc->config.dpll.p2 = clock.p2;
5793         }
5794
5795         /* Ensure that the cursor is valid for the new mode before changing... */
5796         intel_crtc_update_cursor(crtc, true);
5797
5798         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5799         drm_mode_debug_printmodeline(mode);
5800
5801         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5802         if (intel_crtc->config.has_pch_encoder) {
5803                 struct intel_pch_pll *pll;
5804
5805                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5806                 if (has_reduced_clock)
5807                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5808
5809                 dpll = ironlake_compute_dpll(intel_crtc,
5810                                              &fp, &reduced_clock,
5811                                              has_reduced_clock ? &fp2 : NULL);
5812
5813                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5814                 if (pll == NULL) {
5815                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5816                                          pipe_name(pipe));
5817                         return -EINVAL;
5818                 }
5819         } else
5820                 intel_put_pch_pll(intel_crtc);
5821
5822         if (intel_crtc->config.has_dp_encoder)
5823                 intel_dp_set_m_n(intel_crtc);
5824
5825         for_each_encoder_on_crtc(dev, crtc, encoder)
5826                 if (encoder->pre_pll_enable)
5827                         encoder->pre_pll_enable(encoder);
5828
5829         if (intel_crtc->pch_pll) {
5830                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5831
5832                 /* Wait for the clocks to stabilize. */
5833                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5834                 udelay(150);
5835
5836                 /* The pixel multiplier can only be updated once the
5837                  * DPLL is enabled and the clocks are stable.
5838                  *
5839                  * So write it again.
5840                  */
5841                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5842         }
5843
5844         intel_crtc->lowfreq_avail = false;
5845         if (intel_crtc->pch_pll) {
5846                 if (is_lvds && has_reduced_clock && i915_powersave) {
5847                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5848                         intel_crtc->lowfreq_avail = true;
5849                 } else {
5850                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5851                 }
5852         }
5853
5854         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5855
5856         if (intel_crtc->config.has_pch_encoder) {
5857                 intel_cpu_transcoder_set_m_n(intel_crtc,
5858                                              &intel_crtc->config.fdi_m_n);
5859         }
5860
5861         if (IS_IVYBRIDGE(dev))
5862                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5863
5864         ironlake_set_pipeconf(crtc);
5865
5866         /* Set up the display plane register */
5867         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5868         POSTING_READ(DSPCNTR(plane));
5869
5870         ret = intel_pipe_set_base(crtc, x, y, fb);
5871
5872         intel_update_watermarks(dev);
5873
5874         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5875
5876         return ret;
5877 }
5878
5879 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5880                                         struct intel_crtc_config *pipe_config)
5881 {
5882         struct drm_device *dev = crtc->base.dev;
5883         struct drm_i915_private *dev_priv = dev->dev_private;
5884         enum transcoder transcoder = pipe_config->cpu_transcoder;
5885
5886         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5887         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5888         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5889                                         & ~TU_SIZE_MASK;
5890         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5891         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5892                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5893 }
5894
5895 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5896                                      struct intel_crtc_config *pipe_config)
5897 {
5898         struct drm_device *dev = crtc->base.dev;
5899         struct drm_i915_private *dev_priv = dev->dev_private;
5900         uint32_t tmp;
5901
5902         tmp = I915_READ(PIPECONF(crtc->pipe));
5903         if (!(tmp & PIPECONF_ENABLE))
5904                 return false;
5905
5906         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5907                 pipe_config->has_pch_encoder = true;
5908
5909                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5910                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5911                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5912
5913                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5914         }
5915
5916         intel_get_pipe_timings(crtc, pipe_config);
5917
5918         return true;
5919 }
5920
5921 static void haswell_modeset_global_resources(struct drm_device *dev)
5922 {
5923         bool enable = false;
5924         struct intel_crtc *crtc;
5925         struct intel_encoder *encoder;
5926
5927         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5928                 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5929                         enable = true;
5930                 /* XXX: Should check for edp transcoder here, but thanks to init
5931                  * sequence that's not yet available. Just in case desktop eDP
5932                  * on PORT D is possible on haswell, too. */
5933                 /* Even the eDP panel fitter is outside the always-on well. */
5934                 if (crtc->config.pch_pfit.size && crtc->base.enabled)
5935                         enable = true;
5936         }
5937
5938         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5939                             base.head) {
5940                 if (encoder->type != INTEL_OUTPUT_EDP &&
5941                     encoder->connectors_active)
5942                         enable = true;
5943         }
5944
5945         intel_set_power_well(dev, enable);
5946 }
5947
5948 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5949                                  int x, int y,
5950                                  struct drm_framebuffer *fb)
5951 {
5952         struct drm_device *dev = crtc->dev;
5953         struct drm_i915_private *dev_priv = dev->dev_private;
5954         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5955         struct drm_display_mode *adjusted_mode =
5956                 &intel_crtc->config.adjusted_mode;
5957         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5958         int pipe = intel_crtc->pipe;
5959         int plane = intel_crtc->plane;
5960         int num_connectors = 0;
5961         bool is_cpu_edp = false;
5962         struct intel_encoder *encoder;
5963         int ret;
5964
5965         for_each_encoder_on_crtc(dev, crtc, encoder) {
5966                 switch (encoder->type) {
5967                 case INTEL_OUTPUT_EDP:
5968                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5969                                 is_cpu_edp = true;
5970                         break;
5971                 }
5972
5973                 num_connectors++;
5974         }
5975
5976         if (is_cpu_edp)
5977                 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5978         else
5979                 intel_crtc->config.cpu_transcoder = pipe;
5980
5981         /* We are not sure yet this won't happen. */
5982         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5983              INTEL_PCH_TYPE(dev));
5984
5985         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5986              num_connectors, pipe_name(pipe));
5987
5988         WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5989                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5990
5991         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5992
5993         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5994                 return -EINVAL;
5995
5996         /* Ensure that the cursor is valid for the new mode before changing... */
5997         intel_crtc_update_cursor(crtc, true);
5998
5999         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
6000         drm_mode_debug_printmodeline(mode);
6001
6002         if (intel_crtc->config.has_dp_encoder)
6003                 intel_dp_set_m_n(intel_crtc);
6004
6005         intel_crtc->lowfreq_avail = false;
6006
6007         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
6008
6009         if (intel_crtc->config.has_pch_encoder) {
6010                 intel_cpu_transcoder_set_m_n(intel_crtc,
6011                                              &intel_crtc->config.fdi_m_n);
6012         }
6013
6014         haswell_set_pipeconf(crtc);
6015
6016         intel_set_pipe_csc(crtc);
6017
6018         /* Set up the display plane register */
6019         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6020         POSTING_READ(DSPCNTR(plane));
6021
6022         ret = intel_pipe_set_base(crtc, x, y, fb);
6023
6024         intel_update_watermarks(dev);
6025
6026         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
6027
6028         return ret;
6029 }
6030
6031 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6032                                     struct intel_crtc_config *pipe_config)
6033 {
6034         struct drm_device *dev = crtc->base.dev;
6035         struct drm_i915_private *dev_priv = dev->dev_private;
6036         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
6037         uint32_t tmp;
6038
6039         if (!intel_display_power_enabled(dev,
6040                         POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
6041                 return false;
6042
6043         tmp = I915_READ(PIPECONF(cpu_transcoder));
6044         if (!(tmp & PIPECONF_ENABLE))
6045                 return false;
6046
6047         /*
6048          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6049          * DDI E. So just check whether this pipe is wired to DDI E and whether
6050          * the PCH transcoder is on.
6051          */
6052         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
6053         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6054             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6055                 pipe_config->has_pch_encoder = true;
6056
6057                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6058                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6059                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6060
6061                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6062         }
6063
6064         intel_get_pipe_timings(crtc, pipe_config);
6065
6066         return true;
6067 }
6068
6069 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6070                                int x, int y,
6071                                struct drm_framebuffer *fb)
6072 {
6073         struct drm_device *dev = crtc->dev;
6074         struct drm_i915_private *dev_priv = dev->dev_private;
6075         struct drm_encoder_helper_funcs *encoder_funcs;
6076         struct intel_encoder *encoder;
6077         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6078         struct drm_display_mode *adjusted_mode =
6079                 &intel_crtc->config.adjusted_mode;
6080         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6081         int pipe = intel_crtc->pipe;
6082         int ret;
6083
6084         drm_vblank_pre_modeset(dev, pipe);
6085
6086         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6087
6088         drm_vblank_post_modeset(dev, pipe);
6089
6090         if (ret != 0)
6091                 return ret;
6092
6093         for_each_encoder_on_crtc(dev, crtc, encoder) {
6094                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6095                         encoder->base.base.id,
6096                         drm_get_encoder_name(&encoder->base),
6097                         mode->base.id, mode->name);
6098                 if (encoder->mode_set) {
6099                         encoder->mode_set(encoder);
6100                 } else {
6101                         encoder_funcs = encoder->base.helper_private;
6102                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6103                 }
6104         }
6105
6106         return 0;
6107 }
6108
6109 static bool intel_eld_uptodate(struct drm_connector *connector,
6110                                int reg_eldv, uint32_t bits_eldv,
6111                                int reg_elda, uint32_t bits_elda,
6112                                int reg_edid)
6113 {
6114         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6115         uint8_t *eld = connector->eld;
6116         uint32_t i;
6117
6118         i = I915_READ(reg_eldv);
6119         i &= bits_eldv;
6120
6121         if (!eld[0])
6122                 return !i;
6123
6124         if (!i)
6125                 return false;
6126
6127         i = I915_READ(reg_elda);
6128         i &= ~bits_elda;
6129         I915_WRITE(reg_elda, i);
6130
6131         for (i = 0; i < eld[2]; i++)
6132                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6133                         return false;
6134
6135         return true;
6136 }
6137
6138 static void g4x_write_eld(struct drm_connector *connector,
6139                           struct drm_crtc *crtc)
6140 {
6141         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6142         uint8_t *eld = connector->eld;
6143         uint32_t eldv;
6144         uint32_t len;
6145         uint32_t i;
6146
6147         i = I915_READ(G4X_AUD_VID_DID);
6148
6149         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6150                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6151         else
6152                 eldv = G4X_ELDV_DEVCTG;
6153
6154         if (intel_eld_uptodate(connector,
6155                                G4X_AUD_CNTL_ST, eldv,
6156                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6157                                G4X_HDMIW_HDMIEDID))
6158                 return;
6159
6160         i = I915_READ(G4X_AUD_CNTL_ST);
6161         i &= ~(eldv | G4X_ELD_ADDR);
6162         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6163         I915_WRITE(G4X_AUD_CNTL_ST, i);
6164
6165         if (!eld[0])
6166                 return;
6167
6168         len = min_t(uint8_t, eld[2], len);
6169         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6170         for (i = 0; i < len; i++)
6171                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6172
6173         i = I915_READ(G4X_AUD_CNTL_ST);
6174         i |= eldv;
6175         I915_WRITE(G4X_AUD_CNTL_ST, i);
6176 }
6177
6178 static void haswell_write_eld(struct drm_connector *connector,
6179                                      struct drm_crtc *crtc)
6180 {
6181         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6182         uint8_t *eld = connector->eld;
6183         struct drm_device *dev = crtc->dev;
6184         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6185         uint32_t eldv;
6186         uint32_t i;
6187         int len;
6188         int pipe = to_intel_crtc(crtc)->pipe;
6189         int tmp;
6190
6191         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6192         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6193         int aud_config = HSW_AUD_CFG(pipe);
6194         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6195
6196
6197         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6198
6199         /* Audio output enable */
6200         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6201         tmp = I915_READ(aud_cntrl_st2);
6202         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6203         I915_WRITE(aud_cntrl_st2, tmp);
6204
6205         /* Wait for 1 vertical blank */
6206         intel_wait_for_vblank(dev, pipe);
6207
6208         /* Set ELD valid state */
6209         tmp = I915_READ(aud_cntrl_st2);
6210         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6211         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6212         I915_WRITE(aud_cntrl_st2, tmp);
6213         tmp = I915_READ(aud_cntrl_st2);
6214         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6215
6216         /* Enable HDMI mode */
6217         tmp = I915_READ(aud_config);
6218         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6219         /* clear N_programing_enable and N_value_index */
6220         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6221         I915_WRITE(aud_config, tmp);
6222
6223         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6224
6225         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6226         intel_crtc->eld_vld = true;
6227
6228         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6229                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6230                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6231                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6232         } else
6233                 I915_WRITE(aud_config, 0);
6234
6235         if (intel_eld_uptodate(connector,
6236                                aud_cntrl_st2, eldv,
6237                                aud_cntl_st, IBX_ELD_ADDRESS,
6238                                hdmiw_hdmiedid))
6239                 return;
6240
6241         i = I915_READ(aud_cntrl_st2);
6242         i &= ~eldv;
6243         I915_WRITE(aud_cntrl_st2, i);
6244
6245         if (!eld[0])
6246                 return;
6247
6248         i = I915_READ(aud_cntl_st);
6249         i &= ~IBX_ELD_ADDRESS;
6250         I915_WRITE(aud_cntl_st, i);
6251         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6252         DRM_DEBUG_DRIVER("port num:%d\n", i);
6253
6254         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6255         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6256         for (i = 0; i < len; i++)
6257                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6258
6259         i = I915_READ(aud_cntrl_st2);
6260         i |= eldv;
6261         I915_WRITE(aud_cntrl_st2, i);
6262
6263 }
6264
6265 static void ironlake_write_eld(struct drm_connector *connector,
6266                                      struct drm_crtc *crtc)
6267 {
6268         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6269         uint8_t *eld = connector->eld;
6270         uint32_t eldv;
6271         uint32_t i;
6272         int len;
6273         int hdmiw_hdmiedid;
6274         int aud_config;
6275         int aud_cntl_st;
6276         int aud_cntrl_st2;
6277         int pipe = to_intel_crtc(crtc)->pipe;
6278
6279         if (HAS_PCH_IBX(connector->dev)) {
6280                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6281                 aud_config = IBX_AUD_CFG(pipe);
6282                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6283                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6284         } else {
6285                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6286                 aud_config = CPT_AUD_CFG(pipe);
6287                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6288                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6289         }
6290
6291         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6292
6293         i = I915_READ(aud_cntl_st);
6294         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6295         if (!i) {
6296                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6297                 /* operate blindly on all ports */
6298                 eldv = IBX_ELD_VALIDB;
6299                 eldv |= IBX_ELD_VALIDB << 4;
6300                 eldv |= IBX_ELD_VALIDB << 8;
6301         } else {
6302                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6303                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6304         }
6305
6306         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6307                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6308                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6309                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6310         } else
6311                 I915_WRITE(aud_config, 0);
6312
6313         if (intel_eld_uptodate(connector,
6314                                aud_cntrl_st2, eldv,
6315                                aud_cntl_st, IBX_ELD_ADDRESS,
6316                                hdmiw_hdmiedid))
6317                 return;
6318
6319         i = I915_READ(aud_cntrl_st2);
6320         i &= ~eldv;
6321         I915_WRITE(aud_cntrl_st2, i);
6322
6323         if (!eld[0])
6324                 return;
6325
6326         i = I915_READ(aud_cntl_st);
6327         i &= ~IBX_ELD_ADDRESS;
6328         I915_WRITE(aud_cntl_st, i);
6329
6330         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6331         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6332         for (i = 0; i < len; i++)
6333                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6334
6335         i = I915_READ(aud_cntrl_st2);
6336         i |= eldv;
6337         I915_WRITE(aud_cntrl_st2, i);
6338 }
6339
6340 void intel_write_eld(struct drm_encoder *encoder,
6341                      struct drm_display_mode *mode)
6342 {
6343         struct drm_crtc *crtc = encoder->crtc;
6344         struct drm_connector *connector;
6345         struct drm_device *dev = encoder->dev;
6346         struct drm_i915_private *dev_priv = dev->dev_private;
6347
6348         connector = drm_select_eld(encoder, mode);
6349         if (!connector)
6350                 return;
6351
6352         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6353                          connector->base.id,
6354                          drm_get_connector_name(connector),
6355                          connector->encoder->base.id,
6356                          drm_get_encoder_name(connector->encoder));
6357
6358         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6359
6360         if (dev_priv->display.write_eld)
6361                 dev_priv->display.write_eld(connector, crtc);
6362 }
6363
6364 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6365 void intel_crtc_load_lut(struct drm_crtc *crtc)
6366 {
6367         struct drm_device *dev = crtc->dev;
6368         struct drm_i915_private *dev_priv = dev->dev_private;
6369         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6370         int palreg = PALETTE(intel_crtc->pipe);
6371         int i;
6372
6373         /* The clocks have to be on to load the palette. */
6374         if (!crtc->enabled || !intel_crtc->active)
6375                 return;
6376
6377         /* use legacy palette for Ironlake */
6378         if (HAS_PCH_SPLIT(dev))
6379                 palreg = LGC_PALETTE(intel_crtc->pipe);
6380
6381         for (i = 0; i < 256; i++) {
6382                 I915_WRITE(palreg + 4 * i,
6383                            (intel_crtc->lut_r[i] << 16) |
6384                            (intel_crtc->lut_g[i] << 8) |
6385                            intel_crtc->lut_b[i]);
6386         }
6387 }
6388
6389 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6390 {
6391         struct drm_device *dev = crtc->dev;
6392         struct drm_i915_private *dev_priv = dev->dev_private;
6393         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6394         bool visible = base != 0;
6395         u32 cntl;
6396
6397         if (intel_crtc->cursor_visible == visible)
6398                 return;
6399
6400         cntl = I915_READ(_CURACNTR);
6401         if (visible) {
6402                 /* On these chipsets we can only modify the base whilst
6403                  * the cursor is disabled.
6404                  */
6405                 I915_WRITE(_CURABASE, base);
6406
6407                 cntl &= ~(CURSOR_FORMAT_MASK);
6408                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6409                 cntl |= CURSOR_ENABLE |
6410                         CURSOR_GAMMA_ENABLE |
6411                         CURSOR_FORMAT_ARGB;
6412         } else
6413                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6414         I915_WRITE(_CURACNTR, cntl);
6415
6416         intel_crtc->cursor_visible = visible;
6417 }
6418
6419 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6420 {
6421         struct drm_device *dev = crtc->dev;
6422         struct drm_i915_private *dev_priv = dev->dev_private;
6423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6424         int pipe = intel_crtc->pipe;
6425         bool visible = base != 0;
6426
6427         if (intel_crtc->cursor_visible != visible) {
6428                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6429                 if (base) {
6430                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6431                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6432                         cntl |= pipe << 28; /* Connect to correct pipe */
6433                 } else {
6434                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6435                         cntl |= CURSOR_MODE_DISABLE;
6436                 }
6437                 I915_WRITE(CURCNTR(pipe), cntl);
6438
6439                 intel_crtc->cursor_visible = visible;
6440         }
6441         /* and commit changes on next vblank */
6442         I915_WRITE(CURBASE(pipe), base);
6443 }
6444
6445 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6446 {
6447         struct drm_device *dev = crtc->dev;
6448         struct drm_i915_private *dev_priv = dev->dev_private;
6449         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6450         int pipe = intel_crtc->pipe;
6451         bool visible = base != 0;
6452
6453         if (intel_crtc->cursor_visible != visible) {
6454                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6455                 if (base) {
6456                         cntl &= ~CURSOR_MODE;
6457                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6458                 } else {
6459                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6460                         cntl |= CURSOR_MODE_DISABLE;
6461                 }
6462                 if (IS_HASWELL(dev))
6463                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6464                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6465
6466                 intel_crtc->cursor_visible = visible;
6467         }
6468         /* and commit changes on next vblank */
6469         I915_WRITE(CURBASE_IVB(pipe), base);
6470 }
6471
6472 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6473 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6474                                      bool on)
6475 {
6476         struct drm_device *dev = crtc->dev;
6477         struct drm_i915_private *dev_priv = dev->dev_private;
6478         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6479         int pipe = intel_crtc->pipe;
6480         int x = intel_crtc->cursor_x;
6481         int y = intel_crtc->cursor_y;
6482         u32 base, pos;
6483         bool visible;
6484
6485         pos = 0;
6486
6487         if (on && crtc->enabled && crtc->fb) {
6488                 base = intel_crtc->cursor_addr;
6489                 if (x > (int) crtc->fb->width)
6490                         base = 0;
6491
6492                 if (y > (int) crtc->fb->height)
6493                         base = 0;
6494         } else
6495                 base = 0;
6496
6497         if (x < 0) {
6498                 if (x + intel_crtc->cursor_width < 0)
6499                         base = 0;
6500
6501                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6502                 x = -x;
6503         }
6504         pos |= x << CURSOR_X_SHIFT;
6505
6506         if (y < 0) {
6507                 if (y + intel_crtc->cursor_height < 0)
6508                         base = 0;
6509
6510                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6511                 y = -y;
6512         }
6513         pos |= y << CURSOR_Y_SHIFT;
6514
6515         visible = base != 0;
6516         if (!visible && !intel_crtc->cursor_visible)
6517                 return;
6518
6519         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6520                 I915_WRITE(CURPOS_IVB(pipe), pos);
6521                 ivb_update_cursor(crtc, base);
6522         } else {
6523                 I915_WRITE(CURPOS(pipe), pos);
6524                 if (IS_845G(dev) || IS_I865G(dev))
6525                         i845_update_cursor(crtc, base);
6526                 else
6527                         i9xx_update_cursor(crtc, base);
6528         }
6529 }
6530
6531 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6532                                  struct drm_file *file,
6533                                  uint32_t handle,
6534                                  uint32_t width, uint32_t height)
6535 {
6536         struct drm_device *dev = crtc->dev;
6537         struct drm_i915_private *dev_priv = dev->dev_private;
6538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6539         struct drm_i915_gem_object *obj;
6540         uint32_t addr;
6541         int ret;
6542
6543         /* if we want to turn off the cursor ignore width and height */
6544         if (!handle) {
6545                 DRM_DEBUG_KMS("cursor off\n");
6546                 addr = 0;
6547                 obj = NULL;
6548                 mutex_lock(&dev->struct_mutex);
6549                 goto finish;
6550         }
6551
6552         /* Currently we only support 64x64 cursors */
6553         if (width != 64 || height != 64) {
6554                 DRM_ERROR("we currently only support 64x64 cursors\n");
6555                 return -EINVAL;
6556         }
6557
6558         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6559         if (&obj->base == NULL)
6560                 return -ENOENT;
6561
6562         if (obj->base.size < width * height * 4) {
6563                 DRM_ERROR("buffer is to small\n");
6564                 ret = -ENOMEM;
6565                 goto fail;
6566         }
6567
6568         /* we only need to pin inside GTT if cursor is non-phy */
6569         mutex_lock(&dev->struct_mutex);
6570         if (!dev_priv->info->cursor_needs_physical) {
6571                 unsigned alignment;
6572
6573                 if (obj->tiling_mode) {
6574                         DRM_ERROR("cursor cannot be tiled\n");
6575                         ret = -EINVAL;
6576                         goto fail_locked;
6577                 }
6578
6579                 /* Note that the w/a also requires 2 PTE of padding following
6580                  * the bo. We currently fill all unused PTE with the shadow
6581                  * page and so we should always have valid PTE following the
6582                  * cursor preventing the VT-d warning.
6583                  */
6584                 alignment = 0;
6585                 if (need_vtd_wa(dev))
6586                         alignment = 64*1024;
6587
6588                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6589                 if (ret) {
6590                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6591                         goto fail_locked;
6592                 }
6593
6594                 ret = i915_gem_object_put_fence(obj);
6595                 if (ret) {
6596                         DRM_ERROR("failed to release fence for cursor");
6597                         goto fail_unpin;
6598                 }
6599
6600                 addr = obj->gtt_offset;
6601         } else {
6602                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6603                 ret = i915_gem_attach_phys_object(dev, obj,
6604                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6605                                                   align);
6606                 if (ret) {
6607                         DRM_ERROR("failed to attach phys object\n");
6608                         goto fail_locked;
6609                 }
6610                 addr = obj->phys_obj->handle->busaddr;
6611         }
6612
6613         if (IS_GEN2(dev))
6614                 I915_WRITE(CURSIZE, (height << 12) | width);
6615
6616  finish:
6617         if (intel_crtc->cursor_bo) {
6618                 if (dev_priv->info->cursor_needs_physical) {
6619                         if (intel_crtc->cursor_bo != obj)
6620                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6621                 } else
6622                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6623                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6624         }
6625
6626         mutex_unlock(&dev->struct_mutex);
6627
6628         intel_crtc->cursor_addr = addr;
6629         intel_crtc->cursor_bo = obj;
6630         intel_crtc->cursor_width = width;
6631         intel_crtc->cursor_height = height;
6632
6633         intel_crtc_update_cursor(crtc, true);
6634
6635         return 0;
6636 fail_unpin:
6637         i915_gem_object_unpin(obj);
6638 fail_locked:
6639         mutex_unlock(&dev->struct_mutex);
6640 fail:
6641         drm_gem_object_unreference_unlocked(&obj->base);
6642         return ret;
6643 }
6644
6645 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6646 {
6647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6648
6649         intel_crtc->cursor_x = x;
6650         intel_crtc->cursor_y = y;
6651
6652         intel_crtc_update_cursor(crtc, true);
6653
6654         return 0;
6655 }
6656
6657 /** Sets the color ramps on behalf of RandR */
6658 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6659                                  u16 blue, int regno)
6660 {
6661         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6662
6663         intel_crtc->lut_r[regno] = red >> 8;
6664         intel_crtc->lut_g[regno] = green >> 8;
6665         intel_crtc->lut_b[regno] = blue >> 8;
6666 }
6667
6668 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6669                              u16 *blue, int regno)
6670 {
6671         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6672
6673         *red = intel_crtc->lut_r[regno] << 8;
6674         *green = intel_crtc->lut_g[regno] << 8;
6675         *blue = intel_crtc->lut_b[regno] << 8;
6676 }
6677
6678 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6679                                  u16 *blue, uint32_t start, uint32_t size)
6680 {
6681         int end = (start + size > 256) ? 256 : start + size, i;
6682         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6683
6684         for (i = start; i < end; i++) {
6685                 intel_crtc->lut_r[i] = red[i] >> 8;
6686                 intel_crtc->lut_g[i] = green[i] >> 8;
6687                 intel_crtc->lut_b[i] = blue[i] >> 8;
6688         }
6689
6690         intel_crtc_load_lut(crtc);
6691 }
6692
6693 /* VESA 640x480x72Hz mode to set on the pipe */
6694 static struct drm_display_mode load_detect_mode = {
6695         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6696                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6697 };
6698
6699 static struct drm_framebuffer *
6700 intel_framebuffer_create(struct drm_device *dev,
6701                          struct drm_mode_fb_cmd2 *mode_cmd,
6702                          struct drm_i915_gem_object *obj)
6703 {
6704         struct intel_framebuffer *intel_fb;
6705         int ret;
6706
6707         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6708         if (!intel_fb) {
6709                 drm_gem_object_unreference_unlocked(&obj->base);
6710                 return ERR_PTR(-ENOMEM);
6711         }
6712
6713         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6714         if (ret) {
6715                 drm_gem_object_unreference_unlocked(&obj->base);
6716                 kfree(intel_fb);
6717                 return ERR_PTR(ret);
6718         }
6719
6720         return &intel_fb->base;
6721 }
6722
6723 static u32
6724 intel_framebuffer_pitch_for_width(int width, int bpp)
6725 {
6726         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6727         return ALIGN(pitch, 64);
6728 }
6729
6730 static u32
6731 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6732 {
6733         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6734         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6735 }
6736
6737 static struct drm_framebuffer *
6738 intel_framebuffer_create_for_mode(struct drm_device *dev,
6739                                   struct drm_display_mode *mode,
6740                                   int depth, int bpp)
6741 {
6742         struct drm_i915_gem_object *obj;
6743         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6744
6745         obj = i915_gem_alloc_object(dev,
6746                                     intel_framebuffer_size_for_mode(mode, bpp));
6747         if (obj == NULL)
6748                 return ERR_PTR(-ENOMEM);
6749
6750         mode_cmd.width = mode->hdisplay;
6751         mode_cmd.height = mode->vdisplay;
6752         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6753                                                                 bpp);
6754         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6755
6756         return intel_framebuffer_create(dev, &mode_cmd, obj);
6757 }
6758
6759 static struct drm_framebuffer *
6760 mode_fits_in_fbdev(struct drm_device *dev,
6761                    struct drm_display_mode *mode)
6762 {
6763         struct drm_i915_private *dev_priv = dev->dev_private;
6764         struct drm_i915_gem_object *obj;
6765         struct drm_framebuffer *fb;
6766
6767         if (dev_priv->fbdev == NULL)
6768                 return NULL;
6769
6770         obj = dev_priv->fbdev->ifb.obj;
6771         if (obj == NULL)
6772                 return NULL;
6773
6774         fb = &dev_priv->fbdev->ifb.base;
6775         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6776                                                                fb->bits_per_pixel))
6777                 return NULL;
6778
6779         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6780                 return NULL;
6781
6782         return fb;
6783 }
6784
6785 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6786                                 struct drm_display_mode *mode,
6787                                 struct intel_load_detect_pipe *old)
6788 {
6789         struct intel_crtc *intel_crtc;
6790         struct intel_encoder *intel_encoder =
6791                 intel_attached_encoder(connector);
6792         struct drm_crtc *possible_crtc;
6793         struct drm_encoder *encoder = &intel_encoder->base;
6794         struct drm_crtc *crtc = NULL;
6795         struct drm_device *dev = encoder->dev;
6796         struct drm_framebuffer *fb;
6797         int i = -1;
6798
6799         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6800                       connector->base.id, drm_get_connector_name(connector),
6801                       encoder->base.id, drm_get_encoder_name(encoder));
6802
6803         /*
6804          * Algorithm gets a little messy:
6805          *
6806          *   - if the connector already has an assigned crtc, use it (but make
6807          *     sure it's on first)
6808          *
6809          *   - try to find the first unused crtc that can drive this connector,
6810          *     and use that if we find one
6811          */
6812
6813         /* See if we already have a CRTC for this connector */
6814         if (encoder->crtc) {
6815                 crtc = encoder->crtc;
6816
6817                 mutex_lock(&crtc->mutex);
6818
6819                 old->dpms_mode = connector->dpms;
6820                 old->load_detect_temp = false;
6821
6822                 /* Make sure the crtc and connector are running */
6823                 if (connector->dpms != DRM_MODE_DPMS_ON)
6824                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6825
6826                 return true;
6827         }
6828
6829         /* Find an unused one (if possible) */
6830         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6831                 i++;
6832                 if (!(encoder->possible_crtcs & (1 << i)))
6833                         continue;
6834                 if (!possible_crtc->enabled) {
6835                         crtc = possible_crtc;
6836                         break;
6837                 }
6838         }
6839
6840         /*
6841          * If we didn't find an unused CRTC, don't use any.
6842          */
6843         if (!crtc) {
6844                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6845                 return false;
6846         }
6847
6848         mutex_lock(&crtc->mutex);
6849         intel_encoder->new_crtc = to_intel_crtc(crtc);
6850         to_intel_connector(connector)->new_encoder = intel_encoder;
6851
6852         intel_crtc = to_intel_crtc(crtc);
6853         old->dpms_mode = connector->dpms;
6854         old->load_detect_temp = true;
6855         old->release_fb = NULL;
6856
6857         if (!mode)
6858                 mode = &load_detect_mode;
6859
6860         /* We need a framebuffer large enough to accommodate all accesses
6861          * that the plane may generate whilst we perform load detection.
6862          * We can not rely on the fbcon either being present (we get called
6863          * during its initialisation to detect all boot displays, or it may
6864          * not even exist) or that it is large enough to satisfy the
6865          * requested mode.
6866          */
6867         fb = mode_fits_in_fbdev(dev, mode);
6868         if (fb == NULL) {
6869                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6870                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6871                 old->release_fb = fb;
6872         } else
6873                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6874         if (IS_ERR(fb)) {
6875                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6876                 mutex_unlock(&crtc->mutex);
6877                 return false;
6878         }
6879
6880         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6881                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6882                 if (old->release_fb)
6883                         old->release_fb->funcs->destroy(old->release_fb);
6884                 mutex_unlock(&crtc->mutex);
6885                 return false;
6886         }
6887
6888         /* let the connector get through one full cycle before testing */
6889         intel_wait_for_vblank(dev, intel_crtc->pipe);
6890         return true;
6891 }
6892
6893 void intel_release_load_detect_pipe(struct drm_connector *connector,
6894                                     struct intel_load_detect_pipe *old)
6895 {
6896         struct intel_encoder *intel_encoder =
6897                 intel_attached_encoder(connector);
6898         struct drm_encoder *encoder = &intel_encoder->base;
6899         struct drm_crtc *crtc = encoder->crtc;
6900
6901         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6902                       connector->base.id, drm_get_connector_name(connector),
6903                       encoder->base.id, drm_get_encoder_name(encoder));
6904
6905         if (old->load_detect_temp) {
6906                 to_intel_connector(connector)->new_encoder = NULL;
6907                 intel_encoder->new_crtc = NULL;
6908                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6909
6910                 if (old->release_fb) {
6911                         drm_framebuffer_unregister_private(old->release_fb);
6912                         drm_framebuffer_unreference(old->release_fb);
6913                 }
6914
6915                 mutex_unlock(&crtc->mutex);
6916                 return;
6917         }
6918
6919         /* Switch crtc and encoder back off if necessary */
6920         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6921                 connector->funcs->dpms(connector, old->dpms_mode);
6922
6923         mutex_unlock(&crtc->mutex);
6924 }
6925
6926 /* Returns the clock of the currently programmed mode of the given pipe. */
6927 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6928 {
6929         struct drm_i915_private *dev_priv = dev->dev_private;
6930         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6931         int pipe = intel_crtc->pipe;
6932         u32 dpll = I915_READ(DPLL(pipe));
6933         u32 fp;
6934         intel_clock_t clock;
6935
6936         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6937                 fp = I915_READ(FP0(pipe));
6938         else
6939                 fp = I915_READ(FP1(pipe));
6940
6941         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6942         if (IS_PINEVIEW(dev)) {
6943                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6944                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6945         } else {
6946                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6947                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6948         }
6949
6950         if (!IS_GEN2(dev)) {
6951                 if (IS_PINEVIEW(dev))
6952                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6953                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6954                 else
6955                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6956                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6957
6958                 switch (dpll & DPLL_MODE_MASK) {
6959                 case DPLLB_MODE_DAC_SERIAL:
6960                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6961                                 5 : 10;
6962                         break;
6963                 case DPLLB_MODE_LVDS:
6964                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6965                                 7 : 14;
6966                         break;
6967                 default:
6968                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6969                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6970                         return 0;
6971                 }
6972
6973                 /* XXX: Handle the 100Mhz refclk */
6974                 intel_clock(dev, 96000, &clock);
6975         } else {
6976                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6977
6978                 if (is_lvds) {
6979                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6980                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6981                         clock.p2 = 14;
6982
6983                         if ((dpll & PLL_REF_INPUT_MASK) ==
6984                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6985                                 /* XXX: might not be 66MHz */
6986                                 intel_clock(dev, 66000, &clock);
6987                         } else
6988                                 intel_clock(dev, 48000, &clock);
6989                 } else {
6990                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6991                                 clock.p1 = 2;
6992                         else {
6993                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6994                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6995                         }
6996                         if (dpll & PLL_P2_DIVIDE_BY_4)
6997                                 clock.p2 = 4;
6998                         else
6999                                 clock.p2 = 2;
7000
7001                         intel_clock(dev, 48000, &clock);
7002                 }
7003         }
7004
7005         /* XXX: It would be nice to validate the clocks, but we can't reuse
7006          * i830PllIsValid() because it relies on the xf86_config connector
7007          * configuration being accurate, which it isn't necessarily.
7008          */
7009
7010         return clock.dot;
7011 }
7012
7013 /** Returns the currently programmed mode of the given pipe. */
7014 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7015                                              struct drm_crtc *crtc)
7016 {
7017         struct drm_i915_private *dev_priv = dev->dev_private;
7018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7019         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7020         struct drm_display_mode *mode;
7021         int htot = I915_READ(HTOTAL(cpu_transcoder));
7022         int hsync = I915_READ(HSYNC(cpu_transcoder));
7023         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7024         int vsync = I915_READ(VSYNC(cpu_transcoder));
7025
7026         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7027         if (!mode)
7028                 return NULL;
7029
7030         mode->clock = intel_crtc_clock_get(dev, crtc);
7031         mode->hdisplay = (htot & 0xffff) + 1;
7032         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7033         mode->hsync_start = (hsync & 0xffff) + 1;
7034         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7035         mode->vdisplay = (vtot & 0xffff) + 1;
7036         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7037         mode->vsync_start = (vsync & 0xffff) + 1;
7038         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7039
7040         drm_mode_set_name(mode);
7041
7042         return mode;
7043 }
7044
7045 static void intel_increase_pllclock(struct drm_crtc *crtc)
7046 {
7047         struct drm_device *dev = crtc->dev;
7048         drm_i915_private_t *dev_priv = dev->dev_private;
7049         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7050         int pipe = intel_crtc->pipe;
7051         int dpll_reg = DPLL(pipe);
7052         int dpll;
7053
7054         if (HAS_PCH_SPLIT(dev))
7055                 return;
7056
7057         if (!dev_priv->lvds_downclock_avail)
7058                 return;
7059
7060         dpll = I915_READ(dpll_reg);
7061         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7062                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7063
7064                 assert_panel_unlocked(dev_priv, pipe);
7065
7066                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7067                 I915_WRITE(dpll_reg, dpll);
7068                 intel_wait_for_vblank(dev, pipe);
7069
7070                 dpll = I915_READ(dpll_reg);
7071                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7072                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7073         }
7074 }
7075
7076 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7077 {
7078         struct drm_device *dev = crtc->dev;
7079         drm_i915_private_t *dev_priv = dev->dev_private;
7080         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7081
7082         if (HAS_PCH_SPLIT(dev))
7083                 return;
7084
7085         if (!dev_priv->lvds_downclock_avail)
7086                 return;
7087
7088         /*
7089          * Since this is called by a timer, we should never get here in
7090          * the manual case.
7091          */
7092         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7093                 int pipe = intel_crtc->pipe;
7094                 int dpll_reg = DPLL(pipe);
7095                 int dpll;
7096
7097                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7098
7099                 assert_panel_unlocked(dev_priv, pipe);
7100
7101                 dpll = I915_READ(dpll_reg);
7102                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7103                 I915_WRITE(dpll_reg, dpll);
7104                 intel_wait_for_vblank(dev, pipe);
7105                 dpll = I915_READ(dpll_reg);
7106                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7107                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7108         }
7109
7110 }
7111
7112 void intel_mark_busy(struct drm_device *dev)
7113 {
7114         i915_update_gfx_val(dev->dev_private);
7115 }
7116
7117 void intel_mark_idle(struct drm_device *dev)
7118 {
7119         struct drm_crtc *crtc;
7120
7121         if (!i915_powersave)
7122                 return;
7123
7124         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7125                 if (!crtc->fb)
7126                         continue;
7127
7128                 intel_decrease_pllclock(crtc);
7129         }
7130 }
7131
7132 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7133 {
7134         struct drm_device *dev = obj->base.dev;
7135         struct drm_crtc *crtc;
7136
7137         if (!i915_powersave)
7138                 return;
7139
7140         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7141                 if (!crtc->fb)
7142                         continue;
7143
7144                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7145                         intel_increase_pllclock(crtc);
7146         }
7147 }
7148
7149 static void intel_crtc_destroy(struct drm_crtc *crtc)
7150 {
7151         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7152         struct drm_device *dev = crtc->dev;
7153         struct intel_unpin_work *work;
7154         unsigned long flags;
7155
7156         spin_lock_irqsave(&dev->event_lock, flags);
7157         work = intel_crtc->unpin_work;
7158         intel_crtc->unpin_work = NULL;
7159         spin_unlock_irqrestore(&dev->event_lock, flags);
7160
7161         if (work) {
7162                 cancel_work_sync(&work->work);
7163                 kfree(work);
7164         }
7165
7166         drm_crtc_cleanup(crtc);
7167
7168         kfree(intel_crtc);
7169 }
7170
7171 static void intel_unpin_work_fn(struct work_struct *__work)
7172 {
7173         struct intel_unpin_work *work =
7174                 container_of(__work, struct intel_unpin_work, work);
7175         struct drm_device *dev = work->crtc->dev;
7176
7177         mutex_lock(&dev->struct_mutex);
7178         intel_unpin_fb_obj(work->old_fb_obj);
7179         drm_gem_object_unreference(&work->pending_flip_obj->base);
7180         drm_gem_object_unreference(&work->old_fb_obj->base);
7181
7182         intel_update_fbc(dev);
7183         mutex_unlock(&dev->struct_mutex);
7184
7185         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7186         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7187
7188         kfree(work);
7189 }
7190
7191 static void do_intel_finish_page_flip(struct drm_device *dev,
7192                                       struct drm_crtc *crtc)
7193 {
7194         drm_i915_private_t *dev_priv = dev->dev_private;
7195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7196         struct intel_unpin_work *work;
7197         unsigned long flags;
7198
7199         /* Ignore early vblank irqs */
7200         if (intel_crtc == NULL)
7201                 return;
7202
7203         spin_lock_irqsave(&dev->event_lock, flags);
7204         work = intel_crtc->unpin_work;
7205
7206         /* Ensure we don't miss a work->pending update ... */
7207         smp_rmb();
7208
7209         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7210                 spin_unlock_irqrestore(&dev->event_lock, flags);
7211                 return;
7212         }
7213
7214         /* and that the unpin work is consistent wrt ->pending. */
7215         smp_rmb();
7216
7217         intel_crtc->unpin_work = NULL;
7218
7219         if (work->event)
7220                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7221
7222         drm_vblank_put(dev, intel_crtc->pipe);
7223
7224         spin_unlock_irqrestore(&dev->event_lock, flags);
7225
7226         wake_up_all(&dev_priv->pending_flip_queue);
7227
7228         queue_work(dev_priv->wq, &work->work);
7229
7230         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7231 }
7232
7233 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7234 {
7235         drm_i915_private_t *dev_priv = dev->dev_private;
7236         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7237
7238         do_intel_finish_page_flip(dev, crtc);
7239 }
7240
7241 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7242 {
7243         drm_i915_private_t *dev_priv = dev->dev_private;
7244         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7245
7246         do_intel_finish_page_flip(dev, crtc);
7247 }
7248
7249 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7250 {
7251         drm_i915_private_t *dev_priv = dev->dev_private;
7252         struct intel_crtc *intel_crtc =
7253                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7254         unsigned long flags;
7255
7256         /* NB: An MMIO update of the plane base pointer will also
7257          * generate a page-flip completion irq, i.e. every modeset
7258          * is also accompanied by a spurious intel_prepare_page_flip().
7259          */
7260         spin_lock_irqsave(&dev->event_lock, flags);
7261         if (intel_crtc->unpin_work)
7262                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7263         spin_unlock_irqrestore(&dev->event_lock, flags);
7264 }
7265
7266 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7267 {
7268         /* Ensure that the work item is consistent when activating it ... */
7269         smp_wmb();
7270         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7271         /* and that it is marked active as soon as the irq could fire. */
7272         smp_wmb();
7273 }
7274
7275 static int intel_gen2_queue_flip(struct drm_device *dev,
7276                                  struct drm_crtc *crtc,
7277                                  struct drm_framebuffer *fb,
7278                                  struct drm_i915_gem_object *obj)
7279 {
7280         struct drm_i915_private *dev_priv = dev->dev_private;
7281         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7282         u32 flip_mask;
7283         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7284         int ret;
7285
7286         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7287         if (ret)
7288                 goto err;
7289
7290         ret = intel_ring_begin(ring, 6);
7291         if (ret)
7292                 goto err_unpin;
7293
7294         /* Can't queue multiple flips, so wait for the previous
7295          * one to finish before executing the next.
7296          */
7297         if (intel_crtc->plane)
7298                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7299         else
7300                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7301         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7302         intel_ring_emit(ring, MI_NOOP);
7303         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7304                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7305         intel_ring_emit(ring, fb->pitches[0]);
7306         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7307         intel_ring_emit(ring, 0); /* aux display base address, unused */
7308
7309         intel_mark_page_flip_active(intel_crtc);
7310         intel_ring_advance(ring);
7311         return 0;
7312
7313 err_unpin:
7314         intel_unpin_fb_obj(obj);
7315 err:
7316         return ret;
7317 }
7318
7319 static int intel_gen3_queue_flip(struct drm_device *dev,
7320                                  struct drm_crtc *crtc,
7321                                  struct drm_framebuffer *fb,
7322                                  struct drm_i915_gem_object *obj)
7323 {
7324         struct drm_i915_private *dev_priv = dev->dev_private;
7325         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7326         u32 flip_mask;
7327         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7328         int ret;
7329
7330         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7331         if (ret)
7332                 goto err;
7333
7334         ret = intel_ring_begin(ring, 6);
7335         if (ret)
7336                 goto err_unpin;
7337
7338         if (intel_crtc->plane)
7339                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7340         else
7341                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7342         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7343         intel_ring_emit(ring, MI_NOOP);
7344         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7345                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7346         intel_ring_emit(ring, fb->pitches[0]);
7347         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7348         intel_ring_emit(ring, MI_NOOP);
7349
7350         intel_mark_page_flip_active(intel_crtc);
7351         intel_ring_advance(ring);
7352         return 0;
7353
7354 err_unpin:
7355         intel_unpin_fb_obj(obj);
7356 err:
7357         return ret;
7358 }
7359
7360 static int intel_gen4_queue_flip(struct drm_device *dev,
7361                                  struct drm_crtc *crtc,
7362                                  struct drm_framebuffer *fb,
7363                                  struct drm_i915_gem_object *obj)
7364 {
7365         struct drm_i915_private *dev_priv = dev->dev_private;
7366         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7367         uint32_t pf, pipesrc;
7368         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7369         int ret;
7370
7371         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7372         if (ret)
7373                 goto err;
7374
7375         ret = intel_ring_begin(ring, 4);
7376         if (ret)
7377                 goto err_unpin;
7378
7379         /* i965+ uses the linear or tiled offsets from the
7380          * Display Registers (which do not change across a page-flip)
7381          * so we need only reprogram the base address.
7382          */
7383         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7384                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7385         intel_ring_emit(ring, fb->pitches[0]);
7386         intel_ring_emit(ring,
7387                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7388                         obj->tiling_mode);
7389
7390         /* XXX Enabling the panel-fitter across page-flip is so far
7391          * untested on non-native modes, so ignore it for now.
7392          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7393          */
7394         pf = 0;
7395         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7396         intel_ring_emit(ring, pf | pipesrc);
7397
7398         intel_mark_page_flip_active(intel_crtc);
7399         intel_ring_advance(ring);
7400         return 0;
7401
7402 err_unpin:
7403         intel_unpin_fb_obj(obj);
7404 err:
7405         return ret;
7406 }
7407
7408 static int intel_gen6_queue_flip(struct drm_device *dev,
7409                                  struct drm_crtc *crtc,
7410                                  struct drm_framebuffer *fb,
7411                                  struct drm_i915_gem_object *obj)
7412 {
7413         struct drm_i915_private *dev_priv = dev->dev_private;
7414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7415         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7416         uint32_t pf, pipesrc;
7417         int ret;
7418
7419         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7420         if (ret)
7421                 goto err;
7422
7423         ret = intel_ring_begin(ring, 4);
7424         if (ret)
7425                 goto err_unpin;
7426
7427         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7428                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7429         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7430         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7431
7432         /* Contrary to the suggestions in the documentation,
7433          * "Enable Panel Fitter" does not seem to be required when page
7434          * flipping with a non-native mode, and worse causes a normal
7435          * modeset to fail.
7436          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7437          */
7438         pf = 0;
7439         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7440         intel_ring_emit(ring, pf | pipesrc);
7441
7442         intel_mark_page_flip_active(intel_crtc);
7443         intel_ring_advance(ring);
7444         return 0;
7445
7446 err_unpin:
7447         intel_unpin_fb_obj(obj);
7448 err:
7449         return ret;
7450 }
7451
7452 /*
7453  * On gen7 we currently use the blit ring because (in early silicon at least)
7454  * the render ring doesn't give us interrpts for page flip completion, which
7455  * means clients will hang after the first flip is queued.  Fortunately the
7456  * blit ring generates interrupts properly, so use it instead.
7457  */
7458 static int intel_gen7_queue_flip(struct drm_device *dev,
7459                                  struct drm_crtc *crtc,
7460                                  struct drm_framebuffer *fb,
7461                                  struct drm_i915_gem_object *obj)
7462 {
7463         struct drm_i915_private *dev_priv = dev->dev_private;
7464         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7465         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7466         uint32_t plane_bit = 0;
7467         int ret;
7468
7469         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7470         if (ret)
7471                 goto err;
7472
7473         switch(intel_crtc->plane) {
7474         case PLANE_A:
7475                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7476                 break;
7477         case PLANE_B:
7478                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7479                 break;
7480         case PLANE_C:
7481                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7482                 break;
7483         default:
7484                 WARN_ONCE(1, "unknown plane in flip command\n");
7485                 ret = -ENODEV;
7486                 goto err_unpin;
7487         }
7488
7489         ret = intel_ring_begin(ring, 4);
7490         if (ret)
7491                 goto err_unpin;
7492
7493         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7494         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7495         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7496         intel_ring_emit(ring, (MI_NOOP));
7497
7498         intel_mark_page_flip_active(intel_crtc);
7499         intel_ring_advance(ring);
7500         return 0;
7501
7502 err_unpin:
7503         intel_unpin_fb_obj(obj);
7504 err:
7505         return ret;
7506 }
7507
7508 static int intel_default_queue_flip(struct drm_device *dev,
7509                                     struct drm_crtc *crtc,
7510                                     struct drm_framebuffer *fb,
7511                                     struct drm_i915_gem_object *obj)
7512 {
7513         return -ENODEV;
7514 }
7515
7516 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7517                                 struct drm_framebuffer *fb,
7518                                 struct drm_pending_vblank_event *event)
7519 {
7520         struct drm_device *dev = crtc->dev;
7521         struct drm_i915_private *dev_priv = dev->dev_private;
7522         struct drm_framebuffer *old_fb = crtc->fb;
7523         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7524         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7525         struct intel_unpin_work *work;
7526         unsigned long flags;
7527         int ret;
7528
7529         /* Can't change pixel format via MI display flips. */
7530         if (fb->pixel_format != crtc->fb->pixel_format)
7531                 return -EINVAL;
7532
7533         /*
7534          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7535          * Note that pitch changes could also affect these register.
7536          */
7537         if (INTEL_INFO(dev)->gen > 3 &&
7538             (fb->offsets[0] != crtc->fb->offsets[0] ||
7539              fb->pitches[0] != crtc->fb->pitches[0]))
7540                 return -EINVAL;
7541
7542         work = kzalloc(sizeof *work, GFP_KERNEL);
7543         if (work == NULL)
7544                 return -ENOMEM;
7545
7546         work->event = event;
7547         work->crtc = crtc;
7548         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7549         INIT_WORK(&work->work, intel_unpin_work_fn);
7550
7551         ret = drm_vblank_get(dev, intel_crtc->pipe);
7552         if (ret)
7553                 goto free_work;
7554
7555         /* We borrow the event spin lock for protecting unpin_work */
7556         spin_lock_irqsave(&dev->event_lock, flags);
7557         if (intel_crtc->unpin_work) {
7558                 spin_unlock_irqrestore(&dev->event_lock, flags);
7559                 kfree(work);
7560                 drm_vblank_put(dev, intel_crtc->pipe);
7561
7562                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7563                 return -EBUSY;
7564         }
7565         intel_crtc->unpin_work = work;
7566         spin_unlock_irqrestore(&dev->event_lock, flags);
7567
7568         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7569                 flush_workqueue(dev_priv->wq);
7570
7571         ret = i915_mutex_lock_interruptible(dev);
7572         if (ret)
7573                 goto cleanup;
7574
7575         /* Reference the objects for the scheduled work. */
7576         drm_gem_object_reference(&work->old_fb_obj->base);
7577         drm_gem_object_reference(&obj->base);
7578
7579         crtc->fb = fb;
7580
7581         work->pending_flip_obj = obj;
7582
7583         work->enable_stall_check = true;
7584
7585         atomic_inc(&intel_crtc->unpin_work_count);
7586         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7587
7588         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7589         if (ret)
7590                 goto cleanup_pending;
7591
7592         intel_disable_fbc(dev);
7593         intel_mark_fb_busy(obj);
7594         mutex_unlock(&dev->struct_mutex);
7595
7596         trace_i915_flip_request(intel_crtc->plane, obj);
7597
7598         return 0;
7599
7600 cleanup_pending:
7601         atomic_dec(&intel_crtc->unpin_work_count);
7602         crtc->fb = old_fb;
7603         drm_gem_object_unreference(&work->old_fb_obj->base);
7604         drm_gem_object_unreference(&obj->base);
7605         mutex_unlock(&dev->struct_mutex);
7606
7607 cleanup:
7608         spin_lock_irqsave(&dev->event_lock, flags);
7609         intel_crtc->unpin_work = NULL;
7610         spin_unlock_irqrestore(&dev->event_lock, flags);
7611
7612         drm_vblank_put(dev, intel_crtc->pipe);
7613 free_work:
7614         kfree(work);
7615
7616         return ret;
7617 }
7618
7619 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7620         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7621         .load_lut = intel_crtc_load_lut,
7622 };
7623
7624 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7625 {
7626         struct intel_encoder *other_encoder;
7627         struct drm_crtc *crtc = &encoder->new_crtc->base;
7628
7629         if (WARN_ON(!crtc))
7630                 return false;
7631
7632         list_for_each_entry(other_encoder,
7633                             &crtc->dev->mode_config.encoder_list,
7634                             base.head) {
7635
7636                 if (&other_encoder->new_crtc->base != crtc ||
7637                     encoder == other_encoder)
7638                         continue;
7639                 else
7640                         return true;
7641         }
7642
7643         return false;
7644 }
7645
7646 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7647                                   struct drm_crtc *crtc)
7648 {
7649         struct drm_device *dev;
7650         struct drm_crtc *tmp;
7651         int crtc_mask = 1;
7652
7653         WARN(!crtc, "checking null crtc?\n");
7654
7655         dev = crtc->dev;
7656
7657         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7658                 if (tmp == crtc)
7659                         break;
7660                 crtc_mask <<= 1;
7661         }
7662
7663         if (encoder->possible_crtcs & crtc_mask)
7664                 return true;
7665         return false;
7666 }
7667
7668 /**
7669  * intel_modeset_update_staged_output_state
7670  *
7671  * Updates the staged output configuration state, e.g. after we've read out the
7672  * current hw state.
7673  */
7674 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7675 {
7676         struct intel_encoder *encoder;
7677         struct intel_connector *connector;
7678
7679         list_for_each_entry(connector, &dev->mode_config.connector_list,
7680                             base.head) {
7681                 connector->new_encoder =
7682                         to_intel_encoder(connector->base.encoder);
7683         }
7684
7685         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7686                             base.head) {
7687                 encoder->new_crtc =
7688                         to_intel_crtc(encoder->base.crtc);
7689         }
7690 }
7691
7692 /**
7693  * intel_modeset_commit_output_state
7694  *
7695  * This function copies the stage display pipe configuration to the real one.
7696  */
7697 static void intel_modeset_commit_output_state(struct drm_device *dev)
7698 {
7699         struct intel_encoder *encoder;
7700         struct intel_connector *connector;
7701
7702         list_for_each_entry(connector, &dev->mode_config.connector_list,
7703                             base.head) {
7704                 connector->base.encoder = &connector->new_encoder->base;
7705         }
7706
7707         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7708                             base.head) {
7709                 encoder->base.crtc = &encoder->new_crtc->base;
7710         }
7711 }
7712
7713 static int
7714 pipe_config_set_bpp(struct drm_crtc *crtc,
7715                     struct drm_framebuffer *fb,
7716                     struct intel_crtc_config *pipe_config)
7717 {
7718         struct drm_device *dev = crtc->dev;
7719         struct drm_connector *connector;
7720         int bpp;
7721
7722         switch (fb->pixel_format) {
7723         case DRM_FORMAT_C8:
7724                 bpp = 8*3; /* since we go through a colormap */
7725                 break;
7726         case DRM_FORMAT_XRGB1555:
7727         case DRM_FORMAT_ARGB1555:
7728                 /* checked in intel_framebuffer_init already */
7729                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7730                         return -EINVAL;
7731         case DRM_FORMAT_RGB565:
7732                 bpp = 6*3; /* min is 18bpp */
7733                 break;
7734         case DRM_FORMAT_XBGR8888:
7735         case DRM_FORMAT_ABGR8888:
7736                 /* checked in intel_framebuffer_init already */
7737                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7738                         return -EINVAL;
7739         case DRM_FORMAT_XRGB8888:
7740         case DRM_FORMAT_ARGB8888:
7741                 bpp = 8*3;
7742                 break;
7743         case DRM_FORMAT_XRGB2101010:
7744         case DRM_FORMAT_ARGB2101010:
7745         case DRM_FORMAT_XBGR2101010:
7746         case DRM_FORMAT_ABGR2101010:
7747                 /* checked in intel_framebuffer_init already */
7748                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7749                         return -EINVAL;
7750                 bpp = 10*3;
7751                 break;
7752         /* TODO: gen4+ supports 16 bpc floating point, too. */
7753         default:
7754                 DRM_DEBUG_KMS("unsupported depth\n");
7755                 return -EINVAL;
7756         }
7757
7758         pipe_config->pipe_bpp = bpp;
7759
7760         /* Clamp display bpp to EDID value */
7761         list_for_each_entry(connector, &dev->mode_config.connector_list,
7762                             head) {
7763                 if (connector->encoder && connector->encoder->crtc != crtc)
7764                         continue;
7765
7766                 /* Don't use an invalid EDID bpc value */
7767                 if (connector->display_info.bpc &&
7768                     connector->display_info.bpc * 3 < bpp) {
7769                         DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7770                                       bpp, connector->display_info.bpc*3);
7771                         pipe_config->pipe_bpp = connector->display_info.bpc*3;
7772                 }
7773
7774                 /* Clamp bpp to 8 on screens without EDID 1.4 */
7775                 if (connector->display_info.bpc == 0 && bpp > 24) {
7776                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7777                                       bpp);
7778                         pipe_config->pipe_bpp = 24;
7779                 }
7780         }
7781
7782         return bpp;
7783 }
7784
7785 static struct intel_crtc_config *
7786 intel_modeset_pipe_config(struct drm_crtc *crtc,
7787                           struct drm_framebuffer *fb,
7788                           struct drm_display_mode *mode)
7789 {
7790         struct drm_device *dev = crtc->dev;
7791         struct drm_encoder_helper_funcs *encoder_funcs;
7792         struct intel_encoder *encoder;
7793         struct intel_crtc_config *pipe_config;
7794         int plane_bpp, ret = -EINVAL;
7795         bool retry = true;
7796
7797         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7798         if (!pipe_config)
7799                 return ERR_PTR(-ENOMEM);
7800
7801         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7802         drm_mode_copy(&pipe_config->requested_mode, mode);
7803
7804         plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7805         if (plane_bpp < 0)
7806                 goto fail;
7807
7808 encoder_retry:
7809         /* Pass our mode to the connectors and the CRTC to give them a chance to
7810          * adjust it according to limitations or connector properties, and also
7811          * a chance to reject the mode entirely.
7812          */
7813         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7814                             base.head) {
7815
7816                 if (&encoder->new_crtc->base != crtc)
7817                         continue;
7818
7819                 if (encoder->compute_config) {
7820                         if (!(encoder->compute_config(encoder, pipe_config))) {
7821                                 DRM_DEBUG_KMS("Encoder config failure\n");
7822                                 goto fail;
7823                         }
7824
7825                         continue;
7826                 }
7827
7828                 encoder_funcs = encoder->base.helper_private;
7829                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7830                                                 &pipe_config->requested_mode,
7831                                                 &pipe_config->adjusted_mode))) {
7832                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7833                         goto fail;
7834                 }
7835         }
7836
7837         ret = intel_crtc_compute_config(crtc, pipe_config);
7838         if (ret < 0) {
7839                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7840                 goto fail;
7841         }
7842
7843         if (ret == RETRY) {
7844                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7845                         ret = -EINVAL;
7846                         goto fail;
7847                 }
7848
7849                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7850                 retry = false;
7851                 goto encoder_retry;
7852         }
7853
7854         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7855
7856         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7857         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7858                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7859
7860         return pipe_config;
7861 fail:
7862         kfree(pipe_config);
7863         return ERR_PTR(ret);
7864 }
7865
7866 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7867  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7868 static void
7869 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7870                              unsigned *prepare_pipes, unsigned *disable_pipes)
7871 {
7872         struct intel_crtc *intel_crtc;
7873         struct drm_device *dev = crtc->dev;
7874         struct intel_encoder *encoder;
7875         struct intel_connector *connector;
7876         struct drm_crtc *tmp_crtc;
7877
7878         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7879
7880         /* Check which crtcs have changed outputs connected to them, these need
7881          * to be part of the prepare_pipes mask. We don't (yet) support global
7882          * modeset across multiple crtcs, so modeset_pipes will only have one
7883          * bit set at most. */
7884         list_for_each_entry(connector, &dev->mode_config.connector_list,
7885                             base.head) {
7886                 if (connector->base.encoder == &connector->new_encoder->base)
7887                         continue;
7888
7889                 if (connector->base.encoder) {
7890                         tmp_crtc = connector->base.encoder->crtc;
7891
7892                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7893                 }
7894
7895                 if (connector->new_encoder)
7896                         *prepare_pipes |=
7897                                 1 << connector->new_encoder->new_crtc->pipe;
7898         }
7899
7900         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7901                             base.head) {
7902                 if (encoder->base.crtc == &encoder->new_crtc->base)
7903                         continue;
7904
7905                 if (encoder->base.crtc) {
7906                         tmp_crtc = encoder->base.crtc;
7907
7908                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7909                 }
7910
7911                 if (encoder->new_crtc)
7912                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7913         }
7914
7915         /* Check for any pipes that will be fully disabled ... */
7916         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7917                             base.head) {
7918                 bool used = false;
7919
7920                 /* Don't try to disable disabled crtcs. */
7921                 if (!intel_crtc->base.enabled)
7922                         continue;
7923
7924                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7925                                     base.head) {
7926                         if (encoder->new_crtc == intel_crtc)
7927                                 used = true;
7928                 }
7929
7930                 if (!used)
7931                         *disable_pipes |= 1 << intel_crtc->pipe;
7932         }
7933
7934
7935         /* set_mode is also used to update properties on life display pipes. */
7936         intel_crtc = to_intel_crtc(crtc);
7937         if (crtc->enabled)
7938                 *prepare_pipes |= 1 << intel_crtc->pipe;
7939
7940         /*
7941          * For simplicity do a full modeset on any pipe where the output routing
7942          * changed. We could be more clever, but that would require us to be
7943          * more careful with calling the relevant encoder->mode_set functions.
7944          */
7945         if (*prepare_pipes)
7946                 *modeset_pipes = *prepare_pipes;
7947
7948         /* ... and mask these out. */
7949         *modeset_pipes &= ~(*disable_pipes);
7950         *prepare_pipes &= ~(*disable_pipes);
7951
7952         /*
7953          * HACK: We don't (yet) fully support global modesets. intel_set_config
7954          * obies this rule, but the modeset restore mode of
7955          * intel_modeset_setup_hw_state does not.
7956          */
7957         *modeset_pipes &= 1 << intel_crtc->pipe;
7958         *prepare_pipes &= 1 << intel_crtc->pipe;
7959
7960         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7961                       *modeset_pipes, *prepare_pipes, *disable_pipes);
7962 }
7963
7964 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7965 {
7966         struct drm_encoder *encoder;
7967         struct drm_device *dev = crtc->dev;
7968
7969         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7970                 if (encoder->crtc == crtc)
7971                         return true;
7972
7973         return false;
7974 }
7975
7976 static void
7977 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7978 {
7979         struct intel_encoder *intel_encoder;
7980         struct intel_crtc *intel_crtc;
7981         struct drm_connector *connector;
7982
7983         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7984                             base.head) {
7985                 if (!intel_encoder->base.crtc)
7986                         continue;
7987
7988                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7989
7990                 if (prepare_pipes & (1 << intel_crtc->pipe))
7991                         intel_encoder->connectors_active = false;
7992         }
7993
7994         intel_modeset_commit_output_state(dev);
7995
7996         /* Update computed state. */
7997         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7998                             base.head) {
7999                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8000         }
8001
8002         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8003                 if (!connector->encoder || !connector->encoder->crtc)
8004                         continue;
8005
8006                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8007
8008                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8009                         struct drm_property *dpms_property =
8010                                 dev->mode_config.dpms_property;
8011
8012                         connector->dpms = DRM_MODE_DPMS_ON;
8013                         drm_object_property_set_value(&connector->base,
8014                                                          dpms_property,
8015                                                          DRM_MODE_DPMS_ON);
8016
8017                         intel_encoder = to_intel_encoder(connector->encoder);
8018                         intel_encoder->connectors_active = true;
8019                 }
8020         }
8021
8022 }
8023
8024 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8025         list_for_each_entry((intel_crtc), \
8026                             &(dev)->mode_config.crtc_list, \
8027                             base.head) \
8028                 if (mask & (1 <<(intel_crtc)->pipe))
8029
8030 static bool
8031 intel_pipe_config_compare(struct intel_crtc_config *current_config,
8032                           struct intel_crtc_config *pipe_config)
8033 {
8034 #define PIPE_CONF_CHECK_I(name) \
8035         if (current_config->name != pipe_config->name) { \
8036                 DRM_ERROR("mismatch in " #name " " \
8037                           "(expected %i, found %i)\n", \
8038                           current_config->name, \
8039                           pipe_config->name); \
8040                 return false; \
8041         }
8042
8043 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8044         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8045                 DRM_ERROR("mismatch in " #name " " \
8046                           "(expected %i, found %i)\n", \
8047                           current_config->name & (mask), \
8048                           pipe_config->name & (mask)); \
8049                 return false; \
8050         }
8051
8052         PIPE_CONF_CHECK_I(has_pch_encoder);
8053         PIPE_CONF_CHECK_I(fdi_lanes);
8054         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8055         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8056         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8057         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8058         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8059
8060         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8061         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8062         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8063         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8064         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8065         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8066
8067         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8068         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8069         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8070         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8071         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8072         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8073
8074         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8075                               DRM_MODE_FLAG_INTERLACE);
8076
8077         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8078         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8079
8080 #undef PIPE_CONF_CHECK_I
8081 #undef PIPE_CONF_CHECK_FLAGS
8082
8083         return true;
8084 }
8085
8086 void
8087 intel_modeset_check_state(struct drm_device *dev)
8088 {
8089         drm_i915_private_t *dev_priv = dev->dev_private;
8090         struct intel_crtc *crtc;
8091         struct intel_encoder *encoder;
8092         struct intel_connector *connector;
8093         struct intel_crtc_config pipe_config;
8094
8095         list_for_each_entry(connector, &dev->mode_config.connector_list,
8096                             base.head) {
8097                 /* This also checks the encoder/connector hw state with the
8098                  * ->get_hw_state callbacks. */
8099                 intel_connector_check_state(connector);
8100
8101                 WARN(&connector->new_encoder->base != connector->base.encoder,
8102                      "connector's staged encoder doesn't match current encoder\n");
8103         }
8104
8105         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8106                             base.head) {
8107                 bool enabled = false;
8108                 bool active = false;
8109                 enum pipe pipe, tracked_pipe;
8110
8111                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8112                               encoder->base.base.id,
8113                               drm_get_encoder_name(&encoder->base));
8114
8115                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8116                      "encoder's stage crtc doesn't match current crtc\n");
8117                 WARN(encoder->connectors_active && !encoder->base.crtc,
8118                      "encoder's active_connectors set, but no crtc\n");
8119
8120                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8121                                     base.head) {
8122                         if (connector->base.encoder != &encoder->base)
8123                                 continue;
8124                         enabled = true;
8125                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8126                                 active = true;
8127                 }
8128                 WARN(!!encoder->base.crtc != enabled,
8129                      "encoder's enabled state mismatch "
8130                      "(expected %i, found %i)\n",
8131                      !!encoder->base.crtc, enabled);
8132                 WARN(active && !encoder->base.crtc,
8133                      "active encoder with no crtc\n");
8134
8135                 WARN(encoder->connectors_active != active,
8136                      "encoder's computed active state doesn't match tracked active state "
8137                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8138
8139                 active = encoder->get_hw_state(encoder, &pipe);
8140                 WARN(active != encoder->connectors_active,
8141                      "encoder's hw state doesn't match sw tracking "
8142                      "(expected %i, found %i)\n",
8143                      encoder->connectors_active, active);
8144
8145                 if (!encoder->base.crtc)
8146                         continue;
8147
8148                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8149                 WARN(active && pipe != tracked_pipe,
8150                      "active encoder's pipe doesn't match"
8151                      "(expected %i, found %i)\n",
8152                      tracked_pipe, pipe);
8153
8154         }
8155
8156         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8157                             base.head) {
8158                 bool enabled = false;
8159                 bool active = false;
8160
8161                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8162                               crtc->base.base.id);
8163
8164                 WARN(crtc->active && !crtc->base.enabled,
8165                      "active crtc, but not enabled in sw tracking\n");
8166
8167                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8168                                     base.head) {
8169                         if (encoder->base.crtc != &crtc->base)
8170                                 continue;
8171                         enabled = true;
8172                         if (encoder->connectors_active)
8173                                 active = true;
8174                 }
8175                 WARN(active != crtc->active,
8176                      "crtc's computed active state doesn't match tracked active state "
8177                      "(expected %i, found %i)\n", active, crtc->active);
8178                 WARN(enabled != crtc->base.enabled,
8179                      "crtc's computed enabled state doesn't match tracked enabled state "
8180                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8181
8182                 memset(&pipe_config, 0, sizeof(pipe_config));
8183                 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
8184                 active = dev_priv->display.get_pipe_config(crtc,
8185                                                            &pipe_config);
8186                 WARN(crtc->active != active,
8187                      "crtc active state doesn't match with hw state "
8188                      "(expected %i, found %i)\n", crtc->active, active);
8189
8190                 WARN(active &&
8191                      !intel_pipe_config_compare(&crtc->config, &pipe_config),
8192                      "pipe state doesn't match!\n");
8193         }
8194 }
8195
8196 static int __intel_set_mode(struct drm_crtc *crtc,
8197                             struct drm_display_mode *mode,
8198                             int x, int y, struct drm_framebuffer *fb)
8199 {
8200         struct drm_device *dev = crtc->dev;
8201         drm_i915_private_t *dev_priv = dev->dev_private;
8202         struct drm_display_mode *saved_mode, *saved_hwmode;
8203         struct intel_crtc_config *pipe_config = NULL;
8204         struct intel_crtc *intel_crtc;
8205         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8206         int ret = 0;
8207
8208         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8209         if (!saved_mode)
8210                 return -ENOMEM;
8211         saved_hwmode = saved_mode + 1;
8212
8213         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8214                                      &prepare_pipes, &disable_pipes);
8215
8216         *saved_hwmode = crtc->hwmode;
8217         *saved_mode = crtc->mode;
8218
8219         /* Hack: Because we don't (yet) support global modeset on multiple
8220          * crtcs, we don't keep track of the new mode for more than one crtc.
8221          * Hence simply check whether any bit is set in modeset_pipes in all the
8222          * pieces of code that are not yet converted to deal with mutliple crtcs
8223          * changing their mode at the same time. */
8224         if (modeset_pipes) {
8225                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8226                 if (IS_ERR(pipe_config)) {
8227                         ret = PTR_ERR(pipe_config);
8228                         pipe_config = NULL;
8229
8230                         goto out;
8231                 }
8232         }
8233
8234         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8235                 intel_crtc_disable(&intel_crtc->base);
8236
8237         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8238                 if (intel_crtc->base.enabled)
8239                         dev_priv->display.crtc_disable(&intel_crtc->base);
8240         }
8241
8242         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8243          * to set it here already despite that we pass it down the callchain.
8244          */
8245         if (modeset_pipes) {
8246                 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
8247                 crtc->mode = *mode;
8248                 /* mode_set/enable/disable functions rely on a correct pipe
8249                  * config. */
8250                 to_intel_crtc(crtc)->config = *pipe_config;
8251                 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8252         }
8253
8254         /* Only after disabling all output pipelines that will be changed can we
8255          * update the the output configuration. */
8256         intel_modeset_update_state(dev, prepare_pipes);
8257
8258         if (dev_priv->display.modeset_global_resources)
8259                 dev_priv->display.modeset_global_resources(dev);
8260
8261         /* Set up the DPLL and any encoders state that needs to adjust or depend
8262          * on the DPLL.
8263          */
8264         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8265                 ret = intel_crtc_mode_set(&intel_crtc->base,
8266                                           x, y, fb);
8267                 if (ret)
8268                         goto done;
8269         }
8270
8271         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8272         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8273                 dev_priv->display.crtc_enable(&intel_crtc->base);
8274
8275         if (modeset_pipes) {
8276                 /* Store real post-adjustment hardware mode. */
8277                 crtc->hwmode = pipe_config->adjusted_mode;
8278
8279                 /* Calculate and store various constants which
8280                  * are later needed by vblank and swap-completion
8281                  * timestamping. They are derived from true hwmode.
8282                  */
8283                 drm_calc_timestamping_constants(crtc);
8284         }
8285
8286         /* FIXME: add subpixel order */
8287 done:
8288         if (ret && crtc->enabled) {
8289                 crtc->hwmode = *saved_hwmode;
8290                 crtc->mode = *saved_mode;
8291         }
8292
8293 out:
8294         kfree(pipe_config);
8295         kfree(saved_mode);
8296         return ret;
8297 }
8298
8299 int intel_set_mode(struct drm_crtc *crtc,
8300                      struct drm_display_mode *mode,
8301                      int x, int y, struct drm_framebuffer *fb)
8302 {
8303         int ret;
8304
8305         ret = __intel_set_mode(crtc, mode, x, y, fb);
8306
8307         if (ret == 0)
8308                 intel_modeset_check_state(crtc->dev);
8309
8310         return ret;
8311 }
8312
8313 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8314 {
8315         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8316 }
8317
8318 #undef for_each_intel_crtc_masked
8319
8320 static void intel_set_config_free(struct intel_set_config *config)
8321 {
8322         if (!config)
8323                 return;
8324
8325         kfree(config->save_connector_encoders);
8326         kfree(config->save_encoder_crtcs);
8327         kfree(config);
8328 }
8329
8330 static int intel_set_config_save_state(struct drm_device *dev,
8331                                        struct intel_set_config *config)
8332 {
8333         struct drm_encoder *encoder;
8334         struct drm_connector *connector;
8335         int count;
8336
8337         config->save_encoder_crtcs =
8338                 kcalloc(dev->mode_config.num_encoder,
8339                         sizeof(struct drm_crtc *), GFP_KERNEL);
8340         if (!config->save_encoder_crtcs)
8341                 return -ENOMEM;
8342
8343         config->save_connector_encoders =
8344                 kcalloc(dev->mode_config.num_connector,
8345                         sizeof(struct drm_encoder *), GFP_KERNEL);
8346         if (!config->save_connector_encoders)
8347                 return -ENOMEM;
8348
8349         /* Copy data. Note that driver private data is not affected.
8350          * Should anything bad happen only the expected state is
8351          * restored, not the drivers personal bookkeeping.
8352          */
8353         count = 0;
8354         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8355                 config->save_encoder_crtcs[count++] = encoder->crtc;
8356         }
8357
8358         count = 0;
8359         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8360                 config->save_connector_encoders[count++] = connector->encoder;
8361         }
8362
8363         return 0;
8364 }
8365
8366 static void intel_set_config_restore_state(struct drm_device *dev,
8367                                            struct intel_set_config *config)
8368 {
8369         struct intel_encoder *encoder;
8370         struct intel_connector *connector;
8371         int count;
8372
8373         count = 0;
8374         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8375                 encoder->new_crtc =
8376                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8377         }
8378
8379         count = 0;
8380         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8381                 connector->new_encoder =
8382                         to_intel_encoder(config->save_connector_encoders[count++]);
8383         }
8384 }
8385
8386 static void
8387 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8388                                       struct intel_set_config *config)
8389 {
8390
8391         /* We should be able to check here if the fb has the same properties
8392          * and then just flip_or_move it */
8393         if (set->crtc->fb != set->fb) {
8394                 /* If we have no fb then treat it as a full mode set */
8395                 if (set->crtc->fb == NULL) {
8396                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8397                         config->mode_changed = true;
8398                 } else if (set->fb == NULL) {
8399                         config->mode_changed = true;
8400                 } else if (set->fb->pixel_format !=
8401                            set->crtc->fb->pixel_format) {
8402                         config->mode_changed = true;
8403                 } else
8404                         config->fb_changed = true;
8405         }
8406
8407         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8408                 config->fb_changed = true;
8409
8410         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8411                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8412                 drm_mode_debug_printmodeline(&set->crtc->mode);
8413                 drm_mode_debug_printmodeline(set->mode);
8414                 config->mode_changed = true;
8415         }
8416 }
8417
8418 static int
8419 intel_modeset_stage_output_state(struct drm_device *dev,
8420                                  struct drm_mode_set *set,
8421                                  struct intel_set_config *config)
8422 {
8423         struct drm_crtc *new_crtc;
8424         struct intel_connector *connector;
8425         struct intel_encoder *encoder;
8426         int count, ro;
8427
8428         /* The upper layers ensure that we either disable a crtc or have a list
8429          * of connectors. For paranoia, double-check this. */
8430         WARN_ON(!set->fb && (set->num_connectors != 0));
8431         WARN_ON(set->fb && (set->num_connectors == 0));
8432
8433         count = 0;
8434         list_for_each_entry(connector, &dev->mode_config.connector_list,
8435                             base.head) {
8436                 /* Otherwise traverse passed in connector list and get encoders
8437                  * for them. */
8438                 for (ro = 0; ro < set->num_connectors; ro++) {
8439                         if (set->connectors[ro] == &connector->base) {
8440                                 connector->new_encoder = connector->encoder;
8441                                 break;
8442                         }
8443                 }
8444
8445                 /* If we disable the crtc, disable all its connectors. Also, if
8446                  * the connector is on the changing crtc but not on the new
8447                  * connector list, disable it. */
8448                 if ((!set->fb || ro == set->num_connectors) &&
8449                     connector->base.encoder &&
8450                     connector->base.encoder->crtc == set->crtc) {
8451                         connector->new_encoder = NULL;
8452
8453                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8454                                 connector->base.base.id,
8455                                 drm_get_connector_name(&connector->base));
8456                 }
8457
8458
8459                 if (&connector->new_encoder->base != connector->base.encoder) {
8460                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8461                         config->mode_changed = true;
8462                 }
8463         }
8464         /* connector->new_encoder is now updated for all connectors. */
8465
8466         /* Update crtc of enabled connectors. */
8467         count = 0;
8468         list_for_each_entry(connector, &dev->mode_config.connector_list,
8469                             base.head) {
8470                 if (!connector->new_encoder)
8471                         continue;
8472
8473                 new_crtc = connector->new_encoder->base.crtc;
8474
8475                 for (ro = 0; ro < set->num_connectors; ro++) {
8476                         if (set->connectors[ro] == &connector->base)
8477                                 new_crtc = set->crtc;
8478                 }
8479
8480                 /* Make sure the new CRTC will work with the encoder */
8481                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8482                                            new_crtc)) {
8483                         return -EINVAL;
8484                 }
8485                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8486
8487                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8488                         connector->base.base.id,
8489                         drm_get_connector_name(&connector->base),
8490                         new_crtc->base.id);
8491         }
8492
8493         /* Check for any encoders that needs to be disabled. */
8494         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8495                             base.head) {
8496                 list_for_each_entry(connector,
8497                                     &dev->mode_config.connector_list,
8498                                     base.head) {
8499                         if (connector->new_encoder == encoder) {
8500                                 WARN_ON(!connector->new_encoder->new_crtc);
8501
8502                                 goto next_encoder;
8503                         }
8504                 }
8505                 encoder->new_crtc = NULL;
8506 next_encoder:
8507                 /* Only now check for crtc changes so we don't miss encoders
8508                  * that will be disabled. */
8509                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8510                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8511                         config->mode_changed = true;
8512                 }
8513         }
8514         /* Now we've also updated encoder->new_crtc for all encoders. */
8515
8516         return 0;
8517 }
8518
8519 static int intel_crtc_set_config(struct drm_mode_set *set)
8520 {
8521         struct drm_device *dev;
8522         struct drm_mode_set save_set;
8523         struct intel_set_config *config;
8524         int ret;
8525
8526         BUG_ON(!set);
8527         BUG_ON(!set->crtc);
8528         BUG_ON(!set->crtc->helper_private);
8529
8530         /* Enforce sane interface api - has been abused by the fb helper. */
8531         BUG_ON(!set->mode && set->fb);
8532         BUG_ON(set->fb && set->num_connectors == 0);
8533
8534         if (set->fb) {
8535                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8536                                 set->crtc->base.id, set->fb->base.id,
8537                                 (int)set->num_connectors, set->x, set->y);
8538         } else {
8539                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8540         }
8541
8542         dev = set->crtc->dev;
8543
8544         ret = -ENOMEM;
8545         config = kzalloc(sizeof(*config), GFP_KERNEL);
8546         if (!config)
8547                 goto out_config;
8548
8549         ret = intel_set_config_save_state(dev, config);
8550         if (ret)
8551                 goto out_config;
8552
8553         save_set.crtc = set->crtc;
8554         save_set.mode = &set->crtc->mode;
8555         save_set.x = set->crtc->x;
8556         save_set.y = set->crtc->y;
8557         save_set.fb = set->crtc->fb;
8558
8559         /* Compute whether we need a full modeset, only an fb base update or no
8560          * change at all. In the future we might also check whether only the
8561          * mode changed, e.g. for LVDS where we only change the panel fitter in
8562          * such cases. */
8563         intel_set_config_compute_mode_changes(set, config);
8564
8565         ret = intel_modeset_stage_output_state(dev, set, config);
8566         if (ret)
8567                 goto fail;
8568
8569         if (config->mode_changed) {
8570                 if (set->mode) {
8571                         DRM_DEBUG_KMS("attempting to set mode from"
8572                                         " userspace\n");
8573                         drm_mode_debug_printmodeline(set->mode);
8574                 }
8575
8576                 ret = intel_set_mode(set->crtc, set->mode,
8577                                      set->x, set->y, set->fb);
8578                 if (ret) {
8579                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8580                                   set->crtc->base.id, ret);
8581                         goto fail;
8582                 }
8583         } else if (config->fb_changed) {
8584                 intel_crtc_wait_for_pending_flips(set->crtc);
8585
8586                 ret = intel_pipe_set_base(set->crtc,
8587                                           set->x, set->y, set->fb);
8588         }
8589
8590         intel_set_config_free(config);
8591
8592         return 0;
8593
8594 fail:
8595         intel_set_config_restore_state(dev, config);
8596
8597         /* Try to restore the config */
8598         if (config->mode_changed &&
8599             intel_set_mode(save_set.crtc, save_set.mode,
8600                            save_set.x, save_set.y, save_set.fb))
8601                 DRM_ERROR("failed to restore config after modeset failure\n");
8602
8603 out_config:
8604         intel_set_config_free(config);
8605         return ret;
8606 }
8607
8608 static const struct drm_crtc_funcs intel_crtc_funcs = {
8609         .cursor_set = intel_crtc_cursor_set,
8610         .cursor_move = intel_crtc_cursor_move,
8611         .gamma_set = intel_crtc_gamma_set,
8612         .set_config = intel_crtc_set_config,
8613         .destroy = intel_crtc_destroy,
8614         .page_flip = intel_crtc_page_flip,
8615 };
8616
8617 static void intel_cpu_pll_init(struct drm_device *dev)
8618 {
8619         if (HAS_DDI(dev))
8620                 intel_ddi_pll_init(dev);
8621 }
8622
8623 static void intel_pch_pll_init(struct drm_device *dev)
8624 {
8625         drm_i915_private_t *dev_priv = dev->dev_private;
8626         int i;
8627
8628         if (dev_priv->num_pch_pll == 0) {
8629                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8630                 return;
8631         }
8632
8633         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8634                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8635                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8636                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8637         }
8638 }
8639
8640 static void intel_crtc_init(struct drm_device *dev, int pipe)
8641 {
8642         drm_i915_private_t *dev_priv = dev->dev_private;
8643         struct intel_crtc *intel_crtc;
8644         int i;
8645
8646         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8647         if (intel_crtc == NULL)
8648                 return;
8649
8650         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8651
8652         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8653         for (i = 0; i < 256; i++) {
8654                 intel_crtc->lut_r[i] = i;
8655                 intel_crtc->lut_g[i] = i;
8656                 intel_crtc->lut_b[i] = i;
8657         }
8658
8659         /* Swap pipes & planes for FBC on pre-965 */
8660         intel_crtc->pipe = pipe;
8661         intel_crtc->plane = pipe;
8662         intel_crtc->config.cpu_transcoder = pipe;
8663         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8664                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8665                 intel_crtc->plane = !pipe;
8666         }
8667
8668         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8669                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8670         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8671         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8672
8673         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8674 }
8675
8676 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8677                                 struct drm_file *file)
8678 {
8679         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8680         struct drm_mode_object *drmmode_obj;
8681         struct intel_crtc *crtc;
8682
8683         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8684                 return -ENODEV;
8685
8686         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8687                         DRM_MODE_OBJECT_CRTC);
8688
8689         if (!drmmode_obj) {
8690                 DRM_ERROR("no such CRTC id\n");
8691                 return -EINVAL;
8692         }
8693
8694         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8695         pipe_from_crtc_id->pipe = crtc->pipe;
8696
8697         return 0;
8698 }
8699
8700 static int intel_encoder_clones(struct intel_encoder *encoder)
8701 {
8702         struct drm_device *dev = encoder->base.dev;
8703         struct intel_encoder *source_encoder;
8704         int index_mask = 0;
8705         int entry = 0;
8706
8707         list_for_each_entry(source_encoder,
8708                             &dev->mode_config.encoder_list, base.head) {
8709
8710                 if (encoder == source_encoder)
8711                         index_mask |= (1 << entry);
8712
8713                 /* Intel hw has only one MUX where enocoders could be cloned. */
8714                 if (encoder->cloneable && source_encoder->cloneable)
8715                         index_mask |= (1 << entry);
8716
8717                 entry++;
8718         }
8719
8720         return index_mask;
8721 }
8722
8723 static bool has_edp_a(struct drm_device *dev)
8724 {
8725         struct drm_i915_private *dev_priv = dev->dev_private;
8726
8727         if (!IS_MOBILE(dev))
8728                 return false;
8729
8730         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8731                 return false;
8732
8733         if (IS_GEN5(dev) &&
8734             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8735                 return false;
8736
8737         return true;
8738 }
8739
8740 static void intel_setup_outputs(struct drm_device *dev)
8741 {
8742         struct drm_i915_private *dev_priv = dev->dev_private;
8743         struct intel_encoder *encoder;
8744         bool dpd_is_edp = false;
8745         bool has_lvds;
8746
8747         has_lvds = intel_lvds_init(dev);
8748         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8749                 /* disable the panel fitter on everything but LVDS */
8750                 I915_WRITE(PFIT_CONTROL, 0);
8751         }
8752
8753         if (!IS_ULT(dev))
8754                 intel_crt_init(dev);
8755
8756         if (HAS_DDI(dev)) {
8757                 int found;
8758
8759                 /* Haswell uses DDI functions to detect digital outputs */
8760                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8761                 /* DDI A only supports eDP */
8762                 if (found)
8763                         intel_ddi_init(dev, PORT_A);
8764
8765                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8766                  * register */
8767                 found = I915_READ(SFUSE_STRAP);
8768
8769                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8770                         intel_ddi_init(dev, PORT_B);
8771                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8772                         intel_ddi_init(dev, PORT_C);
8773                 if (found & SFUSE_STRAP_DDID_DETECTED)
8774                         intel_ddi_init(dev, PORT_D);
8775         } else if (HAS_PCH_SPLIT(dev)) {
8776                 int found;
8777                 dpd_is_edp = intel_dpd_is_edp(dev);
8778
8779                 if (has_edp_a(dev))
8780                         intel_dp_init(dev, DP_A, PORT_A);
8781
8782                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8783                         /* PCH SDVOB multiplex with HDMIB */
8784                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8785                         if (!found)
8786                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8787                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8788                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8789                 }
8790
8791                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8792                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8793
8794                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8795                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8796
8797                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8798                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8799
8800                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8801                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8802         } else if (IS_VALLEYVIEW(dev)) {
8803                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8804                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8805                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8806
8807                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8808                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8809                                         PORT_B);
8810                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8811                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8812                 }
8813         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8814                 bool found = false;
8815
8816                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8817                         DRM_DEBUG_KMS("probing SDVOB\n");
8818                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8819                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8820                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8821                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8822                         }
8823
8824                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8825                                 DRM_DEBUG_KMS("probing DP_B\n");
8826                                 intel_dp_init(dev, DP_B, PORT_B);
8827                         }
8828                 }
8829
8830                 /* Before G4X SDVOC doesn't have its own detect register */
8831
8832                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8833                         DRM_DEBUG_KMS("probing SDVOC\n");
8834                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8835                 }
8836
8837                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8838
8839                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8840                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8841                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8842                         }
8843                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8844                                 DRM_DEBUG_KMS("probing DP_C\n");
8845                                 intel_dp_init(dev, DP_C, PORT_C);
8846                         }
8847                 }
8848
8849                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8850                     (I915_READ(DP_D) & DP_DETECTED)) {
8851                         DRM_DEBUG_KMS("probing DP_D\n");
8852                         intel_dp_init(dev, DP_D, PORT_D);
8853                 }
8854         } else if (IS_GEN2(dev))
8855                 intel_dvo_init(dev);
8856
8857         if (SUPPORTS_TV(dev))
8858                 intel_tv_init(dev);
8859
8860         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8861                 encoder->base.possible_crtcs = encoder->crtc_mask;
8862                 encoder->base.possible_clones =
8863                         intel_encoder_clones(encoder);
8864         }
8865
8866         intel_init_pch_refclk(dev);
8867
8868         drm_helper_move_panel_connectors_to_head(dev);
8869 }
8870
8871 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8872 {
8873         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8874
8875         drm_framebuffer_cleanup(fb);
8876         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8877
8878         kfree(intel_fb);
8879 }
8880
8881 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8882                                                 struct drm_file *file,
8883                                                 unsigned int *handle)
8884 {
8885         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8886         struct drm_i915_gem_object *obj = intel_fb->obj;
8887
8888         return drm_gem_handle_create(file, &obj->base, handle);
8889 }
8890
8891 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8892         .destroy = intel_user_framebuffer_destroy,
8893         .create_handle = intel_user_framebuffer_create_handle,
8894 };
8895
8896 int intel_framebuffer_init(struct drm_device *dev,
8897                            struct intel_framebuffer *intel_fb,
8898                            struct drm_mode_fb_cmd2 *mode_cmd,
8899                            struct drm_i915_gem_object *obj)
8900 {
8901         int ret;
8902
8903         if (obj->tiling_mode == I915_TILING_Y) {
8904                 DRM_DEBUG("hardware does not support tiling Y\n");
8905                 return -EINVAL;
8906         }
8907
8908         if (mode_cmd->pitches[0] & 63) {
8909                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8910                           mode_cmd->pitches[0]);
8911                 return -EINVAL;
8912         }
8913
8914         /* FIXME <= Gen4 stride limits are bit unclear */
8915         if (mode_cmd->pitches[0] > 32768) {
8916                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8917                           mode_cmd->pitches[0]);
8918                 return -EINVAL;
8919         }
8920
8921         if (obj->tiling_mode != I915_TILING_NONE &&
8922             mode_cmd->pitches[0] != obj->stride) {
8923                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8924                           mode_cmd->pitches[0], obj->stride);
8925                 return -EINVAL;
8926         }
8927
8928         /* Reject formats not supported by any plane early. */
8929         switch (mode_cmd->pixel_format) {
8930         case DRM_FORMAT_C8:
8931         case DRM_FORMAT_RGB565:
8932         case DRM_FORMAT_XRGB8888:
8933         case DRM_FORMAT_ARGB8888:
8934                 break;
8935         case DRM_FORMAT_XRGB1555:
8936         case DRM_FORMAT_ARGB1555:
8937                 if (INTEL_INFO(dev)->gen > 3) {
8938                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8939                         return -EINVAL;
8940                 }
8941                 break;
8942         case DRM_FORMAT_XBGR8888:
8943         case DRM_FORMAT_ABGR8888:
8944         case DRM_FORMAT_XRGB2101010:
8945         case DRM_FORMAT_ARGB2101010:
8946         case DRM_FORMAT_XBGR2101010:
8947         case DRM_FORMAT_ABGR2101010:
8948                 if (INTEL_INFO(dev)->gen < 4) {
8949                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8950                         return -EINVAL;
8951                 }
8952                 break;
8953         case DRM_FORMAT_YUYV:
8954         case DRM_FORMAT_UYVY:
8955         case DRM_FORMAT_YVYU:
8956         case DRM_FORMAT_VYUY:
8957                 if (INTEL_INFO(dev)->gen < 5) {
8958                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8959                         return -EINVAL;
8960                 }
8961                 break;
8962         default:
8963                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8964                 return -EINVAL;
8965         }
8966
8967         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8968         if (mode_cmd->offsets[0] != 0)
8969                 return -EINVAL;
8970
8971         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8972         intel_fb->obj = obj;
8973
8974         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8975         if (ret) {
8976                 DRM_ERROR("framebuffer init failed %d\n", ret);
8977                 return ret;
8978         }
8979
8980         return 0;
8981 }
8982
8983 static struct drm_framebuffer *
8984 intel_user_framebuffer_create(struct drm_device *dev,
8985                               struct drm_file *filp,
8986                               struct drm_mode_fb_cmd2 *mode_cmd)
8987 {
8988         struct drm_i915_gem_object *obj;
8989
8990         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8991                                                 mode_cmd->handles[0]));
8992         if (&obj->base == NULL)
8993                 return ERR_PTR(-ENOENT);
8994
8995         return intel_framebuffer_create(dev, mode_cmd, obj);
8996 }
8997
8998 static const struct drm_mode_config_funcs intel_mode_funcs = {
8999         .fb_create = intel_user_framebuffer_create,
9000         .output_poll_changed = intel_fb_output_poll_changed,
9001 };
9002
9003 /* Set up chip specific display functions */
9004 static void intel_init_display(struct drm_device *dev)
9005 {
9006         struct drm_i915_private *dev_priv = dev->dev_private;
9007
9008         if (HAS_DDI(dev)) {
9009                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9010                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9011                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9012                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9013                 dev_priv->display.off = haswell_crtc_off;
9014                 dev_priv->display.update_plane = ironlake_update_plane;
9015         } else if (HAS_PCH_SPLIT(dev)) {
9016                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9017                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9018                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9019                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9020                 dev_priv->display.off = ironlake_crtc_off;
9021                 dev_priv->display.update_plane = ironlake_update_plane;
9022         } else if (IS_VALLEYVIEW(dev)) {
9023                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9024                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9025                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9026                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9027                 dev_priv->display.off = i9xx_crtc_off;
9028                 dev_priv->display.update_plane = i9xx_update_plane;
9029         } else {
9030                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9031                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9032                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9033                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9034                 dev_priv->display.off = i9xx_crtc_off;
9035                 dev_priv->display.update_plane = i9xx_update_plane;
9036         }
9037
9038         /* Returns the core display clock speed */
9039         if (IS_VALLEYVIEW(dev))
9040                 dev_priv->display.get_display_clock_speed =
9041                         valleyview_get_display_clock_speed;
9042         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9043                 dev_priv->display.get_display_clock_speed =
9044                         i945_get_display_clock_speed;
9045         else if (IS_I915G(dev))
9046                 dev_priv->display.get_display_clock_speed =
9047                         i915_get_display_clock_speed;
9048         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9049                 dev_priv->display.get_display_clock_speed =
9050                         i9xx_misc_get_display_clock_speed;
9051         else if (IS_I915GM(dev))
9052                 dev_priv->display.get_display_clock_speed =
9053                         i915gm_get_display_clock_speed;
9054         else if (IS_I865G(dev))
9055                 dev_priv->display.get_display_clock_speed =
9056                         i865_get_display_clock_speed;
9057         else if (IS_I85X(dev))
9058                 dev_priv->display.get_display_clock_speed =
9059                         i855_get_display_clock_speed;
9060         else /* 852, 830 */
9061                 dev_priv->display.get_display_clock_speed =
9062                         i830_get_display_clock_speed;
9063
9064         if (HAS_PCH_SPLIT(dev)) {
9065                 if (IS_GEN5(dev)) {
9066                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9067                         dev_priv->display.write_eld = ironlake_write_eld;
9068                 } else if (IS_GEN6(dev)) {
9069                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9070                         dev_priv->display.write_eld = ironlake_write_eld;
9071                 } else if (IS_IVYBRIDGE(dev)) {
9072                         /* FIXME: detect B0+ stepping and use auto training */
9073                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9074                         dev_priv->display.write_eld = ironlake_write_eld;
9075                         dev_priv->display.modeset_global_resources =
9076                                 ivb_modeset_global_resources;
9077                 } else if (IS_HASWELL(dev)) {
9078                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9079                         dev_priv->display.write_eld = haswell_write_eld;
9080                         dev_priv->display.modeset_global_resources =
9081                                 haswell_modeset_global_resources;
9082                 }
9083         } else if (IS_G4X(dev)) {
9084                 dev_priv->display.write_eld = g4x_write_eld;
9085         }
9086
9087         /* Default just returns -ENODEV to indicate unsupported */
9088         dev_priv->display.queue_flip = intel_default_queue_flip;
9089
9090         switch (INTEL_INFO(dev)->gen) {
9091         case 2:
9092                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9093                 break;
9094
9095         case 3:
9096                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9097                 break;
9098
9099         case 4:
9100         case 5:
9101                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9102                 break;
9103
9104         case 6:
9105                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9106                 break;
9107         case 7:
9108                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9109                 break;
9110         }
9111 }
9112
9113 /*
9114  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9115  * resume, or other times.  This quirk makes sure that's the case for
9116  * affected systems.
9117  */
9118 static void quirk_pipea_force(struct drm_device *dev)
9119 {
9120         struct drm_i915_private *dev_priv = dev->dev_private;
9121
9122         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9123         DRM_INFO("applying pipe a force quirk\n");
9124 }
9125
9126 /*
9127  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9128  */
9129 static void quirk_ssc_force_disable(struct drm_device *dev)
9130 {
9131         struct drm_i915_private *dev_priv = dev->dev_private;
9132         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9133         DRM_INFO("applying lvds SSC disable quirk\n");
9134 }
9135
9136 /*
9137  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9138  * brightness value
9139  */
9140 static void quirk_invert_brightness(struct drm_device *dev)
9141 {
9142         struct drm_i915_private *dev_priv = dev->dev_private;
9143         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9144         DRM_INFO("applying inverted panel brightness quirk\n");
9145 }
9146
9147 struct intel_quirk {
9148         int device;
9149         int subsystem_vendor;
9150         int subsystem_device;
9151         void (*hook)(struct drm_device *dev);
9152 };
9153
9154 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9155 struct intel_dmi_quirk {
9156         void (*hook)(struct drm_device *dev);
9157         const struct dmi_system_id (*dmi_id_list)[];
9158 };
9159
9160 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9161 {
9162         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9163         return 1;
9164 }
9165
9166 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9167         {
9168                 .dmi_id_list = &(const struct dmi_system_id[]) {
9169                         {
9170                                 .callback = intel_dmi_reverse_brightness,
9171                                 .ident = "NCR Corporation",
9172                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9173                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9174                                 },
9175                         },
9176                         { }  /* terminating entry */
9177                 },
9178                 .hook = quirk_invert_brightness,
9179         },
9180 };
9181
9182 static struct intel_quirk intel_quirks[] = {
9183         /* HP Mini needs pipe A force quirk (LP: #322104) */
9184         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9185
9186         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9187         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9188
9189         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9190         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9191
9192         /* 830/845 need to leave pipe A & dpll A up */
9193         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9194         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9195
9196         /* Lenovo U160 cannot use SSC on LVDS */
9197         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9198
9199         /* Sony Vaio Y cannot use SSC on LVDS */
9200         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9201
9202         /* Acer Aspire 5734Z must invert backlight brightness */
9203         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9204
9205         /* Acer/eMachines G725 */
9206         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9207
9208         /* Acer/eMachines e725 */
9209         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9210
9211         /* Acer/Packard Bell NCL20 */
9212         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9213
9214         /* Acer Aspire 4736Z */
9215         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9216 };
9217
9218 static void intel_init_quirks(struct drm_device *dev)
9219 {
9220         struct pci_dev *d = dev->pdev;
9221         int i;
9222
9223         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9224                 struct intel_quirk *q = &intel_quirks[i];
9225
9226                 if (d->device == q->device &&
9227                     (d->subsystem_vendor == q->subsystem_vendor ||
9228                      q->subsystem_vendor == PCI_ANY_ID) &&
9229                     (d->subsystem_device == q->subsystem_device ||
9230                      q->subsystem_device == PCI_ANY_ID))
9231                         q->hook(dev);
9232         }
9233         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9234                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9235                         intel_dmi_quirks[i].hook(dev);
9236         }
9237 }
9238
9239 /* Disable the VGA plane that we never use */
9240 static void i915_disable_vga(struct drm_device *dev)
9241 {
9242         struct drm_i915_private *dev_priv = dev->dev_private;
9243         u8 sr1;
9244         u32 vga_reg = i915_vgacntrl_reg(dev);
9245
9246         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9247         outb(SR01, VGA_SR_INDEX);
9248         sr1 = inb(VGA_SR_DATA);
9249         outb(sr1 | 1<<5, VGA_SR_DATA);
9250         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9251         udelay(300);
9252
9253         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9254         POSTING_READ(vga_reg);
9255 }
9256
9257 void intel_modeset_init_hw(struct drm_device *dev)
9258 {
9259         intel_init_power_well(dev);
9260
9261         intel_prepare_ddi(dev);
9262
9263         intel_init_clock_gating(dev);
9264
9265         mutex_lock(&dev->struct_mutex);
9266         intel_enable_gt_powersave(dev);
9267         mutex_unlock(&dev->struct_mutex);
9268 }
9269
9270 void intel_modeset_suspend_hw(struct drm_device *dev)
9271 {
9272         intel_suspend_hw(dev);
9273 }
9274
9275 void intel_modeset_init(struct drm_device *dev)
9276 {
9277         struct drm_i915_private *dev_priv = dev->dev_private;
9278         int i, j, ret;
9279
9280         drm_mode_config_init(dev);
9281
9282         dev->mode_config.min_width = 0;
9283         dev->mode_config.min_height = 0;
9284
9285         dev->mode_config.preferred_depth = 24;
9286         dev->mode_config.prefer_shadow = 1;
9287
9288         dev->mode_config.funcs = &intel_mode_funcs;
9289
9290         intel_init_quirks(dev);
9291
9292         intel_init_pm(dev);
9293
9294         if (INTEL_INFO(dev)->num_pipes == 0)
9295                 return;
9296
9297         intel_init_display(dev);
9298
9299         if (IS_GEN2(dev)) {
9300                 dev->mode_config.max_width = 2048;
9301                 dev->mode_config.max_height = 2048;
9302         } else if (IS_GEN3(dev)) {
9303                 dev->mode_config.max_width = 4096;
9304                 dev->mode_config.max_height = 4096;
9305         } else {
9306                 dev->mode_config.max_width = 8192;
9307                 dev->mode_config.max_height = 8192;
9308         }
9309         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9310
9311         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9312                       INTEL_INFO(dev)->num_pipes,
9313                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9314
9315         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9316                 intel_crtc_init(dev, i);
9317                 for (j = 0; j < dev_priv->num_plane; j++) {
9318                         ret = intel_plane_init(dev, i, j);
9319                         if (ret)
9320                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9321                                               pipe_name(i), sprite_name(i, j), ret);
9322                 }
9323         }
9324
9325         intel_cpu_pll_init(dev);
9326         intel_pch_pll_init(dev);
9327
9328         /* Just disable it once at startup */
9329         i915_disable_vga(dev);
9330         intel_setup_outputs(dev);
9331
9332         /* Just in case the BIOS is doing something questionable. */
9333         intel_disable_fbc(dev);
9334 }
9335
9336 static void
9337 intel_connector_break_all_links(struct intel_connector *connector)
9338 {
9339         connector->base.dpms = DRM_MODE_DPMS_OFF;
9340         connector->base.encoder = NULL;
9341         connector->encoder->connectors_active = false;
9342         connector->encoder->base.crtc = NULL;
9343 }
9344
9345 static void intel_enable_pipe_a(struct drm_device *dev)
9346 {
9347         struct intel_connector *connector;
9348         struct drm_connector *crt = NULL;
9349         struct intel_load_detect_pipe load_detect_temp;
9350
9351         /* We can't just switch on the pipe A, we need to set things up with a
9352          * proper mode and output configuration. As a gross hack, enable pipe A
9353          * by enabling the load detect pipe once. */
9354         list_for_each_entry(connector,
9355                             &dev->mode_config.connector_list,
9356                             base.head) {
9357                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9358                         crt = &connector->base;
9359                         break;
9360                 }
9361         }
9362
9363         if (!crt)
9364                 return;
9365
9366         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9367                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9368
9369
9370 }
9371
9372 static bool
9373 intel_check_plane_mapping(struct intel_crtc *crtc)
9374 {
9375         struct drm_device *dev = crtc->base.dev;
9376         struct drm_i915_private *dev_priv = dev->dev_private;
9377         u32 reg, val;
9378
9379         if (INTEL_INFO(dev)->num_pipes == 1)
9380                 return true;
9381
9382         reg = DSPCNTR(!crtc->plane);
9383         val = I915_READ(reg);
9384
9385         if ((val & DISPLAY_PLANE_ENABLE) &&
9386             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9387                 return false;
9388
9389         return true;
9390 }
9391
9392 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9393 {
9394         struct drm_device *dev = crtc->base.dev;
9395         struct drm_i915_private *dev_priv = dev->dev_private;
9396         u32 reg;
9397
9398         /* Clear any frame start delays used for debugging left by the BIOS */
9399         reg = PIPECONF(crtc->config.cpu_transcoder);
9400         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9401
9402         /* We need to sanitize the plane -> pipe mapping first because this will
9403          * disable the crtc (and hence change the state) if it is wrong. Note
9404          * that gen4+ has a fixed plane -> pipe mapping.  */
9405         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9406                 struct intel_connector *connector;
9407                 bool plane;
9408
9409                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9410                               crtc->base.base.id);
9411
9412                 /* Pipe has the wrong plane attached and the plane is active.
9413                  * Temporarily change the plane mapping and disable everything
9414                  * ...  */
9415                 plane = crtc->plane;
9416                 crtc->plane = !plane;
9417                 dev_priv->display.crtc_disable(&crtc->base);
9418                 crtc->plane = plane;
9419
9420                 /* ... and break all links. */
9421                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9422                                     base.head) {
9423                         if (connector->encoder->base.crtc != &crtc->base)
9424                                 continue;
9425
9426                         intel_connector_break_all_links(connector);
9427                 }
9428
9429                 WARN_ON(crtc->active);
9430                 crtc->base.enabled = false;
9431         }
9432
9433         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9434             crtc->pipe == PIPE_A && !crtc->active) {
9435                 /* BIOS forgot to enable pipe A, this mostly happens after
9436                  * resume. Force-enable the pipe to fix this, the update_dpms
9437                  * call below we restore the pipe to the right state, but leave
9438                  * the required bits on. */
9439                 intel_enable_pipe_a(dev);
9440         }
9441
9442         /* Adjust the state of the output pipe according to whether we
9443          * have active connectors/encoders. */
9444         intel_crtc_update_dpms(&crtc->base);
9445
9446         if (crtc->active != crtc->base.enabled) {
9447                 struct intel_encoder *encoder;
9448
9449                 /* This can happen either due to bugs in the get_hw_state
9450                  * functions or because the pipe is force-enabled due to the
9451                  * pipe A quirk. */
9452                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9453                               crtc->base.base.id,
9454                               crtc->base.enabled ? "enabled" : "disabled",
9455                               crtc->active ? "enabled" : "disabled");
9456
9457                 crtc->base.enabled = crtc->active;
9458
9459                 /* Because we only establish the connector -> encoder ->
9460                  * crtc links if something is active, this means the
9461                  * crtc is now deactivated. Break the links. connector
9462                  * -> encoder links are only establish when things are
9463                  *  actually up, hence no need to break them. */
9464                 WARN_ON(crtc->active);
9465
9466                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9467                         WARN_ON(encoder->connectors_active);
9468                         encoder->base.crtc = NULL;
9469                 }
9470         }
9471 }
9472
9473 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9474 {
9475         struct intel_connector *connector;
9476         struct drm_device *dev = encoder->base.dev;
9477
9478         /* We need to check both for a crtc link (meaning that the
9479          * encoder is active and trying to read from a pipe) and the
9480          * pipe itself being active. */
9481         bool has_active_crtc = encoder->base.crtc &&
9482                 to_intel_crtc(encoder->base.crtc)->active;
9483
9484         if (encoder->connectors_active && !has_active_crtc) {
9485                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9486                               encoder->base.base.id,
9487                               drm_get_encoder_name(&encoder->base));
9488
9489                 /* Connector is active, but has no active pipe. This is
9490                  * fallout from our resume register restoring. Disable
9491                  * the encoder manually again. */
9492                 if (encoder->base.crtc) {
9493                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9494                                       encoder->base.base.id,
9495                                       drm_get_encoder_name(&encoder->base));
9496                         encoder->disable(encoder);
9497                 }
9498
9499                 /* Inconsistent output/port/pipe state happens presumably due to
9500                  * a bug in one of the get_hw_state functions. Or someplace else
9501                  * in our code, like the register restore mess on resume. Clamp
9502                  * things to off as a safer default. */
9503                 list_for_each_entry(connector,
9504                                     &dev->mode_config.connector_list,
9505                                     base.head) {
9506                         if (connector->encoder != encoder)
9507                                 continue;
9508
9509                         intel_connector_break_all_links(connector);
9510                 }
9511         }
9512         /* Enabled encoders without active connectors will be fixed in
9513          * the crtc fixup. */
9514 }
9515
9516 void i915_redisable_vga(struct drm_device *dev)
9517 {
9518         struct drm_i915_private *dev_priv = dev->dev_private;
9519         u32 vga_reg = i915_vgacntrl_reg(dev);
9520
9521         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9522                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9523                 i915_disable_vga(dev);
9524         }
9525 }
9526
9527 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9528  * and i915 state tracking structures. */
9529 void intel_modeset_setup_hw_state(struct drm_device *dev,
9530                                   bool force_restore)
9531 {
9532         struct drm_i915_private *dev_priv = dev->dev_private;
9533         enum pipe pipe;
9534         u32 tmp;
9535         struct drm_plane *plane;
9536         struct intel_crtc *crtc;
9537         struct intel_encoder *encoder;
9538         struct intel_connector *connector;
9539
9540         if (HAS_DDI(dev)) {
9541                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9542
9543                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9544                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9545                         case TRANS_DDI_EDP_INPUT_A_ON:
9546                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9547                                 pipe = PIPE_A;
9548                                 break;
9549                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9550                                 pipe = PIPE_B;
9551                                 break;
9552                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9553                                 pipe = PIPE_C;
9554                                 break;
9555                         default:
9556                                 /* A bogus value has been programmed, disable
9557                                  * the transcoder */
9558                                 WARN(1, "Bogus eDP source %08x\n", tmp);
9559                                 intel_ddi_disable_transcoder_func(dev_priv,
9560                                                 TRANSCODER_EDP);
9561                                 goto setup_pipes;
9562                         }
9563
9564                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9565                         crtc->config.cpu_transcoder = TRANSCODER_EDP;
9566
9567                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9568                                       pipe_name(pipe));
9569                 }
9570         }
9571
9572 setup_pipes:
9573         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9574                             base.head) {
9575                 enum transcoder tmp = crtc->config.cpu_transcoder;
9576                 memset(&crtc->config, 0, sizeof(crtc->config));
9577                 crtc->config.cpu_transcoder = tmp;
9578
9579                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9580                                                                  &crtc->config);
9581
9582                 crtc->base.enabled = crtc->active;
9583
9584                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9585                               crtc->base.base.id,
9586                               crtc->active ? "enabled" : "disabled");
9587         }
9588
9589         if (HAS_DDI(dev))
9590                 intel_ddi_setup_hw_pll_state(dev);
9591
9592         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9593                             base.head) {
9594                 pipe = 0;
9595
9596                 if (encoder->get_hw_state(encoder, &pipe)) {
9597                         encoder->base.crtc =
9598                                 dev_priv->pipe_to_crtc_mapping[pipe];
9599                 } else {
9600                         encoder->base.crtc = NULL;
9601                 }
9602
9603                 encoder->connectors_active = false;
9604                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9605                               encoder->base.base.id,
9606                               drm_get_encoder_name(&encoder->base),
9607                               encoder->base.crtc ? "enabled" : "disabled",
9608                               pipe);
9609         }
9610
9611         list_for_each_entry(connector, &dev->mode_config.connector_list,
9612                             base.head) {
9613                 if (connector->get_hw_state(connector)) {
9614                         connector->base.dpms = DRM_MODE_DPMS_ON;
9615                         connector->encoder->connectors_active = true;
9616                         connector->base.encoder = &connector->encoder->base;
9617                 } else {
9618                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9619                         connector->base.encoder = NULL;
9620                 }
9621                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9622                               connector->base.base.id,
9623                               drm_get_connector_name(&connector->base),
9624                               connector->base.encoder ? "enabled" : "disabled");
9625         }
9626
9627         /* HW state is read out, now we need to sanitize this mess. */
9628         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9629                             base.head) {
9630                 intel_sanitize_encoder(encoder);
9631         }
9632
9633         for_each_pipe(pipe) {
9634                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9635                 intel_sanitize_crtc(crtc);
9636         }
9637
9638         if (force_restore) {
9639                 /*
9640                  * We need to use raw interfaces for restoring state to avoid
9641                  * checking (bogus) intermediate states.
9642                  */
9643                 for_each_pipe(pipe) {
9644                         struct drm_crtc *crtc =
9645                                 dev_priv->pipe_to_crtc_mapping[pipe];
9646
9647                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9648                                          crtc->fb);
9649                 }
9650                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9651                         intel_plane_restore(plane);
9652
9653                 i915_redisable_vga(dev);
9654         } else {
9655                 intel_modeset_update_staged_output_state(dev);
9656         }
9657
9658         intel_modeset_check_state(dev);
9659
9660         drm_mode_config_reset(dev);
9661 }
9662
9663 void intel_modeset_gem_init(struct drm_device *dev)
9664 {
9665         intel_modeset_init_hw(dev);
9666
9667         intel_setup_overlay(dev);
9668
9669         intel_modeset_setup_hw_state(dev, false);
9670 }
9671
9672 void intel_modeset_cleanup(struct drm_device *dev)
9673 {
9674         struct drm_i915_private *dev_priv = dev->dev_private;
9675         struct drm_crtc *crtc;
9676         struct intel_crtc *intel_crtc;
9677
9678         /*
9679          * Interrupts and polling as the first thing to avoid creating havoc.
9680          * Too much stuff here (turning of rps, connectors, ...) would
9681          * experience fancy races otherwise.
9682          */
9683         drm_irq_uninstall(dev);
9684         cancel_work_sync(&dev_priv->hotplug_work);
9685         /*
9686          * Due to the hpd irq storm handling the hotplug work can re-arm the
9687          * poll handlers. Hence disable polling after hpd handling is shut down.
9688          */
9689         drm_kms_helper_poll_fini(dev);
9690
9691         mutex_lock(&dev->struct_mutex);
9692
9693         intel_unregister_dsm_handler();
9694
9695         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9696                 /* Skip inactive CRTCs */
9697                 if (!crtc->fb)
9698                         continue;
9699
9700                 intel_crtc = to_intel_crtc(crtc);
9701                 intel_increase_pllclock(crtc);
9702         }
9703
9704         intel_disable_fbc(dev);
9705
9706         intel_disable_gt_powersave(dev);
9707
9708         ironlake_teardown_rc6(dev);
9709
9710         mutex_unlock(&dev->struct_mutex);
9711
9712         /* flush any delayed tasks or pending work */
9713         flush_scheduled_work();
9714
9715         /* destroy backlight, if any, before the connectors */
9716         intel_panel_destroy_backlight(dev);
9717
9718         drm_mode_config_cleanup(dev);
9719
9720         intel_cleanup_overlay(dev);
9721 }
9722
9723 /*
9724  * Return which encoder is currently attached for connector.
9725  */
9726 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9727 {
9728         return &intel_attached_encoder(connector)->base;
9729 }
9730
9731 void intel_connector_attach_encoder(struct intel_connector *connector,
9732                                     struct intel_encoder *encoder)
9733 {
9734         connector->encoder = encoder;
9735         drm_mode_connector_attach_encoder(&connector->base,
9736                                           &encoder->base);
9737 }
9738
9739 /*
9740  * set vga decode state - true == enable VGA decode
9741  */
9742 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9743 {
9744         struct drm_i915_private *dev_priv = dev->dev_private;
9745         u16 gmch_ctrl;
9746
9747         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9748         if (state)
9749                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9750         else
9751                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9752         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9753         return 0;
9754 }
9755
9756 #ifdef CONFIG_DEBUG_FS
9757 #include <linux/seq_file.h>
9758
9759 struct intel_display_error_state {
9760
9761         u32 power_well_driver;
9762
9763         struct intel_cursor_error_state {
9764                 u32 control;
9765                 u32 position;
9766                 u32 base;
9767                 u32 size;
9768         } cursor[I915_MAX_PIPES];
9769
9770         struct intel_pipe_error_state {
9771                 enum transcoder cpu_transcoder;
9772                 u32 conf;
9773                 u32 source;
9774
9775                 u32 htotal;
9776                 u32 hblank;
9777                 u32 hsync;
9778                 u32 vtotal;
9779                 u32 vblank;
9780                 u32 vsync;
9781         } pipe[I915_MAX_PIPES];
9782
9783         struct intel_plane_error_state {
9784                 u32 control;
9785                 u32 stride;
9786                 u32 size;
9787                 u32 pos;
9788                 u32 addr;
9789                 u32 surface;
9790                 u32 tile_offset;
9791         } plane[I915_MAX_PIPES];
9792 };
9793
9794 struct intel_display_error_state *
9795 intel_display_capture_error_state(struct drm_device *dev)
9796 {
9797         drm_i915_private_t *dev_priv = dev->dev_private;
9798         struct intel_display_error_state *error;
9799         enum transcoder cpu_transcoder;
9800         int i;
9801
9802         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9803         if (error == NULL)
9804                 return NULL;
9805
9806         if (HAS_POWER_WELL(dev))
9807                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9808
9809         for_each_pipe(i) {
9810                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9811                 error->pipe[i].cpu_transcoder = cpu_transcoder;
9812
9813                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9814                         error->cursor[i].control = I915_READ(CURCNTR(i));
9815                         error->cursor[i].position = I915_READ(CURPOS(i));
9816                         error->cursor[i].base = I915_READ(CURBASE(i));
9817                 } else {
9818                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9819                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9820                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9821                 }
9822
9823                 error->plane[i].control = I915_READ(DSPCNTR(i));
9824                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9825                 if (INTEL_INFO(dev)->gen <= 3) {
9826                         error->plane[i].size = I915_READ(DSPSIZE(i));
9827                         error->plane[i].pos = I915_READ(DSPPOS(i));
9828                 }
9829                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9830                         error->plane[i].addr = I915_READ(DSPADDR(i));
9831                 if (INTEL_INFO(dev)->gen >= 4) {
9832                         error->plane[i].surface = I915_READ(DSPSURF(i));
9833                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9834                 }
9835
9836                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9837                 error->pipe[i].source = I915_READ(PIPESRC(i));
9838                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9839                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9840                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9841                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9842                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9843                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9844         }
9845
9846         /* In the code above we read the registers without checking if the power
9847          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9848          * prevent the next I915_WRITE from detecting it and printing an error
9849          * message. */
9850         if (HAS_POWER_WELL(dev))
9851                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9852
9853         return error;
9854 }
9855
9856 void
9857 intel_display_print_error_state(struct seq_file *m,
9858                                 struct drm_device *dev,
9859                                 struct intel_display_error_state *error)
9860 {
9861         int i;
9862
9863         seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9864         if (HAS_POWER_WELL(dev))
9865                 seq_printf(m, "PWR_WELL_CTL2: %08x\n",
9866                            error->power_well_driver);
9867         for_each_pipe(i) {
9868                 seq_printf(m, "Pipe [%d]:\n", i);
9869                 seq_printf(m, "  CPU transcoder: %c\n",
9870                            transcoder_name(error->pipe[i].cpu_transcoder));
9871                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9872                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9873                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9874                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9875                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9876                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9877                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9878                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9879
9880                 seq_printf(m, "Plane [%d]:\n", i);
9881                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9882                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9883                 if (INTEL_INFO(dev)->gen <= 3) {
9884                         seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9885                         seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9886                 }
9887                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9888                         seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9889                 if (INTEL_INFO(dev)->gen >= 4) {
9890                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9891                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9892                 }
9893
9894                 seq_printf(m, "Cursor [%d]:\n", i);
9895                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9896                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9897                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9898         }
9899 }
9900 #endif