2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
52 static bool is_mmio_work(struct intel_flip_work *work)
54 return work->mmio_work.func;
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
71 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
75 static const uint32_t skl_primary_formats[] = {
82 DRM_FORMAT_XRGB2101010,
83 DRM_FORMAT_XBGR2101010,
91 static const uint32_t intel_cursor_formats[] = {
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98 struct intel_crtc_state *pipe_config);
100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
101 struct drm_i915_gem_object *obj,
102 struct drm_mode_fb_cmd2 *mode_cmd);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
119 struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
129 } dot, vco, n, m, m1, m2, p, p1;
133 int p2_slow, p2_fast;
137 /* returns HPLL frequency in kHz */
138 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
140 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
142 /* Obtain SKU information */
143 mutex_lock(&dev_priv->sb_lock);
144 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
145 CCK_FUSE_HPLL_FREQ_MASK;
146 mutex_unlock(&dev_priv->sb_lock);
148 return vco_freq[hpll_freq] * 1000;
151 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
152 const char *name, u32 reg, int ref_freq)
157 mutex_lock(&dev_priv->sb_lock);
158 val = vlv_cck_read(dev_priv, reg);
159 mutex_unlock(&dev_priv->sb_lock);
161 divider = val & CCK_FREQUENCY_VALUES;
163 WARN((val & CCK_FREQUENCY_STATUS) !=
164 (divider << CCK_FREQUENCY_STATUS_SHIFT),
165 "%s change in progress\n", name);
167 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
170 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
171 const char *name, u32 reg)
173 if (dev_priv->hpll_freq == 0)
174 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
176 return vlv_get_cck_clock(dev_priv, name, reg,
177 dev_priv->hpll_freq);
180 static void intel_update_czclk(struct drm_i915_private *dev_priv)
182 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
185 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
186 CCK_CZ_CLOCK_CONTROL);
188 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
191 static inline u32 /* units of 100MHz */
192 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
193 const struct intel_crtc_state *pipe_config)
195 if (HAS_DDI(dev_priv))
196 return pipe_config->port_clock; /* SPLL */
197 else if (IS_GEN5(dev_priv))
198 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
203 static const struct intel_limit intel_limits_i8xx_dac = {
204 .dot = { .min = 25000, .max = 350000 },
205 .vco = { .min = 908000, .max = 1512000 },
206 .n = { .min = 2, .max = 16 },
207 .m = { .min = 96, .max = 140 },
208 .m1 = { .min = 18, .max = 26 },
209 .m2 = { .min = 6, .max = 16 },
210 .p = { .min = 4, .max = 128 },
211 .p1 = { .min = 2, .max = 33 },
212 .p2 = { .dot_limit = 165000,
213 .p2_slow = 4, .p2_fast = 2 },
216 static const struct intel_limit intel_limits_i8xx_dvo = {
217 .dot = { .min = 25000, .max = 350000 },
218 .vco = { .min = 908000, .max = 1512000 },
219 .n = { .min = 2, .max = 16 },
220 .m = { .min = 96, .max = 140 },
221 .m1 = { .min = 18, .max = 26 },
222 .m2 = { .min = 6, .max = 16 },
223 .p = { .min = 4, .max = 128 },
224 .p1 = { .min = 2, .max = 33 },
225 .p2 = { .dot_limit = 165000,
226 .p2_slow = 4, .p2_fast = 4 },
229 static const struct intel_limit intel_limits_i8xx_lvds = {
230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 908000, .max = 1512000 },
232 .n = { .min = 2, .max = 16 },
233 .m = { .min = 96, .max = 140 },
234 .m1 = { .min = 18, .max = 26 },
235 .m2 = { .min = 6, .max = 16 },
236 .p = { .min = 4, .max = 128 },
237 .p1 = { .min = 1, .max = 6 },
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 14, .p2_fast = 7 },
242 static const struct intel_limit intel_limits_i9xx_sdvo = {
243 .dot = { .min = 20000, .max = 400000 },
244 .vco = { .min = 1400000, .max = 2800000 },
245 .n = { .min = 1, .max = 6 },
246 .m = { .min = 70, .max = 120 },
247 .m1 = { .min = 8, .max = 18 },
248 .m2 = { .min = 3, .max = 7 },
249 .p = { .min = 5, .max = 80 },
250 .p1 = { .min = 1, .max = 8 },
251 .p2 = { .dot_limit = 200000,
252 .p2_slow = 10, .p2_fast = 5 },
255 static const struct intel_limit intel_limits_i9xx_lvds = {
256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1400000, .max = 2800000 },
258 .n = { .min = 1, .max = 6 },
259 .m = { .min = 70, .max = 120 },
260 .m1 = { .min = 8, .max = 18 },
261 .m2 = { .min = 3, .max = 7 },
262 .p = { .min = 7, .max = 98 },
263 .p1 = { .min = 1, .max = 8 },
264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 7 },
269 static const struct intel_limit intel_limits_g4x_sdvo = {
270 .dot = { .min = 25000, .max = 270000 },
271 .vco = { .min = 1750000, .max = 3500000},
272 .n = { .min = 1, .max = 4 },
273 .m = { .min = 104, .max = 138 },
274 .m1 = { .min = 17, .max = 23 },
275 .m2 = { .min = 5, .max = 11 },
276 .p = { .min = 10, .max = 30 },
277 .p1 = { .min = 1, .max = 3},
278 .p2 = { .dot_limit = 270000,
284 static const struct intel_limit intel_limits_g4x_hdmi = {
285 .dot = { .min = 22000, .max = 400000 },
286 .vco = { .min = 1750000, .max = 3500000},
287 .n = { .min = 1, .max = 4 },
288 .m = { .min = 104, .max = 138 },
289 .m1 = { .min = 16, .max = 23 },
290 .m2 = { .min = 5, .max = 11 },
291 .p = { .min = 5, .max = 80 },
292 .p1 = { .min = 1, .max = 8},
293 .p2 = { .dot_limit = 165000,
294 .p2_slow = 10, .p2_fast = 5 },
297 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
298 .dot = { .min = 20000, .max = 115000 },
299 .vco = { .min = 1750000, .max = 3500000 },
300 .n = { .min = 1, .max = 3 },
301 .m = { .min = 104, .max = 138 },
302 .m1 = { .min = 17, .max = 23 },
303 .m2 = { .min = 5, .max = 11 },
304 .p = { .min = 28, .max = 112 },
305 .p1 = { .min = 2, .max = 8 },
306 .p2 = { .dot_limit = 0,
307 .p2_slow = 14, .p2_fast = 14
311 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
312 .dot = { .min = 80000, .max = 224000 },
313 .vco = { .min = 1750000, .max = 3500000 },
314 .n = { .min = 1, .max = 3 },
315 .m = { .min = 104, .max = 138 },
316 .m1 = { .min = 17, .max = 23 },
317 .m2 = { .min = 5, .max = 11 },
318 .p = { .min = 14, .max = 42 },
319 .p1 = { .min = 2, .max = 6 },
320 .p2 = { .dot_limit = 0,
321 .p2_slow = 7, .p2_fast = 7
325 static const struct intel_limit intel_limits_pineview_sdvo = {
326 .dot = { .min = 20000, .max = 400000},
327 .vco = { .min = 1700000, .max = 3500000 },
328 /* Pineview's Ncounter is a ring counter */
329 .n = { .min = 3, .max = 6 },
330 .m = { .min = 2, .max = 256 },
331 /* Pineview only has one combined m divider, which we treat as m2. */
332 .m1 = { .min = 0, .max = 0 },
333 .m2 = { .min = 0, .max = 254 },
334 .p = { .min = 5, .max = 80 },
335 .p1 = { .min = 1, .max = 8 },
336 .p2 = { .dot_limit = 200000,
337 .p2_slow = 10, .p2_fast = 5 },
340 static const struct intel_limit intel_limits_pineview_lvds = {
341 .dot = { .min = 20000, .max = 400000 },
342 .vco = { .min = 1700000, .max = 3500000 },
343 .n = { .min = 3, .max = 6 },
344 .m = { .min = 2, .max = 256 },
345 .m1 = { .min = 0, .max = 0 },
346 .m2 = { .min = 0, .max = 254 },
347 .p = { .min = 7, .max = 112 },
348 .p1 = { .min = 1, .max = 8 },
349 .p2 = { .dot_limit = 112000,
350 .p2_slow = 14, .p2_fast = 14 },
353 /* Ironlake / Sandybridge
355 * We calculate clock using (register_value + 2) for N/M1/M2, so here
356 * the range value for them is (actual_value - 2).
358 static const struct intel_limit intel_limits_ironlake_dac = {
359 .dot = { .min = 25000, .max = 350000 },
360 .vco = { .min = 1760000, .max = 3510000 },
361 .n = { .min = 1, .max = 5 },
362 .m = { .min = 79, .max = 127 },
363 .m1 = { .min = 12, .max = 22 },
364 .m2 = { .min = 5, .max = 9 },
365 .p = { .min = 5, .max = 80 },
366 .p1 = { .min = 1, .max = 8 },
367 .p2 = { .dot_limit = 225000,
368 .p2_slow = 10, .p2_fast = 5 },
371 static const struct intel_limit intel_limits_ironlake_single_lvds = {
372 .dot = { .min = 25000, .max = 350000 },
373 .vco = { .min = 1760000, .max = 3510000 },
374 .n = { .min = 1, .max = 3 },
375 .m = { .min = 79, .max = 118 },
376 .m1 = { .min = 12, .max = 22 },
377 .m2 = { .min = 5, .max = 9 },
378 .p = { .min = 28, .max = 112 },
379 .p1 = { .min = 2, .max = 8 },
380 .p2 = { .dot_limit = 225000,
381 .p2_slow = 14, .p2_fast = 14 },
384 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
385 .dot = { .min = 25000, .max = 350000 },
386 .vco = { .min = 1760000, .max = 3510000 },
387 .n = { .min = 1, .max = 3 },
388 .m = { .min = 79, .max = 127 },
389 .m1 = { .min = 12, .max = 22 },
390 .m2 = { .min = 5, .max = 9 },
391 .p = { .min = 14, .max = 56 },
392 .p1 = { .min = 2, .max = 8 },
393 .p2 = { .dot_limit = 225000,
394 .p2_slow = 7, .p2_fast = 7 },
397 /* LVDS 100mhz refclk limits. */
398 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
399 .dot = { .min = 25000, .max = 350000 },
400 .vco = { .min = 1760000, .max = 3510000 },
401 .n = { .min = 1, .max = 2 },
402 .m = { .min = 79, .max = 126 },
403 .m1 = { .min = 12, .max = 22 },
404 .m2 = { .min = 5, .max = 9 },
405 .p = { .min = 28, .max = 112 },
406 .p1 = { .min = 2, .max = 8 },
407 .p2 = { .dot_limit = 225000,
408 .p2_slow = 14, .p2_fast = 14 },
411 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
412 .dot = { .min = 25000, .max = 350000 },
413 .vco = { .min = 1760000, .max = 3510000 },
414 .n = { .min = 1, .max = 3 },
415 .m = { .min = 79, .max = 126 },
416 .m1 = { .min = 12, .max = 22 },
417 .m2 = { .min = 5, .max = 9 },
418 .p = { .min = 14, .max = 42 },
419 .p1 = { .min = 2, .max = 6 },
420 .p2 = { .dot_limit = 225000,
421 .p2_slow = 7, .p2_fast = 7 },
424 static const struct intel_limit intel_limits_vlv = {
426 * These are the data rate limits (measured in fast clocks)
427 * since those are the strictest limits we have. The fast
428 * clock and actual rate limits are more relaxed, so checking
429 * them would make no difference.
431 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
432 .vco = { .min = 4000000, .max = 6000000 },
433 .n = { .min = 1, .max = 7 },
434 .m1 = { .min = 2, .max = 3 },
435 .m2 = { .min = 11, .max = 156 },
436 .p1 = { .min = 2, .max = 3 },
437 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
440 static const struct intel_limit intel_limits_chv = {
442 * These are the data rate limits (measured in fast clocks)
443 * since those are the strictest limits we have. The fast
444 * clock and actual rate limits are more relaxed, so checking
445 * them would make no difference.
447 .dot = { .min = 25000 * 5, .max = 540000 * 5},
448 .vco = { .min = 4800000, .max = 6480000 },
449 .n = { .min = 1, .max = 1 },
450 .m1 = { .min = 2, .max = 2 },
451 .m2 = { .min = 24 << 22, .max = 175 << 22 },
452 .p1 = { .min = 2, .max = 4 },
453 .p2 = { .p2_slow = 1, .p2_fast = 14 },
456 static const struct intel_limit intel_limits_bxt = {
457 /* FIXME: find real dot limits */
458 .dot = { .min = 0, .max = INT_MAX },
459 .vco = { .min = 4800000, .max = 6700000 },
460 .n = { .min = 1, .max = 1 },
461 .m1 = { .min = 2, .max = 2 },
462 /* FIXME: find real m2 limits */
463 .m2 = { .min = 2 << 22, .max = 255 << 22 },
464 .p1 = { .min = 2, .max = 4 },
465 .p2 = { .p2_slow = 1, .p2_fast = 20 },
469 needs_modeset(struct drm_crtc_state *state)
471 return drm_atomic_crtc_needs_modeset(state);
475 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
476 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
477 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
478 * The helpers' return value is the rate of the clock that is fed to the
479 * display engine's pipe which can be the above fast dot clock rate or a
480 * divided-down version of it.
482 /* m1 is reserved as 0 in Pineview, n is a ring counter */
483 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
485 clock->m = clock->m2 + 2;
486 clock->p = clock->p1 * clock->p2;
487 if (WARN_ON(clock->n == 0 || clock->p == 0))
489 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
490 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
495 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
497 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
500 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
502 clock->m = i9xx_dpll_compute_m(clock);
503 clock->p = clock->p1 * clock->p2;
504 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
506 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
507 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
512 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
514 clock->m = clock->m1 * clock->m2;
515 clock->p = clock->p1 * clock->p2;
516 if (WARN_ON(clock->n == 0 || clock->p == 0))
518 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
519 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
521 return clock->dot / 5;
524 int chv_calc_dpll_params(int refclk, struct dpll *clock)
526 clock->m = clock->m1 * clock->m2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
534 return clock->dot / 5;
537 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
539 * Returns whether the given set of divisors are valid for a given refclk with
540 * the given connectors.
543 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
544 const struct intel_limit *limit,
545 const struct dpll *clock)
547 if (clock->n < limit->n.min || limit->n.max < clock->n)
548 INTELPllInvalid("n out of range\n");
549 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
550 INTELPllInvalid("p1 out of range\n");
551 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
552 INTELPllInvalid("m2 out of range\n");
553 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
554 INTELPllInvalid("m1 out of range\n");
556 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
557 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
558 if (clock->m1 <= clock->m2)
559 INTELPllInvalid("m1 <= m2\n");
561 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
562 !IS_GEN9_LP(dev_priv)) {
563 if (clock->p < limit->p.min || limit->p.max < clock->p)
564 INTELPllInvalid("p out of range\n");
565 if (clock->m < limit->m.min || limit->m.max < clock->m)
566 INTELPllInvalid("m out of range\n");
569 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
570 INTELPllInvalid("vco out of range\n");
571 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
572 * connector, etc., rather than just a single range.
574 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
575 INTELPllInvalid("dot out of range\n");
581 i9xx_select_p2_div(const struct intel_limit *limit,
582 const struct intel_crtc_state *crtc_state,
585 struct drm_device *dev = crtc_state->base.crtc->dev;
587 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
593 if (intel_is_dual_link_lvds(dev))
594 return limit->p2.p2_fast;
596 return limit->p2.p2_slow;
598 if (target < limit->p2.dot_limit)
599 return limit->p2.p2_slow;
601 return limit->p2.p2_fast;
606 * Returns a set of divisors for the desired target clock with the given
607 * refclk, or FALSE. The returned values represent the clock equation:
608 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
610 * Target and reference clocks are specified in kHz.
612 * If match_clock is provided, then best_clock P divider must match the P
613 * divider from @match_clock used for LVDS downclocking.
616 i9xx_find_best_dpll(const struct intel_limit *limit,
617 struct intel_crtc_state *crtc_state,
618 int target, int refclk, struct dpll *match_clock,
619 struct dpll *best_clock)
621 struct drm_device *dev = crtc_state->base.crtc->dev;
625 memset(best_clock, 0, sizeof(*best_clock));
627 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
641 i9xx_calc_dpll_params(refclk, &clock);
642 if (!intel_PLL_is_valid(to_i915(dev),
647 clock.p != match_clock->p)
650 this_err = abs(clock.dot - target);
651 if (this_err < err) {
660 return (err != target);
664 * Returns a set of divisors for the desired target clock with the given
665 * refclk, or FALSE. The returned values represent the clock equation:
666 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
668 * Target and reference clocks are specified in kHz.
670 * If match_clock is provided, then best_clock P divider must match the P
671 * divider from @match_clock used for LVDS downclocking.
674 pnv_find_best_dpll(const struct intel_limit *limit,
675 struct intel_crtc_state *crtc_state,
676 int target, int refclk, struct dpll *match_clock,
677 struct dpll *best_clock)
679 struct drm_device *dev = crtc_state->base.crtc->dev;
683 memset(best_clock, 0, sizeof(*best_clock));
685 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
687 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
689 for (clock.m2 = limit->m2.min;
690 clock.m2 <= limit->m2.max; clock.m2++) {
691 for (clock.n = limit->n.min;
692 clock.n <= limit->n.max; clock.n++) {
693 for (clock.p1 = limit->p1.min;
694 clock.p1 <= limit->p1.max; clock.p1++) {
697 pnv_calc_dpll_params(refclk, &clock);
698 if (!intel_PLL_is_valid(to_i915(dev),
703 clock.p != match_clock->p)
706 this_err = abs(clock.dot - target);
707 if (this_err < err) {
716 return (err != target);
720 * Returns a set of divisors for the desired target clock with the given
721 * refclk, or FALSE. The returned values represent the clock equation:
722 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
724 * Target and reference clocks are specified in kHz.
726 * If match_clock is provided, then best_clock P divider must match the P
727 * divider from @match_clock used for LVDS downclocking.
730 g4x_find_best_dpll(const struct intel_limit *limit,
731 struct intel_crtc_state *crtc_state,
732 int target, int refclk, struct dpll *match_clock,
733 struct dpll *best_clock)
735 struct drm_device *dev = crtc_state->base.crtc->dev;
739 /* approximately equals target * 0.00585 */
740 int err_most = (target >> 8) + (target >> 9);
742 memset(best_clock, 0, sizeof(*best_clock));
744 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
746 max_n = limit->n.max;
747 /* based on hardware requirement, prefer smaller n to precision */
748 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
749 /* based on hardware requirement, prefere larger m1,m2 */
750 for (clock.m1 = limit->m1.max;
751 clock.m1 >= limit->m1.min; clock.m1--) {
752 for (clock.m2 = limit->m2.max;
753 clock.m2 >= limit->m2.min; clock.m2--) {
754 for (clock.p1 = limit->p1.max;
755 clock.p1 >= limit->p1.min; clock.p1--) {
758 i9xx_calc_dpll_params(refclk, &clock);
759 if (!intel_PLL_is_valid(to_i915(dev),
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
779 * Check if the calculated PLL configuration is more optimal compared to the
780 * best configuration and error found so far. Return the calculated error.
782 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
783 const struct dpll *calculated_clock,
784 const struct dpll *best_clock,
785 unsigned int best_error_ppm,
786 unsigned int *error_ppm)
789 * For CHV ignore the error and consider only the P value.
790 * Prefer a bigger P value based on HW requirements.
792 if (IS_CHERRYVIEW(to_i915(dev))) {
795 return calculated_clock->p > best_clock->p;
798 if (WARN_ON_ONCE(!target_freq))
801 *error_ppm = div_u64(1000000ULL *
802 abs(target_freq - calculated_clock->dot),
805 * Prefer a better P value over a better (smaller) error if the error
806 * is small. Ensure this preference for future configurations too by
807 * setting the error to 0.
809 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
815 return *error_ppm + 10 < best_error_ppm;
819 * Returns a set of divisors for the desired target clock with the given
820 * refclk, or FALSE. The returned values represent the clock equation:
821 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
824 vlv_find_best_dpll(const struct intel_limit *limit,
825 struct intel_crtc_state *crtc_state,
826 int target, int refclk, struct dpll *match_clock,
827 struct dpll *best_clock)
829 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
830 struct drm_device *dev = crtc->base.dev;
832 unsigned int bestppm = 1000000;
833 /* min update 19.2 MHz */
834 int max_n = min(limit->n.max, refclk / 19200);
837 target *= 5; /* fast clock */
839 memset(best_clock, 0, sizeof(*best_clock));
841 /* based on hardware requirement, prefer smaller n to precision */
842 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
843 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
844 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
845 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
846 clock.p = clock.p1 * clock.p2;
847 /* based on hardware requirement, prefer bigger m1,m2 values */
848 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
851 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
854 vlv_calc_dpll_params(refclk, &clock);
856 if (!intel_PLL_is_valid(to_i915(dev),
861 if (!vlv_PLL_is_optimal(dev, target,
879 * Returns a set of divisors for the desired target clock with the given
880 * refclk, or FALSE. The returned values represent the clock equation:
881 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
884 chv_find_best_dpll(const struct intel_limit *limit,
885 struct intel_crtc_state *crtc_state,
886 int target, int refclk, struct dpll *match_clock,
887 struct dpll *best_clock)
889 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
890 struct drm_device *dev = crtc->base.dev;
891 unsigned int best_error_ppm;
896 memset(best_clock, 0, sizeof(*best_clock));
897 best_error_ppm = 1000000;
900 * Based on hardware doc, the n always set to 1, and m1 always
901 * set to 2. If requires to support 200Mhz refclk, we need to
902 * revisit this because n may not 1 anymore.
904 clock.n = 1, clock.m1 = 2;
905 target *= 5; /* fast clock */
907 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
908 for (clock.p2 = limit->p2.p2_fast;
909 clock.p2 >= limit->p2.p2_slow;
910 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
911 unsigned int error_ppm;
913 clock.p = clock.p1 * clock.p2;
915 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
916 clock.n) << 22, refclk * clock.m1);
918 if (m2 > INT_MAX/clock.m1)
923 chv_calc_dpll_params(refclk, &clock);
925 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
928 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
929 best_error_ppm, &error_ppm))
933 best_error_ppm = error_ppm;
941 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
942 struct dpll *best_clock)
945 const struct intel_limit *limit = &intel_limits_bxt;
947 return chv_find_best_dpll(limit, crtc_state,
948 target_clock, refclk, NULL, best_clock);
951 bool intel_crtc_active(struct intel_crtc *crtc)
953 /* Be paranoid as we can arrive here with only partial
954 * state retrieved from the hardware during setup.
956 * We can ditch the adjusted_mode.crtc_clock check as soon
957 * as Haswell has gained clock readout/fastboot support.
959 * We can ditch the crtc->primary->fb check as soon as we can
960 * properly reconstruct framebuffers.
962 * FIXME: The intel_crtc->active here should be switched to
963 * crtc->state->active once we have proper CRTC states wired up
966 return crtc->active && crtc->base.primary->state->fb &&
967 crtc->config->base.adjusted_mode.crtc_clock;
970 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
973 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
975 return crtc->config->cpu_transcoder;
978 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
980 i915_reg_t reg = PIPEDSL(pipe);
984 if (IS_GEN2(dev_priv))
985 line_mask = DSL_LINEMASK_GEN2;
987 line_mask = DSL_LINEMASK_GEN3;
989 line1 = I915_READ(reg) & line_mask;
991 line2 = I915_READ(reg) & line_mask;
993 return line1 == line2;
997 * intel_wait_for_pipe_off - wait for pipe to turn off
998 * @crtc: crtc whose pipe to wait for
1000 * After disabling a pipe, we can't wait for vblank in the usual way,
1001 * spinning on the vblank interrupt status bit, since we won't actually
1002 * see an interrupt when the pipe is disabled.
1004 * On Gen4 and above:
1005 * wait for the pipe register state bit to turn off
1008 * wait for the display line value to settle (it usually
1009 * ends up stopping at the start of the next frame).
1012 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1014 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1015 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1016 enum pipe pipe = crtc->pipe;
1018 if (INTEL_GEN(dev_priv) >= 4) {
1019 i915_reg_t reg = PIPECONF(cpu_transcoder);
1021 /* Wait for the Pipe State to go off */
1022 if (intel_wait_for_register(dev_priv,
1023 reg, I965_PIPECONF_ACTIVE, 0,
1025 WARN(1, "pipe_off wait timed out\n");
1027 /* Wait for the display line to settle */
1028 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1029 WARN(1, "pipe_off wait timed out\n");
1033 /* Only for pre-ILK configs */
1034 void assert_pll(struct drm_i915_private *dev_priv,
1035 enum pipe pipe, bool state)
1040 val = I915_READ(DPLL(pipe));
1041 cur_state = !!(val & DPLL_VCO_ENABLE);
1042 I915_STATE_WARN(cur_state != state,
1043 "PLL state assertion failure (expected %s, current %s)\n",
1044 onoff(state), onoff(cur_state));
1047 /* XXX: the dsi pll is shared between MIPI DSI ports */
1048 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1053 mutex_lock(&dev_priv->sb_lock);
1054 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1055 mutex_unlock(&dev_priv->sb_lock);
1057 cur_state = val & DSI_PLL_VCO_EN;
1058 I915_STATE_WARN(cur_state != state,
1059 "DSI PLL state assertion failure (expected %s, current %s)\n",
1060 onoff(state), onoff(cur_state));
1063 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1064 enum pipe pipe, bool state)
1067 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1070 if (HAS_DDI(dev_priv)) {
1071 /* DDI does not have a specific FDI_TX register */
1072 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1073 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1075 u32 val = I915_READ(FDI_TX_CTL(pipe));
1076 cur_state = !!(val & FDI_TX_ENABLE);
1078 I915_STATE_WARN(cur_state != state,
1079 "FDI TX state assertion failure (expected %s, current %s)\n",
1080 onoff(state), onoff(cur_state));
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086 enum pipe pipe, bool state)
1091 val = I915_READ(FDI_RX_CTL(pipe));
1092 cur_state = !!(val & FDI_RX_ENABLE);
1093 I915_STATE_WARN(cur_state != state,
1094 "FDI RX state assertion failure (expected %s, current %s)\n",
1095 onoff(state), onoff(cur_state));
1097 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1098 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1100 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1105 /* ILK FDI PLL is always enabled */
1106 if (IS_GEN5(dev_priv))
1109 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1110 if (HAS_DDI(dev_priv))
1113 val = I915_READ(FDI_TX_CTL(pipe));
1114 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1117 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1118 enum pipe pipe, bool state)
1123 val = I915_READ(FDI_RX_CTL(pipe));
1124 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1125 I915_STATE_WARN(cur_state != state,
1126 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1127 onoff(state), onoff(cur_state));
1130 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1134 enum pipe panel_pipe = PIPE_A;
1137 if (WARN_ON(HAS_DDI(dev_priv)))
1140 if (HAS_PCH_SPLIT(dev_priv)) {
1143 pp_reg = PP_CONTROL(0);
1144 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1146 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1147 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1148 panel_pipe = PIPE_B;
1149 /* XXX: else fix for eDP */
1150 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1151 /* presumably write lock depends on pipe, not port select */
1152 pp_reg = PP_CONTROL(pipe);
1155 pp_reg = PP_CONTROL(0);
1156 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1157 panel_pipe = PIPE_B;
1160 val = I915_READ(pp_reg);
1161 if (!(val & PANEL_POWER_ON) ||
1162 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1165 I915_STATE_WARN(panel_pipe == pipe && locked,
1166 "panel assertion failure, pipe %c regs locked\n",
1170 static void assert_cursor(struct drm_i915_private *dev_priv,
1171 enum pipe pipe, bool state)
1175 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1176 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1178 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1180 I915_STATE_WARN(cur_state != state,
1181 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1182 pipe_name(pipe), onoff(state), onoff(cur_state));
1184 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1185 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1187 void assert_pipe(struct drm_i915_private *dev_priv,
1188 enum pipe pipe, bool state)
1191 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1193 enum intel_display_power_domain power_domain;
1195 /* if we need the pipe quirk it must be always on */
1196 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1197 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1200 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203 cur_state = !!(val & PIPECONF_ENABLE);
1205 intel_display_power_put(dev_priv, power_domain);
1210 I915_STATE_WARN(cur_state != state,
1211 "pipe %c assertion failure (expected %s, current %s)\n",
1212 pipe_name(pipe), onoff(state), onoff(cur_state));
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216 enum plane plane, bool state)
1221 val = I915_READ(DSPCNTR(plane));
1222 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223 I915_STATE_WARN(cur_state != state,
1224 "plane %c assertion failure (expected %s, current %s)\n",
1225 plane_name(plane), onoff(state), onoff(cur_state));
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1236 /* Primary planes are fixed to pipes on gen4+ */
1237 if (INTEL_GEN(dev_priv) >= 4) {
1238 u32 val = I915_READ(DSPCNTR(pipe));
1239 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240 "plane %c assertion failure, should be disabled but not\n",
1245 /* Need to check both planes against the pipe */
1246 for_each_pipe(dev_priv, i) {
1247 u32 val = I915_READ(DSPCNTR(i));
1248 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249 DISPPLANE_SEL_PIPE_SHIFT;
1250 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252 plane_name(i), pipe_name(pipe));
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1261 if (INTEL_GEN(dev_priv) >= 9) {
1262 for_each_sprite(dev_priv, pipe, sprite) {
1263 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266 sprite, pipe_name(pipe));
1268 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269 for_each_sprite(dev_priv, pipe, sprite) {
1270 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271 I915_STATE_WARN(val & SP_ENABLE,
1272 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273 sprite_name(pipe, sprite), pipe_name(pipe));
1275 } else if (INTEL_GEN(dev_priv) >= 7) {
1276 u32 val = I915_READ(SPRCTL(pipe));
1277 I915_STATE_WARN(val & SPRITE_ENABLE,
1278 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279 plane_name(pipe), pipe_name(pipe));
1280 } else if (INTEL_GEN(dev_priv) >= 5) {
1281 u32 val = I915_READ(DVSCNTR(pipe));
1282 I915_STATE_WARN(val & DVS_ENABLE,
1283 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284 plane_name(pipe), pipe_name(pipe));
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1290 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291 drm_crtc_vblank_put(crtc);
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1300 val = I915_READ(PCH_TRANSCONF(pipe));
1301 enabled = !!(val & TRANS_ENABLE);
1302 I915_STATE_WARN(enabled,
1303 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe, u32 port_sel, u32 val)
1310 if ((val & DP_PORT_EN) == 0)
1313 if (HAS_PCH_CPT(dev_priv)) {
1314 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1317 } else if (IS_CHERRYVIEW(dev_priv)) {
1318 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1330 if ((val & SDVO_ENABLE) == 0)
1333 if (HAS_PCH_CPT(dev_priv)) {
1334 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1336 } else if (IS_CHERRYVIEW(dev_priv)) {
1337 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1340 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347 enum pipe pipe, u32 val)
1349 if ((val & LVDS_PORT_EN) == 0)
1352 if (HAS_PCH_CPT(dev_priv)) {
1353 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1356 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363 enum pipe pipe, u32 val)
1365 if ((val & ADPA_DAC_ENABLE) == 0)
1367 if (HAS_PCH_CPT(dev_priv)) {
1368 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1371 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378 enum pipe pipe, i915_reg_t reg,
1381 u32 val = I915_READ(reg);
1382 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384 i915_mmio_reg_offset(reg), pipe_name(pipe));
1386 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387 && (val & DP_PIPEB_SELECT),
1388 "IBX PCH dp port still using transcoder B\n");
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, i915_reg_t reg)
1394 u32 val = I915_READ(reg);
1395 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397 i915_mmio_reg_offset(reg), pipe_name(pipe));
1399 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400 && (val & SDVO_PIPE_B_SELECT),
1401 "IBX PCH hdmi port still using transcoder B\n");
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1409 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1413 val = I915_READ(PCH_ADPA);
1414 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415 "PCH VGA enabled on transcoder %c, should be disabled\n",
1418 val = I915_READ(PCH_LVDS);
1419 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1423 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429 const struct intel_crtc_state *pipe_config)
1431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432 enum pipe pipe = crtc->pipe;
1434 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435 POSTING_READ(DPLL(pipe));
1438 if (intel_wait_for_register(dev_priv,
1443 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447 const struct intel_crtc_state *pipe_config)
1449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450 enum pipe pipe = crtc->pipe;
1452 assert_pipe_disabled(dev_priv, pipe);
1454 /* PLL is protected by panel, make sure we can write it */
1455 assert_panel_unlocked(dev_priv, pipe);
1457 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458 _vlv_enable_pll(crtc, pipe_config);
1460 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461 POSTING_READ(DPLL_MD(pipe));
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466 const struct intel_crtc_state *pipe_config)
1468 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469 enum pipe pipe = crtc->pipe;
1470 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1473 mutex_lock(&dev_priv->sb_lock);
1475 /* Enable back the 10bit clock to display controller */
1476 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477 tmp |= DPIO_DCLKP_EN;
1478 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1480 mutex_unlock(&dev_priv->sb_lock);
1483 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1488 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1490 /* Check PLL is locked */
1491 if (intel_wait_for_register(dev_priv,
1492 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1494 DRM_ERROR("PLL %d failed to lock\n", pipe);
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498 const struct intel_crtc_state *pipe_config)
1500 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501 enum pipe pipe = crtc->pipe;
1503 assert_pipe_disabled(dev_priv, pipe);
1505 /* PLL is protected by panel, make sure we can write it */
1506 assert_panel_unlocked(dev_priv, pipe);
1508 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509 _chv_enable_pll(crtc, pipe_config);
1511 if (pipe != PIPE_A) {
1513 * WaPixelRepeatModeFixForC0:chv
1515 * DPLLCMD is AWOL. Use chicken bits to propagate
1516 * the value from DPLLBMD to either pipe B or C.
1518 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520 I915_WRITE(CBR4_VLV, 0);
1521 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1524 * DPLLB VGA mode also seems to cause problems.
1525 * We should always have it disabled.
1527 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1529 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530 POSTING_READ(DPLL_MD(pipe));
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1536 struct intel_crtc *crtc;
1539 for_each_intel_crtc(&dev_priv->drm, crtc) {
1540 count += crtc->base.state->active &&
1541 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550 i915_reg_t reg = DPLL(crtc->pipe);
1551 u32 dpll = crtc->config->dpll_hw_state.dpll;
1553 assert_pipe_disabled(dev_priv, crtc->pipe);
1555 /* PLL is protected by panel, make sure we can write it */
1556 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1557 assert_panel_unlocked(dev_priv, crtc->pipe);
1559 /* Enable DVO 2x clock on both PLLs if necessary */
1560 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1562 * It appears to be important that we don't enable this
1563 * for the current pipe before otherwise configuring the
1564 * PLL. No idea how this should be handled if multiple
1565 * DVO outputs are enabled simultaneosly.
1567 dpll |= DPLL_DVO_2X_MODE;
1568 I915_WRITE(DPLL(!crtc->pipe),
1569 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1573 * Apparently we need to have VGA mode enabled prior to changing
1574 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1575 * dividers, even though the register value does change.
1579 I915_WRITE(reg, dpll);
1581 /* Wait for the clocks to stabilize. */
1585 if (INTEL_GEN(dev_priv) >= 4) {
1586 I915_WRITE(DPLL_MD(crtc->pipe),
1587 crtc->config->dpll_hw_state.dpll_md);
1589 /* The pixel multiplier can only be updated once the
1590 * DPLL is enabled and the clocks are stable.
1592 * So write it again.
1594 I915_WRITE(reg, dpll);
1597 /* We do this three times for luck */
1598 I915_WRITE(reg, dpll);
1600 udelay(150); /* wait for warmup */
1601 I915_WRITE(reg, dpll);
1603 udelay(150); /* wait for warmup */
1604 I915_WRITE(reg, dpll);
1606 udelay(150); /* wait for warmup */
1610 * i9xx_disable_pll - disable a PLL
1611 * @dev_priv: i915 private structure
1612 * @pipe: pipe PLL to disable
1614 * Disable the PLL for @pipe, making sure the pipe is off first.
1616 * Note! This is for pre-ILK only.
1618 static void i9xx_disable_pll(struct intel_crtc *crtc)
1620 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1621 enum pipe pipe = crtc->pipe;
1623 /* Disable DVO 2x clock on both PLLs if necessary */
1624 if (IS_I830(dev_priv) &&
1625 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1626 !intel_num_dvo_pipes(dev_priv)) {
1627 I915_WRITE(DPLL(PIPE_B),
1628 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1629 I915_WRITE(DPLL(PIPE_A),
1630 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1633 /* Don't disable pipe or pipe PLLs if needed */
1634 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1635 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1638 /* Make sure the pipe isn't still relying on us */
1639 assert_pipe_disabled(dev_priv, pipe);
1641 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1642 POSTING_READ(DPLL(pipe));
1645 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1649 /* Make sure the pipe isn't still relying on us */
1650 assert_pipe_disabled(dev_priv, pipe);
1652 val = DPLL_INTEGRATED_REF_CLK_VLV |
1653 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1655 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1657 I915_WRITE(DPLL(pipe), val);
1658 POSTING_READ(DPLL(pipe));
1661 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1663 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1666 /* Make sure the pipe isn't still relying on us */
1667 assert_pipe_disabled(dev_priv, pipe);
1669 val = DPLL_SSC_REF_CLK_CHV |
1670 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1672 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1674 I915_WRITE(DPLL(pipe), val);
1675 POSTING_READ(DPLL(pipe));
1677 mutex_lock(&dev_priv->sb_lock);
1679 /* Disable 10bit clock to display controller */
1680 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1681 val &= ~DPIO_DCLKP_EN;
1682 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1684 mutex_unlock(&dev_priv->sb_lock);
1687 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1688 struct intel_digital_port *dport,
1689 unsigned int expected_mask)
1692 i915_reg_t dpll_reg;
1694 switch (dport->port) {
1696 port_mask = DPLL_PORTB_READY_MASK;
1700 port_mask = DPLL_PORTC_READY_MASK;
1702 expected_mask <<= 4;
1705 port_mask = DPLL_PORTD_READY_MASK;
1706 dpll_reg = DPIO_PHY_STATUS;
1712 if (intel_wait_for_register(dev_priv,
1713 dpll_reg, port_mask, expected_mask,
1715 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1716 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1719 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1722 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1725 uint32_t val, pipeconf_val;
1727 /* Make sure PCH DPLL is enabled */
1728 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1730 /* FDI must be feeding us bits for PCH ports */
1731 assert_fdi_tx_enabled(dev_priv, pipe);
1732 assert_fdi_rx_enabled(dev_priv, pipe);
1734 if (HAS_PCH_CPT(dev_priv)) {
1735 /* Workaround: Set the timing override bit before enabling the
1736 * pch transcoder. */
1737 reg = TRANS_CHICKEN2(pipe);
1738 val = I915_READ(reg);
1739 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1740 I915_WRITE(reg, val);
1743 reg = PCH_TRANSCONF(pipe);
1744 val = I915_READ(reg);
1745 pipeconf_val = I915_READ(PIPECONF(pipe));
1747 if (HAS_PCH_IBX(dev_priv)) {
1749 * Make the BPC in transcoder be consistent with
1750 * that in pipeconf reg. For HDMI we must use 8bpc
1751 * here for both 8bpc and 12bpc.
1753 val &= ~PIPECONF_BPC_MASK;
1754 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1755 val |= PIPECONF_8BPC;
1757 val |= pipeconf_val & PIPECONF_BPC_MASK;
1760 val &= ~TRANS_INTERLACE_MASK;
1761 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1762 if (HAS_PCH_IBX(dev_priv) &&
1763 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1764 val |= TRANS_LEGACY_INTERLACED_ILK;
1766 val |= TRANS_INTERLACED;
1768 val |= TRANS_PROGRESSIVE;
1770 I915_WRITE(reg, val | TRANS_ENABLE);
1771 if (intel_wait_for_register(dev_priv,
1772 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1774 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1777 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1778 enum transcoder cpu_transcoder)
1780 u32 val, pipeconf_val;
1782 /* FDI must be feeding us bits for PCH ports */
1783 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1784 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1786 /* Workaround: set timing override bit. */
1787 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1788 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1789 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1792 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1794 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1795 PIPECONF_INTERLACED_ILK)
1796 val |= TRANS_INTERLACED;
1798 val |= TRANS_PROGRESSIVE;
1800 I915_WRITE(LPT_TRANSCONF, val);
1801 if (intel_wait_for_register(dev_priv,
1806 DRM_ERROR("Failed to enable PCH transcoder\n");
1809 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1815 /* FDI relies on the transcoder */
1816 assert_fdi_tx_disabled(dev_priv, pipe);
1817 assert_fdi_rx_disabled(dev_priv, pipe);
1819 /* Ports must be off as well */
1820 assert_pch_ports_disabled(dev_priv, pipe);
1822 reg = PCH_TRANSCONF(pipe);
1823 val = I915_READ(reg);
1824 val &= ~TRANS_ENABLE;
1825 I915_WRITE(reg, val);
1826 /* wait for PCH transcoder off, transcoder state */
1827 if (intel_wait_for_register(dev_priv,
1828 reg, TRANS_STATE_ENABLE, 0,
1830 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1832 if (HAS_PCH_CPT(dev_priv)) {
1833 /* Workaround: Clear the timing override chicken bit again. */
1834 reg = TRANS_CHICKEN2(pipe);
1835 val = I915_READ(reg);
1836 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1837 I915_WRITE(reg, val);
1841 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1845 val = I915_READ(LPT_TRANSCONF);
1846 val &= ~TRANS_ENABLE;
1847 I915_WRITE(LPT_TRANSCONF, val);
1848 /* wait for PCH transcoder off, transcoder state */
1849 if (intel_wait_for_register(dev_priv,
1850 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1852 DRM_ERROR("Failed to disable PCH transcoder\n");
1854 /* Workaround: clear timing override bit. */
1855 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1857 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1860 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1862 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1864 WARN_ON(!crtc->config->has_pch_encoder);
1866 if (HAS_PCH_LPT(dev_priv))
1867 return TRANSCODER_A;
1869 return (enum transcoder) crtc->pipe;
1873 * intel_enable_pipe - enable a pipe, asserting requirements
1874 * @crtc: crtc responsible for the pipe
1876 * Enable @crtc's pipe, making sure that various hardware specific requirements
1877 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1879 static void intel_enable_pipe(struct intel_crtc *crtc)
1881 struct drm_device *dev = crtc->base.dev;
1882 struct drm_i915_private *dev_priv = to_i915(dev);
1883 enum pipe pipe = crtc->pipe;
1884 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1888 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1890 assert_planes_disabled(dev_priv, pipe);
1891 assert_cursor_disabled(dev_priv, pipe);
1892 assert_sprites_disabled(dev_priv, pipe);
1895 * A pipe without a PLL won't actually be able to drive bits from
1896 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1899 if (HAS_GMCH_DISPLAY(dev_priv)) {
1900 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1901 assert_dsi_pll_enabled(dev_priv);
1903 assert_pll_enabled(dev_priv, pipe);
1905 if (crtc->config->has_pch_encoder) {
1906 /* if driving the PCH, we need FDI enabled */
1907 assert_fdi_rx_pll_enabled(dev_priv,
1908 (enum pipe) intel_crtc_pch_transcoder(crtc));
1909 assert_fdi_tx_pll_enabled(dev_priv,
1910 (enum pipe) cpu_transcoder);
1912 /* FIXME: assert CPU port conditions for SNB+ */
1915 reg = PIPECONF(cpu_transcoder);
1916 val = I915_READ(reg);
1917 if (val & PIPECONF_ENABLE) {
1918 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1919 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1923 I915_WRITE(reg, val | PIPECONF_ENABLE);
1927 * Until the pipe starts DSL will read as 0, which would cause
1928 * an apparent vblank timestamp jump, which messes up also the
1929 * frame count when it's derived from the timestamps. So let's
1930 * wait for the pipe to start properly before we call
1931 * drm_crtc_vblank_on()
1933 if (dev->max_vblank_count == 0 &&
1934 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1935 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1939 * intel_disable_pipe - disable a pipe, asserting requirements
1940 * @crtc: crtc whose pipes is to be disabled
1942 * Disable the pipe of @crtc, making sure that various hardware
1943 * specific requirements are met, if applicable, e.g. plane
1944 * disabled, panel fitter off, etc.
1946 * Will wait until the pipe has shut down before returning.
1948 static void intel_disable_pipe(struct intel_crtc *crtc)
1950 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1951 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1952 enum pipe pipe = crtc->pipe;
1956 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1959 * Make sure planes won't keep trying to pump pixels to us,
1960 * or we might hang the display.
1962 assert_planes_disabled(dev_priv, pipe);
1963 assert_cursor_disabled(dev_priv, pipe);
1964 assert_sprites_disabled(dev_priv, pipe);
1966 reg = PIPECONF(cpu_transcoder);
1967 val = I915_READ(reg);
1968 if ((val & PIPECONF_ENABLE) == 0)
1972 * Double wide has implications for planes
1973 * so best keep it disabled when not needed.
1975 if (crtc->config->double_wide)
1976 val &= ~PIPECONF_DOUBLE_WIDE;
1978 /* Don't disable pipe or pipe PLLs if needed */
1979 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
1980 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1981 val &= ~PIPECONF_ENABLE;
1983 I915_WRITE(reg, val);
1984 if ((val & PIPECONF_ENABLE) == 0)
1985 intel_wait_for_pipe_off(crtc);
1988 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1990 return IS_GEN2(dev_priv) ? 2048 : 4096;
1994 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1996 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1997 unsigned int cpp = fb->format->cpp[plane];
1999 switch (fb->modifier) {
2000 case DRM_FORMAT_MOD_LINEAR:
2002 case I915_FORMAT_MOD_X_TILED:
2003 if (IS_GEN2(dev_priv))
2007 case I915_FORMAT_MOD_Y_TILED:
2008 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2012 case I915_FORMAT_MOD_Yf_TILED:
2028 MISSING_CASE(fb->modifier);
2034 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2036 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2039 return intel_tile_size(to_i915(fb->dev)) /
2040 intel_tile_width_bytes(fb, plane);
2043 /* Return the tile dimensions in pixel units */
2044 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2045 unsigned int *tile_width,
2046 unsigned int *tile_height)
2048 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2049 unsigned int cpp = fb->format->cpp[plane];
2051 *tile_width = tile_width_bytes / cpp;
2052 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2056 intel_fb_align_height(const struct drm_framebuffer *fb,
2057 int plane, unsigned int height)
2059 unsigned int tile_height = intel_tile_height(fb, plane);
2061 return ALIGN(height, tile_height);
2064 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2066 unsigned int size = 0;
2069 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2070 size += rot_info->plane[i].width * rot_info->plane[i].height;
2076 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2077 const struct drm_framebuffer *fb,
2078 unsigned int rotation)
2080 view->type = I915_GGTT_VIEW_NORMAL;
2081 if (drm_rotation_90_or_270(rotation)) {
2082 view->type = I915_GGTT_VIEW_ROTATED;
2083 view->rotated = to_intel_framebuffer(fb)->rot_info;
2087 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2089 if (INTEL_INFO(dev_priv)->gen >= 9)
2091 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2092 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2094 else if (INTEL_INFO(dev_priv)->gen >= 4)
2100 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2103 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2105 /* AUX_DIST needs only 4K alignment */
2106 if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2109 switch (fb->modifier) {
2110 case DRM_FORMAT_MOD_LINEAR:
2111 return intel_linear_alignment(dev_priv);
2112 case I915_FORMAT_MOD_X_TILED:
2113 if (INTEL_GEN(dev_priv) >= 9)
2116 case I915_FORMAT_MOD_Y_TILED:
2117 case I915_FORMAT_MOD_Yf_TILED:
2118 return 1 * 1024 * 1024;
2120 MISSING_CASE(fb->modifier);
2126 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2128 struct drm_device *dev = fb->dev;
2129 struct drm_i915_private *dev_priv = to_i915(dev);
2130 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2131 struct i915_ggtt_view view;
2132 struct i915_vma *vma;
2135 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2137 alignment = intel_surf_alignment(fb, 0);
2139 intel_fill_fb_ggtt_view(&view, fb, rotation);
2141 /* Note that the w/a also requires 64 PTE of padding following the
2142 * bo. We currently fill all unused PTE with the shadow page and so
2143 * we should always have valid PTE following the scanout preventing
2146 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2147 alignment = 256 * 1024;
2150 * Global gtt pte registers are special registers which actually forward
2151 * writes to a chunk of system memory. Which means that there is no risk
2152 * that the register values disappear as soon as we call
2153 * intel_runtime_pm_put(), so it is correct to wrap only the
2154 * pin/unpin/fence and not more.
2156 intel_runtime_pm_get(dev_priv);
2158 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2162 if (i915_vma_is_map_and_fenceable(vma)) {
2163 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2164 * fence, whereas 965+ only requires a fence if using
2165 * framebuffer compression. For simplicity, we always, when
2166 * possible, install a fence as the cost is not that onerous.
2168 * If we fail to fence the tiled scanout, then either the
2169 * modeset will reject the change (which is highly unlikely as
2170 * the affected systems, all but one, do not have unmappable
2171 * space) or we will not be able to enable full powersaving
2172 * techniques (also likely not to apply due to various limits
2173 * FBC and the like impose on the size of the buffer, which
2174 * presumably we violated anyway with this unmappable buffer).
2175 * Anyway, it is presumably better to stumble onwards with
2176 * something and try to run the system in a "less than optimal"
2177 * mode that matches the user configuration.
2179 if (i915_vma_get_fence(vma) == 0)
2180 i915_vma_pin_fence(vma);
2185 intel_runtime_pm_put(dev_priv);
2189 void intel_unpin_fb_vma(struct i915_vma *vma)
2191 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2193 i915_vma_unpin_fence(vma);
2194 i915_gem_object_unpin_from_display_plane(vma);
2198 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2199 unsigned int rotation)
2201 if (drm_rotation_90_or_270(rotation))
2202 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2204 return fb->pitches[plane];
2208 * Convert the x/y offsets into a linear offset.
2209 * Only valid with 0/180 degree rotation, which is fine since linear
2210 * offset is only used with linear buffers on pre-hsw and tiled buffers
2211 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2213 u32 intel_fb_xy_to_linear(int x, int y,
2214 const struct intel_plane_state *state,
2217 const struct drm_framebuffer *fb = state->base.fb;
2218 unsigned int cpp = fb->format->cpp[plane];
2219 unsigned int pitch = fb->pitches[plane];
2221 return y * pitch + x * cpp;
2225 * Add the x/y offsets derived from fb->offsets[] to the user
2226 * specified plane src x/y offsets. The resulting x/y offsets
2227 * specify the start of scanout from the beginning of the gtt mapping.
2229 void intel_add_fb_offsets(int *x, int *y,
2230 const struct intel_plane_state *state,
2234 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2235 unsigned int rotation = state->base.rotation;
2237 if (drm_rotation_90_or_270(rotation)) {
2238 *x += intel_fb->rotated[plane].x;
2239 *y += intel_fb->rotated[plane].y;
2241 *x += intel_fb->normal[plane].x;
2242 *y += intel_fb->normal[plane].y;
2247 * Input tile dimensions and pitch must already be
2248 * rotated to match x and y, and in pixel units.
2250 static u32 _intel_adjust_tile_offset(int *x, int *y,
2251 unsigned int tile_width,
2252 unsigned int tile_height,
2253 unsigned int tile_size,
2254 unsigned int pitch_tiles,
2258 unsigned int pitch_pixels = pitch_tiles * tile_width;
2261 WARN_ON(old_offset & (tile_size - 1));
2262 WARN_ON(new_offset & (tile_size - 1));
2263 WARN_ON(new_offset > old_offset);
2265 tiles = (old_offset - new_offset) / tile_size;
2267 *y += tiles / pitch_tiles * tile_height;
2268 *x += tiles % pitch_tiles * tile_width;
2270 /* minimize x in case it got needlessly big */
2271 *y += *x / pitch_pixels * tile_height;
2278 * Adjust the tile offset by moving the difference into
2281 static u32 intel_adjust_tile_offset(int *x, int *y,
2282 const struct intel_plane_state *state, int plane,
2283 u32 old_offset, u32 new_offset)
2285 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2286 const struct drm_framebuffer *fb = state->base.fb;
2287 unsigned int cpp = fb->format->cpp[plane];
2288 unsigned int rotation = state->base.rotation;
2289 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2291 WARN_ON(new_offset > old_offset);
2293 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2294 unsigned int tile_size, tile_width, tile_height;
2295 unsigned int pitch_tiles;
2297 tile_size = intel_tile_size(dev_priv);
2298 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2300 if (drm_rotation_90_or_270(rotation)) {
2301 pitch_tiles = pitch / tile_height;
2302 swap(tile_width, tile_height);
2304 pitch_tiles = pitch / (tile_width * cpp);
2307 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2308 tile_size, pitch_tiles,
2309 old_offset, new_offset);
2311 old_offset += *y * pitch + *x * cpp;
2313 *y = (old_offset - new_offset) / pitch;
2314 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2321 * Computes the linear offset to the base tile and adjusts
2322 * x, y. bytes per pixel is assumed to be a power-of-two.
2324 * In the 90/270 rotated case, x and y are assumed
2325 * to be already rotated to match the rotated GTT view, and
2326 * pitch is the tile_height aligned framebuffer height.
2328 * This function is used when computing the derived information
2329 * under intel_framebuffer, so using any of that information
2330 * here is not allowed. Anything under drm_framebuffer can be
2331 * used. This is why the user has to pass in the pitch since it
2332 * is specified in the rotated orientation.
2334 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2336 const struct drm_framebuffer *fb, int plane,
2338 unsigned int rotation,
2341 uint64_t fb_modifier = fb->modifier;
2342 unsigned int cpp = fb->format->cpp[plane];
2343 u32 offset, offset_aligned;
2348 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2349 unsigned int tile_size, tile_width, tile_height;
2350 unsigned int tile_rows, tiles, pitch_tiles;
2352 tile_size = intel_tile_size(dev_priv);
2353 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2355 if (drm_rotation_90_or_270(rotation)) {
2356 pitch_tiles = pitch / tile_height;
2357 swap(tile_width, tile_height);
2359 pitch_tiles = pitch / (tile_width * cpp);
2362 tile_rows = *y / tile_height;
2365 tiles = *x / tile_width;
2368 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2369 offset_aligned = offset & ~alignment;
2371 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2372 tile_size, pitch_tiles,
2373 offset, offset_aligned);
2375 offset = *y * pitch + *x * cpp;
2376 offset_aligned = offset & ~alignment;
2378 *y = (offset & alignment) / pitch;
2379 *x = ((offset & alignment) - *y * pitch) / cpp;
2382 return offset_aligned;
2385 u32 intel_compute_tile_offset(int *x, int *y,
2386 const struct intel_plane_state *state,
2389 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2390 const struct drm_framebuffer *fb = state->base.fb;
2391 unsigned int rotation = state->base.rotation;
2392 int pitch = intel_fb_pitch(fb, plane, rotation);
2393 u32 alignment = intel_surf_alignment(fb, plane);
2395 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2396 rotation, alignment);
2399 /* Convert the fb->offset[] linear offset into x/y offsets */
2400 static void intel_fb_offset_to_xy(int *x, int *y,
2401 const struct drm_framebuffer *fb, int plane)
2403 unsigned int cpp = fb->format->cpp[plane];
2404 unsigned int pitch = fb->pitches[plane];
2405 u32 linear_offset = fb->offsets[plane];
2407 *y = linear_offset / pitch;
2408 *x = linear_offset % pitch / cpp;
2411 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2413 switch (fb_modifier) {
2414 case I915_FORMAT_MOD_X_TILED:
2415 return I915_TILING_X;
2416 case I915_FORMAT_MOD_Y_TILED:
2417 return I915_TILING_Y;
2419 return I915_TILING_NONE;
2424 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2425 struct drm_framebuffer *fb)
2427 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2428 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2429 u32 gtt_offset_rotated = 0;
2430 unsigned int max_size = 0;
2431 int i, num_planes = fb->format->num_planes;
2432 unsigned int tile_size = intel_tile_size(dev_priv);
2434 for (i = 0; i < num_planes; i++) {
2435 unsigned int width, height;
2436 unsigned int cpp, size;
2440 cpp = fb->format->cpp[i];
2441 width = drm_framebuffer_plane_width(fb->width, fb, i);
2442 height = drm_framebuffer_plane_height(fb->height, fb, i);
2444 intel_fb_offset_to_xy(&x, &y, fb, i);
2447 * The fence (if used) is aligned to the start of the object
2448 * so having the framebuffer wrap around across the edge of the
2449 * fenced region doesn't really work. We have no API to configure
2450 * the fence start offset within the object (nor could we probably
2451 * on gen2/3). So it's just easier if we just require that the
2452 * fb layout agrees with the fence layout. We already check that the
2453 * fb stride matches the fence stride elsewhere.
2455 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2456 (x + width) * cpp > fb->pitches[i]) {
2457 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2463 * First pixel of the framebuffer from
2464 * the start of the normal gtt mapping.
2466 intel_fb->normal[i].x = x;
2467 intel_fb->normal[i].y = y;
2469 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2470 fb, i, fb->pitches[i],
2471 DRM_ROTATE_0, tile_size);
2472 offset /= tile_size;
2474 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2475 unsigned int tile_width, tile_height;
2476 unsigned int pitch_tiles;
2479 intel_tile_dims(fb, i, &tile_width, &tile_height);
2481 rot_info->plane[i].offset = offset;
2482 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2483 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2484 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2486 intel_fb->rotated[i].pitch =
2487 rot_info->plane[i].height * tile_height;
2489 /* how many tiles does this plane need */
2490 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2492 * If the plane isn't horizontally tile aligned,
2493 * we need one more tile.
2498 /* rotate the x/y offsets to match the GTT view */
2504 rot_info->plane[i].width * tile_width,
2505 rot_info->plane[i].height * tile_height,
2510 /* rotate the tile dimensions to match the GTT view */
2511 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2512 swap(tile_width, tile_height);
2515 * We only keep the x/y offsets, so push all of the
2516 * gtt offset into the x/y offsets.
2518 _intel_adjust_tile_offset(&x, &y,
2519 tile_width, tile_height,
2520 tile_size, pitch_tiles,
2521 gtt_offset_rotated * tile_size, 0);
2523 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2526 * First pixel of the framebuffer from
2527 * the start of the rotated gtt mapping.
2529 intel_fb->rotated[i].x = x;
2530 intel_fb->rotated[i].y = y;
2532 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2533 x * cpp, tile_size);
2536 /* how many tiles in total needed in the bo */
2537 max_size = max(max_size, offset + size);
2540 if (max_size * tile_size > intel_fb->obj->base.size) {
2541 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2542 max_size * tile_size, intel_fb->obj->base.size);
2549 static int i9xx_format_to_fourcc(int format)
2552 case DISPPLANE_8BPP:
2553 return DRM_FORMAT_C8;
2554 case DISPPLANE_BGRX555:
2555 return DRM_FORMAT_XRGB1555;
2556 case DISPPLANE_BGRX565:
2557 return DRM_FORMAT_RGB565;
2559 case DISPPLANE_BGRX888:
2560 return DRM_FORMAT_XRGB8888;
2561 case DISPPLANE_RGBX888:
2562 return DRM_FORMAT_XBGR8888;
2563 case DISPPLANE_BGRX101010:
2564 return DRM_FORMAT_XRGB2101010;
2565 case DISPPLANE_RGBX101010:
2566 return DRM_FORMAT_XBGR2101010;
2570 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2573 case PLANE_CTL_FORMAT_RGB_565:
2574 return DRM_FORMAT_RGB565;
2576 case PLANE_CTL_FORMAT_XRGB_8888:
2579 return DRM_FORMAT_ABGR8888;
2581 return DRM_FORMAT_XBGR8888;
2584 return DRM_FORMAT_ARGB8888;
2586 return DRM_FORMAT_XRGB8888;
2588 case PLANE_CTL_FORMAT_XRGB_2101010:
2590 return DRM_FORMAT_XBGR2101010;
2592 return DRM_FORMAT_XRGB2101010;
2597 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2598 struct intel_initial_plane_config *plane_config)
2600 struct drm_device *dev = crtc->base.dev;
2601 struct drm_i915_private *dev_priv = to_i915(dev);
2602 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2603 struct drm_i915_gem_object *obj = NULL;
2604 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2605 struct drm_framebuffer *fb = &plane_config->fb->base;
2606 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2607 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2610 size_aligned -= base_aligned;
2612 if (plane_config->size == 0)
2615 /* If the FB is too big, just don't use it since fbdev is not very
2616 * important and we should probably use that space with FBC or other
2618 if (size_aligned * 2 > ggtt->stolen_usable_size)
2621 mutex_lock(&dev->struct_mutex);
2622 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2626 mutex_unlock(&dev->struct_mutex);
2630 if (plane_config->tiling == I915_TILING_X)
2631 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2633 mode_cmd.pixel_format = fb->format->format;
2634 mode_cmd.width = fb->width;
2635 mode_cmd.height = fb->height;
2636 mode_cmd.pitches[0] = fb->pitches[0];
2637 mode_cmd.modifier[0] = fb->modifier;
2638 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2640 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2641 DRM_DEBUG_KMS("intel fb init failed\n");
2646 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2650 i915_gem_object_put(obj);
2654 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2656 update_state_fb(struct drm_plane *plane)
2658 if (plane->fb == plane->state->fb)
2661 if (plane->state->fb)
2662 drm_framebuffer_unreference(plane->state->fb);
2663 plane->state->fb = plane->fb;
2664 if (plane->state->fb)
2665 drm_framebuffer_reference(plane->state->fb);
2669 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2670 struct intel_plane_state *plane_state,
2673 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2675 plane_state->base.visible = visible;
2677 /* FIXME pre-g4x don't work like this */
2679 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2680 crtc_state->active_planes |= BIT(plane->id);
2682 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2683 crtc_state->active_planes &= ~BIT(plane->id);
2686 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2687 crtc_state->base.crtc->name,
2688 crtc_state->active_planes);
2692 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2693 struct intel_initial_plane_config *plane_config)
2695 struct drm_device *dev = intel_crtc->base.dev;
2696 struct drm_i915_private *dev_priv = to_i915(dev);
2698 struct drm_i915_gem_object *obj;
2699 struct drm_plane *primary = intel_crtc->base.primary;
2700 struct drm_plane_state *plane_state = primary->state;
2701 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2702 struct intel_plane *intel_plane = to_intel_plane(primary);
2703 struct intel_plane_state *intel_state =
2704 to_intel_plane_state(plane_state);
2705 struct drm_framebuffer *fb;
2707 if (!plane_config->fb)
2710 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2711 fb = &plane_config->fb->base;
2715 kfree(plane_config->fb);
2718 * Failed to alloc the obj, check to see if we should share
2719 * an fb with another CRTC instead
2721 for_each_crtc(dev, c) {
2722 struct intel_plane_state *state;
2724 if (c == &intel_crtc->base)
2727 if (!to_intel_crtc(c)->active)
2730 state = to_intel_plane_state(c->primary->state);
2734 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2735 fb = c->primary->fb;
2736 drm_framebuffer_reference(fb);
2742 * We've failed to reconstruct the BIOS FB. Current display state
2743 * indicates that the primary plane is visible, but has a NULL FB,
2744 * which will lead to problems later if we don't fix it up. The
2745 * simplest solution is to just disable the primary plane now and
2746 * pretend the BIOS never had it enabled.
2748 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2749 to_intel_plane_state(plane_state),
2751 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2752 trace_intel_disable_plane(primary, intel_crtc);
2753 intel_plane->disable_plane(primary, &intel_crtc->base);
2758 mutex_lock(&dev->struct_mutex);
2760 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2761 mutex_unlock(&dev->struct_mutex);
2762 if (IS_ERR(intel_state->vma)) {
2763 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2764 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2766 intel_state->vma = NULL;
2767 drm_framebuffer_unreference(fb);
2771 plane_state->src_x = 0;
2772 plane_state->src_y = 0;
2773 plane_state->src_w = fb->width << 16;
2774 plane_state->src_h = fb->height << 16;
2776 plane_state->crtc_x = 0;
2777 plane_state->crtc_y = 0;
2778 plane_state->crtc_w = fb->width;
2779 plane_state->crtc_h = fb->height;
2781 intel_state->base.src = drm_plane_state_src(plane_state);
2782 intel_state->base.dst = drm_plane_state_dest(plane_state);
2784 obj = intel_fb_obj(fb);
2785 if (i915_gem_object_is_tiled(obj))
2786 dev_priv->preserve_bios_swizzle = true;
2788 drm_framebuffer_reference(fb);
2789 primary->fb = primary->state->fb = fb;
2790 primary->crtc = primary->state->crtc = &intel_crtc->base;
2792 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2793 to_intel_plane_state(plane_state),
2796 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2797 &obj->frontbuffer_bits);
2800 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2801 unsigned int rotation)
2803 int cpp = fb->format->cpp[plane];
2805 switch (fb->modifier) {
2806 case DRM_FORMAT_MOD_LINEAR:
2807 case I915_FORMAT_MOD_X_TILED:
2820 case I915_FORMAT_MOD_Y_TILED:
2821 case I915_FORMAT_MOD_Yf_TILED:
2836 MISSING_CASE(fb->modifier);
2842 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2844 const struct drm_framebuffer *fb = plane_state->base.fb;
2845 unsigned int rotation = plane_state->base.rotation;
2846 int x = plane_state->base.src.x1 >> 16;
2847 int y = plane_state->base.src.y1 >> 16;
2848 int w = drm_rect_width(&plane_state->base.src) >> 16;
2849 int h = drm_rect_height(&plane_state->base.src) >> 16;
2850 int max_width = skl_max_plane_width(fb, 0, rotation);
2851 int max_height = 4096;
2852 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2854 if (w > max_width || h > max_height) {
2855 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2856 w, h, max_width, max_height);
2860 intel_add_fb_offsets(&x, &y, plane_state, 0);
2861 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2862 alignment = intel_surf_alignment(fb, 0);
2865 * AUX surface offset is specified as the distance from the
2866 * main surface offset, and it must be non-negative. Make
2867 * sure that is what we will get.
2869 if (offset > aux_offset)
2870 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2871 offset, aux_offset & ~(alignment - 1));
2874 * When using an X-tiled surface, the plane blows up
2875 * if the x offset + width exceed the stride.
2877 * TODO: linear and Y-tiled seem fine, Yf untested,
2879 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2880 int cpp = fb->format->cpp[0];
2882 while ((x + w) * cpp > fb->pitches[0]) {
2884 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2888 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2889 offset, offset - alignment);
2893 plane_state->main.offset = offset;
2894 plane_state->main.x = x;
2895 plane_state->main.y = y;
2900 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2902 const struct drm_framebuffer *fb = plane_state->base.fb;
2903 unsigned int rotation = plane_state->base.rotation;
2904 int max_width = skl_max_plane_width(fb, 1, rotation);
2905 int max_height = 4096;
2906 int x = plane_state->base.src.x1 >> 17;
2907 int y = plane_state->base.src.y1 >> 17;
2908 int w = drm_rect_width(&plane_state->base.src) >> 17;
2909 int h = drm_rect_height(&plane_state->base.src) >> 17;
2912 intel_add_fb_offsets(&x, &y, plane_state, 1);
2913 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2915 /* FIXME not quite sure how/if these apply to the chroma plane */
2916 if (w > max_width || h > max_height) {
2917 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2918 w, h, max_width, max_height);
2922 plane_state->aux.offset = offset;
2923 plane_state->aux.x = x;
2924 plane_state->aux.y = y;
2929 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2931 const struct drm_framebuffer *fb = plane_state->base.fb;
2932 unsigned int rotation = plane_state->base.rotation;
2935 if (!plane_state->base.visible)
2938 /* Rotate src coordinates to match rotated GTT view */
2939 if (drm_rotation_90_or_270(rotation))
2940 drm_rect_rotate(&plane_state->base.src,
2941 fb->width << 16, fb->height << 16,
2945 * Handle the AUX surface first since
2946 * the main surface setup depends on it.
2948 if (fb->format->format == DRM_FORMAT_NV12) {
2949 ret = skl_check_nv12_aux_surface(plane_state);
2953 plane_state->aux.offset = ~0xfff;
2954 plane_state->aux.x = 0;
2955 plane_state->aux.y = 0;
2958 ret = skl_check_main_surface(plane_state);
2965 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2966 const struct intel_plane_state *plane_state)
2968 struct drm_i915_private *dev_priv =
2969 to_i915(plane_state->base.plane->dev);
2970 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2971 const struct drm_framebuffer *fb = plane_state->base.fb;
2972 unsigned int rotation = plane_state->base.rotation;
2975 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
2977 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
2978 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2979 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2981 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2982 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2984 if (INTEL_GEN(dev_priv) < 4) {
2985 if (crtc->pipe == PIPE_B)
2986 dspcntr |= DISPPLANE_SEL_PIPE_B;
2989 switch (fb->format->format) {
2991 dspcntr |= DISPPLANE_8BPP;
2993 case DRM_FORMAT_XRGB1555:
2994 dspcntr |= DISPPLANE_BGRX555;
2996 case DRM_FORMAT_RGB565:
2997 dspcntr |= DISPPLANE_BGRX565;
2999 case DRM_FORMAT_XRGB8888:
3000 dspcntr |= DISPPLANE_BGRX888;
3002 case DRM_FORMAT_XBGR8888:
3003 dspcntr |= DISPPLANE_RGBX888;
3005 case DRM_FORMAT_XRGB2101010:
3006 dspcntr |= DISPPLANE_BGRX101010;
3008 case DRM_FORMAT_XBGR2101010:
3009 dspcntr |= DISPPLANE_RGBX101010;
3012 MISSING_CASE(fb->format->format);
3016 if (INTEL_GEN(dev_priv) >= 4 &&
3017 fb->modifier == I915_FORMAT_MOD_X_TILED)
3018 dspcntr |= DISPPLANE_TILED;
3020 if (rotation & DRM_ROTATE_180)
3021 dspcntr |= DISPPLANE_ROTATE_180;
3023 if (rotation & DRM_REFLECT_X)
3024 dspcntr |= DISPPLANE_MIRROR;
3029 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3031 struct drm_i915_private *dev_priv =
3032 to_i915(plane_state->base.plane->dev);
3033 int src_x = plane_state->base.src.x1 >> 16;
3034 int src_y = plane_state->base.src.y1 >> 16;
3037 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3039 if (INTEL_GEN(dev_priv) >= 4)
3040 offset = intel_compute_tile_offset(&src_x, &src_y,
3045 /* HSW/BDW do this automagically in hardware */
3046 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3047 unsigned int rotation = plane_state->base.rotation;
3048 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3049 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3051 if (rotation & DRM_ROTATE_180) {
3054 } else if (rotation & DRM_REFLECT_X) {
3059 plane_state->main.offset = offset;
3060 plane_state->main.x = src_x;
3061 plane_state->main.y = src_y;
3066 static void i9xx_update_primary_plane(struct drm_plane *primary,
3067 const struct intel_crtc_state *crtc_state,
3068 const struct intel_plane_state *plane_state)
3070 struct drm_i915_private *dev_priv = to_i915(primary->dev);
3071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3072 struct drm_framebuffer *fb = plane_state->base.fb;
3073 int plane = intel_crtc->plane;
3075 u32 dspcntr = plane_state->ctl;
3076 i915_reg_t reg = DSPCNTR(plane);
3077 int x = plane_state->main.x;
3078 int y = plane_state->main.y;
3079 unsigned long irqflags;
3081 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3083 if (INTEL_GEN(dev_priv) >= 4)
3084 intel_crtc->dspaddr_offset = plane_state->main.offset;
3086 intel_crtc->dspaddr_offset = linear_offset;
3088 intel_crtc->adjusted_x = x;
3089 intel_crtc->adjusted_y = y;
3091 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3093 if (INTEL_GEN(dev_priv) < 4) {
3094 /* pipesrc and dspsize control the size that is scaled from,
3095 * which should always be the user's requested size.
3097 I915_WRITE_FW(DSPSIZE(plane),
3098 ((crtc_state->pipe_src_h - 1) << 16) |
3099 (crtc_state->pipe_src_w - 1));
3100 I915_WRITE_FW(DSPPOS(plane), 0);
3101 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3102 I915_WRITE_FW(PRIMSIZE(plane),
3103 ((crtc_state->pipe_src_h - 1) << 16) |
3104 (crtc_state->pipe_src_w - 1));
3105 I915_WRITE_FW(PRIMPOS(plane), 0);
3106 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3109 I915_WRITE_FW(reg, dspcntr);
3111 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3112 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3113 I915_WRITE_FW(DSPSURF(plane),
3114 intel_plane_ggtt_offset(plane_state) +
3115 intel_crtc->dspaddr_offset);
3116 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3117 } else if (INTEL_GEN(dev_priv) >= 4) {
3118 I915_WRITE_FW(DSPSURF(plane),
3119 intel_plane_ggtt_offset(plane_state) +
3120 intel_crtc->dspaddr_offset);
3121 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3122 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3124 I915_WRITE_FW(DSPADDR(plane),
3125 intel_plane_ggtt_offset(plane_state) +
3126 intel_crtc->dspaddr_offset);
3128 POSTING_READ_FW(reg);
3130 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3133 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3134 struct drm_crtc *crtc)
3136 struct drm_device *dev = crtc->dev;
3137 struct drm_i915_private *dev_priv = to_i915(dev);
3138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3139 int plane = intel_crtc->plane;
3140 unsigned long irqflags;
3142 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3144 I915_WRITE_FW(DSPCNTR(plane), 0);
3145 if (INTEL_INFO(dev_priv)->gen >= 4)
3146 I915_WRITE_FW(DSPSURF(plane), 0);
3148 I915_WRITE_FW(DSPADDR(plane), 0);
3149 POSTING_READ_FW(DSPCNTR(plane));
3151 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3155 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3157 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3160 return intel_tile_width_bytes(fb, plane);
3163 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3165 struct drm_device *dev = intel_crtc->base.dev;
3166 struct drm_i915_private *dev_priv = to_i915(dev);
3168 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3169 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3170 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3174 * This function detaches (aka. unbinds) unused scalers in hardware
3176 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3178 struct intel_crtc_scaler_state *scaler_state;
3181 scaler_state = &intel_crtc->config->scaler_state;
3183 /* loop through and disable scalers that aren't in use */
3184 for (i = 0; i < intel_crtc->num_scalers; i++) {
3185 if (!scaler_state->scalers[i].in_use)
3186 skl_detach_scaler(intel_crtc, i);
3190 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3191 unsigned int rotation)
3195 if (plane >= fb->format->num_planes)
3198 stride = intel_fb_pitch(fb, plane, rotation);
3201 * The stride is either expressed as a multiple of 64 bytes chunks for
3202 * linear buffers or in number of tiles for tiled buffers.
3204 if (drm_rotation_90_or_270(rotation))
3205 stride /= intel_tile_height(fb, plane);
3207 stride /= intel_fb_stride_alignment(fb, plane);
3212 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3214 switch (pixel_format) {
3216 return PLANE_CTL_FORMAT_INDEXED;
3217 case DRM_FORMAT_RGB565:
3218 return PLANE_CTL_FORMAT_RGB_565;
3219 case DRM_FORMAT_XBGR8888:
3220 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3221 case DRM_FORMAT_XRGB8888:
3222 return PLANE_CTL_FORMAT_XRGB_8888;
3224 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3225 * to be already pre-multiplied. We need to add a knob (or a different
3226 * DRM_FORMAT) for user-space to configure that.
3228 case DRM_FORMAT_ABGR8888:
3229 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3230 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3231 case DRM_FORMAT_ARGB8888:
3232 return PLANE_CTL_FORMAT_XRGB_8888 |
3233 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3234 case DRM_FORMAT_XRGB2101010:
3235 return PLANE_CTL_FORMAT_XRGB_2101010;
3236 case DRM_FORMAT_XBGR2101010:
3237 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3238 case DRM_FORMAT_YUYV:
3239 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3240 case DRM_FORMAT_YVYU:
3241 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3242 case DRM_FORMAT_UYVY:
3243 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3244 case DRM_FORMAT_VYUY:
3245 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3247 MISSING_CASE(pixel_format);
3253 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3255 switch (fb_modifier) {
3256 case DRM_FORMAT_MOD_LINEAR:
3258 case I915_FORMAT_MOD_X_TILED:
3259 return PLANE_CTL_TILED_X;
3260 case I915_FORMAT_MOD_Y_TILED:
3261 return PLANE_CTL_TILED_Y;
3262 case I915_FORMAT_MOD_Yf_TILED:
3263 return PLANE_CTL_TILED_YF;
3265 MISSING_CASE(fb_modifier);
3271 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3277 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3278 * while i915 HW rotation is clockwise, thats why this swapping.
3281 return PLANE_CTL_ROTATE_270;
3282 case DRM_ROTATE_180:
3283 return PLANE_CTL_ROTATE_180;
3284 case DRM_ROTATE_270:
3285 return PLANE_CTL_ROTATE_90;
3287 MISSING_CASE(rotation);
3293 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3294 const struct intel_plane_state *plane_state)
3296 struct drm_i915_private *dev_priv =
3297 to_i915(plane_state->base.plane->dev);
3298 const struct drm_framebuffer *fb = plane_state->base.fb;
3299 unsigned int rotation = plane_state->base.rotation;
3300 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3303 plane_ctl = PLANE_CTL_ENABLE;
3305 if (!IS_GEMINILAKE(dev_priv)) {
3307 PLANE_CTL_PIPE_GAMMA_ENABLE |
3308 PLANE_CTL_PIPE_CSC_ENABLE |
3309 PLANE_CTL_PLANE_GAMMA_DISABLE;
3312 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3313 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3314 plane_ctl |= skl_plane_ctl_rotation(rotation);
3316 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3317 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3318 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3319 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3324 static void skylake_update_primary_plane(struct drm_plane *plane,
3325 const struct intel_crtc_state *crtc_state,
3326 const struct intel_plane_state *plane_state)
3328 struct drm_device *dev = plane->dev;
3329 struct drm_i915_private *dev_priv = to_i915(dev);
3330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3331 struct drm_framebuffer *fb = plane_state->base.fb;
3332 enum plane_id plane_id = to_intel_plane(plane)->id;
3333 enum pipe pipe = to_intel_plane(plane)->pipe;
3334 u32 plane_ctl = plane_state->ctl;
3335 unsigned int rotation = plane_state->base.rotation;
3336 u32 stride = skl_plane_stride(fb, 0, rotation);
3337 u32 surf_addr = plane_state->main.offset;
3338 int scaler_id = plane_state->scaler_id;
3339 int src_x = plane_state->main.x;
3340 int src_y = plane_state->main.y;
3341 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3342 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3343 int dst_x = plane_state->base.dst.x1;
3344 int dst_y = plane_state->base.dst.y1;
3345 int dst_w = drm_rect_width(&plane_state->base.dst);
3346 int dst_h = drm_rect_height(&plane_state->base.dst);
3347 unsigned long irqflags;
3349 /* Sizes are 0 based */
3355 intel_crtc->dspaddr_offset = surf_addr;
3357 intel_crtc->adjusted_x = src_x;
3358 intel_crtc->adjusted_y = src_y;
3360 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3362 if (IS_GEMINILAKE(dev_priv)) {
3363 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3364 PLANE_COLOR_PIPE_GAMMA_ENABLE |
3365 PLANE_COLOR_PIPE_CSC_ENABLE |
3366 PLANE_COLOR_PLANE_GAMMA_DISABLE);
3369 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3370 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3371 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3372 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3374 if (scaler_id >= 0) {
3375 uint32_t ps_ctrl = 0;
3377 WARN_ON(!dst_w || !dst_h);
3378 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3379 crtc_state->scaler_state.scalers[scaler_id].mode;
3380 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3381 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3382 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3383 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3384 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3386 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3389 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3390 intel_plane_ggtt_offset(plane_state) + surf_addr);
3392 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3394 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3397 static void skylake_disable_primary_plane(struct drm_plane *primary,
3398 struct drm_crtc *crtc)
3400 struct drm_device *dev = crtc->dev;
3401 struct drm_i915_private *dev_priv = to_i915(dev);
3402 enum plane_id plane_id = to_intel_plane(primary)->id;
3403 enum pipe pipe = to_intel_plane(primary)->pipe;
3404 unsigned long irqflags;
3406 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3408 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3409 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3410 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3412 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3415 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3417 struct intel_crtc *crtc;
3419 for_each_intel_crtc(&dev_priv->drm, crtc)
3420 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3423 static void intel_update_primary_planes(struct drm_device *dev)
3425 struct drm_crtc *crtc;
3427 for_each_crtc(dev, crtc) {
3428 struct intel_plane *plane = to_intel_plane(crtc->primary);
3429 struct intel_plane_state *plane_state =
3430 to_intel_plane_state(plane->base.state);
3432 if (plane_state->base.visible) {
3433 trace_intel_update_plane(&plane->base,
3434 to_intel_crtc(crtc));
3436 plane->update_plane(&plane->base,
3437 to_intel_crtc_state(crtc->state),
3444 __intel_display_resume(struct drm_device *dev,
3445 struct drm_atomic_state *state,
3446 struct drm_modeset_acquire_ctx *ctx)
3448 struct drm_crtc_state *crtc_state;
3449 struct drm_crtc *crtc;
3452 intel_modeset_setup_hw_state(dev);
3453 i915_redisable_vga(to_i915(dev));
3459 * We've duplicated the state, pointers to the old state are invalid.
3461 * Don't attempt to use the old state until we commit the duplicated state.
3463 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3465 * Force recalculation even if we restore
3466 * current state. With fast modeset this may not result
3467 * in a modeset when the state is compatible.
3469 crtc_state->mode_changed = true;
3472 /* ignore any reset values/BIOS leftovers in the WM registers */
3473 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3474 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3476 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3478 WARN_ON(ret == -EDEADLK);
3482 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3484 return intel_has_gpu_reset(dev_priv) &&
3485 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3488 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3490 struct drm_device *dev = &dev_priv->drm;
3491 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3492 struct drm_atomic_state *state;
3496 * Need mode_config.mutex so that we don't
3497 * trample ongoing ->detect() and whatnot.
3499 mutex_lock(&dev->mode_config.mutex);
3500 drm_modeset_acquire_init(ctx, 0);
3502 ret = drm_modeset_lock_all_ctx(dev, ctx);
3503 if (ret != -EDEADLK)
3506 drm_modeset_backoff(ctx);
3509 /* reset doesn't touch the display, but flips might get nuked anyway, */
3510 if (!i915.force_reset_modeset_test &&
3511 !gpu_reset_clobbers_display(dev_priv))
3515 * Disabling the crtcs gracefully seems nicer. Also the
3516 * g33 docs say we should at least disable all the planes.
3518 state = drm_atomic_helper_duplicate_state(dev, ctx);
3519 if (IS_ERR(state)) {
3520 ret = PTR_ERR(state);
3521 DRM_ERROR("Duplicating state failed with %i\n", ret);
3525 ret = drm_atomic_helper_disable_all(dev, ctx);
3527 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3528 drm_atomic_state_put(state);
3532 dev_priv->modeset_restore_state = state;
3533 state->acquire_ctx = ctx;
3536 void intel_finish_reset(struct drm_i915_private *dev_priv)
3538 struct drm_device *dev = &dev_priv->drm;
3539 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3540 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3544 * Flips in the rings will be nuked by the reset,
3545 * so complete all pending flips so that user space
3546 * will get its events and not get stuck.
3548 intel_complete_page_flips(dev_priv);
3550 dev_priv->modeset_restore_state = NULL;
3552 /* reset doesn't touch the display */
3553 if (!gpu_reset_clobbers_display(dev_priv)) {
3556 * Flips in the rings have been nuked by the reset,
3557 * so update the base address of all primary
3558 * planes to the the last fb to make sure we're
3559 * showing the correct fb after a reset.
3561 * FIXME: Atomic will make this obsolete since we won't schedule
3562 * CS-based flips (which might get lost in gpu resets) any more.
3564 intel_update_primary_planes(dev);
3566 ret = __intel_display_resume(dev, state, ctx);
3568 DRM_ERROR("Restoring old state failed with %i\n", ret);
3572 * The display has been reset as well,
3573 * so need a full re-initialization.
3575 intel_runtime_pm_disable_interrupts(dev_priv);
3576 intel_runtime_pm_enable_interrupts(dev_priv);
3578 intel_pps_unlock_regs_wa(dev_priv);
3579 intel_modeset_init_hw(dev);
3581 spin_lock_irq(&dev_priv->irq_lock);
3582 if (dev_priv->display.hpd_irq_setup)
3583 dev_priv->display.hpd_irq_setup(dev_priv);
3584 spin_unlock_irq(&dev_priv->irq_lock);
3586 ret = __intel_display_resume(dev, state, ctx);
3588 DRM_ERROR("Restoring old state failed with %i\n", ret);
3590 intel_hpd_init(dev_priv);
3594 drm_atomic_state_put(state);
3595 drm_modeset_drop_locks(ctx);
3596 drm_modeset_acquire_fini(ctx);
3597 mutex_unlock(&dev->mode_config.mutex);
3600 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3602 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3604 if (i915_reset_backoff(error))
3607 if (crtc->reset_count != i915_reset_count(error))
3613 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3615 struct drm_device *dev = crtc->dev;
3616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3619 if (abort_flip_on_reset(intel_crtc))
3622 spin_lock_irq(&dev->event_lock);
3623 pending = to_intel_crtc(crtc)->flip_work != NULL;
3624 spin_unlock_irq(&dev->event_lock);
3629 static void intel_update_pipe_config(struct intel_crtc *crtc,
3630 struct intel_crtc_state *old_crtc_state)
3632 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3633 struct intel_crtc_state *pipe_config =
3634 to_intel_crtc_state(crtc->base.state);
3636 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3637 crtc->base.mode = crtc->base.state->mode;
3640 * Update pipe size and adjust fitter if needed: the reason for this is
3641 * that in compute_mode_changes we check the native mode (not the pfit
3642 * mode) to see if we can flip rather than do a full mode set. In the
3643 * fastboot case, we'll flip, but if we don't update the pipesrc and
3644 * pfit state, we'll end up with a big fb scanned out into the wrong
3648 I915_WRITE(PIPESRC(crtc->pipe),
3649 ((pipe_config->pipe_src_w - 1) << 16) |
3650 (pipe_config->pipe_src_h - 1));
3652 /* on skylake this is done by detaching scalers */
3653 if (INTEL_GEN(dev_priv) >= 9) {
3654 skl_detach_scalers(crtc);
3656 if (pipe_config->pch_pfit.enabled)
3657 skylake_pfit_enable(crtc);
3658 } else if (HAS_PCH_SPLIT(dev_priv)) {
3659 if (pipe_config->pch_pfit.enabled)
3660 ironlake_pfit_enable(crtc);
3661 else if (old_crtc_state->pch_pfit.enabled)
3662 ironlake_pfit_disable(crtc, true);
3666 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3668 struct drm_device *dev = crtc->base.dev;
3669 struct drm_i915_private *dev_priv = to_i915(dev);
3670 int pipe = crtc->pipe;
3674 /* enable normal train */
3675 reg = FDI_TX_CTL(pipe);
3676 temp = I915_READ(reg);
3677 if (IS_IVYBRIDGE(dev_priv)) {
3678 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3679 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3681 temp &= ~FDI_LINK_TRAIN_NONE;
3682 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3684 I915_WRITE(reg, temp);
3686 reg = FDI_RX_CTL(pipe);
3687 temp = I915_READ(reg);
3688 if (HAS_PCH_CPT(dev_priv)) {
3689 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3690 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3692 temp &= ~FDI_LINK_TRAIN_NONE;
3693 temp |= FDI_LINK_TRAIN_NONE;
3695 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3697 /* wait one idle pattern time */
3701 /* IVB wants error correction enabled */
3702 if (IS_IVYBRIDGE(dev_priv))
3703 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3704 FDI_FE_ERRC_ENABLE);
3707 /* The FDI link training functions for ILK/Ibexpeak. */
3708 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3709 const struct intel_crtc_state *crtc_state)
3711 struct drm_device *dev = crtc->base.dev;
3712 struct drm_i915_private *dev_priv = to_i915(dev);
3713 int pipe = crtc->pipe;
3717 /* FDI needs bits from pipe first */
3718 assert_pipe_enabled(dev_priv, pipe);
3720 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3722 reg = FDI_RX_IMR(pipe);
3723 temp = I915_READ(reg);
3724 temp &= ~FDI_RX_SYMBOL_LOCK;
3725 temp &= ~FDI_RX_BIT_LOCK;
3726 I915_WRITE(reg, temp);
3730 /* enable CPU FDI TX and PCH FDI RX */
3731 reg = FDI_TX_CTL(pipe);
3732 temp = I915_READ(reg);
3733 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3734 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3735 temp &= ~FDI_LINK_TRAIN_NONE;
3736 temp |= FDI_LINK_TRAIN_PATTERN_1;
3737 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3739 reg = FDI_RX_CTL(pipe);
3740 temp = I915_READ(reg);
3741 temp &= ~FDI_LINK_TRAIN_NONE;
3742 temp |= FDI_LINK_TRAIN_PATTERN_1;
3743 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3748 /* Ironlake workaround, enable clock pointer after FDI enable*/
3749 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3750 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3751 FDI_RX_PHASE_SYNC_POINTER_EN);
3753 reg = FDI_RX_IIR(pipe);
3754 for (tries = 0; tries < 5; tries++) {
3755 temp = I915_READ(reg);
3756 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3758 if ((temp & FDI_RX_BIT_LOCK)) {
3759 DRM_DEBUG_KMS("FDI train 1 done.\n");
3760 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3765 DRM_ERROR("FDI train 1 fail!\n");
3768 reg = FDI_TX_CTL(pipe);
3769 temp = I915_READ(reg);
3770 temp &= ~FDI_LINK_TRAIN_NONE;
3771 temp |= FDI_LINK_TRAIN_PATTERN_2;
3772 I915_WRITE(reg, temp);
3774 reg = FDI_RX_CTL(pipe);
3775 temp = I915_READ(reg);
3776 temp &= ~FDI_LINK_TRAIN_NONE;
3777 temp |= FDI_LINK_TRAIN_PATTERN_2;
3778 I915_WRITE(reg, temp);
3783 reg = FDI_RX_IIR(pipe);
3784 for (tries = 0; tries < 5; tries++) {
3785 temp = I915_READ(reg);
3786 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3788 if (temp & FDI_RX_SYMBOL_LOCK) {
3789 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3790 DRM_DEBUG_KMS("FDI train 2 done.\n");
3795 DRM_ERROR("FDI train 2 fail!\n");
3797 DRM_DEBUG_KMS("FDI train done\n");
3801 static const int snb_b_fdi_train_param[] = {
3802 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3803 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3804 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3805 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3808 /* The FDI link training functions for SNB/Cougarpoint. */
3809 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3810 const struct intel_crtc_state *crtc_state)
3812 struct drm_device *dev = crtc->base.dev;
3813 struct drm_i915_private *dev_priv = to_i915(dev);
3814 int pipe = crtc->pipe;
3818 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3820 reg = FDI_RX_IMR(pipe);
3821 temp = I915_READ(reg);
3822 temp &= ~FDI_RX_SYMBOL_LOCK;
3823 temp &= ~FDI_RX_BIT_LOCK;
3824 I915_WRITE(reg, temp);
3829 /* enable CPU FDI TX and PCH FDI RX */
3830 reg = FDI_TX_CTL(pipe);
3831 temp = I915_READ(reg);
3832 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3833 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3834 temp &= ~FDI_LINK_TRAIN_NONE;
3835 temp |= FDI_LINK_TRAIN_PATTERN_1;
3836 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3838 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3839 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3841 I915_WRITE(FDI_RX_MISC(pipe),
3842 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3844 reg = FDI_RX_CTL(pipe);
3845 temp = I915_READ(reg);
3846 if (HAS_PCH_CPT(dev_priv)) {
3847 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3848 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3850 temp &= ~FDI_LINK_TRAIN_NONE;
3851 temp |= FDI_LINK_TRAIN_PATTERN_1;
3853 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3858 for (i = 0; i < 4; i++) {
3859 reg = FDI_TX_CTL(pipe);
3860 temp = I915_READ(reg);
3861 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3862 temp |= snb_b_fdi_train_param[i];
3863 I915_WRITE(reg, temp);
3868 for (retry = 0; retry < 5; retry++) {
3869 reg = FDI_RX_IIR(pipe);
3870 temp = I915_READ(reg);
3871 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3872 if (temp & FDI_RX_BIT_LOCK) {
3873 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3874 DRM_DEBUG_KMS("FDI train 1 done.\n");
3883 DRM_ERROR("FDI train 1 fail!\n");
3886 reg = FDI_TX_CTL(pipe);
3887 temp = I915_READ(reg);
3888 temp &= ~FDI_LINK_TRAIN_NONE;
3889 temp |= FDI_LINK_TRAIN_PATTERN_2;
3890 if (IS_GEN6(dev_priv)) {
3891 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3893 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3895 I915_WRITE(reg, temp);
3897 reg = FDI_RX_CTL(pipe);
3898 temp = I915_READ(reg);
3899 if (HAS_PCH_CPT(dev_priv)) {
3900 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3901 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3903 temp &= ~FDI_LINK_TRAIN_NONE;
3904 temp |= FDI_LINK_TRAIN_PATTERN_2;
3906 I915_WRITE(reg, temp);
3911 for (i = 0; i < 4; i++) {
3912 reg = FDI_TX_CTL(pipe);
3913 temp = I915_READ(reg);
3914 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3915 temp |= snb_b_fdi_train_param[i];
3916 I915_WRITE(reg, temp);
3921 for (retry = 0; retry < 5; retry++) {
3922 reg = FDI_RX_IIR(pipe);
3923 temp = I915_READ(reg);
3924 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3925 if (temp & FDI_RX_SYMBOL_LOCK) {
3926 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3927 DRM_DEBUG_KMS("FDI train 2 done.\n");
3936 DRM_ERROR("FDI train 2 fail!\n");
3938 DRM_DEBUG_KMS("FDI train done.\n");
3941 /* Manual link training for Ivy Bridge A0 parts */
3942 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3943 const struct intel_crtc_state *crtc_state)
3945 struct drm_device *dev = crtc->base.dev;
3946 struct drm_i915_private *dev_priv = to_i915(dev);
3947 int pipe = crtc->pipe;
3951 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3953 reg = FDI_RX_IMR(pipe);
3954 temp = I915_READ(reg);
3955 temp &= ~FDI_RX_SYMBOL_LOCK;
3956 temp &= ~FDI_RX_BIT_LOCK;
3957 I915_WRITE(reg, temp);
3962 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3963 I915_READ(FDI_RX_IIR(pipe)));
3965 /* Try each vswing and preemphasis setting twice before moving on */
3966 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3967 /* disable first in case we need to retry */
3968 reg = FDI_TX_CTL(pipe);
3969 temp = I915_READ(reg);
3970 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3971 temp &= ~FDI_TX_ENABLE;
3972 I915_WRITE(reg, temp);
3974 reg = FDI_RX_CTL(pipe);
3975 temp = I915_READ(reg);
3976 temp &= ~FDI_LINK_TRAIN_AUTO;
3977 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3978 temp &= ~FDI_RX_ENABLE;
3979 I915_WRITE(reg, temp);
3981 /* enable CPU FDI TX and PCH FDI RX */
3982 reg = FDI_TX_CTL(pipe);
3983 temp = I915_READ(reg);
3984 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3985 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3986 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3987 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3988 temp |= snb_b_fdi_train_param[j/2];
3989 temp |= FDI_COMPOSITE_SYNC;
3990 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3992 I915_WRITE(FDI_RX_MISC(pipe),
3993 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3995 reg = FDI_RX_CTL(pipe);
3996 temp = I915_READ(reg);
3997 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3998 temp |= FDI_COMPOSITE_SYNC;
3999 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4002 udelay(1); /* should be 0.5us */
4004 for (i = 0; i < 4; i++) {
4005 reg = FDI_RX_IIR(pipe);
4006 temp = I915_READ(reg);
4007 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4009 if (temp & FDI_RX_BIT_LOCK ||
4010 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4011 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4012 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4016 udelay(1); /* should be 0.5us */
4019 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4024 reg = FDI_TX_CTL(pipe);
4025 temp = I915_READ(reg);
4026 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4027 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4028 I915_WRITE(reg, temp);
4030 reg = FDI_RX_CTL(pipe);
4031 temp = I915_READ(reg);
4032 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4033 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4034 I915_WRITE(reg, temp);
4037 udelay(2); /* should be 1.5us */
4039 for (i = 0; i < 4; i++) {
4040 reg = FDI_RX_IIR(pipe);
4041 temp = I915_READ(reg);
4042 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4044 if (temp & FDI_RX_SYMBOL_LOCK ||
4045 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4046 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4047 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4051 udelay(2); /* should be 1.5us */
4054 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4058 DRM_DEBUG_KMS("FDI train done.\n");
4061 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4063 struct drm_device *dev = intel_crtc->base.dev;
4064 struct drm_i915_private *dev_priv = to_i915(dev);
4065 int pipe = intel_crtc->pipe;
4069 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4070 reg = FDI_RX_CTL(pipe);
4071 temp = I915_READ(reg);
4072 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4073 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4074 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4075 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4080 /* Switch from Rawclk to PCDclk */
4081 temp = I915_READ(reg);
4082 I915_WRITE(reg, temp | FDI_PCDCLK);
4087 /* Enable CPU FDI TX PLL, always on for Ironlake */
4088 reg = FDI_TX_CTL(pipe);
4089 temp = I915_READ(reg);
4090 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4091 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4098 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4100 struct drm_device *dev = intel_crtc->base.dev;
4101 struct drm_i915_private *dev_priv = to_i915(dev);
4102 int pipe = intel_crtc->pipe;
4106 /* Switch from PCDclk to Rawclk */
4107 reg = FDI_RX_CTL(pipe);
4108 temp = I915_READ(reg);
4109 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4111 /* Disable CPU FDI TX PLL */
4112 reg = FDI_TX_CTL(pipe);
4113 temp = I915_READ(reg);
4114 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4119 reg = FDI_RX_CTL(pipe);
4120 temp = I915_READ(reg);
4121 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4123 /* Wait for the clocks to turn off. */
4128 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4130 struct drm_device *dev = crtc->dev;
4131 struct drm_i915_private *dev_priv = to_i915(dev);
4132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4133 int pipe = intel_crtc->pipe;
4137 /* disable CPU FDI tx and PCH FDI rx */
4138 reg = FDI_TX_CTL(pipe);
4139 temp = I915_READ(reg);
4140 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4143 reg = FDI_RX_CTL(pipe);
4144 temp = I915_READ(reg);
4145 temp &= ~(0x7 << 16);
4146 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4147 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4152 /* Ironlake workaround, disable clock pointer after downing FDI */
4153 if (HAS_PCH_IBX(dev_priv))
4154 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4156 /* still set train pattern 1 */
4157 reg = FDI_TX_CTL(pipe);
4158 temp = I915_READ(reg);
4159 temp &= ~FDI_LINK_TRAIN_NONE;
4160 temp |= FDI_LINK_TRAIN_PATTERN_1;
4161 I915_WRITE(reg, temp);
4163 reg = FDI_RX_CTL(pipe);
4164 temp = I915_READ(reg);
4165 if (HAS_PCH_CPT(dev_priv)) {
4166 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4167 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4169 temp &= ~FDI_LINK_TRAIN_NONE;
4170 temp |= FDI_LINK_TRAIN_PATTERN_1;
4172 /* BPC in FDI rx is consistent with that in PIPECONF */
4173 temp &= ~(0x07 << 16);
4174 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4175 I915_WRITE(reg, temp);
4181 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4183 struct intel_crtc *crtc;
4185 /* Note that we don't need to be called with mode_config.lock here
4186 * as our list of CRTC objects is static for the lifetime of the
4187 * device and so cannot disappear as we iterate. Similarly, we can
4188 * happily treat the predicates as racy, atomic checks as userspace
4189 * cannot claim and pin a new fb without at least acquring the
4190 * struct_mutex and so serialising with us.
4192 for_each_intel_crtc(&dev_priv->drm, crtc) {
4193 if (atomic_read(&crtc->unpin_work_count) == 0)
4196 if (crtc->flip_work)
4197 intel_wait_for_vblank(dev_priv, crtc->pipe);
4205 static void page_flip_completed(struct intel_crtc *intel_crtc)
4207 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4208 struct intel_flip_work *work = intel_crtc->flip_work;
4210 intel_crtc->flip_work = NULL;
4213 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4215 drm_crtc_vblank_put(&intel_crtc->base);
4217 wake_up_all(&dev_priv->pending_flip_queue);
4218 trace_i915_flip_complete(intel_crtc->plane,
4219 work->pending_flip_obj);
4221 queue_work(dev_priv->wq, &work->unpin_work);
4224 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4226 struct drm_device *dev = crtc->dev;
4227 struct drm_i915_private *dev_priv = to_i915(dev);
4230 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4232 ret = wait_event_interruptible_timeout(
4233 dev_priv->pending_flip_queue,
4234 !intel_crtc_has_pending_flip(crtc),
4241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4242 struct intel_flip_work *work;
4244 spin_lock_irq(&dev->event_lock);
4245 work = intel_crtc->flip_work;
4246 if (work && !is_mmio_work(work)) {
4247 WARN_ONCE(1, "Removing stuck page flip\n");
4248 page_flip_completed(intel_crtc);
4250 spin_unlock_irq(&dev->event_lock);
4256 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4260 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4262 mutex_lock(&dev_priv->sb_lock);
4264 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4265 temp |= SBI_SSCCTL_DISABLE;
4266 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4268 mutex_unlock(&dev_priv->sb_lock);
4271 /* Program iCLKIP clock to the desired frequency */
4272 static void lpt_program_iclkip(struct intel_crtc *crtc)
4274 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4275 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4276 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4279 lpt_disable_iclkip(dev_priv);
4281 /* The iCLK virtual clock root frequency is in MHz,
4282 * but the adjusted_mode->crtc_clock in in KHz. To get the
4283 * divisors, it is necessary to divide one by another, so we
4284 * convert the virtual clock precision to KHz here for higher
4287 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4288 u32 iclk_virtual_root_freq = 172800 * 1000;
4289 u32 iclk_pi_range = 64;
4290 u32 desired_divisor;
4292 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4294 divsel = (desired_divisor / iclk_pi_range) - 2;
4295 phaseinc = desired_divisor % iclk_pi_range;
4298 * Near 20MHz is a corner case which is
4299 * out of range for the 7-bit divisor
4305 /* This should not happen with any sane values */
4306 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4307 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4308 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4309 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4311 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4318 mutex_lock(&dev_priv->sb_lock);
4320 /* Program SSCDIVINTPHASE6 */
4321 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4322 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4323 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4324 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4325 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4326 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4327 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4328 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4330 /* Program SSCAUXDIV */
4331 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4332 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4333 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4334 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4336 /* Enable modulator and associated divider */
4337 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4338 temp &= ~SBI_SSCCTL_DISABLE;
4339 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4341 mutex_unlock(&dev_priv->sb_lock);
4343 /* Wait for initialization time */
4346 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4349 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4351 u32 divsel, phaseinc, auxdiv;
4352 u32 iclk_virtual_root_freq = 172800 * 1000;
4353 u32 iclk_pi_range = 64;
4354 u32 desired_divisor;
4357 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4360 mutex_lock(&dev_priv->sb_lock);
4362 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4363 if (temp & SBI_SSCCTL_DISABLE) {
4364 mutex_unlock(&dev_priv->sb_lock);
4368 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4369 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4370 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4371 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4372 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4374 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4375 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4376 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4378 mutex_unlock(&dev_priv->sb_lock);
4380 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4382 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4383 desired_divisor << auxdiv);
4386 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4387 enum pipe pch_transcoder)
4389 struct drm_device *dev = crtc->base.dev;
4390 struct drm_i915_private *dev_priv = to_i915(dev);
4391 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4393 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4394 I915_READ(HTOTAL(cpu_transcoder)));
4395 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4396 I915_READ(HBLANK(cpu_transcoder)));
4397 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4398 I915_READ(HSYNC(cpu_transcoder)));
4400 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4401 I915_READ(VTOTAL(cpu_transcoder)));
4402 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4403 I915_READ(VBLANK(cpu_transcoder)));
4404 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4405 I915_READ(VSYNC(cpu_transcoder)));
4406 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4407 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4410 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4412 struct drm_i915_private *dev_priv = to_i915(dev);
4415 temp = I915_READ(SOUTH_CHICKEN1);
4416 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4419 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4420 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4422 temp &= ~FDI_BC_BIFURCATION_SELECT;
4424 temp |= FDI_BC_BIFURCATION_SELECT;
4426 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4427 I915_WRITE(SOUTH_CHICKEN1, temp);
4428 POSTING_READ(SOUTH_CHICKEN1);
4431 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4433 struct drm_device *dev = intel_crtc->base.dev;
4435 switch (intel_crtc->pipe) {
4439 if (intel_crtc->config->fdi_lanes > 2)
4440 cpt_set_fdi_bc_bifurcation(dev, false);
4442 cpt_set_fdi_bc_bifurcation(dev, true);
4446 cpt_set_fdi_bc_bifurcation(dev, true);
4454 /* Return which DP Port should be selected for Transcoder DP control */
4456 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4458 struct drm_device *dev = crtc->base.dev;
4459 struct intel_encoder *encoder;
4461 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4462 if (encoder->type == INTEL_OUTPUT_DP ||
4463 encoder->type == INTEL_OUTPUT_EDP)
4464 return enc_to_dig_port(&encoder->base)->port;
4471 * Enable PCH resources required for PCH ports:
4473 * - FDI training & RX/TX
4474 * - update transcoder timings
4475 * - DP transcoding bits
4478 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4480 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4481 struct drm_device *dev = crtc->base.dev;
4482 struct drm_i915_private *dev_priv = to_i915(dev);
4483 int pipe = crtc->pipe;
4486 assert_pch_transcoder_disabled(dev_priv, pipe);
4488 if (IS_IVYBRIDGE(dev_priv))
4489 ivybridge_update_fdi_bc_bifurcation(crtc);
4491 /* Write the TU size bits before fdi link training, so that error
4492 * detection works. */
4493 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4494 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4496 /* For PCH output, training FDI link */
4497 dev_priv->display.fdi_link_train(crtc, crtc_state);
4499 /* We need to program the right clock selection before writing the pixel
4500 * mutliplier into the DPLL. */
4501 if (HAS_PCH_CPT(dev_priv)) {
4504 temp = I915_READ(PCH_DPLL_SEL);
4505 temp |= TRANS_DPLL_ENABLE(pipe);
4506 sel = TRANS_DPLLB_SEL(pipe);
4507 if (crtc_state->shared_dpll ==
4508 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4512 I915_WRITE(PCH_DPLL_SEL, temp);
4515 /* XXX: pch pll's can be enabled any time before we enable the PCH
4516 * transcoder, and we actually should do this to not upset any PCH
4517 * transcoder that already use the clock when we share it.
4519 * Note that enable_shared_dpll tries to do the right thing, but
4520 * get_shared_dpll unconditionally resets the pll - we need that to have
4521 * the right LVDS enable sequence. */
4522 intel_enable_shared_dpll(crtc);
4524 /* set transcoder timing, panel must allow it */
4525 assert_panel_unlocked(dev_priv, pipe);
4526 ironlake_pch_transcoder_set_timings(crtc, pipe);
4528 intel_fdi_normal_train(crtc);
4530 /* For PCH DP, enable TRANS_DP_CTL */
4531 if (HAS_PCH_CPT(dev_priv) &&
4532 intel_crtc_has_dp_encoder(crtc_state)) {
4533 const struct drm_display_mode *adjusted_mode =
4534 &crtc_state->base.adjusted_mode;
4535 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4536 i915_reg_t reg = TRANS_DP_CTL(pipe);
4537 temp = I915_READ(reg);
4538 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4539 TRANS_DP_SYNC_MASK |
4541 temp |= TRANS_DP_OUTPUT_ENABLE;
4542 temp |= bpc << 9; /* same format but at 11:9 */
4544 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4545 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4546 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4547 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4549 switch (intel_trans_dp_port_sel(crtc)) {
4551 temp |= TRANS_DP_PORT_SEL_B;
4554 temp |= TRANS_DP_PORT_SEL_C;
4557 temp |= TRANS_DP_PORT_SEL_D;
4563 I915_WRITE(reg, temp);
4566 ironlake_enable_pch_transcoder(dev_priv, pipe);
4569 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4571 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4572 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4573 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4575 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4577 lpt_program_iclkip(crtc);
4579 /* Set transcoder timing. */
4580 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4582 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4585 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4587 struct drm_i915_private *dev_priv = to_i915(dev);
4588 i915_reg_t dslreg = PIPEDSL(pipe);
4591 temp = I915_READ(dslreg);
4593 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4594 if (wait_for(I915_READ(dslreg) != temp, 5))
4595 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4600 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4601 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4602 int src_w, int src_h, int dst_w, int dst_h)
4604 struct intel_crtc_scaler_state *scaler_state =
4605 &crtc_state->scaler_state;
4606 struct intel_crtc *intel_crtc =
4607 to_intel_crtc(crtc_state->base.crtc);
4610 need_scaling = drm_rotation_90_or_270(rotation) ?
4611 (src_h != dst_w || src_w != dst_h):
4612 (src_w != dst_w || src_h != dst_h);
4615 * if plane is being disabled or scaler is no more required or force detach
4616 * - free scaler binded to this plane/crtc
4617 * - in order to do this, update crtc->scaler_usage
4619 * Here scaler state in crtc_state is set free so that
4620 * scaler can be assigned to other user. Actual register
4621 * update to free the scaler is done in plane/panel-fit programming.
4622 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4624 if (force_detach || !need_scaling) {
4625 if (*scaler_id >= 0) {
4626 scaler_state->scaler_users &= ~(1 << scaler_user);
4627 scaler_state->scalers[*scaler_id].in_use = 0;
4629 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4630 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4631 intel_crtc->pipe, scaler_user, *scaler_id,
4632 scaler_state->scaler_users);
4639 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4640 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4642 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4643 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4644 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4645 "size is out of scaler range\n",
4646 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4650 /* mark this plane as a scaler user in crtc_state */
4651 scaler_state->scaler_users |= (1 << scaler_user);
4652 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4653 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4654 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4655 scaler_state->scaler_users);
4661 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4663 * @state: crtc's scaler state
4666 * 0 - scaler_usage updated successfully
4667 * error - requested scaling cannot be supported or other error condition
4669 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4671 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4673 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4674 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4675 state->pipe_src_w, state->pipe_src_h,
4676 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4680 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4682 * @state: crtc's scaler state
4683 * @plane_state: atomic plane state to update
4686 * 0 - scaler_usage updated successfully
4687 * error - requested scaling cannot be supported or other error condition
4689 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4690 struct intel_plane_state *plane_state)
4693 struct intel_plane *intel_plane =
4694 to_intel_plane(plane_state->base.plane);
4695 struct drm_framebuffer *fb = plane_state->base.fb;
4698 bool force_detach = !fb || !plane_state->base.visible;
4700 ret = skl_update_scaler(crtc_state, force_detach,
4701 drm_plane_index(&intel_plane->base),
4702 &plane_state->scaler_id,
4703 plane_state->base.rotation,
4704 drm_rect_width(&plane_state->base.src) >> 16,
4705 drm_rect_height(&plane_state->base.src) >> 16,
4706 drm_rect_width(&plane_state->base.dst),
4707 drm_rect_height(&plane_state->base.dst));
4709 if (ret || plane_state->scaler_id < 0)
4712 /* check colorkey */
4713 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4714 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4715 intel_plane->base.base.id,
4716 intel_plane->base.name);
4720 /* Check src format */
4721 switch (fb->format->format) {
4722 case DRM_FORMAT_RGB565:
4723 case DRM_FORMAT_XBGR8888:
4724 case DRM_FORMAT_XRGB8888:
4725 case DRM_FORMAT_ABGR8888:
4726 case DRM_FORMAT_ARGB8888:
4727 case DRM_FORMAT_XRGB2101010:
4728 case DRM_FORMAT_XBGR2101010:
4729 case DRM_FORMAT_YUYV:
4730 case DRM_FORMAT_YVYU:
4731 case DRM_FORMAT_UYVY:
4732 case DRM_FORMAT_VYUY:
4735 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4736 intel_plane->base.base.id, intel_plane->base.name,
4737 fb->base.id, fb->format->format);
4744 static void skylake_scaler_disable(struct intel_crtc *crtc)
4748 for (i = 0; i < crtc->num_scalers; i++)
4749 skl_detach_scaler(crtc, i);
4752 static void skylake_pfit_enable(struct intel_crtc *crtc)
4754 struct drm_device *dev = crtc->base.dev;
4755 struct drm_i915_private *dev_priv = to_i915(dev);
4756 int pipe = crtc->pipe;
4757 struct intel_crtc_scaler_state *scaler_state =
4758 &crtc->config->scaler_state;
4760 if (crtc->config->pch_pfit.enabled) {
4763 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4766 id = scaler_state->scaler_id;
4767 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4768 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4769 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4770 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4774 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4776 struct drm_device *dev = crtc->base.dev;
4777 struct drm_i915_private *dev_priv = to_i915(dev);
4778 int pipe = crtc->pipe;
4780 if (crtc->config->pch_pfit.enabled) {
4781 /* Force use of hard-coded filter coefficients
4782 * as some pre-programmed values are broken,
4785 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4786 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4787 PF_PIPE_SEL_IVB(pipe));
4789 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4790 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4791 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4795 void hsw_enable_ips(struct intel_crtc *crtc)
4797 struct drm_device *dev = crtc->base.dev;
4798 struct drm_i915_private *dev_priv = to_i915(dev);
4800 if (!crtc->config->ips_enabled)
4804 * We can only enable IPS after we enable a plane and wait for a vblank
4805 * This function is called from post_plane_update, which is run after
4809 assert_plane_enabled(dev_priv, crtc->plane);
4810 if (IS_BROADWELL(dev_priv)) {
4811 mutex_lock(&dev_priv->rps.hw_lock);
4812 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4813 mutex_unlock(&dev_priv->rps.hw_lock);
4814 /* Quoting Art Runyan: "its not safe to expect any particular
4815 * value in IPS_CTL bit 31 after enabling IPS through the
4816 * mailbox." Moreover, the mailbox may return a bogus state,
4817 * so we need to just enable it and continue on.
4820 I915_WRITE(IPS_CTL, IPS_ENABLE);
4821 /* The bit only becomes 1 in the next vblank, so this wait here
4822 * is essentially intel_wait_for_vblank. If we don't have this
4823 * and don't wait for vblanks until the end of crtc_enable, then
4824 * the HW state readout code will complain that the expected
4825 * IPS_CTL value is not the one we read. */
4826 if (intel_wait_for_register(dev_priv,
4827 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4829 DRM_ERROR("Timed out waiting for IPS enable\n");
4833 void hsw_disable_ips(struct intel_crtc *crtc)
4835 struct drm_device *dev = crtc->base.dev;
4836 struct drm_i915_private *dev_priv = to_i915(dev);
4838 if (!crtc->config->ips_enabled)
4841 assert_plane_enabled(dev_priv, crtc->plane);
4842 if (IS_BROADWELL(dev_priv)) {
4843 mutex_lock(&dev_priv->rps.hw_lock);
4844 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4845 mutex_unlock(&dev_priv->rps.hw_lock);
4846 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4847 if (intel_wait_for_register(dev_priv,
4848 IPS_CTL, IPS_ENABLE, 0,
4850 DRM_ERROR("Timed out waiting for IPS disable\n");
4852 I915_WRITE(IPS_CTL, 0);
4853 POSTING_READ(IPS_CTL);
4856 /* We need to wait for a vblank before we can disable the plane. */
4857 intel_wait_for_vblank(dev_priv, crtc->pipe);
4860 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4862 if (intel_crtc->overlay) {
4863 struct drm_device *dev = intel_crtc->base.dev;
4864 struct drm_i915_private *dev_priv = to_i915(dev);
4866 mutex_lock(&dev->struct_mutex);
4867 dev_priv->mm.interruptible = false;
4868 (void) intel_overlay_switch_off(intel_crtc->overlay);
4869 dev_priv->mm.interruptible = true;
4870 mutex_unlock(&dev->struct_mutex);
4873 /* Let userspace switch the overlay on again. In most cases userspace
4874 * has to recompute where to put it anyway.
4879 * intel_post_enable_primary - Perform operations after enabling primary plane
4880 * @crtc: the CRTC whose primary plane was just enabled
4882 * Performs potentially sleeping operations that must be done after the primary
4883 * plane is enabled, such as updating FBC and IPS. Note that this may be
4884 * called due to an explicit primary plane update, or due to an implicit
4885 * re-enable that is caused when a sprite plane is updated to no longer
4886 * completely hide the primary plane.
4889 intel_post_enable_primary(struct drm_crtc *crtc)
4891 struct drm_device *dev = crtc->dev;
4892 struct drm_i915_private *dev_priv = to_i915(dev);
4893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4894 int pipe = intel_crtc->pipe;
4897 * FIXME IPS should be fine as long as one plane is
4898 * enabled, but in practice it seems to have problems
4899 * when going from primary only to sprite only and vice
4902 hsw_enable_ips(intel_crtc);
4905 * Gen2 reports pipe underruns whenever all planes are disabled.
4906 * So don't enable underrun reporting before at least some planes
4908 * FIXME: Need to fix the logic to work when we turn off all planes
4909 * but leave the pipe running.
4911 if (IS_GEN2(dev_priv))
4912 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4914 /* Underruns don't always raise interrupts, so check manually. */
4915 intel_check_cpu_fifo_underruns(dev_priv);
4916 intel_check_pch_fifo_underruns(dev_priv);
4919 /* FIXME move all this to pre_plane_update() with proper state tracking */
4921 intel_pre_disable_primary(struct drm_crtc *crtc)
4923 struct drm_device *dev = crtc->dev;
4924 struct drm_i915_private *dev_priv = to_i915(dev);
4925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4926 int pipe = intel_crtc->pipe;
4929 * Gen2 reports pipe underruns whenever all planes are disabled.
4930 * So diasble underrun reporting before all the planes get disabled.
4931 * FIXME: Need to fix the logic to work when we turn off all planes
4932 * but leave the pipe running.
4934 if (IS_GEN2(dev_priv))
4935 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4938 * FIXME IPS should be fine as long as one plane is
4939 * enabled, but in practice it seems to have problems
4940 * when going from primary only to sprite only and vice
4943 hsw_disable_ips(intel_crtc);
4946 /* FIXME get rid of this and use pre_plane_update */
4948 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4950 struct drm_device *dev = crtc->dev;
4951 struct drm_i915_private *dev_priv = to_i915(dev);
4952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4953 int pipe = intel_crtc->pipe;
4955 intel_pre_disable_primary(crtc);
4958 * Vblank time updates from the shadow to live plane control register
4959 * are blocked if the memory self-refresh mode is active at that
4960 * moment. So to make sure the plane gets truly disabled, disable
4961 * first the self-refresh mode. The self-refresh enable bit in turn
4962 * will be checked/applied by the HW only at the next frame start
4963 * event which is after the vblank start event, so we need to have a
4964 * wait-for-vblank between disabling the plane and the pipe.
4966 if (HAS_GMCH_DISPLAY(dev_priv) &&
4967 intel_set_memory_cxsr(dev_priv, false))
4968 intel_wait_for_vblank(dev_priv, pipe);
4971 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4973 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4974 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4975 struct intel_crtc_state *pipe_config =
4976 to_intel_crtc_state(crtc->base.state);
4977 struct drm_plane *primary = crtc->base.primary;
4978 struct drm_plane_state *old_pri_state =
4979 drm_atomic_get_existing_plane_state(old_state, primary);
4981 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
4983 if (pipe_config->update_wm_post && pipe_config->base.active)
4984 intel_update_watermarks(crtc);
4986 if (old_pri_state) {
4987 struct intel_plane_state *primary_state =
4988 to_intel_plane_state(primary->state);
4989 struct intel_plane_state *old_primary_state =
4990 to_intel_plane_state(old_pri_state);
4992 intel_fbc_post_update(crtc);
4994 if (primary_state->base.visible &&
4995 (needs_modeset(&pipe_config->base) ||
4996 !old_primary_state->base.visible))
4997 intel_post_enable_primary(&crtc->base);
5001 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5002 struct intel_crtc_state *pipe_config)
5004 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5005 struct drm_device *dev = crtc->base.dev;
5006 struct drm_i915_private *dev_priv = to_i915(dev);
5007 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5008 struct drm_plane *primary = crtc->base.primary;
5009 struct drm_plane_state *old_pri_state =
5010 drm_atomic_get_existing_plane_state(old_state, primary);
5011 bool modeset = needs_modeset(&pipe_config->base);
5012 struct intel_atomic_state *old_intel_state =
5013 to_intel_atomic_state(old_state);
5015 if (old_pri_state) {
5016 struct intel_plane_state *primary_state =
5017 to_intel_plane_state(primary->state);
5018 struct intel_plane_state *old_primary_state =
5019 to_intel_plane_state(old_pri_state);
5021 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5023 if (old_primary_state->base.visible &&
5024 (modeset || !primary_state->base.visible))
5025 intel_pre_disable_primary(&crtc->base);
5029 * Vblank time updates from the shadow to live plane control register
5030 * are blocked if the memory self-refresh mode is active at that
5031 * moment. So to make sure the plane gets truly disabled, disable
5032 * first the self-refresh mode. The self-refresh enable bit in turn
5033 * will be checked/applied by the HW only at the next frame start
5034 * event which is after the vblank start event, so we need to have a
5035 * wait-for-vblank between disabling the plane and the pipe.
5037 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5038 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5039 intel_wait_for_vblank(dev_priv, crtc->pipe);
5042 * IVB workaround: must disable low power watermarks for at least
5043 * one frame before enabling scaling. LP watermarks can be re-enabled
5044 * when scaling is disabled.
5046 * WaCxSRDisabledForSpriteScaling:ivb
5048 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5049 intel_wait_for_vblank(dev_priv, crtc->pipe);
5052 * If we're doing a modeset, we're done. No need to do any pre-vblank
5053 * watermark programming here.
5055 if (needs_modeset(&pipe_config->base))
5059 * For platforms that support atomic watermarks, program the
5060 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5061 * will be the intermediate values that are safe for both pre- and
5062 * post- vblank; when vblank happens, the 'active' values will be set
5063 * to the final 'target' values and we'll do this again to get the
5064 * optimal watermarks. For gen9+ platforms, the values we program here
5065 * will be the final target values which will get automatically latched
5066 * at vblank time; no further programming will be necessary.
5068 * If a platform hasn't been transitioned to atomic watermarks yet,
5069 * we'll continue to update watermarks the old way, if flags tell
5072 if (dev_priv->display.initial_watermarks != NULL)
5073 dev_priv->display.initial_watermarks(old_intel_state,
5075 else if (pipe_config->update_wm_pre)
5076 intel_update_watermarks(crtc);
5079 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5081 struct drm_device *dev = crtc->dev;
5082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5083 struct drm_plane *p;
5084 int pipe = intel_crtc->pipe;
5086 intel_crtc_dpms_overlay_disable(intel_crtc);
5088 drm_for_each_plane_mask(p, dev, plane_mask)
5089 to_intel_plane(p)->disable_plane(p, crtc);
5092 * FIXME: Once we grow proper nuclear flip support out of this we need
5093 * to compute the mask of flip planes precisely. For the time being
5094 * consider this a flip to a NULL plane.
5096 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5099 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5100 struct intel_crtc_state *crtc_state,
5101 struct drm_atomic_state *old_state)
5103 struct drm_connector_state *conn_state;
5104 struct drm_connector *conn;
5107 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5108 struct intel_encoder *encoder =
5109 to_intel_encoder(conn_state->best_encoder);
5111 if (conn_state->crtc != crtc)
5114 if (encoder->pre_pll_enable)
5115 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5119 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5120 struct intel_crtc_state *crtc_state,
5121 struct drm_atomic_state *old_state)
5123 struct drm_connector_state *conn_state;
5124 struct drm_connector *conn;
5127 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5128 struct intel_encoder *encoder =
5129 to_intel_encoder(conn_state->best_encoder);
5131 if (conn_state->crtc != crtc)
5134 if (encoder->pre_enable)
5135 encoder->pre_enable(encoder, crtc_state, conn_state);
5139 static void intel_encoders_enable(struct drm_crtc *crtc,
5140 struct intel_crtc_state *crtc_state,
5141 struct drm_atomic_state *old_state)
5143 struct drm_connector_state *conn_state;
5144 struct drm_connector *conn;
5147 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5148 struct intel_encoder *encoder =
5149 to_intel_encoder(conn_state->best_encoder);
5151 if (conn_state->crtc != crtc)
5154 encoder->enable(encoder, crtc_state, conn_state);
5155 intel_opregion_notify_encoder(encoder, true);
5159 static void intel_encoders_disable(struct drm_crtc *crtc,
5160 struct intel_crtc_state *old_crtc_state,
5161 struct drm_atomic_state *old_state)
5163 struct drm_connector_state *old_conn_state;
5164 struct drm_connector *conn;
5167 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5168 struct intel_encoder *encoder =
5169 to_intel_encoder(old_conn_state->best_encoder);
5171 if (old_conn_state->crtc != crtc)
5174 intel_opregion_notify_encoder(encoder, false);
5175 encoder->disable(encoder, old_crtc_state, old_conn_state);
5179 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5180 struct intel_crtc_state *old_crtc_state,
5181 struct drm_atomic_state *old_state)
5183 struct drm_connector_state *old_conn_state;
5184 struct drm_connector *conn;
5187 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5188 struct intel_encoder *encoder =
5189 to_intel_encoder(old_conn_state->best_encoder);
5191 if (old_conn_state->crtc != crtc)
5194 if (encoder->post_disable)
5195 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5199 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5200 struct intel_crtc_state *old_crtc_state,
5201 struct drm_atomic_state *old_state)
5203 struct drm_connector_state *old_conn_state;
5204 struct drm_connector *conn;
5207 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5208 struct intel_encoder *encoder =
5209 to_intel_encoder(old_conn_state->best_encoder);
5211 if (old_conn_state->crtc != crtc)
5214 if (encoder->post_pll_disable)
5215 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5219 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5220 struct drm_atomic_state *old_state)
5222 struct drm_crtc *crtc = pipe_config->base.crtc;
5223 struct drm_device *dev = crtc->dev;
5224 struct drm_i915_private *dev_priv = to_i915(dev);
5225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5226 int pipe = intel_crtc->pipe;
5227 struct intel_atomic_state *old_intel_state =
5228 to_intel_atomic_state(old_state);
5230 if (WARN_ON(intel_crtc->active))
5234 * Sometimes spurious CPU pipe underruns happen during FDI
5235 * training, at least with VGA+HDMI cloning. Suppress them.
5237 * On ILK we get an occasional spurious CPU pipe underruns
5238 * between eDP port A enable and vdd enable. Also PCH port
5239 * enable seems to result in the occasional CPU pipe underrun.
5241 * Spurious PCH underruns also occur during PCH enabling.
5243 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5244 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5245 if (intel_crtc->config->has_pch_encoder)
5246 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5248 if (intel_crtc->config->has_pch_encoder)
5249 intel_prepare_shared_dpll(intel_crtc);
5251 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5252 intel_dp_set_m_n(intel_crtc, M1_N1);
5254 intel_set_pipe_timings(intel_crtc);
5255 intel_set_pipe_src_size(intel_crtc);
5257 if (intel_crtc->config->has_pch_encoder) {
5258 intel_cpu_transcoder_set_m_n(intel_crtc,
5259 &intel_crtc->config->fdi_m_n, NULL);
5262 ironlake_set_pipeconf(crtc);
5264 intel_crtc->active = true;
5266 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5268 if (intel_crtc->config->has_pch_encoder) {
5269 /* Note: FDI PLL enabling _must_ be done before we enable the
5270 * cpu pipes, hence this is separate from all the other fdi/pch
5272 ironlake_fdi_pll_enable(intel_crtc);
5274 assert_fdi_tx_disabled(dev_priv, pipe);
5275 assert_fdi_rx_disabled(dev_priv, pipe);
5278 ironlake_pfit_enable(intel_crtc);
5281 * On ILK+ LUT must be loaded before the pipe is running but with
5284 intel_color_load_luts(&pipe_config->base);
5286 if (dev_priv->display.initial_watermarks != NULL)
5287 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5288 intel_enable_pipe(intel_crtc);
5290 if (intel_crtc->config->has_pch_encoder)
5291 ironlake_pch_enable(pipe_config);
5293 assert_vblank_disabled(crtc);
5294 drm_crtc_vblank_on(crtc);
5296 intel_encoders_enable(crtc, pipe_config, old_state);
5298 if (HAS_PCH_CPT(dev_priv))
5299 cpt_verify_modeset(dev, intel_crtc->pipe);
5301 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5302 if (intel_crtc->config->has_pch_encoder)
5303 intel_wait_for_vblank(dev_priv, pipe);
5304 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5305 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5308 /* IPS only exists on ULT machines and is tied to pipe A. */
5309 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5311 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5314 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5315 struct drm_atomic_state *old_state)
5317 struct drm_crtc *crtc = pipe_config->base.crtc;
5318 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5320 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5321 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5322 struct intel_atomic_state *old_intel_state =
5323 to_intel_atomic_state(old_state);
5325 if (WARN_ON(intel_crtc->active))
5328 if (intel_crtc->config->has_pch_encoder)
5329 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5332 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5334 if (intel_crtc->config->shared_dpll)
5335 intel_enable_shared_dpll(intel_crtc);
5337 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5338 intel_dp_set_m_n(intel_crtc, M1_N1);
5340 if (!transcoder_is_dsi(cpu_transcoder))
5341 intel_set_pipe_timings(intel_crtc);
5343 intel_set_pipe_src_size(intel_crtc);
5345 if (cpu_transcoder != TRANSCODER_EDP &&
5346 !transcoder_is_dsi(cpu_transcoder)) {
5347 I915_WRITE(PIPE_MULT(cpu_transcoder),
5348 intel_crtc->config->pixel_multiplier - 1);
5351 if (intel_crtc->config->has_pch_encoder) {
5352 intel_cpu_transcoder_set_m_n(intel_crtc,
5353 &intel_crtc->config->fdi_m_n, NULL);
5356 if (!transcoder_is_dsi(cpu_transcoder))
5357 haswell_set_pipeconf(crtc);
5359 haswell_set_pipemisc(crtc);
5361 intel_color_set_csc(&pipe_config->base);
5363 intel_crtc->active = true;
5365 if (intel_crtc->config->has_pch_encoder)
5366 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5368 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5370 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5372 if (intel_crtc->config->has_pch_encoder)
5373 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5375 if (!transcoder_is_dsi(cpu_transcoder))
5376 intel_ddi_enable_pipe_clock(pipe_config);
5378 if (INTEL_GEN(dev_priv) >= 9)
5379 skylake_pfit_enable(intel_crtc);
5381 ironlake_pfit_enable(intel_crtc);
5384 * On ILK+ LUT must be loaded before the pipe is running but with
5387 intel_color_load_luts(&pipe_config->base);
5389 intel_ddi_set_pipe_settings(pipe_config);
5390 if (!transcoder_is_dsi(cpu_transcoder))
5391 intel_ddi_enable_transcoder_func(pipe_config);
5393 if (dev_priv->display.initial_watermarks != NULL)
5394 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5396 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5397 if (!transcoder_is_dsi(cpu_transcoder))
5398 intel_enable_pipe(intel_crtc);
5400 if (intel_crtc->config->has_pch_encoder)
5401 lpt_pch_enable(pipe_config);
5403 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5404 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5406 assert_vblank_disabled(crtc);
5407 drm_crtc_vblank_on(crtc);
5409 intel_encoders_enable(crtc, pipe_config, old_state);
5411 if (intel_crtc->config->has_pch_encoder) {
5412 intel_wait_for_vblank(dev_priv, pipe);
5413 intel_wait_for_vblank(dev_priv, pipe);
5414 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5415 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5419 /* If we change the relative order between pipe/planes enabling, we need
5420 * to change the workaround. */
5421 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5422 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5423 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5424 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5428 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5430 struct drm_device *dev = crtc->base.dev;
5431 struct drm_i915_private *dev_priv = to_i915(dev);
5432 int pipe = crtc->pipe;
5434 /* To avoid upsetting the power well on haswell only disable the pfit if
5435 * it's in use. The hw state code will make sure we get this right. */
5436 if (force || crtc->config->pch_pfit.enabled) {
5437 I915_WRITE(PF_CTL(pipe), 0);
5438 I915_WRITE(PF_WIN_POS(pipe), 0);
5439 I915_WRITE(PF_WIN_SZ(pipe), 0);
5443 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5444 struct drm_atomic_state *old_state)
5446 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5447 struct drm_device *dev = crtc->dev;
5448 struct drm_i915_private *dev_priv = to_i915(dev);
5449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5450 int pipe = intel_crtc->pipe;
5453 * Sometimes spurious CPU pipe underruns happen when the
5454 * pipe is already disabled, but FDI RX/TX is still enabled.
5455 * Happens at least with VGA+HDMI cloning. Suppress them.
5457 if (intel_crtc->config->has_pch_encoder) {
5458 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5459 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5462 intel_encoders_disable(crtc, old_crtc_state, old_state);
5464 drm_crtc_vblank_off(crtc);
5465 assert_vblank_disabled(crtc);
5467 intel_disable_pipe(intel_crtc);
5469 ironlake_pfit_disable(intel_crtc, false);
5471 if (intel_crtc->config->has_pch_encoder)
5472 ironlake_fdi_disable(crtc);
5474 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5476 if (intel_crtc->config->has_pch_encoder) {
5477 ironlake_disable_pch_transcoder(dev_priv, pipe);
5479 if (HAS_PCH_CPT(dev_priv)) {
5483 /* disable TRANS_DP_CTL */
5484 reg = TRANS_DP_CTL(pipe);
5485 temp = I915_READ(reg);
5486 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5487 TRANS_DP_PORT_SEL_MASK);
5488 temp |= TRANS_DP_PORT_SEL_NONE;
5489 I915_WRITE(reg, temp);
5491 /* disable DPLL_SEL */
5492 temp = I915_READ(PCH_DPLL_SEL);
5493 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5494 I915_WRITE(PCH_DPLL_SEL, temp);
5497 ironlake_fdi_pll_disable(intel_crtc);
5500 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5501 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5504 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5505 struct drm_atomic_state *old_state)
5507 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5508 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5510 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5512 if (intel_crtc->config->has_pch_encoder)
5513 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5516 intel_encoders_disable(crtc, old_crtc_state, old_state);
5518 drm_crtc_vblank_off(crtc);
5519 assert_vblank_disabled(crtc);
5521 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5522 if (!transcoder_is_dsi(cpu_transcoder))
5523 intel_disable_pipe(intel_crtc);
5525 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5526 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5528 if (!transcoder_is_dsi(cpu_transcoder))
5529 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5531 if (INTEL_GEN(dev_priv) >= 9)
5532 skylake_scaler_disable(intel_crtc);
5534 ironlake_pfit_disable(intel_crtc, false);
5536 if (!transcoder_is_dsi(cpu_transcoder))
5537 intel_ddi_disable_pipe_clock(intel_crtc->config);
5539 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5541 if (old_crtc_state->has_pch_encoder)
5542 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5546 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5548 struct drm_device *dev = crtc->base.dev;
5549 struct drm_i915_private *dev_priv = to_i915(dev);
5550 struct intel_crtc_state *pipe_config = crtc->config;
5552 if (!pipe_config->gmch_pfit.control)
5556 * The panel fitter should only be adjusted whilst the pipe is disabled,
5557 * according to register description and PRM.
5559 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5560 assert_pipe_disabled(dev_priv, crtc->pipe);
5562 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5563 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5565 /* Border color in case we don't scale up to the full screen. Black by
5566 * default, change to something else for debugging. */
5567 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5570 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5574 return POWER_DOMAIN_PORT_DDI_A_LANES;
5576 return POWER_DOMAIN_PORT_DDI_B_LANES;
5578 return POWER_DOMAIN_PORT_DDI_C_LANES;
5580 return POWER_DOMAIN_PORT_DDI_D_LANES;
5582 return POWER_DOMAIN_PORT_DDI_E_LANES;
5585 return POWER_DOMAIN_PORT_OTHER;
5589 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5590 struct intel_crtc_state *crtc_state)
5592 struct drm_device *dev = crtc->dev;
5593 struct drm_i915_private *dev_priv = to_i915(dev);
5594 struct drm_encoder *encoder;
5595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5596 enum pipe pipe = intel_crtc->pipe;
5598 enum transcoder transcoder = crtc_state->cpu_transcoder;
5600 if (!crtc_state->base.active)
5603 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5604 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5605 if (crtc_state->pch_pfit.enabled ||
5606 crtc_state->pch_pfit.force_thru)
5607 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5609 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5610 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5612 mask |= BIT_ULL(intel_encoder->power_domain);
5615 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5616 mask |= BIT(POWER_DOMAIN_AUDIO);
5618 if (crtc_state->shared_dpll)
5619 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5625 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5626 struct intel_crtc_state *crtc_state)
5628 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5630 enum intel_display_power_domain domain;
5631 u64 domains, new_domains, old_domains;
5633 old_domains = intel_crtc->enabled_power_domains;
5634 intel_crtc->enabled_power_domains = new_domains =
5635 get_crtc_power_domains(crtc, crtc_state);
5637 domains = new_domains & ~old_domains;
5639 for_each_power_domain(domain, domains)
5640 intel_display_power_get(dev_priv, domain);
5642 return old_domains & ~new_domains;
5645 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5648 enum intel_display_power_domain domain;
5650 for_each_power_domain(domain, domains)
5651 intel_display_power_put(dev_priv, domain);
5654 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5655 struct drm_atomic_state *old_state)
5657 struct intel_atomic_state *old_intel_state =
5658 to_intel_atomic_state(old_state);
5659 struct drm_crtc *crtc = pipe_config->base.crtc;
5660 struct drm_device *dev = crtc->dev;
5661 struct drm_i915_private *dev_priv = to_i915(dev);
5662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5663 int pipe = intel_crtc->pipe;
5665 if (WARN_ON(intel_crtc->active))
5668 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5669 intel_dp_set_m_n(intel_crtc, M1_N1);
5671 intel_set_pipe_timings(intel_crtc);
5672 intel_set_pipe_src_size(intel_crtc);
5674 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5675 struct drm_i915_private *dev_priv = to_i915(dev);
5677 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5678 I915_WRITE(CHV_CANVAS(pipe), 0);
5681 i9xx_set_pipeconf(intel_crtc);
5683 intel_crtc->active = true;
5685 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5687 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5689 if (IS_CHERRYVIEW(dev_priv)) {
5690 chv_prepare_pll(intel_crtc, intel_crtc->config);
5691 chv_enable_pll(intel_crtc, intel_crtc->config);
5693 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5694 vlv_enable_pll(intel_crtc, intel_crtc->config);
5697 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5699 i9xx_pfit_enable(intel_crtc);
5701 intel_color_load_luts(&pipe_config->base);
5703 dev_priv->display.initial_watermarks(old_intel_state,
5705 intel_enable_pipe(intel_crtc);
5707 assert_vblank_disabled(crtc);
5708 drm_crtc_vblank_on(crtc);
5710 intel_encoders_enable(crtc, pipe_config, old_state);
5713 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5715 struct drm_device *dev = crtc->base.dev;
5716 struct drm_i915_private *dev_priv = to_i915(dev);
5718 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5719 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5722 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5723 struct drm_atomic_state *old_state)
5725 struct drm_crtc *crtc = pipe_config->base.crtc;
5726 struct drm_device *dev = crtc->dev;
5727 struct drm_i915_private *dev_priv = to_i915(dev);
5728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5729 enum pipe pipe = intel_crtc->pipe;
5731 if (WARN_ON(intel_crtc->active))
5734 i9xx_set_pll_dividers(intel_crtc);
5736 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5737 intel_dp_set_m_n(intel_crtc, M1_N1);
5739 intel_set_pipe_timings(intel_crtc);
5740 intel_set_pipe_src_size(intel_crtc);
5742 i9xx_set_pipeconf(intel_crtc);
5744 intel_crtc->active = true;
5746 if (!IS_GEN2(dev_priv))
5747 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5749 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5751 i9xx_enable_pll(intel_crtc);
5753 i9xx_pfit_enable(intel_crtc);
5755 intel_color_load_luts(&pipe_config->base);
5757 intel_update_watermarks(intel_crtc);
5758 intel_enable_pipe(intel_crtc);
5760 assert_vblank_disabled(crtc);
5761 drm_crtc_vblank_on(crtc);
5763 intel_encoders_enable(crtc, pipe_config, old_state);
5766 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5768 struct drm_device *dev = crtc->base.dev;
5769 struct drm_i915_private *dev_priv = to_i915(dev);
5771 if (!crtc->config->gmch_pfit.control)
5774 assert_pipe_disabled(dev_priv, crtc->pipe);
5776 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5777 I915_READ(PFIT_CONTROL));
5778 I915_WRITE(PFIT_CONTROL, 0);
5781 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5782 struct drm_atomic_state *old_state)
5784 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5785 struct drm_device *dev = crtc->dev;
5786 struct drm_i915_private *dev_priv = to_i915(dev);
5787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5788 int pipe = intel_crtc->pipe;
5791 * On gen2 planes are double buffered but the pipe isn't, so we must
5792 * wait for planes to fully turn off before disabling the pipe.
5794 if (IS_GEN2(dev_priv))
5795 intel_wait_for_vblank(dev_priv, pipe);
5797 intel_encoders_disable(crtc, old_crtc_state, old_state);
5799 drm_crtc_vblank_off(crtc);
5800 assert_vblank_disabled(crtc);
5802 intel_disable_pipe(intel_crtc);
5804 i9xx_pfit_disable(intel_crtc);
5806 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5808 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5809 if (IS_CHERRYVIEW(dev_priv))
5810 chv_disable_pll(dev_priv, pipe);
5811 else if (IS_VALLEYVIEW(dev_priv))
5812 vlv_disable_pll(dev_priv, pipe);
5814 i9xx_disable_pll(intel_crtc);
5817 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5819 if (!IS_GEN2(dev_priv))
5820 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5822 if (!dev_priv->display.initial_watermarks)
5823 intel_update_watermarks(intel_crtc);
5826 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
5828 struct intel_encoder *encoder;
5829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5830 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5831 enum intel_display_power_domain domain;
5833 struct drm_atomic_state *state;
5834 struct intel_crtc_state *crtc_state;
5837 if (!intel_crtc->active)
5840 if (crtc->primary->state->visible) {
5841 WARN_ON(intel_crtc->flip_work);
5843 intel_pre_disable_primary_noatomic(crtc);
5845 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5846 crtc->primary->state->visible = false;
5849 state = drm_atomic_state_alloc(crtc->dev);
5851 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5852 crtc->base.id, crtc->name);
5856 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
5858 /* Everything's already locked, -EDEADLK can't happen. */
5859 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5860 ret = drm_atomic_add_affected_connectors(state, crtc);
5862 WARN_ON(IS_ERR(crtc_state) || ret);
5864 dev_priv->display.crtc_disable(crtc_state, state);
5866 drm_atomic_state_put(state);
5868 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5869 crtc->base.id, crtc->name);
5871 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5872 crtc->state->active = false;
5873 intel_crtc->active = false;
5874 crtc->enabled = false;
5875 crtc->state->connector_mask = 0;
5876 crtc->state->encoder_mask = 0;
5878 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5879 encoder->base.crtc = NULL;
5881 intel_fbc_disable(intel_crtc);
5882 intel_update_watermarks(intel_crtc);
5883 intel_disable_shared_dpll(intel_crtc);
5885 domains = intel_crtc->enabled_power_domains;
5886 for_each_power_domain(domain, domains)
5887 intel_display_power_put(dev_priv, domain);
5888 intel_crtc->enabled_power_domains = 0;
5890 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5891 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5895 * turn all crtc's off, but do not adjust state
5896 * This has to be paired with a call to intel_modeset_setup_hw_state.
5898 int intel_display_suspend(struct drm_device *dev)
5900 struct drm_i915_private *dev_priv = to_i915(dev);
5901 struct drm_atomic_state *state;
5904 state = drm_atomic_helper_suspend(dev);
5905 ret = PTR_ERR_OR_ZERO(state);
5907 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5909 dev_priv->modeset_restore_state = state;
5913 void intel_encoder_destroy(struct drm_encoder *encoder)
5915 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5917 drm_encoder_cleanup(encoder);
5918 kfree(intel_encoder);
5921 /* Cross check the actual hw state with our own modeset state tracking (and it's
5922 * internal consistency). */
5923 static void intel_connector_verify_state(struct intel_connector *connector)
5925 struct drm_crtc *crtc = connector->base.state->crtc;
5927 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5928 connector->base.base.id,
5929 connector->base.name);
5931 if (connector->get_hw_state(connector)) {
5932 struct intel_encoder *encoder = connector->encoder;
5933 struct drm_connector_state *conn_state = connector->base.state;
5935 I915_STATE_WARN(!crtc,
5936 "connector enabled without attached crtc\n");
5941 I915_STATE_WARN(!crtc->state->active,
5942 "connector is active, but attached crtc isn't\n");
5944 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5947 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5948 "atomic encoder doesn't match attached encoder\n");
5950 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5951 "attached encoder crtc differs from connector crtc\n");
5953 I915_STATE_WARN(crtc && crtc->state->active,
5954 "attached crtc is active, but connector isn't\n");
5955 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
5956 "best encoder set without crtc!\n");
5960 int intel_connector_init(struct intel_connector *connector)
5962 drm_atomic_helper_connector_reset(&connector->base);
5964 if (!connector->base.state)
5970 struct intel_connector *intel_connector_alloc(void)
5972 struct intel_connector *connector;
5974 connector = kzalloc(sizeof *connector, GFP_KERNEL);
5978 if (intel_connector_init(connector) < 0) {
5986 /* Simple connector->get_hw_state implementation for encoders that support only
5987 * one connector and no cloning and hence the encoder state determines the state
5988 * of the connector. */
5989 bool intel_connector_get_hw_state(struct intel_connector *connector)
5992 struct intel_encoder *encoder = connector->encoder;
5994 return encoder->get_hw_state(encoder, &pipe);
5997 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
5999 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6000 return crtc_state->fdi_lanes;
6005 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6006 struct intel_crtc_state *pipe_config)
6008 struct drm_i915_private *dev_priv = to_i915(dev);
6009 struct drm_atomic_state *state = pipe_config->base.state;
6010 struct intel_crtc *other_crtc;
6011 struct intel_crtc_state *other_crtc_state;
6013 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6014 pipe_name(pipe), pipe_config->fdi_lanes);
6015 if (pipe_config->fdi_lanes > 4) {
6016 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6017 pipe_name(pipe), pipe_config->fdi_lanes);
6021 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6022 if (pipe_config->fdi_lanes > 2) {
6023 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6024 pipe_config->fdi_lanes);
6031 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6034 /* Ivybridge 3 pipe is really complicated */
6039 if (pipe_config->fdi_lanes <= 2)
6042 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6044 intel_atomic_get_crtc_state(state, other_crtc);
6045 if (IS_ERR(other_crtc_state))
6046 return PTR_ERR(other_crtc_state);
6048 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6049 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6050 pipe_name(pipe), pipe_config->fdi_lanes);
6055 if (pipe_config->fdi_lanes > 2) {
6056 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6057 pipe_name(pipe), pipe_config->fdi_lanes);
6061 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6063 intel_atomic_get_crtc_state(state, other_crtc);
6064 if (IS_ERR(other_crtc_state))
6065 return PTR_ERR(other_crtc_state);
6067 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6068 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6078 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6079 struct intel_crtc_state *pipe_config)
6081 struct drm_device *dev = intel_crtc->base.dev;
6082 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6083 int lane, link_bw, fdi_dotclock, ret;
6084 bool needs_recompute = false;
6087 /* FDI is a binary signal running at ~2.7GHz, encoding
6088 * each output octet as 10 bits. The actual frequency
6089 * is stored as a divider into a 100MHz clock, and the
6090 * mode pixel clock is stored in units of 1KHz.
6091 * Hence the bw of each lane in terms of the mode signal
6094 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6096 fdi_dotclock = adjusted_mode->crtc_clock;
6098 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6099 pipe_config->pipe_bpp);
6101 pipe_config->fdi_lanes = lane;
6103 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6104 link_bw, &pipe_config->fdi_m_n);
6106 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6107 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6108 pipe_config->pipe_bpp -= 2*3;
6109 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6110 pipe_config->pipe_bpp);
6111 needs_recompute = true;
6112 pipe_config->bw_constrained = true;
6117 if (needs_recompute)
6123 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6124 struct intel_crtc_state *pipe_config)
6126 if (pipe_config->pipe_bpp > 24)
6129 /* HSW can handle pixel rate up to cdclk? */
6130 if (IS_HASWELL(dev_priv))
6134 * We compare against max which means we must take
6135 * the increased cdclk requirement into account when
6136 * calculating the new cdclk.
6138 * Should measure whether using a lower cdclk w/o IPS
6140 return pipe_config->pixel_rate <=
6141 dev_priv->max_cdclk_freq * 95 / 100;
6144 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6145 struct intel_crtc_state *pipe_config)
6147 struct drm_device *dev = crtc->base.dev;
6148 struct drm_i915_private *dev_priv = to_i915(dev);
6150 pipe_config->ips_enabled = i915.enable_ips &&
6151 hsw_crtc_supports_ips(crtc) &&
6152 pipe_config_supports_ips(dev_priv, pipe_config);
6155 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6157 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6159 /* GDG double wide on either pipe, otherwise pipe A only */
6160 return INTEL_INFO(dev_priv)->gen < 4 &&
6161 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6164 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6166 uint32_t pixel_rate;
6168 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6171 * We only use IF-ID interlacing. If we ever use
6172 * PF-ID we'll need to adjust the pixel_rate here.
6175 if (pipe_config->pch_pfit.enabled) {
6176 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6177 uint32_t pfit_size = pipe_config->pch_pfit.size;
6179 pipe_w = pipe_config->pipe_src_w;
6180 pipe_h = pipe_config->pipe_src_h;
6182 pfit_w = (pfit_size >> 16) & 0xFFFF;
6183 pfit_h = pfit_size & 0xFFFF;
6184 if (pipe_w < pfit_w)
6186 if (pipe_h < pfit_h)
6189 if (WARN_ON(!pfit_w || !pfit_h))
6192 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6199 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6201 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6203 if (HAS_GMCH_DISPLAY(dev_priv))
6204 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6205 crtc_state->pixel_rate =
6206 crtc_state->base.adjusted_mode.crtc_clock;
6208 crtc_state->pixel_rate =
6209 ilk_pipe_pixel_rate(crtc_state);
6212 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6213 struct intel_crtc_state *pipe_config)
6215 struct drm_device *dev = crtc->base.dev;
6216 struct drm_i915_private *dev_priv = to_i915(dev);
6217 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6218 int clock_limit = dev_priv->max_dotclk_freq;
6220 if (INTEL_GEN(dev_priv) < 4) {
6221 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6224 * Enable double wide mode when the dot clock
6225 * is > 90% of the (display) core speed.
6227 if (intel_crtc_supports_double_wide(crtc) &&
6228 adjusted_mode->crtc_clock > clock_limit) {
6229 clock_limit = dev_priv->max_dotclk_freq;
6230 pipe_config->double_wide = true;
6234 if (adjusted_mode->crtc_clock > clock_limit) {
6235 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6236 adjusted_mode->crtc_clock, clock_limit,
6237 yesno(pipe_config->double_wide));
6242 * Pipe horizontal size must be even in:
6244 * - LVDS dual channel mode
6245 * - Double wide pipe
6247 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6248 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6249 pipe_config->pipe_src_w &= ~1;
6251 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6252 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6254 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6255 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6258 intel_crtc_compute_pixel_rate(pipe_config);
6260 if (HAS_IPS(dev_priv))
6261 hsw_compute_ips_config(crtc, pipe_config);
6263 if (pipe_config->has_pch_encoder)
6264 return ironlake_fdi_compute_config(crtc, pipe_config);
6270 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6272 while (*num > DATA_LINK_M_N_MASK ||
6273 *den > DATA_LINK_M_N_MASK) {
6279 static void compute_m_n(unsigned int m, unsigned int n,
6280 uint32_t *ret_m, uint32_t *ret_n)
6283 * Reduce M/N as much as possible without loss in precision. Several DP
6284 * dongles in particular seem to be fussy about too large *link* M/N
6285 * values. The passed in values are more likely to have the least
6286 * significant bits zero than M after rounding below, so do this first.
6288 while ((m & 1) == 0 && (n & 1) == 0) {
6293 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6294 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6295 intel_reduce_m_n_ratio(ret_m, ret_n);
6299 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6300 int pixel_clock, int link_clock,
6301 struct intel_link_m_n *m_n)
6305 compute_m_n(bits_per_pixel * pixel_clock,
6306 link_clock * nlanes * 8,
6307 &m_n->gmch_m, &m_n->gmch_n);
6309 compute_m_n(pixel_clock, link_clock,
6310 &m_n->link_m, &m_n->link_n);
6313 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6315 if (i915.panel_use_ssc >= 0)
6316 return i915.panel_use_ssc != 0;
6317 return dev_priv->vbt.lvds_use_ssc
6318 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6321 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6323 return (1 << dpll->n) << 16 | dpll->m2;
6326 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6328 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6331 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6332 struct intel_crtc_state *crtc_state,
6333 struct dpll *reduced_clock)
6335 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6338 if (IS_PINEVIEW(dev_priv)) {
6339 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6341 fp2 = pnv_dpll_compute_fp(reduced_clock);
6343 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6345 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6348 crtc_state->dpll_hw_state.fp0 = fp;
6350 crtc->lowfreq_avail = false;
6351 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6353 crtc_state->dpll_hw_state.fp1 = fp2;
6354 crtc->lowfreq_avail = true;
6356 crtc_state->dpll_hw_state.fp1 = fp;
6360 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6366 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6367 * and set it to a reasonable value instead.
6369 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6370 reg_val &= 0xffffff00;
6371 reg_val |= 0x00000030;
6372 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6374 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6375 reg_val &= 0x8cffffff;
6376 reg_val = 0x8c000000;
6377 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6379 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6380 reg_val &= 0xffffff00;
6381 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6383 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6384 reg_val &= 0x00ffffff;
6385 reg_val |= 0xb0000000;
6386 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6389 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6390 struct intel_link_m_n *m_n)
6392 struct drm_device *dev = crtc->base.dev;
6393 struct drm_i915_private *dev_priv = to_i915(dev);
6394 int pipe = crtc->pipe;
6396 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6397 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6398 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6399 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6402 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6403 struct intel_link_m_n *m_n,
6404 struct intel_link_m_n *m2_n2)
6406 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6407 int pipe = crtc->pipe;
6408 enum transcoder transcoder = crtc->config->cpu_transcoder;
6410 if (INTEL_GEN(dev_priv) >= 5) {
6411 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6412 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6413 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6414 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6415 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6416 * for gen < 8) and if DRRS is supported (to make sure the
6417 * registers are not unnecessarily accessed).
6419 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6420 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6421 I915_WRITE(PIPE_DATA_M2(transcoder),
6422 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6423 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6424 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6425 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6428 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6429 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6430 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6431 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6435 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6437 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6440 dp_m_n = &crtc->config->dp_m_n;
6441 dp_m2_n2 = &crtc->config->dp_m2_n2;
6442 } else if (m_n == M2_N2) {
6445 * M2_N2 registers are not supported. Hence m2_n2 divider value
6446 * needs to be programmed into M1_N1.
6448 dp_m_n = &crtc->config->dp_m2_n2;
6450 DRM_ERROR("Unsupported divider value\n");
6454 if (crtc->config->has_pch_encoder)
6455 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6457 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6460 static void vlv_compute_dpll(struct intel_crtc *crtc,
6461 struct intel_crtc_state *pipe_config)
6463 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6464 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6465 if (crtc->pipe != PIPE_A)
6466 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6468 /* DPLL not used with DSI, but still need the rest set up */
6469 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6470 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6471 DPLL_EXT_BUFFER_ENABLE_VLV;
6473 pipe_config->dpll_hw_state.dpll_md =
6474 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6477 static void chv_compute_dpll(struct intel_crtc *crtc,
6478 struct intel_crtc_state *pipe_config)
6480 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6481 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6482 if (crtc->pipe != PIPE_A)
6483 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6485 /* DPLL not used with DSI, but still need the rest set up */
6486 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6487 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6489 pipe_config->dpll_hw_state.dpll_md =
6490 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6493 static void vlv_prepare_pll(struct intel_crtc *crtc,
6494 const struct intel_crtc_state *pipe_config)
6496 struct drm_device *dev = crtc->base.dev;
6497 struct drm_i915_private *dev_priv = to_i915(dev);
6498 enum pipe pipe = crtc->pipe;
6500 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6501 u32 coreclk, reg_val;
6504 I915_WRITE(DPLL(pipe),
6505 pipe_config->dpll_hw_state.dpll &
6506 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6508 /* No need to actually set up the DPLL with DSI */
6509 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6512 mutex_lock(&dev_priv->sb_lock);
6514 bestn = pipe_config->dpll.n;
6515 bestm1 = pipe_config->dpll.m1;
6516 bestm2 = pipe_config->dpll.m2;
6517 bestp1 = pipe_config->dpll.p1;
6518 bestp2 = pipe_config->dpll.p2;
6520 /* See eDP HDMI DPIO driver vbios notes doc */
6522 /* PLL B needs special handling */
6524 vlv_pllb_recal_opamp(dev_priv, pipe);
6526 /* Set up Tx target for periodic Rcomp update */
6527 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6529 /* Disable target IRef on PLL */
6530 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6531 reg_val &= 0x00ffffff;
6532 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6534 /* Disable fast lock */
6535 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6537 /* Set idtafcrecal before PLL is enabled */
6538 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6539 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6540 mdiv |= ((bestn << DPIO_N_SHIFT));
6541 mdiv |= (1 << DPIO_K_SHIFT);
6544 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6545 * but we don't support that).
6546 * Note: don't use the DAC post divider as it seems unstable.
6548 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6549 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6551 mdiv |= DPIO_ENABLE_CALIBRATION;
6552 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6554 /* Set HBR and RBR LPF coefficients */
6555 if (pipe_config->port_clock == 162000 ||
6556 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6557 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6558 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6561 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6564 if (intel_crtc_has_dp_encoder(pipe_config)) {
6565 /* Use SSC source */
6567 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6570 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6572 } else { /* HDMI or VGA */
6573 /* Use bend source */
6575 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6578 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6582 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6583 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6584 if (intel_crtc_has_dp_encoder(crtc->config))
6585 coreclk |= 0x01000000;
6586 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6588 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6589 mutex_unlock(&dev_priv->sb_lock);
6592 static void chv_prepare_pll(struct intel_crtc *crtc,
6593 const struct intel_crtc_state *pipe_config)
6595 struct drm_device *dev = crtc->base.dev;
6596 struct drm_i915_private *dev_priv = to_i915(dev);
6597 enum pipe pipe = crtc->pipe;
6598 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6599 u32 loopfilter, tribuf_calcntr;
6600 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6604 /* Enable Refclk and SSC */
6605 I915_WRITE(DPLL(pipe),
6606 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6608 /* No need to actually set up the DPLL with DSI */
6609 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6612 bestn = pipe_config->dpll.n;
6613 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6614 bestm1 = pipe_config->dpll.m1;
6615 bestm2 = pipe_config->dpll.m2 >> 22;
6616 bestp1 = pipe_config->dpll.p1;
6617 bestp2 = pipe_config->dpll.p2;
6618 vco = pipe_config->dpll.vco;
6622 mutex_lock(&dev_priv->sb_lock);
6624 /* p1 and p2 divider */
6625 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6626 5 << DPIO_CHV_S1_DIV_SHIFT |
6627 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6628 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6629 1 << DPIO_CHV_K_DIV_SHIFT);
6631 /* Feedback post-divider - m2 */
6632 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6634 /* Feedback refclk divider - n and m1 */
6635 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6636 DPIO_CHV_M1_DIV_BY_2 |
6637 1 << DPIO_CHV_N_DIV_SHIFT);
6639 /* M2 fraction division */
6640 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6642 /* M2 fraction division enable */
6643 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6644 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6645 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6647 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6648 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6650 /* Program digital lock detect threshold */
6651 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6652 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6653 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6654 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6656 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6657 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6660 if (vco == 5400000) {
6661 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6662 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6663 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6664 tribuf_calcntr = 0x9;
6665 } else if (vco <= 6200000) {
6666 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6667 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6668 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6669 tribuf_calcntr = 0x9;
6670 } else if (vco <= 6480000) {
6671 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6672 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6673 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6674 tribuf_calcntr = 0x8;
6676 /* Not supported. Apply the same limits as in the max case */
6677 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6678 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6679 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6682 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6684 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6685 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6686 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6687 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6690 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6691 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6694 mutex_unlock(&dev_priv->sb_lock);
6698 * vlv_force_pll_on - forcibly enable just the PLL
6699 * @dev_priv: i915 private structure
6700 * @pipe: pipe PLL to enable
6701 * @dpll: PLL configuration
6703 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6704 * in cases where we need the PLL enabled even when @pipe is not going to
6707 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6708 const struct dpll *dpll)
6710 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6711 struct intel_crtc_state *pipe_config;
6713 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6717 pipe_config->base.crtc = &crtc->base;
6718 pipe_config->pixel_multiplier = 1;
6719 pipe_config->dpll = *dpll;
6721 if (IS_CHERRYVIEW(dev_priv)) {
6722 chv_compute_dpll(crtc, pipe_config);
6723 chv_prepare_pll(crtc, pipe_config);
6724 chv_enable_pll(crtc, pipe_config);
6726 vlv_compute_dpll(crtc, pipe_config);
6727 vlv_prepare_pll(crtc, pipe_config);
6728 vlv_enable_pll(crtc, pipe_config);
6737 * vlv_force_pll_off - forcibly disable just the PLL
6738 * @dev_priv: i915 private structure
6739 * @pipe: pipe PLL to disable
6741 * Disable the PLL for @pipe. To be used in cases where we need
6742 * the PLL enabled even when @pipe is not going to be enabled.
6744 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6746 if (IS_CHERRYVIEW(dev_priv))
6747 chv_disable_pll(dev_priv, pipe);
6749 vlv_disable_pll(dev_priv, pipe);
6752 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6753 struct intel_crtc_state *crtc_state,
6754 struct dpll *reduced_clock)
6756 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6758 struct dpll *clock = &crtc_state->dpll;
6760 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6762 dpll = DPLL_VGA_MODE_DIS;
6764 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6765 dpll |= DPLLB_MODE_LVDS;
6767 dpll |= DPLLB_MODE_DAC_SERIAL;
6769 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6770 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6771 dpll |= (crtc_state->pixel_multiplier - 1)
6772 << SDVO_MULTIPLIER_SHIFT_HIRES;
6775 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6776 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6777 dpll |= DPLL_SDVO_HIGH_SPEED;
6779 if (intel_crtc_has_dp_encoder(crtc_state))
6780 dpll |= DPLL_SDVO_HIGH_SPEED;
6782 /* compute bitmask from p1 value */
6783 if (IS_PINEVIEW(dev_priv))
6784 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6786 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6787 if (IS_G4X(dev_priv) && reduced_clock)
6788 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6790 switch (clock->p2) {
6792 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6795 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6798 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6801 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6804 if (INTEL_GEN(dev_priv) >= 4)
6805 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6807 if (crtc_state->sdvo_tv_clock)
6808 dpll |= PLL_REF_INPUT_TVCLKINBC;
6809 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6810 intel_panel_use_ssc(dev_priv))
6811 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6813 dpll |= PLL_REF_INPUT_DREFCLK;
6815 dpll |= DPLL_VCO_ENABLE;
6816 crtc_state->dpll_hw_state.dpll = dpll;
6818 if (INTEL_GEN(dev_priv) >= 4) {
6819 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6820 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6821 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6825 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6826 struct intel_crtc_state *crtc_state,
6827 struct dpll *reduced_clock)
6829 struct drm_device *dev = crtc->base.dev;
6830 struct drm_i915_private *dev_priv = to_i915(dev);
6832 struct dpll *clock = &crtc_state->dpll;
6834 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6836 dpll = DPLL_VGA_MODE_DIS;
6838 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6839 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6842 dpll |= PLL_P1_DIVIDE_BY_TWO;
6844 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6846 dpll |= PLL_P2_DIVIDE_BY_4;
6849 if (!IS_I830(dev_priv) &&
6850 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6851 dpll |= DPLL_DVO_2X_MODE;
6853 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6854 intel_panel_use_ssc(dev_priv))
6855 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6857 dpll |= PLL_REF_INPUT_DREFCLK;
6859 dpll |= DPLL_VCO_ENABLE;
6860 crtc_state->dpll_hw_state.dpll = dpll;
6863 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6865 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6866 enum pipe pipe = intel_crtc->pipe;
6867 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6868 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6869 uint32_t crtc_vtotal, crtc_vblank_end;
6872 /* We need to be careful not to changed the adjusted mode, for otherwise
6873 * the hw state checker will get angry at the mismatch. */
6874 crtc_vtotal = adjusted_mode->crtc_vtotal;
6875 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6877 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6878 /* the chip adds 2 halflines automatically */
6880 crtc_vblank_end -= 1;
6882 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6883 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6885 vsyncshift = adjusted_mode->crtc_hsync_start -
6886 adjusted_mode->crtc_htotal / 2;
6888 vsyncshift += adjusted_mode->crtc_htotal;
6891 if (INTEL_GEN(dev_priv) > 3)
6892 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6894 I915_WRITE(HTOTAL(cpu_transcoder),
6895 (adjusted_mode->crtc_hdisplay - 1) |
6896 ((adjusted_mode->crtc_htotal - 1) << 16));
6897 I915_WRITE(HBLANK(cpu_transcoder),
6898 (adjusted_mode->crtc_hblank_start - 1) |
6899 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6900 I915_WRITE(HSYNC(cpu_transcoder),
6901 (adjusted_mode->crtc_hsync_start - 1) |
6902 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6904 I915_WRITE(VTOTAL(cpu_transcoder),
6905 (adjusted_mode->crtc_vdisplay - 1) |
6906 ((crtc_vtotal - 1) << 16));
6907 I915_WRITE(VBLANK(cpu_transcoder),
6908 (adjusted_mode->crtc_vblank_start - 1) |
6909 ((crtc_vblank_end - 1) << 16));
6910 I915_WRITE(VSYNC(cpu_transcoder),
6911 (adjusted_mode->crtc_vsync_start - 1) |
6912 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6914 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6915 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6916 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6918 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6919 (pipe == PIPE_B || pipe == PIPE_C))
6920 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6924 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6926 struct drm_device *dev = intel_crtc->base.dev;
6927 struct drm_i915_private *dev_priv = to_i915(dev);
6928 enum pipe pipe = intel_crtc->pipe;
6930 /* pipesrc controls the size that is scaled from, which should
6931 * always be the user's requested size.
6933 I915_WRITE(PIPESRC(pipe),
6934 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6935 (intel_crtc->config->pipe_src_h - 1));
6938 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6939 struct intel_crtc_state *pipe_config)
6941 struct drm_device *dev = crtc->base.dev;
6942 struct drm_i915_private *dev_priv = to_i915(dev);
6943 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6946 tmp = I915_READ(HTOTAL(cpu_transcoder));
6947 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6948 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6949 tmp = I915_READ(HBLANK(cpu_transcoder));
6950 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6951 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6952 tmp = I915_READ(HSYNC(cpu_transcoder));
6953 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6954 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6956 tmp = I915_READ(VTOTAL(cpu_transcoder));
6957 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6958 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6959 tmp = I915_READ(VBLANK(cpu_transcoder));
6960 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6961 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6962 tmp = I915_READ(VSYNC(cpu_transcoder));
6963 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6964 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6966 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6967 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6968 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6969 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6973 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
6974 struct intel_crtc_state *pipe_config)
6976 struct drm_device *dev = crtc->base.dev;
6977 struct drm_i915_private *dev_priv = to_i915(dev);
6980 tmp = I915_READ(PIPESRC(crtc->pipe));
6981 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6982 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6984 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6985 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6988 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6989 struct intel_crtc_state *pipe_config)
6991 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6992 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6993 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6994 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6996 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6997 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6998 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6999 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7001 mode->flags = pipe_config->base.adjusted_mode.flags;
7002 mode->type = DRM_MODE_TYPE_DRIVER;
7004 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7006 mode->hsync = drm_mode_hsync(mode);
7007 mode->vrefresh = drm_mode_vrefresh(mode);
7008 drm_mode_set_name(mode);
7011 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7013 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7018 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7019 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7020 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7022 if (intel_crtc->config->double_wide)
7023 pipeconf |= PIPECONF_DOUBLE_WIDE;
7025 /* only g4x and later have fancy bpc/dither controls */
7026 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7027 IS_CHERRYVIEW(dev_priv)) {
7028 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7029 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7030 pipeconf |= PIPECONF_DITHER_EN |
7031 PIPECONF_DITHER_TYPE_SP;
7033 switch (intel_crtc->config->pipe_bpp) {
7035 pipeconf |= PIPECONF_6BPC;
7038 pipeconf |= PIPECONF_8BPC;
7041 pipeconf |= PIPECONF_10BPC;
7044 /* Case prevented by intel_choose_pipe_bpp_dither. */
7049 if (HAS_PIPE_CXSR(dev_priv)) {
7050 if (intel_crtc->lowfreq_avail) {
7051 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7052 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7054 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7058 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7059 if (INTEL_GEN(dev_priv) < 4 ||
7060 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7061 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7063 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7065 pipeconf |= PIPECONF_PROGRESSIVE;
7067 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7068 intel_crtc->config->limited_color_range)
7069 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7071 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7072 POSTING_READ(PIPECONF(intel_crtc->pipe));
7075 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7076 struct intel_crtc_state *crtc_state)
7078 struct drm_device *dev = crtc->base.dev;
7079 struct drm_i915_private *dev_priv = to_i915(dev);
7080 const struct intel_limit *limit;
7083 memset(&crtc_state->dpll_hw_state, 0,
7084 sizeof(crtc_state->dpll_hw_state));
7086 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7087 if (intel_panel_use_ssc(dev_priv)) {
7088 refclk = dev_priv->vbt.lvds_ssc_freq;
7089 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7092 limit = &intel_limits_i8xx_lvds;
7093 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7094 limit = &intel_limits_i8xx_dvo;
7096 limit = &intel_limits_i8xx_dac;
7099 if (!crtc_state->clock_set &&
7100 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7101 refclk, NULL, &crtc_state->dpll)) {
7102 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7106 i8xx_compute_dpll(crtc, crtc_state, NULL);
7111 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7112 struct intel_crtc_state *crtc_state)
7114 struct drm_device *dev = crtc->base.dev;
7115 struct drm_i915_private *dev_priv = to_i915(dev);
7116 const struct intel_limit *limit;
7119 memset(&crtc_state->dpll_hw_state, 0,
7120 sizeof(crtc_state->dpll_hw_state));
7122 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7123 if (intel_panel_use_ssc(dev_priv)) {
7124 refclk = dev_priv->vbt.lvds_ssc_freq;
7125 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7128 if (intel_is_dual_link_lvds(dev))
7129 limit = &intel_limits_g4x_dual_channel_lvds;
7131 limit = &intel_limits_g4x_single_channel_lvds;
7132 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7133 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7134 limit = &intel_limits_g4x_hdmi;
7135 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7136 limit = &intel_limits_g4x_sdvo;
7138 /* The option is for other outputs */
7139 limit = &intel_limits_i9xx_sdvo;
7142 if (!crtc_state->clock_set &&
7143 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7144 refclk, NULL, &crtc_state->dpll)) {
7145 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7149 i9xx_compute_dpll(crtc, crtc_state, NULL);
7154 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7155 struct intel_crtc_state *crtc_state)
7157 struct drm_device *dev = crtc->base.dev;
7158 struct drm_i915_private *dev_priv = to_i915(dev);
7159 const struct intel_limit *limit;
7162 memset(&crtc_state->dpll_hw_state, 0,
7163 sizeof(crtc_state->dpll_hw_state));
7165 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7166 if (intel_panel_use_ssc(dev_priv)) {
7167 refclk = dev_priv->vbt.lvds_ssc_freq;
7168 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7171 limit = &intel_limits_pineview_lvds;
7173 limit = &intel_limits_pineview_sdvo;
7176 if (!crtc_state->clock_set &&
7177 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7178 refclk, NULL, &crtc_state->dpll)) {
7179 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7183 i9xx_compute_dpll(crtc, crtc_state, NULL);
7188 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7189 struct intel_crtc_state *crtc_state)
7191 struct drm_device *dev = crtc->base.dev;
7192 struct drm_i915_private *dev_priv = to_i915(dev);
7193 const struct intel_limit *limit;
7196 memset(&crtc_state->dpll_hw_state, 0,
7197 sizeof(crtc_state->dpll_hw_state));
7199 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7200 if (intel_panel_use_ssc(dev_priv)) {
7201 refclk = dev_priv->vbt.lvds_ssc_freq;
7202 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7205 limit = &intel_limits_i9xx_lvds;
7207 limit = &intel_limits_i9xx_sdvo;
7210 if (!crtc_state->clock_set &&
7211 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7212 refclk, NULL, &crtc_state->dpll)) {
7213 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7217 i9xx_compute_dpll(crtc, crtc_state, NULL);
7222 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7223 struct intel_crtc_state *crtc_state)
7225 int refclk = 100000;
7226 const struct intel_limit *limit = &intel_limits_chv;
7228 memset(&crtc_state->dpll_hw_state, 0,
7229 sizeof(crtc_state->dpll_hw_state));
7231 if (!crtc_state->clock_set &&
7232 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7233 refclk, NULL, &crtc_state->dpll)) {
7234 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7238 chv_compute_dpll(crtc, crtc_state);
7243 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7244 struct intel_crtc_state *crtc_state)
7246 int refclk = 100000;
7247 const struct intel_limit *limit = &intel_limits_vlv;
7249 memset(&crtc_state->dpll_hw_state, 0,
7250 sizeof(crtc_state->dpll_hw_state));
7252 if (!crtc_state->clock_set &&
7253 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7254 refclk, NULL, &crtc_state->dpll)) {
7255 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7259 vlv_compute_dpll(crtc, crtc_state);
7264 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7265 struct intel_crtc_state *pipe_config)
7267 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7270 if (INTEL_GEN(dev_priv) <= 3 &&
7271 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7274 tmp = I915_READ(PFIT_CONTROL);
7275 if (!(tmp & PFIT_ENABLE))
7278 /* Check whether the pfit is attached to our pipe. */
7279 if (INTEL_GEN(dev_priv) < 4) {
7280 if (crtc->pipe != PIPE_B)
7283 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7287 pipe_config->gmch_pfit.control = tmp;
7288 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7291 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7292 struct intel_crtc_state *pipe_config)
7294 struct drm_device *dev = crtc->base.dev;
7295 struct drm_i915_private *dev_priv = to_i915(dev);
7296 int pipe = pipe_config->cpu_transcoder;
7299 int refclk = 100000;
7301 /* In case of DSI, DPLL will not be used */
7302 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7305 mutex_lock(&dev_priv->sb_lock);
7306 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7307 mutex_unlock(&dev_priv->sb_lock);
7309 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7310 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7311 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7312 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7313 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7315 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7319 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7320 struct intel_initial_plane_config *plane_config)
7322 struct drm_device *dev = crtc->base.dev;
7323 struct drm_i915_private *dev_priv = to_i915(dev);
7324 u32 val, base, offset;
7325 int pipe = crtc->pipe, plane = crtc->plane;
7326 int fourcc, pixel_format;
7327 unsigned int aligned_height;
7328 struct drm_framebuffer *fb;
7329 struct intel_framebuffer *intel_fb;
7331 val = I915_READ(DSPCNTR(plane));
7332 if (!(val & DISPLAY_PLANE_ENABLE))
7335 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7337 DRM_DEBUG_KMS("failed to alloc fb\n");
7341 fb = &intel_fb->base;
7345 if (INTEL_GEN(dev_priv) >= 4) {
7346 if (val & DISPPLANE_TILED) {
7347 plane_config->tiling = I915_TILING_X;
7348 fb->modifier = I915_FORMAT_MOD_X_TILED;
7352 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7353 fourcc = i9xx_format_to_fourcc(pixel_format);
7354 fb->format = drm_format_info(fourcc);
7356 if (INTEL_GEN(dev_priv) >= 4) {
7357 if (plane_config->tiling)
7358 offset = I915_READ(DSPTILEOFF(plane));
7360 offset = I915_READ(DSPLINOFF(plane));
7361 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7363 base = I915_READ(DSPADDR(plane));
7365 plane_config->base = base;
7367 val = I915_READ(PIPESRC(pipe));
7368 fb->width = ((val >> 16) & 0xfff) + 1;
7369 fb->height = ((val >> 0) & 0xfff) + 1;
7371 val = I915_READ(DSPSTRIDE(pipe));
7372 fb->pitches[0] = val & 0xffffffc0;
7374 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7376 plane_config->size = fb->pitches[0] * aligned_height;
7378 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7379 pipe_name(pipe), plane, fb->width, fb->height,
7380 fb->format->cpp[0] * 8, base, fb->pitches[0],
7381 plane_config->size);
7383 plane_config->fb = intel_fb;
7386 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7387 struct intel_crtc_state *pipe_config)
7389 struct drm_device *dev = crtc->base.dev;
7390 struct drm_i915_private *dev_priv = to_i915(dev);
7391 int pipe = pipe_config->cpu_transcoder;
7392 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7394 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7395 int refclk = 100000;
7397 /* In case of DSI, DPLL will not be used */
7398 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7401 mutex_lock(&dev_priv->sb_lock);
7402 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7403 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7404 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7405 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7406 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7407 mutex_unlock(&dev_priv->sb_lock);
7409 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7410 clock.m2 = (pll_dw0 & 0xff) << 22;
7411 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7412 clock.m2 |= pll_dw2 & 0x3fffff;
7413 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7414 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7415 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7417 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7420 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7421 struct intel_crtc_state *pipe_config)
7423 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7424 enum intel_display_power_domain power_domain;
7428 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7429 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7432 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7433 pipe_config->shared_dpll = NULL;
7437 tmp = I915_READ(PIPECONF(crtc->pipe));
7438 if (!(tmp & PIPECONF_ENABLE))
7441 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7442 IS_CHERRYVIEW(dev_priv)) {
7443 switch (tmp & PIPECONF_BPC_MASK) {
7445 pipe_config->pipe_bpp = 18;
7448 pipe_config->pipe_bpp = 24;
7450 case PIPECONF_10BPC:
7451 pipe_config->pipe_bpp = 30;
7458 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7459 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7460 pipe_config->limited_color_range = true;
7462 if (INTEL_GEN(dev_priv) < 4)
7463 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7465 intel_get_pipe_timings(crtc, pipe_config);
7466 intel_get_pipe_src_size(crtc, pipe_config);
7468 i9xx_get_pfit_config(crtc, pipe_config);
7470 if (INTEL_GEN(dev_priv) >= 4) {
7471 /* No way to read it out on pipes B and C */
7472 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7473 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7475 tmp = I915_READ(DPLL_MD(crtc->pipe));
7476 pipe_config->pixel_multiplier =
7477 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7478 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7479 pipe_config->dpll_hw_state.dpll_md = tmp;
7480 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7481 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7482 tmp = I915_READ(DPLL(crtc->pipe));
7483 pipe_config->pixel_multiplier =
7484 ((tmp & SDVO_MULTIPLIER_MASK)
7485 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7487 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7488 * port and will be fixed up in the encoder->get_config
7490 pipe_config->pixel_multiplier = 1;
7492 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7493 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7495 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7496 * on 830. Filter it out here so that we don't
7497 * report errors due to that.
7499 if (IS_I830(dev_priv))
7500 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7502 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7503 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7505 /* Mask out read-only status bits. */
7506 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7507 DPLL_PORTC_READY_MASK |
7508 DPLL_PORTB_READY_MASK);
7511 if (IS_CHERRYVIEW(dev_priv))
7512 chv_crtc_clock_get(crtc, pipe_config);
7513 else if (IS_VALLEYVIEW(dev_priv))
7514 vlv_crtc_clock_get(crtc, pipe_config);
7516 i9xx_crtc_clock_get(crtc, pipe_config);
7519 * Normally the dotclock is filled in by the encoder .get_config()
7520 * but in case the pipe is enabled w/o any ports we need a sane
7523 pipe_config->base.adjusted_mode.crtc_clock =
7524 pipe_config->port_clock / pipe_config->pixel_multiplier;
7529 intel_display_power_put(dev_priv, power_domain);
7534 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7536 struct intel_encoder *encoder;
7539 bool has_lvds = false;
7540 bool has_cpu_edp = false;
7541 bool has_panel = false;
7542 bool has_ck505 = false;
7543 bool can_ssc = false;
7544 bool using_ssc_source = false;
7546 /* We need to take the global config into account */
7547 for_each_intel_encoder(&dev_priv->drm, encoder) {
7548 switch (encoder->type) {
7549 case INTEL_OUTPUT_LVDS:
7553 case INTEL_OUTPUT_EDP:
7555 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7563 if (HAS_PCH_IBX(dev_priv)) {
7564 has_ck505 = dev_priv->vbt.display_clock_mode;
7565 can_ssc = has_ck505;
7571 /* Check if any DPLLs are using the SSC source */
7572 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7573 u32 temp = I915_READ(PCH_DPLL(i));
7575 if (!(temp & DPLL_VCO_ENABLE))
7578 if ((temp & PLL_REF_INPUT_MASK) ==
7579 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7580 using_ssc_source = true;
7585 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7586 has_panel, has_lvds, has_ck505, using_ssc_source);
7588 /* Ironlake: try to setup display ref clock before DPLL
7589 * enabling. This is only under driver's control after
7590 * PCH B stepping, previous chipset stepping should be
7591 * ignoring this setting.
7593 val = I915_READ(PCH_DREF_CONTROL);
7595 /* As we must carefully and slowly disable/enable each source in turn,
7596 * compute the final state we want first and check if we need to
7597 * make any changes at all.
7600 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7602 final |= DREF_NONSPREAD_CK505_ENABLE;
7604 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7606 final &= ~DREF_SSC_SOURCE_MASK;
7607 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7608 final &= ~DREF_SSC1_ENABLE;
7611 final |= DREF_SSC_SOURCE_ENABLE;
7613 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7614 final |= DREF_SSC1_ENABLE;
7617 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7618 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7620 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7622 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7623 } else if (using_ssc_source) {
7624 final |= DREF_SSC_SOURCE_ENABLE;
7625 final |= DREF_SSC1_ENABLE;
7631 /* Always enable nonspread source */
7632 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7635 val |= DREF_NONSPREAD_CK505_ENABLE;
7637 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7640 val &= ~DREF_SSC_SOURCE_MASK;
7641 val |= DREF_SSC_SOURCE_ENABLE;
7643 /* SSC must be turned on before enabling the CPU output */
7644 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7645 DRM_DEBUG_KMS("Using SSC on panel\n");
7646 val |= DREF_SSC1_ENABLE;
7648 val &= ~DREF_SSC1_ENABLE;
7650 /* Get SSC going before enabling the outputs */
7651 I915_WRITE(PCH_DREF_CONTROL, val);
7652 POSTING_READ(PCH_DREF_CONTROL);
7655 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7657 /* Enable CPU source on CPU attached eDP */
7659 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7660 DRM_DEBUG_KMS("Using SSC on eDP\n");
7661 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7663 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7665 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7667 I915_WRITE(PCH_DREF_CONTROL, val);
7668 POSTING_READ(PCH_DREF_CONTROL);
7671 DRM_DEBUG_KMS("Disabling CPU source output\n");
7673 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7675 /* Turn off CPU output */
7676 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7678 I915_WRITE(PCH_DREF_CONTROL, val);
7679 POSTING_READ(PCH_DREF_CONTROL);
7682 if (!using_ssc_source) {
7683 DRM_DEBUG_KMS("Disabling SSC source\n");
7685 /* Turn off the SSC source */
7686 val &= ~DREF_SSC_SOURCE_MASK;
7687 val |= DREF_SSC_SOURCE_DISABLE;
7690 val &= ~DREF_SSC1_ENABLE;
7692 I915_WRITE(PCH_DREF_CONTROL, val);
7693 POSTING_READ(PCH_DREF_CONTROL);
7698 BUG_ON(val != final);
7701 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7705 tmp = I915_READ(SOUTH_CHICKEN2);
7706 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7707 I915_WRITE(SOUTH_CHICKEN2, tmp);
7709 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7710 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7711 DRM_ERROR("FDI mPHY reset assert timeout\n");
7713 tmp = I915_READ(SOUTH_CHICKEN2);
7714 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7715 I915_WRITE(SOUTH_CHICKEN2, tmp);
7717 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7718 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7719 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7722 /* WaMPhyProgramming:hsw */
7723 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7727 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7728 tmp &= ~(0xFF << 24);
7729 tmp |= (0x12 << 24);
7730 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7732 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7734 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7736 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7738 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7740 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7741 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7742 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7744 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7745 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7746 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7748 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7751 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7753 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7756 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7758 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7761 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7763 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7766 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7768 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7769 tmp &= ~(0xFF << 16);
7770 tmp |= (0x1C << 16);
7771 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7773 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7774 tmp &= ~(0xFF << 16);
7775 tmp |= (0x1C << 16);
7776 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7778 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7780 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7782 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7784 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7786 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7787 tmp &= ~(0xF << 28);
7789 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7791 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7792 tmp &= ~(0xF << 28);
7794 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7797 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7798 * Programming" based on the parameters passed:
7799 * - Sequence to enable CLKOUT_DP
7800 * - Sequence to enable CLKOUT_DP without spread
7801 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7803 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7804 bool with_spread, bool with_fdi)
7808 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7810 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7811 with_fdi, "LP PCH doesn't have FDI\n"))
7814 mutex_lock(&dev_priv->sb_lock);
7816 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7817 tmp &= ~SBI_SSCCTL_DISABLE;
7818 tmp |= SBI_SSCCTL_PATHALT;
7819 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7824 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7825 tmp &= ~SBI_SSCCTL_PATHALT;
7826 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7829 lpt_reset_fdi_mphy(dev_priv);
7830 lpt_program_fdi_mphy(dev_priv);
7834 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7835 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7836 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7837 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7839 mutex_unlock(&dev_priv->sb_lock);
7842 /* Sequence to disable CLKOUT_DP */
7843 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7847 mutex_lock(&dev_priv->sb_lock);
7849 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7850 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7851 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7852 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7854 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7855 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7856 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7857 tmp |= SBI_SSCCTL_PATHALT;
7858 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7861 tmp |= SBI_SSCCTL_DISABLE;
7862 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7865 mutex_unlock(&dev_priv->sb_lock);
7868 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7870 static const uint16_t sscdivintphase[] = {
7871 [BEND_IDX( 50)] = 0x3B23,
7872 [BEND_IDX( 45)] = 0x3B23,
7873 [BEND_IDX( 40)] = 0x3C23,
7874 [BEND_IDX( 35)] = 0x3C23,
7875 [BEND_IDX( 30)] = 0x3D23,
7876 [BEND_IDX( 25)] = 0x3D23,
7877 [BEND_IDX( 20)] = 0x3E23,
7878 [BEND_IDX( 15)] = 0x3E23,
7879 [BEND_IDX( 10)] = 0x3F23,
7880 [BEND_IDX( 5)] = 0x3F23,
7881 [BEND_IDX( 0)] = 0x0025,
7882 [BEND_IDX( -5)] = 0x0025,
7883 [BEND_IDX(-10)] = 0x0125,
7884 [BEND_IDX(-15)] = 0x0125,
7885 [BEND_IDX(-20)] = 0x0225,
7886 [BEND_IDX(-25)] = 0x0225,
7887 [BEND_IDX(-30)] = 0x0325,
7888 [BEND_IDX(-35)] = 0x0325,
7889 [BEND_IDX(-40)] = 0x0425,
7890 [BEND_IDX(-45)] = 0x0425,
7891 [BEND_IDX(-50)] = 0x0525,
7896 * steps -50 to 50 inclusive, in steps of 5
7897 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7898 * change in clock period = -(steps / 10) * 5.787 ps
7900 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7903 int idx = BEND_IDX(steps);
7905 if (WARN_ON(steps % 5 != 0))
7908 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7911 mutex_lock(&dev_priv->sb_lock);
7913 if (steps % 10 != 0)
7917 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7919 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7921 tmp |= sscdivintphase[idx];
7922 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7924 mutex_unlock(&dev_priv->sb_lock);
7929 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7931 struct intel_encoder *encoder;
7932 bool has_vga = false;
7934 for_each_intel_encoder(&dev_priv->drm, encoder) {
7935 switch (encoder->type) {
7936 case INTEL_OUTPUT_ANALOG:
7945 lpt_bend_clkout_dp(dev_priv, 0);
7946 lpt_enable_clkout_dp(dev_priv, true, true);
7948 lpt_disable_clkout_dp(dev_priv);
7953 * Initialize reference clocks when the driver loads
7955 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7957 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7958 ironlake_init_pch_refclk(dev_priv);
7959 else if (HAS_PCH_LPT(dev_priv))
7960 lpt_init_pch_refclk(dev_priv);
7963 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7965 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7967 int pipe = intel_crtc->pipe;
7972 switch (intel_crtc->config->pipe_bpp) {
7974 val |= PIPECONF_6BPC;
7977 val |= PIPECONF_8BPC;
7980 val |= PIPECONF_10BPC;
7983 val |= PIPECONF_12BPC;
7986 /* Case prevented by intel_choose_pipe_bpp_dither. */
7990 if (intel_crtc->config->dither)
7991 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7993 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7994 val |= PIPECONF_INTERLACED_ILK;
7996 val |= PIPECONF_PROGRESSIVE;
7998 if (intel_crtc->config->limited_color_range)
7999 val |= PIPECONF_COLOR_RANGE_SELECT;
8001 I915_WRITE(PIPECONF(pipe), val);
8002 POSTING_READ(PIPECONF(pipe));
8005 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8007 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8009 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8012 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8013 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8015 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8016 val |= PIPECONF_INTERLACED_ILK;
8018 val |= PIPECONF_PROGRESSIVE;
8020 I915_WRITE(PIPECONF(cpu_transcoder), val);
8021 POSTING_READ(PIPECONF(cpu_transcoder));
8024 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8026 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8029 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8032 switch (intel_crtc->config->pipe_bpp) {
8034 val |= PIPEMISC_DITHER_6_BPC;
8037 val |= PIPEMISC_DITHER_8_BPC;
8040 val |= PIPEMISC_DITHER_10_BPC;
8043 val |= PIPEMISC_DITHER_12_BPC;
8046 /* Case prevented by pipe_config_set_bpp. */
8050 if (intel_crtc->config->dither)
8051 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8053 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8057 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8060 * Account for spread spectrum to avoid
8061 * oversubscribing the link. Max center spread
8062 * is 2.5%; use 5% for safety's sake.
8064 u32 bps = target_clock * bpp * 21 / 20;
8065 return DIV_ROUND_UP(bps, link_bw * 8);
8068 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8070 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8073 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8074 struct intel_crtc_state *crtc_state,
8075 struct dpll *reduced_clock)
8077 struct drm_crtc *crtc = &intel_crtc->base;
8078 struct drm_device *dev = crtc->dev;
8079 struct drm_i915_private *dev_priv = to_i915(dev);
8083 /* Enable autotuning of the PLL clock (if permissible) */
8085 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8086 if ((intel_panel_use_ssc(dev_priv) &&
8087 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8088 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8090 } else if (crtc_state->sdvo_tv_clock)
8093 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8095 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8098 if (reduced_clock) {
8099 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8101 if (reduced_clock->m < factor * reduced_clock->n)
8109 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8110 dpll |= DPLLB_MODE_LVDS;
8112 dpll |= DPLLB_MODE_DAC_SERIAL;
8114 dpll |= (crtc_state->pixel_multiplier - 1)
8115 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8117 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8118 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8119 dpll |= DPLL_SDVO_HIGH_SPEED;
8121 if (intel_crtc_has_dp_encoder(crtc_state))
8122 dpll |= DPLL_SDVO_HIGH_SPEED;
8125 * The high speed IO clock is only really required for
8126 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8127 * possible to share the DPLL between CRT and HDMI. Enabling
8128 * the clock needlessly does no real harm, except use up a
8129 * bit of power potentially.
8131 * We'll limit this to IVB with 3 pipes, since it has only two
8132 * DPLLs and so DPLL sharing is the only way to get three pipes
8133 * driving PCH ports at the same time. On SNB we could do this,
8134 * and potentially avoid enabling the second DPLL, but it's not
8135 * clear if it''s a win or loss power wise. No point in doing
8136 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8138 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8139 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8140 dpll |= DPLL_SDVO_HIGH_SPEED;
8142 /* compute bitmask from p1 value */
8143 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8145 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8147 switch (crtc_state->dpll.p2) {
8149 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8152 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8155 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8158 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8162 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8163 intel_panel_use_ssc(dev_priv))
8164 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8166 dpll |= PLL_REF_INPUT_DREFCLK;
8168 dpll |= DPLL_VCO_ENABLE;
8170 crtc_state->dpll_hw_state.dpll = dpll;
8171 crtc_state->dpll_hw_state.fp0 = fp;
8172 crtc_state->dpll_hw_state.fp1 = fp2;
8175 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8176 struct intel_crtc_state *crtc_state)
8178 struct drm_device *dev = crtc->base.dev;
8179 struct drm_i915_private *dev_priv = to_i915(dev);
8180 struct dpll reduced_clock;
8181 bool has_reduced_clock = false;
8182 struct intel_shared_dpll *pll;
8183 const struct intel_limit *limit;
8184 int refclk = 120000;
8186 memset(&crtc_state->dpll_hw_state, 0,
8187 sizeof(crtc_state->dpll_hw_state));
8189 crtc->lowfreq_avail = false;
8191 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8192 if (!crtc_state->has_pch_encoder)
8195 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8196 if (intel_panel_use_ssc(dev_priv)) {
8197 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8198 dev_priv->vbt.lvds_ssc_freq);
8199 refclk = dev_priv->vbt.lvds_ssc_freq;
8202 if (intel_is_dual_link_lvds(dev)) {
8203 if (refclk == 100000)
8204 limit = &intel_limits_ironlake_dual_lvds_100m;
8206 limit = &intel_limits_ironlake_dual_lvds;
8208 if (refclk == 100000)
8209 limit = &intel_limits_ironlake_single_lvds_100m;
8211 limit = &intel_limits_ironlake_single_lvds;
8214 limit = &intel_limits_ironlake_dac;
8217 if (!crtc_state->clock_set &&
8218 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8219 refclk, NULL, &crtc_state->dpll)) {
8220 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8224 ironlake_compute_dpll(crtc, crtc_state,
8225 has_reduced_clock ? &reduced_clock : NULL);
8227 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8229 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8230 pipe_name(crtc->pipe));
8234 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8236 crtc->lowfreq_avail = true;
8241 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8242 struct intel_link_m_n *m_n)
8244 struct drm_device *dev = crtc->base.dev;
8245 struct drm_i915_private *dev_priv = to_i915(dev);
8246 enum pipe pipe = crtc->pipe;
8248 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8249 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8250 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8252 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8253 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8254 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8257 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8258 enum transcoder transcoder,
8259 struct intel_link_m_n *m_n,
8260 struct intel_link_m_n *m2_n2)
8262 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8263 enum pipe pipe = crtc->pipe;
8265 if (INTEL_GEN(dev_priv) >= 5) {
8266 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8267 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8268 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8270 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8271 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8272 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8273 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8274 * gen < 8) and if DRRS is supported (to make sure the
8275 * registers are not unnecessarily read).
8277 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8278 crtc->config->has_drrs) {
8279 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8280 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8281 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8283 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8284 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8285 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8288 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8289 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8290 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8292 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8293 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8294 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8298 void intel_dp_get_m_n(struct intel_crtc *crtc,
8299 struct intel_crtc_state *pipe_config)
8301 if (pipe_config->has_pch_encoder)
8302 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8304 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8305 &pipe_config->dp_m_n,
8306 &pipe_config->dp_m2_n2);
8309 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8310 struct intel_crtc_state *pipe_config)
8312 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8313 &pipe_config->fdi_m_n, NULL);
8316 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8317 struct intel_crtc_state *pipe_config)
8319 struct drm_device *dev = crtc->base.dev;
8320 struct drm_i915_private *dev_priv = to_i915(dev);
8321 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8322 uint32_t ps_ctrl = 0;
8326 /* find scaler attached to this pipe */
8327 for (i = 0; i < crtc->num_scalers; i++) {
8328 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8329 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8331 pipe_config->pch_pfit.enabled = true;
8332 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8333 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8338 scaler_state->scaler_id = id;
8340 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8342 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8347 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8348 struct intel_initial_plane_config *plane_config)
8350 struct drm_device *dev = crtc->base.dev;
8351 struct drm_i915_private *dev_priv = to_i915(dev);
8352 u32 val, base, offset, stride_mult, tiling;
8353 int pipe = crtc->pipe;
8354 int fourcc, pixel_format;
8355 unsigned int aligned_height;
8356 struct drm_framebuffer *fb;
8357 struct intel_framebuffer *intel_fb;
8359 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8361 DRM_DEBUG_KMS("failed to alloc fb\n");
8365 fb = &intel_fb->base;
8369 val = I915_READ(PLANE_CTL(pipe, 0));
8370 if (!(val & PLANE_CTL_ENABLE))
8373 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8374 fourcc = skl_format_to_fourcc(pixel_format,
8375 val & PLANE_CTL_ORDER_RGBX,
8376 val & PLANE_CTL_ALPHA_MASK);
8377 fb->format = drm_format_info(fourcc);
8379 tiling = val & PLANE_CTL_TILED_MASK;
8381 case PLANE_CTL_TILED_LINEAR:
8382 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8384 case PLANE_CTL_TILED_X:
8385 plane_config->tiling = I915_TILING_X;
8386 fb->modifier = I915_FORMAT_MOD_X_TILED;
8388 case PLANE_CTL_TILED_Y:
8389 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8391 case PLANE_CTL_TILED_YF:
8392 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8395 MISSING_CASE(tiling);
8399 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8400 plane_config->base = base;
8402 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8404 val = I915_READ(PLANE_SIZE(pipe, 0));
8405 fb->height = ((val >> 16) & 0xfff) + 1;
8406 fb->width = ((val >> 0) & 0x1fff) + 1;
8408 val = I915_READ(PLANE_STRIDE(pipe, 0));
8409 stride_mult = intel_fb_stride_alignment(fb, 0);
8410 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8412 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8414 plane_config->size = fb->pitches[0] * aligned_height;
8416 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8417 pipe_name(pipe), fb->width, fb->height,
8418 fb->format->cpp[0] * 8, base, fb->pitches[0],
8419 plane_config->size);
8421 plane_config->fb = intel_fb;
8428 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8429 struct intel_crtc_state *pipe_config)
8431 struct drm_device *dev = crtc->base.dev;
8432 struct drm_i915_private *dev_priv = to_i915(dev);
8435 tmp = I915_READ(PF_CTL(crtc->pipe));
8437 if (tmp & PF_ENABLE) {
8438 pipe_config->pch_pfit.enabled = true;
8439 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8440 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8442 /* We currently do not free assignements of panel fitters on
8443 * ivb/hsw (since we don't use the higher upscaling modes which
8444 * differentiates them) so just WARN about this case for now. */
8445 if (IS_GEN7(dev_priv)) {
8446 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8447 PF_PIPE_SEL_IVB(crtc->pipe));
8453 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8454 struct intel_initial_plane_config *plane_config)
8456 struct drm_device *dev = crtc->base.dev;
8457 struct drm_i915_private *dev_priv = to_i915(dev);
8458 u32 val, base, offset;
8459 int pipe = crtc->pipe;
8460 int fourcc, pixel_format;
8461 unsigned int aligned_height;
8462 struct drm_framebuffer *fb;
8463 struct intel_framebuffer *intel_fb;
8465 val = I915_READ(DSPCNTR(pipe));
8466 if (!(val & DISPLAY_PLANE_ENABLE))
8469 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8471 DRM_DEBUG_KMS("failed to alloc fb\n");
8475 fb = &intel_fb->base;
8479 if (INTEL_GEN(dev_priv) >= 4) {
8480 if (val & DISPPLANE_TILED) {
8481 plane_config->tiling = I915_TILING_X;
8482 fb->modifier = I915_FORMAT_MOD_X_TILED;
8486 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8487 fourcc = i9xx_format_to_fourcc(pixel_format);
8488 fb->format = drm_format_info(fourcc);
8490 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8491 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8492 offset = I915_READ(DSPOFFSET(pipe));
8494 if (plane_config->tiling)
8495 offset = I915_READ(DSPTILEOFF(pipe));
8497 offset = I915_READ(DSPLINOFF(pipe));
8499 plane_config->base = base;
8501 val = I915_READ(PIPESRC(pipe));
8502 fb->width = ((val >> 16) & 0xfff) + 1;
8503 fb->height = ((val >> 0) & 0xfff) + 1;
8505 val = I915_READ(DSPSTRIDE(pipe));
8506 fb->pitches[0] = val & 0xffffffc0;
8508 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8510 plane_config->size = fb->pitches[0] * aligned_height;
8512 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8513 pipe_name(pipe), fb->width, fb->height,
8514 fb->format->cpp[0] * 8, base, fb->pitches[0],
8515 plane_config->size);
8517 plane_config->fb = intel_fb;
8520 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8521 struct intel_crtc_state *pipe_config)
8523 struct drm_device *dev = crtc->base.dev;
8524 struct drm_i915_private *dev_priv = to_i915(dev);
8525 enum intel_display_power_domain power_domain;
8529 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8530 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8533 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8534 pipe_config->shared_dpll = NULL;
8537 tmp = I915_READ(PIPECONF(crtc->pipe));
8538 if (!(tmp & PIPECONF_ENABLE))
8541 switch (tmp & PIPECONF_BPC_MASK) {
8543 pipe_config->pipe_bpp = 18;
8546 pipe_config->pipe_bpp = 24;
8548 case PIPECONF_10BPC:
8549 pipe_config->pipe_bpp = 30;
8551 case PIPECONF_12BPC:
8552 pipe_config->pipe_bpp = 36;
8558 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8559 pipe_config->limited_color_range = true;
8561 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8562 struct intel_shared_dpll *pll;
8563 enum intel_dpll_id pll_id;
8565 pipe_config->has_pch_encoder = true;
8567 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8568 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8569 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8571 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8573 if (HAS_PCH_IBX(dev_priv)) {
8575 * The pipe->pch transcoder and pch transcoder->pll
8578 pll_id = (enum intel_dpll_id) crtc->pipe;
8580 tmp = I915_READ(PCH_DPLL_SEL);
8581 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8582 pll_id = DPLL_ID_PCH_PLL_B;
8584 pll_id= DPLL_ID_PCH_PLL_A;
8587 pipe_config->shared_dpll =
8588 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8589 pll = pipe_config->shared_dpll;
8591 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8592 &pipe_config->dpll_hw_state));
8594 tmp = pipe_config->dpll_hw_state.dpll;
8595 pipe_config->pixel_multiplier =
8596 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8597 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8599 ironlake_pch_clock_get(crtc, pipe_config);
8601 pipe_config->pixel_multiplier = 1;
8604 intel_get_pipe_timings(crtc, pipe_config);
8605 intel_get_pipe_src_size(crtc, pipe_config);
8607 ironlake_get_pfit_config(crtc, pipe_config);
8612 intel_display_power_put(dev_priv, power_domain);
8617 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8619 struct drm_device *dev = &dev_priv->drm;
8620 struct intel_crtc *crtc;
8622 for_each_intel_crtc(dev, crtc)
8623 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8624 pipe_name(crtc->pipe));
8626 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8627 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8628 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8629 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8630 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8631 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8632 "CPU PWM1 enabled\n");
8633 if (IS_HASWELL(dev_priv))
8634 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8635 "CPU PWM2 enabled\n");
8636 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8637 "PCH PWM1 enabled\n");
8638 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8639 "Utility pin enabled\n");
8640 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8643 * In theory we can still leave IRQs enabled, as long as only the HPD
8644 * interrupts remain enabled. We used to check for that, but since it's
8645 * gen-specific and since we only disable LCPLL after we fully disable
8646 * the interrupts, the check below should be enough.
8648 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8651 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8653 if (IS_HASWELL(dev_priv))
8654 return I915_READ(D_COMP_HSW);
8656 return I915_READ(D_COMP_BDW);
8659 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8661 if (IS_HASWELL(dev_priv)) {
8662 mutex_lock(&dev_priv->rps.hw_lock);
8663 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8665 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8666 mutex_unlock(&dev_priv->rps.hw_lock);
8668 I915_WRITE(D_COMP_BDW, val);
8669 POSTING_READ(D_COMP_BDW);
8674 * This function implements pieces of two sequences from BSpec:
8675 * - Sequence for display software to disable LCPLL
8676 * - Sequence for display software to allow package C8+
8677 * The steps implemented here are just the steps that actually touch the LCPLL
8678 * register. Callers should take care of disabling all the display engine
8679 * functions, doing the mode unset, fixing interrupts, etc.
8681 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8682 bool switch_to_fclk, bool allow_power_down)
8686 assert_can_disable_lcpll(dev_priv);
8688 val = I915_READ(LCPLL_CTL);
8690 if (switch_to_fclk) {
8691 val |= LCPLL_CD_SOURCE_FCLK;
8692 I915_WRITE(LCPLL_CTL, val);
8694 if (wait_for_us(I915_READ(LCPLL_CTL) &
8695 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8696 DRM_ERROR("Switching to FCLK failed\n");
8698 val = I915_READ(LCPLL_CTL);
8701 val |= LCPLL_PLL_DISABLE;
8702 I915_WRITE(LCPLL_CTL, val);
8703 POSTING_READ(LCPLL_CTL);
8705 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8706 DRM_ERROR("LCPLL still locked\n");
8708 val = hsw_read_dcomp(dev_priv);
8709 val |= D_COMP_COMP_DISABLE;
8710 hsw_write_dcomp(dev_priv, val);
8713 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8715 DRM_ERROR("D_COMP RCOMP still in progress\n");
8717 if (allow_power_down) {
8718 val = I915_READ(LCPLL_CTL);
8719 val |= LCPLL_POWER_DOWN_ALLOW;
8720 I915_WRITE(LCPLL_CTL, val);
8721 POSTING_READ(LCPLL_CTL);
8726 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8729 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8733 val = I915_READ(LCPLL_CTL);
8735 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8736 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8740 * Make sure we're not on PC8 state before disabling PC8, otherwise
8741 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8743 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8745 if (val & LCPLL_POWER_DOWN_ALLOW) {
8746 val &= ~LCPLL_POWER_DOWN_ALLOW;
8747 I915_WRITE(LCPLL_CTL, val);
8748 POSTING_READ(LCPLL_CTL);
8751 val = hsw_read_dcomp(dev_priv);
8752 val |= D_COMP_COMP_FORCE;
8753 val &= ~D_COMP_COMP_DISABLE;
8754 hsw_write_dcomp(dev_priv, val);
8756 val = I915_READ(LCPLL_CTL);
8757 val &= ~LCPLL_PLL_DISABLE;
8758 I915_WRITE(LCPLL_CTL, val);
8760 if (intel_wait_for_register(dev_priv,
8761 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8763 DRM_ERROR("LCPLL not locked yet\n");
8765 if (val & LCPLL_CD_SOURCE_FCLK) {
8766 val = I915_READ(LCPLL_CTL);
8767 val &= ~LCPLL_CD_SOURCE_FCLK;
8768 I915_WRITE(LCPLL_CTL, val);
8770 if (wait_for_us((I915_READ(LCPLL_CTL) &
8771 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8772 DRM_ERROR("Switching back to LCPLL failed\n");
8775 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8776 intel_update_cdclk(dev_priv);
8780 * Package states C8 and deeper are really deep PC states that can only be
8781 * reached when all the devices on the system allow it, so even if the graphics
8782 * device allows PC8+, it doesn't mean the system will actually get to these
8783 * states. Our driver only allows PC8+ when going into runtime PM.
8785 * The requirements for PC8+ are that all the outputs are disabled, the power
8786 * well is disabled and most interrupts are disabled, and these are also
8787 * requirements for runtime PM. When these conditions are met, we manually do
8788 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8789 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8792 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8793 * the state of some registers, so when we come back from PC8+ we need to
8794 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8795 * need to take care of the registers kept by RC6. Notice that this happens even
8796 * if we don't put the device in PCI D3 state (which is what currently happens
8797 * because of the runtime PM support).
8799 * For more, read "Display Sequences for Package C8" on the hardware
8802 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8806 DRM_DEBUG_KMS("Enabling package C8+\n");
8808 if (HAS_PCH_LPT_LP(dev_priv)) {
8809 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8810 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8811 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8814 lpt_disable_clkout_dp(dev_priv);
8815 hsw_disable_lcpll(dev_priv, true, true);
8818 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8822 DRM_DEBUG_KMS("Disabling package C8+\n");
8824 hsw_restore_lcpll(dev_priv);
8825 lpt_init_pch_refclk(dev_priv);
8827 if (HAS_PCH_LPT_LP(dev_priv)) {
8828 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8829 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8830 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8834 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8835 struct intel_crtc_state *crtc_state)
8837 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8838 struct intel_encoder *encoder =
8839 intel_ddi_get_crtc_new_encoder(crtc_state);
8841 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8842 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8843 pipe_name(crtc->pipe));
8848 crtc->lowfreq_avail = false;
8853 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8855 struct intel_crtc_state *pipe_config)
8857 enum intel_dpll_id id;
8861 id = DPLL_ID_SKL_DPLL0;
8864 id = DPLL_ID_SKL_DPLL1;
8867 id = DPLL_ID_SKL_DPLL2;
8870 DRM_ERROR("Incorrect port type\n");
8874 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8877 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8879 struct intel_crtc_state *pipe_config)
8881 enum intel_dpll_id id;
8884 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8885 id = temp >> (port * 3 + 1);
8887 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8890 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8893 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8895 struct intel_crtc_state *pipe_config)
8897 enum intel_dpll_id id;
8898 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8900 switch (ddi_pll_sel) {
8901 case PORT_CLK_SEL_WRPLL1:
8902 id = DPLL_ID_WRPLL1;
8904 case PORT_CLK_SEL_WRPLL2:
8905 id = DPLL_ID_WRPLL2;
8907 case PORT_CLK_SEL_SPLL:
8910 case PORT_CLK_SEL_LCPLL_810:
8911 id = DPLL_ID_LCPLL_810;
8913 case PORT_CLK_SEL_LCPLL_1350:
8914 id = DPLL_ID_LCPLL_1350;
8916 case PORT_CLK_SEL_LCPLL_2700:
8917 id = DPLL_ID_LCPLL_2700;
8920 MISSING_CASE(ddi_pll_sel);
8922 case PORT_CLK_SEL_NONE:
8926 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8929 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8930 struct intel_crtc_state *pipe_config,
8931 u64 *power_domain_mask)
8933 struct drm_device *dev = crtc->base.dev;
8934 struct drm_i915_private *dev_priv = to_i915(dev);
8935 enum intel_display_power_domain power_domain;
8939 * The pipe->transcoder mapping is fixed with the exception of the eDP
8940 * transcoder handled below.
8942 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8945 * XXX: Do intel_display_power_get_if_enabled before reading this (for
8946 * consistency and less surprising code; it's in always on power).
8948 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8949 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8950 enum pipe trans_edp_pipe;
8951 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8953 WARN(1, "unknown pipe linked to edp transcoder\n");
8954 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8955 case TRANS_DDI_EDP_INPUT_A_ON:
8956 trans_edp_pipe = PIPE_A;
8958 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8959 trans_edp_pipe = PIPE_B;
8961 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8962 trans_edp_pipe = PIPE_C;
8966 if (trans_edp_pipe == crtc->pipe)
8967 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8970 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
8971 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8973 *power_domain_mask |= BIT_ULL(power_domain);
8975 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8977 return tmp & PIPECONF_ENABLE;
8980 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
8981 struct intel_crtc_state *pipe_config,
8982 u64 *power_domain_mask)
8984 struct drm_device *dev = crtc->base.dev;
8985 struct drm_i915_private *dev_priv = to_i915(dev);
8986 enum intel_display_power_domain power_domain;
8988 enum transcoder cpu_transcoder;
8991 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
8993 cpu_transcoder = TRANSCODER_DSI_A;
8995 cpu_transcoder = TRANSCODER_DSI_C;
8997 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
8998 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9000 *power_domain_mask |= BIT_ULL(power_domain);
9003 * The PLL needs to be enabled with a valid divider
9004 * configuration, otherwise accessing DSI registers will hang
9005 * the machine. See BSpec North Display Engine
9006 * registers/MIPI[BXT]. We can break out here early, since we
9007 * need the same DSI PLL to be enabled for both DSI ports.
9009 if (!intel_dsi_pll_is_enabled(dev_priv))
9012 /* XXX: this works for video mode only */
9013 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9014 if (!(tmp & DPI_ENABLE))
9017 tmp = I915_READ(MIPI_CTRL(port));
9018 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9021 pipe_config->cpu_transcoder = cpu_transcoder;
9025 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9028 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9029 struct intel_crtc_state *pipe_config)
9031 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9032 struct intel_shared_dpll *pll;
9036 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9038 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9040 if (IS_GEN9_BC(dev_priv))
9041 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9042 else if (IS_GEN9_LP(dev_priv))
9043 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9045 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9047 pll = pipe_config->shared_dpll;
9049 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9050 &pipe_config->dpll_hw_state));
9054 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9055 * DDI E. So just check whether this pipe is wired to DDI E and whether
9056 * the PCH transcoder is on.
9058 if (INTEL_GEN(dev_priv) < 9 &&
9059 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9060 pipe_config->has_pch_encoder = true;
9062 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9063 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9064 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9066 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9070 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9071 struct intel_crtc_state *pipe_config)
9073 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9074 enum intel_display_power_domain power_domain;
9075 u64 power_domain_mask;
9078 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9079 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9081 power_domain_mask = BIT_ULL(power_domain);
9083 pipe_config->shared_dpll = NULL;
9085 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9087 if (IS_GEN9_LP(dev_priv) &&
9088 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9096 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9097 haswell_get_ddi_port_state(crtc, pipe_config);
9098 intel_get_pipe_timings(crtc, pipe_config);
9101 intel_get_pipe_src_size(crtc, pipe_config);
9103 pipe_config->gamma_mode =
9104 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9106 if (INTEL_GEN(dev_priv) >= 9) {
9107 intel_crtc_init_scalers(crtc, pipe_config);
9109 pipe_config->scaler_state.scaler_id = -1;
9110 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9113 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9114 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9115 power_domain_mask |= BIT_ULL(power_domain);
9116 if (INTEL_GEN(dev_priv) >= 9)
9117 skylake_get_pfit_config(crtc, pipe_config);
9119 ironlake_get_pfit_config(crtc, pipe_config);
9122 if (IS_HASWELL(dev_priv))
9123 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9124 (I915_READ(IPS_CTL) & IPS_ENABLE);
9126 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9127 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9128 pipe_config->pixel_multiplier =
9129 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9131 pipe_config->pixel_multiplier = 1;
9135 for_each_power_domain(power_domain, power_domain_mask)
9136 intel_display_power_put(dev_priv, power_domain);
9141 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9142 const struct intel_plane_state *plane_state)
9144 unsigned int width = plane_state->base.crtc_w;
9145 unsigned int stride = roundup_pow_of_two(width) * 4;
9149 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9160 return CURSOR_ENABLE |
9161 CURSOR_GAMMA_ENABLE |
9162 CURSOR_FORMAT_ARGB |
9163 CURSOR_STRIDE(stride);
9166 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
9167 const struct intel_plane_state *plane_state)
9169 struct drm_device *dev = crtc->dev;
9170 struct drm_i915_private *dev_priv = to_i915(dev);
9171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9172 uint32_t cntl = 0, size = 0;
9174 if (plane_state && plane_state->base.visible) {
9175 unsigned int width = plane_state->base.crtc_w;
9176 unsigned int height = plane_state->base.crtc_h;
9178 cntl = plane_state->ctl;
9179 size = (height << 12) | width;
9182 if (intel_crtc->cursor_cntl != 0 &&
9183 (intel_crtc->cursor_base != base ||
9184 intel_crtc->cursor_size != size ||
9185 intel_crtc->cursor_cntl != cntl)) {
9186 /* On these chipsets we can only modify the base/size/stride
9187 * whilst the cursor is disabled.
9189 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9190 POSTING_READ_FW(CURCNTR(PIPE_A));
9191 intel_crtc->cursor_cntl = 0;
9194 if (intel_crtc->cursor_base != base) {
9195 I915_WRITE_FW(CURBASE(PIPE_A), base);
9196 intel_crtc->cursor_base = base;
9199 if (intel_crtc->cursor_size != size) {
9200 I915_WRITE_FW(CURSIZE, size);
9201 intel_crtc->cursor_size = size;
9204 if (intel_crtc->cursor_cntl != cntl) {
9205 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9206 POSTING_READ_FW(CURCNTR(PIPE_A));
9207 intel_crtc->cursor_cntl = cntl;
9211 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9212 const struct intel_plane_state *plane_state)
9214 struct drm_i915_private *dev_priv =
9215 to_i915(plane_state->base.plane->dev);
9216 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9217 enum pipe pipe = crtc->pipe;
9220 cntl = MCURSOR_GAMMA_ENABLE;
9222 if (HAS_DDI(dev_priv))
9223 cntl |= CURSOR_PIPE_CSC_ENABLE;
9225 cntl |= pipe << 28; /* Connect to correct pipe */
9227 switch (plane_state->base.crtc_w) {
9229 cntl |= CURSOR_MODE_64_ARGB_AX;
9232 cntl |= CURSOR_MODE_128_ARGB_AX;
9235 cntl |= CURSOR_MODE_256_ARGB_AX;
9238 MISSING_CASE(plane_state->base.crtc_w);
9242 if (plane_state->base.rotation & DRM_ROTATE_180)
9243 cntl |= CURSOR_ROTATE_180;
9248 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
9249 const struct intel_plane_state *plane_state)
9251 struct drm_device *dev = crtc->dev;
9252 struct drm_i915_private *dev_priv = to_i915(dev);
9253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9254 int pipe = intel_crtc->pipe;
9257 if (plane_state && plane_state->base.visible)
9258 cntl = plane_state->ctl;
9260 if (intel_crtc->cursor_cntl != cntl) {
9261 I915_WRITE_FW(CURCNTR(pipe), cntl);
9262 POSTING_READ_FW(CURCNTR(pipe));
9263 intel_crtc->cursor_cntl = cntl;
9266 /* and commit changes on next vblank */
9267 I915_WRITE_FW(CURBASE(pipe), base);
9268 POSTING_READ_FW(CURBASE(pipe));
9270 intel_crtc->cursor_base = base;
9273 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9274 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9275 const struct intel_plane_state *plane_state)
9277 struct drm_device *dev = crtc->dev;
9278 struct drm_i915_private *dev_priv = to_i915(dev);
9279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9280 int pipe = intel_crtc->pipe;
9281 u32 base = intel_crtc->cursor_addr;
9282 unsigned long irqflags;
9286 int x = plane_state->base.crtc_x;
9287 int y = plane_state->base.crtc_y;
9290 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9293 pos |= x << CURSOR_X_SHIFT;
9296 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9299 pos |= y << CURSOR_Y_SHIFT;
9301 /* ILK+ do this automagically */
9302 if (HAS_GMCH_DISPLAY(dev_priv) &&
9303 plane_state->base.rotation & DRM_ROTATE_180) {
9304 base += (plane_state->base.crtc_h *
9305 plane_state->base.crtc_w - 1) * 4;
9309 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9311 I915_WRITE_FW(CURPOS(pipe), pos);
9313 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
9314 i845_update_cursor(crtc, base, plane_state);
9316 i9xx_update_cursor(crtc, base, plane_state);
9318 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9321 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
9322 uint32_t width, uint32_t height)
9324 if (width == 0 || height == 0)
9328 * 845g/865g are special in that they are only limited by
9329 * the width of their cursors, the height is arbitrary up to
9330 * the precision of the register. Everything else requires
9331 * square cursors, limited to a few power-of-two sizes.
9333 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
9334 if ((width & 63) != 0)
9337 if (width > (IS_I845G(dev_priv) ? 64 : 512))
9343 switch (width | height) {
9346 if (IS_GEN2(dev_priv))
9358 /* VESA 640x480x72Hz mode to set on the pipe */
9359 static struct drm_display_mode load_detect_mode = {
9360 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9361 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9364 struct drm_framebuffer *
9365 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9366 struct drm_mode_fb_cmd2 *mode_cmd)
9368 struct intel_framebuffer *intel_fb;
9371 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9373 return ERR_PTR(-ENOMEM);
9375 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9379 return &intel_fb->base;
9383 return ERR_PTR(ret);
9387 intel_framebuffer_pitch_for_width(int width, int bpp)
9389 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9390 return ALIGN(pitch, 64);
9394 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9396 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9397 return PAGE_ALIGN(pitch * mode->vdisplay);
9400 static struct drm_framebuffer *
9401 intel_framebuffer_create_for_mode(struct drm_device *dev,
9402 struct drm_display_mode *mode,
9405 struct drm_framebuffer *fb;
9406 struct drm_i915_gem_object *obj;
9407 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9409 obj = i915_gem_object_create(to_i915(dev),
9410 intel_framebuffer_size_for_mode(mode, bpp));
9412 return ERR_CAST(obj);
9414 mode_cmd.width = mode->hdisplay;
9415 mode_cmd.height = mode->vdisplay;
9416 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9418 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9420 fb = intel_framebuffer_create(obj, &mode_cmd);
9422 i915_gem_object_put(obj);
9427 static struct drm_framebuffer *
9428 mode_fits_in_fbdev(struct drm_device *dev,
9429 struct drm_display_mode *mode)
9431 #ifdef CONFIG_DRM_FBDEV_EMULATION
9432 struct drm_i915_private *dev_priv = to_i915(dev);
9433 struct drm_i915_gem_object *obj;
9434 struct drm_framebuffer *fb;
9436 if (!dev_priv->fbdev)
9439 if (!dev_priv->fbdev->fb)
9442 obj = dev_priv->fbdev->fb->obj;
9445 fb = &dev_priv->fbdev->fb->base;
9446 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9447 fb->format->cpp[0] * 8))
9450 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9453 drm_framebuffer_reference(fb);
9460 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9461 struct drm_crtc *crtc,
9462 struct drm_display_mode *mode,
9463 struct drm_framebuffer *fb,
9466 struct drm_plane_state *plane_state;
9467 int hdisplay, vdisplay;
9470 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9471 if (IS_ERR(plane_state))
9472 return PTR_ERR(plane_state);
9475 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9477 hdisplay = vdisplay = 0;
9479 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9482 drm_atomic_set_fb_for_plane(plane_state, fb);
9483 plane_state->crtc_x = 0;
9484 plane_state->crtc_y = 0;
9485 plane_state->crtc_w = hdisplay;
9486 plane_state->crtc_h = vdisplay;
9487 plane_state->src_x = x << 16;
9488 plane_state->src_y = y << 16;
9489 plane_state->src_w = hdisplay << 16;
9490 plane_state->src_h = vdisplay << 16;
9495 int intel_get_load_detect_pipe(struct drm_connector *connector,
9496 struct drm_display_mode *mode,
9497 struct intel_load_detect_pipe *old,
9498 struct drm_modeset_acquire_ctx *ctx)
9500 struct intel_crtc *intel_crtc;
9501 struct intel_encoder *intel_encoder =
9502 intel_attached_encoder(connector);
9503 struct drm_crtc *possible_crtc;
9504 struct drm_encoder *encoder = &intel_encoder->base;
9505 struct drm_crtc *crtc = NULL;
9506 struct drm_device *dev = encoder->dev;
9507 struct drm_i915_private *dev_priv = to_i915(dev);
9508 struct drm_framebuffer *fb;
9509 struct drm_mode_config *config = &dev->mode_config;
9510 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9511 struct drm_connector_state *connector_state;
9512 struct intel_crtc_state *crtc_state;
9515 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9516 connector->base.id, connector->name,
9517 encoder->base.id, encoder->name);
9519 old->restore_state = NULL;
9521 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9524 * Algorithm gets a little messy:
9526 * - if the connector already has an assigned crtc, use it (but make
9527 * sure it's on first)
9529 * - try to find the first unused crtc that can drive this connector,
9530 * and use that if we find one
9533 /* See if we already have a CRTC for this connector */
9534 if (connector->state->crtc) {
9535 crtc = connector->state->crtc;
9537 ret = drm_modeset_lock(&crtc->mutex, ctx);
9541 /* Make sure the crtc and connector are running */
9545 /* Find an unused one (if possible) */
9546 for_each_crtc(dev, possible_crtc) {
9548 if (!(encoder->possible_crtcs & (1 << i)))
9551 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9555 if (possible_crtc->state->enable) {
9556 drm_modeset_unlock(&possible_crtc->mutex);
9560 crtc = possible_crtc;
9565 * If we didn't find an unused CRTC, don't use any.
9568 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9573 intel_crtc = to_intel_crtc(crtc);
9575 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9579 state = drm_atomic_state_alloc(dev);
9580 restore_state = drm_atomic_state_alloc(dev);
9581 if (!state || !restore_state) {
9586 state->acquire_ctx = ctx;
9587 restore_state->acquire_ctx = ctx;
9589 connector_state = drm_atomic_get_connector_state(state, connector);
9590 if (IS_ERR(connector_state)) {
9591 ret = PTR_ERR(connector_state);
9595 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9599 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9600 if (IS_ERR(crtc_state)) {
9601 ret = PTR_ERR(crtc_state);
9605 crtc_state->base.active = crtc_state->base.enable = true;
9608 mode = &load_detect_mode;
9610 /* We need a framebuffer large enough to accommodate all accesses
9611 * that the plane may generate whilst we perform load detection.
9612 * We can not rely on the fbcon either being present (we get called
9613 * during its initialisation to detect all boot displays, or it may
9614 * not even exist) or that it is large enough to satisfy the
9617 fb = mode_fits_in_fbdev(dev, mode);
9619 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9620 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9622 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9624 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9628 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9632 drm_framebuffer_unreference(fb);
9634 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9638 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9640 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9642 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9644 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9648 ret = drm_atomic_commit(state);
9650 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9654 old->restore_state = restore_state;
9655 drm_atomic_state_put(state);
9657 /* let the connector get through one full cycle before testing */
9658 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9663 drm_atomic_state_put(state);
9666 if (restore_state) {
9667 drm_atomic_state_put(restore_state);
9668 restore_state = NULL;
9671 if (ret == -EDEADLK)
9677 void intel_release_load_detect_pipe(struct drm_connector *connector,
9678 struct intel_load_detect_pipe *old,
9679 struct drm_modeset_acquire_ctx *ctx)
9681 struct intel_encoder *intel_encoder =
9682 intel_attached_encoder(connector);
9683 struct drm_encoder *encoder = &intel_encoder->base;
9684 struct drm_atomic_state *state = old->restore_state;
9687 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9688 connector->base.id, connector->name,
9689 encoder->base.id, encoder->name);
9694 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9696 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9697 drm_atomic_state_put(state);
9700 static int i9xx_pll_refclk(struct drm_device *dev,
9701 const struct intel_crtc_state *pipe_config)
9703 struct drm_i915_private *dev_priv = to_i915(dev);
9704 u32 dpll = pipe_config->dpll_hw_state.dpll;
9706 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9707 return dev_priv->vbt.lvds_ssc_freq;
9708 else if (HAS_PCH_SPLIT(dev_priv))
9710 else if (!IS_GEN2(dev_priv))
9716 /* Returns the clock of the currently programmed mode of the given pipe. */
9717 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9718 struct intel_crtc_state *pipe_config)
9720 struct drm_device *dev = crtc->base.dev;
9721 struct drm_i915_private *dev_priv = to_i915(dev);
9722 int pipe = pipe_config->cpu_transcoder;
9723 u32 dpll = pipe_config->dpll_hw_state.dpll;
9727 int refclk = i9xx_pll_refclk(dev, pipe_config);
9729 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9730 fp = pipe_config->dpll_hw_state.fp0;
9732 fp = pipe_config->dpll_hw_state.fp1;
9734 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9735 if (IS_PINEVIEW(dev_priv)) {
9736 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9737 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9739 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9740 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9743 if (!IS_GEN2(dev_priv)) {
9744 if (IS_PINEVIEW(dev_priv))
9745 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9746 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9748 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9749 DPLL_FPA01_P1_POST_DIV_SHIFT);
9751 switch (dpll & DPLL_MODE_MASK) {
9752 case DPLLB_MODE_DAC_SERIAL:
9753 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9756 case DPLLB_MODE_LVDS:
9757 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9761 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9762 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9766 if (IS_PINEVIEW(dev_priv))
9767 port_clock = pnv_calc_dpll_params(refclk, &clock);
9769 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9771 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9772 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9775 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9776 DPLL_FPA01_P1_POST_DIV_SHIFT);
9778 if (lvds & LVDS_CLKB_POWER_UP)
9783 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9786 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9787 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9789 if (dpll & PLL_P2_DIVIDE_BY_4)
9795 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9799 * This value includes pixel_multiplier. We will use
9800 * port_clock to compute adjusted_mode.crtc_clock in the
9801 * encoder's get_config() function.
9803 pipe_config->port_clock = port_clock;
9806 int intel_dotclock_calculate(int link_freq,
9807 const struct intel_link_m_n *m_n)
9810 * The calculation for the data clock is:
9811 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9812 * But we want to avoid losing precison if possible, so:
9813 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9815 * and the link clock is simpler:
9816 * link_clock = (m * link_clock) / n
9822 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9825 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9826 struct intel_crtc_state *pipe_config)
9828 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9830 /* read out port_clock from the DPLL */
9831 i9xx_crtc_clock_get(crtc, pipe_config);
9834 * In case there is an active pipe without active ports,
9835 * we may need some idea for the dotclock anyway.
9836 * Calculate one based on the FDI configuration.
9838 pipe_config->base.adjusted_mode.crtc_clock =
9839 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
9840 &pipe_config->fdi_m_n);
9843 /** Returns the currently programmed mode of the given pipe. */
9844 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9845 struct drm_crtc *crtc)
9847 struct drm_i915_private *dev_priv = to_i915(dev);
9848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9849 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9850 struct drm_display_mode *mode;
9851 struct intel_crtc_state *pipe_config;
9852 int htot = I915_READ(HTOTAL(cpu_transcoder));
9853 int hsync = I915_READ(HSYNC(cpu_transcoder));
9854 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9855 int vsync = I915_READ(VSYNC(cpu_transcoder));
9856 enum pipe pipe = intel_crtc->pipe;
9858 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9862 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9869 * Construct a pipe_config sufficient for getting the clock info
9870 * back out of crtc_clock_get.
9872 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9873 * to use a real value here instead.
9875 pipe_config->cpu_transcoder = (enum transcoder) pipe;
9876 pipe_config->pixel_multiplier = 1;
9877 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9878 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9879 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9880 i9xx_crtc_clock_get(intel_crtc, pipe_config);
9882 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
9883 mode->hdisplay = (htot & 0xffff) + 1;
9884 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9885 mode->hsync_start = (hsync & 0xffff) + 1;
9886 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9887 mode->vdisplay = (vtot & 0xffff) + 1;
9888 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9889 mode->vsync_start = (vsync & 0xffff) + 1;
9890 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9892 drm_mode_set_name(mode);
9899 static void intel_crtc_destroy(struct drm_crtc *crtc)
9901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9902 struct drm_device *dev = crtc->dev;
9903 struct intel_flip_work *work;
9905 spin_lock_irq(&dev->event_lock);
9906 work = intel_crtc->flip_work;
9907 intel_crtc->flip_work = NULL;
9908 spin_unlock_irq(&dev->event_lock);
9911 cancel_work_sync(&work->mmio_work);
9912 cancel_work_sync(&work->unpin_work);
9916 drm_crtc_cleanup(crtc);
9921 static void intel_unpin_work_fn(struct work_struct *__work)
9923 struct intel_flip_work *work =
9924 container_of(__work, struct intel_flip_work, unpin_work);
9925 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
9926 struct drm_device *dev = crtc->base.dev;
9927 struct drm_plane *primary = crtc->base.primary;
9929 if (is_mmio_work(work))
9930 flush_work(&work->mmio_work);
9932 mutex_lock(&dev->struct_mutex);
9933 intel_unpin_fb_vma(work->old_vma);
9934 i915_gem_object_put(work->pending_flip_obj);
9935 mutex_unlock(&dev->struct_mutex);
9937 i915_gem_request_put(work->flip_queued_req);
9939 intel_frontbuffer_flip_complete(to_i915(dev),
9940 to_intel_plane(primary)->frontbuffer_bit);
9941 intel_fbc_post_update(crtc);
9942 drm_framebuffer_unreference(work->old_fb);
9944 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
9945 atomic_dec(&crtc->unpin_work_count);
9950 /* Is 'a' after or equal to 'b'? */
9951 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9953 return !((a - b) & 0x80000000);
9956 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
9957 struct intel_flip_work *work)
9959 struct drm_device *dev = crtc->base.dev;
9960 struct drm_i915_private *dev_priv = to_i915(dev);
9962 if (abort_flip_on_reset(crtc))
9966 * The relevant registers doen't exist on pre-ctg.
9967 * As the flip done interrupt doesn't trigger for mmio
9968 * flips on gmch platforms, a flip count check isn't
9969 * really needed there. But since ctg has the registers,
9970 * include it in the check anyway.
9972 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
9976 * BDW signals flip done immediately if the plane
9977 * is disabled, even if the plane enable is already
9978 * armed to occur at the next vblank :(
9982 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9983 * used the same base address. In that case the mmio flip might
9984 * have completed, but the CS hasn't even executed the flip yet.
9986 * A flip count check isn't enough as the CS might have updated
9987 * the base address just after start of vblank, but before we
9988 * managed to process the interrupt. This means we'd complete the
9991 * Combining both checks should get us a good enough result. It may
9992 * still happen that the CS flip has been executed, but has not
9993 * yet actually completed. But in case the base address is the same
9994 * anyway, we don't really care.
9996 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9997 crtc->flip_work->gtt_offset &&
9998 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
9999 crtc->flip_work->flip_count);
10003 __pageflip_finished_mmio(struct intel_crtc *crtc,
10004 struct intel_flip_work *work)
10007 * MMIO work completes when vblank is different from
10008 * flip_queued_vblank.
10010 * Reset counter value doesn't matter, this is handled by
10011 * i915_wait_request finishing early, so no need to handle
10014 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10018 static bool pageflip_finished(struct intel_crtc *crtc,
10019 struct intel_flip_work *work)
10021 if (!atomic_read(&work->pending))
10026 if (is_mmio_work(work))
10027 return __pageflip_finished_mmio(crtc, work);
10029 return __pageflip_finished_cs(crtc, work);
10032 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10034 struct drm_device *dev = &dev_priv->drm;
10035 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10036 struct intel_flip_work *work;
10037 unsigned long flags;
10039 /* Ignore early vblank irqs */
10044 * This is called both by irq handlers and the reset code (to complete
10045 * lost pageflips) so needs the full irqsave spinlocks.
10047 spin_lock_irqsave(&dev->event_lock, flags);
10048 work = crtc->flip_work;
10050 if (work != NULL &&
10051 !is_mmio_work(work) &&
10052 pageflip_finished(crtc, work))
10053 page_flip_completed(crtc);
10055 spin_unlock_irqrestore(&dev->event_lock, flags);
10058 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10060 struct drm_device *dev = &dev_priv->drm;
10061 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10062 struct intel_flip_work *work;
10063 unsigned long flags;
10065 /* Ignore early vblank irqs */
10070 * This is called both by irq handlers and the reset code (to complete
10071 * lost pageflips) so needs the full irqsave spinlocks.
10073 spin_lock_irqsave(&dev->event_lock, flags);
10074 work = crtc->flip_work;
10076 if (work != NULL &&
10077 is_mmio_work(work) &&
10078 pageflip_finished(crtc, work))
10079 page_flip_completed(crtc);
10081 spin_unlock_irqrestore(&dev->event_lock, flags);
10084 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10085 struct intel_flip_work *work)
10087 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10089 /* Ensure that the work item is consistent when activating it ... */
10090 smp_mb__before_atomic();
10091 atomic_set(&work->pending, 1);
10094 static int intel_gen2_queue_flip(struct drm_device *dev,
10095 struct drm_crtc *crtc,
10096 struct drm_framebuffer *fb,
10097 struct drm_i915_gem_object *obj,
10098 struct drm_i915_gem_request *req,
10101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10102 u32 flip_mask, *cs;
10104 cs = intel_ring_begin(req, 6);
10106 return PTR_ERR(cs);
10108 /* Can't queue multiple flips, so wait for the previous
10109 * one to finish before executing the next.
10111 if (intel_crtc->plane)
10112 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10114 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10115 *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10117 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10118 *cs++ = fb->pitches[0];
10119 *cs++ = intel_crtc->flip_work->gtt_offset;
10120 *cs++ = 0; /* aux display base address, unused */
10125 static int intel_gen3_queue_flip(struct drm_device *dev,
10126 struct drm_crtc *crtc,
10127 struct drm_framebuffer *fb,
10128 struct drm_i915_gem_object *obj,
10129 struct drm_i915_gem_request *req,
10132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10133 u32 flip_mask, *cs;
10135 cs = intel_ring_begin(req, 6);
10137 return PTR_ERR(cs);
10139 if (intel_crtc->plane)
10140 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10142 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10143 *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10145 *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10146 *cs++ = fb->pitches[0];
10147 *cs++ = intel_crtc->flip_work->gtt_offset;
10153 static int intel_gen4_queue_flip(struct drm_device *dev,
10154 struct drm_crtc *crtc,
10155 struct drm_framebuffer *fb,
10156 struct drm_i915_gem_object *obj,
10157 struct drm_i915_gem_request *req,
10160 struct drm_i915_private *dev_priv = to_i915(dev);
10161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10162 u32 pf, pipesrc, *cs;
10164 cs = intel_ring_begin(req, 4);
10166 return PTR_ERR(cs);
10168 /* i965+ uses the linear or tiled offsets from the
10169 * Display Registers (which do not change across a page-flip)
10170 * so we need only reprogram the base address.
10172 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10173 *cs++ = fb->pitches[0];
10174 *cs++ = intel_crtc->flip_work->gtt_offset |
10175 intel_fb_modifier_to_tiling(fb->modifier);
10177 /* XXX Enabling the panel-fitter across page-flip is so far
10178 * untested on non-native modes, so ignore it for now.
10179 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10182 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10183 *cs++ = pf | pipesrc;
10188 static int intel_gen6_queue_flip(struct drm_device *dev,
10189 struct drm_crtc *crtc,
10190 struct drm_framebuffer *fb,
10191 struct drm_i915_gem_object *obj,
10192 struct drm_i915_gem_request *req,
10195 struct drm_i915_private *dev_priv = to_i915(dev);
10196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10197 u32 pf, pipesrc, *cs;
10199 cs = intel_ring_begin(req, 4);
10201 return PTR_ERR(cs);
10203 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10204 *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10205 *cs++ = intel_crtc->flip_work->gtt_offset;
10207 /* Contrary to the suggestions in the documentation,
10208 * "Enable Panel Fitter" does not seem to be required when page
10209 * flipping with a non-native mode, and worse causes a normal
10211 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10214 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10215 *cs++ = pf | pipesrc;
10220 static int intel_gen7_queue_flip(struct drm_device *dev,
10221 struct drm_crtc *crtc,
10222 struct drm_framebuffer *fb,
10223 struct drm_i915_gem_object *obj,
10224 struct drm_i915_gem_request *req,
10227 struct drm_i915_private *dev_priv = to_i915(dev);
10228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10229 u32 *cs, plane_bit = 0;
10232 switch (intel_crtc->plane) {
10234 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10237 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10240 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10243 WARN_ONCE(1, "unknown plane in flip command\n");
10248 if (req->engine->id == RCS) {
10251 * On Gen 8, SRM is now taking an extra dword to accommodate
10252 * 48bits addresses, and we need a NOOP for the batch size to
10255 if (IS_GEN8(dev_priv))
10260 * BSpec MI_DISPLAY_FLIP for IVB:
10261 * "The full packet must be contained within the same cache line."
10263 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10264 * cacheline, if we ever start emitting more commands before
10265 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10266 * then do the cacheline alignment, and finally emit the
10269 ret = intel_ring_cacheline_align(req);
10273 cs = intel_ring_begin(req, len);
10275 return PTR_ERR(cs);
10277 /* Unmask the flip-done completion message. Note that the bspec says that
10278 * we should do this for both the BCS and RCS, and that we must not unmask
10279 * more than one flip event at any time (or ensure that one flip message
10280 * can be sent by waiting for flip-done prior to queueing new flips).
10281 * Experimentation says that BCS works despite DERRMR masking all
10282 * flip-done completion events and that unmasking all planes at once
10283 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10284 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10286 if (req->engine->id == RCS) {
10287 *cs++ = MI_LOAD_REGISTER_IMM(1);
10288 *cs++ = i915_mmio_reg_offset(DERRMR);
10289 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10290 DERRMR_PIPEB_PRI_FLIP_DONE |
10291 DERRMR_PIPEC_PRI_FLIP_DONE);
10292 if (IS_GEN8(dev_priv))
10293 *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10294 MI_SRM_LRM_GLOBAL_GTT;
10296 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10297 *cs++ = i915_mmio_reg_offset(DERRMR);
10298 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
10299 if (IS_GEN8(dev_priv)) {
10305 *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10306 *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10307 *cs++ = intel_crtc->flip_work->gtt_offset;
10313 static bool use_mmio_flip(struct intel_engine_cs *engine,
10314 struct drm_i915_gem_object *obj)
10317 * This is not being used for older platforms, because
10318 * non-availability of flip done interrupt forces us to use
10319 * CS flips. Older platforms derive flip done using some clever
10320 * tricks involving the flip_pending status bits and vblank irqs.
10321 * So using MMIO flips there would disrupt this mechanism.
10324 if (engine == NULL)
10327 if (INTEL_GEN(engine->i915) < 5)
10330 if (i915.use_mmio_flip < 0)
10332 else if (i915.use_mmio_flip > 0)
10334 else if (i915.enable_execlists)
10337 return engine != i915_gem_object_last_write_engine(obj);
10340 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10341 unsigned int rotation,
10342 struct intel_flip_work *work)
10344 struct drm_device *dev = intel_crtc->base.dev;
10345 struct drm_i915_private *dev_priv = to_i915(dev);
10346 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10347 const enum pipe pipe = intel_crtc->pipe;
10348 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10350 ctl = I915_READ(PLANE_CTL(pipe, 0));
10351 ctl &= ~PLANE_CTL_TILED_MASK;
10352 switch (fb->modifier) {
10353 case DRM_FORMAT_MOD_LINEAR:
10355 case I915_FORMAT_MOD_X_TILED:
10356 ctl |= PLANE_CTL_TILED_X;
10358 case I915_FORMAT_MOD_Y_TILED:
10359 ctl |= PLANE_CTL_TILED_Y;
10361 case I915_FORMAT_MOD_Yf_TILED:
10362 ctl |= PLANE_CTL_TILED_YF;
10365 MISSING_CASE(fb->modifier);
10369 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10370 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10372 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10373 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10375 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10376 POSTING_READ(PLANE_SURF(pipe, 0));
10379 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10380 struct intel_flip_work *work)
10382 struct drm_device *dev = intel_crtc->base.dev;
10383 struct drm_i915_private *dev_priv = to_i915(dev);
10384 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10385 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10388 dspcntr = I915_READ(reg);
10390 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10391 dspcntr |= DISPPLANE_TILED;
10393 dspcntr &= ~DISPPLANE_TILED;
10395 I915_WRITE(reg, dspcntr);
10397 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10398 POSTING_READ(DSPSURF(intel_crtc->plane));
10401 static void intel_mmio_flip_work_func(struct work_struct *w)
10403 struct intel_flip_work *work =
10404 container_of(w, struct intel_flip_work, mmio_work);
10405 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10406 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10407 struct intel_framebuffer *intel_fb =
10408 to_intel_framebuffer(crtc->base.primary->fb);
10409 struct drm_i915_gem_object *obj = intel_fb->obj;
10411 WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10413 intel_pipe_update_start(crtc);
10415 if (INTEL_GEN(dev_priv) >= 9)
10416 skl_do_mmio_flip(crtc, work->rotation, work);
10418 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10419 ilk_do_mmio_flip(crtc, work);
10421 intel_pipe_update_end(crtc, work);
10424 static int intel_default_queue_flip(struct drm_device *dev,
10425 struct drm_crtc *crtc,
10426 struct drm_framebuffer *fb,
10427 struct drm_i915_gem_object *obj,
10428 struct drm_i915_gem_request *req,
10434 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10435 struct intel_crtc *intel_crtc,
10436 struct intel_flip_work *work)
10440 if (!atomic_read(&work->pending))
10445 vblank = intel_crtc_get_vblank_counter(intel_crtc);
10446 if (work->flip_ready_vblank == 0) {
10447 if (work->flip_queued_req &&
10448 !i915_gem_request_completed(work->flip_queued_req))
10451 work->flip_ready_vblank = vblank;
10454 if (vblank - work->flip_ready_vblank < 3)
10457 /* Potential stall - if we see that the flip has happened,
10458 * assume a missed interrupt. */
10459 if (INTEL_GEN(dev_priv) >= 4)
10460 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10462 addr = I915_READ(DSPADDR(intel_crtc->plane));
10464 /* There is a potential issue here with a false positive after a flip
10465 * to the same address. We could address this by checking for a
10466 * non-incrementing frame counter.
10468 return addr == work->gtt_offset;
10471 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10473 struct drm_device *dev = &dev_priv->drm;
10474 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10475 struct intel_flip_work *work;
10477 WARN_ON(!in_interrupt());
10482 spin_lock(&dev->event_lock);
10483 work = crtc->flip_work;
10485 if (work != NULL && !is_mmio_work(work) &&
10486 __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10488 "Kicking stuck page flip: queued at %d, now %d\n",
10489 work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10490 page_flip_completed(crtc);
10494 if (work != NULL && !is_mmio_work(work) &&
10495 intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10496 intel_queue_rps_boost_for_request(work->flip_queued_req);
10497 spin_unlock(&dev->event_lock);
10501 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10502 struct drm_framebuffer *fb,
10503 struct drm_pending_vblank_event *event,
10504 uint32_t page_flip_flags)
10506 struct drm_device *dev = crtc->dev;
10507 struct drm_i915_private *dev_priv = to_i915(dev);
10508 struct drm_framebuffer *old_fb = crtc->primary->fb;
10509 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10511 struct drm_plane *primary = crtc->primary;
10512 enum pipe pipe = intel_crtc->pipe;
10513 struct intel_flip_work *work;
10514 struct intel_engine_cs *engine;
10516 struct drm_i915_gem_request *request;
10517 struct i915_vma *vma;
10521 * drm_mode_page_flip_ioctl() should already catch this, but double
10522 * check to be safe. In the future we may enable pageflipping from
10523 * a disabled primary plane.
10525 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10528 /* Can't change pixel format via MI display flips. */
10529 if (fb->format != crtc->primary->fb->format)
10533 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10534 * Note that pitch changes could also affect these register.
10536 if (INTEL_GEN(dev_priv) > 3 &&
10537 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10538 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10541 if (i915_terminally_wedged(&dev_priv->gpu_error))
10544 work = kzalloc(sizeof(*work), GFP_KERNEL);
10548 work->event = event;
10550 work->old_fb = old_fb;
10551 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10553 ret = drm_crtc_vblank_get(crtc);
10557 /* We borrow the event spin lock for protecting flip_work */
10558 spin_lock_irq(&dev->event_lock);
10559 if (intel_crtc->flip_work) {
10560 /* Before declaring the flip queue wedged, check if
10561 * the hardware completed the operation behind our backs.
10563 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10564 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10565 page_flip_completed(intel_crtc);
10567 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10568 spin_unlock_irq(&dev->event_lock);
10570 drm_crtc_vblank_put(crtc);
10575 intel_crtc->flip_work = work;
10576 spin_unlock_irq(&dev->event_lock);
10578 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10579 flush_workqueue(dev_priv->wq);
10581 /* Reference the objects for the scheduled work. */
10582 drm_framebuffer_reference(work->old_fb);
10584 crtc->primary->fb = fb;
10585 update_state_fb(crtc->primary);
10587 work->pending_flip_obj = i915_gem_object_get(obj);
10589 ret = i915_mutex_lock_interruptible(dev);
10593 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10594 if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) {
10599 atomic_inc(&intel_crtc->unpin_work_count);
10601 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10602 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10604 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10605 engine = dev_priv->engine[BCS];
10606 if (fb->modifier != old_fb->modifier)
10607 /* vlv: DISPLAY_FLIP fails to change tiling */
10609 } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10610 engine = dev_priv->engine[BCS];
10611 } else if (INTEL_GEN(dev_priv) >= 7) {
10612 engine = i915_gem_object_last_write_engine(obj);
10613 if (engine == NULL || engine->id != RCS)
10614 engine = dev_priv->engine[BCS];
10616 engine = dev_priv->engine[RCS];
10619 mmio_flip = use_mmio_flip(engine, obj);
10621 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10623 ret = PTR_ERR(vma);
10624 goto cleanup_pending;
10627 work->old_vma = to_intel_plane_state(primary->state)->vma;
10628 to_intel_plane_state(primary->state)->vma = vma;
10630 work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10631 work->rotation = crtc->primary->state->rotation;
10634 * There's the potential that the next frame will not be compatible with
10635 * FBC, so we want to call pre_update() before the actual page flip.
10636 * The problem is that pre_update() caches some information about the fb
10637 * object, so we want to do this only after the object is pinned. Let's
10638 * be on the safe side and do this immediately before scheduling the
10641 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10642 to_intel_plane_state(primary->state));
10645 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10646 queue_work(system_unbound_wq, &work->mmio_work);
10648 request = i915_gem_request_alloc(engine,
10649 dev_priv->kernel_context);
10650 if (IS_ERR(request)) {
10651 ret = PTR_ERR(request);
10652 goto cleanup_unpin;
10655 ret = i915_gem_request_await_object(request, obj, false);
10657 goto cleanup_request;
10659 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10662 goto cleanup_request;
10664 intel_mark_page_flip_active(intel_crtc, work);
10666 work->flip_queued_req = i915_gem_request_get(request);
10667 i915_add_request(request);
10670 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10671 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10672 to_intel_plane(primary)->frontbuffer_bit);
10673 mutex_unlock(&dev->struct_mutex);
10675 intel_frontbuffer_flip_prepare(to_i915(dev),
10676 to_intel_plane(primary)->frontbuffer_bit);
10678 trace_i915_flip_request(intel_crtc->plane, obj);
10683 i915_add_request(request);
10685 to_intel_plane_state(primary->state)->vma = work->old_vma;
10686 intel_unpin_fb_vma(vma);
10688 atomic_dec(&intel_crtc->unpin_work_count);
10690 mutex_unlock(&dev->struct_mutex);
10692 crtc->primary->fb = old_fb;
10693 update_state_fb(crtc->primary);
10695 i915_gem_object_put(obj);
10696 drm_framebuffer_unreference(work->old_fb);
10698 spin_lock_irq(&dev->event_lock);
10699 intel_crtc->flip_work = NULL;
10700 spin_unlock_irq(&dev->event_lock);
10702 drm_crtc_vblank_put(crtc);
10707 struct drm_atomic_state *state;
10708 struct drm_plane_state *plane_state;
10711 state = drm_atomic_state_alloc(dev);
10714 state->acquire_ctx = dev->mode_config.acquire_ctx;
10717 plane_state = drm_atomic_get_plane_state(state, primary);
10718 ret = PTR_ERR_OR_ZERO(plane_state);
10720 drm_atomic_set_fb_for_plane(plane_state, fb);
10722 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10724 ret = drm_atomic_commit(state);
10727 if (ret == -EDEADLK) {
10728 drm_modeset_backoff(state->acquire_ctx);
10729 drm_atomic_state_clear(state);
10733 drm_atomic_state_put(state);
10735 if (ret == 0 && event) {
10736 spin_lock_irq(&dev->event_lock);
10737 drm_crtc_send_vblank_event(crtc, event);
10738 spin_unlock_irq(&dev->event_lock);
10746 * intel_wm_need_update - Check whether watermarks need updating
10747 * @plane: drm plane
10748 * @state: new plane state
10750 * Check current plane state versus the new one to determine whether
10751 * watermarks need to be recalculated.
10753 * Returns true or false.
10755 static bool intel_wm_need_update(struct drm_plane *plane,
10756 struct drm_plane_state *state)
10758 struct intel_plane_state *new = to_intel_plane_state(state);
10759 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10761 /* Update watermarks on tiling or size changes. */
10762 if (new->base.visible != cur->base.visible)
10765 if (!cur->base.fb || !new->base.fb)
10768 if (cur->base.fb->modifier != new->base.fb->modifier ||
10769 cur->base.rotation != new->base.rotation ||
10770 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10771 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10772 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10773 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10779 static bool needs_scaling(struct intel_plane_state *state)
10781 int src_w = drm_rect_width(&state->base.src) >> 16;
10782 int src_h = drm_rect_height(&state->base.src) >> 16;
10783 int dst_w = drm_rect_width(&state->base.dst);
10784 int dst_h = drm_rect_height(&state->base.dst);
10786 return (src_w != dst_w || src_h != dst_h);
10789 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10790 struct drm_plane_state *plane_state)
10792 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10793 struct drm_crtc *crtc = crtc_state->crtc;
10794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10795 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10796 struct drm_device *dev = crtc->dev;
10797 struct drm_i915_private *dev_priv = to_i915(dev);
10798 struct intel_plane_state *old_plane_state =
10799 to_intel_plane_state(plane->base.state);
10800 bool mode_changed = needs_modeset(crtc_state);
10801 bool was_crtc_enabled = crtc->state->active;
10802 bool is_crtc_enabled = crtc_state->active;
10803 bool turn_off, turn_on, visible, was_visible;
10804 struct drm_framebuffer *fb = plane_state->fb;
10807 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10808 ret = skl_update_scaler_plane(
10809 to_intel_crtc_state(crtc_state),
10810 to_intel_plane_state(plane_state));
10815 was_visible = old_plane_state->base.visible;
10816 visible = plane_state->visible;
10818 if (!was_crtc_enabled && WARN_ON(was_visible))
10819 was_visible = false;
10822 * Visibility is calculated as if the crtc was on, but
10823 * after scaler setup everything depends on it being off
10824 * when the crtc isn't active.
10826 * FIXME this is wrong for watermarks. Watermarks should also
10827 * be computed as if the pipe would be active. Perhaps move
10828 * per-plane wm computation to the .check_plane() hook, and
10829 * only combine the results from all planes in the current place?
10831 if (!is_crtc_enabled) {
10832 plane_state->visible = visible = false;
10833 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10836 if (!was_visible && !visible)
10839 if (fb != old_plane_state->base.fb)
10840 pipe_config->fb_changed = true;
10842 turn_off = was_visible && (!visible || mode_changed);
10843 turn_on = visible && (!was_visible || mode_changed);
10845 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10846 intel_crtc->base.base.id, intel_crtc->base.name,
10847 plane->base.base.id, plane->base.name,
10848 fb ? fb->base.id : -1);
10850 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10851 plane->base.base.id, plane->base.name,
10852 was_visible, visible,
10853 turn_off, turn_on, mode_changed);
10856 if (INTEL_GEN(dev_priv) < 5)
10857 pipe_config->update_wm_pre = true;
10859 /* must disable cxsr around plane enable/disable */
10860 if (plane->id != PLANE_CURSOR)
10861 pipe_config->disable_cxsr = true;
10862 } else if (turn_off) {
10863 if (INTEL_GEN(dev_priv) < 5)
10864 pipe_config->update_wm_post = true;
10866 /* must disable cxsr around plane enable/disable */
10867 if (plane->id != PLANE_CURSOR)
10868 pipe_config->disable_cxsr = true;
10869 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10870 if (INTEL_GEN(dev_priv) < 5) {
10871 /* FIXME bollocks */
10872 pipe_config->update_wm_pre = true;
10873 pipe_config->update_wm_post = true;
10877 if (visible || was_visible)
10878 pipe_config->fb_bits |= plane->frontbuffer_bit;
10881 * WaCxSRDisabledForSpriteScaling:ivb
10883 * cstate->update_wm was already set above, so this flag will
10884 * take effect when we commit and program watermarks.
10886 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10887 needs_scaling(to_intel_plane_state(plane_state)) &&
10888 !needs_scaling(old_plane_state))
10889 pipe_config->disable_lp_wm = true;
10894 static bool encoders_cloneable(const struct intel_encoder *a,
10895 const struct intel_encoder *b)
10897 /* masks could be asymmetric, so check both ways */
10898 return a == b || (a->cloneable & (1 << b->type) &&
10899 b->cloneable & (1 << a->type));
10902 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10903 struct intel_crtc *crtc,
10904 struct intel_encoder *encoder)
10906 struct intel_encoder *source_encoder;
10907 struct drm_connector *connector;
10908 struct drm_connector_state *connector_state;
10911 for_each_new_connector_in_state(state, connector, connector_state, i) {
10912 if (connector_state->crtc != &crtc->base)
10916 to_intel_encoder(connector_state->best_encoder);
10917 if (!encoders_cloneable(encoder, source_encoder))
10924 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10925 struct drm_crtc_state *crtc_state)
10927 struct drm_device *dev = crtc->dev;
10928 struct drm_i915_private *dev_priv = to_i915(dev);
10929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10930 struct intel_crtc_state *pipe_config =
10931 to_intel_crtc_state(crtc_state);
10932 struct drm_atomic_state *state = crtc_state->state;
10934 bool mode_changed = needs_modeset(crtc_state);
10936 if (mode_changed && !crtc_state->active)
10937 pipe_config->update_wm_post = true;
10939 if (mode_changed && crtc_state->enable &&
10940 dev_priv->display.crtc_compute_clock &&
10941 !WARN_ON(pipe_config->shared_dpll)) {
10942 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10948 if (crtc_state->color_mgmt_changed) {
10949 ret = intel_color_check(crtc, crtc_state);
10954 * Changing color management on Intel hardware is
10955 * handled as part of planes update.
10957 crtc_state->planes_changed = true;
10961 if (dev_priv->display.compute_pipe_wm) {
10962 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10964 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10969 if (dev_priv->display.compute_intermediate_wm &&
10970 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10971 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10975 * Calculate 'intermediate' watermarks that satisfy both the
10976 * old state and the new state. We can program these
10979 ret = dev_priv->display.compute_intermediate_wm(dev,
10983 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10986 } else if (dev_priv->display.compute_intermediate_wm) {
10987 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10988 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10991 if (INTEL_GEN(dev_priv) >= 9) {
10993 ret = skl_update_scaler_crtc(pipe_config);
10996 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11003 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11004 .atomic_begin = intel_begin_crtc_commit,
11005 .atomic_flush = intel_finish_crtc_commit,
11006 .atomic_check = intel_crtc_atomic_check,
11009 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11011 struct intel_connector *connector;
11012 struct drm_connector_list_iter conn_iter;
11014 drm_connector_list_iter_begin(dev, &conn_iter);
11015 for_each_intel_connector_iter(connector, &conn_iter) {
11016 if (connector->base.state->crtc)
11017 drm_connector_unreference(&connector->base);
11019 if (connector->base.encoder) {
11020 connector->base.state->best_encoder =
11021 connector->base.encoder;
11022 connector->base.state->crtc =
11023 connector->base.encoder->crtc;
11025 drm_connector_reference(&connector->base);
11027 connector->base.state->best_encoder = NULL;
11028 connector->base.state->crtc = NULL;
11031 drm_connector_list_iter_end(&conn_iter);
11035 connected_sink_compute_bpp(struct intel_connector *connector,
11036 struct intel_crtc_state *pipe_config)
11038 const struct drm_display_info *info = &connector->base.display_info;
11039 int bpp = pipe_config->pipe_bpp;
11041 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11042 connector->base.base.id,
11043 connector->base.name);
11045 /* Don't use an invalid EDID bpc value */
11046 if (info->bpc != 0 && info->bpc * 3 < bpp) {
11047 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11048 bpp, info->bpc * 3);
11049 pipe_config->pipe_bpp = info->bpc * 3;
11052 /* Clamp bpp to 8 on screens without EDID 1.4 */
11053 if (info->bpc == 0 && bpp > 24) {
11054 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11056 pipe_config->pipe_bpp = 24;
11061 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11062 struct intel_crtc_state *pipe_config)
11064 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11065 struct drm_atomic_state *state;
11066 struct drm_connector *connector;
11067 struct drm_connector_state *connector_state;
11070 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11071 IS_CHERRYVIEW(dev_priv)))
11073 else if (INTEL_GEN(dev_priv) >= 5)
11079 pipe_config->pipe_bpp = bpp;
11081 state = pipe_config->base.state;
11083 /* Clamp display bpp to EDID value */
11084 for_each_new_connector_in_state(state, connector, connector_state, i) {
11085 if (connector_state->crtc != &crtc->base)
11088 connected_sink_compute_bpp(to_intel_connector(connector),
11095 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11097 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11098 "type: 0x%x flags: 0x%x\n",
11100 mode->crtc_hdisplay, mode->crtc_hsync_start,
11101 mode->crtc_hsync_end, mode->crtc_htotal,
11102 mode->crtc_vdisplay, mode->crtc_vsync_start,
11103 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11107 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11108 unsigned int lane_count, struct intel_link_m_n *m_n)
11110 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11112 m_n->gmch_m, m_n->gmch_n,
11113 m_n->link_m, m_n->link_n, m_n->tu);
11116 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11117 struct intel_crtc_state *pipe_config,
11118 const char *context)
11120 struct drm_device *dev = crtc->base.dev;
11121 struct drm_i915_private *dev_priv = to_i915(dev);
11122 struct drm_plane *plane;
11123 struct intel_plane *intel_plane;
11124 struct intel_plane_state *state;
11125 struct drm_framebuffer *fb;
11127 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11128 crtc->base.base.id, crtc->base.name, context);
11130 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11131 transcoder_name(pipe_config->cpu_transcoder),
11132 pipe_config->pipe_bpp, pipe_config->dither);
11134 if (pipe_config->has_pch_encoder)
11135 intel_dump_m_n_config(pipe_config, "fdi",
11136 pipe_config->fdi_lanes,
11137 &pipe_config->fdi_m_n);
11139 if (intel_crtc_has_dp_encoder(pipe_config)) {
11140 intel_dump_m_n_config(pipe_config, "dp m_n",
11141 pipe_config->lane_count, &pipe_config->dp_m_n);
11142 if (pipe_config->has_drrs)
11143 intel_dump_m_n_config(pipe_config, "dp m2_n2",
11144 pipe_config->lane_count,
11145 &pipe_config->dp_m2_n2);
11148 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11149 pipe_config->has_audio, pipe_config->has_infoframe);
11151 DRM_DEBUG_KMS("requested mode:\n");
11152 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11153 DRM_DEBUG_KMS("adjusted mode:\n");
11154 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11155 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11156 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11157 pipe_config->port_clock,
11158 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11159 pipe_config->pixel_rate);
11161 if (INTEL_GEN(dev_priv) >= 9)
11162 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11164 pipe_config->scaler_state.scaler_users,
11165 pipe_config->scaler_state.scaler_id);
11167 if (HAS_GMCH_DISPLAY(dev_priv))
11168 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11169 pipe_config->gmch_pfit.control,
11170 pipe_config->gmch_pfit.pgm_ratios,
11171 pipe_config->gmch_pfit.lvds_border_bits);
11173 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11174 pipe_config->pch_pfit.pos,
11175 pipe_config->pch_pfit.size,
11176 enableddisabled(pipe_config->pch_pfit.enabled));
11178 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11179 pipe_config->ips_enabled, pipe_config->double_wide);
11181 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11183 DRM_DEBUG_KMS("planes on this crtc\n");
11184 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11185 struct drm_format_name_buf format_name;
11186 intel_plane = to_intel_plane(plane);
11187 if (intel_plane->pipe != crtc->pipe)
11190 state = to_intel_plane_state(plane->state);
11191 fb = state->base.fb;
11193 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11194 plane->base.id, plane->name, state->scaler_id);
11198 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11199 plane->base.id, plane->name,
11200 fb->base.id, fb->width, fb->height,
11201 drm_get_format_name(fb->format->format, &format_name));
11202 if (INTEL_GEN(dev_priv) >= 9)
11203 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11205 state->base.src.x1 >> 16,
11206 state->base.src.y1 >> 16,
11207 drm_rect_width(&state->base.src) >> 16,
11208 drm_rect_height(&state->base.src) >> 16,
11209 state->base.dst.x1, state->base.dst.y1,
11210 drm_rect_width(&state->base.dst),
11211 drm_rect_height(&state->base.dst));
11215 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11217 struct drm_device *dev = state->dev;
11218 struct drm_connector *connector;
11219 unsigned int used_ports = 0;
11220 unsigned int used_mst_ports = 0;
11223 * Walk the connector list instead of the encoder
11224 * list to detect the problem on ddi platforms
11225 * where there's just one encoder per digital port.
11227 drm_for_each_connector(connector, dev) {
11228 struct drm_connector_state *connector_state;
11229 struct intel_encoder *encoder;
11231 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11232 if (!connector_state)
11233 connector_state = connector->state;
11235 if (!connector_state->best_encoder)
11238 encoder = to_intel_encoder(connector_state->best_encoder);
11240 WARN_ON(!connector_state->crtc);
11242 switch (encoder->type) {
11243 unsigned int port_mask;
11244 case INTEL_OUTPUT_UNKNOWN:
11245 if (WARN_ON(!HAS_DDI(to_i915(dev))))
11247 case INTEL_OUTPUT_DP:
11248 case INTEL_OUTPUT_HDMI:
11249 case INTEL_OUTPUT_EDP:
11250 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11252 /* the same port mustn't appear more than once */
11253 if (used_ports & port_mask)
11256 used_ports |= port_mask;
11258 case INTEL_OUTPUT_DP_MST:
11260 1 << enc_to_mst(&encoder->base)->primary->port;
11267 /* can't mix MST and SST/HDMI on the same port */
11268 if (used_ports & used_mst_ports)
11275 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11277 struct drm_i915_private *dev_priv =
11278 to_i915(crtc_state->base.crtc->dev);
11279 struct intel_crtc_scaler_state scaler_state;
11280 struct intel_dpll_hw_state dpll_hw_state;
11281 struct intel_shared_dpll *shared_dpll;
11282 struct intel_crtc_wm_state wm_state;
11285 /* FIXME: before the switch to atomic started, a new pipe_config was
11286 * kzalloc'd. Code that depends on any field being zero should be
11287 * fixed, so that the crtc_state can be safely duplicated. For now,
11288 * only fields that are know to not cause problems are preserved. */
11290 scaler_state = crtc_state->scaler_state;
11291 shared_dpll = crtc_state->shared_dpll;
11292 dpll_hw_state = crtc_state->dpll_hw_state;
11293 force_thru = crtc_state->pch_pfit.force_thru;
11294 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11295 wm_state = crtc_state->wm;
11297 /* Keep base drm_crtc_state intact, only clear our extended struct */
11298 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11299 memset(&crtc_state->base + 1, 0,
11300 sizeof(*crtc_state) - sizeof(crtc_state->base));
11302 crtc_state->scaler_state = scaler_state;
11303 crtc_state->shared_dpll = shared_dpll;
11304 crtc_state->dpll_hw_state = dpll_hw_state;
11305 crtc_state->pch_pfit.force_thru = force_thru;
11306 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11307 crtc_state->wm = wm_state;
11311 intel_modeset_pipe_config(struct drm_crtc *crtc,
11312 struct intel_crtc_state *pipe_config)
11314 struct drm_atomic_state *state = pipe_config->base.state;
11315 struct intel_encoder *encoder;
11316 struct drm_connector *connector;
11317 struct drm_connector_state *connector_state;
11318 int base_bpp, ret = -EINVAL;
11322 clear_intel_crtc_state(pipe_config);
11324 pipe_config->cpu_transcoder =
11325 (enum transcoder) to_intel_crtc(crtc)->pipe;
11328 * Sanitize sync polarity flags based on requested ones. If neither
11329 * positive or negative polarity is requested, treat this as meaning
11330 * negative polarity.
11332 if (!(pipe_config->base.adjusted_mode.flags &
11333 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11334 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11336 if (!(pipe_config->base.adjusted_mode.flags &
11337 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11338 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11340 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11346 * Determine the real pipe dimensions. Note that stereo modes can
11347 * increase the actual pipe size due to the frame doubling and
11348 * insertion of additional space for blanks between the frame. This
11349 * is stored in the crtc timings. We use the requested mode to do this
11350 * computation to clearly distinguish it from the adjusted mode, which
11351 * can be changed by the connectors in the below retry loop.
11353 drm_mode_get_hv_timing(&pipe_config->base.mode,
11354 &pipe_config->pipe_src_w,
11355 &pipe_config->pipe_src_h);
11357 for_each_new_connector_in_state(state, connector, connector_state, i) {
11358 if (connector_state->crtc != crtc)
11361 encoder = to_intel_encoder(connector_state->best_encoder);
11363 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11364 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11369 * Determine output_types before calling the .compute_config()
11370 * hooks so that the hooks can use this information safely.
11372 pipe_config->output_types |= 1 << encoder->type;
11376 /* Ensure the port clock defaults are reset when retrying. */
11377 pipe_config->port_clock = 0;
11378 pipe_config->pixel_multiplier = 1;
11380 /* Fill in default crtc timings, allow encoders to overwrite them. */
11381 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11382 CRTC_STEREO_DOUBLE);
11384 /* Pass our mode to the connectors and the CRTC to give them a chance to
11385 * adjust it according to limitations or connector properties, and also
11386 * a chance to reject the mode entirely.
11388 for_each_new_connector_in_state(state, connector, connector_state, i) {
11389 if (connector_state->crtc != crtc)
11392 encoder = to_intel_encoder(connector_state->best_encoder);
11394 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11395 DRM_DEBUG_KMS("Encoder config failure\n");
11400 /* Set default port clock if not overwritten by the encoder. Needs to be
11401 * done afterwards in case the encoder adjusts the mode. */
11402 if (!pipe_config->port_clock)
11403 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11404 * pipe_config->pixel_multiplier;
11406 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11408 DRM_DEBUG_KMS("CRTC fixup failed\n");
11412 if (ret == RETRY) {
11413 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11418 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11420 goto encoder_retry;
11423 /* Dithering seems to not pass-through bits correctly when it should, so
11424 * only enable it on 6bpc panels and when its not a compliance
11425 * test requesting 6bpc video pattern.
11427 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11428 !pipe_config->dither_force_disable;
11429 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11430 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11437 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11439 struct drm_crtc *crtc;
11440 struct drm_crtc_state *new_crtc_state;
11443 /* Double check state. */
11444 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11445 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11447 /* Update hwmode for vblank functions */
11448 if (new_crtc_state->active)
11449 crtc->hwmode = new_crtc_state->adjusted_mode;
11451 crtc->hwmode.crtc_clock = 0;
11454 * Update legacy state to satisfy fbc code. This can
11455 * be removed when fbc uses the atomic state.
11457 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11458 struct drm_plane_state *plane_state = crtc->primary->state;
11460 crtc->primary->fb = plane_state->fb;
11461 crtc->x = plane_state->src_x >> 16;
11462 crtc->y = plane_state->src_y >> 16;
11467 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11471 if (clock1 == clock2)
11474 if (!clock1 || !clock2)
11477 diff = abs(clock1 - clock2);
11479 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11486 intel_compare_m_n(unsigned int m, unsigned int n,
11487 unsigned int m2, unsigned int n2,
11490 if (m == m2 && n == n2)
11493 if (exact || !m || !n || !m2 || !n2)
11496 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11503 } else if (n < n2) {
11513 return intel_fuzzy_clock_check(m, m2);
11517 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11518 struct intel_link_m_n *m2_n2,
11521 if (m_n->tu == m2_n2->tu &&
11522 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11523 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11524 intel_compare_m_n(m_n->link_m, m_n->link_n,
11525 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11535 static void __printf(3, 4)
11536 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11539 unsigned int category;
11540 struct va_format vaf;
11544 level = KERN_DEBUG;
11545 category = DRM_UT_KMS;
11548 category = DRM_UT_NONE;
11551 va_start(args, format);
11555 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11561 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11562 struct intel_crtc_state *current_config,
11563 struct intel_crtc_state *pipe_config,
11568 #define PIPE_CONF_CHECK_X(name) \
11569 if (current_config->name != pipe_config->name) { \
11570 pipe_config_err(adjust, __stringify(name), \
11571 "(expected 0x%08x, found 0x%08x)\n", \
11572 current_config->name, \
11573 pipe_config->name); \
11577 #define PIPE_CONF_CHECK_I(name) \
11578 if (current_config->name != pipe_config->name) { \
11579 pipe_config_err(adjust, __stringify(name), \
11580 "(expected %i, found %i)\n", \
11581 current_config->name, \
11582 pipe_config->name); \
11586 #define PIPE_CONF_CHECK_P(name) \
11587 if (current_config->name != pipe_config->name) { \
11588 pipe_config_err(adjust, __stringify(name), \
11589 "(expected %p, found %p)\n", \
11590 current_config->name, \
11591 pipe_config->name); \
11595 #define PIPE_CONF_CHECK_M_N(name) \
11596 if (!intel_compare_link_m_n(¤t_config->name, \
11597 &pipe_config->name,\
11599 pipe_config_err(adjust, __stringify(name), \
11600 "(expected tu %i gmch %i/%i link %i/%i, " \
11601 "found tu %i, gmch %i/%i link %i/%i)\n", \
11602 current_config->name.tu, \
11603 current_config->name.gmch_m, \
11604 current_config->name.gmch_n, \
11605 current_config->name.link_m, \
11606 current_config->name.link_n, \
11607 pipe_config->name.tu, \
11608 pipe_config->name.gmch_m, \
11609 pipe_config->name.gmch_n, \
11610 pipe_config->name.link_m, \
11611 pipe_config->name.link_n); \
11615 /* This is required for BDW+ where there is only one set of registers for
11616 * switching between high and low RR.
11617 * This macro can be used whenever a comparison has to be made between one
11618 * hw state and multiple sw state variables.
11620 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11621 if (!intel_compare_link_m_n(¤t_config->name, \
11622 &pipe_config->name, adjust) && \
11623 !intel_compare_link_m_n(¤t_config->alt_name, \
11624 &pipe_config->name, adjust)) { \
11625 pipe_config_err(adjust, __stringify(name), \
11626 "(expected tu %i gmch %i/%i link %i/%i, " \
11627 "or tu %i gmch %i/%i link %i/%i, " \
11628 "found tu %i, gmch %i/%i link %i/%i)\n", \
11629 current_config->name.tu, \
11630 current_config->name.gmch_m, \
11631 current_config->name.gmch_n, \
11632 current_config->name.link_m, \
11633 current_config->name.link_n, \
11634 current_config->alt_name.tu, \
11635 current_config->alt_name.gmch_m, \
11636 current_config->alt_name.gmch_n, \
11637 current_config->alt_name.link_m, \
11638 current_config->alt_name.link_n, \
11639 pipe_config->name.tu, \
11640 pipe_config->name.gmch_m, \
11641 pipe_config->name.gmch_n, \
11642 pipe_config->name.link_m, \
11643 pipe_config->name.link_n); \
11647 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11648 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11649 pipe_config_err(adjust, __stringify(name), \
11650 "(%x) (expected %i, found %i)\n", \
11652 current_config->name & (mask), \
11653 pipe_config->name & (mask)); \
11657 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11658 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11659 pipe_config_err(adjust, __stringify(name), \
11660 "(expected %i, found %i)\n", \
11661 current_config->name, \
11662 pipe_config->name); \
11666 #define PIPE_CONF_QUIRK(quirk) \
11667 ((current_config->quirks | pipe_config->quirks) & (quirk))
11669 PIPE_CONF_CHECK_I(cpu_transcoder);
11671 PIPE_CONF_CHECK_I(has_pch_encoder);
11672 PIPE_CONF_CHECK_I(fdi_lanes);
11673 PIPE_CONF_CHECK_M_N(fdi_m_n);
11675 PIPE_CONF_CHECK_I(lane_count);
11676 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11678 if (INTEL_GEN(dev_priv) < 8) {
11679 PIPE_CONF_CHECK_M_N(dp_m_n);
11681 if (current_config->has_drrs)
11682 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11684 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11686 PIPE_CONF_CHECK_X(output_types);
11688 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11689 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11690 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11691 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11692 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11693 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11695 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11696 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11697 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11698 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11699 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11700 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11702 PIPE_CONF_CHECK_I(pixel_multiplier);
11703 PIPE_CONF_CHECK_I(has_hdmi_sink);
11704 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11705 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11706 PIPE_CONF_CHECK_I(limited_color_range);
11708 PIPE_CONF_CHECK_I(hdmi_scrambling);
11709 PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11710 PIPE_CONF_CHECK_I(has_infoframe);
11712 PIPE_CONF_CHECK_I(has_audio);
11714 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11715 DRM_MODE_FLAG_INTERLACE);
11717 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11718 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11719 DRM_MODE_FLAG_PHSYNC);
11720 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11721 DRM_MODE_FLAG_NHSYNC);
11722 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11723 DRM_MODE_FLAG_PVSYNC);
11724 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11725 DRM_MODE_FLAG_NVSYNC);
11728 PIPE_CONF_CHECK_X(gmch_pfit.control);
11729 /* pfit ratios are autocomputed by the hw on gen4+ */
11730 if (INTEL_GEN(dev_priv) < 4)
11731 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11732 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11735 PIPE_CONF_CHECK_I(pipe_src_w);
11736 PIPE_CONF_CHECK_I(pipe_src_h);
11738 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11739 if (current_config->pch_pfit.enabled) {
11740 PIPE_CONF_CHECK_X(pch_pfit.pos);
11741 PIPE_CONF_CHECK_X(pch_pfit.size);
11744 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11745 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11748 /* BDW+ don't expose a synchronous way to read the state */
11749 if (IS_HASWELL(dev_priv))
11750 PIPE_CONF_CHECK_I(ips_enabled);
11752 PIPE_CONF_CHECK_I(double_wide);
11754 PIPE_CONF_CHECK_P(shared_dpll);
11755 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11756 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11757 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11758 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11759 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11760 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11761 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11762 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11763 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11765 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11766 PIPE_CONF_CHECK_X(dsi_pll.div);
11768 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11769 PIPE_CONF_CHECK_I(pipe_bpp);
11771 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11772 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11774 #undef PIPE_CONF_CHECK_X
11775 #undef PIPE_CONF_CHECK_I
11776 #undef PIPE_CONF_CHECK_P
11777 #undef PIPE_CONF_CHECK_FLAGS
11778 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11779 #undef PIPE_CONF_QUIRK
11784 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11785 const struct intel_crtc_state *pipe_config)
11787 if (pipe_config->has_pch_encoder) {
11788 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11789 &pipe_config->fdi_m_n);
11790 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11793 * FDI already provided one idea for the dotclock.
11794 * Yell if the encoder disagrees.
11796 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11797 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11798 fdi_dotclock, dotclock);
11802 static void verify_wm_state(struct drm_crtc *crtc,
11803 struct drm_crtc_state *new_state)
11805 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11806 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11807 struct skl_pipe_wm hw_wm, *sw_wm;
11808 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11809 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11811 const enum pipe pipe = intel_crtc->pipe;
11812 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11814 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11817 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11818 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11820 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11821 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11824 for_each_universal_plane(dev_priv, pipe, plane) {
11825 hw_plane_wm = &hw_wm.planes[plane];
11826 sw_plane_wm = &sw_wm->planes[plane];
11829 for (level = 0; level <= max_level; level++) {
11830 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11831 &sw_plane_wm->wm[level]))
11834 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11835 pipe_name(pipe), plane + 1, level,
11836 sw_plane_wm->wm[level].plane_en,
11837 sw_plane_wm->wm[level].plane_res_b,
11838 sw_plane_wm->wm[level].plane_res_l,
11839 hw_plane_wm->wm[level].plane_en,
11840 hw_plane_wm->wm[level].plane_res_b,
11841 hw_plane_wm->wm[level].plane_res_l);
11844 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11845 &sw_plane_wm->trans_wm)) {
11846 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11847 pipe_name(pipe), plane + 1,
11848 sw_plane_wm->trans_wm.plane_en,
11849 sw_plane_wm->trans_wm.plane_res_b,
11850 sw_plane_wm->trans_wm.plane_res_l,
11851 hw_plane_wm->trans_wm.plane_en,
11852 hw_plane_wm->trans_wm.plane_res_b,
11853 hw_plane_wm->trans_wm.plane_res_l);
11857 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11858 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11860 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11861 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11862 pipe_name(pipe), plane + 1,
11863 sw_ddb_entry->start, sw_ddb_entry->end,
11864 hw_ddb_entry->start, hw_ddb_entry->end);
11870 * If the cursor plane isn't active, we may not have updated it's ddb
11871 * allocation. In that case since the ddb allocation will be updated
11872 * once the plane becomes visible, we can skip this check
11874 if (intel_crtc->cursor_addr) {
11875 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11876 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11879 for (level = 0; level <= max_level; level++) {
11880 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11881 &sw_plane_wm->wm[level]))
11884 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11885 pipe_name(pipe), level,
11886 sw_plane_wm->wm[level].plane_en,
11887 sw_plane_wm->wm[level].plane_res_b,
11888 sw_plane_wm->wm[level].plane_res_l,
11889 hw_plane_wm->wm[level].plane_en,
11890 hw_plane_wm->wm[level].plane_res_b,
11891 hw_plane_wm->wm[level].plane_res_l);
11894 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11895 &sw_plane_wm->trans_wm)) {
11896 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11898 sw_plane_wm->trans_wm.plane_en,
11899 sw_plane_wm->trans_wm.plane_res_b,
11900 sw_plane_wm->trans_wm.plane_res_l,
11901 hw_plane_wm->trans_wm.plane_en,
11902 hw_plane_wm->trans_wm.plane_res_b,
11903 hw_plane_wm->trans_wm.plane_res_l);
11907 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11908 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11910 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11911 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11913 sw_ddb_entry->start, sw_ddb_entry->end,
11914 hw_ddb_entry->start, hw_ddb_entry->end);
11920 verify_connector_state(struct drm_device *dev,
11921 struct drm_atomic_state *state,
11922 struct drm_crtc *crtc)
11924 struct drm_connector *connector;
11925 struct drm_connector_state *new_conn_state;
11928 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11929 struct drm_encoder *encoder = connector->encoder;
11931 if (new_conn_state->crtc != crtc)
11934 intel_connector_verify_state(to_intel_connector(connector));
11936 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11937 "connector's atomic encoder doesn't match legacy encoder\n");
11942 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11944 struct intel_encoder *encoder;
11945 struct drm_connector *connector;
11946 struct drm_connector_state *old_conn_state, *new_conn_state;
11949 for_each_intel_encoder(dev, encoder) {
11950 bool enabled = false, found = false;
11953 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11954 encoder->base.base.id,
11955 encoder->base.name);
11957 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11958 new_conn_state, i) {
11959 if (old_conn_state->best_encoder == &encoder->base)
11962 if (new_conn_state->best_encoder != &encoder->base)
11964 found = enabled = true;
11966 I915_STATE_WARN(new_conn_state->crtc !=
11967 encoder->base.crtc,
11968 "connector's crtc doesn't match encoder crtc\n");
11974 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11975 "encoder's enabled state mismatch "
11976 "(expected %i, found %i)\n",
11977 !!encoder->base.crtc, enabled);
11979 if (!encoder->base.crtc) {
11982 active = encoder->get_hw_state(encoder, &pipe);
11983 I915_STATE_WARN(active,
11984 "encoder detached but still enabled on pipe %c.\n",
11991 verify_crtc_state(struct drm_crtc *crtc,
11992 struct drm_crtc_state *old_crtc_state,
11993 struct drm_crtc_state *new_crtc_state)
11995 struct drm_device *dev = crtc->dev;
11996 struct drm_i915_private *dev_priv = to_i915(dev);
11997 struct intel_encoder *encoder;
11998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11999 struct intel_crtc_state *pipe_config, *sw_config;
12000 struct drm_atomic_state *old_state;
12003 old_state = old_crtc_state->state;
12004 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12005 pipe_config = to_intel_crtc_state(old_crtc_state);
12006 memset(pipe_config, 0, sizeof(*pipe_config));
12007 pipe_config->base.crtc = crtc;
12008 pipe_config->base.state = old_state;
12010 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12012 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12014 /* hw state is inconsistent with the pipe quirk */
12015 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12016 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12017 active = new_crtc_state->active;
12019 I915_STATE_WARN(new_crtc_state->active != active,
12020 "crtc active state doesn't match with hw state "
12021 "(expected %i, found %i)\n", new_crtc_state->active, active);
12023 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12024 "transitional active state does not match atomic hw state "
12025 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12027 for_each_encoder_on_crtc(dev, crtc, encoder) {
12030 active = encoder->get_hw_state(encoder, &pipe);
12031 I915_STATE_WARN(active != new_crtc_state->active,
12032 "[ENCODER:%i] active %i with crtc active %i\n",
12033 encoder->base.base.id, active, new_crtc_state->active);
12035 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12036 "Encoder connected to wrong pipe %c\n",
12040 pipe_config->output_types |= 1 << encoder->type;
12041 encoder->get_config(encoder, pipe_config);
12045 intel_crtc_compute_pixel_rate(pipe_config);
12047 if (!new_crtc_state->active)
12050 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12052 sw_config = to_intel_crtc_state(crtc->state);
12053 if (!intel_pipe_config_compare(dev_priv, sw_config,
12054 pipe_config, false)) {
12055 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12056 intel_dump_pipe_config(intel_crtc, pipe_config,
12058 intel_dump_pipe_config(intel_crtc, sw_config,
12064 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12065 struct intel_shared_dpll *pll,
12066 struct drm_crtc *crtc,
12067 struct drm_crtc_state *new_state)
12069 struct intel_dpll_hw_state dpll_hw_state;
12070 unsigned crtc_mask;
12073 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12075 DRM_DEBUG_KMS("%s\n", pll->name);
12077 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12079 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12080 I915_STATE_WARN(!pll->on && pll->active_mask,
12081 "pll in active use but not on in sw tracking\n");
12082 I915_STATE_WARN(pll->on && !pll->active_mask,
12083 "pll is on but not used by any active crtc\n");
12084 I915_STATE_WARN(pll->on != active,
12085 "pll on state mismatch (expected %i, found %i)\n",
12090 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12091 "more active pll users than references: %x vs %x\n",
12092 pll->active_mask, pll->state.crtc_mask);
12097 crtc_mask = 1 << drm_crtc_index(crtc);
12099 if (new_state->active)
12100 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12101 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12102 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12104 I915_STATE_WARN(pll->active_mask & crtc_mask,
12105 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12106 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12108 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12109 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12110 crtc_mask, pll->state.crtc_mask);
12112 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12114 sizeof(dpll_hw_state)),
12115 "pll hw state mismatch\n");
12119 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12120 struct drm_crtc_state *old_crtc_state,
12121 struct drm_crtc_state *new_crtc_state)
12123 struct drm_i915_private *dev_priv = to_i915(dev);
12124 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12125 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12127 if (new_state->shared_dpll)
12128 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12130 if (old_state->shared_dpll &&
12131 old_state->shared_dpll != new_state->shared_dpll) {
12132 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12133 struct intel_shared_dpll *pll = old_state->shared_dpll;
12135 I915_STATE_WARN(pll->active_mask & crtc_mask,
12136 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12137 pipe_name(drm_crtc_index(crtc)));
12138 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12139 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12140 pipe_name(drm_crtc_index(crtc)));
12145 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12146 struct drm_atomic_state *state,
12147 struct drm_crtc_state *old_state,
12148 struct drm_crtc_state *new_state)
12150 if (!needs_modeset(new_state) &&
12151 !to_intel_crtc_state(new_state)->update_pipe)
12154 verify_wm_state(crtc, new_state);
12155 verify_connector_state(crtc->dev, state, crtc);
12156 verify_crtc_state(crtc, old_state, new_state);
12157 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12161 verify_disabled_dpll_state(struct drm_device *dev)
12163 struct drm_i915_private *dev_priv = to_i915(dev);
12166 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12167 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12171 intel_modeset_verify_disabled(struct drm_device *dev,
12172 struct drm_atomic_state *state)
12174 verify_encoder_state(dev, state);
12175 verify_connector_state(dev, state, NULL);
12176 verify_disabled_dpll_state(dev);
12179 static void update_scanline_offset(struct intel_crtc *crtc)
12181 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12184 * The scanline counter increments at the leading edge of hsync.
12186 * On most platforms it starts counting from vtotal-1 on the
12187 * first active line. That means the scanline counter value is
12188 * always one less than what we would expect. Ie. just after
12189 * start of vblank, which also occurs at start of hsync (on the
12190 * last active line), the scanline counter will read vblank_start-1.
12192 * On gen2 the scanline counter starts counting from 1 instead
12193 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12194 * to keep the value positive), instead of adding one.
12196 * On HSW+ the behaviour of the scanline counter depends on the output
12197 * type. For DP ports it behaves like most other platforms, but on HDMI
12198 * there's an extra 1 line difference. So we need to add two instead of
12199 * one to the value.
12201 if (IS_GEN2(dev_priv)) {
12202 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12205 vtotal = adjusted_mode->crtc_vtotal;
12206 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12209 crtc->scanline_offset = vtotal - 1;
12210 } else if (HAS_DDI(dev_priv) &&
12211 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12212 crtc->scanline_offset = 2;
12214 crtc->scanline_offset = 1;
12217 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12219 struct drm_device *dev = state->dev;
12220 struct drm_i915_private *dev_priv = to_i915(dev);
12221 struct drm_crtc *crtc;
12222 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12225 if (!dev_priv->display.crtc_compute_clock)
12228 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12230 struct intel_shared_dpll *old_dpll =
12231 to_intel_crtc_state(old_crtc_state)->shared_dpll;
12233 if (!needs_modeset(new_crtc_state))
12236 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12241 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12246 * This implements the workaround described in the "notes" section of the mode
12247 * set sequence documentation. When going from no pipes or single pipe to
12248 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12249 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12251 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12253 struct drm_crtc_state *crtc_state;
12254 struct intel_crtc *intel_crtc;
12255 struct drm_crtc *crtc;
12256 struct intel_crtc_state *first_crtc_state = NULL;
12257 struct intel_crtc_state *other_crtc_state = NULL;
12258 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12261 /* look at all crtc's that are going to be enabled in during modeset */
12262 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12263 intel_crtc = to_intel_crtc(crtc);
12265 if (!crtc_state->active || !needs_modeset(crtc_state))
12268 if (first_crtc_state) {
12269 other_crtc_state = to_intel_crtc_state(crtc_state);
12272 first_crtc_state = to_intel_crtc_state(crtc_state);
12273 first_pipe = intel_crtc->pipe;
12277 /* No workaround needed? */
12278 if (!first_crtc_state)
12281 /* w/a possibly needed, check how many crtc's are already enabled. */
12282 for_each_intel_crtc(state->dev, intel_crtc) {
12283 struct intel_crtc_state *pipe_config;
12285 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12286 if (IS_ERR(pipe_config))
12287 return PTR_ERR(pipe_config);
12289 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12291 if (!pipe_config->base.active ||
12292 needs_modeset(&pipe_config->base))
12295 /* 2 or more enabled crtcs means no need for w/a */
12296 if (enabled_pipe != INVALID_PIPE)
12299 enabled_pipe = intel_crtc->pipe;
12302 if (enabled_pipe != INVALID_PIPE)
12303 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12304 else if (other_crtc_state)
12305 other_crtc_state->hsw_workaround_pipe = first_pipe;
12310 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12312 struct drm_crtc *crtc;
12314 /* Add all pipes to the state */
12315 for_each_crtc(state->dev, crtc) {
12316 struct drm_crtc_state *crtc_state;
12318 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12319 if (IS_ERR(crtc_state))
12320 return PTR_ERR(crtc_state);
12326 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12328 struct drm_crtc *crtc;
12331 * Add all pipes to the state, and force
12332 * a modeset on all the active ones.
12334 for_each_crtc(state->dev, crtc) {
12335 struct drm_crtc_state *crtc_state;
12338 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12339 if (IS_ERR(crtc_state))
12340 return PTR_ERR(crtc_state);
12342 if (!crtc_state->active || needs_modeset(crtc_state))
12345 crtc_state->mode_changed = true;
12347 ret = drm_atomic_add_affected_connectors(state, crtc);
12351 ret = drm_atomic_add_affected_planes(state, crtc);
12359 static int intel_modeset_checks(struct drm_atomic_state *state)
12361 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12362 struct drm_i915_private *dev_priv = to_i915(state->dev);
12363 struct drm_crtc *crtc;
12364 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12367 if (!check_digital_port_conflicts(state)) {
12368 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12372 intel_state->modeset = true;
12373 intel_state->active_crtcs = dev_priv->active_crtcs;
12374 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12375 intel_state->cdclk.actual = dev_priv->cdclk.actual;
12377 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12378 if (new_crtc_state->active)
12379 intel_state->active_crtcs |= 1 << i;
12381 intel_state->active_crtcs &= ~(1 << i);
12383 if (old_crtc_state->active != new_crtc_state->active)
12384 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12388 * See if the config requires any additional preparation, e.g.
12389 * to adjust global state with pipes off. We need to do this
12390 * here so we can get the modeset_pipe updated config for the new
12391 * mode set on this crtc. For other crtcs we need to use the
12392 * adjusted_mode bits in the crtc directly.
12394 if (dev_priv->display.modeset_calc_cdclk) {
12395 ret = dev_priv->display.modeset_calc_cdclk(state);
12400 * Writes to dev_priv->cdclk.logical must protected by
12401 * holding all the crtc locks, even if we don't end up
12402 * touching the hardware
12404 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12405 &intel_state->cdclk.logical)) {
12406 ret = intel_lock_all_pipes(state);
12411 /* All pipes must be switched off while we change the cdclk. */
12412 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12413 &intel_state->cdclk.actual)) {
12414 ret = intel_modeset_all_pipes(state);
12419 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12420 intel_state->cdclk.logical.cdclk,
12421 intel_state->cdclk.actual.cdclk);
12423 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12426 intel_modeset_clear_plls(state);
12428 if (IS_HASWELL(dev_priv))
12429 return haswell_mode_set_planes_workaround(state);
12435 * Handle calculation of various watermark data at the end of the atomic check
12436 * phase. The code here should be run after the per-crtc and per-plane 'check'
12437 * handlers to ensure that all derived state has been updated.
12439 static int calc_watermark_data(struct drm_atomic_state *state)
12441 struct drm_device *dev = state->dev;
12442 struct drm_i915_private *dev_priv = to_i915(dev);
12444 /* Is there platform-specific watermark information to calculate? */
12445 if (dev_priv->display.compute_global_watermarks)
12446 return dev_priv->display.compute_global_watermarks(state);
12452 * intel_atomic_check - validate state object
12454 * @state: state to validate
12456 static int intel_atomic_check(struct drm_device *dev,
12457 struct drm_atomic_state *state)
12459 struct drm_i915_private *dev_priv = to_i915(dev);
12460 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12461 struct drm_crtc *crtc;
12462 struct drm_crtc_state *old_crtc_state, *crtc_state;
12464 bool any_ms = false;
12466 ret = drm_atomic_helper_check_modeset(dev, state);
12470 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12471 struct intel_crtc_state *pipe_config =
12472 to_intel_crtc_state(crtc_state);
12474 /* Catch I915_MODE_FLAG_INHERITED */
12475 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12476 crtc_state->mode_changed = true;
12478 if (!needs_modeset(crtc_state))
12481 if (!crtc_state->enable) {
12486 /* FIXME: For only active_changed we shouldn't need to do any
12487 * state recomputation at all. */
12489 ret = drm_atomic_add_affected_connectors(state, crtc);
12493 ret = intel_modeset_pipe_config(crtc, pipe_config);
12495 intel_dump_pipe_config(to_intel_crtc(crtc),
12496 pipe_config, "[failed]");
12500 if (i915.fastboot &&
12501 intel_pipe_config_compare(dev_priv,
12502 to_intel_crtc_state(old_crtc_state),
12503 pipe_config, true)) {
12504 crtc_state->mode_changed = false;
12505 pipe_config->update_pipe = true;
12508 if (needs_modeset(crtc_state))
12511 ret = drm_atomic_add_affected_planes(state, crtc);
12515 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12516 needs_modeset(crtc_state) ?
12517 "[modeset]" : "[fastset]");
12521 ret = intel_modeset_checks(state);
12526 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12529 ret = drm_atomic_helper_check_planes(dev, state);
12533 intel_fbc_choose_crtc(dev_priv, state);
12534 return calc_watermark_data(state);
12537 static int intel_atomic_prepare_commit(struct drm_device *dev,
12538 struct drm_atomic_state *state)
12540 struct drm_i915_private *dev_priv = to_i915(dev);
12541 struct drm_crtc_state *crtc_state;
12542 struct drm_crtc *crtc;
12545 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12546 if (state->legacy_cursor_update)
12549 ret = intel_crtc_wait_for_pending_flips(crtc);
12553 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12554 flush_workqueue(dev_priv->wq);
12557 ret = mutex_lock_interruptible(&dev->struct_mutex);
12561 ret = drm_atomic_helper_prepare_planes(dev, state);
12562 mutex_unlock(&dev->struct_mutex);
12567 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12569 struct drm_device *dev = crtc->base.dev;
12571 if (!dev->max_vblank_count)
12572 return drm_accurate_vblank_count(&crtc->base);
12574 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12577 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12578 struct drm_i915_private *dev_priv,
12579 unsigned crtc_mask)
12581 unsigned last_vblank_count[I915_MAX_PIPES];
12588 for_each_pipe(dev_priv, pipe) {
12589 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12592 if (!((1 << pipe) & crtc_mask))
12595 ret = drm_crtc_vblank_get(&crtc->base);
12596 if (WARN_ON(ret != 0)) {
12597 crtc_mask &= ~(1 << pipe);
12601 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12604 for_each_pipe(dev_priv, pipe) {
12605 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12609 if (!((1 << pipe) & crtc_mask))
12612 lret = wait_event_timeout(dev->vblank[pipe].queue,
12613 last_vblank_count[pipe] !=
12614 drm_crtc_vblank_count(&crtc->base),
12615 msecs_to_jiffies(50));
12617 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12619 drm_crtc_vblank_put(&crtc->base);
12623 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12625 /* fb updated, need to unpin old fb */
12626 if (crtc_state->fb_changed)
12629 /* wm changes, need vblank before final wm's */
12630 if (crtc_state->update_wm_post)
12633 if (crtc_state->wm.need_postvbl_update)
12639 static void intel_update_crtc(struct drm_crtc *crtc,
12640 struct drm_atomic_state *state,
12641 struct drm_crtc_state *old_crtc_state,
12642 struct drm_crtc_state *new_crtc_state,
12643 unsigned int *crtc_vblank_mask)
12645 struct drm_device *dev = crtc->dev;
12646 struct drm_i915_private *dev_priv = to_i915(dev);
12647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12648 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12649 bool modeset = needs_modeset(new_crtc_state);
12652 update_scanline_offset(intel_crtc);
12653 dev_priv->display.crtc_enable(pipe_config, state);
12655 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12659 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12661 intel_crtc, pipe_config,
12662 to_intel_plane_state(crtc->primary->state));
12665 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12667 if (needs_vblank_wait(pipe_config))
12668 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12671 static void intel_update_crtcs(struct drm_atomic_state *state,
12672 unsigned int *crtc_vblank_mask)
12674 struct drm_crtc *crtc;
12675 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12678 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12679 if (!new_crtc_state->active)
12682 intel_update_crtc(crtc, state, old_crtc_state,
12683 new_crtc_state, crtc_vblank_mask);
12687 static void skl_update_crtcs(struct drm_atomic_state *state,
12688 unsigned int *crtc_vblank_mask)
12690 struct drm_i915_private *dev_priv = to_i915(state->dev);
12691 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12692 struct drm_crtc *crtc;
12693 struct intel_crtc *intel_crtc;
12694 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12695 struct intel_crtc_state *cstate;
12696 unsigned int updated = 0;
12701 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12703 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12704 /* ignore allocations for crtc's that have been turned off. */
12705 if (new_crtc_state->active)
12706 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12709 * Whenever the number of active pipes changes, we need to make sure we
12710 * update the pipes in the right order so that their ddb allocations
12711 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12712 * cause pipe underruns and other bad stuff.
12717 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12718 bool vbl_wait = false;
12719 unsigned int cmask = drm_crtc_mask(crtc);
12721 intel_crtc = to_intel_crtc(crtc);
12722 cstate = to_intel_crtc_state(crtc->state);
12723 pipe = intel_crtc->pipe;
12725 if (updated & cmask || !cstate->base.active)
12728 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12732 entries[i] = &cstate->wm.skl.ddb;
12735 * If this is an already active pipe, it's DDB changed,
12736 * and this isn't the last pipe that needs updating
12737 * then we need to wait for a vblank to pass for the
12738 * new ddb allocation to take effect.
12740 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12741 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12742 !new_crtc_state->active_changed &&
12743 intel_state->wm_results.dirty_pipes != updated)
12746 intel_update_crtc(crtc, state, old_crtc_state,
12747 new_crtc_state, crtc_vblank_mask);
12750 intel_wait_for_vblank(dev_priv, pipe);
12754 } while (progress);
12757 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12759 struct intel_atomic_state *state, *next;
12760 struct llist_node *freed;
12762 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12763 llist_for_each_entry_safe(state, next, freed, freed)
12764 drm_atomic_state_put(&state->base);
12767 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12769 struct drm_i915_private *dev_priv =
12770 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12772 intel_atomic_helper_free_state(dev_priv);
12775 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12777 struct drm_device *dev = state->dev;
12778 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12779 struct drm_i915_private *dev_priv = to_i915(dev);
12780 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12781 struct drm_crtc *crtc;
12782 struct intel_crtc_state *intel_cstate;
12783 bool hw_check = intel_state->modeset;
12784 u64 put_domains[I915_MAX_PIPES] = {};
12785 unsigned crtc_vblank_mask = 0;
12788 drm_atomic_helper_wait_for_dependencies(state);
12790 if (intel_state->modeset)
12791 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12793 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12796 if (needs_modeset(new_crtc_state) ||
12797 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12800 put_domains[to_intel_crtc(crtc)->pipe] =
12801 modeset_get_crtc_power_domains(crtc,
12802 to_intel_crtc_state(new_crtc_state));
12805 if (!needs_modeset(new_crtc_state))
12808 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12809 to_intel_crtc_state(new_crtc_state));
12811 if (old_crtc_state->active) {
12812 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12813 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12814 intel_crtc->active = false;
12815 intel_fbc_disable(intel_crtc);
12816 intel_disable_shared_dpll(intel_crtc);
12819 * Underruns don't always raise
12820 * interrupts, so check manually.
12822 intel_check_cpu_fifo_underruns(dev_priv);
12823 intel_check_pch_fifo_underruns(dev_priv);
12825 if (!crtc->state->active) {
12827 * Make sure we don't call initial_watermarks
12828 * for ILK-style watermark updates.
12830 * No clue what this is supposed to achieve.
12832 if (INTEL_GEN(dev_priv) >= 9)
12833 dev_priv->display.initial_watermarks(intel_state,
12834 to_intel_crtc_state(crtc->state));
12839 /* Only after disabling all output pipelines that will be changed can we
12840 * update the the output configuration. */
12841 intel_modeset_update_crtc_state(state);
12843 if (intel_state->modeset) {
12844 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12846 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12849 * SKL workaround: bspec recommends we disable the SAGV when we
12850 * have more then one pipe enabled
12852 if (!intel_can_enable_sagv(state))
12853 intel_disable_sagv(dev_priv);
12855 intel_modeset_verify_disabled(dev, state);
12858 /* Complete the events for pipes that have now been disabled */
12859 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12860 bool modeset = needs_modeset(new_crtc_state);
12862 /* Complete events for now disable pipes here. */
12863 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12864 spin_lock_irq(&dev->event_lock);
12865 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12866 spin_unlock_irq(&dev->event_lock);
12868 new_crtc_state->event = NULL;
12872 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12873 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12875 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12876 * already, but still need the state for the delayed optimization. To
12878 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12879 * - schedule that vblank worker _before_ calling hw_done
12880 * - at the start of commit_tail, cancel it _synchrously
12881 * - switch over to the vblank wait helper in the core after that since
12882 * we don't need out special handling any more.
12884 if (!state->legacy_cursor_update)
12885 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12888 * Now that the vblank has passed, we can go ahead and program the
12889 * optimal watermarks on platforms that need two-step watermark
12892 * TODO: Move this (and other cleanup) to an async worker eventually.
12894 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12895 intel_cstate = to_intel_crtc_state(new_crtc_state);
12897 if (dev_priv->display.optimize_watermarks)
12898 dev_priv->display.optimize_watermarks(intel_state,
12902 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12903 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12905 if (put_domains[i])
12906 modeset_put_power_domains(dev_priv, put_domains[i]);
12908 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12911 if (intel_state->modeset && intel_can_enable_sagv(state))
12912 intel_enable_sagv(dev_priv);
12914 drm_atomic_helper_commit_hw_done(state);
12916 if (intel_state->modeset)
12917 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12919 mutex_lock(&dev->struct_mutex);
12920 drm_atomic_helper_cleanup_planes(dev, state);
12921 mutex_unlock(&dev->struct_mutex);
12923 drm_atomic_helper_commit_cleanup_done(state);
12925 drm_atomic_state_put(state);
12927 /* As one of the primary mmio accessors, KMS has a high likelihood
12928 * of triggering bugs in unclaimed access. After we finish
12929 * modesetting, see if an error has been flagged, and if so
12930 * enable debugging for the next modeset - and hope we catch
12933 * XXX note that we assume display power is on at this point.
12934 * This might hold true now but we need to add pm helper to check
12935 * unclaimed only when the hardware is on, as atomic commits
12936 * can happen also when the device is completely off.
12938 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12940 intel_atomic_helper_free_state(dev_priv);
12943 static void intel_atomic_commit_work(struct work_struct *work)
12945 struct drm_atomic_state *state =
12946 container_of(work, struct drm_atomic_state, commit_work);
12948 intel_atomic_commit_tail(state);
12951 static int __i915_sw_fence_call
12952 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12953 enum i915_sw_fence_notify notify)
12955 struct intel_atomic_state *state =
12956 container_of(fence, struct intel_atomic_state, commit_ready);
12959 case FENCE_COMPLETE:
12960 if (state->base.commit_work.func)
12961 queue_work(system_unbound_wq, &state->base.commit_work);
12966 struct intel_atomic_helper *helper =
12967 &to_i915(state->base.dev)->atomic_helper;
12969 if (llist_add(&state->freed, &helper->free_list))
12970 schedule_work(&helper->free_work);
12975 return NOTIFY_DONE;
12978 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12980 struct drm_plane_state *old_plane_state, *new_plane_state;
12981 struct drm_plane *plane;
12984 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12985 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12986 intel_fb_obj(new_plane_state->fb),
12987 to_intel_plane(plane)->frontbuffer_bit);
12991 * intel_atomic_commit - commit validated state object
12993 * @state: the top-level driver state object
12994 * @nonblock: nonblocking commit
12996 * This function commits a top-level state object that has been validated
12997 * with drm_atomic_helper_check().
13000 * Zero for success or -errno.
13002 static int intel_atomic_commit(struct drm_device *dev,
13003 struct drm_atomic_state *state,
13006 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13007 struct drm_i915_private *dev_priv = to_i915(dev);
13010 ret = drm_atomic_helper_setup_commit(state, nonblock);
13014 drm_atomic_state_get(state);
13015 i915_sw_fence_init(&intel_state->commit_ready,
13016 intel_atomic_commit_ready);
13018 ret = intel_atomic_prepare_commit(dev, state);
13020 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13021 i915_sw_fence_commit(&intel_state->commit_ready);
13026 * The intel_legacy_cursor_update() fast path takes care
13027 * of avoiding the vblank waits for simple cursor
13028 * movement and flips. For cursor on/off and size changes,
13029 * we want to perform the vblank waits so that watermark
13030 * updates happen during the correct frames. Gen9+ have
13031 * double buffered watermarks and so shouldn't need this.
13033 * Do this after drm_atomic_helper_setup_commit() and
13034 * intel_atomic_prepare_commit() because we still want
13035 * to skip the flip and fb cleanup waits. Although that
13036 * does risk yanking the mapping from under the display
13039 * FIXME doing watermarks and fb cleanup from a vblank worker
13040 * (assuming we had any) would solve these problems.
13042 if (INTEL_GEN(dev_priv) < 9)
13043 state->legacy_cursor_update = false;
13045 drm_atomic_helper_swap_state(state, true);
13046 dev_priv->wm.distrust_bios_wm = false;
13047 intel_shared_dpll_swap_state(state);
13048 intel_atomic_track_fbs(state);
13050 if (intel_state->modeset) {
13051 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13052 sizeof(intel_state->min_pixclk));
13053 dev_priv->active_crtcs = intel_state->active_crtcs;
13054 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13055 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13058 drm_atomic_state_get(state);
13059 INIT_WORK(&state->commit_work,
13060 nonblock ? intel_atomic_commit_work : NULL);
13062 i915_sw_fence_commit(&intel_state->commit_ready);
13064 i915_sw_fence_wait(&intel_state->commit_ready);
13065 intel_atomic_commit_tail(state);
13071 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13073 struct drm_device *dev = crtc->dev;
13074 struct drm_atomic_state *state;
13075 struct drm_crtc_state *crtc_state;
13078 state = drm_atomic_state_alloc(dev);
13080 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13081 crtc->base.id, crtc->name);
13085 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
13088 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13089 ret = PTR_ERR_OR_ZERO(crtc_state);
13091 if (!crtc_state->active)
13094 crtc_state->mode_changed = true;
13095 ret = drm_atomic_commit(state);
13098 if (ret == -EDEADLK) {
13099 drm_atomic_state_clear(state);
13100 drm_modeset_backoff(state->acquire_ctx);
13105 drm_atomic_state_put(state);
13108 static const struct drm_crtc_funcs intel_crtc_funcs = {
13109 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13110 .set_config = drm_atomic_helper_set_config,
13111 .set_property = drm_atomic_helper_crtc_set_property,
13112 .destroy = intel_crtc_destroy,
13113 .page_flip = drm_atomic_helper_page_flip,
13114 .atomic_duplicate_state = intel_crtc_duplicate_state,
13115 .atomic_destroy_state = intel_crtc_destroy_state,
13116 .set_crc_source = intel_crtc_set_crc_source,
13120 * intel_prepare_plane_fb - Prepare fb for usage on plane
13121 * @plane: drm plane to prepare for
13122 * @fb: framebuffer to prepare for presentation
13124 * Prepares a framebuffer for usage on a display plane. Generally this
13125 * involves pinning the underlying object and updating the frontbuffer tracking
13126 * bits. Some older platforms need special physical address handling for
13129 * Must be called with struct_mutex held.
13131 * Returns 0 on success, negative error code on failure.
13134 intel_prepare_plane_fb(struct drm_plane *plane,
13135 struct drm_plane_state *new_state)
13137 struct intel_atomic_state *intel_state =
13138 to_intel_atomic_state(new_state->state);
13139 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13140 struct drm_framebuffer *fb = new_state->fb;
13141 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13142 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13146 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13147 INTEL_INFO(dev_priv)->cursor_needs_physical) {
13148 const int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13150 ret = i915_gem_object_attach_phys(obj, align);
13152 DRM_DEBUG_KMS("failed to attach phys object\n");
13156 struct i915_vma *vma;
13158 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13160 DRM_DEBUG_KMS("failed to pin object\n");
13161 return PTR_ERR(vma);
13164 to_intel_plane_state(new_state)->vma = vma;
13168 if (!obj && !old_obj)
13172 struct drm_crtc_state *crtc_state =
13173 drm_atomic_get_existing_crtc_state(new_state->state,
13174 plane->state->crtc);
13176 /* Big Hammer, we also need to ensure that any pending
13177 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13178 * current scanout is retired before unpinning the old
13179 * framebuffer. Note that we rely on userspace rendering
13180 * into the buffer attached to the pipe they are waiting
13181 * on. If not, userspace generates a GPU hang with IPEHR
13182 * point to the MI_WAIT_FOR_EVENT.
13184 * This should only fail upon a hung GPU, in which case we
13185 * can safely continue.
13187 if (needs_modeset(crtc_state)) {
13188 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13189 old_obj->resv, NULL,
13197 if (new_state->fence) { /* explicit fencing */
13198 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13200 I915_FENCE_TIMEOUT,
13209 if (!new_state->fence) { /* implicit fencing */
13210 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13212 false, I915_FENCE_TIMEOUT,
13217 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13224 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13225 * @plane: drm plane to clean up for
13226 * @fb: old framebuffer that was on plane
13228 * Cleans up a framebuffer that has just been removed from a plane.
13230 * Must be called with struct_mutex held.
13233 intel_cleanup_plane_fb(struct drm_plane *plane,
13234 struct drm_plane_state *old_state)
13236 struct i915_vma *vma;
13238 /* Should only be called after a successful intel_prepare_plane_fb()! */
13239 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13241 intel_unpin_fb_vma(vma);
13245 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13247 struct drm_i915_private *dev_priv;
13249 int crtc_clock, max_dotclk;
13251 if (!intel_crtc || !crtc_state->base.enable)
13252 return DRM_PLANE_HELPER_NO_SCALING;
13254 dev_priv = to_i915(intel_crtc->base.dev);
13256 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13257 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13259 if (IS_GEMINILAKE(dev_priv))
13262 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13263 return DRM_PLANE_HELPER_NO_SCALING;
13266 * skl max scale is lower of:
13267 * close to 3 but not 3, -1 is for that purpose
13271 max_scale = min((1 << 16) * 3 - 1,
13272 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
13278 intel_check_primary_plane(struct drm_plane *plane,
13279 struct intel_crtc_state *crtc_state,
13280 struct intel_plane_state *state)
13282 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13283 struct drm_crtc *crtc = state->base.crtc;
13284 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13285 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13286 bool can_position = false;
13289 if (INTEL_GEN(dev_priv) >= 9) {
13290 /* use scaler when colorkey is not required */
13291 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13293 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13295 can_position = true;
13298 ret = drm_plane_helper_check_state(&state->base,
13300 min_scale, max_scale,
13301 can_position, true);
13305 if (!state->base.fb)
13308 if (INTEL_GEN(dev_priv) >= 9) {
13309 ret = skl_check_plane_surface(state);
13313 state->ctl = skl_plane_ctl(crtc_state, state);
13315 ret = i9xx_check_plane_surface(state);
13319 state->ctl = i9xx_plane_ctl(crtc_state, state);
13325 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13326 struct drm_crtc_state *old_crtc_state)
13328 struct drm_device *dev = crtc->dev;
13329 struct drm_i915_private *dev_priv = to_i915(dev);
13330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13331 struct intel_crtc_state *intel_cstate =
13332 to_intel_crtc_state(crtc->state);
13333 struct intel_crtc_state *old_intel_cstate =
13334 to_intel_crtc_state(old_crtc_state);
13335 struct intel_atomic_state *old_intel_state =
13336 to_intel_atomic_state(old_crtc_state->state);
13337 bool modeset = needs_modeset(crtc->state);
13340 (intel_cstate->base.color_mgmt_changed ||
13341 intel_cstate->update_pipe)) {
13342 intel_color_set_csc(crtc->state);
13343 intel_color_load_luts(crtc->state);
13346 /* Perform vblank evasion around commit operation */
13347 intel_pipe_update_start(intel_crtc);
13352 if (intel_cstate->update_pipe)
13353 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13354 else if (INTEL_GEN(dev_priv) >= 9)
13355 skl_detach_scalers(intel_crtc);
13358 if (dev_priv->display.atomic_update_watermarks)
13359 dev_priv->display.atomic_update_watermarks(old_intel_state,
13363 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13364 struct drm_crtc_state *old_crtc_state)
13366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13368 intel_pipe_update_end(intel_crtc, NULL);
13372 * intel_plane_destroy - destroy a plane
13373 * @plane: plane to destroy
13375 * Common destruction function for all types of planes (primary, cursor,
13378 void intel_plane_destroy(struct drm_plane *plane)
13380 drm_plane_cleanup(plane);
13381 kfree(to_intel_plane(plane));
13384 const struct drm_plane_funcs intel_plane_funcs = {
13385 .update_plane = drm_atomic_helper_update_plane,
13386 .disable_plane = drm_atomic_helper_disable_plane,
13387 .destroy = intel_plane_destroy,
13388 .set_property = drm_atomic_helper_plane_set_property,
13389 .atomic_get_property = intel_plane_atomic_get_property,
13390 .atomic_set_property = intel_plane_atomic_set_property,
13391 .atomic_duplicate_state = intel_plane_duplicate_state,
13392 .atomic_destroy_state = intel_plane_destroy_state,
13396 intel_legacy_cursor_update(struct drm_plane *plane,
13397 struct drm_crtc *crtc,
13398 struct drm_framebuffer *fb,
13399 int crtc_x, int crtc_y,
13400 unsigned int crtc_w, unsigned int crtc_h,
13401 uint32_t src_x, uint32_t src_y,
13402 uint32_t src_w, uint32_t src_h,
13403 struct drm_modeset_acquire_ctx *ctx)
13405 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13407 struct drm_plane_state *old_plane_state, *new_plane_state;
13408 struct intel_plane *intel_plane = to_intel_plane(plane);
13409 struct drm_framebuffer *old_fb;
13410 struct drm_crtc_state *crtc_state = crtc->state;
13411 struct i915_vma *old_vma;
13414 * When crtc is inactive or there is a modeset pending,
13415 * wait for it to complete in the slowpath
13417 if (!crtc_state->active || needs_modeset(crtc_state) ||
13418 to_intel_crtc_state(crtc_state)->update_pipe)
13421 old_plane_state = plane->state;
13424 * If any parameters change that may affect watermarks,
13425 * take the slowpath. Only changing fb or position should be
13428 if (old_plane_state->crtc != crtc ||
13429 old_plane_state->src_w != src_w ||
13430 old_plane_state->src_h != src_h ||
13431 old_plane_state->crtc_w != crtc_w ||
13432 old_plane_state->crtc_h != crtc_h ||
13433 !old_plane_state->fb != !fb)
13436 new_plane_state = intel_plane_duplicate_state(plane);
13437 if (!new_plane_state)
13440 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13442 new_plane_state->src_x = src_x;
13443 new_plane_state->src_y = src_y;
13444 new_plane_state->src_w = src_w;
13445 new_plane_state->src_h = src_h;
13446 new_plane_state->crtc_x = crtc_x;
13447 new_plane_state->crtc_y = crtc_y;
13448 new_plane_state->crtc_w = crtc_w;
13449 new_plane_state->crtc_h = crtc_h;
13451 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13452 to_intel_plane_state(new_plane_state));
13456 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13460 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13461 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13463 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13465 DRM_DEBUG_KMS("failed to attach phys object\n");
13469 struct i915_vma *vma;
13471 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13473 DRM_DEBUG_KMS("failed to pin object\n");
13475 ret = PTR_ERR(vma);
13479 to_intel_plane_state(new_plane_state)->vma = vma;
13482 old_fb = old_plane_state->fb;
13483 old_vma = to_intel_plane_state(old_plane_state)->vma;
13485 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13486 intel_plane->frontbuffer_bit);
13488 /* Swap plane state */
13489 new_plane_state->fence = old_plane_state->fence;
13490 *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13491 new_plane_state->fence = NULL;
13492 new_plane_state->fb = old_fb;
13493 to_intel_plane_state(new_plane_state)->vma = old_vma;
13495 if (plane->state->visible) {
13496 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13497 intel_plane->update_plane(plane,
13498 to_intel_crtc_state(crtc->state),
13499 to_intel_plane_state(plane->state));
13501 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13502 intel_plane->disable_plane(plane, crtc);
13505 intel_cleanup_plane_fb(plane, new_plane_state);
13508 mutex_unlock(&dev_priv->drm.struct_mutex);
13510 intel_plane_destroy_state(plane, new_plane_state);
13514 return drm_atomic_helper_update_plane(plane, crtc, fb,
13515 crtc_x, crtc_y, crtc_w, crtc_h,
13516 src_x, src_y, src_w, src_h, ctx);
13519 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13520 .update_plane = intel_legacy_cursor_update,
13521 .disable_plane = drm_atomic_helper_disable_plane,
13522 .destroy = intel_plane_destroy,
13523 .set_property = drm_atomic_helper_plane_set_property,
13524 .atomic_get_property = intel_plane_atomic_get_property,
13525 .atomic_set_property = intel_plane_atomic_set_property,
13526 .atomic_duplicate_state = intel_plane_duplicate_state,
13527 .atomic_destroy_state = intel_plane_destroy_state,
13530 static struct intel_plane *
13531 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13533 struct intel_plane *primary = NULL;
13534 struct intel_plane_state *state = NULL;
13535 const uint32_t *intel_primary_formats;
13536 unsigned int supported_rotations;
13537 unsigned int num_formats;
13540 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13546 state = intel_create_plane_state(&primary->base);
13552 primary->base.state = &state->base;
13554 primary->can_scale = false;
13555 primary->max_downscale = 1;
13556 if (INTEL_GEN(dev_priv) >= 9) {
13557 primary->can_scale = true;
13558 state->scaler_id = -1;
13560 primary->pipe = pipe;
13562 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13563 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13565 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13566 primary->plane = (enum plane) !pipe;
13568 primary->plane = (enum plane) pipe;
13569 primary->id = PLANE_PRIMARY;
13570 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13571 primary->check_plane = intel_check_primary_plane;
13573 if (INTEL_GEN(dev_priv) >= 9) {
13574 intel_primary_formats = skl_primary_formats;
13575 num_formats = ARRAY_SIZE(skl_primary_formats);
13577 primary->update_plane = skylake_update_primary_plane;
13578 primary->disable_plane = skylake_disable_primary_plane;
13579 } else if (INTEL_GEN(dev_priv) >= 4) {
13580 intel_primary_formats = i965_primary_formats;
13581 num_formats = ARRAY_SIZE(i965_primary_formats);
13583 primary->update_plane = i9xx_update_primary_plane;
13584 primary->disable_plane = i9xx_disable_primary_plane;
13586 intel_primary_formats = i8xx_primary_formats;
13587 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13589 primary->update_plane = i9xx_update_primary_plane;
13590 primary->disable_plane = i9xx_disable_primary_plane;
13593 if (INTEL_GEN(dev_priv) >= 9)
13594 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13595 0, &intel_plane_funcs,
13596 intel_primary_formats, num_formats,
13597 DRM_PLANE_TYPE_PRIMARY,
13598 "plane 1%c", pipe_name(pipe));
13599 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13600 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13601 0, &intel_plane_funcs,
13602 intel_primary_formats, num_formats,
13603 DRM_PLANE_TYPE_PRIMARY,
13604 "primary %c", pipe_name(pipe));
13606 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13607 0, &intel_plane_funcs,
13608 intel_primary_formats, num_formats,
13609 DRM_PLANE_TYPE_PRIMARY,
13610 "plane %c", plane_name(primary->plane));
13614 if (INTEL_GEN(dev_priv) >= 9) {
13615 supported_rotations =
13616 DRM_ROTATE_0 | DRM_ROTATE_90 |
13617 DRM_ROTATE_180 | DRM_ROTATE_270;
13618 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13619 supported_rotations =
13620 DRM_ROTATE_0 | DRM_ROTATE_180 |
13622 } else if (INTEL_GEN(dev_priv) >= 4) {
13623 supported_rotations =
13624 DRM_ROTATE_0 | DRM_ROTATE_180;
13626 supported_rotations = DRM_ROTATE_0;
13629 if (INTEL_GEN(dev_priv) >= 4)
13630 drm_plane_create_rotation_property(&primary->base,
13632 supported_rotations);
13634 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13642 return ERR_PTR(ret);
13646 intel_check_cursor_plane(struct drm_plane *plane,
13647 struct intel_crtc_state *crtc_state,
13648 struct intel_plane_state *state)
13650 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13651 struct drm_framebuffer *fb = state->base.fb;
13652 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13653 enum pipe pipe = to_intel_plane(plane)->pipe;
13657 ret = drm_plane_helper_check_state(&state->base,
13659 DRM_PLANE_HELPER_NO_SCALING,
13660 DRM_PLANE_HELPER_NO_SCALING,
13665 /* if we want to turn off the cursor ignore width and height */
13669 /* Check for which cursor types we support */
13670 if (!cursor_size_ok(dev_priv, state->base.crtc_w,
13671 state->base.crtc_h)) {
13672 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13673 state->base.crtc_w, state->base.crtc_h);
13677 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13678 if (obj->base.size < stride * state->base.crtc_h) {
13679 DRM_DEBUG_KMS("buffer is too small\n");
13683 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
13684 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13689 * There's something wrong with the cursor on CHV pipe C.
13690 * If it straddles the left edge of the screen then
13691 * moving it away from the edge or disabling it often
13692 * results in a pipe underrun, and often that can lead to
13693 * dead pipe (constant underrun reported, and it scans
13694 * out just a solid color). To recover from that, the
13695 * display power well must be turned off and on again.
13696 * Refuse the put the cursor into that compromised position.
13698 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
13699 state->base.visible && state->base.crtc_x < 0) {
13700 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13704 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
13705 state->ctl = i845_cursor_ctl(crtc_state, state);
13707 state->ctl = i9xx_cursor_ctl(crtc_state, state);
13713 intel_disable_cursor_plane(struct drm_plane *plane,
13714 struct drm_crtc *crtc)
13716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13718 intel_crtc->cursor_addr = 0;
13719 intel_crtc_update_cursor(crtc, NULL);
13723 intel_update_cursor_plane(struct drm_plane *plane,
13724 const struct intel_crtc_state *crtc_state,
13725 const struct intel_plane_state *state)
13727 struct drm_crtc *crtc = crtc_state->base.crtc;
13728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13729 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13730 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13735 else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
13736 addr = intel_plane_ggtt_offset(state);
13738 addr = obj->phys_handle->busaddr;
13740 intel_crtc->cursor_addr = addr;
13741 intel_crtc_update_cursor(crtc, state);
13744 static struct intel_plane *
13745 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13747 struct intel_plane *cursor = NULL;
13748 struct intel_plane_state *state = NULL;
13751 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13757 state = intel_create_plane_state(&cursor->base);
13763 cursor->base.state = &state->base;
13765 cursor->can_scale = false;
13766 cursor->max_downscale = 1;
13767 cursor->pipe = pipe;
13768 cursor->plane = pipe;
13769 cursor->id = PLANE_CURSOR;
13770 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13771 cursor->check_plane = intel_check_cursor_plane;
13772 cursor->update_plane = intel_update_cursor_plane;
13773 cursor->disable_plane = intel_disable_cursor_plane;
13775 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13776 0, &intel_cursor_plane_funcs,
13777 intel_cursor_formats,
13778 ARRAY_SIZE(intel_cursor_formats),
13779 DRM_PLANE_TYPE_CURSOR,
13780 "cursor %c", pipe_name(pipe));
13784 if (INTEL_GEN(dev_priv) >= 4)
13785 drm_plane_create_rotation_property(&cursor->base,
13790 if (INTEL_GEN(dev_priv) >= 9)
13791 state->scaler_id = -1;
13793 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13801 return ERR_PTR(ret);
13804 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13805 struct intel_crtc_state *crtc_state)
13807 struct intel_crtc_scaler_state *scaler_state =
13808 &crtc_state->scaler_state;
13809 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13812 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13813 if (!crtc->num_scalers)
13816 for (i = 0; i < crtc->num_scalers; i++) {
13817 struct intel_scaler *scaler = &scaler_state->scalers[i];
13819 scaler->in_use = 0;
13820 scaler->mode = PS_SCALER_MODE_DYN;
13823 scaler_state->scaler_id = -1;
13826 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13828 struct intel_crtc *intel_crtc;
13829 struct intel_crtc_state *crtc_state = NULL;
13830 struct intel_plane *primary = NULL;
13831 struct intel_plane *cursor = NULL;
13834 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13838 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13843 intel_crtc->config = crtc_state;
13844 intel_crtc->base.state = &crtc_state->base;
13845 crtc_state->base.crtc = &intel_crtc->base;
13847 primary = intel_primary_plane_create(dev_priv, pipe);
13848 if (IS_ERR(primary)) {
13849 ret = PTR_ERR(primary);
13852 intel_crtc->plane_ids_mask |= BIT(primary->id);
13854 for_each_sprite(dev_priv, pipe, sprite) {
13855 struct intel_plane *plane;
13857 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13858 if (IS_ERR(plane)) {
13859 ret = PTR_ERR(plane);
13862 intel_crtc->plane_ids_mask |= BIT(plane->id);
13865 cursor = intel_cursor_plane_create(dev_priv, pipe);
13866 if (IS_ERR(cursor)) {
13867 ret = PTR_ERR(cursor);
13870 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13872 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13873 &primary->base, &cursor->base,
13875 "pipe %c", pipe_name(pipe));
13879 intel_crtc->pipe = pipe;
13880 intel_crtc->plane = primary->plane;
13882 intel_crtc->cursor_base = ~0;
13883 intel_crtc->cursor_cntl = ~0;
13884 intel_crtc->cursor_size = ~0;
13886 /* initialize shared scalers */
13887 intel_crtc_init_scalers(intel_crtc, crtc_state);
13889 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13890 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13891 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13892 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13894 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13896 intel_color_init(&intel_crtc->base);
13898 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13904 * drm_mode_config_cleanup() will free up any
13905 * crtcs/planes already initialized.
13913 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13915 struct drm_device *dev = connector->base.dev;
13917 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13919 if (!connector->base.state->crtc)
13920 return INVALID_PIPE;
13922 return to_intel_crtc(connector->base.state->crtc)->pipe;
13925 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13926 struct drm_file *file)
13928 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13929 struct drm_crtc *drmmode_crtc;
13930 struct intel_crtc *crtc;
13932 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13936 crtc = to_intel_crtc(drmmode_crtc);
13937 pipe_from_crtc_id->pipe = crtc->pipe;
13942 static int intel_encoder_clones(struct intel_encoder *encoder)
13944 struct drm_device *dev = encoder->base.dev;
13945 struct intel_encoder *source_encoder;
13946 int index_mask = 0;
13949 for_each_intel_encoder(dev, source_encoder) {
13950 if (encoders_cloneable(encoder, source_encoder))
13951 index_mask |= (1 << entry);
13959 static bool has_edp_a(struct drm_i915_private *dev_priv)
13961 if (!IS_MOBILE(dev_priv))
13964 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13967 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13973 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13975 if (INTEL_GEN(dev_priv) >= 9)
13978 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13981 if (IS_CHERRYVIEW(dev_priv))
13984 if (HAS_PCH_LPT_H(dev_priv) &&
13985 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13988 /* DDI E can't be used if DDI A requires 4 lanes */
13989 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13992 if (!dev_priv->vbt.int_crt_support)
13998 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14003 if (HAS_DDI(dev_priv))
14006 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14007 * everywhere where registers can be write protected.
14009 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14014 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14015 u32 val = I915_READ(PP_CONTROL(pps_idx));
14017 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14018 I915_WRITE(PP_CONTROL(pps_idx), val);
14022 static void intel_pps_init(struct drm_i915_private *dev_priv)
14024 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14025 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14026 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14027 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14029 dev_priv->pps_mmio_base = PPS_BASE;
14031 intel_pps_unlock_regs_wa(dev_priv);
14034 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14036 struct intel_encoder *encoder;
14037 bool dpd_is_edp = false;
14039 intel_pps_init(dev_priv);
14042 * intel_edp_init_connector() depends on this completing first, to
14043 * prevent the registeration of both eDP and LVDS and the incorrect
14044 * sharing of the PPS.
14046 intel_lvds_init(dev_priv);
14048 if (intel_crt_present(dev_priv))
14049 intel_crt_init(dev_priv);
14051 if (IS_GEN9_LP(dev_priv)) {
14053 * FIXME: Broxton doesn't support port detection via the
14054 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14055 * detect the ports.
14057 intel_ddi_init(dev_priv, PORT_A);
14058 intel_ddi_init(dev_priv, PORT_B);
14059 intel_ddi_init(dev_priv, PORT_C);
14061 intel_dsi_init(dev_priv);
14062 } else if (HAS_DDI(dev_priv)) {
14066 * Haswell uses DDI functions to detect digital outputs.
14067 * On SKL pre-D0 the strap isn't connected, so we assume
14070 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14071 /* WaIgnoreDDIAStrap: skl */
14072 if (found || IS_GEN9_BC(dev_priv))
14073 intel_ddi_init(dev_priv, PORT_A);
14075 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14077 found = I915_READ(SFUSE_STRAP);
14079 if (found & SFUSE_STRAP_DDIB_DETECTED)
14080 intel_ddi_init(dev_priv, PORT_B);
14081 if (found & SFUSE_STRAP_DDIC_DETECTED)
14082 intel_ddi_init(dev_priv, PORT_C);
14083 if (found & SFUSE_STRAP_DDID_DETECTED)
14084 intel_ddi_init(dev_priv, PORT_D);
14086 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14088 if (IS_GEN9_BC(dev_priv) &&
14089 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14090 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14091 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14092 intel_ddi_init(dev_priv, PORT_E);
14094 } else if (HAS_PCH_SPLIT(dev_priv)) {
14096 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14098 if (has_edp_a(dev_priv))
14099 intel_dp_init(dev_priv, DP_A, PORT_A);
14101 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14102 /* PCH SDVOB multiplex with HDMIB */
14103 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14105 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14106 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14107 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14110 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14111 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14113 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14114 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14116 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14117 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14119 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14120 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14121 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14122 bool has_edp, has_port;
14125 * The DP_DETECTED bit is the latched state of the DDC
14126 * SDA pin at boot. However since eDP doesn't require DDC
14127 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14128 * eDP ports may have been muxed to an alternate function.
14129 * Thus we can't rely on the DP_DETECTED bit alone to detect
14130 * eDP ports. Consult the VBT as well as DP_DETECTED to
14131 * detect eDP ports.
14133 * Sadly the straps seem to be missing sometimes even for HDMI
14134 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14135 * and VBT for the presence of the port. Additionally we can't
14136 * trust the port type the VBT declares as we've seen at least
14137 * HDMI ports that the VBT claim are DP or eDP.
14139 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14140 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14141 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14142 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14143 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14144 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14146 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14147 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14148 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14149 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14150 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14151 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14153 if (IS_CHERRYVIEW(dev_priv)) {
14155 * eDP not supported on port D,
14156 * so no need to worry about it
14158 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14159 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14160 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14161 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14162 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14165 intel_dsi_init(dev_priv);
14166 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14167 bool found = false;
14169 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14170 DRM_DEBUG_KMS("probing SDVOB\n");
14171 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14172 if (!found && IS_G4X(dev_priv)) {
14173 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14174 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14177 if (!found && IS_G4X(dev_priv))
14178 intel_dp_init(dev_priv, DP_B, PORT_B);
14181 /* Before G4X SDVOC doesn't have its own detect register */
14183 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14184 DRM_DEBUG_KMS("probing SDVOC\n");
14185 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14188 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14190 if (IS_G4X(dev_priv)) {
14191 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14192 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14194 if (IS_G4X(dev_priv))
14195 intel_dp_init(dev_priv, DP_C, PORT_C);
14198 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14199 intel_dp_init(dev_priv, DP_D, PORT_D);
14200 } else if (IS_GEN2(dev_priv))
14201 intel_dvo_init(dev_priv);
14203 if (SUPPORTS_TV(dev_priv))
14204 intel_tv_init(dev_priv);
14206 intel_psr_init(dev_priv);
14208 for_each_intel_encoder(&dev_priv->drm, encoder) {
14209 encoder->base.possible_crtcs = encoder->crtc_mask;
14210 encoder->base.possible_clones =
14211 intel_encoder_clones(encoder);
14214 intel_init_pch_refclk(dev_priv);
14216 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14219 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14221 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14223 drm_framebuffer_cleanup(fb);
14225 i915_gem_object_lock(intel_fb->obj);
14226 WARN_ON(!intel_fb->obj->framebuffer_references--);
14227 i915_gem_object_unlock(intel_fb->obj);
14229 i915_gem_object_put(intel_fb->obj);
14234 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14235 struct drm_file *file,
14236 unsigned int *handle)
14238 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14239 struct drm_i915_gem_object *obj = intel_fb->obj;
14241 if (obj->userptr.mm) {
14242 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14246 return drm_gem_handle_create(file, &obj->base, handle);
14249 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14250 struct drm_file *file,
14251 unsigned flags, unsigned color,
14252 struct drm_clip_rect *clips,
14253 unsigned num_clips)
14255 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14257 i915_gem_object_flush_if_display(obj);
14258 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14263 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14264 .destroy = intel_user_framebuffer_destroy,
14265 .create_handle = intel_user_framebuffer_create_handle,
14266 .dirty = intel_user_framebuffer_dirty,
14270 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14271 uint64_t fb_modifier, uint32_t pixel_format)
14273 u32 gen = INTEL_GEN(dev_priv);
14276 int cpp = drm_format_plane_cpp(pixel_format, 0);
14278 /* "The stride in bytes must not exceed the of the size of 8K
14279 * pixels and 32K bytes."
14281 return min(8192 * cpp, 32768);
14282 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14284 } else if (gen >= 4) {
14285 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14289 } else if (gen >= 3) {
14290 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14295 /* XXX DSPC is limited to 4k tiled */
14300 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14301 struct drm_i915_gem_object *obj,
14302 struct drm_mode_fb_cmd2 *mode_cmd)
14304 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14305 struct drm_format_name_buf format_name;
14306 u32 pitch_limit, stride_alignment;
14307 unsigned int tiling, stride;
14310 i915_gem_object_lock(obj);
14311 obj->framebuffer_references++;
14312 tiling = i915_gem_object_get_tiling(obj);
14313 stride = i915_gem_object_get_stride(obj);
14314 i915_gem_object_unlock(obj);
14316 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14318 * If there's a fence, enforce that
14319 * the fb modifier and tiling mode match.
14321 if (tiling != I915_TILING_NONE &&
14322 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14323 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14327 if (tiling == I915_TILING_X) {
14328 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14329 } else if (tiling == I915_TILING_Y) {
14330 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14335 /* Passed in modifier sanity checking. */
14336 switch (mode_cmd->modifier[0]) {
14337 case I915_FORMAT_MOD_Y_TILED:
14338 case I915_FORMAT_MOD_Yf_TILED:
14339 if (INTEL_GEN(dev_priv) < 9) {
14340 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14341 mode_cmd->modifier[0]);
14344 case DRM_FORMAT_MOD_LINEAR:
14345 case I915_FORMAT_MOD_X_TILED:
14348 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14349 mode_cmd->modifier[0]);
14354 * gen2/3 display engine uses the fence if present,
14355 * so the tiling mode must match the fb modifier exactly.
14357 if (INTEL_INFO(dev_priv)->gen < 4 &&
14358 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14359 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14363 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14364 mode_cmd->pixel_format);
14365 if (mode_cmd->pitches[0] > pitch_limit) {
14366 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14367 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14368 "tiled" : "linear",
14369 mode_cmd->pitches[0], pitch_limit);
14374 * If there's a fence, enforce that
14375 * the fb pitch and fence stride match.
14377 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14378 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14379 mode_cmd->pitches[0], stride);
14383 /* Reject formats not supported by any plane early. */
14384 switch (mode_cmd->pixel_format) {
14385 case DRM_FORMAT_C8:
14386 case DRM_FORMAT_RGB565:
14387 case DRM_FORMAT_XRGB8888:
14388 case DRM_FORMAT_ARGB8888:
14390 case DRM_FORMAT_XRGB1555:
14391 if (INTEL_GEN(dev_priv) > 3) {
14392 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14393 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14397 case DRM_FORMAT_ABGR8888:
14398 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14399 INTEL_GEN(dev_priv) < 9) {
14400 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14401 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14405 case DRM_FORMAT_XBGR8888:
14406 case DRM_FORMAT_XRGB2101010:
14407 case DRM_FORMAT_XBGR2101010:
14408 if (INTEL_GEN(dev_priv) < 4) {
14409 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14410 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14414 case DRM_FORMAT_ABGR2101010:
14415 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14416 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14417 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14421 case DRM_FORMAT_YUYV:
14422 case DRM_FORMAT_UYVY:
14423 case DRM_FORMAT_YVYU:
14424 case DRM_FORMAT_VYUY:
14425 if (INTEL_GEN(dev_priv) < 5) {
14426 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14427 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14432 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14433 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14437 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14438 if (mode_cmd->offsets[0] != 0)
14441 drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14442 &intel_fb->base, mode_cmd);
14444 stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
14445 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14446 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
14447 mode_cmd->pitches[0], stride_alignment);
14451 intel_fb->obj = obj;
14453 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14457 ret = drm_framebuffer_init(obj->base.dev,
14461 DRM_ERROR("framebuffer init failed %d\n", ret);
14468 i915_gem_object_lock(obj);
14469 obj->framebuffer_references--;
14470 i915_gem_object_unlock(obj);
14474 static struct drm_framebuffer *
14475 intel_user_framebuffer_create(struct drm_device *dev,
14476 struct drm_file *filp,
14477 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14479 struct drm_framebuffer *fb;
14480 struct drm_i915_gem_object *obj;
14481 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14483 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14485 return ERR_PTR(-ENOENT);
14487 fb = intel_framebuffer_create(obj, &mode_cmd);
14489 i915_gem_object_put(obj);
14494 static void intel_atomic_state_free(struct drm_atomic_state *state)
14496 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14498 drm_atomic_state_default_release(state);
14500 i915_sw_fence_fini(&intel_state->commit_ready);
14505 static const struct drm_mode_config_funcs intel_mode_funcs = {
14506 .fb_create = intel_user_framebuffer_create,
14507 .output_poll_changed = intel_fbdev_output_poll_changed,
14508 .atomic_check = intel_atomic_check,
14509 .atomic_commit = intel_atomic_commit,
14510 .atomic_state_alloc = intel_atomic_state_alloc,
14511 .atomic_state_clear = intel_atomic_state_clear,
14512 .atomic_state_free = intel_atomic_state_free,
14516 * intel_init_display_hooks - initialize the display modesetting hooks
14517 * @dev_priv: device private
14519 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14521 intel_init_cdclk_hooks(dev_priv);
14523 if (INTEL_INFO(dev_priv)->gen >= 9) {
14524 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14525 dev_priv->display.get_initial_plane_config =
14526 skylake_get_initial_plane_config;
14527 dev_priv->display.crtc_compute_clock =
14528 haswell_crtc_compute_clock;
14529 dev_priv->display.crtc_enable = haswell_crtc_enable;
14530 dev_priv->display.crtc_disable = haswell_crtc_disable;
14531 } else if (HAS_DDI(dev_priv)) {
14532 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14533 dev_priv->display.get_initial_plane_config =
14534 ironlake_get_initial_plane_config;
14535 dev_priv->display.crtc_compute_clock =
14536 haswell_crtc_compute_clock;
14537 dev_priv->display.crtc_enable = haswell_crtc_enable;
14538 dev_priv->display.crtc_disable = haswell_crtc_disable;
14539 } else if (HAS_PCH_SPLIT(dev_priv)) {
14540 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14541 dev_priv->display.get_initial_plane_config =
14542 ironlake_get_initial_plane_config;
14543 dev_priv->display.crtc_compute_clock =
14544 ironlake_crtc_compute_clock;
14545 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14546 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14547 } else if (IS_CHERRYVIEW(dev_priv)) {
14548 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14549 dev_priv->display.get_initial_plane_config =
14550 i9xx_get_initial_plane_config;
14551 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14552 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14553 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14554 } else if (IS_VALLEYVIEW(dev_priv)) {
14555 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14556 dev_priv->display.get_initial_plane_config =
14557 i9xx_get_initial_plane_config;
14558 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14559 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14560 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14561 } else if (IS_G4X(dev_priv)) {
14562 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14563 dev_priv->display.get_initial_plane_config =
14564 i9xx_get_initial_plane_config;
14565 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14566 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14567 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14568 } else if (IS_PINEVIEW(dev_priv)) {
14569 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14570 dev_priv->display.get_initial_plane_config =
14571 i9xx_get_initial_plane_config;
14572 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14573 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14574 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14575 } else if (!IS_GEN2(dev_priv)) {
14576 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14577 dev_priv->display.get_initial_plane_config =
14578 i9xx_get_initial_plane_config;
14579 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14580 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14581 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14583 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14584 dev_priv->display.get_initial_plane_config =
14585 i9xx_get_initial_plane_config;
14586 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14587 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14588 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14591 if (IS_GEN5(dev_priv)) {
14592 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14593 } else if (IS_GEN6(dev_priv)) {
14594 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14595 } else if (IS_IVYBRIDGE(dev_priv)) {
14596 /* FIXME: detect B0+ stepping and use auto training */
14597 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14598 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14599 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14602 if (dev_priv->info.gen >= 9)
14603 dev_priv->display.update_crtcs = skl_update_crtcs;
14605 dev_priv->display.update_crtcs = intel_update_crtcs;
14607 switch (INTEL_INFO(dev_priv)->gen) {
14609 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14613 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14618 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14622 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14625 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14626 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14629 /* Drop through - unsupported since execlist only. */
14631 /* Default just returns -ENODEV to indicate unsupported */
14632 dev_priv->display.queue_flip = intel_default_queue_flip;
14637 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14638 * resume, or other times. This quirk makes sure that's the case for
14639 * affected systems.
14641 static void quirk_pipea_force(struct drm_device *dev)
14643 struct drm_i915_private *dev_priv = to_i915(dev);
14645 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14646 DRM_INFO("applying pipe a force quirk\n");
14649 static void quirk_pipeb_force(struct drm_device *dev)
14651 struct drm_i915_private *dev_priv = to_i915(dev);
14653 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14654 DRM_INFO("applying pipe b force quirk\n");
14658 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14660 static void quirk_ssc_force_disable(struct drm_device *dev)
14662 struct drm_i915_private *dev_priv = to_i915(dev);
14663 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14664 DRM_INFO("applying lvds SSC disable quirk\n");
14668 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14671 static void quirk_invert_brightness(struct drm_device *dev)
14673 struct drm_i915_private *dev_priv = to_i915(dev);
14674 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14675 DRM_INFO("applying inverted panel brightness quirk\n");
14678 /* Some VBT's incorrectly indicate no backlight is present */
14679 static void quirk_backlight_present(struct drm_device *dev)
14681 struct drm_i915_private *dev_priv = to_i915(dev);
14682 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14683 DRM_INFO("applying backlight present quirk\n");
14686 struct intel_quirk {
14688 int subsystem_vendor;
14689 int subsystem_device;
14690 void (*hook)(struct drm_device *dev);
14693 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14694 struct intel_dmi_quirk {
14695 void (*hook)(struct drm_device *dev);
14696 const struct dmi_system_id (*dmi_id_list)[];
14699 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14701 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14705 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14707 .dmi_id_list = &(const struct dmi_system_id[]) {
14709 .callback = intel_dmi_reverse_brightness,
14710 .ident = "NCR Corporation",
14711 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14712 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14715 { } /* terminating entry */
14717 .hook = quirk_invert_brightness,
14721 static struct intel_quirk intel_quirks[] = {
14722 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14723 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14725 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14726 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14728 /* 830 needs to leave pipe A & dpll A up */
14729 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14731 /* 830 needs to leave pipe B & dpll B up */
14732 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14734 /* Lenovo U160 cannot use SSC on LVDS */
14735 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14737 /* Sony Vaio Y cannot use SSC on LVDS */
14738 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14740 /* Acer Aspire 5734Z must invert backlight brightness */
14741 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14743 /* Acer/eMachines G725 */
14744 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14746 /* Acer/eMachines e725 */
14747 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14749 /* Acer/Packard Bell NCL20 */
14750 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14752 /* Acer Aspire 4736Z */
14753 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14755 /* Acer Aspire 5336 */
14756 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14758 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14759 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14761 /* Acer C720 Chromebook (Core i3 4005U) */
14762 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14764 /* Apple Macbook 2,1 (Core 2 T7400) */
14765 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14767 /* Apple Macbook 4,1 */
14768 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14770 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14771 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14773 /* HP Chromebook 14 (Celeron 2955U) */
14774 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14776 /* Dell Chromebook 11 */
14777 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14779 /* Dell Chromebook 11 (2015 version) */
14780 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14783 static void intel_init_quirks(struct drm_device *dev)
14785 struct pci_dev *d = dev->pdev;
14788 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14789 struct intel_quirk *q = &intel_quirks[i];
14791 if (d->device == q->device &&
14792 (d->subsystem_vendor == q->subsystem_vendor ||
14793 q->subsystem_vendor == PCI_ANY_ID) &&
14794 (d->subsystem_device == q->subsystem_device ||
14795 q->subsystem_device == PCI_ANY_ID))
14798 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14799 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14800 intel_dmi_quirks[i].hook(dev);
14804 /* Disable the VGA plane that we never use */
14805 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14807 struct pci_dev *pdev = dev_priv->drm.pdev;
14809 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14811 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14812 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14813 outb(SR01, VGA_SR_INDEX);
14814 sr1 = inb(VGA_SR_DATA);
14815 outb(sr1 | 1<<5, VGA_SR_DATA);
14816 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14819 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14820 POSTING_READ(vga_reg);
14823 void intel_modeset_init_hw(struct drm_device *dev)
14825 struct drm_i915_private *dev_priv = to_i915(dev);
14827 intel_update_cdclk(dev_priv);
14828 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14830 intel_init_clock_gating(dev_priv);
14834 * Calculate what we think the watermarks should be for the state we've read
14835 * out of the hardware and then immediately program those watermarks so that
14836 * we ensure the hardware settings match our internal state.
14838 * We can calculate what we think WM's should be by creating a duplicate of the
14839 * current state (which was constructed during hardware readout) and running it
14840 * through the atomic check code to calculate new watermark values in the
14843 static void sanitize_watermarks(struct drm_device *dev)
14845 struct drm_i915_private *dev_priv = to_i915(dev);
14846 struct drm_atomic_state *state;
14847 struct intel_atomic_state *intel_state;
14848 struct drm_crtc *crtc;
14849 struct drm_crtc_state *cstate;
14850 struct drm_modeset_acquire_ctx ctx;
14854 /* Only supported on platforms that use atomic watermark design */
14855 if (!dev_priv->display.optimize_watermarks)
14859 * We need to hold connection_mutex before calling duplicate_state so
14860 * that the connector loop is protected.
14862 drm_modeset_acquire_init(&ctx, 0);
14864 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14865 if (ret == -EDEADLK) {
14866 drm_modeset_backoff(&ctx);
14868 } else if (WARN_ON(ret)) {
14872 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14873 if (WARN_ON(IS_ERR(state)))
14876 intel_state = to_intel_atomic_state(state);
14879 * Hardware readout is the only time we don't want to calculate
14880 * intermediate watermarks (since we don't trust the current
14883 if (!HAS_GMCH_DISPLAY(dev_priv))
14884 intel_state->skip_intermediate_wm = true;
14886 ret = intel_atomic_check(dev, state);
14889 * If we fail here, it means that the hardware appears to be
14890 * programmed in a way that shouldn't be possible, given our
14891 * understanding of watermark requirements. This might mean a
14892 * mistake in the hardware readout code or a mistake in the
14893 * watermark calculations for a given platform. Raise a WARN
14894 * so that this is noticeable.
14896 * If this actually happens, we'll have to just leave the
14897 * BIOS-programmed watermarks untouched and hope for the best.
14899 WARN(true, "Could not determine valid watermarks for inherited state\n");
14903 /* Write calculated watermark values back */
14904 for_each_new_crtc_in_state(state, crtc, cstate, i) {
14905 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14907 cs->wm.need_postvbl_update = true;
14908 dev_priv->display.optimize_watermarks(intel_state, cs);
14912 drm_atomic_state_put(state);
14914 drm_modeset_drop_locks(&ctx);
14915 drm_modeset_acquire_fini(&ctx);
14918 int intel_modeset_init(struct drm_device *dev)
14920 struct drm_i915_private *dev_priv = to_i915(dev);
14921 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14923 struct intel_crtc *crtc;
14925 drm_mode_config_init(dev);
14927 dev->mode_config.min_width = 0;
14928 dev->mode_config.min_height = 0;
14930 dev->mode_config.preferred_depth = 24;
14931 dev->mode_config.prefer_shadow = 1;
14933 dev->mode_config.allow_fb_modifiers = true;
14935 dev->mode_config.funcs = &intel_mode_funcs;
14937 INIT_WORK(&dev_priv->atomic_helper.free_work,
14938 intel_atomic_helper_free_state_worker);
14940 intel_init_quirks(dev);
14942 intel_init_pm(dev_priv);
14944 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14948 * There may be no VBT; and if the BIOS enabled SSC we can
14949 * just keep using it to avoid unnecessary flicker. Whereas if the
14950 * BIOS isn't using it, don't assume it will work even if the VBT
14951 * indicates as much.
14953 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14954 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14957 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14958 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14959 bios_lvds_use_ssc ? "en" : "dis",
14960 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14961 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14965 if (IS_GEN2(dev_priv)) {
14966 dev->mode_config.max_width = 2048;
14967 dev->mode_config.max_height = 2048;
14968 } else if (IS_GEN3(dev_priv)) {
14969 dev->mode_config.max_width = 4096;
14970 dev->mode_config.max_height = 4096;
14972 dev->mode_config.max_width = 8192;
14973 dev->mode_config.max_height = 8192;
14976 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14977 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14978 dev->mode_config.cursor_height = 1023;
14979 } else if (IS_GEN2(dev_priv)) {
14980 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14981 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14983 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14984 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14987 dev->mode_config.fb_base = ggtt->mappable_base;
14989 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14990 INTEL_INFO(dev_priv)->num_pipes,
14991 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14993 for_each_pipe(dev_priv, pipe) {
14996 ret = intel_crtc_init(dev_priv, pipe);
14998 drm_mode_config_cleanup(dev);
15003 intel_shared_dpll_init(dev);
15005 intel_update_czclk(dev_priv);
15006 intel_modeset_init_hw(dev);
15008 if (dev_priv->max_cdclk_freq == 0)
15009 intel_update_max_cdclk(dev_priv);
15011 /* Just disable it once at startup */
15012 i915_disable_vga(dev_priv);
15013 intel_setup_outputs(dev_priv);
15015 drm_modeset_lock_all(dev);
15016 intel_modeset_setup_hw_state(dev);
15017 drm_modeset_unlock_all(dev);
15019 for_each_intel_crtc(dev, crtc) {
15020 struct intel_initial_plane_config plane_config = {};
15026 * Note that reserving the BIOS fb up front prevents us
15027 * from stuffing other stolen allocations like the ring
15028 * on top. This prevents some ugliness at boot time, and
15029 * can even allow for smooth boot transitions if the BIOS
15030 * fb is large enough for the active pipe configuration.
15032 dev_priv->display.get_initial_plane_config(crtc,
15036 * If the fb is shared between multiple heads, we'll
15037 * just get the first one.
15039 intel_find_initial_plane_obj(crtc, &plane_config);
15043 * Make sure hardware watermarks really match the state we read out.
15044 * Note that we need to do this after reconstructing the BIOS fb's
15045 * since the watermark calculation done here will use pstate->fb.
15047 if (!HAS_GMCH_DISPLAY(dev_priv))
15048 sanitize_watermarks(dev);
15053 static void intel_enable_pipe_a(struct drm_device *dev)
15055 struct intel_connector *connector;
15056 struct drm_connector_list_iter conn_iter;
15057 struct drm_connector *crt = NULL;
15058 struct intel_load_detect_pipe load_detect_temp;
15059 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15062 /* We can't just switch on the pipe A, we need to set things up with a
15063 * proper mode and output configuration. As a gross hack, enable pipe A
15064 * by enabling the load detect pipe once. */
15065 drm_connector_list_iter_begin(dev, &conn_iter);
15066 for_each_intel_connector_iter(connector, &conn_iter) {
15067 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15068 crt = &connector->base;
15072 drm_connector_list_iter_end(&conn_iter);
15077 ret = intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx);
15078 WARN(ret < 0, "All modeset mutexes are locked, but intel_get_load_detect_pipe failed\n");
15081 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15085 intel_check_plane_mapping(struct intel_crtc *crtc)
15087 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15090 if (INTEL_INFO(dev_priv)->num_pipes == 1)
15093 val = I915_READ(DSPCNTR(!crtc->plane));
15095 if ((val & DISPLAY_PLANE_ENABLE) &&
15096 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15102 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15104 struct drm_device *dev = crtc->base.dev;
15105 struct intel_encoder *encoder;
15107 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15113 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15115 struct drm_device *dev = encoder->base.dev;
15116 struct intel_connector *connector;
15118 for_each_connector_on_encoder(dev, &encoder->base, connector)
15124 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15125 enum transcoder pch_transcoder)
15127 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15128 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15131 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15133 struct drm_device *dev = crtc->base.dev;
15134 struct drm_i915_private *dev_priv = to_i915(dev);
15135 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15137 /* Clear any frame start delays used for debugging left by the BIOS */
15138 if (!transcoder_is_dsi(cpu_transcoder)) {
15139 i915_reg_t reg = PIPECONF(cpu_transcoder);
15142 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15145 /* restore vblank interrupts to correct state */
15146 drm_crtc_vblank_reset(&crtc->base);
15147 if (crtc->active) {
15148 struct intel_plane *plane;
15150 drm_crtc_vblank_on(&crtc->base);
15152 /* Disable everything but the primary plane */
15153 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15154 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15157 trace_intel_disable_plane(&plane->base, crtc);
15158 plane->disable_plane(&plane->base, &crtc->base);
15162 /* We need to sanitize the plane -> pipe mapping first because this will
15163 * disable the crtc (and hence change the state) if it is wrong. Note
15164 * that gen4+ has a fixed plane -> pipe mapping. */
15165 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15168 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15169 crtc->base.base.id, crtc->base.name);
15171 /* Pipe has the wrong plane attached and the plane is active.
15172 * Temporarily change the plane mapping and disable everything
15174 plane = crtc->plane;
15175 crtc->base.primary->state->visible = true;
15176 crtc->plane = !plane;
15177 intel_crtc_disable_noatomic(&crtc->base);
15178 crtc->plane = plane;
15181 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15182 crtc->pipe == PIPE_A && !crtc->active) {
15183 /* BIOS forgot to enable pipe A, this mostly happens after
15184 * resume. Force-enable the pipe to fix this, the update_dpms
15185 * call below we restore the pipe to the right state, but leave
15186 * the required bits on. */
15187 intel_enable_pipe_a(dev);
15190 /* Adjust the state of the output pipe according to whether we
15191 * have active connectors/encoders. */
15192 if (crtc->active && !intel_crtc_has_encoders(crtc))
15193 intel_crtc_disable_noatomic(&crtc->base);
15195 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15197 * We start out with underrun reporting disabled to avoid races.
15198 * For correct bookkeeping mark this on active crtcs.
15200 * Also on gmch platforms we dont have any hardware bits to
15201 * disable the underrun reporting. Which means we need to start
15202 * out with underrun reporting disabled also on inactive pipes,
15203 * since otherwise we'll complain about the garbage we read when
15204 * e.g. coming up after runtime pm.
15206 * No protection against concurrent access is required - at
15207 * worst a fifo underrun happens which also sets this to false.
15209 crtc->cpu_fifo_underrun_disabled = true;
15211 * We track the PCH trancoder underrun reporting state
15212 * within the crtc. With crtc for pipe A housing the underrun
15213 * reporting state for PCH transcoder A, crtc for pipe B housing
15214 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15215 * and marking underrun reporting as disabled for the non-existing
15216 * PCH transcoders B and C would prevent enabling the south
15217 * error interrupt (see cpt_can_enable_serr_int()).
15219 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15220 crtc->pch_fifo_underrun_disabled = true;
15224 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15226 struct intel_connector *connector;
15228 /* We need to check both for a crtc link (meaning that the
15229 * encoder is active and trying to read from a pipe) and the
15230 * pipe itself being active. */
15231 bool has_active_crtc = encoder->base.crtc &&
15232 to_intel_crtc(encoder->base.crtc)->active;
15234 connector = intel_encoder_find_connector(encoder);
15235 if (connector && !has_active_crtc) {
15236 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15237 encoder->base.base.id,
15238 encoder->base.name);
15240 /* Connector is active, but has no active pipe. This is
15241 * fallout from our resume register restoring. Disable
15242 * the encoder manually again. */
15243 if (encoder->base.crtc) {
15244 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15246 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15247 encoder->base.base.id,
15248 encoder->base.name);
15249 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15250 if (encoder->post_disable)
15251 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15253 encoder->base.crtc = NULL;
15255 /* Inconsistent output/port/pipe state happens presumably due to
15256 * a bug in one of the get_hw_state functions. Or someplace else
15257 * in our code, like the register restore mess on resume. Clamp
15258 * things to off as a safer default. */
15260 connector->base.dpms = DRM_MODE_DPMS_OFF;
15261 connector->base.encoder = NULL;
15263 /* Enabled encoders without active connectors will be fixed in
15264 * the crtc fixup. */
15267 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15269 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15271 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15272 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15273 i915_disable_vga(dev_priv);
15277 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15279 /* This function can be called both from intel_modeset_setup_hw_state or
15280 * at a very early point in our resume sequence, where the power well
15281 * structures are not yet restored. Since this function is at a very
15282 * paranoid "someone might have enabled VGA while we were not looking"
15283 * level, just check if the power well is enabled instead of trying to
15284 * follow the "don't touch the power well if we don't need it" policy
15285 * the rest of the driver uses. */
15286 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15289 i915_redisable_vga_power_on(dev_priv);
15291 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15294 static bool primary_get_hw_state(struct intel_plane *plane)
15296 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15298 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15301 /* FIXME read out full plane state for all planes */
15302 static void readout_plane_state(struct intel_crtc *crtc)
15304 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
15307 visible = crtc->active && primary_get_hw_state(primary);
15309 intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
15310 to_intel_plane_state(primary->base.state),
15314 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15316 struct drm_i915_private *dev_priv = to_i915(dev);
15318 struct intel_crtc *crtc;
15319 struct intel_encoder *encoder;
15320 struct intel_connector *connector;
15321 struct drm_connector_list_iter conn_iter;
15324 dev_priv->active_crtcs = 0;
15326 for_each_intel_crtc(dev, crtc) {
15327 struct intel_crtc_state *crtc_state =
15328 to_intel_crtc_state(crtc->base.state);
15330 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15331 memset(crtc_state, 0, sizeof(*crtc_state));
15332 crtc_state->base.crtc = &crtc->base;
15334 crtc_state->base.active = crtc_state->base.enable =
15335 dev_priv->display.get_pipe_config(crtc, crtc_state);
15337 crtc->base.enabled = crtc_state->base.enable;
15338 crtc->active = crtc_state->base.active;
15340 if (crtc_state->base.active)
15341 dev_priv->active_crtcs |= 1 << crtc->pipe;
15343 readout_plane_state(crtc);
15345 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15346 crtc->base.base.id, crtc->base.name,
15347 enableddisabled(crtc_state->base.active));
15350 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15351 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15353 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15354 &pll->state.hw_state);
15355 pll->state.crtc_mask = 0;
15356 for_each_intel_crtc(dev, crtc) {
15357 struct intel_crtc_state *crtc_state =
15358 to_intel_crtc_state(crtc->base.state);
15360 if (crtc_state->base.active &&
15361 crtc_state->shared_dpll == pll)
15362 pll->state.crtc_mask |= 1 << crtc->pipe;
15364 pll->active_mask = pll->state.crtc_mask;
15366 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15367 pll->name, pll->state.crtc_mask, pll->on);
15370 for_each_intel_encoder(dev, encoder) {
15373 if (encoder->get_hw_state(encoder, &pipe)) {
15374 struct intel_crtc_state *crtc_state;
15376 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15377 crtc_state = to_intel_crtc_state(crtc->base.state);
15379 encoder->base.crtc = &crtc->base;
15380 crtc_state->output_types |= 1 << encoder->type;
15381 encoder->get_config(encoder, crtc_state);
15383 encoder->base.crtc = NULL;
15386 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15387 encoder->base.base.id, encoder->base.name,
15388 enableddisabled(encoder->base.crtc),
15392 drm_connector_list_iter_begin(dev, &conn_iter);
15393 for_each_intel_connector_iter(connector, &conn_iter) {
15394 if (connector->get_hw_state(connector)) {
15395 connector->base.dpms = DRM_MODE_DPMS_ON;
15397 encoder = connector->encoder;
15398 connector->base.encoder = &encoder->base;
15400 if (encoder->base.crtc &&
15401 encoder->base.crtc->state->active) {
15403 * This has to be done during hardware readout
15404 * because anything calling .crtc_disable may
15405 * rely on the connector_mask being accurate.
15407 encoder->base.crtc->state->connector_mask |=
15408 1 << drm_connector_index(&connector->base);
15409 encoder->base.crtc->state->encoder_mask |=
15410 1 << drm_encoder_index(&encoder->base);
15414 connector->base.dpms = DRM_MODE_DPMS_OFF;
15415 connector->base.encoder = NULL;
15417 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15418 connector->base.base.id, connector->base.name,
15419 enableddisabled(connector->base.encoder));
15421 drm_connector_list_iter_end(&conn_iter);
15423 for_each_intel_crtc(dev, crtc) {
15424 struct intel_crtc_state *crtc_state =
15425 to_intel_crtc_state(crtc->base.state);
15428 crtc->base.hwmode = crtc_state->base.adjusted_mode;
15430 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15431 if (crtc_state->base.active) {
15432 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15433 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15434 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15437 * The initial mode needs to be set in order to keep
15438 * the atomic core happy. It wants a valid mode if the
15439 * crtc's enabled, so we do the above call.
15441 * But we don't set all the derived state fully, hence
15442 * set a flag to indicate that a full recalculation is
15443 * needed on the next commit.
15445 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15447 intel_crtc_compute_pixel_rate(crtc_state);
15449 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15450 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15451 pixclk = crtc_state->pixel_rate;
15453 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15455 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15456 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15457 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15459 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15460 update_scanline_offset(crtc);
15463 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15465 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15470 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15472 struct intel_encoder *encoder;
15474 for_each_intel_encoder(&dev_priv->drm, encoder) {
15476 enum intel_display_power_domain domain;
15478 if (!encoder->get_power_domains)
15481 get_domains = encoder->get_power_domains(encoder);
15482 for_each_power_domain(domain, get_domains)
15483 intel_display_power_get(dev_priv, domain);
15487 /* Scan out the current hw modeset state,
15488 * and sanitizes it to the current state
15491 intel_modeset_setup_hw_state(struct drm_device *dev)
15493 struct drm_i915_private *dev_priv = to_i915(dev);
15495 struct intel_crtc *crtc;
15496 struct intel_encoder *encoder;
15499 intel_modeset_readout_hw_state(dev);
15501 /* HW state is read out, now we need to sanitize this mess. */
15502 get_encoder_power_domains(dev_priv);
15504 for_each_intel_encoder(dev, encoder) {
15505 intel_sanitize_encoder(encoder);
15508 for_each_pipe(dev_priv, pipe) {
15509 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15511 intel_sanitize_crtc(crtc);
15512 intel_dump_pipe_config(crtc, crtc->config,
15513 "[setup_hw_state]");
15516 intel_modeset_update_connector_atomic_state(dev);
15518 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15519 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15521 if (!pll->on || pll->active_mask)
15524 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15526 pll->funcs.disable(dev_priv, pll);
15530 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15531 vlv_wm_get_hw_state(dev);
15532 vlv_wm_sanitize(dev_priv);
15533 } else if (IS_GEN9(dev_priv)) {
15534 skl_wm_get_hw_state(dev);
15535 } else if (HAS_PCH_SPLIT(dev_priv)) {
15536 ilk_wm_get_hw_state(dev);
15539 for_each_intel_crtc(dev, crtc) {
15542 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15543 if (WARN_ON(put_domains))
15544 modeset_put_power_domains(dev_priv, put_domains);
15546 intel_display_set_init_power(dev_priv, false);
15548 intel_power_domains_verify_state(dev_priv);
15550 intel_fbc_init_pipe_state(dev_priv);
15553 void intel_display_resume(struct drm_device *dev)
15555 struct drm_i915_private *dev_priv = to_i915(dev);
15556 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15557 struct drm_modeset_acquire_ctx ctx;
15560 dev_priv->modeset_restore_state = NULL;
15562 state->acquire_ctx = &ctx;
15565 * This is a cludge because with real atomic modeset mode_config.mutex
15566 * won't be taken. Unfortunately some probed state like
15567 * audio_codec_enable is still protected by mode_config.mutex, so lock
15570 mutex_lock(&dev->mode_config.mutex);
15571 drm_modeset_acquire_init(&ctx, 0);
15574 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15575 if (ret != -EDEADLK)
15578 drm_modeset_backoff(&ctx);
15582 ret = __intel_display_resume(dev, state, &ctx);
15584 drm_modeset_drop_locks(&ctx);
15585 drm_modeset_acquire_fini(&ctx);
15586 mutex_unlock(&dev->mode_config.mutex);
15589 DRM_ERROR("Restoring old state failed with %i\n", ret);
15591 drm_atomic_state_put(state);
15594 void intel_modeset_gem_init(struct drm_device *dev)
15596 struct drm_i915_private *dev_priv = to_i915(dev);
15598 intel_init_gt_powersave(dev_priv);
15600 intel_setup_overlay(dev_priv);
15603 int intel_connector_register(struct drm_connector *connector)
15605 struct intel_connector *intel_connector = to_intel_connector(connector);
15608 ret = intel_backlight_device_register(intel_connector);
15618 void intel_connector_unregister(struct drm_connector *connector)
15620 struct intel_connector *intel_connector = to_intel_connector(connector);
15622 intel_backlight_device_unregister(intel_connector);
15623 intel_panel_destroy_backlight(connector);
15626 void intel_modeset_cleanup(struct drm_device *dev)
15628 struct drm_i915_private *dev_priv = to_i915(dev);
15630 flush_work(&dev_priv->atomic_helper.free_work);
15631 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15633 intel_disable_gt_powersave(dev_priv);
15636 * Interrupts and polling as the first thing to avoid creating havoc.
15637 * Too much stuff here (turning of connectors, ...) would
15638 * experience fancy races otherwise.
15640 intel_irq_uninstall(dev_priv);
15643 * Due to the hpd irq storm handling the hotplug work can re-arm the
15644 * poll handlers. Hence disable polling after hpd handling is shut down.
15646 drm_kms_helper_poll_fini(dev);
15648 intel_unregister_dsm_handler();
15650 intel_fbc_global_disable(dev_priv);
15652 /* flush any delayed tasks or pending work */
15653 flush_scheduled_work();
15655 drm_mode_config_cleanup(dev);
15657 intel_cleanup_overlay(dev_priv);
15659 intel_cleanup_gt_powersave(dev_priv);
15661 intel_teardown_gmbus(dev_priv);
15664 void intel_connector_attach_encoder(struct intel_connector *connector,
15665 struct intel_encoder *encoder)
15667 connector->encoder = encoder;
15668 drm_mode_connector_attach_encoder(&connector->base,
15673 * set vga decode state - true == enable VGA decode
15675 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15677 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15680 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15681 DRM_ERROR("failed to read control word\n");
15685 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15689 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15691 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15693 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15694 DRM_ERROR("failed to write control word\n");
15701 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15703 struct intel_display_error_state {
15705 u32 power_well_driver;
15707 int num_transcoders;
15709 struct intel_cursor_error_state {
15714 } cursor[I915_MAX_PIPES];
15716 struct intel_pipe_error_state {
15717 bool power_domain_on;
15720 } pipe[I915_MAX_PIPES];
15722 struct intel_plane_error_state {
15730 } plane[I915_MAX_PIPES];
15732 struct intel_transcoder_error_state {
15733 bool power_domain_on;
15734 enum transcoder cpu_transcoder;
15747 struct intel_display_error_state *
15748 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15750 struct intel_display_error_state *error;
15751 int transcoders[] = {
15759 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15762 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15766 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15767 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15769 for_each_pipe(dev_priv, i) {
15770 error->pipe[i].power_domain_on =
15771 __intel_display_power_is_enabled(dev_priv,
15772 POWER_DOMAIN_PIPE(i));
15773 if (!error->pipe[i].power_domain_on)
15776 error->cursor[i].control = I915_READ(CURCNTR(i));
15777 error->cursor[i].position = I915_READ(CURPOS(i));
15778 error->cursor[i].base = I915_READ(CURBASE(i));
15780 error->plane[i].control = I915_READ(DSPCNTR(i));
15781 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15782 if (INTEL_GEN(dev_priv) <= 3) {
15783 error->plane[i].size = I915_READ(DSPSIZE(i));
15784 error->plane[i].pos = I915_READ(DSPPOS(i));
15786 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15787 error->plane[i].addr = I915_READ(DSPADDR(i));
15788 if (INTEL_GEN(dev_priv) >= 4) {
15789 error->plane[i].surface = I915_READ(DSPSURF(i));
15790 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15793 error->pipe[i].source = I915_READ(PIPESRC(i));
15795 if (HAS_GMCH_DISPLAY(dev_priv))
15796 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15799 /* Note: this does not include DSI transcoders. */
15800 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15801 if (HAS_DDI(dev_priv))
15802 error->num_transcoders++; /* Account for eDP. */
15804 for (i = 0; i < error->num_transcoders; i++) {
15805 enum transcoder cpu_transcoder = transcoders[i];
15807 error->transcoder[i].power_domain_on =
15808 __intel_display_power_is_enabled(dev_priv,
15809 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15810 if (!error->transcoder[i].power_domain_on)
15813 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15815 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15816 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15817 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15818 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15819 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15820 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15821 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15827 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15830 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15831 struct intel_display_error_state *error)
15833 struct drm_i915_private *dev_priv = m->i915;
15839 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15840 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15841 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15842 error->power_well_driver);
15843 for_each_pipe(dev_priv, i) {
15844 err_printf(m, "Pipe [%d]:\n", i);
15845 err_printf(m, " Power: %s\n",
15846 onoff(error->pipe[i].power_domain_on));
15847 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15848 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15850 err_printf(m, "Plane [%d]:\n", i);
15851 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15852 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15853 if (INTEL_GEN(dev_priv) <= 3) {
15854 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15855 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15857 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15858 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15859 if (INTEL_GEN(dev_priv) >= 4) {
15860 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15861 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15864 err_printf(m, "Cursor [%d]:\n", i);
15865 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15866 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15867 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15870 for (i = 0; i < error->num_transcoders; i++) {
15871 err_printf(m, "CPU transcoder: %s\n",
15872 transcoder_name(error->transcoder[i].cpu_transcoder));
15873 err_printf(m, " Power: %s\n",
15874 onoff(error->transcoder[i].power_domain_on));
15875 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15876 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15877 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15878 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15879 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15880 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15881 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);