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1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 static bool is_mmio_work(struct intel_flip_work *work)
53 {
54         return work->mmio_work.func;
55 }
56
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
59         DRM_FORMAT_C8,
60         DRM_FORMAT_RGB565,
61         DRM_FORMAT_XRGB1555,
62         DRM_FORMAT_XRGB8888,
63 };
64
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
67         DRM_FORMAT_C8,
68         DRM_FORMAT_RGB565,
69         DRM_FORMAT_XRGB8888,
70         DRM_FORMAT_XBGR8888,
71         DRM_FORMAT_XRGB2101010,
72         DRM_FORMAT_XBGR2101010,
73 };
74
75 static const uint32_t skl_primary_formats[] = {
76         DRM_FORMAT_C8,
77         DRM_FORMAT_RGB565,
78         DRM_FORMAT_XRGB8888,
79         DRM_FORMAT_XBGR8888,
80         DRM_FORMAT_ARGB8888,
81         DRM_FORMAT_ABGR8888,
82         DRM_FORMAT_XRGB2101010,
83         DRM_FORMAT_XBGR2101010,
84         DRM_FORMAT_YUYV,
85         DRM_FORMAT_YVYU,
86         DRM_FORMAT_UYVY,
87         DRM_FORMAT_VYUY,
88 };
89
90 /* Cursor formats */
91 static const uint32_t intel_cursor_formats[] = {
92         DRM_FORMAT_ARGB8888,
93 };
94
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96                                 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98                                    struct intel_crtc_state *pipe_config);
99
100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
101                                   struct drm_i915_gem_object *obj,
102                                   struct drm_mode_fb_cmd2 *mode_cmd);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107                                          struct intel_link_m_n *m_n,
108                                          struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113                             const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115                             const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
119                                     struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
125
126 struct intel_limit {
127         struct {
128                 int min, max;
129         } dot, vco, n, m, m1, m2, p, p1;
130
131         struct {
132                 int dot_limit;
133                 int p2_slow, p2_fast;
134         } p2;
135 };
136
137 /* returns HPLL frequency in kHz */
138 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
139 {
140         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
141
142         /* Obtain SKU information */
143         mutex_lock(&dev_priv->sb_lock);
144         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
145                 CCK_FUSE_HPLL_FREQ_MASK;
146         mutex_unlock(&dev_priv->sb_lock);
147
148         return vco_freq[hpll_freq] * 1000;
149 }
150
151 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
152                       const char *name, u32 reg, int ref_freq)
153 {
154         u32 val;
155         int divider;
156
157         mutex_lock(&dev_priv->sb_lock);
158         val = vlv_cck_read(dev_priv, reg);
159         mutex_unlock(&dev_priv->sb_lock);
160
161         divider = val & CCK_FREQUENCY_VALUES;
162
163         WARN((val & CCK_FREQUENCY_STATUS) !=
164              (divider << CCK_FREQUENCY_STATUS_SHIFT),
165              "%s change in progress\n", name);
166
167         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
168 }
169
170 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
171                            const char *name, u32 reg)
172 {
173         if (dev_priv->hpll_freq == 0)
174                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
175
176         return vlv_get_cck_clock(dev_priv, name, reg,
177                                  dev_priv->hpll_freq);
178 }
179
180 static void intel_update_czclk(struct drm_i915_private *dev_priv)
181 {
182         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
183                 return;
184
185         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
186                                                       CCK_CZ_CLOCK_CONTROL);
187
188         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
189 }
190
191 static inline u32 /* units of 100MHz */
192 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
193                     const struct intel_crtc_state *pipe_config)
194 {
195         if (HAS_DDI(dev_priv))
196                 return pipe_config->port_clock; /* SPLL */
197         else if (IS_GEN5(dev_priv))
198                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
199         else
200                 return 270000;
201 }
202
203 static const struct intel_limit intel_limits_i8xx_dac = {
204         .dot = { .min = 25000, .max = 350000 },
205         .vco = { .min = 908000, .max = 1512000 },
206         .n = { .min = 2, .max = 16 },
207         .m = { .min = 96, .max = 140 },
208         .m1 = { .min = 18, .max = 26 },
209         .m2 = { .min = 6, .max = 16 },
210         .p = { .min = 4, .max = 128 },
211         .p1 = { .min = 2, .max = 33 },
212         .p2 = { .dot_limit = 165000,
213                 .p2_slow = 4, .p2_fast = 2 },
214 };
215
216 static const struct intel_limit intel_limits_i8xx_dvo = {
217         .dot = { .min = 25000, .max = 350000 },
218         .vco = { .min = 908000, .max = 1512000 },
219         .n = { .min = 2, .max = 16 },
220         .m = { .min = 96, .max = 140 },
221         .m1 = { .min = 18, .max = 26 },
222         .m2 = { .min = 6, .max = 16 },
223         .p = { .min = 4, .max = 128 },
224         .p1 = { .min = 2, .max = 33 },
225         .p2 = { .dot_limit = 165000,
226                 .p2_slow = 4, .p2_fast = 4 },
227 };
228
229 static const struct intel_limit intel_limits_i8xx_lvds = {
230         .dot = { .min = 25000, .max = 350000 },
231         .vco = { .min = 908000, .max = 1512000 },
232         .n = { .min = 2, .max = 16 },
233         .m = { .min = 96, .max = 140 },
234         .m1 = { .min = 18, .max = 26 },
235         .m2 = { .min = 6, .max = 16 },
236         .p = { .min = 4, .max = 128 },
237         .p1 = { .min = 1, .max = 6 },
238         .p2 = { .dot_limit = 165000,
239                 .p2_slow = 14, .p2_fast = 7 },
240 };
241
242 static const struct intel_limit intel_limits_i9xx_sdvo = {
243         .dot = { .min = 20000, .max = 400000 },
244         .vco = { .min = 1400000, .max = 2800000 },
245         .n = { .min = 1, .max = 6 },
246         .m = { .min = 70, .max = 120 },
247         .m1 = { .min = 8, .max = 18 },
248         .m2 = { .min = 3, .max = 7 },
249         .p = { .min = 5, .max = 80 },
250         .p1 = { .min = 1, .max = 8 },
251         .p2 = { .dot_limit = 200000,
252                 .p2_slow = 10, .p2_fast = 5 },
253 };
254
255 static const struct intel_limit intel_limits_i9xx_lvds = {
256         .dot = { .min = 20000, .max = 400000 },
257         .vco = { .min = 1400000, .max = 2800000 },
258         .n = { .min = 1, .max = 6 },
259         .m = { .min = 70, .max = 120 },
260         .m1 = { .min = 8, .max = 18 },
261         .m2 = { .min = 3, .max = 7 },
262         .p = { .min = 7, .max = 98 },
263         .p1 = { .min = 1, .max = 8 },
264         .p2 = { .dot_limit = 112000,
265                 .p2_slow = 14, .p2_fast = 7 },
266 };
267
268
269 static const struct intel_limit intel_limits_g4x_sdvo = {
270         .dot = { .min = 25000, .max = 270000 },
271         .vco = { .min = 1750000, .max = 3500000},
272         .n = { .min = 1, .max = 4 },
273         .m = { .min = 104, .max = 138 },
274         .m1 = { .min = 17, .max = 23 },
275         .m2 = { .min = 5, .max = 11 },
276         .p = { .min = 10, .max = 30 },
277         .p1 = { .min = 1, .max = 3},
278         .p2 = { .dot_limit = 270000,
279                 .p2_slow = 10,
280                 .p2_fast = 10
281         },
282 };
283
284 static const struct intel_limit intel_limits_g4x_hdmi = {
285         .dot = { .min = 22000, .max = 400000 },
286         .vco = { .min = 1750000, .max = 3500000},
287         .n = { .min = 1, .max = 4 },
288         .m = { .min = 104, .max = 138 },
289         .m1 = { .min = 16, .max = 23 },
290         .m2 = { .min = 5, .max = 11 },
291         .p = { .min = 5, .max = 80 },
292         .p1 = { .min = 1, .max = 8},
293         .p2 = { .dot_limit = 165000,
294                 .p2_slow = 10, .p2_fast = 5 },
295 };
296
297 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
298         .dot = { .min = 20000, .max = 115000 },
299         .vco = { .min = 1750000, .max = 3500000 },
300         .n = { .min = 1, .max = 3 },
301         .m = { .min = 104, .max = 138 },
302         .m1 = { .min = 17, .max = 23 },
303         .m2 = { .min = 5, .max = 11 },
304         .p = { .min = 28, .max = 112 },
305         .p1 = { .min = 2, .max = 8 },
306         .p2 = { .dot_limit = 0,
307                 .p2_slow = 14, .p2_fast = 14
308         },
309 };
310
311 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
312         .dot = { .min = 80000, .max = 224000 },
313         .vco = { .min = 1750000, .max = 3500000 },
314         .n = { .min = 1, .max = 3 },
315         .m = { .min = 104, .max = 138 },
316         .m1 = { .min = 17, .max = 23 },
317         .m2 = { .min = 5, .max = 11 },
318         .p = { .min = 14, .max = 42 },
319         .p1 = { .min = 2, .max = 6 },
320         .p2 = { .dot_limit = 0,
321                 .p2_slow = 7, .p2_fast = 7
322         },
323 };
324
325 static const struct intel_limit intel_limits_pineview_sdvo = {
326         .dot = { .min = 20000, .max = 400000},
327         .vco = { .min = 1700000, .max = 3500000 },
328         /* Pineview's Ncounter is a ring counter */
329         .n = { .min = 3, .max = 6 },
330         .m = { .min = 2, .max = 256 },
331         /* Pineview only has one combined m divider, which we treat as m2. */
332         .m1 = { .min = 0, .max = 0 },
333         .m2 = { .min = 0, .max = 254 },
334         .p = { .min = 5, .max = 80 },
335         .p1 = { .min = 1, .max = 8 },
336         .p2 = { .dot_limit = 200000,
337                 .p2_slow = 10, .p2_fast = 5 },
338 };
339
340 static const struct intel_limit intel_limits_pineview_lvds = {
341         .dot = { .min = 20000, .max = 400000 },
342         .vco = { .min = 1700000, .max = 3500000 },
343         .n = { .min = 3, .max = 6 },
344         .m = { .min = 2, .max = 256 },
345         .m1 = { .min = 0, .max = 0 },
346         .m2 = { .min = 0, .max = 254 },
347         .p = { .min = 7, .max = 112 },
348         .p1 = { .min = 1, .max = 8 },
349         .p2 = { .dot_limit = 112000,
350                 .p2_slow = 14, .p2_fast = 14 },
351 };
352
353 /* Ironlake / Sandybridge
354  *
355  * We calculate clock using (register_value + 2) for N/M1/M2, so here
356  * the range value for them is (actual_value - 2).
357  */
358 static const struct intel_limit intel_limits_ironlake_dac = {
359         .dot = { .min = 25000, .max = 350000 },
360         .vco = { .min = 1760000, .max = 3510000 },
361         .n = { .min = 1, .max = 5 },
362         .m = { .min = 79, .max = 127 },
363         .m1 = { .min = 12, .max = 22 },
364         .m2 = { .min = 5, .max = 9 },
365         .p = { .min = 5, .max = 80 },
366         .p1 = { .min = 1, .max = 8 },
367         .p2 = { .dot_limit = 225000,
368                 .p2_slow = 10, .p2_fast = 5 },
369 };
370
371 static const struct intel_limit intel_limits_ironlake_single_lvds = {
372         .dot = { .min = 25000, .max = 350000 },
373         .vco = { .min = 1760000, .max = 3510000 },
374         .n = { .min = 1, .max = 3 },
375         .m = { .min = 79, .max = 118 },
376         .m1 = { .min = 12, .max = 22 },
377         .m2 = { .min = 5, .max = 9 },
378         .p = { .min = 28, .max = 112 },
379         .p1 = { .min = 2, .max = 8 },
380         .p2 = { .dot_limit = 225000,
381                 .p2_slow = 14, .p2_fast = 14 },
382 };
383
384 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
385         .dot = { .min = 25000, .max = 350000 },
386         .vco = { .min = 1760000, .max = 3510000 },
387         .n = { .min = 1, .max = 3 },
388         .m = { .min = 79, .max = 127 },
389         .m1 = { .min = 12, .max = 22 },
390         .m2 = { .min = 5, .max = 9 },
391         .p = { .min = 14, .max = 56 },
392         .p1 = { .min = 2, .max = 8 },
393         .p2 = { .dot_limit = 225000,
394                 .p2_slow = 7, .p2_fast = 7 },
395 };
396
397 /* LVDS 100mhz refclk limits. */
398 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
399         .dot = { .min = 25000, .max = 350000 },
400         .vco = { .min = 1760000, .max = 3510000 },
401         .n = { .min = 1, .max = 2 },
402         .m = { .min = 79, .max = 126 },
403         .m1 = { .min = 12, .max = 22 },
404         .m2 = { .min = 5, .max = 9 },
405         .p = { .min = 28, .max = 112 },
406         .p1 = { .min = 2, .max = 8 },
407         .p2 = { .dot_limit = 225000,
408                 .p2_slow = 14, .p2_fast = 14 },
409 };
410
411 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
412         .dot = { .min = 25000, .max = 350000 },
413         .vco = { .min = 1760000, .max = 3510000 },
414         .n = { .min = 1, .max = 3 },
415         .m = { .min = 79, .max = 126 },
416         .m1 = { .min = 12, .max = 22 },
417         .m2 = { .min = 5, .max = 9 },
418         .p = { .min = 14, .max = 42 },
419         .p1 = { .min = 2, .max = 6 },
420         .p2 = { .dot_limit = 225000,
421                 .p2_slow = 7, .p2_fast = 7 },
422 };
423
424 static const struct intel_limit intel_limits_vlv = {
425          /*
426           * These are the data rate limits (measured in fast clocks)
427           * since those are the strictest limits we have. The fast
428           * clock and actual rate limits are more relaxed, so checking
429           * them would make no difference.
430           */
431         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
432         .vco = { .min = 4000000, .max = 6000000 },
433         .n = { .min = 1, .max = 7 },
434         .m1 = { .min = 2, .max = 3 },
435         .m2 = { .min = 11, .max = 156 },
436         .p1 = { .min = 2, .max = 3 },
437         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
438 };
439
440 static const struct intel_limit intel_limits_chv = {
441         /*
442          * These are the data rate limits (measured in fast clocks)
443          * since those are the strictest limits we have.  The fast
444          * clock and actual rate limits are more relaxed, so checking
445          * them would make no difference.
446          */
447         .dot = { .min = 25000 * 5, .max = 540000 * 5},
448         .vco = { .min = 4800000, .max = 6480000 },
449         .n = { .min = 1, .max = 1 },
450         .m1 = { .min = 2, .max = 2 },
451         .m2 = { .min = 24 << 22, .max = 175 << 22 },
452         .p1 = { .min = 2, .max = 4 },
453         .p2 = { .p2_slow = 1, .p2_fast = 14 },
454 };
455
456 static const struct intel_limit intel_limits_bxt = {
457         /* FIXME: find real dot limits */
458         .dot = { .min = 0, .max = INT_MAX },
459         .vco = { .min = 4800000, .max = 6700000 },
460         .n = { .min = 1, .max = 1 },
461         .m1 = { .min = 2, .max = 2 },
462         /* FIXME: find real m2 limits */
463         .m2 = { .min = 2 << 22, .max = 255 << 22 },
464         .p1 = { .min = 2, .max = 4 },
465         .p2 = { .p2_slow = 1, .p2_fast = 20 },
466 };
467
468 static bool
469 needs_modeset(struct drm_crtc_state *state)
470 {
471         return drm_atomic_crtc_needs_modeset(state);
472 }
473
474 /*
475  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
476  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
477  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
478  * The helpers' return value is the rate of the clock that is fed to the
479  * display engine's pipe which can be the above fast dot clock rate or a
480  * divided-down version of it.
481  */
482 /* m1 is reserved as 0 in Pineview, n is a ring counter */
483 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
484 {
485         clock->m = clock->m2 + 2;
486         clock->p = clock->p1 * clock->p2;
487         if (WARN_ON(clock->n == 0 || clock->p == 0))
488                 return 0;
489         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
490         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
491
492         return clock->dot;
493 }
494
495 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
496 {
497         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
498 }
499
500 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
501 {
502         clock->m = i9xx_dpll_compute_m(clock);
503         clock->p = clock->p1 * clock->p2;
504         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
505                 return 0;
506         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
507         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
508
509         return clock->dot;
510 }
511
512 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
513 {
514         clock->m = clock->m1 * clock->m2;
515         clock->p = clock->p1 * clock->p2;
516         if (WARN_ON(clock->n == 0 || clock->p == 0))
517                 return 0;
518         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
519         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
520
521         return clock->dot / 5;
522 }
523
524 int chv_calc_dpll_params(int refclk, struct dpll *clock)
525 {
526         clock->m = clock->m1 * clock->m2;
527         clock->p = clock->p1 * clock->p2;
528         if (WARN_ON(clock->n == 0 || clock->p == 0))
529                 return 0;
530         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
531                         clock->n << 22);
532         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533
534         return clock->dot / 5;
535 }
536
537 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
538 /**
539  * Returns whether the given set of divisors are valid for a given refclk with
540  * the given connectors.
541  */
542
543 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
544                                const struct intel_limit *limit,
545                                const struct dpll *clock)
546 {
547         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
548                 INTELPllInvalid("n out of range\n");
549         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
550                 INTELPllInvalid("p1 out of range\n");
551         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
552                 INTELPllInvalid("m2 out of range\n");
553         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
554                 INTELPllInvalid("m1 out of range\n");
555
556         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
557             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
558                 if (clock->m1 <= clock->m2)
559                         INTELPllInvalid("m1 <= m2\n");
560
561         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
562             !IS_GEN9_LP(dev_priv)) {
563                 if (clock->p < limit->p.min || limit->p.max < clock->p)
564                         INTELPllInvalid("p out of range\n");
565                 if (clock->m < limit->m.min || limit->m.max < clock->m)
566                         INTELPllInvalid("m out of range\n");
567         }
568
569         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
570                 INTELPllInvalid("vco out of range\n");
571         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
572          * connector, etc., rather than just a single range.
573          */
574         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
575                 INTELPllInvalid("dot out of range\n");
576
577         return true;
578 }
579
580 static int
581 i9xx_select_p2_div(const struct intel_limit *limit,
582                    const struct intel_crtc_state *crtc_state,
583                    int target)
584 {
585         struct drm_device *dev = crtc_state->base.crtc->dev;
586
587         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
588                 /*
589                  * For LVDS just rely on its current settings for dual-channel.
590                  * We haven't figured out how to reliably set up different
591                  * single/dual channel state, if we even can.
592                  */
593                 if (intel_is_dual_link_lvds(dev))
594                         return limit->p2.p2_fast;
595                 else
596                         return limit->p2.p2_slow;
597         } else {
598                 if (target < limit->p2.dot_limit)
599                         return limit->p2.p2_slow;
600                 else
601                         return limit->p2.p2_fast;
602         }
603 }
604
605 /*
606  * Returns a set of divisors for the desired target clock with the given
607  * refclk, or FALSE.  The returned values represent the clock equation:
608  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
609  *
610  * Target and reference clocks are specified in kHz.
611  *
612  * If match_clock is provided, then best_clock P divider must match the P
613  * divider from @match_clock used for LVDS downclocking.
614  */
615 static bool
616 i9xx_find_best_dpll(const struct intel_limit *limit,
617                     struct intel_crtc_state *crtc_state,
618                     int target, int refclk, struct dpll *match_clock,
619                     struct dpll *best_clock)
620 {
621         struct drm_device *dev = crtc_state->base.crtc->dev;
622         struct dpll clock;
623         int err = target;
624
625         memset(best_clock, 0, sizeof(*best_clock));
626
627         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
628
629         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630              clock.m1++) {
631                 for (clock.m2 = limit->m2.min;
632                      clock.m2 <= limit->m2.max; clock.m2++) {
633                         if (clock.m2 >= clock.m1)
634                                 break;
635                         for (clock.n = limit->n.min;
636                              clock.n <= limit->n.max; clock.n++) {
637                                 for (clock.p1 = limit->p1.min;
638                                         clock.p1 <= limit->p1.max; clock.p1++) {
639                                         int this_err;
640
641                                         i9xx_calc_dpll_params(refclk, &clock);
642                                         if (!intel_PLL_is_valid(to_i915(dev),
643                                                                 limit,
644                                                                 &clock))
645                                                 continue;
646                                         if (match_clock &&
647                                             clock.p != match_clock->p)
648                                                 continue;
649
650                                         this_err = abs(clock.dot - target);
651                                         if (this_err < err) {
652                                                 *best_clock = clock;
653                                                 err = this_err;
654                                         }
655                                 }
656                         }
657                 }
658         }
659
660         return (err != target);
661 }
662
663 /*
664  * Returns a set of divisors for the desired target clock with the given
665  * refclk, or FALSE.  The returned values represent the clock equation:
666  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
667  *
668  * Target and reference clocks are specified in kHz.
669  *
670  * If match_clock is provided, then best_clock P divider must match the P
671  * divider from @match_clock used for LVDS downclocking.
672  */
673 static bool
674 pnv_find_best_dpll(const struct intel_limit *limit,
675                    struct intel_crtc_state *crtc_state,
676                    int target, int refclk, struct dpll *match_clock,
677                    struct dpll *best_clock)
678 {
679         struct drm_device *dev = crtc_state->base.crtc->dev;
680         struct dpll clock;
681         int err = target;
682
683         memset(best_clock, 0, sizeof(*best_clock));
684
685         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
686
687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688              clock.m1++) {
689                 for (clock.m2 = limit->m2.min;
690                      clock.m2 <= limit->m2.max; clock.m2++) {
691                         for (clock.n = limit->n.min;
692                              clock.n <= limit->n.max; clock.n++) {
693                                 for (clock.p1 = limit->p1.min;
694                                         clock.p1 <= limit->p1.max; clock.p1++) {
695                                         int this_err;
696
697                                         pnv_calc_dpll_params(refclk, &clock);
698                                         if (!intel_PLL_is_valid(to_i915(dev),
699                                                                 limit,
700                                                                 &clock))
701                                                 continue;
702                                         if (match_clock &&
703                                             clock.p != match_clock->p)
704                                                 continue;
705
706                                         this_err = abs(clock.dot - target);
707                                         if (this_err < err) {
708                                                 *best_clock = clock;
709                                                 err = this_err;
710                                         }
711                                 }
712                         }
713                 }
714         }
715
716         return (err != target);
717 }
718
719 /*
720  * Returns a set of divisors for the desired target clock with the given
721  * refclk, or FALSE.  The returned values represent the clock equation:
722  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
723  *
724  * Target and reference clocks are specified in kHz.
725  *
726  * If match_clock is provided, then best_clock P divider must match the P
727  * divider from @match_clock used for LVDS downclocking.
728  */
729 static bool
730 g4x_find_best_dpll(const struct intel_limit *limit,
731                    struct intel_crtc_state *crtc_state,
732                    int target, int refclk, struct dpll *match_clock,
733                    struct dpll *best_clock)
734 {
735         struct drm_device *dev = crtc_state->base.crtc->dev;
736         struct dpll clock;
737         int max_n;
738         bool found = false;
739         /* approximately equals target * 0.00585 */
740         int err_most = (target >> 8) + (target >> 9);
741
742         memset(best_clock, 0, sizeof(*best_clock));
743
744         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
745
746         max_n = limit->n.max;
747         /* based on hardware requirement, prefer smaller n to precision */
748         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
749                 /* based on hardware requirement, prefere larger m1,m2 */
750                 for (clock.m1 = limit->m1.max;
751                      clock.m1 >= limit->m1.min; clock.m1--) {
752                         for (clock.m2 = limit->m2.max;
753                              clock.m2 >= limit->m2.min; clock.m2--) {
754                                 for (clock.p1 = limit->p1.max;
755                                      clock.p1 >= limit->p1.min; clock.p1--) {
756                                         int this_err;
757
758                                         i9xx_calc_dpll_params(refclk, &clock);
759                                         if (!intel_PLL_is_valid(to_i915(dev),
760                                                                 limit,
761                                                                 &clock))
762                                                 continue;
763
764                                         this_err = abs(clock.dot - target);
765                                         if (this_err < err_most) {
766                                                 *best_clock = clock;
767                                                 err_most = this_err;
768                                                 max_n = clock.n;
769                                                 found = true;
770                                         }
771                                 }
772                         }
773                 }
774         }
775         return found;
776 }
777
778 /*
779  * Check if the calculated PLL configuration is more optimal compared to the
780  * best configuration and error found so far. Return the calculated error.
781  */
782 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
783                                const struct dpll *calculated_clock,
784                                const struct dpll *best_clock,
785                                unsigned int best_error_ppm,
786                                unsigned int *error_ppm)
787 {
788         /*
789          * For CHV ignore the error and consider only the P value.
790          * Prefer a bigger P value based on HW requirements.
791          */
792         if (IS_CHERRYVIEW(to_i915(dev))) {
793                 *error_ppm = 0;
794
795                 return calculated_clock->p > best_clock->p;
796         }
797
798         if (WARN_ON_ONCE(!target_freq))
799                 return false;
800
801         *error_ppm = div_u64(1000000ULL *
802                                 abs(target_freq - calculated_clock->dot),
803                              target_freq);
804         /*
805          * Prefer a better P value over a better (smaller) error if the error
806          * is small. Ensure this preference for future configurations too by
807          * setting the error to 0.
808          */
809         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
810                 *error_ppm = 0;
811
812                 return true;
813         }
814
815         return *error_ppm + 10 < best_error_ppm;
816 }
817
818 /*
819  * Returns a set of divisors for the desired target clock with the given
820  * refclk, or FALSE.  The returned values represent the clock equation:
821  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
822  */
823 static bool
824 vlv_find_best_dpll(const struct intel_limit *limit,
825                    struct intel_crtc_state *crtc_state,
826                    int target, int refclk, struct dpll *match_clock,
827                    struct dpll *best_clock)
828 {
829         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
830         struct drm_device *dev = crtc->base.dev;
831         struct dpll clock;
832         unsigned int bestppm = 1000000;
833         /* min update 19.2 MHz */
834         int max_n = min(limit->n.max, refclk / 19200);
835         bool found = false;
836
837         target *= 5; /* fast clock */
838
839         memset(best_clock, 0, sizeof(*best_clock));
840
841         /* based on hardware requirement, prefer smaller n to precision */
842         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
843                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
844                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
845                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
846                                 clock.p = clock.p1 * clock.p2;
847                                 /* based on hardware requirement, prefer bigger m1,m2 values */
848                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
849                                         unsigned int ppm;
850
851                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
852                                                                      refclk * clock.m1);
853
854                                         vlv_calc_dpll_params(refclk, &clock);
855
856                                         if (!intel_PLL_is_valid(to_i915(dev),
857                                                                 limit,
858                                                                 &clock))
859                                                 continue;
860
861                                         if (!vlv_PLL_is_optimal(dev, target,
862                                                                 &clock,
863                                                                 best_clock,
864                                                                 bestppm, &ppm))
865                                                 continue;
866
867                                         *best_clock = clock;
868                                         bestppm = ppm;
869                                         found = true;
870                                 }
871                         }
872                 }
873         }
874
875         return found;
876 }
877
878 /*
879  * Returns a set of divisors for the desired target clock with the given
880  * refclk, or FALSE.  The returned values represent the clock equation:
881  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
882  */
883 static bool
884 chv_find_best_dpll(const struct intel_limit *limit,
885                    struct intel_crtc_state *crtc_state,
886                    int target, int refclk, struct dpll *match_clock,
887                    struct dpll *best_clock)
888 {
889         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
890         struct drm_device *dev = crtc->base.dev;
891         unsigned int best_error_ppm;
892         struct dpll clock;
893         uint64_t m2;
894         int found = false;
895
896         memset(best_clock, 0, sizeof(*best_clock));
897         best_error_ppm = 1000000;
898
899         /*
900          * Based on hardware doc, the n always set to 1, and m1 always
901          * set to 2.  If requires to support 200Mhz refclk, we need to
902          * revisit this because n may not 1 anymore.
903          */
904         clock.n = 1, clock.m1 = 2;
905         target *= 5;    /* fast clock */
906
907         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
908                 for (clock.p2 = limit->p2.p2_fast;
909                                 clock.p2 >= limit->p2.p2_slow;
910                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
911                         unsigned int error_ppm;
912
913                         clock.p = clock.p1 * clock.p2;
914
915                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
916                                         clock.n) << 22, refclk * clock.m1);
917
918                         if (m2 > INT_MAX/clock.m1)
919                                 continue;
920
921                         clock.m2 = m2;
922
923                         chv_calc_dpll_params(refclk, &clock);
924
925                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
926                                 continue;
927
928                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
929                                                 best_error_ppm, &error_ppm))
930                                 continue;
931
932                         *best_clock = clock;
933                         best_error_ppm = error_ppm;
934                         found = true;
935                 }
936         }
937
938         return found;
939 }
940
941 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
942                         struct dpll *best_clock)
943 {
944         int refclk = 100000;
945         const struct intel_limit *limit = &intel_limits_bxt;
946
947         return chv_find_best_dpll(limit, crtc_state,
948                                   target_clock, refclk, NULL, best_clock);
949 }
950
951 bool intel_crtc_active(struct intel_crtc *crtc)
952 {
953         /* Be paranoid as we can arrive here with only partial
954          * state retrieved from the hardware during setup.
955          *
956          * We can ditch the adjusted_mode.crtc_clock check as soon
957          * as Haswell has gained clock readout/fastboot support.
958          *
959          * We can ditch the crtc->primary->fb check as soon as we can
960          * properly reconstruct framebuffers.
961          *
962          * FIXME: The intel_crtc->active here should be switched to
963          * crtc->state->active once we have proper CRTC states wired up
964          * for atomic.
965          */
966         return crtc->active && crtc->base.primary->state->fb &&
967                 crtc->config->base.adjusted_mode.crtc_clock;
968 }
969
970 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
971                                              enum pipe pipe)
972 {
973         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
974
975         return crtc->config->cpu_transcoder;
976 }
977
978 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
979 {
980         i915_reg_t reg = PIPEDSL(pipe);
981         u32 line1, line2;
982         u32 line_mask;
983
984         if (IS_GEN2(dev_priv))
985                 line_mask = DSL_LINEMASK_GEN2;
986         else
987                 line_mask = DSL_LINEMASK_GEN3;
988
989         line1 = I915_READ(reg) & line_mask;
990         msleep(5);
991         line2 = I915_READ(reg) & line_mask;
992
993         return line1 == line2;
994 }
995
996 /*
997  * intel_wait_for_pipe_off - wait for pipe to turn off
998  * @crtc: crtc whose pipe to wait for
999  *
1000  * After disabling a pipe, we can't wait for vblank in the usual way,
1001  * spinning on the vblank interrupt status bit, since we won't actually
1002  * see an interrupt when the pipe is disabled.
1003  *
1004  * On Gen4 and above:
1005  *   wait for the pipe register state bit to turn off
1006  *
1007  * Otherwise:
1008  *   wait for the display line value to settle (it usually
1009  *   ends up stopping at the start of the next frame).
1010  *
1011  */
1012 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1013 {
1014         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1015         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1016         enum pipe pipe = crtc->pipe;
1017
1018         if (INTEL_GEN(dev_priv) >= 4) {
1019                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1020
1021                 /* Wait for the Pipe State to go off */
1022                 if (intel_wait_for_register(dev_priv,
1023                                             reg, I965_PIPECONF_ACTIVE, 0,
1024                                             100))
1025                         WARN(1, "pipe_off wait timed out\n");
1026         } else {
1027                 /* Wait for the display line to settle */
1028                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1029                         WARN(1, "pipe_off wait timed out\n");
1030         }
1031 }
1032
1033 /* Only for pre-ILK configs */
1034 void assert_pll(struct drm_i915_private *dev_priv,
1035                 enum pipe pipe, bool state)
1036 {
1037         u32 val;
1038         bool cur_state;
1039
1040         val = I915_READ(DPLL(pipe));
1041         cur_state = !!(val & DPLL_VCO_ENABLE);
1042         I915_STATE_WARN(cur_state != state,
1043              "PLL state assertion failure (expected %s, current %s)\n",
1044                         onoff(state), onoff(cur_state));
1045 }
1046
1047 /* XXX: the dsi pll is shared between MIPI DSI ports */
1048 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1049 {
1050         u32 val;
1051         bool cur_state;
1052
1053         mutex_lock(&dev_priv->sb_lock);
1054         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1055         mutex_unlock(&dev_priv->sb_lock);
1056
1057         cur_state = val & DSI_PLL_VCO_EN;
1058         I915_STATE_WARN(cur_state != state,
1059              "DSI PLL state assertion failure (expected %s, current %s)\n",
1060                         onoff(state), onoff(cur_state));
1061 }
1062
1063 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1064                           enum pipe pipe, bool state)
1065 {
1066         bool cur_state;
1067         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1068                                                                       pipe);
1069
1070         if (HAS_DDI(dev_priv)) {
1071                 /* DDI does not have a specific FDI_TX register */
1072                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1073                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1074         } else {
1075                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1076                 cur_state = !!(val & FDI_TX_ENABLE);
1077         }
1078         I915_STATE_WARN(cur_state != state,
1079              "FDI TX state assertion failure (expected %s, current %s)\n",
1080                         onoff(state), onoff(cur_state));
1081 }
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1084
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086                           enum pipe pipe, bool state)
1087 {
1088         u32 val;
1089         bool cur_state;
1090
1091         val = I915_READ(FDI_RX_CTL(pipe));
1092         cur_state = !!(val & FDI_RX_ENABLE);
1093         I915_STATE_WARN(cur_state != state,
1094              "FDI RX state assertion failure (expected %s, current %s)\n",
1095                         onoff(state), onoff(cur_state));
1096 }
1097 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1098 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1099
1100 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1101                                       enum pipe pipe)
1102 {
1103         u32 val;
1104
1105         /* ILK FDI PLL is always enabled */
1106         if (IS_GEN5(dev_priv))
1107                 return;
1108
1109         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1110         if (HAS_DDI(dev_priv))
1111                 return;
1112
1113         val = I915_READ(FDI_TX_CTL(pipe));
1114         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1115 }
1116
1117 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1118                        enum pipe pipe, bool state)
1119 {
1120         u32 val;
1121         bool cur_state;
1122
1123         val = I915_READ(FDI_RX_CTL(pipe));
1124         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1125         I915_STATE_WARN(cur_state != state,
1126              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1127                         onoff(state), onoff(cur_state));
1128 }
1129
1130 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1131 {
1132         i915_reg_t pp_reg;
1133         u32 val;
1134         enum pipe panel_pipe = PIPE_A;
1135         bool locked = true;
1136
1137         if (WARN_ON(HAS_DDI(dev_priv)))
1138                 return;
1139
1140         if (HAS_PCH_SPLIT(dev_priv)) {
1141                 u32 port_sel;
1142
1143                 pp_reg = PP_CONTROL(0);
1144                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1145
1146                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1147                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1148                         panel_pipe = PIPE_B;
1149                 /* XXX: else fix for eDP */
1150         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1151                 /* presumably write lock depends on pipe, not port select */
1152                 pp_reg = PP_CONTROL(pipe);
1153                 panel_pipe = pipe;
1154         } else {
1155                 pp_reg = PP_CONTROL(0);
1156                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1157                         panel_pipe = PIPE_B;
1158         }
1159
1160         val = I915_READ(pp_reg);
1161         if (!(val & PANEL_POWER_ON) ||
1162             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1163                 locked = false;
1164
1165         I915_STATE_WARN(panel_pipe == pipe && locked,
1166              "panel assertion failure, pipe %c regs locked\n",
1167              pipe_name(pipe));
1168 }
1169
1170 static void assert_cursor(struct drm_i915_private *dev_priv,
1171                           enum pipe pipe, bool state)
1172 {
1173         bool cur_state;
1174
1175         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1176                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1177         else
1178                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1179
1180         I915_STATE_WARN(cur_state != state,
1181              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1182                         pipe_name(pipe), onoff(state), onoff(cur_state));
1183 }
1184 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1185 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1186
1187 void assert_pipe(struct drm_i915_private *dev_priv,
1188                  enum pipe pipe, bool state)
1189 {
1190         bool cur_state;
1191         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192                                                                       pipe);
1193         enum intel_display_power_domain power_domain;
1194
1195         /* if we need the pipe quirk it must be always on */
1196         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1197             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1198                 state = true;
1199
1200         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203                 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205                 intel_display_power_put(dev_priv, power_domain);
1206         } else {
1207                 cur_state = false;
1208         }
1209
1210         I915_STATE_WARN(cur_state != state,
1211              "pipe %c assertion failure (expected %s, current %s)\n",
1212                         pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216                          enum plane plane, bool state)
1217 {
1218         u32 val;
1219         bool cur_state;
1220
1221         val = I915_READ(DSPCNTR(plane));
1222         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223         I915_STATE_WARN(cur_state != state,
1224              "plane %c assertion failure (expected %s, current %s)\n",
1225                         plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232                                    enum pipe pipe)
1233 {
1234         int i;
1235
1236         /* Primary planes are fixed to pipes on gen4+ */
1237         if (INTEL_GEN(dev_priv) >= 4) {
1238                 u32 val = I915_READ(DSPCNTR(pipe));
1239                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240                      "plane %c assertion failure, should be disabled but not\n",
1241                      plane_name(pipe));
1242                 return;
1243         }
1244
1245         /* Need to check both planes against the pipe */
1246         for_each_pipe(dev_priv, i) {
1247                 u32 val = I915_READ(DSPCNTR(i));
1248                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249                         DISPPLANE_SEL_PIPE_SHIFT;
1250                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252                      plane_name(i), pipe_name(pipe));
1253         }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257                                     enum pipe pipe)
1258 {
1259         int sprite;
1260
1261         if (INTEL_GEN(dev_priv) >= 9) {
1262                 for_each_sprite(dev_priv, pipe, sprite) {
1263                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266                              sprite, pipe_name(pipe));
1267                 }
1268         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269                 for_each_sprite(dev_priv, pipe, sprite) {
1270                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271                         I915_STATE_WARN(val & SP_ENABLE,
1272                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273                              sprite_name(pipe, sprite), pipe_name(pipe));
1274                 }
1275         } else if (INTEL_GEN(dev_priv) >= 7) {
1276                 u32 val = I915_READ(SPRCTL(pipe));
1277                 I915_STATE_WARN(val & SPRITE_ENABLE,
1278                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279                      plane_name(pipe), pipe_name(pipe));
1280         } else if (INTEL_GEN(dev_priv) >= 5) {
1281                 u32 val = I915_READ(DVSCNTR(pipe));
1282                 I915_STATE_WARN(val & DVS_ENABLE,
1283                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284                      plane_name(pipe), pipe_name(pipe));
1285         }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291                 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295                                     enum pipe pipe)
1296 {
1297         u32 val;
1298         bool enabled;
1299
1300         val = I915_READ(PCH_TRANSCONF(pipe));
1301         enabled = !!(val & TRANS_ENABLE);
1302         I915_STATE_WARN(enabled,
1303              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304              pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308                             enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310         if ((val & DP_PORT_EN) == 0)
1311                 return false;
1312
1313         if (HAS_PCH_CPT(dev_priv)) {
1314                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else if (IS_CHERRYVIEW(dev_priv)) {
1318                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319                         return false;
1320         } else {
1321                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322                         return false;
1323         }
1324         return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328                               enum pipe pipe, u32 val)
1329 {
1330         if ((val & SDVO_ENABLE) == 0)
1331                 return false;
1332
1333         if (HAS_PCH_CPT(dev_priv)) {
1334                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335                         return false;
1336         } else if (IS_CHERRYVIEW(dev_priv)) {
1337                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338                         return false;
1339         } else {
1340                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341                         return false;
1342         }
1343         return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347                               enum pipe pipe, u32 val)
1348 {
1349         if ((val & LVDS_PORT_EN) == 0)
1350                 return false;
1351
1352         if (HAS_PCH_CPT(dev_priv)) {
1353                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354                         return false;
1355         } else {
1356                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357                         return false;
1358         }
1359         return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363                               enum pipe pipe, u32 val)
1364 {
1365         if ((val & ADPA_DAC_ENABLE) == 0)
1366                 return false;
1367         if (HAS_PCH_CPT(dev_priv)) {
1368                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369                         return false;
1370         } else {
1371                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372                         return false;
1373         }
1374         return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378                                    enum pipe pipe, i915_reg_t reg,
1379                                    u32 port_sel)
1380 {
1381         u32 val = I915_READ(reg);
1382         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384              i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387              && (val & DP_PIPEB_SELECT),
1388              "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392                                      enum pipe pipe, i915_reg_t reg)
1393 {
1394         u32 val = I915_READ(reg);
1395         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397              i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400              && (val & SDVO_PIPE_B_SELECT),
1401              "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405                                       enum pipe pipe)
1406 {
1407         u32 val;
1408
1409         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413         val = I915_READ(PCH_ADPA);
1414         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415              "PCH VGA enabled on transcoder %c, should be disabled\n",
1416              pipe_name(pipe));
1417
1418         val = I915_READ(PCH_LVDS);
1419         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421              pipe_name(pipe));
1422
1423         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429                             const struct intel_crtc_state *pipe_config)
1430 {
1431         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432         enum pipe pipe = crtc->pipe;
1433
1434         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435         POSTING_READ(DPLL(pipe));
1436         udelay(150);
1437
1438         if (intel_wait_for_register(dev_priv,
1439                                     DPLL(pipe),
1440                                     DPLL_LOCK_VLV,
1441                                     DPLL_LOCK_VLV,
1442                                     1))
1443                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447                            const struct intel_crtc_state *pipe_config)
1448 {
1449         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450         enum pipe pipe = crtc->pipe;
1451
1452         assert_pipe_disabled(dev_priv, pipe);
1453
1454         /* PLL is protected by panel, make sure we can write it */
1455         assert_panel_unlocked(dev_priv, pipe);
1456
1457         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458                 _vlv_enable_pll(crtc, pipe_config);
1459
1460         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461         POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466                             const struct intel_crtc_state *pipe_config)
1467 {
1468         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469         enum pipe pipe = crtc->pipe;
1470         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471         u32 tmp;
1472
1473         mutex_lock(&dev_priv->sb_lock);
1474
1475         /* Enable back the 10bit clock to display controller */
1476         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477         tmp |= DPIO_DCLKP_EN;
1478         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480         mutex_unlock(&dev_priv->sb_lock);
1481
1482         /*
1483          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484          */
1485         udelay(1);
1486
1487         /* Enable PLL */
1488         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490         /* Check PLL is locked */
1491         if (intel_wait_for_register(dev_priv,
1492                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493                                     1))
1494                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498                            const struct intel_crtc_state *pipe_config)
1499 {
1500         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501         enum pipe pipe = crtc->pipe;
1502
1503         assert_pipe_disabled(dev_priv, pipe);
1504
1505         /* PLL is protected by panel, make sure we can write it */
1506         assert_panel_unlocked(dev_priv, pipe);
1507
1508         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509                 _chv_enable_pll(crtc, pipe_config);
1510
1511         if (pipe != PIPE_A) {
1512                 /*
1513                  * WaPixelRepeatModeFixForC0:chv
1514                  *
1515                  * DPLLCMD is AWOL. Use chicken bits to propagate
1516                  * the value from DPLLBMD to either pipe B or C.
1517                  */
1518                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520                 I915_WRITE(CBR4_VLV, 0);
1521                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523                 /*
1524                  * DPLLB VGA mode also seems to cause problems.
1525                  * We should always have it disabled.
1526                  */
1527                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528         } else {
1529                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530                 POSTING_READ(DPLL_MD(pipe));
1531         }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536         struct intel_crtc *crtc;
1537         int count = 0;
1538
1539         for_each_intel_crtc(&dev_priv->drm, crtc) {
1540                 count += crtc->base.state->active &&
1541                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542         }
1543
1544         return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550         i915_reg_t reg = DPLL(crtc->pipe);
1551         u32 dpll = crtc->config->dpll_hw_state.dpll;
1552
1553         assert_pipe_disabled(dev_priv, crtc->pipe);
1554
1555         /* PLL is protected by panel, make sure we can write it */
1556         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1557                 assert_panel_unlocked(dev_priv, crtc->pipe);
1558
1559         /* Enable DVO 2x clock on both PLLs if necessary */
1560         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1561                 /*
1562                  * It appears to be important that we don't enable this
1563                  * for the current pipe before otherwise configuring the
1564                  * PLL. No idea how this should be handled if multiple
1565                  * DVO outputs are enabled simultaneosly.
1566                  */
1567                 dpll |= DPLL_DVO_2X_MODE;
1568                 I915_WRITE(DPLL(!crtc->pipe),
1569                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1570         }
1571
1572         /*
1573          * Apparently we need to have VGA mode enabled prior to changing
1574          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1575          * dividers, even though the register value does change.
1576          */
1577         I915_WRITE(reg, 0);
1578
1579         I915_WRITE(reg, dpll);
1580
1581         /* Wait for the clocks to stabilize. */
1582         POSTING_READ(reg);
1583         udelay(150);
1584
1585         if (INTEL_GEN(dev_priv) >= 4) {
1586                 I915_WRITE(DPLL_MD(crtc->pipe),
1587                            crtc->config->dpll_hw_state.dpll_md);
1588         } else {
1589                 /* The pixel multiplier can only be updated once the
1590                  * DPLL is enabled and the clocks are stable.
1591                  *
1592                  * So write it again.
1593                  */
1594                 I915_WRITE(reg, dpll);
1595         }
1596
1597         /* We do this three times for luck */
1598         I915_WRITE(reg, dpll);
1599         POSTING_READ(reg);
1600         udelay(150); /* wait for warmup */
1601         I915_WRITE(reg, dpll);
1602         POSTING_READ(reg);
1603         udelay(150); /* wait for warmup */
1604         I915_WRITE(reg, dpll);
1605         POSTING_READ(reg);
1606         udelay(150); /* wait for warmup */
1607 }
1608
1609 /**
1610  * i9xx_disable_pll - disable a PLL
1611  * @dev_priv: i915 private structure
1612  * @pipe: pipe PLL to disable
1613  *
1614  * Disable the PLL for @pipe, making sure the pipe is off first.
1615  *
1616  * Note!  This is for pre-ILK only.
1617  */
1618 static void i9xx_disable_pll(struct intel_crtc *crtc)
1619 {
1620         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1621         enum pipe pipe = crtc->pipe;
1622
1623         /* Disable DVO 2x clock on both PLLs if necessary */
1624         if (IS_I830(dev_priv) &&
1625             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1626             !intel_num_dvo_pipes(dev_priv)) {
1627                 I915_WRITE(DPLL(PIPE_B),
1628                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1629                 I915_WRITE(DPLL(PIPE_A),
1630                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1631         }
1632
1633         /* Don't disable pipe or pipe PLLs if needed */
1634         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1635             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1636                 return;
1637
1638         /* Make sure the pipe isn't still relying on us */
1639         assert_pipe_disabled(dev_priv, pipe);
1640
1641         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1642         POSTING_READ(DPLL(pipe));
1643 }
1644
1645 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1646 {
1647         u32 val;
1648
1649         /* Make sure the pipe isn't still relying on us */
1650         assert_pipe_disabled(dev_priv, pipe);
1651
1652         val = DPLL_INTEGRATED_REF_CLK_VLV |
1653                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1654         if (pipe != PIPE_A)
1655                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1656
1657         I915_WRITE(DPLL(pipe), val);
1658         POSTING_READ(DPLL(pipe));
1659 }
1660
1661 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1662 {
1663         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1664         u32 val;
1665
1666         /* Make sure the pipe isn't still relying on us */
1667         assert_pipe_disabled(dev_priv, pipe);
1668
1669         val = DPLL_SSC_REF_CLK_CHV |
1670                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1671         if (pipe != PIPE_A)
1672                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1673
1674         I915_WRITE(DPLL(pipe), val);
1675         POSTING_READ(DPLL(pipe));
1676
1677         mutex_lock(&dev_priv->sb_lock);
1678
1679         /* Disable 10bit clock to display controller */
1680         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1681         val &= ~DPIO_DCLKP_EN;
1682         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1683
1684         mutex_unlock(&dev_priv->sb_lock);
1685 }
1686
1687 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1688                          struct intel_digital_port *dport,
1689                          unsigned int expected_mask)
1690 {
1691         u32 port_mask;
1692         i915_reg_t dpll_reg;
1693
1694         switch (dport->port) {
1695         case PORT_B:
1696                 port_mask = DPLL_PORTB_READY_MASK;
1697                 dpll_reg = DPLL(0);
1698                 break;
1699         case PORT_C:
1700                 port_mask = DPLL_PORTC_READY_MASK;
1701                 dpll_reg = DPLL(0);
1702                 expected_mask <<= 4;
1703                 break;
1704         case PORT_D:
1705                 port_mask = DPLL_PORTD_READY_MASK;
1706                 dpll_reg = DPIO_PHY_STATUS;
1707                 break;
1708         default:
1709                 BUG();
1710         }
1711
1712         if (intel_wait_for_register(dev_priv,
1713                                     dpll_reg, port_mask, expected_mask,
1714                                     1000))
1715                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1716                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1717 }
1718
1719 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1720                                            enum pipe pipe)
1721 {
1722         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1723                                                                 pipe);
1724         i915_reg_t reg;
1725         uint32_t val, pipeconf_val;
1726
1727         /* Make sure PCH DPLL is enabled */
1728         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1729
1730         /* FDI must be feeding us bits for PCH ports */
1731         assert_fdi_tx_enabled(dev_priv, pipe);
1732         assert_fdi_rx_enabled(dev_priv, pipe);
1733
1734         if (HAS_PCH_CPT(dev_priv)) {
1735                 /* Workaround: Set the timing override bit before enabling the
1736                  * pch transcoder. */
1737                 reg = TRANS_CHICKEN2(pipe);
1738                 val = I915_READ(reg);
1739                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1740                 I915_WRITE(reg, val);
1741         }
1742
1743         reg = PCH_TRANSCONF(pipe);
1744         val = I915_READ(reg);
1745         pipeconf_val = I915_READ(PIPECONF(pipe));
1746
1747         if (HAS_PCH_IBX(dev_priv)) {
1748                 /*
1749                  * Make the BPC in transcoder be consistent with
1750                  * that in pipeconf reg. For HDMI we must use 8bpc
1751                  * here for both 8bpc and 12bpc.
1752                  */
1753                 val &= ~PIPECONF_BPC_MASK;
1754                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1755                         val |= PIPECONF_8BPC;
1756                 else
1757                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1758         }
1759
1760         val &= ~TRANS_INTERLACE_MASK;
1761         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1762                 if (HAS_PCH_IBX(dev_priv) &&
1763                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1764                         val |= TRANS_LEGACY_INTERLACED_ILK;
1765                 else
1766                         val |= TRANS_INTERLACED;
1767         else
1768                 val |= TRANS_PROGRESSIVE;
1769
1770         I915_WRITE(reg, val | TRANS_ENABLE);
1771         if (intel_wait_for_register(dev_priv,
1772                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1773                                     100))
1774                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1775 }
1776
1777 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1778                                       enum transcoder cpu_transcoder)
1779 {
1780         u32 val, pipeconf_val;
1781
1782         /* FDI must be feeding us bits for PCH ports */
1783         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1784         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1785
1786         /* Workaround: set timing override bit. */
1787         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1788         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1789         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1790
1791         val = TRANS_ENABLE;
1792         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1793
1794         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1795             PIPECONF_INTERLACED_ILK)
1796                 val |= TRANS_INTERLACED;
1797         else
1798                 val |= TRANS_PROGRESSIVE;
1799
1800         I915_WRITE(LPT_TRANSCONF, val);
1801         if (intel_wait_for_register(dev_priv,
1802                                     LPT_TRANSCONF,
1803                                     TRANS_STATE_ENABLE,
1804                                     TRANS_STATE_ENABLE,
1805                                     100))
1806                 DRM_ERROR("Failed to enable PCH transcoder\n");
1807 }
1808
1809 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1810                                             enum pipe pipe)
1811 {
1812         i915_reg_t reg;
1813         uint32_t val;
1814
1815         /* FDI relies on the transcoder */
1816         assert_fdi_tx_disabled(dev_priv, pipe);
1817         assert_fdi_rx_disabled(dev_priv, pipe);
1818
1819         /* Ports must be off as well */
1820         assert_pch_ports_disabled(dev_priv, pipe);
1821
1822         reg = PCH_TRANSCONF(pipe);
1823         val = I915_READ(reg);
1824         val &= ~TRANS_ENABLE;
1825         I915_WRITE(reg, val);
1826         /* wait for PCH transcoder off, transcoder state */
1827         if (intel_wait_for_register(dev_priv,
1828                                     reg, TRANS_STATE_ENABLE, 0,
1829                                     50))
1830                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1831
1832         if (HAS_PCH_CPT(dev_priv)) {
1833                 /* Workaround: Clear the timing override chicken bit again. */
1834                 reg = TRANS_CHICKEN2(pipe);
1835                 val = I915_READ(reg);
1836                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1837                 I915_WRITE(reg, val);
1838         }
1839 }
1840
1841 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1842 {
1843         u32 val;
1844
1845         val = I915_READ(LPT_TRANSCONF);
1846         val &= ~TRANS_ENABLE;
1847         I915_WRITE(LPT_TRANSCONF, val);
1848         /* wait for PCH transcoder off, transcoder state */
1849         if (intel_wait_for_register(dev_priv,
1850                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1851                                     50))
1852                 DRM_ERROR("Failed to disable PCH transcoder\n");
1853
1854         /* Workaround: clear timing override bit. */
1855         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1857         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858 }
1859
1860 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1861 {
1862         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1863
1864         WARN_ON(!crtc->config->has_pch_encoder);
1865
1866         if (HAS_PCH_LPT(dev_priv))
1867                 return TRANSCODER_A;
1868         else
1869                 return (enum transcoder) crtc->pipe;
1870 }
1871
1872 /**
1873  * intel_enable_pipe - enable a pipe, asserting requirements
1874  * @crtc: crtc responsible for the pipe
1875  *
1876  * Enable @crtc's pipe, making sure that various hardware specific requirements
1877  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1878  */
1879 static void intel_enable_pipe(struct intel_crtc *crtc)
1880 {
1881         struct drm_device *dev = crtc->base.dev;
1882         struct drm_i915_private *dev_priv = to_i915(dev);
1883         enum pipe pipe = crtc->pipe;
1884         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1885         i915_reg_t reg;
1886         u32 val;
1887
1888         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1889
1890         assert_planes_disabled(dev_priv, pipe);
1891         assert_cursor_disabled(dev_priv, pipe);
1892         assert_sprites_disabled(dev_priv, pipe);
1893
1894         /*
1895          * A pipe without a PLL won't actually be able to drive bits from
1896          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1897          * need the check.
1898          */
1899         if (HAS_GMCH_DISPLAY(dev_priv)) {
1900                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1901                         assert_dsi_pll_enabled(dev_priv);
1902                 else
1903                         assert_pll_enabled(dev_priv, pipe);
1904         } else {
1905                 if (crtc->config->has_pch_encoder) {
1906                         /* if driving the PCH, we need FDI enabled */
1907                         assert_fdi_rx_pll_enabled(dev_priv,
1908                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1909                         assert_fdi_tx_pll_enabled(dev_priv,
1910                                                   (enum pipe) cpu_transcoder);
1911                 }
1912                 /* FIXME: assert CPU port conditions for SNB+ */
1913         }
1914
1915         reg = PIPECONF(cpu_transcoder);
1916         val = I915_READ(reg);
1917         if (val & PIPECONF_ENABLE) {
1918                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1919                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1920                 return;
1921         }
1922
1923         I915_WRITE(reg, val | PIPECONF_ENABLE);
1924         POSTING_READ(reg);
1925
1926         /*
1927          * Until the pipe starts DSL will read as 0, which would cause
1928          * an apparent vblank timestamp jump, which messes up also the
1929          * frame count when it's derived from the timestamps. So let's
1930          * wait for the pipe to start properly before we call
1931          * drm_crtc_vblank_on()
1932          */
1933         if (dev->max_vblank_count == 0 &&
1934             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1935                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1936 }
1937
1938 /**
1939  * intel_disable_pipe - disable a pipe, asserting requirements
1940  * @crtc: crtc whose pipes is to be disabled
1941  *
1942  * Disable the pipe of @crtc, making sure that various hardware
1943  * specific requirements are met, if applicable, e.g. plane
1944  * disabled, panel fitter off, etc.
1945  *
1946  * Will wait until the pipe has shut down before returning.
1947  */
1948 static void intel_disable_pipe(struct intel_crtc *crtc)
1949 {
1950         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1951         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1952         enum pipe pipe = crtc->pipe;
1953         i915_reg_t reg;
1954         u32 val;
1955
1956         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1957
1958         /*
1959          * Make sure planes won't keep trying to pump pixels to us,
1960          * or we might hang the display.
1961          */
1962         assert_planes_disabled(dev_priv, pipe);
1963         assert_cursor_disabled(dev_priv, pipe);
1964         assert_sprites_disabled(dev_priv, pipe);
1965
1966         reg = PIPECONF(cpu_transcoder);
1967         val = I915_READ(reg);
1968         if ((val & PIPECONF_ENABLE) == 0)
1969                 return;
1970
1971         /*
1972          * Double wide has implications for planes
1973          * so best keep it disabled when not needed.
1974          */
1975         if (crtc->config->double_wide)
1976                 val &= ~PIPECONF_DOUBLE_WIDE;
1977
1978         /* Don't disable pipe or pipe PLLs if needed */
1979         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
1980             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1981                 val &= ~PIPECONF_ENABLE;
1982
1983         I915_WRITE(reg, val);
1984         if ((val & PIPECONF_ENABLE) == 0)
1985                 intel_wait_for_pipe_off(crtc);
1986 }
1987
1988 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1989 {
1990         return IS_GEN2(dev_priv) ? 2048 : 4096;
1991 }
1992
1993 static unsigned int
1994 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1995 {
1996         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1997         unsigned int cpp = fb->format->cpp[plane];
1998
1999         switch (fb->modifier) {
2000         case DRM_FORMAT_MOD_LINEAR:
2001                 return cpp;
2002         case I915_FORMAT_MOD_X_TILED:
2003                 if (IS_GEN2(dev_priv))
2004                         return 128;
2005                 else
2006                         return 512;
2007         case I915_FORMAT_MOD_Y_TILED:
2008                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2009                         return 128;
2010                 else
2011                         return 512;
2012         case I915_FORMAT_MOD_Yf_TILED:
2013                 switch (cpp) {
2014                 case 1:
2015                         return 64;
2016                 case 2:
2017                 case 4:
2018                         return 128;
2019                 case 8:
2020                 case 16:
2021                         return 256;
2022                 default:
2023                         MISSING_CASE(cpp);
2024                         return cpp;
2025                 }
2026                 break;
2027         default:
2028                 MISSING_CASE(fb->modifier);
2029                 return cpp;
2030         }
2031 }
2032
2033 static unsigned int
2034 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2035 {
2036         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2037                 return 1;
2038         else
2039                 return intel_tile_size(to_i915(fb->dev)) /
2040                         intel_tile_width_bytes(fb, plane);
2041 }
2042
2043 /* Return the tile dimensions in pixel units */
2044 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2045                             unsigned int *tile_width,
2046                             unsigned int *tile_height)
2047 {
2048         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2049         unsigned int cpp = fb->format->cpp[plane];
2050
2051         *tile_width = tile_width_bytes / cpp;
2052         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2053 }
2054
2055 unsigned int
2056 intel_fb_align_height(const struct drm_framebuffer *fb,
2057                       int plane, unsigned int height)
2058 {
2059         unsigned int tile_height = intel_tile_height(fb, plane);
2060
2061         return ALIGN(height, tile_height);
2062 }
2063
2064 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2065 {
2066         unsigned int size = 0;
2067         int i;
2068
2069         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2070                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2071
2072         return size;
2073 }
2074
2075 static void
2076 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2077                         const struct drm_framebuffer *fb,
2078                         unsigned int rotation)
2079 {
2080         view->type = I915_GGTT_VIEW_NORMAL;
2081         if (drm_rotation_90_or_270(rotation)) {
2082                 view->type = I915_GGTT_VIEW_ROTATED;
2083                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2084         }
2085 }
2086
2087 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2088 {
2089         if (INTEL_INFO(dev_priv)->gen >= 9)
2090                 return 256 * 1024;
2091         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2092                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2093                 return 128 * 1024;
2094         else if (INTEL_INFO(dev_priv)->gen >= 4)
2095                 return 4 * 1024;
2096         else
2097                 return 0;
2098 }
2099
2100 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2101                                          int plane)
2102 {
2103         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2104
2105         /* AUX_DIST needs only 4K alignment */
2106         if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2107                 return 4096;
2108
2109         switch (fb->modifier) {
2110         case DRM_FORMAT_MOD_LINEAR:
2111                 return intel_linear_alignment(dev_priv);
2112         case I915_FORMAT_MOD_X_TILED:
2113                 if (INTEL_GEN(dev_priv) >= 9)
2114                         return 256 * 1024;
2115                 return 0;
2116         case I915_FORMAT_MOD_Y_TILED:
2117         case I915_FORMAT_MOD_Yf_TILED:
2118                 return 1 * 1024 * 1024;
2119         default:
2120                 MISSING_CASE(fb->modifier);
2121                 return 0;
2122         }
2123 }
2124
2125 struct i915_vma *
2126 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2127 {
2128         struct drm_device *dev = fb->dev;
2129         struct drm_i915_private *dev_priv = to_i915(dev);
2130         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2131         struct i915_ggtt_view view;
2132         struct i915_vma *vma;
2133         u32 alignment;
2134
2135         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2136
2137         alignment = intel_surf_alignment(fb, 0);
2138
2139         intel_fill_fb_ggtt_view(&view, fb, rotation);
2140
2141         /* Note that the w/a also requires 64 PTE of padding following the
2142          * bo. We currently fill all unused PTE with the shadow page and so
2143          * we should always have valid PTE following the scanout preventing
2144          * the VT-d warning.
2145          */
2146         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2147                 alignment = 256 * 1024;
2148
2149         /*
2150          * Global gtt pte registers are special registers which actually forward
2151          * writes to a chunk of system memory. Which means that there is no risk
2152          * that the register values disappear as soon as we call
2153          * intel_runtime_pm_put(), so it is correct to wrap only the
2154          * pin/unpin/fence and not more.
2155          */
2156         intel_runtime_pm_get(dev_priv);
2157
2158         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2159         if (IS_ERR(vma))
2160                 goto err;
2161
2162         if (i915_vma_is_map_and_fenceable(vma)) {
2163                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2164                  * fence, whereas 965+ only requires a fence if using
2165                  * framebuffer compression.  For simplicity, we always, when
2166                  * possible, install a fence as the cost is not that onerous.
2167                  *
2168                  * If we fail to fence the tiled scanout, then either the
2169                  * modeset will reject the change (which is highly unlikely as
2170                  * the affected systems, all but one, do not have unmappable
2171                  * space) or we will not be able to enable full powersaving
2172                  * techniques (also likely not to apply due to various limits
2173                  * FBC and the like impose on the size of the buffer, which
2174                  * presumably we violated anyway with this unmappable buffer).
2175                  * Anyway, it is presumably better to stumble onwards with
2176                  * something and try to run the system in a "less than optimal"
2177                  * mode that matches the user configuration.
2178                  */
2179                 if (i915_vma_get_fence(vma) == 0)
2180                         i915_vma_pin_fence(vma);
2181         }
2182
2183         i915_vma_get(vma);
2184 err:
2185         intel_runtime_pm_put(dev_priv);
2186         return vma;
2187 }
2188
2189 void intel_unpin_fb_vma(struct i915_vma *vma)
2190 {
2191         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2192
2193         i915_vma_unpin_fence(vma);
2194         i915_gem_object_unpin_from_display_plane(vma);
2195         i915_vma_put(vma);
2196 }
2197
2198 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2199                           unsigned int rotation)
2200 {
2201         if (drm_rotation_90_or_270(rotation))
2202                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2203         else
2204                 return fb->pitches[plane];
2205 }
2206
2207 /*
2208  * Convert the x/y offsets into a linear offset.
2209  * Only valid with 0/180 degree rotation, which is fine since linear
2210  * offset is only used with linear buffers on pre-hsw and tiled buffers
2211  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2212  */
2213 u32 intel_fb_xy_to_linear(int x, int y,
2214                           const struct intel_plane_state *state,
2215                           int plane)
2216 {
2217         const struct drm_framebuffer *fb = state->base.fb;
2218         unsigned int cpp = fb->format->cpp[plane];
2219         unsigned int pitch = fb->pitches[plane];
2220
2221         return y * pitch + x * cpp;
2222 }
2223
2224 /*
2225  * Add the x/y offsets derived from fb->offsets[] to the user
2226  * specified plane src x/y offsets. The resulting x/y offsets
2227  * specify the start of scanout from the beginning of the gtt mapping.
2228  */
2229 void intel_add_fb_offsets(int *x, int *y,
2230                           const struct intel_plane_state *state,
2231                           int plane)
2232
2233 {
2234         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2235         unsigned int rotation = state->base.rotation;
2236
2237         if (drm_rotation_90_or_270(rotation)) {
2238                 *x += intel_fb->rotated[plane].x;
2239                 *y += intel_fb->rotated[plane].y;
2240         } else {
2241                 *x += intel_fb->normal[plane].x;
2242                 *y += intel_fb->normal[plane].y;
2243         }
2244 }
2245
2246 /*
2247  * Input tile dimensions and pitch must already be
2248  * rotated to match x and y, and in pixel units.
2249  */
2250 static u32 _intel_adjust_tile_offset(int *x, int *y,
2251                                      unsigned int tile_width,
2252                                      unsigned int tile_height,
2253                                      unsigned int tile_size,
2254                                      unsigned int pitch_tiles,
2255                                      u32 old_offset,
2256                                      u32 new_offset)
2257 {
2258         unsigned int pitch_pixels = pitch_tiles * tile_width;
2259         unsigned int tiles;
2260
2261         WARN_ON(old_offset & (tile_size - 1));
2262         WARN_ON(new_offset & (tile_size - 1));
2263         WARN_ON(new_offset > old_offset);
2264
2265         tiles = (old_offset - new_offset) / tile_size;
2266
2267         *y += tiles / pitch_tiles * tile_height;
2268         *x += tiles % pitch_tiles * tile_width;
2269
2270         /* minimize x in case it got needlessly big */
2271         *y += *x / pitch_pixels * tile_height;
2272         *x %= pitch_pixels;
2273
2274         return new_offset;
2275 }
2276
2277 /*
2278  * Adjust the tile offset by moving the difference into
2279  * the x/y offsets.
2280  */
2281 static u32 intel_adjust_tile_offset(int *x, int *y,
2282                                     const struct intel_plane_state *state, int plane,
2283                                     u32 old_offset, u32 new_offset)
2284 {
2285         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2286         const struct drm_framebuffer *fb = state->base.fb;
2287         unsigned int cpp = fb->format->cpp[plane];
2288         unsigned int rotation = state->base.rotation;
2289         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2290
2291         WARN_ON(new_offset > old_offset);
2292
2293         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2294                 unsigned int tile_size, tile_width, tile_height;
2295                 unsigned int pitch_tiles;
2296
2297                 tile_size = intel_tile_size(dev_priv);
2298                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2299
2300                 if (drm_rotation_90_or_270(rotation)) {
2301                         pitch_tiles = pitch / tile_height;
2302                         swap(tile_width, tile_height);
2303                 } else {
2304                         pitch_tiles = pitch / (tile_width * cpp);
2305                 }
2306
2307                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2308                                           tile_size, pitch_tiles,
2309                                           old_offset, new_offset);
2310         } else {
2311                 old_offset += *y * pitch + *x * cpp;
2312
2313                 *y = (old_offset - new_offset) / pitch;
2314                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2315         }
2316
2317         return new_offset;
2318 }
2319
2320 /*
2321  * Computes the linear offset to the base tile and adjusts
2322  * x, y. bytes per pixel is assumed to be a power-of-two.
2323  *
2324  * In the 90/270 rotated case, x and y are assumed
2325  * to be already rotated to match the rotated GTT view, and
2326  * pitch is the tile_height aligned framebuffer height.
2327  *
2328  * This function is used when computing the derived information
2329  * under intel_framebuffer, so using any of that information
2330  * here is not allowed. Anything under drm_framebuffer can be
2331  * used. This is why the user has to pass in the pitch since it
2332  * is specified in the rotated orientation.
2333  */
2334 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2335                                       int *x, int *y,
2336                                       const struct drm_framebuffer *fb, int plane,
2337                                       unsigned int pitch,
2338                                       unsigned int rotation,
2339                                       u32 alignment)
2340 {
2341         uint64_t fb_modifier = fb->modifier;
2342         unsigned int cpp = fb->format->cpp[plane];
2343         u32 offset, offset_aligned;
2344
2345         if (alignment)
2346                 alignment--;
2347
2348         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2349                 unsigned int tile_size, tile_width, tile_height;
2350                 unsigned int tile_rows, tiles, pitch_tiles;
2351
2352                 tile_size = intel_tile_size(dev_priv);
2353                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2354
2355                 if (drm_rotation_90_or_270(rotation)) {
2356                         pitch_tiles = pitch / tile_height;
2357                         swap(tile_width, tile_height);
2358                 } else {
2359                         pitch_tiles = pitch / (tile_width * cpp);
2360                 }
2361
2362                 tile_rows = *y / tile_height;
2363                 *y %= tile_height;
2364
2365                 tiles = *x / tile_width;
2366                 *x %= tile_width;
2367
2368                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2369                 offset_aligned = offset & ~alignment;
2370
2371                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2372                                           tile_size, pitch_tiles,
2373                                           offset, offset_aligned);
2374         } else {
2375                 offset = *y * pitch + *x * cpp;
2376                 offset_aligned = offset & ~alignment;
2377
2378                 *y = (offset & alignment) / pitch;
2379                 *x = ((offset & alignment) - *y * pitch) / cpp;
2380         }
2381
2382         return offset_aligned;
2383 }
2384
2385 u32 intel_compute_tile_offset(int *x, int *y,
2386                               const struct intel_plane_state *state,
2387                               int plane)
2388 {
2389         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2390         const struct drm_framebuffer *fb = state->base.fb;
2391         unsigned int rotation = state->base.rotation;
2392         int pitch = intel_fb_pitch(fb, plane, rotation);
2393         u32 alignment = intel_surf_alignment(fb, plane);
2394
2395         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2396                                           rotation, alignment);
2397 }
2398
2399 /* Convert the fb->offset[] linear offset into x/y offsets */
2400 static void intel_fb_offset_to_xy(int *x, int *y,
2401                                   const struct drm_framebuffer *fb, int plane)
2402 {
2403         unsigned int cpp = fb->format->cpp[plane];
2404         unsigned int pitch = fb->pitches[plane];
2405         u32 linear_offset = fb->offsets[plane];
2406
2407         *y = linear_offset / pitch;
2408         *x = linear_offset % pitch / cpp;
2409 }
2410
2411 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2412 {
2413         switch (fb_modifier) {
2414         case I915_FORMAT_MOD_X_TILED:
2415                 return I915_TILING_X;
2416         case I915_FORMAT_MOD_Y_TILED:
2417                 return I915_TILING_Y;
2418         default:
2419                 return I915_TILING_NONE;
2420         }
2421 }
2422
2423 static int
2424 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2425                    struct drm_framebuffer *fb)
2426 {
2427         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2428         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2429         u32 gtt_offset_rotated = 0;
2430         unsigned int max_size = 0;
2431         int i, num_planes = fb->format->num_planes;
2432         unsigned int tile_size = intel_tile_size(dev_priv);
2433
2434         for (i = 0; i < num_planes; i++) {
2435                 unsigned int width, height;
2436                 unsigned int cpp, size;
2437                 u32 offset;
2438                 int x, y;
2439
2440                 cpp = fb->format->cpp[i];
2441                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2442                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2443
2444                 intel_fb_offset_to_xy(&x, &y, fb, i);
2445
2446                 /*
2447                  * The fence (if used) is aligned to the start of the object
2448                  * so having the framebuffer wrap around across the edge of the
2449                  * fenced region doesn't really work. We have no API to configure
2450                  * the fence start offset within the object (nor could we probably
2451                  * on gen2/3). So it's just easier if we just require that the
2452                  * fb layout agrees with the fence layout. We already check that the
2453                  * fb stride matches the fence stride elsewhere.
2454                  */
2455                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2456                     (x + width) * cpp > fb->pitches[i]) {
2457                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2458                                       i, fb->offsets[i]);
2459                         return -EINVAL;
2460                 }
2461
2462                 /*
2463                  * First pixel of the framebuffer from
2464                  * the start of the normal gtt mapping.
2465                  */
2466                 intel_fb->normal[i].x = x;
2467                 intel_fb->normal[i].y = y;
2468
2469                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2470                                                     fb, i, fb->pitches[i],
2471                                                     DRM_ROTATE_0, tile_size);
2472                 offset /= tile_size;
2473
2474                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2475                         unsigned int tile_width, tile_height;
2476                         unsigned int pitch_tiles;
2477                         struct drm_rect r;
2478
2479                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2480
2481                         rot_info->plane[i].offset = offset;
2482                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2483                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2484                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2485
2486                         intel_fb->rotated[i].pitch =
2487                                 rot_info->plane[i].height * tile_height;
2488
2489                         /* how many tiles does this plane need */
2490                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2491                         /*
2492                          * If the plane isn't horizontally tile aligned,
2493                          * we need one more tile.
2494                          */
2495                         if (x != 0)
2496                                 size++;
2497
2498                         /* rotate the x/y offsets to match the GTT view */
2499                         r.x1 = x;
2500                         r.y1 = y;
2501                         r.x2 = x + width;
2502                         r.y2 = y + height;
2503                         drm_rect_rotate(&r,
2504                                         rot_info->plane[i].width * tile_width,
2505                                         rot_info->plane[i].height * tile_height,
2506                                         DRM_ROTATE_270);
2507                         x = r.x1;
2508                         y = r.y1;
2509
2510                         /* rotate the tile dimensions to match the GTT view */
2511                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2512                         swap(tile_width, tile_height);
2513
2514                         /*
2515                          * We only keep the x/y offsets, so push all of the
2516                          * gtt offset into the x/y offsets.
2517                          */
2518                         _intel_adjust_tile_offset(&x, &y,
2519                                                   tile_width, tile_height,
2520                                                   tile_size, pitch_tiles,
2521                                                   gtt_offset_rotated * tile_size, 0);
2522
2523                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2524
2525                         /*
2526                          * First pixel of the framebuffer from
2527                          * the start of the rotated gtt mapping.
2528                          */
2529                         intel_fb->rotated[i].x = x;
2530                         intel_fb->rotated[i].y = y;
2531                 } else {
2532                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2533                                             x * cpp, tile_size);
2534                 }
2535
2536                 /* how many tiles in total needed in the bo */
2537                 max_size = max(max_size, offset + size);
2538         }
2539
2540         if (max_size * tile_size > intel_fb->obj->base.size) {
2541                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2542                               max_size * tile_size, intel_fb->obj->base.size);
2543                 return -EINVAL;
2544         }
2545
2546         return 0;
2547 }
2548
2549 static int i9xx_format_to_fourcc(int format)
2550 {
2551         switch (format) {
2552         case DISPPLANE_8BPP:
2553                 return DRM_FORMAT_C8;
2554         case DISPPLANE_BGRX555:
2555                 return DRM_FORMAT_XRGB1555;
2556         case DISPPLANE_BGRX565:
2557                 return DRM_FORMAT_RGB565;
2558         default:
2559         case DISPPLANE_BGRX888:
2560                 return DRM_FORMAT_XRGB8888;
2561         case DISPPLANE_RGBX888:
2562                 return DRM_FORMAT_XBGR8888;
2563         case DISPPLANE_BGRX101010:
2564                 return DRM_FORMAT_XRGB2101010;
2565         case DISPPLANE_RGBX101010:
2566                 return DRM_FORMAT_XBGR2101010;
2567         }
2568 }
2569
2570 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2571 {
2572         switch (format) {
2573         case PLANE_CTL_FORMAT_RGB_565:
2574                 return DRM_FORMAT_RGB565;
2575         default:
2576         case PLANE_CTL_FORMAT_XRGB_8888:
2577                 if (rgb_order) {
2578                         if (alpha)
2579                                 return DRM_FORMAT_ABGR8888;
2580                         else
2581                                 return DRM_FORMAT_XBGR8888;
2582                 } else {
2583                         if (alpha)
2584                                 return DRM_FORMAT_ARGB8888;
2585                         else
2586                                 return DRM_FORMAT_XRGB8888;
2587                 }
2588         case PLANE_CTL_FORMAT_XRGB_2101010:
2589                 if (rgb_order)
2590                         return DRM_FORMAT_XBGR2101010;
2591                 else
2592                         return DRM_FORMAT_XRGB2101010;
2593         }
2594 }
2595
2596 static bool
2597 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2598                               struct intel_initial_plane_config *plane_config)
2599 {
2600         struct drm_device *dev = crtc->base.dev;
2601         struct drm_i915_private *dev_priv = to_i915(dev);
2602         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2603         struct drm_i915_gem_object *obj = NULL;
2604         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2605         struct drm_framebuffer *fb = &plane_config->fb->base;
2606         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2607         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2608                                     PAGE_SIZE);
2609
2610         size_aligned -= base_aligned;
2611
2612         if (plane_config->size == 0)
2613                 return false;
2614
2615         /* If the FB is too big, just don't use it since fbdev is not very
2616          * important and we should probably use that space with FBC or other
2617          * features. */
2618         if (size_aligned * 2 > ggtt->stolen_usable_size)
2619                 return false;
2620
2621         mutex_lock(&dev->struct_mutex);
2622         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2623                                                              base_aligned,
2624                                                              base_aligned,
2625                                                              size_aligned);
2626         mutex_unlock(&dev->struct_mutex);
2627         if (!obj)
2628                 return false;
2629
2630         if (plane_config->tiling == I915_TILING_X)
2631                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2632
2633         mode_cmd.pixel_format = fb->format->format;
2634         mode_cmd.width = fb->width;
2635         mode_cmd.height = fb->height;
2636         mode_cmd.pitches[0] = fb->pitches[0];
2637         mode_cmd.modifier[0] = fb->modifier;
2638         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2639
2640         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2641                 DRM_DEBUG_KMS("intel fb init failed\n");
2642                 goto out_unref_obj;
2643         }
2644
2645
2646         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2647         return true;
2648
2649 out_unref_obj:
2650         i915_gem_object_put(obj);
2651         return false;
2652 }
2653
2654 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2655 static void
2656 update_state_fb(struct drm_plane *plane)
2657 {
2658         if (plane->fb == plane->state->fb)
2659                 return;
2660
2661         if (plane->state->fb)
2662                 drm_framebuffer_unreference(plane->state->fb);
2663         plane->state->fb = plane->fb;
2664         if (plane->state->fb)
2665                 drm_framebuffer_reference(plane->state->fb);
2666 }
2667
2668 static void
2669 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2670                         struct intel_plane_state *plane_state,
2671                         bool visible)
2672 {
2673         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2674
2675         plane_state->base.visible = visible;
2676
2677         /* FIXME pre-g4x don't work like this */
2678         if (visible) {
2679                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2680                 crtc_state->active_planes |= BIT(plane->id);
2681         } else {
2682                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2683                 crtc_state->active_planes &= ~BIT(plane->id);
2684         }
2685
2686         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2687                       crtc_state->base.crtc->name,
2688                       crtc_state->active_planes);
2689 }
2690
2691 static void
2692 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2693                              struct intel_initial_plane_config *plane_config)
2694 {
2695         struct drm_device *dev = intel_crtc->base.dev;
2696         struct drm_i915_private *dev_priv = to_i915(dev);
2697         struct drm_crtc *c;
2698         struct drm_i915_gem_object *obj;
2699         struct drm_plane *primary = intel_crtc->base.primary;
2700         struct drm_plane_state *plane_state = primary->state;
2701         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2702         struct intel_plane *intel_plane = to_intel_plane(primary);
2703         struct intel_plane_state *intel_state =
2704                 to_intel_plane_state(plane_state);
2705         struct drm_framebuffer *fb;
2706
2707         if (!plane_config->fb)
2708                 return;
2709
2710         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2711                 fb = &plane_config->fb->base;
2712                 goto valid_fb;
2713         }
2714
2715         kfree(plane_config->fb);
2716
2717         /*
2718          * Failed to alloc the obj, check to see if we should share
2719          * an fb with another CRTC instead
2720          */
2721         for_each_crtc(dev, c) {
2722                 struct intel_plane_state *state;
2723
2724                 if (c == &intel_crtc->base)
2725                         continue;
2726
2727                 if (!to_intel_crtc(c)->active)
2728                         continue;
2729
2730                 state = to_intel_plane_state(c->primary->state);
2731                 if (!state->vma)
2732                         continue;
2733
2734                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2735                         fb = c->primary->fb;
2736                         drm_framebuffer_reference(fb);
2737                         goto valid_fb;
2738                 }
2739         }
2740
2741         /*
2742          * We've failed to reconstruct the BIOS FB.  Current display state
2743          * indicates that the primary plane is visible, but has a NULL FB,
2744          * which will lead to problems later if we don't fix it up.  The
2745          * simplest solution is to just disable the primary plane now and
2746          * pretend the BIOS never had it enabled.
2747          */
2748         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2749                                 to_intel_plane_state(plane_state),
2750                                 false);
2751         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2752         trace_intel_disable_plane(primary, intel_crtc);
2753         intel_plane->disable_plane(primary, &intel_crtc->base);
2754
2755         return;
2756
2757 valid_fb:
2758         mutex_lock(&dev->struct_mutex);
2759         intel_state->vma =
2760                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2761         mutex_unlock(&dev->struct_mutex);
2762         if (IS_ERR(intel_state->vma)) {
2763                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2764                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2765
2766                 intel_state->vma = NULL;
2767                 drm_framebuffer_unreference(fb);
2768                 return;
2769         }
2770
2771         plane_state->src_x = 0;
2772         plane_state->src_y = 0;
2773         plane_state->src_w = fb->width << 16;
2774         plane_state->src_h = fb->height << 16;
2775
2776         plane_state->crtc_x = 0;
2777         plane_state->crtc_y = 0;
2778         plane_state->crtc_w = fb->width;
2779         plane_state->crtc_h = fb->height;
2780
2781         intel_state->base.src = drm_plane_state_src(plane_state);
2782         intel_state->base.dst = drm_plane_state_dest(plane_state);
2783
2784         obj = intel_fb_obj(fb);
2785         if (i915_gem_object_is_tiled(obj))
2786                 dev_priv->preserve_bios_swizzle = true;
2787
2788         drm_framebuffer_reference(fb);
2789         primary->fb = primary->state->fb = fb;
2790         primary->crtc = primary->state->crtc = &intel_crtc->base;
2791
2792         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2793                                 to_intel_plane_state(plane_state),
2794                                 true);
2795
2796         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2797                   &obj->frontbuffer_bits);
2798 }
2799
2800 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2801                                unsigned int rotation)
2802 {
2803         int cpp = fb->format->cpp[plane];
2804
2805         switch (fb->modifier) {
2806         case DRM_FORMAT_MOD_LINEAR:
2807         case I915_FORMAT_MOD_X_TILED:
2808                 switch (cpp) {
2809                 case 8:
2810                         return 4096;
2811                 case 4:
2812                 case 2:
2813                 case 1:
2814                         return 8192;
2815                 default:
2816                         MISSING_CASE(cpp);
2817                         break;
2818                 }
2819                 break;
2820         case I915_FORMAT_MOD_Y_TILED:
2821         case I915_FORMAT_MOD_Yf_TILED:
2822                 switch (cpp) {
2823                 case 8:
2824                         return 2048;
2825                 case 4:
2826                         return 4096;
2827                 case 2:
2828                 case 1:
2829                         return 8192;
2830                 default:
2831                         MISSING_CASE(cpp);
2832                         break;
2833                 }
2834                 break;
2835         default:
2836                 MISSING_CASE(fb->modifier);
2837         }
2838
2839         return 2048;
2840 }
2841
2842 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2843 {
2844         const struct drm_framebuffer *fb = plane_state->base.fb;
2845         unsigned int rotation = plane_state->base.rotation;
2846         int x = plane_state->base.src.x1 >> 16;
2847         int y = plane_state->base.src.y1 >> 16;
2848         int w = drm_rect_width(&plane_state->base.src) >> 16;
2849         int h = drm_rect_height(&plane_state->base.src) >> 16;
2850         int max_width = skl_max_plane_width(fb, 0, rotation);
2851         int max_height = 4096;
2852         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2853
2854         if (w > max_width || h > max_height) {
2855                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2856                               w, h, max_width, max_height);
2857                 return -EINVAL;
2858         }
2859
2860         intel_add_fb_offsets(&x, &y, plane_state, 0);
2861         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2862         alignment = intel_surf_alignment(fb, 0);
2863
2864         /*
2865          * AUX surface offset is specified as the distance from the
2866          * main surface offset, and it must be non-negative. Make
2867          * sure that is what we will get.
2868          */
2869         if (offset > aux_offset)
2870                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2871                                                   offset, aux_offset & ~(alignment - 1));
2872
2873         /*
2874          * When using an X-tiled surface, the plane blows up
2875          * if the x offset + width exceed the stride.
2876          *
2877          * TODO: linear and Y-tiled seem fine, Yf untested,
2878          */
2879         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2880                 int cpp = fb->format->cpp[0];
2881
2882                 while ((x + w) * cpp > fb->pitches[0]) {
2883                         if (offset == 0) {
2884                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2885                                 return -EINVAL;
2886                         }
2887
2888                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2889                                                           offset, offset - alignment);
2890                 }
2891         }
2892
2893         plane_state->main.offset = offset;
2894         plane_state->main.x = x;
2895         plane_state->main.y = y;
2896
2897         return 0;
2898 }
2899
2900 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2901 {
2902         const struct drm_framebuffer *fb = plane_state->base.fb;
2903         unsigned int rotation = plane_state->base.rotation;
2904         int max_width = skl_max_plane_width(fb, 1, rotation);
2905         int max_height = 4096;
2906         int x = plane_state->base.src.x1 >> 17;
2907         int y = plane_state->base.src.y1 >> 17;
2908         int w = drm_rect_width(&plane_state->base.src) >> 17;
2909         int h = drm_rect_height(&plane_state->base.src) >> 17;
2910         u32 offset;
2911
2912         intel_add_fb_offsets(&x, &y, plane_state, 1);
2913         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2914
2915         /* FIXME not quite sure how/if these apply to the chroma plane */
2916         if (w > max_width || h > max_height) {
2917                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2918                               w, h, max_width, max_height);
2919                 return -EINVAL;
2920         }
2921
2922         plane_state->aux.offset = offset;
2923         plane_state->aux.x = x;
2924         plane_state->aux.y = y;
2925
2926         return 0;
2927 }
2928
2929 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2930 {
2931         const struct drm_framebuffer *fb = plane_state->base.fb;
2932         unsigned int rotation = plane_state->base.rotation;
2933         int ret;
2934
2935         if (!plane_state->base.visible)
2936                 return 0;
2937
2938         /* Rotate src coordinates to match rotated GTT view */
2939         if (drm_rotation_90_or_270(rotation))
2940                 drm_rect_rotate(&plane_state->base.src,
2941                                 fb->width << 16, fb->height << 16,
2942                                 DRM_ROTATE_270);
2943
2944         /*
2945          * Handle the AUX surface first since
2946          * the main surface setup depends on it.
2947          */
2948         if (fb->format->format == DRM_FORMAT_NV12) {
2949                 ret = skl_check_nv12_aux_surface(plane_state);
2950                 if (ret)
2951                         return ret;
2952         } else {
2953                 plane_state->aux.offset = ~0xfff;
2954                 plane_state->aux.x = 0;
2955                 plane_state->aux.y = 0;
2956         }
2957
2958         ret = skl_check_main_surface(plane_state);
2959         if (ret)
2960                 return ret;
2961
2962         return 0;
2963 }
2964
2965 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2966                           const struct intel_plane_state *plane_state)
2967 {
2968         struct drm_i915_private *dev_priv =
2969                 to_i915(plane_state->base.plane->dev);
2970         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2971         const struct drm_framebuffer *fb = plane_state->base.fb;
2972         unsigned int rotation = plane_state->base.rotation;
2973         u32 dspcntr;
2974
2975         dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
2976
2977         if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
2978             IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2979                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2980
2981         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2982                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2983
2984         if (INTEL_GEN(dev_priv) < 4) {
2985                 if (crtc->pipe == PIPE_B)
2986                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2987         }
2988
2989         switch (fb->format->format) {
2990         case DRM_FORMAT_C8:
2991                 dspcntr |= DISPPLANE_8BPP;
2992                 break;
2993         case DRM_FORMAT_XRGB1555:
2994                 dspcntr |= DISPPLANE_BGRX555;
2995                 break;
2996         case DRM_FORMAT_RGB565:
2997                 dspcntr |= DISPPLANE_BGRX565;
2998                 break;
2999         case DRM_FORMAT_XRGB8888:
3000                 dspcntr |= DISPPLANE_BGRX888;
3001                 break;
3002         case DRM_FORMAT_XBGR8888:
3003                 dspcntr |= DISPPLANE_RGBX888;
3004                 break;
3005         case DRM_FORMAT_XRGB2101010:
3006                 dspcntr |= DISPPLANE_BGRX101010;
3007                 break;
3008         case DRM_FORMAT_XBGR2101010:
3009                 dspcntr |= DISPPLANE_RGBX101010;
3010                 break;
3011         default:
3012                 MISSING_CASE(fb->format->format);
3013                 return 0;
3014         }
3015
3016         if (INTEL_GEN(dev_priv) >= 4 &&
3017             fb->modifier == I915_FORMAT_MOD_X_TILED)
3018                 dspcntr |= DISPPLANE_TILED;
3019
3020         if (rotation & DRM_ROTATE_180)
3021                 dspcntr |= DISPPLANE_ROTATE_180;
3022
3023         if (rotation & DRM_REFLECT_X)
3024                 dspcntr |= DISPPLANE_MIRROR;
3025
3026         return dspcntr;
3027 }
3028
3029 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3030 {
3031         struct drm_i915_private *dev_priv =
3032                 to_i915(plane_state->base.plane->dev);
3033         int src_x = plane_state->base.src.x1 >> 16;
3034         int src_y = plane_state->base.src.y1 >> 16;
3035         u32 offset;
3036
3037         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3038
3039         if (INTEL_GEN(dev_priv) >= 4)
3040                 offset = intel_compute_tile_offset(&src_x, &src_y,
3041                                                    plane_state, 0);
3042         else
3043                 offset = 0;
3044
3045         /* HSW/BDW do this automagically in hardware */
3046         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3047                 unsigned int rotation = plane_state->base.rotation;
3048                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3049                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3050
3051                 if (rotation & DRM_ROTATE_180) {
3052                         src_x += src_w - 1;
3053                         src_y += src_h - 1;
3054                 } else if (rotation & DRM_REFLECT_X) {
3055                         src_x += src_w - 1;
3056                 }
3057         }
3058
3059         plane_state->main.offset = offset;
3060         plane_state->main.x = src_x;
3061         plane_state->main.y = src_y;
3062
3063         return 0;
3064 }
3065
3066 static void i9xx_update_primary_plane(struct drm_plane *primary,
3067                                       const struct intel_crtc_state *crtc_state,
3068                                       const struct intel_plane_state *plane_state)
3069 {
3070         struct drm_i915_private *dev_priv = to_i915(primary->dev);
3071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3072         struct drm_framebuffer *fb = plane_state->base.fb;
3073         int plane = intel_crtc->plane;
3074         u32 linear_offset;
3075         u32 dspcntr = plane_state->ctl;
3076         i915_reg_t reg = DSPCNTR(plane);
3077         int x = plane_state->main.x;
3078         int y = plane_state->main.y;
3079         unsigned long irqflags;
3080
3081         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3082
3083         if (INTEL_GEN(dev_priv) >= 4)
3084                 intel_crtc->dspaddr_offset = plane_state->main.offset;
3085         else
3086                 intel_crtc->dspaddr_offset = linear_offset;
3087
3088         intel_crtc->adjusted_x = x;
3089         intel_crtc->adjusted_y = y;
3090
3091         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3092
3093         if (INTEL_GEN(dev_priv) < 4) {
3094                 /* pipesrc and dspsize control the size that is scaled from,
3095                  * which should always be the user's requested size.
3096                  */
3097                 I915_WRITE_FW(DSPSIZE(plane),
3098                               ((crtc_state->pipe_src_h - 1) << 16) |
3099                               (crtc_state->pipe_src_w - 1));
3100                 I915_WRITE_FW(DSPPOS(plane), 0);
3101         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3102                 I915_WRITE_FW(PRIMSIZE(plane),
3103                               ((crtc_state->pipe_src_h - 1) << 16) |
3104                               (crtc_state->pipe_src_w - 1));
3105                 I915_WRITE_FW(PRIMPOS(plane), 0);
3106                 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3107         }
3108
3109         I915_WRITE_FW(reg, dspcntr);
3110
3111         I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3112         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3113                 I915_WRITE_FW(DSPSURF(plane),
3114                               intel_plane_ggtt_offset(plane_state) +
3115                               intel_crtc->dspaddr_offset);
3116                 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3117         } else if (INTEL_GEN(dev_priv) >= 4) {
3118                 I915_WRITE_FW(DSPSURF(plane),
3119                               intel_plane_ggtt_offset(plane_state) +
3120                               intel_crtc->dspaddr_offset);
3121                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3122                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3123         } else {
3124                 I915_WRITE_FW(DSPADDR(plane),
3125                               intel_plane_ggtt_offset(plane_state) +
3126                               intel_crtc->dspaddr_offset);
3127         }
3128         POSTING_READ_FW(reg);
3129
3130         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3131 }
3132
3133 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3134                                        struct drm_crtc *crtc)
3135 {
3136         struct drm_device *dev = crtc->dev;
3137         struct drm_i915_private *dev_priv = to_i915(dev);
3138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3139         int plane = intel_crtc->plane;
3140         unsigned long irqflags;
3141
3142         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3143
3144         I915_WRITE_FW(DSPCNTR(plane), 0);
3145         if (INTEL_INFO(dev_priv)->gen >= 4)
3146                 I915_WRITE_FW(DSPSURF(plane), 0);
3147         else
3148                 I915_WRITE_FW(DSPADDR(plane), 0);
3149         POSTING_READ_FW(DSPCNTR(plane));
3150
3151         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3152 }
3153
3154 static u32
3155 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3156 {
3157         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3158                 return 64;
3159         else
3160                 return intel_tile_width_bytes(fb, plane);
3161 }
3162
3163 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3164 {
3165         struct drm_device *dev = intel_crtc->base.dev;
3166         struct drm_i915_private *dev_priv = to_i915(dev);
3167
3168         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3169         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3170         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3171 }
3172
3173 /*
3174  * This function detaches (aka. unbinds) unused scalers in hardware
3175  */
3176 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3177 {
3178         struct intel_crtc_scaler_state *scaler_state;
3179         int i;
3180
3181         scaler_state = &intel_crtc->config->scaler_state;
3182
3183         /* loop through and disable scalers that aren't in use */
3184         for (i = 0; i < intel_crtc->num_scalers; i++) {
3185                 if (!scaler_state->scalers[i].in_use)
3186                         skl_detach_scaler(intel_crtc, i);
3187         }
3188 }
3189
3190 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3191                      unsigned int rotation)
3192 {
3193         u32 stride;
3194
3195         if (plane >= fb->format->num_planes)
3196                 return 0;
3197
3198         stride = intel_fb_pitch(fb, plane, rotation);
3199
3200         /*
3201          * The stride is either expressed as a multiple of 64 bytes chunks for
3202          * linear buffers or in number of tiles for tiled buffers.
3203          */
3204         if (drm_rotation_90_or_270(rotation))
3205                 stride /= intel_tile_height(fb, plane);
3206         else
3207                 stride /= intel_fb_stride_alignment(fb, plane);
3208
3209         return stride;
3210 }
3211
3212 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3213 {
3214         switch (pixel_format) {
3215         case DRM_FORMAT_C8:
3216                 return PLANE_CTL_FORMAT_INDEXED;
3217         case DRM_FORMAT_RGB565:
3218                 return PLANE_CTL_FORMAT_RGB_565;
3219         case DRM_FORMAT_XBGR8888:
3220                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3221         case DRM_FORMAT_XRGB8888:
3222                 return PLANE_CTL_FORMAT_XRGB_8888;
3223         /*
3224          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3225          * to be already pre-multiplied. We need to add a knob (or a different
3226          * DRM_FORMAT) for user-space to configure that.
3227          */
3228         case DRM_FORMAT_ABGR8888:
3229                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3230                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3231         case DRM_FORMAT_ARGB8888:
3232                 return PLANE_CTL_FORMAT_XRGB_8888 |
3233                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3234         case DRM_FORMAT_XRGB2101010:
3235                 return PLANE_CTL_FORMAT_XRGB_2101010;
3236         case DRM_FORMAT_XBGR2101010:
3237                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3238         case DRM_FORMAT_YUYV:
3239                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3240         case DRM_FORMAT_YVYU:
3241                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3242         case DRM_FORMAT_UYVY:
3243                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3244         case DRM_FORMAT_VYUY:
3245                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3246         default:
3247                 MISSING_CASE(pixel_format);
3248         }
3249
3250         return 0;
3251 }
3252
3253 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3254 {
3255         switch (fb_modifier) {
3256         case DRM_FORMAT_MOD_LINEAR:
3257                 break;
3258         case I915_FORMAT_MOD_X_TILED:
3259                 return PLANE_CTL_TILED_X;
3260         case I915_FORMAT_MOD_Y_TILED:
3261                 return PLANE_CTL_TILED_Y;
3262         case I915_FORMAT_MOD_Yf_TILED:
3263                 return PLANE_CTL_TILED_YF;
3264         default:
3265                 MISSING_CASE(fb_modifier);
3266         }
3267
3268         return 0;
3269 }
3270
3271 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3272 {
3273         switch (rotation) {
3274         case DRM_ROTATE_0:
3275                 break;
3276         /*
3277          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3278          * while i915 HW rotation is clockwise, thats why this swapping.
3279          */
3280         case DRM_ROTATE_90:
3281                 return PLANE_CTL_ROTATE_270;
3282         case DRM_ROTATE_180:
3283                 return PLANE_CTL_ROTATE_180;
3284         case DRM_ROTATE_270:
3285                 return PLANE_CTL_ROTATE_90;
3286         default:
3287                 MISSING_CASE(rotation);
3288         }
3289
3290         return 0;
3291 }
3292
3293 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3294                   const struct intel_plane_state *plane_state)
3295 {
3296         struct drm_i915_private *dev_priv =
3297                 to_i915(plane_state->base.plane->dev);
3298         const struct drm_framebuffer *fb = plane_state->base.fb;
3299         unsigned int rotation = plane_state->base.rotation;
3300         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3301         u32 plane_ctl;
3302
3303         plane_ctl = PLANE_CTL_ENABLE;
3304
3305         if (!IS_GEMINILAKE(dev_priv)) {
3306                 plane_ctl |=
3307                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3308                         PLANE_CTL_PIPE_CSC_ENABLE |
3309                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3310         }
3311
3312         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3313         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3314         plane_ctl |= skl_plane_ctl_rotation(rotation);
3315
3316         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3317                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3318         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3319                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3320
3321         return plane_ctl;
3322 }
3323
3324 static void skylake_update_primary_plane(struct drm_plane *plane,
3325                                          const struct intel_crtc_state *crtc_state,
3326                                          const struct intel_plane_state *plane_state)
3327 {
3328         struct drm_device *dev = plane->dev;
3329         struct drm_i915_private *dev_priv = to_i915(dev);
3330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3331         struct drm_framebuffer *fb = plane_state->base.fb;
3332         enum plane_id plane_id = to_intel_plane(plane)->id;
3333         enum pipe pipe = to_intel_plane(plane)->pipe;
3334         u32 plane_ctl = plane_state->ctl;
3335         unsigned int rotation = plane_state->base.rotation;
3336         u32 stride = skl_plane_stride(fb, 0, rotation);
3337         u32 surf_addr = plane_state->main.offset;
3338         int scaler_id = plane_state->scaler_id;
3339         int src_x = plane_state->main.x;
3340         int src_y = plane_state->main.y;
3341         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3342         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3343         int dst_x = plane_state->base.dst.x1;
3344         int dst_y = plane_state->base.dst.y1;
3345         int dst_w = drm_rect_width(&plane_state->base.dst);
3346         int dst_h = drm_rect_height(&plane_state->base.dst);
3347         unsigned long irqflags;
3348
3349         /* Sizes are 0 based */
3350         src_w--;
3351         src_h--;
3352         dst_w--;
3353         dst_h--;
3354
3355         intel_crtc->dspaddr_offset = surf_addr;
3356
3357         intel_crtc->adjusted_x = src_x;
3358         intel_crtc->adjusted_y = src_y;
3359
3360         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3361
3362         if (IS_GEMINILAKE(dev_priv)) {
3363                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3364                               PLANE_COLOR_PIPE_GAMMA_ENABLE |
3365                               PLANE_COLOR_PIPE_CSC_ENABLE |
3366                               PLANE_COLOR_PLANE_GAMMA_DISABLE);
3367         }
3368
3369         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3370         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3371         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3372         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3373
3374         if (scaler_id >= 0) {
3375                 uint32_t ps_ctrl = 0;
3376
3377                 WARN_ON(!dst_w || !dst_h);
3378                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3379                         crtc_state->scaler_state.scalers[scaler_id].mode;
3380                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3381                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3382                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3383                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3384                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3385         } else {
3386                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3387         }
3388
3389         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3390                       intel_plane_ggtt_offset(plane_state) + surf_addr);
3391
3392         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3393
3394         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3395 }
3396
3397 static void skylake_disable_primary_plane(struct drm_plane *primary,
3398                                           struct drm_crtc *crtc)
3399 {
3400         struct drm_device *dev = crtc->dev;
3401         struct drm_i915_private *dev_priv = to_i915(dev);
3402         enum plane_id plane_id = to_intel_plane(primary)->id;
3403         enum pipe pipe = to_intel_plane(primary)->pipe;
3404         unsigned long irqflags;
3405
3406         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3407
3408         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3409         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3410         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3411
3412         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3413 }
3414
3415 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3416 {
3417         struct intel_crtc *crtc;
3418
3419         for_each_intel_crtc(&dev_priv->drm, crtc)
3420                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3421 }
3422
3423 static void intel_update_primary_planes(struct drm_device *dev)
3424 {
3425         struct drm_crtc *crtc;
3426
3427         for_each_crtc(dev, crtc) {
3428                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3429                 struct intel_plane_state *plane_state =
3430                         to_intel_plane_state(plane->base.state);
3431
3432                 if (plane_state->base.visible) {
3433                         trace_intel_update_plane(&plane->base,
3434                                                  to_intel_crtc(crtc));
3435
3436                         plane->update_plane(&plane->base,
3437                                             to_intel_crtc_state(crtc->state),
3438                                             plane_state);
3439                 }
3440         }
3441 }
3442
3443 static int
3444 __intel_display_resume(struct drm_device *dev,
3445                        struct drm_atomic_state *state,
3446                        struct drm_modeset_acquire_ctx *ctx)
3447 {
3448         struct drm_crtc_state *crtc_state;
3449         struct drm_crtc *crtc;
3450         int i, ret;
3451
3452         intel_modeset_setup_hw_state(dev);
3453         i915_redisable_vga(to_i915(dev));
3454
3455         if (!state)
3456                 return 0;
3457
3458         /*
3459          * We've duplicated the state, pointers to the old state are invalid.
3460          *
3461          * Don't attempt to use the old state until we commit the duplicated state.
3462          */
3463         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3464                 /*
3465                  * Force recalculation even if we restore
3466                  * current state. With fast modeset this may not result
3467                  * in a modeset when the state is compatible.
3468                  */
3469                 crtc_state->mode_changed = true;
3470         }
3471
3472         /* ignore any reset values/BIOS leftovers in the WM registers */
3473         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3474                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3475
3476         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3477
3478         WARN_ON(ret == -EDEADLK);
3479         return ret;
3480 }
3481
3482 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3483 {
3484         return intel_has_gpu_reset(dev_priv) &&
3485                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3486 }
3487
3488 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3489 {
3490         struct drm_device *dev = &dev_priv->drm;
3491         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3492         struct drm_atomic_state *state;
3493         int ret;
3494
3495         /*
3496          * Need mode_config.mutex so that we don't
3497          * trample ongoing ->detect() and whatnot.
3498          */
3499         mutex_lock(&dev->mode_config.mutex);
3500         drm_modeset_acquire_init(ctx, 0);
3501         while (1) {
3502                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3503                 if (ret != -EDEADLK)
3504                         break;
3505
3506                 drm_modeset_backoff(ctx);
3507         }
3508
3509         /* reset doesn't touch the display, but flips might get nuked anyway, */
3510         if (!i915.force_reset_modeset_test &&
3511             !gpu_reset_clobbers_display(dev_priv))
3512                 return;
3513
3514         /*
3515          * Disabling the crtcs gracefully seems nicer. Also the
3516          * g33 docs say we should at least disable all the planes.
3517          */
3518         state = drm_atomic_helper_duplicate_state(dev, ctx);
3519         if (IS_ERR(state)) {
3520                 ret = PTR_ERR(state);
3521                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3522                 return;
3523         }
3524
3525         ret = drm_atomic_helper_disable_all(dev, ctx);
3526         if (ret) {
3527                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3528                 drm_atomic_state_put(state);
3529                 return;
3530         }
3531
3532         dev_priv->modeset_restore_state = state;
3533         state->acquire_ctx = ctx;
3534 }
3535
3536 void intel_finish_reset(struct drm_i915_private *dev_priv)
3537 {
3538         struct drm_device *dev = &dev_priv->drm;
3539         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3540         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3541         int ret;
3542
3543         /*
3544          * Flips in the rings will be nuked by the reset,
3545          * so complete all pending flips so that user space
3546          * will get its events and not get stuck.
3547          */
3548         intel_complete_page_flips(dev_priv);
3549
3550         dev_priv->modeset_restore_state = NULL;
3551
3552         /* reset doesn't touch the display */
3553         if (!gpu_reset_clobbers_display(dev_priv)) {
3554                 if (!state) {
3555                         /*
3556                          * Flips in the rings have been nuked by the reset,
3557                          * so update the base address of all primary
3558                          * planes to the the last fb to make sure we're
3559                          * showing the correct fb after a reset.
3560                          *
3561                          * FIXME: Atomic will make this obsolete since we won't schedule
3562                          * CS-based flips (which might get lost in gpu resets) any more.
3563                          */
3564                         intel_update_primary_planes(dev);
3565                 } else {
3566                         ret = __intel_display_resume(dev, state, ctx);
3567                         if (ret)
3568                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3569                 }
3570         } else {
3571                 /*
3572                  * The display has been reset as well,
3573                  * so need a full re-initialization.
3574                  */
3575                 intel_runtime_pm_disable_interrupts(dev_priv);
3576                 intel_runtime_pm_enable_interrupts(dev_priv);
3577
3578                 intel_pps_unlock_regs_wa(dev_priv);
3579                 intel_modeset_init_hw(dev);
3580
3581                 spin_lock_irq(&dev_priv->irq_lock);
3582                 if (dev_priv->display.hpd_irq_setup)
3583                         dev_priv->display.hpd_irq_setup(dev_priv);
3584                 spin_unlock_irq(&dev_priv->irq_lock);
3585
3586                 ret = __intel_display_resume(dev, state, ctx);
3587                 if (ret)
3588                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3589
3590                 intel_hpd_init(dev_priv);
3591         }
3592
3593         if (state)
3594                 drm_atomic_state_put(state);
3595         drm_modeset_drop_locks(ctx);
3596         drm_modeset_acquire_fini(ctx);
3597         mutex_unlock(&dev->mode_config.mutex);
3598 }
3599
3600 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3601 {
3602         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3603
3604         if (i915_reset_backoff(error))
3605                 return true;
3606
3607         if (crtc->reset_count != i915_reset_count(error))
3608                 return true;
3609
3610         return false;
3611 }
3612
3613 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3614 {
3615         struct drm_device *dev = crtc->dev;
3616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617         bool pending;
3618
3619         if (abort_flip_on_reset(intel_crtc))
3620                 return false;
3621
3622         spin_lock_irq(&dev->event_lock);
3623         pending = to_intel_crtc(crtc)->flip_work != NULL;
3624         spin_unlock_irq(&dev->event_lock);
3625
3626         return pending;
3627 }
3628
3629 static void intel_update_pipe_config(struct intel_crtc *crtc,
3630                                      struct intel_crtc_state *old_crtc_state)
3631 {
3632         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3633         struct intel_crtc_state *pipe_config =
3634                 to_intel_crtc_state(crtc->base.state);
3635
3636         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3637         crtc->base.mode = crtc->base.state->mode;
3638
3639         /*
3640          * Update pipe size and adjust fitter if needed: the reason for this is
3641          * that in compute_mode_changes we check the native mode (not the pfit
3642          * mode) to see if we can flip rather than do a full mode set. In the
3643          * fastboot case, we'll flip, but if we don't update the pipesrc and
3644          * pfit state, we'll end up with a big fb scanned out into the wrong
3645          * sized surface.
3646          */
3647
3648         I915_WRITE(PIPESRC(crtc->pipe),
3649                    ((pipe_config->pipe_src_w - 1) << 16) |
3650                    (pipe_config->pipe_src_h - 1));
3651
3652         /* on skylake this is done by detaching scalers */
3653         if (INTEL_GEN(dev_priv) >= 9) {
3654                 skl_detach_scalers(crtc);
3655
3656                 if (pipe_config->pch_pfit.enabled)
3657                         skylake_pfit_enable(crtc);
3658         } else if (HAS_PCH_SPLIT(dev_priv)) {
3659                 if (pipe_config->pch_pfit.enabled)
3660                         ironlake_pfit_enable(crtc);
3661                 else if (old_crtc_state->pch_pfit.enabled)
3662                         ironlake_pfit_disable(crtc, true);
3663         }
3664 }
3665
3666 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3667 {
3668         struct drm_device *dev = crtc->base.dev;
3669         struct drm_i915_private *dev_priv = to_i915(dev);
3670         int pipe = crtc->pipe;
3671         i915_reg_t reg;
3672         u32 temp;
3673
3674         /* enable normal train */
3675         reg = FDI_TX_CTL(pipe);
3676         temp = I915_READ(reg);
3677         if (IS_IVYBRIDGE(dev_priv)) {
3678                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3679                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3680         } else {
3681                 temp &= ~FDI_LINK_TRAIN_NONE;
3682                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3683         }
3684         I915_WRITE(reg, temp);
3685
3686         reg = FDI_RX_CTL(pipe);
3687         temp = I915_READ(reg);
3688         if (HAS_PCH_CPT(dev_priv)) {
3689                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3690                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3691         } else {
3692                 temp &= ~FDI_LINK_TRAIN_NONE;
3693                 temp |= FDI_LINK_TRAIN_NONE;
3694         }
3695         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3696
3697         /* wait one idle pattern time */
3698         POSTING_READ(reg);
3699         udelay(1000);
3700
3701         /* IVB wants error correction enabled */
3702         if (IS_IVYBRIDGE(dev_priv))
3703                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3704                            FDI_FE_ERRC_ENABLE);
3705 }
3706
3707 /* The FDI link training functions for ILK/Ibexpeak. */
3708 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3709                                     const struct intel_crtc_state *crtc_state)
3710 {
3711         struct drm_device *dev = crtc->base.dev;
3712         struct drm_i915_private *dev_priv = to_i915(dev);
3713         int pipe = crtc->pipe;
3714         i915_reg_t reg;
3715         u32 temp, tries;
3716
3717         /* FDI needs bits from pipe first */
3718         assert_pipe_enabled(dev_priv, pipe);
3719
3720         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3721            for train result */
3722         reg = FDI_RX_IMR(pipe);
3723         temp = I915_READ(reg);
3724         temp &= ~FDI_RX_SYMBOL_LOCK;
3725         temp &= ~FDI_RX_BIT_LOCK;
3726         I915_WRITE(reg, temp);
3727         I915_READ(reg);
3728         udelay(150);
3729
3730         /* enable CPU FDI TX and PCH FDI RX */
3731         reg = FDI_TX_CTL(pipe);
3732         temp = I915_READ(reg);
3733         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3734         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3735         temp &= ~FDI_LINK_TRAIN_NONE;
3736         temp |= FDI_LINK_TRAIN_PATTERN_1;
3737         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3738
3739         reg = FDI_RX_CTL(pipe);
3740         temp = I915_READ(reg);
3741         temp &= ~FDI_LINK_TRAIN_NONE;
3742         temp |= FDI_LINK_TRAIN_PATTERN_1;
3743         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3744
3745         POSTING_READ(reg);
3746         udelay(150);
3747
3748         /* Ironlake workaround, enable clock pointer after FDI enable*/
3749         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3750         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3751                    FDI_RX_PHASE_SYNC_POINTER_EN);
3752
3753         reg = FDI_RX_IIR(pipe);
3754         for (tries = 0; tries < 5; tries++) {
3755                 temp = I915_READ(reg);
3756                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3757
3758                 if ((temp & FDI_RX_BIT_LOCK)) {
3759                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3760                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3761                         break;
3762                 }
3763         }
3764         if (tries == 5)
3765                 DRM_ERROR("FDI train 1 fail!\n");
3766
3767         /* Train 2 */
3768         reg = FDI_TX_CTL(pipe);
3769         temp = I915_READ(reg);
3770         temp &= ~FDI_LINK_TRAIN_NONE;
3771         temp |= FDI_LINK_TRAIN_PATTERN_2;
3772         I915_WRITE(reg, temp);
3773
3774         reg = FDI_RX_CTL(pipe);
3775         temp = I915_READ(reg);
3776         temp &= ~FDI_LINK_TRAIN_NONE;
3777         temp |= FDI_LINK_TRAIN_PATTERN_2;
3778         I915_WRITE(reg, temp);
3779
3780         POSTING_READ(reg);
3781         udelay(150);
3782
3783         reg = FDI_RX_IIR(pipe);
3784         for (tries = 0; tries < 5; tries++) {
3785                 temp = I915_READ(reg);
3786                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3787
3788                 if (temp & FDI_RX_SYMBOL_LOCK) {
3789                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3790                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3791                         break;
3792                 }
3793         }
3794         if (tries == 5)
3795                 DRM_ERROR("FDI train 2 fail!\n");
3796
3797         DRM_DEBUG_KMS("FDI train done\n");
3798
3799 }
3800
3801 static const int snb_b_fdi_train_param[] = {
3802         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3803         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3804         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3805         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3806 };
3807
3808 /* The FDI link training functions for SNB/Cougarpoint. */
3809 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3810                                 const struct intel_crtc_state *crtc_state)
3811 {
3812         struct drm_device *dev = crtc->base.dev;
3813         struct drm_i915_private *dev_priv = to_i915(dev);
3814         int pipe = crtc->pipe;
3815         i915_reg_t reg;
3816         u32 temp, i, retry;
3817
3818         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3819            for train result */
3820         reg = FDI_RX_IMR(pipe);
3821         temp = I915_READ(reg);
3822         temp &= ~FDI_RX_SYMBOL_LOCK;
3823         temp &= ~FDI_RX_BIT_LOCK;
3824         I915_WRITE(reg, temp);
3825
3826         POSTING_READ(reg);
3827         udelay(150);
3828
3829         /* enable CPU FDI TX and PCH FDI RX */
3830         reg = FDI_TX_CTL(pipe);
3831         temp = I915_READ(reg);
3832         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3833         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3834         temp &= ~FDI_LINK_TRAIN_NONE;
3835         temp |= FDI_LINK_TRAIN_PATTERN_1;
3836         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3837         /* SNB-B */
3838         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3839         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3840
3841         I915_WRITE(FDI_RX_MISC(pipe),
3842                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3843
3844         reg = FDI_RX_CTL(pipe);
3845         temp = I915_READ(reg);
3846         if (HAS_PCH_CPT(dev_priv)) {
3847                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3848                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3849         } else {
3850                 temp &= ~FDI_LINK_TRAIN_NONE;
3851                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3852         }
3853         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3854
3855         POSTING_READ(reg);
3856         udelay(150);
3857
3858         for (i = 0; i < 4; i++) {
3859                 reg = FDI_TX_CTL(pipe);
3860                 temp = I915_READ(reg);
3861                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3862                 temp |= snb_b_fdi_train_param[i];
3863                 I915_WRITE(reg, temp);
3864
3865                 POSTING_READ(reg);
3866                 udelay(500);
3867
3868                 for (retry = 0; retry < 5; retry++) {
3869                         reg = FDI_RX_IIR(pipe);
3870                         temp = I915_READ(reg);
3871                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3872                         if (temp & FDI_RX_BIT_LOCK) {
3873                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3874                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3875                                 break;
3876                         }
3877                         udelay(50);
3878                 }
3879                 if (retry < 5)
3880                         break;
3881         }
3882         if (i == 4)
3883                 DRM_ERROR("FDI train 1 fail!\n");
3884
3885         /* Train 2 */
3886         reg = FDI_TX_CTL(pipe);
3887         temp = I915_READ(reg);
3888         temp &= ~FDI_LINK_TRAIN_NONE;
3889         temp |= FDI_LINK_TRAIN_PATTERN_2;
3890         if (IS_GEN6(dev_priv)) {
3891                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3892                 /* SNB-B */
3893                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3894         }
3895         I915_WRITE(reg, temp);
3896
3897         reg = FDI_RX_CTL(pipe);
3898         temp = I915_READ(reg);
3899         if (HAS_PCH_CPT(dev_priv)) {
3900                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3901                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3902         } else {
3903                 temp &= ~FDI_LINK_TRAIN_NONE;
3904                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3905         }
3906         I915_WRITE(reg, temp);
3907
3908         POSTING_READ(reg);
3909         udelay(150);
3910
3911         for (i = 0; i < 4; i++) {
3912                 reg = FDI_TX_CTL(pipe);
3913                 temp = I915_READ(reg);
3914                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3915                 temp |= snb_b_fdi_train_param[i];
3916                 I915_WRITE(reg, temp);
3917
3918                 POSTING_READ(reg);
3919                 udelay(500);
3920
3921                 for (retry = 0; retry < 5; retry++) {
3922                         reg = FDI_RX_IIR(pipe);
3923                         temp = I915_READ(reg);
3924                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3925                         if (temp & FDI_RX_SYMBOL_LOCK) {
3926                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3927                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3928                                 break;
3929                         }
3930                         udelay(50);
3931                 }
3932                 if (retry < 5)
3933                         break;
3934         }
3935         if (i == 4)
3936                 DRM_ERROR("FDI train 2 fail!\n");
3937
3938         DRM_DEBUG_KMS("FDI train done.\n");
3939 }
3940
3941 /* Manual link training for Ivy Bridge A0 parts */
3942 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3943                                       const struct intel_crtc_state *crtc_state)
3944 {
3945         struct drm_device *dev = crtc->base.dev;
3946         struct drm_i915_private *dev_priv = to_i915(dev);
3947         int pipe = crtc->pipe;
3948         i915_reg_t reg;
3949         u32 temp, i, j;
3950
3951         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3952            for train result */
3953         reg = FDI_RX_IMR(pipe);
3954         temp = I915_READ(reg);
3955         temp &= ~FDI_RX_SYMBOL_LOCK;
3956         temp &= ~FDI_RX_BIT_LOCK;
3957         I915_WRITE(reg, temp);
3958
3959         POSTING_READ(reg);
3960         udelay(150);
3961
3962         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3963                       I915_READ(FDI_RX_IIR(pipe)));
3964
3965         /* Try each vswing and preemphasis setting twice before moving on */
3966         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3967                 /* disable first in case we need to retry */
3968                 reg = FDI_TX_CTL(pipe);
3969                 temp = I915_READ(reg);
3970                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3971                 temp &= ~FDI_TX_ENABLE;
3972                 I915_WRITE(reg, temp);
3973
3974                 reg = FDI_RX_CTL(pipe);
3975                 temp = I915_READ(reg);
3976                 temp &= ~FDI_LINK_TRAIN_AUTO;
3977                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3978                 temp &= ~FDI_RX_ENABLE;
3979                 I915_WRITE(reg, temp);
3980
3981                 /* enable CPU FDI TX and PCH FDI RX */
3982                 reg = FDI_TX_CTL(pipe);
3983                 temp = I915_READ(reg);
3984                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3985                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3986                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3987                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3988                 temp |= snb_b_fdi_train_param[j/2];
3989                 temp |= FDI_COMPOSITE_SYNC;
3990                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3991
3992                 I915_WRITE(FDI_RX_MISC(pipe),
3993                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3994
3995                 reg = FDI_RX_CTL(pipe);
3996                 temp = I915_READ(reg);
3997                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3998                 temp |= FDI_COMPOSITE_SYNC;
3999                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4000
4001                 POSTING_READ(reg);
4002                 udelay(1); /* should be 0.5us */
4003
4004                 for (i = 0; i < 4; i++) {
4005                         reg = FDI_RX_IIR(pipe);
4006                         temp = I915_READ(reg);
4007                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4008
4009                         if (temp & FDI_RX_BIT_LOCK ||
4010                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4011                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4012                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4013                                               i);
4014                                 break;
4015                         }
4016                         udelay(1); /* should be 0.5us */
4017                 }
4018                 if (i == 4) {
4019                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4020                         continue;
4021                 }
4022
4023                 /* Train 2 */
4024                 reg = FDI_TX_CTL(pipe);
4025                 temp = I915_READ(reg);
4026                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4027                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4028                 I915_WRITE(reg, temp);
4029
4030                 reg = FDI_RX_CTL(pipe);
4031                 temp = I915_READ(reg);
4032                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4033                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4034                 I915_WRITE(reg, temp);
4035
4036                 POSTING_READ(reg);
4037                 udelay(2); /* should be 1.5us */
4038
4039                 for (i = 0; i < 4; i++) {
4040                         reg = FDI_RX_IIR(pipe);
4041                         temp = I915_READ(reg);
4042                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4043
4044                         if (temp & FDI_RX_SYMBOL_LOCK ||
4045                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4046                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4047                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4048                                               i);
4049                                 goto train_done;
4050                         }
4051                         udelay(2); /* should be 1.5us */
4052                 }
4053                 if (i == 4)
4054                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4055         }
4056
4057 train_done:
4058         DRM_DEBUG_KMS("FDI train done.\n");
4059 }
4060
4061 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4062 {
4063         struct drm_device *dev = intel_crtc->base.dev;
4064         struct drm_i915_private *dev_priv = to_i915(dev);
4065         int pipe = intel_crtc->pipe;
4066         i915_reg_t reg;
4067         u32 temp;
4068
4069         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4070         reg = FDI_RX_CTL(pipe);
4071         temp = I915_READ(reg);
4072         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4073         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4074         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4075         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4076
4077         POSTING_READ(reg);
4078         udelay(200);
4079
4080         /* Switch from Rawclk to PCDclk */
4081         temp = I915_READ(reg);
4082         I915_WRITE(reg, temp | FDI_PCDCLK);
4083
4084         POSTING_READ(reg);
4085         udelay(200);
4086
4087         /* Enable CPU FDI TX PLL, always on for Ironlake */
4088         reg = FDI_TX_CTL(pipe);
4089         temp = I915_READ(reg);
4090         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4091                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4092
4093                 POSTING_READ(reg);
4094                 udelay(100);
4095         }
4096 }
4097
4098 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4099 {
4100         struct drm_device *dev = intel_crtc->base.dev;
4101         struct drm_i915_private *dev_priv = to_i915(dev);
4102         int pipe = intel_crtc->pipe;
4103         i915_reg_t reg;
4104         u32 temp;
4105
4106         /* Switch from PCDclk to Rawclk */
4107         reg = FDI_RX_CTL(pipe);
4108         temp = I915_READ(reg);
4109         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4110
4111         /* Disable CPU FDI TX PLL */
4112         reg = FDI_TX_CTL(pipe);
4113         temp = I915_READ(reg);
4114         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4115
4116         POSTING_READ(reg);
4117         udelay(100);
4118
4119         reg = FDI_RX_CTL(pipe);
4120         temp = I915_READ(reg);
4121         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4122
4123         /* Wait for the clocks to turn off. */
4124         POSTING_READ(reg);
4125         udelay(100);
4126 }
4127
4128 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4129 {
4130         struct drm_device *dev = crtc->dev;
4131         struct drm_i915_private *dev_priv = to_i915(dev);
4132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4133         int pipe = intel_crtc->pipe;
4134         i915_reg_t reg;
4135         u32 temp;
4136
4137         /* disable CPU FDI tx and PCH FDI rx */
4138         reg = FDI_TX_CTL(pipe);
4139         temp = I915_READ(reg);
4140         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4141         POSTING_READ(reg);
4142
4143         reg = FDI_RX_CTL(pipe);
4144         temp = I915_READ(reg);
4145         temp &= ~(0x7 << 16);
4146         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4147         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4148
4149         POSTING_READ(reg);
4150         udelay(100);
4151
4152         /* Ironlake workaround, disable clock pointer after downing FDI */
4153         if (HAS_PCH_IBX(dev_priv))
4154                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4155
4156         /* still set train pattern 1 */
4157         reg = FDI_TX_CTL(pipe);
4158         temp = I915_READ(reg);
4159         temp &= ~FDI_LINK_TRAIN_NONE;
4160         temp |= FDI_LINK_TRAIN_PATTERN_1;
4161         I915_WRITE(reg, temp);
4162
4163         reg = FDI_RX_CTL(pipe);
4164         temp = I915_READ(reg);
4165         if (HAS_PCH_CPT(dev_priv)) {
4166                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4167                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4168         } else {
4169                 temp &= ~FDI_LINK_TRAIN_NONE;
4170                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4171         }
4172         /* BPC in FDI rx is consistent with that in PIPECONF */
4173         temp &= ~(0x07 << 16);
4174         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4175         I915_WRITE(reg, temp);
4176
4177         POSTING_READ(reg);
4178         udelay(100);
4179 }
4180
4181 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4182 {
4183         struct intel_crtc *crtc;
4184
4185         /* Note that we don't need to be called with mode_config.lock here
4186          * as our list of CRTC objects is static for the lifetime of the
4187          * device and so cannot disappear as we iterate. Similarly, we can
4188          * happily treat the predicates as racy, atomic checks as userspace
4189          * cannot claim and pin a new fb without at least acquring the
4190          * struct_mutex and so serialising with us.
4191          */
4192         for_each_intel_crtc(&dev_priv->drm, crtc) {
4193                 if (atomic_read(&crtc->unpin_work_count) == 0)
4194                         continue;
4195
4196                 if (crtc->flip_work)
4197                         intel_wait_for_vblank(dev_priv, crtc->pipe);
4198
4199                 return true;
4200         }
4201
4202         return false;
4203 }
4204
4205 static void page_flip_completed(struct intel_crtc *intel_crtc)
4206 {
4207         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4208         struct intel_flip_work *work = intel_crtc->flip_work;
4209
4210         intel_crtc->flip_work = NULL;
4211
4212         if (work->event)
4213                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4214
4215         drm_crtc_vblank_put(&intel_crtc->base);
4216
4217         wake_up_all(&dev_priv->pending_flip_queue);
4218         trace_i915_flip_complete(intel_crtc->plane,
4219                                  work->pending_flip_obj);
4220
4221         queue_work(dev_priv->wq, &work->unpin_work);
4222 }
4223
4224 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4225 {
4226         struct drm_device *dev = crtc->dev;
4227         struct drm_i915_private *dev_priv = to_i915(dev);
4228         long ret;
4229
4230         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4231
4232         ret = wait_event_interruptible_timeout(
4233                                         dev_priv->pending_flip_queue,
4234                                         !intel_crtc_has_pending_flip(crtc),
4235                                         60*HZ);
4236
4237         if (ret < 0)
4238                 return ret;
4239
4240         if (ret == 0) {
4241                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4242                 struct intel_flip_work *work;
4243
4244                 spin_lock_irq(&dev->event_lock);
4245                 work = intel_crtc->flip_work;
4246                 if (work && !is_mmio_work(work)) {
4247                         WARN_ONCE(1, "Removing stuck page flip\n");
4248                         page_flip_completed(intel_crtc);
4249                 }
4250                 spin_unlock_irq(&dev->event_lock);
4251         }
4252
4253         return 0;
4254 }
4255
4256 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4257 {
4258         u32 temp;
4259
4260         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4261
4262         mutex_lock(&dev_priv->sb_lock);
4263
4264         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4265         temp |= SBI_SSCCTL_DISABLE;
4266         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4267
4268         mutex_unlock(&dev_priv->sb_lock);
4269 }
4270
4271 /* Program iCLKIP clock to the desired frequency */
4272 static void lpt_program_iclkip(struct intel_crtc *crtc)
4273 {
4274         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4275         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4276         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4277         u32 temp;
4278
4279         lpt_disable_iclkip(dev_priv);
4280
4281         /* The iCLK virtual clock root frequency is in MHz,
4282          * but the adjusted_mode->crtc_clock in in KHz. To get the
4283          * divisors, it is necessary to divide one by another, so we
4284          * convert the virtual clock precision to KHz here for higher
4285          * precision.
4286          */
4287         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4288                 u32 iclk_virtual_root_freq = 172800 * 1000;
4289                 u32 iclk_pi_range = 64;
4290                 u32 desired_divisor;
4291
4292                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4293                                                     clock << auxdiv);
4294                 divsel = (desired_divisor / iclk_pi_range) - 2;
4295                 phaseinc = desired_divisor % iclk_pi_range;
4296
4297                 /*
4298                  * Near 20MHz is a corner case which is
4299                  * out of range for the 7-bit divisor
4300                  */
4301                 if (divsel <= 0x7f)
4302                         break;
4303         }
4304
4305         /* This should not happen with any sane values */
4306         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4307                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4308         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4309                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4310
4311         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4312                         clock,
4313                         auxdiv,
4314                         divsel,
4315                         phasedir,
4316                         phaseinc);
4317
4318         mutex_lock(&dev_priv->sb_lock);
4319
4320         /* Program SSCDIVINTPHASE6 */
4321         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4322         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4323         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4324         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4325         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4326         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4327         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4328         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4329
4330         /* Program SSCAUXDIV */
4331         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4332         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4333         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4334         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4335
4336         /* Enable modulator and associated divider */
4337         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4338         temp &= ~SBI_SSCCTL_DISABLE;
4339         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4340
4341         mutex_unlock(&dev_priv->sb_lock);
4342
4343         /* Wait for initialization time */
4344         udelay(24);
4345
4346         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4347 }
4348
4349 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4350 {
4351         u32 divsel, phaseinc, auxdiv;
4352         u32 iclk_virtual_root_freq = 172800 * 1000;
4353         u32 iclk_pi_range = 64;
4354         u32 desired_divisor;
4355         u32 temp;
4356
4357         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4358                 return 0;
4359
4360         mutex_lock(&dev_priv->sb_lock);
4361
4362         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4363         if (temp & SBI_SSCCTL_DISABLE) {
4364                 mutex_unlock(&dev_priv->sb_lock);
4365                 return 0;
4366         }
4367
4368         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4369         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4370                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4371         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4372                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4373
4374         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4375         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4376                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4377
4378         mutex_unlock(&dev_priv->sb_lock);
4379
4380         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4381
4382         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4383                                  desired_divisor << auxdiv);
4384 }
4385
4386 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4387                                                 enum pipe pch_transcoder)
4388 {
4389         struct drm_device *dev = crtc->base.dev;
4390         struct drm_i915_private *dev_priv = to_i915(dev);
4391         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4392
4393         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4394                    I915_READ(HTOTAL(cpu_transcoder)));
4395         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4396                    I915_READ(HBLANK(cpu_transcoder)));
4397         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4398                    I915_READ(HSYNC(cpu_transcoder)));
4399
4400         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4401                    I915_READ(VTOTAL(cpu_transcoder)));
4402         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4403                    I915_READ(VBLANK(cpu_transcoder)));
4404         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4405                    I915_READ(VSYNC(cpu_transcoder)));
4406         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4407                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4408 }
4409
4410 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4411 {
4412         struct drm_i915_private *dev_priv = to_i915(dev);
4413         uint32_t temp;
4414
4415         temp = I915_READ(SOUTH_CHICKEN1);
4416         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4417                 return;
4418
4419         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4420         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4421
4422         temp &= ~FDI_BC_BIFURCATION_SELECT;
4423         if (enable)
4424                 temp |= FDI_BC_BIFURCATION_SELECT;
4425
4426         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4427         I915_WRITE(SOUTH_CHICKEN1, temp);
4428         POSTING_READ(SOUTH_CHICKEN1);
4429 }
4430
4431 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4432 {
4433         struct drm_device *dev = intel_crtc->base.dev;
4434
4435         switch (intel_crtc->pipe) {
4436         case PIPE_A:
4437                 break;
4438         case PIPE_B:
4439                 if (intel_crtc->config->fdi_lanes > 2)
4440                         cpt_set_fdi_bc_bifurcation(dev, false);
4441                 else
4442                         cpt_set_fdi_bc_bifurcation(dev, true);
4443
4444                 break;
4445         case PIPE_C:
4446                 cpt_set_fdi_bc_bifurcation(dev, true);
4447
4448                 break;
4449         default:
4450                 BUG();
4451         }
4452 }
4453
4454 /* Return which DP Port should be selected for Transcoder DP control */
4455 static enum port
4456 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4457 {
4458         struct drm_device *dev = crtc->base.dev;
4459         struct intel_encoder *encoder;
4460
4461         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4462                 if (encoder->type == INTEL_OUTPUT_DP ||
4463                     encoder->type == INTEL_OUTPUT_EDP)
4464                         return enc_to_dig_port(&encoder->base)->port;
4465         }
4466
4467         return -1;
4468 }
4469
4470 /*
4471  * Enable PCH resources required for PCH ports:
4472  *   - PCH PLLs
4473  *   - FDI training & RX/TX
4474  *   - update transcoder timings
4475  *   - DP transcoding bits
4476  *   - transcoder
4477  */
4478 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4479 {
4480         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4481         struct drm_device *dev = crtc->base.dev;
4482         struct drm_i915_private *dev_priv = to_i915(dev);
4483         int pipe = crtc->pipe;
4484         u32 temp;
4485
4486         assert_pch_transcoder_disabled(dev_priv, pipe);
4487
4488         if (IS_IVYBRIDGE(dev_priv))
4489                 ivybridge_update_fdi_bc_bifurcation(crtc);
4490
4491         /* Write the TU size bits before fdi link training, so that error
4492          * detection works. */
4493         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4494                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4495
4496         /* For PCH output, training FDI link */
4497         dev_priv->display.fdi_link_train(crtc, crtc_state);
4498
4499         /* We need to program the right clock selection before writing the pixel
4500          * mutliplier into the DPLL. */
4501         if (HAS_PCH_CPT(dev_priv)) {
4502                 u32 sel;
4503
4504                 temp = I915_READ(PCH_DPLL_SEL);
4505                 temp |= TRANS_DPLL_ENABLE(pipe);
4506                 sel = TRANS_DPLLB_SEL(pipe);
4507                 if (crtc_state->shared_dpll ==
4508                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4509                         temp |= sel;
4510                 else
4511                         temp &= ~sel;
4512                 I915_WRITE(PCH_DPLL_SEL, temp);
4513         }
4514
4515         /* XXX: pch pll's can be enabled any time before we enable the PCH
4516          * transcoder, and we actually should do this to not upset any PCH
4517          * transcoder that already use the clock when we share it.
4518          *
4519          * Note that enable_shared_dpll tries to do the right thing, but
4520          * get_shared_dpll unconditionally resets the pll - we need that to have
4521          * the right LVDS enable sequence. */
4522         intel_enable_shared_dpll(crtc);
4523
4524         /* set transcoder timing, panel must allow it */
4525         assert_panel_unlocked(dev_priv, pipe);
4526         ironlake_pch_transcoder_set_timings(crtc, pipe);
4527
4528         intel_fdi_normal_train(crtc);
4529
4530         /* For PCH DP, enable TRANS_DP_CTL */
4531         if (HAS_PCH_CPT(dev_priv) &&
4532             intel_crtc_has_dp_encoder(crtc_state)) {
4533                 const struct drm_display_mode *adjusted_mode =
4534                         &crtc_state->base.adjusted_mode;
4535                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4536                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4537                 temp = I915_READ(reg);
4538                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4539                           TRANS_DP_SYNC_MASK |
4540                           TRANS_DP_BPC_MASK);
4541                 temp |= TRANS_DP_OUTPUT_ENABLE;
4542                 temp |= bpc << 9; /* same format but at 11:9 */
4543
4544                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4545                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4546                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4547                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4548
4549                 switch (intel_trans_dp_port_sel(crtc)) {
4550                 case PORT_B:
4551                         temp |= TRANS_DP_PORT_SEL_B;
4552                         break;
4553                 case PORT_C:
4554                         temp |= TRANS_DP_PORT_SEL_C;
4555                         break;
4556                 case PORT_D:
4557                         temp |= TRANS_DP_PORT_SEL_D;
4558                         break;
4559                 default:
4560                         BUG();
4561                 }
4562
4563                 I915_WRITE(reg, temp);
4564         }
4565
4566         ironlake_enable_pch_transcoder(dev_priv, pipe);
4567 }
4568
4569 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4570 {
4571         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4572         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4573         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4574
4575         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4576
4577         lpt_program_iclkip(crtc);
4578
4579         /* Set transcoder timing. */
4580         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4581
4582         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4583 }
4584
4585 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4586 {
4587         struct drm_i915_private *dev_priv = to_i915(dev);
4588         i915_reg_t dslreg = PIPEDSL(pipe);
4589         u32 temp;
4590
4591         temp = I915_READ(dslreg);
4592         udelay(500);
4593         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4594                 if (wait_for(I915_READ(dslreg) != temp, 5))
4595                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4596         }
4597 }
4598
4599 static int
4600 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4601                   unsigned int scaler_user, int *scaler_id,
4602                   int src_w, int src_h, int dst_w, int dst_h)
4603 {
4604         struct intel_crtc_scaler_state *scaler_state =
4605                 &crtc_state->scaler_state;
4606         struct intel_crtc *intel_crtc =
4607                 to_intel_crtc(crtc_state->base.crtc);
4608         int need_scaling;
4609
4610         /*
4611          * Src coordinates are already rotated by 270 degrees for
4612          * the 90/270 degree plane rotation cases (to match the
4613          * GTT mapping), hence no need to account for rotation here.
4614          */
4615         need_scaling = src_w != dst_w || src_h != dst_h;
4616
4617         /*
4618          * if plane is being disabled or scaler is no more required or force detach
4619          *  - free scaler binded to this plane/crtc
4620          *  - in order to do this, update crtc->scaler_usage
4621          *
4622          * Here scaler state in crtc_state is set free so that
4623          * scaler can be assigned to other user. Actual register
4624          * update to free the scaler is done in plane/panel-fit programming.
4625          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4626          */
4627         if (force_detach || !need_scaling) {
4628                 if (*scaler_id >= 0) {
4629                         scaler_state->scaler_users &= ~(1 << scaler_user);
4630                         scaler_state->scalers[*scaler_id].in_use = 0;
4631
4632                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4633                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4634                                 intel_crtc->pipe, scaler_user, *scaler_id,
4635                                 scaler_state->scaler_users);
4636                         *scaler_id = -1;
4637                 }
4638                 return 0;
4639         }
4640
4641         /* range checks */
4642         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4643                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4644
4645                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4646                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4647                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4648                         "size is out of scaler range\n",
4649                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4650                 return -EINVAL;
4651         }
4652
4653         /* mark this plane as a scaler user in crtc_state */
4654         scaler_state->scaler_users |= (1 << scaler_user);
4655         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4656                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4657                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4658                 scaler_state->scaler_users);
4659
4660         return 0;
4661 }
4662
4663 /**
4664  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4665  *
4666  * @state: crtc's scaler state
4667  *
4668  * Return
4669  *     0 - scaler_usage updated successfully
4670  *    error - requested scaling cannot be supported or other error condition
4671  */
4672 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4673 {
4674         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4675
4676         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4677                 &state->scaler_state.scaler_id,
4678                 state->pipe_src_w, state->pipe_src_h,
4679                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4680 }
4681
4682 /**
4683  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4684  *
4685  * @state: crtc's scaler state
4686  * @plane_state: atomic plane state to update
4687  *
4688  * Return
4689  *     0 - scaler_usage updated successfully
4690  *    error - requested scaling cannot be supported or other error condition
4691  */
4692 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4693                                    struct intel_plane_state *plane_state)
4694 {
4695
4696         struct intel_plane *intel_plane =
4697                 to_intel_plane(plane_state->base.plane);
4698         struct drm_framebuffer *fb = plane_state->base.fb;
4699         int ret;
4700
4701         bool force_detach = !fb || !plane_state->base.visible;
4702
4703         ret = skl_update_scaler(crtc_state, force_detach,
4704                                 drm_plane_index(&intel_plane->base),
4705                                 &plane_state->scaler_id,
4706                                 drm_rect_width(&plane_state->base.src) >> 16,
4707                                 drm_rect_height(&plane_state->base.src) >> 16,
4708                                 drm_rect_width(&plane_state->base.dst),
4709                                 drm_rect_height(&plane_state->base.dst));
4710
4711         if (ret || plane_state->scaler_id < 0)
4712                 return ret;
4713
4714         /* check colorkey */
4715         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4716                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4717                               intel_plane->base.base.id,
4718                               intel_plane->base.name);
4719                 return -EINVAL;
4720         }
4721
4722         /* Check src format */
4723         switch (fb->format->format) {
4724         case DRM_FORMAT_RGB565:
4725         case DRM_FORMAT_XBGR8888:
4726         case DRM_FORMAT_XRGB8888:
4727         case DRM_FORMAT_ABGR8888:
4728         case DRM_FORMAT_ARGB8888:
4729         case DRM_FORMAT_XRGB2101010:
4730         case DRM_FORMAT_XBGR2101010:
4731         case DRM_FORMAT_YUYV:
4732         case DRM_FORMAT_YVYU:
4733         case DRM_FORMAT_UYVY:
4734         case DRM_FORMAT_VYUY:
4735                 break;
4736         default:
4737                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4738                               intel_plane->base.base.id, intel_plane->base.name,
4739                               fb->base.id, fb->format->format);
4740                 return -EINVAL;
4741         }
4742
4743         return 0;
4744 }
4745
4746 static void skylake_scaler_disable(struct intel_crtc *crtc)
4747 {
4748         int i;
4749
4750         for (i = 0; i < crtc->num_scalers; i++)
4751                 skl_detach_scaler(crtc, i);
4752 }
4753
4754 static void skylake_pfit_enable(struct intel_crtc *crtc)
4755 {
4756         struct drm_device *dev = crtc->base.dev;
4757         struct drm_i915_private *dev_priv = to_i915(dev);
4758         int pipe = crtc->pipe;
4759         struct intel_crtc_scaler_state *scaler_state =
4760                 &crtc->config->scaler_state;
4761
4762         if (crtc->config->pch_pfit.enabled) {
4763                 int id;
4764
4765                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4766                         return;
4767
4768                 id = scaler_state->scaler_id;
4769                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4770                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4771                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4772                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4773         }
4774 }
4775
4776 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4777 {
4778         struct drm_device *dev = crtc->base.dev;
4779         struct drm_i915_private *dev_priv = to_i915(dev);
4780         int pipe = crtc->pipe;
4781
4782         if (crtc->config->pch_pfit.enabled) {
4783                 /* Force use of hard-coded filter coefficients
4784                  * as some pre-programmed values are broken,
4785                  * e.g. x201.
4786                  */
4787                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4788                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4789                                                  PF_PIPE_SEL_IVB(pipe));
4790                 else
4791                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4792                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4793                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4794         }
4795 }
4796
4797 void hsw_enable_ips(struct intel_crtc *crtc)
4798 {
4799         struct drm_device *dev = crtc->base.dev;
4800         struct drm_i915_private *dev_priv = to_i915(dev);
4801
4802         if (!crtc->config->ips_enabled)
4803                 return;
4804
4805         /*
4806          * We can only enable IPS after we enable a plane and wait for a vblank
4807          * This function is called from post_plane_update, which is run after
4808          * a vblank wait.
4809          */
4810
4811         assert_plane_enabled(dev_priv, crtc->plane);
4812         if (IS_BROADWELL(dev_priv)) {
4813                 mutex_lock(&dev_priv->rps.hw_lock);
4814                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4815                 mutex_unlock(&dev_priv->rps.hw_lock);
4816                 /* Quoting Art Runyan: "its not safe to expect any particular
4817                  * value in IPS_CTL bit 31 after enabling IPS through the
4818                  * mailbox." Moreover, the mailbox may return a bogus state,
4819                  * so we need to just enable it and continue on.
4820                  */
4821         } else {
4822                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4823                 /* The bit only becomes 1 in the next vblank, so this wait here
4824                  * is essentially intel_wait_for_vblank. If we don't have this
4825                  * and don't wait for vblanks until the end of crtc_enable, then
4826                  * the HW state readout code will complain that the expected
4827                  * IPS_CTL value is not the one we read. */
4828                 if (intel_wait_for_register(dev_priv,
4829                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4830                                             50))
4831                         DRM_ERROR("Timed out waiting for IPS enable\n");
4832         }
4833 }
4834
4835 void hsw_disable_ips(struct intel_crtc *crtc)
4836 {
4837         struct drm_device *dev = crtc->base.dev;
4838         struct drm_i915_private *dev_priv = to_i915(dev);
4839
4840         if (!crtc->config->ips_enabled)
4841                 return;
4842
4843         assert_plane_enabled(dev_priv, crtc->plane);
4844         if (IS_BROADWELL(dev_priv)) {
4845                 mutex_lock(&dev_priv->rps.hw_lock);
4846                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4847                 mutex_unlock(&dev_priv->rps.hw_lock);
4848                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4849                 if (intel_wait_for_register(dev_priv,
4850                                             IPS_CTL, IPS_ENABLE, 0,
4851                                             42))
4852                         DRM_ERROR("Timed out waiting for IPS disable\n");
4853         } else {
4854                 I915_WRITE(IPS_CTL, 0);
4855                 POSTING_READ(IPS_CTL);
4856         }
4857
4858         /* We need to wait for a vblank before we can disable the plane. */
4859         intel_wait_for_vblank(dev_priv, crtc->pipe);
4860 }
4861
4862 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4863 {
4864         if (intel_crtc->overlay) {
4865                 struct drm_device *dev = intel_crtc->base.dev;
4866                 struct drm_i915_private *dev_priv = to_i915(dev);
4867
4868                 mutex_lock(&dev->struct_mutex);
4869                 dev_priv->mm.interruptible = false;
4870                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4871                 dev_priv->mm.interruptible = true;
4872                 mutex_unlock(&dev->struct_mutex);
4873         }
4874
4875         /* Let userspace switch the overlay on again. In most cases userspace
4876          * has to recompute where to put it anyway.
4877          */
4878 }
4879
4880 /**
4881  * intel_post_enable_primary - Perform operations after enabling primary plane
4882  * @crtc: the CRTC whose primary plane was just enabled
4883  *
4884  * Performs potentially sleeping operations that must be done after the primary
4885  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4886  * called due to an explicit primary plane update, or due to an implicit
4887  * re-enable that is caused when a sprite plane is updated to no longer
4888  * completely hide the primary plane.
4889  */
4890 static void
4891 intel_post_enable_primary(struct drm_crtc *crtc)
4892 {
4893         struct drm_device *dev = crtc->dev;
4894         struct drm_i915_private *dev_priv = to_i915(dev);
4895         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4896         int pipe = intel_crtc->pipe;
4897
4898         /*
4899          * FIXME IPS should be fine as long as one plane is
4900          * enabled, but in practice it seems to have problems
4901          * when going from primary only to sprite only and vice
4902          * versa.
4903          */
4904         hsw_enable_ips(intel_crtc);
4905
4906         /*
4907          * Gen2 reports pipe underruns whenever all planes are disabled.
4908          * So don't enable underrun reporting before at least some planes
4909          * are enabled.
4910          * FIXME: Need to fix the logic to work when we turn off all planes
4911          * but leave the pipe running.
4912          */
4913         if (IS_GEN2(dev_priv))
4914                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4915
4916         /* Underruns don't always raise interrupts, so check manually. */
4917         intel_check_cpu_fifo_underruns(dev_priv);
4918         intel_check_pch_fifo_underruns(dev_priv);
4919 }
4920
4921 /* FIXME move all this to pre_plane_update() with proper state tracking */
4922 static void
4923 intel_pre_disable_primary(struct drm_crtc *crtc)
4924 {
4925         struct drm_device *dev = crtc->dev;
4926         struct drm_i915_private *dev_priv = to_i915(dev);
4927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4928         int pipe = intel_crtc->pipe;
4929
4930         /*
4931          * Gen2 reports pipe underruns whenever all planes are disabled.
4932          * So diasble underrun reporting before all the planes get disabled.
4933          * FIXME: Need to fix the logic to work when we turn off all planes
4934          * but leave the pipe running.
4935          */
4936         if (IS_GEN2(dev_priv))
4937                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4938
4939         /*
4940          * FIXME IPS should be fine as long as one plane is
4941          * enabled, but in practice it seems to have problems
4942          * when going from primary only to sprite only and vice
4943          * versa.
4944          */
4945         hsw_disable_ips(intel_crtc);
4946 }
4947
4948 /* FIXME get rid of this and use pre_plane_update */
4949 static void
4950 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4951 {
4952         struct drm_device *dev = crtc->dev;
4953         struct drm_i915_private *dev_priv = to_i915(dev);
4954         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4955         int pipe = intel_crtc->pipe;
4956
4957         intel_pre_disable_primary(crtc);
4958
4959         /*
4960          * Vblank time updates from the shadow to live plane control register
4961          * are blocked if the memory self-refresh mode is active at that
4962          * moment. So to make sure the plane gets truly disabled, disable
4963          * first the self-refresh mode. The self-refresh enable bit in turn
4964          * will be checked/applied by the HW only at the next frame start
4965          * event which is after the vblank start event, so we need to have a
4966          * wait-for-vblank between disabling the plane and the pipe.
4967          */
4968         if (HAS_GMCH_DISPLAY(dev_priv) &&
4969             intel_set_memory_cxsr(dev_priv, false))
4970                 intel_wait_for_vblank(dev_priv, pipe);
4971 }
4972
4973 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4974 {
4975         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4976         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4977         struct intel_crtc_state *pipe_config =
4978                 to_intel_crtc_state(crtc->base.state);
4979         struct drm_plane *primary = crtc->base.primary;
4980         struct drm_plane_state *old_pri_state =
4981                 drm_atomic_get_existing_plane_state(old_state, primary);
4982
4983         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
4984
4985         if (pipe_config->update_wm_post && pipe_config->base.active)
4986                 intel_update_watermarks(crtc);
4987
4988         if (old_pri_state) {
4989                 struct intel_plane_state *primary_state =
4990                         to_intel_plane_state(primary->state);
4991                 struct intel_plane_state *old_primary_state =
4992                         to_intel_plane_state(old_pri_state);
4993
4994                 intel_fbc_post_update(crtc);
4995
4996                 if (primary_state->base.visible &&
4997                     (needs_modeset(&pipe_config->base) ||
4998                      !old_primary_state->base.visible))
4999                         intel_post_enable_primary(&crtc->base);
5000         }
5001 }
5002
5003 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5004                                    struct intel_crtc_state *pipe_config)
5005 {
5006         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5007         struct drm_device *dev = crtc->base.dev;
5008         struct drm_i915_private *dev_priv = to_i915(dev);
5009         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5010         struct drm_plane *primary = crtc->base.primary;
5011         struct drm_plane_state *old_pri_state =
5012                 drm_atomic_get_existing_plane_state(old_state, primary);
5013         bool modeset = needs_modeset(&pipe_config->base);
5014         struct intel_atomic_state *old_intel_state =
5015                 to_intel_atomic_state(old_state);
5016
5017         if (old_pri_state) {
5018                 struct intel_plane_state *primary_state =
5019                         to_intel_plane_state(primary->state);
5020                 struct intel_plane_state *old_primary_state =
5021                         to_intel_plane_state(old_pri_state);
5022
5023                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5024
5025                 if (old_primary_state->base.visible &&
5026                     (modeset || !primary_state->base.visible))
5027                         intel_pre_disable_primary(&crtc->base);
5028         }
5029
5030         /*
5031          * Vblank time updates from the shadow to live plane control register
5032          * are blocked if the memory self-refresh mode is active at that
5033          * moment. So to make sure the plane gets truly disabled, disable
5034          * first the self-refresh mode. The self-refresh enable bit in turn
5035          * will be checked/applied by the HW only at the next frame start
5036          * event which is after the vblank start event, so we need to have a
5037          * wait-for-vblank between disabling the plane and the pipe.
5038          */
5039         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5040             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5041                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5042
5043         /*
5044          * IVB workaround: must disable low power watermarks for at least
5045          * one frame before enabling scaling.  LP watermarks can be re-enabled
5046          * when scaling is disabled.
5047          *
5048          * WaCxSRDisabledForSpriteScaling:ivb
5049          */
5050         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5051                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5052
5053         /*
5054          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5055          * watermark programming here.
5056          */
5057         if (needs_modeset(&pipe_config->base))
5058                 return;
5059
5060         /*
5061          * For platforms that support atomic watermarks, program the
5062          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5063          * will be the intermediate values that are safe for both pre- and
5064          * post- vblank; when vblank happens, the 'active' values will be set
5065          * to the final 'target' values and we'll do this again to get the
5066          * optimal watermarks.  For gen9+ platforms, the values we program here
5067          * will be the final target values which will get automatically latched
5068          * at vblank time; no further programming will be necessary.
5069          *
5070          * If a platform hasn't been transitioned to atomic watermarks yet,
5071          * we'll continue to update watermarks the old way, if flags tell
5072          * us to.
5073          */
5074         if (dev_priv->display.initial_watermarks != NULL)
5075                 dev_priv->display.initial_watermarks(old_intel_state,
5076                                                      pipe_config);
5077         else if (pipe_config->update_wm_pre)
5078                 intel_update_watermarks(crtc);
5079 }
5080
5081 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5082 {
5083         struct drm_device *dev = crtc->dev;
5084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5085         struct drm_plane *p;
5086         int pipe = intel_crtc->pipe;
5087
5088         intel_crtc_dpms_overlay_disable(intel_crtc);
5089
5090         drm_for_each_plane_mask(p, dev, plane_mask)
5091                 to_intel_plane(p)->disable_plane(p, crtc);
5092
5093         /*
5094          * FIXME: Once we grow proper nuclear flip support out of this we need
5095          * to compute the mask of flip planes precisely. For the time being
5096          * consider this a flip to a NULL plane.
5097          */
5098         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5099 }
5100
5101 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5102                                           struct intel_crtc_state *crtc_state,
5103                                           struct drm_atomic_state *old_state)
5104 {
5105         struct drm_connector_state *conn_state;
5106         struct drm_connector *conn;
5107         int i;
5108
5109         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5110                 struct intel_encoder *encoder =
5111                         to_intel_encoder(conn_state->best_encoder);
5112
5113                 if (conn_state->crtc != crtc)
5114                         continue;
5115
5116                 if (encoder->pre_pll_enable)
5117                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5118         }
5119 }
5120
5121 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5122                                       struct intel_crtc_state *crtc_state,
5123                                       struct drm_atomic_state *old_state)
5124 {
5125         struct drm_connector_state *conn_state;
5126         struct drm_connector *conn;
5127         int i;
5128
5129         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5130                 struct intel_encoder *encoder =
5131                         to_intel_encoder(conn_state->best_encoder);
5132
5133                 if (conn_state->crtc != crtc)
5134                         continue;
5135
5136                 if (encoder->pre_enable)
5137                         encoder->pre_enable(encoder, crtc_state, conn_state);
5138         }
5139 }
5140
5141 static void intel_encoders_enable(struct drm_crtc *crtc,
5142                                   struct intel_crtc_state *crtc_state,
5143                                   struct drm_atomic_state *old_state)
5144 {
5145         struct drm_connector_state *conn_state;
5146         struct drm_connector *conn;
5147         int i;
5148
5149         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5150                 struct intel_encoder *encoder =
5151                         to_intel_encoder(conn_state->best_encoder);
5152
5153                 if (conn_state->crtc != crtc)
5154                         continue;
5155
5156                 encoder->enable(encoder, crtc_state, conn_state);
5157                 intel_opregion_notify_encoder(encoder, true);
5158         }
5159 }
5160
5161 static void intel_encoders_disable(struct drm_crtc *crtc,
5162                                    struct intel_crtc_state *old_crtc_state,
5163                                    struct drm_atomic_state *old_state)
5164 {
5165         struct drm_connector_state *old_conn_state;
5166         struct drm_connector *conn;
5167         int i;
5168
5169         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5170                 struct intel_encoder *encoder =
5171                         to_intel_encoder(old_conn_state->best_encoder);
5172
5173                 if (old_conn_state->crtc != crtc)
5174                         continue;
5175
5176                 intel_opregion_notify_encoder(encoder, false);
5177                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5178         }
5179 }
5180
5181 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5182                                         struct intel_crtc_state *old_crtc_state,
5183                                         struct drm_atomic_state *old_state)
5184 {
5185         struct drm_connector_state *old_conn_state;
5186         struct drm_connector *conn;
5187         int i;
5188
5189         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5190                 struct intel_encoder *encoder =
5191                         to_intel_encoder(old_conn_state->best_encoder);
5192
5193                 if (old_conn_state->crtc != crtc)
5194                         continue;
5195
5196                 if (encoder->post_disable)
5197                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5198         }
5199 }
5200
5201 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5202                                             struct intel_crtc_state *old_crtc_state,
5203                                             struct drm_atomic_state *old_state)
5204 {
5205         struct drm_connector_state *old_conn_state;
5206         struct drm_connector *conn;
5207         int i;
5208
5209         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5210                 struct intel_encoder *encoder =
5211                         to_intel_encoder(old_conn_state->best_encoder);
5212
5213                 if (old_conn_state->crtc != crtc)
5214                         continue;
5215
5216                 if (encoder->post_pll_disable)
5217                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5218         }
5219 }
5220
5221 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5222                                  struct drm_atomic_state *old_state)
5223 {
5224         struct drm_crtc *crtc = pipe_config->base.crtc;
5225         struct drm_device *dev = crtc->dev;
5226         struct drm_i915_private *dev_priv = to_i915(dev);
5227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5228         int pipe = intel_crtc->pipe;
5229         struct intel_atomic_state *old_intel_state =
5230                 to_intel_atomic_state(old_state);
5231
5232         if (WARN_ON(intel_crtc->active))
5233                 return;
5234
5235         /*
5236          * Sometimes spurious CPU pipe underruns happen during FDI
5237          * training, at least with VGA+HDMI cloning. Suppress them.
5238          *
5239          * On ILK we get an occasional spurious CPU pipe underruns
5240          * between eDP port A enable and vdd enable. Also PCH port
5241          * enable seems to result in the occasional CPU pipe underrun.
5242          *
5243          * Spurious PCH underruns also occur during PCH enabling.
5244          */
5245         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5246                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5247         if (intel_crtc->config->has_pch_encoder)
5248                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5249
5250         if (intel_crtc->config->has_pch_encoder)
5251                 intel_prepare_shared_dpll(intel_crtc);
5252
5253         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5254                 intel_dp_set_m_n(intel_crtc, M1_N1);
5255
5256         intel_set_pipe_timings(intel_crtc);
5257         intel_set_pipe_src_size(intel_crtc);
5258
5259         if (intel_crtc->config->has_pch_encoder) {
5260                 intel_cpu_transcoder_set_m_n(intel_crtc,
5261                                      &intel_crtc->config->fdi_m_n, NULL);
5262         }
5263
5264         ironlake_set_pipeconf(crtc);
5265
5266         intel_crtc->active = true;
5267
5268         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5269
5270         if (intel_crtc->config->has_pch_encoder) {
5271                 /* Note: FDI PLL enabling _must_ be done before we enable the
5272                  * cpu pipes, hence this is separate from all the other fdi/pch
5273                  * enabling. */
5274                 ironlake_fdi_pll_enable(intel_crtc);
5275         } else {
5276                 assert_fdi_tx_disabled(dev_priv, pipe);
5277                 assert_fdi_rx_disabled(dev_priv, pipe);
5278         }
5279
5280         ironlake_pfit_enable(intel_crtc);
5281
5282         /*
5283          * On ILK+ LUT must be loaded before the pipe is running but with
5284          * clocks enabled
5285          */
5286         intel_color_load_luts(&pipe_config->base);
5287
5288         if (dev_priv->display.initial_watermarks != NULL)
5289                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5290         intel_enable_pipe(intel_crtc);
5291
5292         if (intel_crtc->config->has_pch_encoder)
5293                 ironlake_pch_enable(pipe_config);
5294
5295         assert_vblank_disabled(crtc);
5296         drm_crtc_vblank_on(crtc);
5297
5298         intel_encoders_enable(crtc, pipe_config, old_state);
5299
5300         if (HAS_PCH_CPT(dev_priv))
5301                 cpt_verify_modeset(dev, intel_crtc->pipe);
5302
5303         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5304         if (intel_crtc->config->has_pch_encoder)
5305                 intel_wait_for_vblank(dev_priv, pipe);
5306         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5307         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5308 }
5309
5310 /* IPS only exists on ULT machines and is tied to pipe A. */
5311 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5312 {
5313         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5314 }
5315
5316 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5317                                 struct drm_atomic_state *old_state)
5318 {
5319         struct drm_crtc *crtc = pipe_config->base.crtc;
5320         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5321         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5322         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5323         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5324         struct intel_atomic_state *old_intel_state =
5325                 to_intel_atomic_state(old_state);
5326
5327         if (WARN_ON(intel_crtc->active))
5328                 return;
5329
5330         if (intel_crtc->config->has_pch_encoder)
5331                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5332                                                       false);
5333
5334         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5335
5336         if (intel_crtc->config->shared_dpll)
5337                 intel_enable_shared_dpll(intel_crtc);
5338
5339         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5340                 intel_dp_set_m_n(intel_crtc, M1_N1);
5341
5342         if (!transcoder_is_dsi(cpu_transcoder))
5343                 intel_set_pipe_timings(intel_crtc);
5344
5345         intel_set_pipe_src_size(intel_crtc);
5346
5347         if (cpu_transcoder != TRANSCODER_EDP &&
5348             !transcoder_is_dsi(cpu_transcoder)) {
5349                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5350                            intel_crtc->config->pixel_multiplier - 1);
5351         }
5352
5353         if (intel_crtc->config->has_pch_encoder) {
5354                 intel_cpu_transcoder_set_m_n(intel_crtc,
5355                                      &intel_crtc->config->fdi_m_n, NULL);
5356         }
5357
5358         if (!transcoder_is_dsi(cpu_transcoder))
5359                 haswell_set_pipeconf(crtc);
5360
5361         haswell_set_pipemisc(crtc);
5362
5363         intel_color_set_csc(&pipe_config->base);
5364
5365         intel_crtc->active = true;
5366
5367         if (intel_crtc->config->has_pch_encoder)
5368                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5369         else
5370                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5371
5372         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5373
5374         if (intel_crtc->config->has_pch_encoder)
5375                 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5376
5377         if (!transcoder_is_dsi(cpu_transcoder))
5378                 intel_ddi_enable_pipe_clock(pipe_config);
5379
5380         if (INTEL_GEN(dev_priv) >= 9)
5381                 skylake_pfit_enable(intel_crtc);
5382         else
5383                 ironlake_pfit_enable(intel_crtc);
5384
5385         /*
5386          * On ILK+ LUT must be loaded before the pipe is running but with
5387          * clocks enabled
5388          */
5389         intel_color_load_luts(&pipe_config->base);
5390
5391         intel_ddi_set_pipe_settings(pipe_config);
5392         if (!transcoder_is_dsi(cpu_transcoder))
5393                 intel_ddi_enable_transcoder_func(pipe_config);
5394
5395         if (dev_priv->display.initial_watermarks != NULL)
5396                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5397
5398         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5399         if (!transcoder_is_dsi(cpu_transcoder))
5400                 intel_enable_pipe(intel_crtc);
5401
5402         if (intel_crtc->config->has_pch_encoder)
5403                 lpt_pch_enable(pipe_config);
5404
5405         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5406                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5407
5408         assert_vblank_disabled(crtc);
5409         drm_crtc_vblank_on(crtc);
5410
5411         intel_encoders_enable(crtc, pipe_config, old_state);
5412
5413         if (intel_crtc->config->has_pch_encoder) {
5414                 intel_wait_for_vblank(dev_priv, pipe);
5415                 intel_wait_for_vblank(dev_priv, pipe);
5416                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5417                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5418                                                       true);
5419         }
5420
5421         /* If we change the relative order between pipe/planes enabling, we need
5422          * to change the workaround. */
5423         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5424         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5425                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5426                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5427         }
5428 }
5429
5430 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5431 {
5432         struct drm_device *dev = crtc->base.dev;
5433         struct drm_i915_private *dev_priv = to_i915(dev);
5434         int pipe = crtc->pipe;
5435
5436         /* To avoid upsetting the power well on haswell only disable the pfit if
5437          * it's in use. The hw state code will make sure we get this right. */
5438         if (force || crtc->config->pch_pfit.enabled) {
5439                 I915_WRITE(PF_CTL(pipe), 0);
5440                 I915_WRITE(PF_WIN_POS(pipe), 0);
5441                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5442         }
5443 }
5444
5445 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5446                                   struct drm_atomic_state *old_state)
5447 {
5448         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5449         struct drm_device *dev = crtc->dev;
5450         struct drm_i915_private *dev_priv = to_i915(dev);
5451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5452         int pipe = intel_crtc->pipe;
5453
5454         /*
5455          * Sometimes spurious CPU pipe underruns happen when the
5456          * pipe is already disabled, but FDI RX/TX is still enabled.
5457          * Happens at least with VGA+HDMI cloning. Suppress them.
5458          */
5459         if (intel_crtc->config->has_pch_encoder) {
5460                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5461                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5462         }
5463
5464         intel_encoders_disable(crtc, old_crtc_state, old_state);
5465
5466         drm_crtc_vblank_off(crtc);
5467         assert_vblank_disabled(crtc);
5468
5469         intel_disable_pipe(intel_crtc);
5470
5471         ironlake_pfit_disable(intel_crtc, false);
5472
5473         if (intel_crtc->config->has_pch_encoder)
5474                 ironlake_fdi_disable(crtc);
5475
5476         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5477
5478         if (intel_crtc->config->has_pch_encoder) {
5479                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5480
5481                 if (HAS_PCH_CPT(dev_priv)) {
5482                         i915_reg_t reg;
5483                         u32 temp;
5484
5485                         /* disable TRANS_DP_CTL */
5486                         reg = TRANS_DP_CTL(pipe);
5487                         temp = I915_READ(reg);
5488                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5489                                   TRANS_DP_PORT_SEL_MASK);
5490                         temp |= TRANS_DP_PORT_SEL_NONE;
5491                         I915_WRITE(reg, temp);
5492
5493                         /* disable DPLL_SEL */
5494                         temp = I915_READ(PCH_DPLL_SEL);
5495                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5496                         I915_WRITE(PCH_DPLL_SEL, temp);
5497                 }
5498
5499                 ironlake_fdi_pll_disable(intel_crtc);
5500         }
5501
5502         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5503         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5504 }
5505
5506 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5507                                  struct drm_atomic_state *old_state)
5508 {
5509         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5510         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5512         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5513
5514         if (intel_crtc->config->has_pch_encoder)
5515                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5516                                                       false);
5517
5518         intel_encoders_disable(crtc, old_crtc_state, old_state);
5519
5520         drm_crtc_vblank_off(crtc);
5521         assert_vblank_disabled(crtc);
5522
5523         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5524         if (!transcoder_is_dsi(cpu_transcoder))
5525                 intel_disable_pipe(intel_crtc);
5526
5527         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5528                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5529
5530         if (!transcoder_is_dsi(cpu_transcoder))
5531                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5532
5533         if (INTEL_GEN(dev_priv) >= 9)
5534                 skylake_scaler_disable(intel_crtc);
5535         else
5536                 ironlake_pfit_disable(intel_crtc, false);
5537
5538         if (!transcoder_is_dsi(cpu_transcoder))
5539                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5540
5541         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5542
5543         if (old_crtc_state->has_pch_encoder)
5544                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5545                                                       true);
5546 }
5547
5548 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5549 {
5550         struct drm_device *dev = crtc->base.dev;
5551         struct drm_i915_private *dev_priv = to_i915(dev);
5552         struct intel_crtc_state *pipe_config = crtc->config;
5553
5554         if (!pipe_config->gmch_pfit.control)
5555                 return;
5556
5557         /*
5558          * The panel fitter should only be adjusted whilst the pipe is disabled,
5559          * according to register description and PRM.
5560          */
5561         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5562         assert_pipe_disabled(dev_priv, crtc->pipe);
5563
5564         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5565         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5566
5567         /* Border color in case we don't scale up to the full screen. Black by
5568          * default, change to something else for debugging. */
5569         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5570 }
5571
5572 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5573 {
5574         switch (port) {
5575         case PORT_A:
5576                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5577         case PORT_B:
5578                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5579         case PORT_C:
5580                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5581         case PORT_D:
5582                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5583         case PORT_E:
5584                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5585         default:
5586                 MISSING_CASE(port);
5587                 return POWER_DOMAIN_PORT_OTHER;
5588         }
5589 }
5590
5591 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5592                                   struct intel_crtc_state *crtc_state)
5593 {
5594         struct drm_device *dev = crtc->dev;
5595         struct drm_i915_private *dev_priv = to_i915(dev);
5596         struct drm_encoder *encoder;
5597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5598         enum pipe pipe = intel_crtc->pipe;
5599         u64 mask;
5600         enum transcoder transcoder = crtc_state->cpu_transcoder;
5601
5602         if (!crtc_state->base.active)
5603                 return 0;
5604
5605         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5606         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5607         if (crtc_state->pch_pfit.enabled ||
5608             crtc_state->pch_pfit.force_thru)
5609                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5610
5611         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5612                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5613
5614                 mask |= BIT_ULL(intel_encoder->power_domain);
5615         }
5616
5617         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5618                 mask |= BIT(POWER_DOMAIN_AUDIO);
5619
5620         if (crtc_state->shared_dpll)
5621                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5622
5623         return mask;
5624 }
5625
5626 static u64
5627 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5628                                struct intel_crtc_state *crtc_state)
5629 {
5630         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5632         enum intel_display_power_domain domain;
5633         u64 domains, new_domains, old_domains;
5634
5635         old_domains = intel_crtc->enabled_power_domains;
5636         intel_crtc->enabled_power_domains = new_domains =
5637                 get_crtc_power_domains(crtc, crtc_state);
5638
5639         domains = new_domains & ~old_domains;
5640
5641         for_each_power_domain(domain, domains)
5642                 intel_display_power_get(dev_priv, domain);
5643
5644         return old_domains & ~new_domains;
5645 }
5646
5647 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5648                                       u64 domains)
5649 {
5650         enum intel_display_power_domain domain;
5651
5652         for_each_power_domain(domain, domains)
5653                 intel_display_power_put(dev_priv, domain);
5654 }
5655
5656 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5657                                    struct drm_atomic_state *old_state)
5658 {
5659         struct intel_atomic_state *old_intel_state =
5660                 to_intel_atomic_state(old_state);
5661         struct drm_crtc *crtc = pipe_config->base.crtc;
5662         struct drm_device *dev = crtc->dev;
5663         struct drm_i915_private *dev_priv = to_i915(dev);
5664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5665         int pipe = intel_crtc->pipe;
5666
5667         if (WARN_ON(intel_crtc->active))
5668                 return;
5669
5670         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5671                 intel_dp_set_m_n(intel_crtc, M1_N1);
5672
5673         intel_set_pipe_timings(intel_crtc);
5674         intel_set_pipe_src_size(intel_crtc);
5675
5676         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5677                 struct drm_i915_private *dev_priv = to_i915(dev);
5678
5679                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5680                 I915_WRITE(CHV_CANVAS(pipe), 0);
5681         }
5682
5683         i9xx_set_pipeconf(intel_crtc);
5684
5685         intel_crtc->active = true;
5686
5687         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5688
5689         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5690
5691         if (IS_CHERRYVIEW(dev_priv)) {
5692                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5693                 chv_enable_pll(intel_crtc, intel_crtc->config);
5694         } else {
5695                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5696                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5697         }
5698
5699         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5700
5701         i9xx_pfit_enable(intel_crtc);
5702
5703         intel_color_load_luts(&pipe_config->base);
5704
5705         dev_priv->display.initial_watermarks(old_intel_state,
5706                                              pipe_config);
5707         intel_enable_pipe(intel_crtc);
5708
5709         assert_vblank_disabled(crtc);
5710         drm_crtc_vblank_on(crtc);
5711
5712         intel_encoders_enable(crtc, pipe_config, old_state);
5713 }
5714
5715 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5716 {
5717         struct drm_device *dev = crtc->base.dev;
5718         struct drm_i915_private *dev_priv = to_i915(dev);
5719
5720         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5721         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5722 }
5723
5724 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5725                              struct drm_atomic_state *old_state)
5726 {
5727         struct drm_crtc *crtc = pipe_config->base.crtc;
5728         struct drm_device *dev = crtc->dev;
5729         struct drm_i915_private *dev_priv = to_i915(dev);
5730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5731         enum pipe pipe = intel_crtc->pipe;
5732
5733         if (WARN_ON(intel_crtc->active))
5734                 return;
5735
5736         i9xx_set_pll_dividers(intel_crtc);
5737
5738         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5739                 intel_dp_set_m_n(intel_crtc, M1_N1);
5740
5741         intel_set_pipe_timings(intel_crtc);
5742         intel_set_pipe_src_size(intel_crtc);
5743
5744         i9xx_set_pipeconf(intel_crtc);
5745
5746         intel_crtc->active = true;
5747
5748         if (!IS_GEN2(dev_priv))
5749                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5750
5751         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5752
5753         i9xx_enable_pll(intel_crtc);
5754
5755         i9xx_pfit_enable(intel_crtc);
5756
5757         intel_color_load_luts(&pipe_config->base);
5758
5759         intel_update_watermarks(intel_crtc);
5760         intel_enable_pipe(intel_crtc);
5761
5762         assert_vblank_disabled(crtc);
5763         drm_crtc_vblank_on(crtc);
5764
5765         intel_encoders_enable(crtc, pipe_config, old_state);
5766 }
5767
5768 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5769 {
5770         struct drm_device *dev = crtc->base.dev;
5771         struct drm_i915_private *dev_priv = to_i915(dev);
5772
5773         if (!crtc->config->gmch_pfit.control)
5774                 return;
5775
5776         assert_pipe_disabled(dev_priv, crtc->pipe);
5777
5778         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5779                          I915_READ(PFIT_CONTROL));
5780         I915_WRITE(PFIT_CONTROL, 0);
5781 }
5782
5783 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5784                               struct drm_atomic_state *old_state)
5785 {
5786         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5787         struct drm_device *dev = crtc->dev;
5788         struct drm_i915_private *dev_priv = to_i915(dev);
5789         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5790         int pipe = intel_crtc->pipe;
5791
5792         /*
5793          * On gen2 planes are double buffered but the pipe isn't, so we must
5794          * wait for planes to fully turn off before disabling the pipe.
5795          */
5796         if (IS_GEN2(dev_priv))
5797                 intel_wait_for_vblank(dev_priv, pipe);
5798
5799         intel_encoders_disable(crtc, old_crtc_state, old_state);
5800
5801         drm_crtc_vblank_off(crtc);
5802         assert_vblank_disabled(crtc);
5803
5804         intel_disable_pipe(intel_crtc);
5805
5806         i9xx_pfit_disable(intel_crtc);
5807
5808         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5809
5810         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5811                 if (IS_CHERRYVIEW(dev_priv))
5812                         chv_disable_pll(dev_priv, pipe);
5813                 else if (IS_VALLEYVIEW(dev_priv))
5814                         vlv_disable_pll(dev_priv, pipe);
5815                 else
5816                         i9xx_disable_pll(intel_crtc);
5817         }
5818
5819         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5820
5821         if (!IS_GEN2(dev_priv))
5822                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5823
5824         if (!dev_priv->display.initial_watermarks)
5825                 intel_update_watermarks(intel_crtc);
5826 }
5827
5828 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
5829 {
5830         struct intel_encoder *encoder;
5831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5832         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5833         enum intel_display_power_domain domain;
5834         u64 domains;
5835         struct drm_atomic_state *state;
5836         struct intel_crtc_state *crtc_state;
5837         int ret;
5838
5839         if (!intel_crtc->active)
5840                 return;
5841
5842         if (crtc->primary->state->visible) {
5843                 WARN_ON(intel_crtc->flip_work);
5844
5845                 intel_pre_disable_primary_noatomic(crtc);
5846
5847                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5848                 crtc->primary->state->visible = false;
5849         }
5850
5851         state = drm_atomic_state_alloc(crtc->dev);
5852         if (!state) {
5853                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5854                               crtc->base.id, crtc->name);
5855                 return;
5856         }
5857
5858         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
5859
5860         /* Everything's already locked, -EDEADLK can't happen. */
5861         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5862         ret = drm_atomic_add_affected_connectors(state, crtc);
5863
5864         WARN_ON(IS_ERR(crtc_state) || ret);
5865
5866         dev_priv->display.crtc_disable(crtc_state, state);
5867
5868         drm_atomic_state_put(state);
5869
5870         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5871                       crtc->base.id, crtc->name);
5872
5873         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5874         crtc->state->active = false;
5875         intel_crtc->active = false;
5876         crtc->enabled = false;
5877         crtc->state->connector_mask = 0;
5878         crtc->state->encoder_mask = 0;
5879
5880         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5881                 encoder->base.crtc = NULL;
5882
5883         intel_fbc_disable(intel_crtc);
5884         intel_update_watermarks(intel_crtc);
5885         intel_disable_shared_dpll(intel_crtc);
5886
5887         domains = intel_crtc->enabled_power_domains;
5888         for_each_power_domain(domain, domains)
5889                 intel_display_power_put(dev_priv, domain);
5890         intel_crtc->enabled_power_domains = 0;
5891
5892         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5893         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5894 }
5895
5896 /*
5897  * turn all crtc's off, but do not adjust state
5898  * This has to be paired with a call to intel_modeset_setup_hw_state.
5899  */
5900 int intel_display_suspend(struct drm_device *dev)
5901 {
5902         struct drm_i915_private *dev_priv = to_i915(dev);
5903         struct drm_atomic_state *state;
5904         int ret;
5905
5906         state = drm_atomic_helper_suspend(dev);
5907         ret = PTR_ERR_OR_ZERO(state);
5908         if (ret)
5909                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5910         else
5911                 dev_priv->modeset_restore_state = state;
5912         return ret;
5913 }
5914
5915 void intel_encoder_destroy(struct drm_encoder *encoder)
5916 {
5917         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5918
5919         drm_encoder_cleanup(encoder);
5920         kfree(intel_encoder);
5921 }
5922
5923 /* Cross check the actual hw state with our own modeset state tracking (and it's
5924  * internal consistency). */
5925 static void intel_connector_verify_state(struct intel_connector *connector)
5926 {
5927         struct drm_crtc *crtc = connector->base.state->crtc;
5928
5929         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5930                       connector->base.base.id,
5931                       connector->base.name);
5932
5933         if (connector->get_hw_state(connector)) {
5934                 struct intel_encoder *encoder = connector->encoder;
5935                 struct drm_connector_state *conn_state = connector->base.state;
5936
5937                 I915_STATE_WARN(!crtc,
5938                          "connector enabled without attached crtc\n");
5939
5940                 if (!crtc)
5941                         return;
5942
5943                 I915_STATE_WARN(!crtc->state->active,
5944                       "connector is active, but attached crtc isn't\n");
5945
5946                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5947                         return;
5948
5949                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5950                         "atomic encoder doesn't match attached encoder\n");
5951
5952                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5953                         "attached encoder crtc differs from connector crtc\n");
5954         } else {
5955                 I915_STATE_WARN(crtc && crtc->state->active,
5956                         "attached crtc is active, but connector isn't\n");
5957                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
5958                         "best encoder set without crtc!\n");
5959         }
5960 }
5961
5962 int intel_connector_init(struct intel_connector *connector)
5963 {
5964         drm_atomic_helper_connector_reset(&connector->base);
5965
5966         if (!connector->base.state)
5967                 return -ENOMEM;
5968
5969         return 0;
5970 }
5971
5972 struct intel_connector *intel_connector_alloc(void)
5973 {
5974         struct intel_connector *connector;
5975
5976         connector = kzalloc(sizeof *connector, GFP_KERNEL);
5977         if (!connector)
5978                 return NULL;
5979
5980         if (intel_connector_init(connector) < 0) {
5981                 kfree(connector);
5982                 return NULL;
5983         }
5984
5985         return connector;
5986 }
5987
5988 /* Simple connector->get_hw_state implementation for encoders that support only
5989  * one connector and no cloning and hence the encoder state determines the state
5990  * of the connector. */
5991 bool intel_connector_get_hw_state(struct intel_connector *connector)
5992 {
5993         enum pipe pipe = 0;
5994         struct intel_encoder *encoder = connector->encoder;
5995
5996         return encoder->get_hw_state(encoder, &pipe);
5997 }
5998
5999 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6000 {
6001         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6002                 return crtc_state->fdi_lanes;
6003
6004         return 0;
6005 }
6006
6007 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6008                                      struct intel_crtc_state *pipe_config)
6009 {
6010         struct drm_i915_private *dev_priv = to_i915(dev);
6011         struct drm_atomic_state *state = pipe_config->base.state;
6012         struct intel_crtc *other_crtc;
6013         struct intel_crtc_state *other_crtc_state;
6014
6015         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6016                       pipe_name(pipe), pipe_config->fdi_lanes);
6017         if (pipe_config->fdi_lanes > 4) {
6018                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6019                               pipe_name(pipe), pipe_config->fdi_lanes);
6020                 return -EINVAL;
6021         }
6022
6023         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6024                 if (pipe_config->fdi_lanes > 2) {
6025                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6026                                       pipe_config->fdi_lanes);
6027                         return -EINVAL;
6028                 } else {
6029                         return 0;
6030                 }
6031         }
6032
6033         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6034                 return 0;
6035
6036         /* Ivybridge 3 pipe is really complicated */
6037         switch (pipe) {
6038         case PIPE_A:
6039                 return 0;
6040         case PIPE_B:
6041                 if (pipe_config->fdi_lanes <= 2)
6042                         return 0;
6043
6044                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6045                 other_crtc_state =
6046                         intel_atomic_get_crtc_state(state, other_crtc);
6047                 if (IS_ERR(other_crtc_state))
6048                         return PTR_ERR(other_crtc_state);
6049
6050                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6051                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6052                                       pipe_name(pipe), pipe_config->fdi_lanes);
6053                         return -EINVAL;
6054                 }
6055                 return 0;
6056         case PIPE_C:
6057                 if (pipe_config->fdi_lanes > 2) {
6058                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6059                                       pipe_name(pipe), pipe_config->fdi_lanes);
6060                         return -EINVAL;
6061                 }
6062
6063                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6064                 other_crtc_state =
6065                         intel_atomic_get_crtc_state(state, other_crtc);
6066                 if (IS_ERR(other_crtc_state))
6067                         return PTR_ERR(other_crtc_state);
6068
6069                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6070                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6071                         return -EINVAL;
6072                 }
6073                 return 0;
6074         default:
6075                 BUG();
6076         }
6077 }
6078
6079 #define RETRY 1
6080 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6081                                        struct intel_crtc_state *pipe_config)
6082 {
6083         struct drm_device *dev = intel_crtc->base.dev;
6084         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6085         int lane, link_bw, fdi_dotclock, ret;
6086         bool needs_recompute = false;
6087
6088 retry:
6089         /* FDI is a binary signal running at ~2.7GHz, encoding
6090          * each output octet as 10 bits. The actual frequency
6091          * is stored as a divider into a 100MHz clock, and the
6092          * mode pixel clock is stored in units of 1KHz.
6093          * Hence the bw of each lane in terms of the mode signal
6094          * is:
6095          */
6096         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6097
6098         fdi_dotclock = adjusted_mode->crtc_clock;
6099
6100         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6101                                            pipe_config->pipe_bpp);
6102
6103         pipe_config->fdi_lanes = lane;
6104
6105         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6106                                link_bw, &pipe_config->fdi_m_n, false);
6107
6108         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6109         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6110                 pipe_config->pipe_bpp -= 2*3;
6111                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6112                               pipe_config->pipe_bpp);
6113                 needs_recompute = true;
6114                 pipe_config->bw_constrained = true;
6115
6116                 goto retry;
6117         }
6118
6119         if (needs_recompute)
6120                 return RETRY;
6121
6122         return ret;
6123 }
6124
6125 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6126                                      struct intel_crtc_state *pipe_config)
6127 {
6128         if (pipe_config->pipe_bpp > 24)
6129                 return false;
6130
6131         /* HSW can handle pixel rate up to cdclk? */
6132         if (IS_HASWELL(dev_priv))
6133                 return true;
6134
6135         /*
6136          * We compare against max which means we must take
6137          * the increased cdclk requirement into account when
6138          * calculating the new cdclk.
6139          *
6140          * Should measure whether using a lower cdclk w/o IPS
6141          */
6142         return pipe_config->pixel_rate <=
6143                 dev_priv->max_cdclk_freq * 95 / 100;
6144 }
6145
6146 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6147                                    struct intel_crtc_state *pipe_config)
6148 {
6149         struct drm_device *dev = crtc->base.dev;
6150         struct drm_i915_private *dev_priv = to_i915(dev);
6151
6152         pipe_config->ips_enabled = i915.enable_ips &&
6153                 hsw_crtc_supports_ips(crtc) &&
6154                 pipe_config_supports_ips(dev_priv, pipe_config);
6155 }
6156
6157 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6158 {
6159         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6160
6161         /* GDG double wide on either pipe, otherwise pipe A only */
6162         return INTEL_INFO(dev_priv)->gen < 4 &&
6163                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6164 }
6165
6166 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6167 {
6168         uint32_t pixel_rate;
6169
6170         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6171
6172         /*
6173          * We only use IF-ID interlacing. If we ever use
6174          * PF-ID we'll need to adjust the pixel_rate here.
6175          */
6176
6177         if (pipe_config->pch_pfit.enabled) {
6178                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6179                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6180
6181                 pipe_w = pipe_config->pipe_src_w;
6182                 pipe_h = pipe_config->pipe_src_h;
6183
6184                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6185                 pfit_h = pfit_size & 0xFFFF;
6186                 if (pipe_w < pfit_w)
6187                         pipe_w = pfit_w;
6188                 if (pipe_h < pfit_h)
6189                         pipe_h = pfit_h;
6190
6191                 if (WARN_ON(!pfit_w || !pfit_h))
6192                         return pixel_rate;
6193
6194                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6195                                      pfit_w * pfit_h);
6196         }
6197
6198         return pixel_rate;
6199 }
6200
6201 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6202 {
6203         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6204
6205         if (HAS_GMCH_DISPLAY(dev_priv))
6206                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6207                 crtc_state->pixel_rate =
6208                         crtc_state->base.adjusted_mode.crtc_clock;
6209         else
6210                 crtc_state->pixel_rate =
6211                         ilk_pipe_pixel_rate(crtc_state);
6212 }
6213
6214 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6215                                      struct intel_crtc_state *pipe_config)
6216 {
6217         struct drm_device *dev = crtc->base.dev;
6218         struct drm_i915_private *dev_priv = to_i915(dev);
6219         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6220         int clock_limit = dev_priv->max_dotclk_freq;
6221
6222         if (INTEL_GEN(dev_priv) < 4) {
6223                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6224
6225                 /*
6226                  * Enable double wide mode when the dot clock
6227                  * is > 90% of the (display) core speed.
6228                  */
6229                 if (intel_crtc_supports_double_wide(crtc) &&
6230                     adjusted_mode->crtc_clock > clock_limit) {
6231                         clock_limit = dev_priv->max_dotclk_freq;
6232                         pipe_config->double_wide = true;
6233                 }
6234         }
6235
6236         if (adjusted_mode->crtc_clock > clock_limit) {
6237                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6238                               adjusted_mode->crtc_clock, clock_limit,
6239                               yesno(pipe_config->double_wide));
6240                 return -EINVAL;
6241         }
6242
6243         /*
6244          * Pipe horizontal size must be even in:
6245          * - DVO ganged mode
6246          * - LVDS dual channel mode
6247          * - Double wide pipe
6248          */
6249         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6250              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6251                 pipe_config->pipe_src_w &= ~1;
6252
6253         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6254          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6255          */
6256         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6257                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6258                 return -EINVAL;
6259
6260         intel_crtc_compute_pixel_rate(pipe_config);
6261
6262         if (HAS_IPS(dev_priv))
6263                 hsw_compute_ips_config(crtc, pipe_config);
6264
6265         if (pipe_config->has_pch_encoder)
6266                 return ironlake_fdi_compute_config(crtc, pipe_config);
6267
6268         return 0;
6269 }
6270
6271 static void
6272 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6273 {
6274         while (*num > DATA_LINK_M_N_MASK ||
6275                *den > DATA_LINK_M_N_MASK) {
6276                 *num >>= 1;
6277                 *den >>= 1;
6278         }
6279 }
6280
6281 static void compute_m_n(unsigned int m, unsigned int n,
6282                         uint32_t *ret_m, uint32_t *ret_n,
6283                         bool reduce_m_n)
6284 {
6285         /*
6286          * Reduce M/N as much as possible without loss in precision. Several DP
6287          * dongles in particular seem to be fussy about too large *link* M/N
6288          * values. The passed in values are more likely to have the least
6289          * significant bits zero than M after rounding below, so do this first.
6290          */
6291         if (reduce_m_n) {
6292                 while ((m & 1) == 0 && (n & 1) == 0) {
6293                         m >>= 1;
6294                         n >>= 1;
6295                 }
6296         }
6297
6298         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6299         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6300         intel_reduce_m_n_ratio(ret_m, ret_n);
6301 }
6302
6303 void
6304 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6305                        int pixel_clock, int link_clock,
6306                        struct intel_link_m_n *m_n,
6307                        bool reduce_m_n)
6308 {
6309         m_n->tu = 64;
6310
6311         compute_m_n(bits_per_pixel * pixel_clock,
6312                     link_clock * nlanes * 8,
6313                     &m_n->gmch_m, &m_n->gmch_n,
6314                     reduce_m_n);
6315
6316         compute_m_n(pixel_clock, link_clock,
6317                     &m_n->link_m, &m_n->link_n,
6318                     reduce_m_n);
6319 }
6320
6321 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6322 {
6323         if (i915.panel_use_ssc >= 0)
6324                 return i915.panel_use_ssc != 0;
6325         return dev_priv->vbt.lvds_use_ssc
6326                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6327 }
6328
6329 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6330 {
6331         return (1 << dpll->n) << 16 | dpll->m2;
6332 }
6333
6334 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6335 {
6336         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6337 }
6338
6339 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6340                                      struct intel_crtc_state *crtc_state,
6341                                      struct dpll *reduced_clock)
6342 {
6343         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6344         u32 fp, fp2 = 0;
6345
6346         if (IS_PINEVIEW(dev_priv)) {
6347                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6348                 if (reduced_clock)
6349                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6350         } else {
6351                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6352                 if (reduced_clock)
6353                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6354         }
6355
6356         crtc_state->dpll_hw_state.fp0 = fp;
6357
6358         crtc->lowfreq_avail = false;
6359         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6360             reduced_clock) {
6361                 crtc_state->dpll_hw_state.fp1 = fp2;
6362                 crtc->lowfreq_avail = true;
6363         } else {
6364                 crtc_state->dpll_hw_state.fp1 = fp;
6365         }
6366 }
6367
6368 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6369                 pipe)
6370 {
6371         u32 reg_val;
6372
6373         /*
6374          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6375          * and set it to a reasonable value instead.
6376          */
6377         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6378         reg_val &= 0xffffff00;
6379         reg_val |= 0x00000030;
6380         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6381
6382         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6383         reg_val &= 0x8cffffff;
6384         reg_val = 0x8c000000;
6385         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6386
6387         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6388         reg_val &= 0xffffff00;
6389         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6390
6391         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6392         reg_val &= 0x00ffffff;
6393         reg_val |= 0xb0000000;
6394         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6395 }
6396
6397 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6398                                          struct intel_link_m_n *m_n)
6399 {
6400         struct drm_device *dev = crtc->base.dev;
6401         struct drm_i915_private *dev_priv = to_i915(dev);
6402         int pipe = crtc->pipe;
6403
6404         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6405         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6406         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6407         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6408 }
6409
6410 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6411                                          struct intel_link_m_n *m_n,
6412                                          struct intel_link_m_n *m2_n2)
6413 {
6414         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6415         int pipe = crtc->pipe;
6416         enum transcoder transcoder = crtc->config->cpu_transcoder;
6417
6418         if (INTEL_GEN(dev_priv) >= 5) {
6419                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6420                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6421                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6422                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6423                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6424                  * for gen < 8) and if DRRS is supported (to make sure the
6425                  * registers are not unnecessarily accessed).
6426                  */
6427                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6428                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6429                         I915_WRITE(PIPE_DATA_M2(transcoder),
6430                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6431                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6432                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6433                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6434                 }
6435         } else {
6436                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6437                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6438                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6439                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6440         }
6441 }
6442
6443 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6444 {
6445         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6446
6447         if (m_n == M1_N1) {
6448                 dp_m_n = &crtc->config->dp_m_n;
6449                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6450         } else if (m_n == M2_N2) {
6451
6452                 /*
6453                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6454                  * needs to be programmed into M1_N1.
6455                  */
6456                 dp_m_n = &crtc->config->dp_m2_n2;
6457         } else {
6458                 DRM_ERROR("Unsupported divider value\n");
6459                 return;
6460         }
6461
6462         if (crtc->config->has_pch_encoder)
6463                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6464         else
6465                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6466 }
6467
6468 static void vlv_compute_dpll(struct intel_crtc *crtc,
6469                              struct intel_crtc_state *pipe_config)
6470 {
6471         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6472                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6473         if (crtc->pipe != PIPE_A)
6474                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6475
6476         /* DPLL not used with DSI, but still need the rest set up */
6477         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6478                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6479                         DPLL_EXT_BUFFER_ENABLE_VLV;
6480
6481         pipe_config->dpll_hw_state.dpll_md =
6482                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6483 }
6484
6485 static void chv_compute_dpll(struct intel_crtc *crtc,
6486                              struct intel_crtc_state *pipe_config)
6487 {
6488         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6489                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6490         if (crtc->pipe != PIPE_A)
6491                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6492
6493         /* DPLL not used with DSI, but still need the rest set up */
6494         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6495                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6496
6497         pipe_config->dpll_hw_state.dpll_md =
6498                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6499 }
6500
6501 static void vlv_prepare_pll(struct intel_crtc *crtc,
6502                             const struct intel_crtc_state *pipe_config)
6503 {
6504         struct drm_device *dev = crtc->base.dev;
6505         struct drm_i915_private *dev_priv = to_i915(dev);
6506         enum pipe pipe = crtc->pipe;
6507         u32 mdiv;
6508         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6509         u32 coreclk, reg_val;
6510
6511         /* Enable Refclk */
6512         I915_WRITE(DPLL(pipe),
6513                    pipe_config->dpll_hw_state.dpll &
6514                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6515
6516         /* No need to actually set up the DPLL with DSI */
6517         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6518                 return;
6519
6520         mutex_lock(&dev_priv->sb_lock);
6521
6522         bestn = pipe_config->dpll.n;
6523         bestm1 = pipe_config->dpll.m1;
6524         bestm2 = pipe_config->dpll.m2;
6525         bestp1 = pipe_config->dpll.p1;
6526         bestp2 = pipe_config->dpll.p2;
6527
6528         /* See eDP HDMI DPIO driver vbios notes doc */
6529
6530         /* PLL B needs special handling */
6531         if (pipe == PIPE_B)
6532                 vlv_pllb_recal_opamp(dev_priv, pipe);
6533
6534         /* Set up Tx target for periodic Rcomp update */
6535         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6536
6537         /* Disable target IRef on PLL */
6538         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6539         reg_val &= 0x00ffffff;
6540         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6541
6542         /* Disable fast lock */
6543         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6544
6545         /* Set idtafcrecal before PLL is enabled */
6546         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6547         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6548         mdiv |= ((bestn << DPIO_N_SHIFT));
6549         mdiv |= (1 << DPIO_K_SHIFT);
6550
6551         /*
6552          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6553          * but we don't support that).
6554          * Note: don't use the DAC post divider as it seems unstable.
6555          */
6556         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6557         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6558
6559         mdiv |= DPIO_ENABLE_CALIBRATION;
6560         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6561
6562         /* Set HBR and RBR LPF coefficients */
6563         if (pipe_config->port_clock == 162000 ||
6564             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6565             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6566                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6567                                  0x009f0003);
6568         else
6569                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6570                                  0x00d0000f);
6571
6572         if (intel_crtc_has_dp_encoder(pipe_config)) {
6573                 /* Use SSC source */
6574                 if (pipe == PIPE_A)
6575                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6576                                          0x0df40000);
6577                 else
6578                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6579                                          0x0df70000);
6580         } else { /* HDMI or VGA */
6581                 /* Use bend source */
6582                 if (pipe == PIPE_A)
6583                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6584                                          0x0df70000);
6585                 else
6586                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6587                                          0x0df40000);
6588         }
6589
6590         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6591         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6592         if (intel_crtc_has_dp_encoder(crtc->config))
6593                 coreclk |= 0x01000000;
6594         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6595
6596         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6597         mutex_unlock(&dev_priv->sb_lock);
6598 }
6599
6600 static void chv_prepare_pll(struct intel_crtc *crtc,
6601                             const struct intel_crtc_state *pipe_config)
6602 {
6603         struct drm_device *dev = crtc->base.dev;
6604         struct drm_i915_private *dev_priv = to_i915(dev);
6605         enum pipe pipe = crtc->pipe;
6606         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6607         u32 loopfilter, tribuf_calcntr;
6608         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6609         u32 dpio_val;
6610         int vco;
6611
6612         /* Enable Refclk and SSC */
6613         I915_WRITE(DPLL(pipe),
6614                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6615
6616         /* No need to actually set up the DPLL with DSI */
6617         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6618                 return;
6619
6620         bestn = pipe_config->dpll.n;
6621         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6622         bestm1 = pipe_config->dpll.m1;
6623         bestm2 = pipe_config->dpll.m2 >> 22;
6624         bestp1 = pipe_config->dpll.p1;
6625         bestp2 = pipe_config->dpll.p2;
6626         vco = pipe_config->dpll.vco;
6627         dpio_val = 0;
6628         loopfilter = 0;
6629
6630         mutex_lock(&dev_priv->sb_lock);
6631
6632         /* p1 and p2 divider */
6633         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6634                         5 << DPIO_CHV_S1_DIV_SHIFT |
6635                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6636                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6637                         1 << DPIO_CHV_K_DIV_SHIFT);
6638
6639         /* Feedback post-divider - m2 */
6640         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6641
6642         /* Feedback refclk divider - n and m1 */
6643         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6644                         DPIO_CHV_M1_DIV_BY_2 |
6645                         1 << DPIO_CHV_N_DIV_SHIFT);
6646
6647         /* M2 fraction division */
6648         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6649
6650         /* M2 fraction division enable */
6651         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6652         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6653         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6654         if (bestm2_frac)
6655                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6656         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6657
6658         /* Program digital lock detect threshold */
6659         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6660         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6661                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6662         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6663         if (!bestm2_frac)
6664                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6665         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6666
6667         /* Loop filter */
6668         if (vco == 5400000) {
6669                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6670                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6671                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6672                 tribuf_calcntr = 0x9;
6673         } else if (vco <= 6200000) {
6674                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6675                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6676                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6677                 tribuf_calcntr = 0x9;
6678         } else if (vco <= 6480000) {
6679                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6680                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6681                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6682                 tribuf_calcntr = 0x8;
6683         } else {
6684                 /* Not supported. Apply the same limits as in the max case */
6685                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6686                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6687                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6688                 tribuf_calcntr = 0;
6689         }
6690         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6691
6692         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6693         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6694         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6695         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6696
6697         /* AFC Recal */
6698         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6699                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6700                         DPIO_AFC_RECAL);
6701
6702         mutex_unlock(&dev_priv->sb_lock);
6703 }
6704
6705 /**
6706  * vlv_force_pll_on - forcibly enable just the PLL
6707  * @dev_priv: i915 private structure
6708  * @pipe: pipe PLL to enable
6709  * @dpll: PLL configuration
6710  *
6711  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6712  * in cases where we need the PLL enabled even when @pipe is not going to
6713  * be enabled.
6714  */
6715 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6716                      const struct dpll *dpll)
6717 {
6718         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6719         struct intel_crtc_state *pipe_config;
6720
6721         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6722         if (!pipe_config)
6723                 return -ENOMEM;
6724
6725         pipe_config->base.crtc = &crtc->base;
6726         pipe_config->pixel_multiplier = 1;
6727         pipe_config->dpll = *dpll;
6728
6729         if (IS_CHERRYVIEW(dev_priv)) {
6730                 chv_compute_dpll(crtc, pipe_config);
6731                 chv_prepare_pll(crtc, pipe_config);
6732                 chv_enable_pll(crtc, pipe_config);
6733         } else {
6734                 vlv_compute_dpll(crtc, pipe_config);
6735                 vlv_prepare_pll(crtc, pipe_config);
6736                 vlv_enable_pll(crtc, pipe_config);
6737         }
6738
6739         kfree(pipe_config);
6740
6741         return 0;
6742 }
6743
6744 /**
6745  * vlv_force_pll_off - forcibly disable just the PLL
6746  * @dev_priv: i915 private structure
6747  * @pipe: pipe PLL to disable
6748  *
6749  * Disable the PLL for @pipe. To be used in cases where we need
6750  * the PLL enabled even when @pipe is not going to be enabled.
6751  */
6752 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6753 {
6754         if (IS_CHERRYVIEW(dev_priv))
6755                 chv_disable_pll(dev_priv, pipe);
6756         else
6757                 vlv_disable_pll(dev_priv, pipe);
6758 }
6759
6760 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6761                               struct intel_crtc_state *crtc_state,
6762                               struct dpll *reduced_clock)
6763 {
6764         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6765         u32 dpll;
6766         struct dpll *clock = &crtc_state->dpll;
6767
6768         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6769
6770         dpll = DPLL_VGA_MODE_DIS;
6771
6772         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6773                 dpll |= DPLLB_MODE_LVDS;
6774         else
6775                 dpll |= DPLLB_MODE_DAC_SERIAL;
6776
6777         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6778             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6779                 dpll |= (crtc_state->pixel_multiplier - 1)
6780                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6781         }
6782
6783         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6784             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6785                 dpll |= DPLL_SDVO_HIGH_SPEED;
6786
6787         if (intel_crtc_has_dp_encoder(crtc_state))
6788                 dpll |= DPLL_SDVO_HIGH_SPEED;
6789
6790         /* compute bitmask from p1 value */
6791         if (IS_PINEVIEW(dev_priv))
6792                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6793         else {
6794                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6795                 if (IS_G4X(dev_priv) && reduced_clock)
6796                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6797         }
6798         switch (clock->p2) {
6799         case 5:
6800                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6801                 break;
6802         case 7:
6803                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6804                 break;
6805         case 10:
6806                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6807                 break;
6808         case 14:
6809                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6810                 break;
6811         }
6812         if (INTEL_GEN(dev_priv) >= 4)
6813                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6814
6815         if (crtc_state->sdvo_tv_clock)
6816                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6817         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6818                  intel_panel_use_ssc(dev_priv))
6819                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6820         else
6821                 dpll |= PLL_REF_INPUT_DREFCLK;
6822
6823         dpll |= DPLL_VCO_ENABLE;
6824         crtc_state->dpll_hw_state.dpll = dpll;
6825
6826         if (INTEL_GEN(dev_priv) >= 4) {
6827                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6828                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6829                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6830         }
6831 }
6832
6833 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6834                               struct intel_crtc_state *crtc_state,
6835                               struct dpll *reduced_clock)
6836 {
6837         struct drm_device *dev = crtc->base.dev;
6838         struct drm_i915_private *dev_priv = to_i915(dev);
6839         u32 dpll;
6840         struct dpll *clock = &crtc_state->dpll;
6841
6842         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6843
6844         dpll = DPLL_VGA_MODE_DIS;
6845
6846         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6847                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6848         } else {
6849                 if (clock->p1 == 2)
6850                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6851                 else
6852                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6853                 if (clock->p2 == 4)
6854                         dpll |= PLL_P2_DIVIDE_BY_4;
6855         }
6856
6857         if (!IS_I830(dev_priv) &&
6858             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6859                 dpll |= DPLL_DVO_2X_MODE;
6860
6861         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6862             intel_panel_use_ssc(dev_priv))
6863                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6864         else
6865                 dpll |= PLL_REF_INPUT_DREFCLK;
6866
6867         dpll |= DPLL_VCO_ENABLE;
6868         crtc_state->dpll_hw_state.dpll = dpll;
6869 }
6870
6871 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6872 {
6873         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6874         enum pipe pipe = intel_crtc->pipe;
6875         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6876         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6877         uint32_t crtc_vtotal, crtc_vblank_end;
6878         int vsyncshift = 0;
6879
6880         /* We need to be careful not to changed the adjusted mode, for otherwise
6881          * the hw state checker will get angry at the mismatch. */
6882         crtc_vtotal = adjusted_mode->crtc_vtotal;
6883         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6884
6885         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6886                 /* the chip adds 2 halflines automatically */
6887                 crtc_vtotal -= 1;
6888                 crtc_vblank_end -= 1;
6889
6890                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6891                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6892                 else
6893                         vsyncshift = adjusted_mode->crtc_hsync_start -
6894                                 adjusted_mode->crtc_htotal / 2;
6895                 if (vsyncshift < 0)
6896                         vsyncshift += adjusted_mode->crtc_htotal;
6897         }
6898
6899         if (INTEL_GEN(dev_priv) > 3)
6900                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6901
6902         I915_WRITE(HTOTAL(cpu_transcoder),
6903                    (adjusted_mode->crtc_hdisplay - 1) |
6904                    ((adjusted_mode->crtc_htotal - 1) << 16));
6905         I915_WRITE(HBLANK(cpu_transcoder),
6906                    (adjusted_mode->crtc_hblank_start - 1) |
6907                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6908         I915_WRITE(HSYNC(cpu_transcoder),
6909                    (adjusted_mode->crtc_hsync_start - 1) |
6910                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6911
6912         I915_WRITE(VTOTAL(cpu_transcoder),
6913                    (adjusted_mode->crtc_vdisplay - 1) |
6914                    ((crtc_vtotal - 1) << 16));
6915         I915_WRITE(VBLANK(cpu_transcoder),
6916                    (adjusted_mode->crtc_vblank_start - 1) |
6917                    ((crtc_vblank_end - 1) << 16));
6918         I915_WRITE(VSYNC(cpu_transcoder),
6919                    (adjusted_mode->crtc_vsync_start - 1) |
6920                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6921
6922         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6923          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6924          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6925          * bits. */
6926         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6927             (pipe == PIPE_B || pipe == PIPE_C))
6928                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6929
6930 }
6931
6932 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6933 {
6934         struct drm_device *dev = intel_crtc->base.dev;
6935         struct drm_i915_private *dev_priv = to_i915(dev);
6936         enum pipe pipe = intel_crtc->pipe;
6937
6938         /* pipesrc controls the size that is scaled from, which should
6939          * always be the user's requested size.
6940          */
6941         I915_WRITE(PIPESRC(pipe),
6942                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6943                    (intel_crtc->config->pipe_src_h - 1));
6944 }
6945
6946 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6947                                    struct intel_crtc_state *pipe_config)
6948 {
6949         struct drm_device *dev = crtc->base.dev;
6950         struct drm_i915_private *dev_priv = to_i915(dev);
6951         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6952         uint32_t tmp;
6953
6954         tmp = I915_READ(HTOTAL(cpu_transcoder));
6955         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6956         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6957         tmp = I915_READ(HBLANK(cpu_transcoder));
6958         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6959         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6960         tmp = I915_READ(HSYNC(cpu_transcoder));
6961         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6962         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6963
6964         tmp = I915_READ(VTOTAL(cpu_transcoder));
6965         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6966         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6967         tmp = I915_READ(VBLANK(cpu_transcoder));
6968         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6969         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6970         tmp = I915_READ(VSYNC(cpu_transcoder));
6971         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6972         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6973
6974         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6975                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6976                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6977                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6978         }
6979 }
6980
6981 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
6982                                     struct intel_crtc_state *pipe_config)
6983 {
6984         struct drm_device *dev = crtc->base.dev;
6985         struct drm_i915_private *dev_priv = to_i915(dev);
6986         u32 tmp;
6987
6988         tmp = I915_READ(PIPESRC(crtc->pipe));
6989         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6990         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6991
6992         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6993         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6994 }
6995
6996 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6997                                  struct intel_crtc_state *pipe_config)
6998 {
6999         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7000         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7001         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7002         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7003
7004         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7005         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7006         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7007         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7008
7009         mode->flags = pipe_config->base.adjusted_mode.flags;
7010         mode->type = DRM_MODE_TYPE_DRIVER;
7011
7012         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7013
7014         mode->hsync = drm_mode_hsync(mode);
7015         mode->vrefresh = drm_mode_vrefresh(mode);
7016         drm_mode_set_name(mode);
7017 }
7018
7019 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7020 {
7021         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7022         uint32_t pipeconf;
7023
7024         pipeconf = 0;
7025
7026         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7027             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7028                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7029
7030         if (intel_crtc->config->double_wide)
7031                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7032
7033         /* only g4x and later have fancy bpc/dither controls */
7034         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7035             IS_CHERRYVIEW(dev_priv)) {
7036                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7037                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7038                         pipeconf |= PIPECONF_DITHER_EN |
7039                                     PIPECONF_DITHER_TYPE_SP;
7040
7041                 switch (intel_crtc->config->pipe_bpp) {
7042                 case 18:
7043                         pipeconf |= PIPECONF_6BPC;
7044                         break;
7045                 case 24:
7046                         pipeconf |= PIPECONF_8BPC;
7047                         break;
7048                 case 30:
7049                         pipeconf |= PIPECONF_10BPC;
7050                         break;
7051                 default:
7052                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7053                         BUG();
7054                 }
7055         }
7056
7057         if (HAS_PIPE_CXSR(dev_priv)) {
7058                 if (intel_crtc->lowfreq_avail) {
7059                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7060                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7061                 } else {
7062                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7063                 }
7064         }
7065
7066         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7067                 if (INTEL_GEN(dev_priv) < 4 ||
7068                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7069                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7070                 else
7071                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7072         } else
7073                 pipeconf |= PIPECONF_PROGRESSIVE;
7074
7075         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7076              intel_crtc->config->limited_color_range)
7077                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7078
7079         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7080         POSTING_READ(PIPECONF(intel_crtc->pipe));
7081 }
7082
7083 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7084                                    struct intel_crtc_state *crtc_state)
7085 {
7086         struct drm_device *dev = crtc->base.dev;
7087         struct drm_i915_private *dev_priv = to_i915(dev);
7088         const struct intel_limit *limit;
7089         int refclk = 48000;
7090
7091         memset(&crtc_state->dpll_hw_state, 0,
7092                sizeof(crtc_state->dpll_hw_state));
7093
7094         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7095                 if (intel_panel_use_ssc(dev_priv)) {
7096                         refclk = dev_priv->vbt.lvds_ssc_freq;
7097                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7098                 }
7099
7100                 limit = &intel_limits_i8xx_lvds;
7101         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7102                 limit = &intel_limits_i8xx_dvo;
7103         } else {
7104                 limit = &intel_limits_i8xx_dac;
7105         }
7106
7107         if (!crtc_state->clock_set &&
7108             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7109                                  refclk, NULL, &crtc_state->dpll)) {
7110                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7111                 return -EINVAL;
7112         }
7113
7114         i8xx_compute_dpll(crtc, crtc_state, NULL);
7115
7116         return 0;
7117 }
7118
7119 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7120                                   struct intel_crtc_state *crtc_state)
7121 {
7122         struct drm_device *dev = crtc->base.dev;
7123         struct drm_i915_private *dev_priv = to_i915(dev);
7124         const struct intel_limit *limit;
7125         int refclk = 96000;
7126
7127         memset(&crtc_state->dpll_hw_state, 0,
7128                sizeof(crtc_state->dpll_hw_state));
7129
7130         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7131                 if (intel_panel_use_ssc(dev_priv)) {
7132                         refclk = dev_priv->vbt.lvds_ssc_freq;
7133                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7134                 }
7135
7136                 if (intel_is_dual_link_lvds(dev))
7137                         limit = &intel_limits_g4x_dual_channel_lvds;
7138                 else
7139                         limit = &intel_limits_g4x_single_channel_lvds;
7140         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7141                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7142                 limit = &intel_limits_g4x_hdmi;
7143         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7144                 limit = &intel_limits_g4x_sdvo;
7145         } else {
7146                 /* The option is for other outputs */
7147                 limit = &intel_limits_i9xx_sdvo;
7148         }
7149
7150         if (!crtc_state->clock_set &&
7151             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7152                                 refclk, NULL, &crtc_state->dpll)) {
7153                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7154                 return -EINVAL;
7155         }
7156
7157         i9xx_compute_dpll(crtc, crtc_state, NULL);
7158
7159         return 0;
7160 }
7161
7162 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7163                                   struct intel_crtc_state *crtc_state)
7164 {
7165         struct drm_device *dev = crtc->base.dev;
7166         struct drm_i915_private *dev_priv = to_i915(dev);
7167         const struct intel_limit *limit;
7168         int refclk = 96000;
7169
7170         memset(&crtc_state->dpll_hw_state, 0,
7171                sizeof(crtc_state->dpll_hw_state));
7172
7173         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7174                 if (intel_panel_use_ssc(dev_priv)) {
7175                         refclk = dev_priv->vbt.lvds_ssc_freq;
7176                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7177                 }
7178
7179                 limit = &intel_limits_pineview_lvds;
7180         } else {
7181                 limit = &intel_limits_pineview_sdvo;
7182         }
7183
7184         if (!crtc_state->clock_set &&
7185             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7186                                 refclk, NULL, &crtc_state->dpll)) {
7187                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7188                 return -EINVAL;
7189         }
7190
7191         i9xx_compute_dpll(crtc, crtc_state, NULL);
7192
7193         return 0;
7194 }
7195
7196 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7197                                    struct intel_crtc_state *crtc_state)
7198 {
7199         struct drm_device *dev = crtc->base.dev;
7200         struct drm_i915_private *dev_priv = to_i915(dev);
7201         const struct intel_limit *limit;
7202         int refclk = 96000;
7203
7204         memset(&crtc_state->dpll_hw_state, 0,
7205                sizeof(crtc_state->dpll_hw_state));
7206
7207         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7208                 if (intel_panel_use_ssc(dev_priv)) {
7209                         refclk = dev_priv->vbt.lvds_ssc_freq;
7210                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7211                 }
7212
7213                 limit = &intel_limits_i9xx_lvds;
7214         } else {
7215                 limit = &intel_limits_i9xx_sdvo;
7216         }
7217
7218         if (!crtc_state->clock_set &&
7219             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7220                                  refclk, NULL, &crtc_state->dpll)) {
7221                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7222                 return -EINVAL;
7223         }
7224
7225         i9xx_compute_dpll(crtc, crtc_state, NULL);
7226
7227         return 0;
7228 }
7229
7230 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7231                                   struct intel_crtc_state *crtc_state)
7232 {
7233         int refclk = 100000;
7234         const struct intel_limit *limit = &intel_limits_chv;
7235
7236         memset(&crtc_state->dpll_hw_state, 0,
7237                sizeof(crtc_state->dpll_hw_state));
7238
7239         if (!crtc_state->clock_set &&
7240             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7241                                 refclk, NULL, &crtc_state->dpll)) {
7242                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7243                 return -EINVAL;
7244         }
7245
7246         chv_compute_dpll(crtc, crtc_state);
7247
7248         return 0;
7249 }
7250
7251 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7252                                   struct intel_crtc_state *crtc_state)
7253 {
7254         int refclk = 100000;
7255         const struct intel_limit *limit = &intel_limits_vlv;
7256
7257         memset(&crtc_state->dpll_hw_state, 0,
7258                sizeof(crtc_state->dpll_hw_state));
7259
7260         if (!crtc_state->clock_set &&
7261             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7262                                 refclk, NULL, &crtc_state->dpll)) {
7263                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7264                 return -EINVAL;
7265         }
7266
7267         vlv_compute_dpll(crtc, crtc_state);
7268
7269         return 0;
7270 }
7271
7272 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7273                                  struct intel_crtc_state *pipe_config)
7274 {
7275         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7276         uint32_t tmp;
7277
7278         if (INTEL_GEN(dev_priv) <= 3 &&
7279             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7280                 return;
7281
7282         tmp = I915_READ(PFIT_CONTROL);
7283         if (!(tmp & PFIT_ENABLE))
7284                 return;
7285
7286         /* Check whether the pfit is attached to our pipe. */
7287         if (INTEL_GEN(dev_priv) < 4) {
7288                 if (crtc->pipe != PIPE_B)
7289                         return;
7290         } else {
7291                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7292                         return;
7293         }
7294
7295         pipe_config->gmch_pfit.control = tmp;
7296         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7297 }
7298
7299 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7300                                struct intel_crtc_state *pipe_config)
7301 {
7302         struct drm_device *dev = crtc->base.dev;
7303         struct drm_i915_private *dev_priv = to_i915(dev);
7304         int pipe = pipe_config->cpu_transcoder;
7305         struct dpll clock;
7306         u32 mdiv;
7307         int refclk = 100000;
7308
7309         /* In case of DSI, DPLL will not be used */
7310         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7311                 return;
7312
7313         mutex_lock(&dev_priv->sb_lock);
7314         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7315         mutex_unlock(&dev_priv->sb_lock);
7316
7317         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7318         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7319         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7320         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7321         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7322
7323         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7324 }
7325
7326 static void
7327 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7328                               struct intel_initial_plane_config *plane_config)
7329 {
7330         struct drm_device *dev = crtc->base.dev;
7331         struct drm_i915_private *dev_priv = to_i915(dev);
7332         u32 val, base, offset;
7333         int pipe = crtc->pipe, plane = crtc->plane;
7334         int fourcc, pixel_format;
7335         unsigned int aligned_height;
7336         struct drm_framebuffer *fb;
7337         struct intel_framebuffer *intel_fb;
7338
7339         val = I915_READ(DSPCNTR(plane));
7340         if (!(val & DISPLAY_PLANE_ENABLE))
7341                 return;
7342
7343         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7344         if (!intel_fb) {
7345                 DRM_DEBUG_KMS("failed to alloc fb\n");
7346                 return;
7347         }
7348
7349         fb = &intel_fb->base;
7350
7351         fb->dev = dev;
7352
7353         if (INTEL_GEN(dev_priv) >= 4) {
7354                 if (val & DISPPLANE_TILED) {
7355                         plane_config->tiling = I915_TILING_X;
7356                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7357                 }
7358         }
7359
7360         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7361         fourcc = i9xx_format_to_fourcc(pixel_format);
7362         fb->format = drm_format_info(fourcc);
7363
7364         if (INTEL_GEN(dev_priv) >= 4) {
7365                 if (plane_config->tiling)
7366                         offset = I915_READ(DSPTILEOFF(plane));
7367                 else
7368                         offset = I915_READ(DSPLINOFF(plane));
7369                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7370         } else {
7371                 base = I915_READ(DSPADDR(plane));
7372         }
7373         plane_config->base = base;
7374
7375         val = I915_READ(PIPESRC(pipe));
7376         fb->width = ((val >> 16) & 0xfff) + 1;
7377         fb->height = ((val >> 0) & 0xfff) + 1;
7378
7379         val = I915_READ(DSPSTRIDE(pipe));
7380         fb->pitches[0] = val & 0xffffffc0;
7381
7382         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7383
7384         plane_config->size = fb->pitches[0] * aligned_height;
7385
7386         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7387                       pipe_name(pipe), plane, fb->width, fb->height,
7388                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7389                       plane_config->size);
7390
7391         plane_config->fb = intel_fb;
7392 }
7393
7394 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7395                                struct intel_crtc_state *pipe_config)
7396 {
7397         struct drm_device *dev = crtc->base.dev;
7398         struct drm_i915_private *dev_priv = to_i915(dev);
7399         int pipe = pipe_config->cpu_transcoder;
7400         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7401         struct dpll clock;
7402         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7403         int refclk = 100000;
7404
7405         /* In case of DSI, DPLL will not be used */
7406         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7407                 return;
7408
7409         mutex_lock(&dev_priv->sb_lock);
7410         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7411         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7412         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7413         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7414         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7415         mutex_unlock(&dev_priv->sb_lock);
7416
7417         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7418         clock.m2 = (pll_dw0 & 0xff) << 22;
7419         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7420                 clock.m2 |= pll_dw2 & 0x3fffff;
7421         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7422         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7423         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7424
7425         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7426 }
7427
7428 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7429                                  struct intel_crtc_state *pipe_config)
7430 {
7431         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7432         enum intel_display_power_domain power_domain;
7433         uint32_t tmp;
7434         bool ret;
7435
7436         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7437         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7438                 return false;
7439
7440         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7441         pipe_config->shared_dpll = NULL;
7442
7443         ret = false;
7444
7445         tmp = I915_READ(PIPECONF(crtc->pipe));
7446         if (!(tmp & PIPECONF_ENABLE))
7447                 goto out;
7448
7449         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7450             IS_CHERRYVIEW(dev_priv)) {
7451                 switch (tmp & PIPECONF_BPC_MASK) {
7452                 case PIPECONF_6BPC:
7453                         pipe_config->pipe_bpp = 18;
7454                         break;
7455                 case PIPECONF_8BPC:
7456                         pipe_config->pipe_bpp = 24;
7457                         break;
7458                 case PIPECONF_10BPC:
7459                         pipe_config->pipe_bpp = 30;
7460                         break;
7461                 default:
7462                         break;
7463                 }
7464         }
7465
7466         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7467             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7468                 pipe_config->limited_color_range = true;
7469
7470         if (INTEL_GEN(dev_priv) < 4)
7471                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7472
7473         intel_get_pipe_timings(crtc, pipe_config);
7474         intel_get_pipe_src_size(crtc, pipe_config);
7475
7476         i9xx_get_pfit_config(crtc, pipe_config);
7477
7478         if (INTEL_GEN(dev_priv) >= 4) {
7479                 /* No way to read it out on pipes B and C */
7480                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7481                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7482                 else
7483                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7484                 pipe_config->pixel_multiplier =
7485                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7486                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7487                 pipe_config->dpll_hw_state.dpll_md = tmp;
7488         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7489                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7490                 tmp = I915_READ(DPLL(crtc->pipe));
7491                 pipe_config->pixel_multiplier =
7492                         ((tmp & SDVO_MULTIPLIER_MASK)
7493                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7494         } else {
7495                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7496                  * port and will be fixed up in the encoder->get_config
7497                  * function. */
7498                 pipe_config->pixel_multiplier = 1;
7499         }
7500         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7501         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7502                 /*
7503                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7504                  * on 830. Filter it out here so that we don't
7505                  * report errors due to that.
7506                  */
7507                 if (IS_I830(dev_priv))
7508                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7509
7510                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7511                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7512         } else {
7513                 /* Mask out read-only status bits. */
7514                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7515                                                      DPLL_PORTC_READY_MASK |
7516                                                      DPLL_PORTB_READY_MASK);
7517         }
7518
7519         if (IS_CHERRYVIEW(dev_priv))
7520                 chv_crtc_clock_get(crtc, pipe_config);
7521         else if (IS_VALLEYVIEW(dev_priv))
7522                 vlv_crtc_clock_get(crtc, pipe_config);
7523         else
7524                 i9xx_crtc_clock_get(crtc, pipe_config);
7525
7526         /*
7527          * Normally the dotclock is filled in by the encoder .get_config()
7528          * but in case the pipe is enabled w/o any ports we need a sane
7529          * default.
7530          */
7531         pipe_config->base.adjusted_mode.crtc_clock =
7532                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7533
7534         ret = true;
7535
7536 out:
7537         intel_display_power_put(dev_priv, power_domain);
7538
7539         return ret;
7540 }
7541
7542 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7543 {
7544         struct intel_encoder *encoder;
7545         int i;
7546         u32 val, final;
7547         bool has_lvds = false;
7548         bool has_cpu_edp = false;
7549         bool has_panel = false;
7550         bool has_ck505 = false;
7551         bool can_ssc = false;
7552         bool using_ssc_source = false;
7553
7554         /* We need to take the global config into account */
7555         for_each_intel_encoder(&dev_priv->drm, encoder) {
7556                 switch (encoder->type) {
7557                 case INTEL_OUTPUT_LVDS:
7558                         has_panel = true;
7559                         has_lvds = true;
7560                         break;
7561                 case INTEL_OUTPUT_EDP:
7562                         has_panel = true;
7563                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7564                                 has_cpu_edp = true;
7565                         break;
7566                 default:
7567                         break;
7568                 }
7569         }
7570
7571         if (HAS_PCH_IBX(dev_priv)) {
7572                 has_ck505 = dev_priv->vbt.display_clock_mode;
7573                 can_ssc = has_ck505;
7574         } else {
7575                 has_ck505 = false;
7576                 can_ssc = true;
7577         }
7578
7579         /* Check if any DPLLs are using the SSC source */
7580         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7581                 u32 temp = I915_READ(PCH_DPLL(i));
7582
7583                 if (!(temp & DPLL_VCO_ENABLE))
7584                         continue;
7585
7586                 if ((temp & PLL_REF_INPUT_MASK) ==
7587                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7588                         using_ssc_source = true;
7589                         break;
7590                 }
7591         }
7592
7593         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7594                       has_panel, has_lvds, has_ck505, using_ssc_source);
7595
7596         /* Ironlake: try to setup display ref clock before DPLL
7597          * enabling. This is only under driver's control after
7598          * PCH B stepping, previous chipset stepping should be
7599          * ignoring this setting.
7600          */
7601         val = I915_READ(PCH_DREF_CONTROL);
7602
7603         /* As we must carefully and slowly disable/enable each source in turn,
7604          * compute the final state we want first and check if we need to
7605          * make any changes at all.
7606          */
7607         final = val;
7608         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7609         if (has_ck505)
7610                 final |= DREF_NONSPREAD_CK505_ENABLE;
7611         else
7612                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7613
7614         final &= ~DREF_SSC_SOURCE_MASK;
7615         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7616         final &= ~DREF_SSC1_ENABLE;
7617
7618         if (has_panel) {
7619                 final |= DREF_SSC_SOURCE_ENABLE;
7620
7621                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7622                         final |= DREF_SSC1_ENABLE;
7623
7624                 if (has_cpu_edp) {
7625                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7626                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7627                         else
7628                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7629                 } else
7630                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7631         } else if (using_ssc_source) {
7632                 final |= DREF_SSC_SOURCE_ENABLE;
7633                 final |= DREF_SSC1_ENABLE;
7634         }
7635
7636         if (final == val)
7637                 return;
7638
7639         /* Always enable nonspread source */
7640         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7641
7642         if (has_ck505)
7643                 val |= DREF_NONSPREAD_CK505_ENABLE;
7644         else
7645                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7646
7647         if (has_panel) {
7648                 val &= ~DREF_SSC_SOURCE_MASK;
7649                 val |= DREF_SSC_SOURCE_ENABLE;
7650
7651                 /* SSC must be turned on before enabling the CPU output  */
7652                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7653                         DRM_DEBUG_KMS("Using SSC on panel\n");
7654                         val |= DREF_SSC1_ENABLE;
7655                 } else
7656                         val &= ~DREF_SSC1_ENABLE;
7657
7658                 /* Get SSC going before enabling the outputs */
7659                 I915_WRITE(PCH_DREF_CONTROL, val);
7660                 POSTING_READ(PCH_DREF_CONTROL);
7661                 udelay(200);
7662
7663                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7664
7665                 /* Enable CPU source on CPU attached eDP */
7666                 if (has_cpu_edp) {
7667                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7668                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7669                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7670                         } else
7671                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7672                 } else
7673                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7674
7675                 I915_WRITE(PCH_DREF_CONTROL, val);
7676                 POSTING_READ(PCH_DREF_CONTROL);
7677                 udelay(200);
7678         } else {
7679                 DRM_DEBUG_KMS("Disabling CPU source output\n");
7680
7681                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7682
7683                 /* Turn off CPU output */
7684                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7685
7686                 I915_WRITE(PCH_DREF_CONTROL, val);
7687                 POSTING_READ(PCH_DREF_CONTROL);
7688                 udelay(200);
7689
7690                 if (!using_ssc_source) {
7691                         DRM_DEBUG_KMS("Disabling SSC source\n");
7692
7693                         /* Turn off the SSC source */
7694                         val &= ~DREF_SSC_SOURCE_MASK;
7695                         val |= DREF_SSC_SOURCE_DISABLE;
7696
7697                         /* Turn off SSC1 */
7698                         val &= ~DREF_SSC1_ENABLE;
7699
7700                         I915_WRITE(PCH_DREF_CONTROL, val);
7701                         POSTING_READ(PCH_DREF_CONTROL);
7702                         udelay(200);
7703                 }
7704         }
7705
7706         BUG_ON(val != final);
7707 }
7708
7709 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7710 {
7711         uint32_t tmp;
7712
7713         tmp = I915_READ(SOUTH_CHICKEN2);
7714         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7715         I915_WRITE(SOUTH_CHICKEN2, tmp);
7716
7717         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7718                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7719                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7720
7721         tmp = I915_READ(SOUTH_CHICKEN2);
7722         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7723         I915_WRITE(SOUTH_CHICKEN2, tmp);
7724
7725         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7726                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7727                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7728 }
7729
7730 /* WaMPhyProgramming:hsw */
7731 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7732 {
7733         uint32_t tmp;
7734
7735         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7736         tmp &= ~(0xFF << 24);
7737         tmp |= (0x12 << 24);
7738         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7739
7740         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7741         tmp |= (1 << 11);
7742         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7743
7744         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7745         tmp |= (1 << 11);
7746         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7747
7748         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7749         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7750         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7751
7752         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7753         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7754         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7755
7756         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7757         tmp &= ~(7 << 13);
7758         tmp |= (5 << 13);
7759         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7760
7761         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7762         tmp &= ~(7 << 13);
7763         tmp |= (5 << 13);
7764         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7765
7766         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7767         tmp &= ~0xFF;
7768         tmp |= 0x1C;
7769         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7770
7771         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7772         tmp &= ~0xFF;
7773         tmp |= 0x1C;
7774         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7775
7776         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7777         tmp &= ~(0xFF << 16);
7778         tmp |= (0x1C << 16);
7779         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7780
7781         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7782         tmp &= ~(0xFF << 16);
7783         tmp |= (0x1C << 16);
7784         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7785
7786         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7787         tmp |= (1 << 27);
7788         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7789
7790         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7791         tmp |= (1 << 27);
7792         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7793
7794         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7795         tmp &= ~(0xF << 28);
7796         tmp |= (4 << 28);
7797         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7798
7799         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7800         tmp &= ~(0xF << 28);
7801         tmp |= (4 << 28);
7802         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7803 }
7804
7805 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7806  * Programming" based on the parameters passed:
7807  * - Sequence to enable CLKOUT_DP
7808  * - Sequence to enable CLKOUT_DP without spread
7809  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7810  */
7811 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7812                                  bool with_spread, bool with_fdi)
7813 {
7814         uint32_t reg, tmp;
7815
7816         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7817                 with_spread = true;
7818         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7819             with_fdi, "LP PCH doesn't have FDI\n"))
7820                 with_fdi = false;
7821
7822         mutex_lock(&dev_priv->sb_lock);
7823
7824         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7825         tmp &= ~SBI_SSCCTL_DISABLE;
7826         tmp |= SBI_SSCCTL_PATHALT;
7827         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7828
7829         udelay(24);
7830
7831         if (with_spread) {
7832                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7833                 tmp &= ~SBI_SSCCTL_PATHALT;
7834                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7835
7836                 if (with_fdi) {
7837                         lpt_reset_fdi_mphy(dev_priv);
7838                         lpt_program_fdi_mphy(dev_priv);
7839                 }
7840         }
7841
7842         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7843         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7844         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7845         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7846
7847         mutex_unlock(&dev_priv->sb_lock);
7848 }
7849
7850 /* Sequence to disable CLKOUT_DP */
7851 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7852 {
7853         uint32_t reg, tmp;
7854
7855         mutex_lock(&dev_priv->sb_lock);
7856
7857         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7858         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7859         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7860         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7861
7862         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7863         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7864                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7865                         tmp |= SBI_SSCCTL_PATHALT;
7866                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7867                         udelay(32);
7868                 }
7869                 tmp |= SBI_SSCCTL_DISABLE;
7870                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7871         }
7872
7873         mutex_unlock(&dev_priv->sb_lock);
7874 }
7875
7876 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7877
7878 static const uint16_t sscdivintphase[] = {
7879         [BEND_IDX( 50)] = 0x3B23,
7880         [BEND_IDX( 45)] = 0x3B23,
7881         [BEND_IDX( 40)] = 0x3C23,
7882         [BEND_IDX( 35)] = 0x3C23,
7883         [BEND_IDX( 30)] = 0x3D23,
7884         [BEND_IDX( 25)] = 0x3D23,
7885         [BEND_IDX( 20)] = 0x3E23,
7886         [BEND_IDX( 15)] = 0x3E23,
7887         [BEND_IDX( 10)] = 0x3F23,
7888         [BEND_IDX(  5)] = 0x3F23,
7889         [BEND_IDX(  0)] = 0x0025,
7890         [BEND_IDX( -5)] = 0x0025,
7891         [BEND_IDX(-10)] = 0x0125,
7892         [BEND_IDX(-15)] = 0x0125,
7893         [BEND_IDX(-20)] = 0x0225,
7894         [BEND_IDX(-25)] = 0x0225,
7895         [BEND_IDX(-30)] = 0x0325,
7896         [BEND_IDX(-35)] = 0x0325,
7897         [BEND_IDX(-40)] = 0x0425,
7898         [BEND_IDX(-45)] = 0x0425,
7899         [BEND_IDX(-50)] = 0x0525,
7900 };
7901
7902 /*
7903  * Bend CLKOUT_DP
7904  * steps -50 to 50 inclusive, in steps of 5
7905  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7906  * change in clock period = -(steps / 10) * 5.787 ps
7907  */
7908 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7909 {
7910         uint32_t tmp;
7911         int idx = BEND_IDX(steps);
7912
7913         if (WARN_ON(steps % 5 != 0))
7914                 return;
7915
7916         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7917                 return;
7918
7919         mutex_lock(&dev_priv->sb_lock);
7920
7921         if (steps % 10 != 0)
7922                 tmp = 0xAAAAAAAB;
7923         else
7924                 tmp = 0x00000000;
7925         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7926
7927         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7928         tmp &= 0xffff0000;
7929         tmp |= sscdivintphase[idx];
7930         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7931
7932         mutex_unlock(&dev_priv->sb_lock);
7933 }
7934
7935 #undef BEND_IDX
7936
7937 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7938 {
7939         struct intel_encoder *encoder;
7940         bool has_vga = false;
7941
7942         for_each_intel_encoder(&dev_priv->drm, encoder) {
7943                 switch (encoder->type) {
7944                 case INTEL_OUTPUT_ANALOG:
7945                         has_vga = true;
7946                         break;
7947                 default:
7948                         break;
7949                 }
7950         }
7951
7952         if (has_vga) {
7953                 lpt_bend_clkout_dp(dev_priv, 0);
7954                 lpt_enable_clkout_dp(dev_priv, true, true);
7955         } else {
7956                 lpt_disable_clkout_dp(dev_priv);
7957         }
7958 }
7959
7960 /*
7961  * Initialize reference clocks when the driver loads
7962  */
7963 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7964 {
7965         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7966                 ironlake_init_pch_refclk(dev_priv);
7967         else if (HAS_PCH_LPT(dev_priv))
7968                 lpt_init_pch_refclk(dev_priv);
7969 }
7970
7971 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7972 {
7973         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7975         int pipe = intel_crtc->pipe;
7976         uint32_t val;
7977
7978         val = 0;
7979
7980         switch (intel_crtc->config->pipe_bpp) {
7981         case 18:
7982                 val |= PIPECONF_6BPC;
7983                 break;
7984         case 24:
7985                 val |= PIPECONF_8BPC;
7986                 break;
7987         case 30:
7988                 val |= PIPECONF_10BPC;
7989                 break;
7990         case 36:
7991                 val |= PIPECONF_12BPC;
7992                 break;
7993         default:
7994                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7995                 BUG();
7996         }
7997
7998         if (intel_crtc->config->dither)
7999                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8000
8001         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8002                 val |= PIPECONF_INTERLACED_ILK;
8003         else
8004                 val |= PIPECONF_PROGRESSIVE;
8005
8006         if (intel_crtc->config->limited_color_range)
8007                 val |= PIPECONF_COLOR_RANGE_SELECT;
8008
8009         I915_WRITE(PIPECONF(pipe), val);
8010         POSTING_READ(PIPECONF(pipe));
8011 }
8012
8013 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8014 {
8015         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8017         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8018         u32 val = 0;
8019
8020         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8021                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8022
8023         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8024                 val |= PIPECONF_INTERLACED_ILK;
8025         else
8026                 val |= PIPECONF_PROGRESSIVE;
8027
8028         I915_WRITE(PIPECONF(cpu_transcoder), val);
8029         POSTING_READ(PIPECONF(cpu_transcoder));
8030 }
8031
8032 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8033 {
8034         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8035         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8036
8037         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8038                 u32 val = 0;
8039
8040                 switch (intel_crtc->config->pipe_bpp) {
8041                 case 18:
8042                         val |= PIPEMISC_DITHER_6_BPC;
8043                         break;
8044                 case 24:
8045                         val |= PIPEMISC_DITHER_8_BPC;
8046                         break;
8047                 case 30:
8048                         val |= PIPEMISC_DITHER_10_BPC;
8049                         break;
8050                 case 36:
8051                         val |= PIPEMISC_DITHER_12_BPC;
8052                         break;
8053                 default:
8054                         /* Case prevented by pipe_config_set_bpp. */
8055                         BUG();
8056                 }
8057
8058                 if (intel_crtc->config->dither)
8059                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8060
8061                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8062         }
8063 }
8064
8065 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8066 {
8067         /*
8068          * Account for spread spectrum to avoid
8069          * oversubscribing the link. Max center spread
8070          * is 2.5%; use 5% for safety's sake.
8071          */
8072         u32 bps = target_clock * bpp * 21 / 20;
8073         return DIV_ROUND_UP(bps, link_bw * 8);
8074 }
8075
8076 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8077 {
8078         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8079 }
8080
8081 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8082                                   struct intel_crtc_state *crtc_state,
8083                                   struct dpll *reduced_clock)
8084 {
8085         struct drm_crtc *crtc = &intel_crtc->base;
8086         struct drm_device *dev = crtc->dev;
8087         struct drm_i915_private *dev_priv = to_i915(dev);
8088         u32 dpll, fp, fp2;
8089         int factor;
8090
8091         /* Enable autotuning of the PLL clock (if permissible) */
8092         factor = 21;
8093         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8094                 if ((intel_panel_use_ssc(dev_priv) &&
8095                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8096                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8097                         factor = 25;
8098         } else if (crtc_state->sdvo_tv_clock)
8099                 factor = 20;
8100
8101         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8102
8103         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8104                 fp |= FP_CB_TUNE;
8105
8106         if (reduced_clock) {
8107                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8108
8109                 if (reduced_clock->m < factor * reduced_clock->n)
8110                         fp2 |= FP_CB_TUNE;
8111         } else {
8112                 fp2 = fp;
8113         }
8114
8115         dpll = 0;
8116
8117         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8118                 dpll |= DPLLB_MODE_LVDS;
8119         else
8120                 dpll |= DPLLB_MODE_DAC_SERIAL;
8121
8122         dpll |= (crtc_state->pixel_multiplier - 1)
8123                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8124
8125         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8126             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8127                 dpll |= DPLL_SDVO_HIGH_SPEED;
8128
8129         if (intel_crtc_has_dp_encoder(crtc_state))
8130                 dpll |= DPLL_SDVO_HIGH_SPEED;
8131
8132         /*
8133          * The high speed IO clock is only really required for
8134          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8135          * possible to share the DPLL between CRT and HDMI. Enabling
8136          * the clock needlessly does no real harm, except use up a
8137          * bit of power potentially.
8138          *
8139          * We'll limit this to IVB with 3 pipes, since it has only two
8140          * DPLLs and so DPLL sharing is the only way to get three pipes
8141          * driving PCH ports at the same time. On SNB we could do this,
8142          * and potentially avoid enabling the second DPLL, but it's not
8143          * clear if it''s a win or loss power wise. No point in doing
8144          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8145          */
8146         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8147             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8148                 dpll |= DPLL_SDVO_HIGH_SPEED;
8149
8150         /* compute bitmask from p1 value */
8151         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8152         /* also FPA1 */
8153         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8154
8155         switch (crtc_state->dpll.p2) {
8156         case 5:
8157                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8158                 break;
8159         case 7:
8160                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8161                 break;
8162         case 10:
8163                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8164                 break;
8165         case 14:
8166                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8167                 break;
8168         }
8169
8170         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8171             intel_panel_use_ssc(dev_priv))
8172                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8173         else
8174                 dpll |= PLL_REF_INPUT_DREFCLK;
8175
8176         dpll |= DPLL_VCO_ENABLE;
8177
8178         crtc_state->dpll_hw_state.dpll = dpll;
8179         crtc_state->dpll_hw_state.fp0 = fp;
8180         crtc_state->dpll_hw_state.fp1 = fp2;
8181 }
8182
8183 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8184                                        struct intel_crtc_state *crtc_state)
8185 {
8186         struct drm_device *dev = crtc->base.dev;
8187         struct drm_i915_private *dev_priv = to_i915(dev);
8188         struct dpll reduced_clock;
8189         bool has_reduced_clock = false;
8190         struct intel_shared_dpll *pll;
8191         const struct intel_limit *limit;
8192         int refclk = 120000;
8193
8194         memset(&crtc_state->dpll_hw_state, 0,
8195                sizeof(crtc_state->dpll_hw_state));
8196
8197         crtc->lowfreq_avail = false;
8198
8199         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8200         if (!crtc_state->has_pch_encoder)
8201                 return 0;
8202
8203         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8204                 if (intel_panel_use_ssc(dev_priv)) {
8205                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8206                                       dev_priv->vbt.lvds_ssc_freq);
8207                         refclk = dev_priv->vbt.lvds_ssc_freq;
8208                 }
8209
8210                 if (intel_is_dual_link_lvds(dev)) {
8211                         if (refclk == 100000)
8212                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8213                         else
8214                                 limit = &intel_limits_ironlake_dual_lvds;
8215                 } else {
8216                         if (refclk == 100000)
8217                                 limit = &intel_limits_ironlake_single_lvds_100m;
8218                         else
8219                                 limit = &intel_limits_ironlake_single_lvds;
8220                 }
8221         } else {
8222                 limit = &intel_limits_ironlake_dac;
8223         }
8224
8225         if (!crtc_state->clock_set &&
8226             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8227                                 refclk, NULL, &crtc_state->dpll)) {
8228                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8229                 return -EINVAL;
8230         }
8231
8232         ironlake_compute_dpll(crtc, crtc_state,
8233                               has_reduced_clock ? &reduced_clock : NULL);
8234
8235         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8236         if (pll == NULL) {
8237                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8238                                  pipe_name(crtc->pipe));
8239                 return -EINVAL;
8240         }
8241
8242         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8243             has_reduced_clock)
8244                 crtc->lowfreq_avail = true;
8245
8246         return 0;
8247 }
8248
8249 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8250                                          struct intel_link_m_n *m_n)
8251 {
8252         struct drm_device *dev = crtc->base.dev;
8253         struct drm_i915_private *dev_priv = to_i915(dev);
8254         enum pipe pipe = crtc->pipe;
8255
8256         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8257         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8258         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8259                 & ~TU_SIZE_MASK;
8260         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8261         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8262                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8263 }
8264
8265 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8266                                          enum transcoder transcoder,
8267                                          struct intel_link_m_n *m_n,
8268                                          struct intel_link_m_n *m2_n2)
8269 {
8270         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8271         enum pipe pipe = crtc->pipe;
8272
8273         if (INTEL_GEN(dev_priv) >= 5) {
8274                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8275                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8276                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8277                         & ~TU_SIZE_MASK;
8278                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8279                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8280                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8281                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8282                  * gen < 8) and if DRRS is supported (to make sure the
8283                  * registers are not unnecessarily read).
8284                  */
8285                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8286                         crtc->config->has_drrs) {
8287                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8288                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8289                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8290                                         & ~TU_SIZE_MASK;
8291                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8292                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8293                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8294                 }
8295         } else {
8296                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8297                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8298                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8299                         & ~TU_SIZE_MASK;
8300                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8301                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8302                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8303         }
8304 }
8305
8306 void intel_dp_get_m_n(struct intel_crtc *crtc,
8307                       struct intel_crtc_state *pipe_config)
8308 {
8309         if (pipe_config->has_pch_encoder)
8310                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8311         else
8312                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8313                                              &pipe_config->dp_m_n,
8314                                              &pipe_config->dp_m2_n2);
8315 }
8316
8317 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8318                                         struct intel_crtc_state *pipe_config)
8319 {
8320         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8321                                      &pipe_config->fdi_m_n, NULL);
8322 }
8323
8324 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8325                                     struct intel_crtc_state *pipe_config)
8326 {
8327         struct drm_device *dev = crtc->base.dev;
8328         struct drm_i915_private *dev_priv = to_i915(dev);
8329         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8330         uint32_t ps_ctrl = 0;
8331         int id = -1;
8332         int i;
8333
8334         /* find scaler attached to this pipe */
8335         for (i = 0; i < crtc->num_scalers; i++) {
8336                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8337                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8338                         id = i;
8339                         pipe_config->pch_pfit.enabled = true;
8340                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8341                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8342                         break;
8343                 }
8344         }
8345
8346         scaler_state->scaler_id = id;
8347         if (id >= 0) {
8348                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8349         } else {
8350                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8351         }
8352 }
8353
8354 static void
8355 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8356                                  struct intel_initial_plane_config *plane_config)
8357 {
8358         struct drm_device *dev = crtc->base.dev;
8359         struct drm_i915_private *dev_priv = to_i915(dev);
8360         u32 val, base, offset, stride_mult, tiling;
8361         int pipe = crtc->pipe;
8362         int fourcc, pixel_format;
8363         unsigned int aligned_height;
8364         struct drm_framebuffer *fb;
8365         struct intel_framebuffer *intel_fb;
8366
8367         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8368         if (!intel_fb) {
8369                 DRM_DEBUG_KMS("failed to alloc fb\n");
8370                 return;
8371         }
8372
8373         fb = &intel_fb->base;
8374
8375         fb->dev = dev;
8376
8377         val = I915_READ(PLANE_CTL(pipe, 0));
8378         if (!(val & PLANE_CTL_ENABLE))
8379                 goto error;
8380
8381         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8382         fourcc = skl_format_to_fourcc(pixel_format,
8383                                       val & PLANE_CTL_ORDER_RGBX,
8384                                       val & PLANE_CTL_ALPHA_MASK);
8385         fb->format = drm_format_info(fourcc);
8386
8387         tiling = val & PLANE_CTL_TILED_MASK;
8388         switch (tiling) {
8389         case PLANE_CTL_TILED_LINEAR:
8390                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8391                 break;
8392         case PLANE_CTL_TILED_X:
8393                 plane_config->tiling = I915_TILING_X;
8394                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8395                 break;
8396         case PLANE_CTL_TILED_Y:
8397                 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8398                 break;
8399         case PLANE_CTL_TILED_YF:
8400                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8401                 break;
8402         default:
8403                 MISSING_CASE(tiling);
8404                 goto error;
8405         }
8406
8407         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8408         plane_config->base = base;
8409
8410         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8411
8412         val = I915_READ(PLANE_SIZE(pipe, 0));
8413         fb->height = ((val >> 16) & 0xfff) + 1;
8414         fb->width = ((val >> 0) & 0x1fff) + 1;
8415
8416         val = I915_READ(PLANE_STRIDE(pipe, 0));
8417         stride_mult = intel_fb_stride_alignment(fb, 0);
8418         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8419
8420         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8421
8422         plane_config->size = fb->pitches[0] * aligned_height;
8423
8424         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8425                       pipe_name(pipe), fb->width, fb->height,
8426                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8427                       plane_config->size);
8428
8429         plane_config->fb = intel_fb;
8430         return;
8431
8432 error:
8433         kfree(intel_fb);
8434 }
8435
8436 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8437                                      struct intel_crtc_state *pipe_config)
8438 {
8439         struct drm_device *dev = crtc->base.dev;
8440         struct drm_i915_private *dev_priv = to_i915(dev);
8441         uint32_t tmp;
8442
8443         tmp = I915_READ(PF_CTL(crtc->pipe));
8444
8445         if (tmp & PF_ENABLE) {
8446                 pipe_config->pch_pfit.enabled = true;
8447                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8448                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8449
8450                 /* We currently do not free assignements of panel fitters on
8451                  * ivb/hsw (since we don't use the higher upscaling modes which
8452                  * differentiates them) so just WARN about this case for now. */
8453                 if (IS_GEN7(dev_priv)) {
8454                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8455                                 PF_PIPE_SEL_IVB(crtc->pipe));
8456                 }
8457         }
8458 }
8459
8460 static void
8461 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8462                                   struct intel_initial_plane_config *plane_config)
8463 {
8464         struct drm_device *dev = crtc->base.dev;
8465         struct drm_i915_private *dev_priv = to_i915(dev);
8466         u32 val, base, offset;
8467         int pipe = crtc->pipe;
8468         int fourcc, pixel_format;
8469         unsigned int aligned_height;
8470         struct drm_framebuffer *fb;
8471         struct intel_framebuffer *intel_fb;
8472
8473         val = I915_READ(DSPCNTR(pipe));
8474         if (!(val & DISPLAY_PLANE_ENABLE))
8475                 return;
8476
8477         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8478         if (!intel_fb) {
8479                 DRM_DEBUG_KMS("failed to alloc fb\n");
8480                 return;
8481         }
8482
8483         fb = &intel_fb->base;
8484
8485         fb->dev = dev;
8486
8487         if (INTEL_GEN(dev_priv) >= 4) {
8488                 if (val & DISPPLANE_TILED) {
8489                         plane_config->tiling = I915_TILING_X;
8490                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8491                 }
8492         }
8493
8494         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8495         fourcc = i9xx_format_to_fourcc(pixel_format);
8496         fb->format = drm_format_info(fourcc);
8497
8498         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8499         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8500                 offset = I915_READ(DSPOFFSET(pipe));
8501         } else {
8502                 if (plane_config->tiling)
8503                         offset = I915_READ(DSPTILEOFF(pipe));
8504                 else
8505                         offset = I915_READ(DSPLINOFF(pipe));
8506         }
8507         plane_config->base = base;
8508
8509         val = I915_READ(PIPESRC(pipe));
8510         fb->width = ((val >> 16) & 0xfff) + 1;
8511         fb->height = ((val >> 0) & 0xfff) + 1;
8512
8513         val = I915_READ(DSPSTRIDE(pipe));
8514         fb->pitches[0] = val & 0xffffffc0;
8515
8516         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8517
8518         plane_config->size = fb->pitches[0] * aligned_height;
8519
8520         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8521                       pipe_name(pipe), fb->width, fb->height,
8522                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8523                       plane_config->size);
8524
8525         plane_config->fb = intel_fb;
8526 }
8527
8528 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8529                                      struct intel_crtc_state *pipe_config)
8530 {
8531         struct drm_device *dev = crtc->base.dev;
8532         struct drm_i915_private *dev_priv = to_i915(dev);
8533         enum intel_display_power_domain power_domain;
8534         uint32_t tmp;
8535         bool ret;
8536
8537         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8538         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8539                 return false;
8540
8541         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8542         pipe_config->shared_dpll = NULL;
8543
8544         ret = false;
8545         tmp = I915_READ(PIPECONF(crtc->pipe));
8546         if (!(tmp & PIPECONF_ENABLE))
8547                 goto out;
8548
8549         switch (tmp & PIPECONF_BPC_MASK) {
8550         case PIPECONF_6BPC:
8551                 pipe_config->pipe_bpp = 18;
8552                 break;
8553         case PIPECONF_8BPC:
8554                 pipe_config->pipe_bpp = 24;
8555                 break;
8556         case PIPECONF_10BPC:
8557                 pipe_config->pipe_bpp = 30;
8558                 break;
8559         case PIPECONF_12BPC:
8560                 pipe_config->pipe_bpp = 36;
8561                 break;
8562         default:
8563                 break;
8564         }
8565
8566         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8567                 pipe_config->limited_color_range = true;
8568
8569         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8570                 struct intel_shared_dpll *pll;
8571                 enum intel_dpll_id pll_id;
8572
8573                 pipe_config->has_pch_encoder = true;
8574
8575                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8576                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8577                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8578
8579                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8580
8581                 if (HAS_PCH_IBX(dev_priv)) {
8582                         /*
8583                          * The pipe->pch transcoder and pch transcoder->pll
8584                          * mapping is fixed.
8585                          */
8586                         pll_id = (enum intel_dpll_id) crtc->pipe;
8587                 } else {
8588                         tmp = I915_READ(PCH_DPLL_SEL);
8589                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8590                                 pll_id = DPLL_ID_PCH_PLL_B;
8591                         else
8592                                 pll_id= DPLL_ID_PCH_PLL_A;
8593                 }
8594
8595                 pipe_config->shared_dpll =
8596                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8597                 pll = pipe_config->shared_dpll;
8598
8599                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8600                                                  &pipe_config->dpll_hw_state));
8601
8602                 tmp = pipe_config->dpll_hw_state.dpll;
8603                 pipe_config->pixel_multiplier =
8604                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8605                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8606
8607                 ironlake_pch_clock_get(crtc, pipe_config);
8608         } else {
8609                 pipe_config->pixel_multiplier = 1;
8610         }
8611
8612         intel_get_pipe_timings(crtc, pipe_config);
8613         intel_get_pipe_src_size(crtc, pipe_config);
8614
8615         ironlake_get_pfit_config(crtc, pipe_config);
8616
8617         ret = true;
8618
8619 out:
8620         intel_display_power_put(dev_priv, power_domain);
8621
8622         return ret;
8623 }
8624
8625 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8626 {
8627         struct drm_device *dev = &dev_priv->drm;
8628         struct intel_crtc *crtc;
8629
8630         for_each_intel_crtc(dev, crtc)
8631                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8632                      pipe_name(crtc->pipe));
8633
8634         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8635         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8636         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8637         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8638         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8639         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8640              "CPU PWM1 enabled\n");
8641         if (IS_HASWELL(dev_priv))
8642                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8643                      "CPU PWM2 enabled\n");
8644         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8645              "PCH PWM1 enabled\n");
8646         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8647              "Utility pin enabled\n");
8648         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8649
8650         /*
8651          * In theory we can still leave IRQs enabled, as long as only the HPD
8652          * interrupts remain enabled. We used to check for that, but since it's
8653          * gen-specific and since we only disable LCPLL after we fully disable
8654          * the interrupts, the check below should be enough.
8655          */
8656         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8657 }
8658
8659 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8660 {
8661         if (IS_HASWELL(dev_priv))
8662                 return I915_READ(D_COMP_HSW);
8663         else
8664                 return I915_READ(D_COMP_BDW);
8665 }
8666
8667 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8668 {
8669         if (IS_HASWELL(dev_priv)) {
8670                 mutex_lock(&dev_priv->rps.hw_lock);
8671                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8672                                             val))
8673                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8674                 mutex_unlock(&dev_priv->rps.hw_lock);
8675         } else {
8676                 I915_WRITE(D_COMP_BDW, val);
8677                 POSTING_READ(D_COMP_BDW);
8678         }
8679 }
8680
8681 /*
8682  * This function implements pieces of two sequences from BSpec:
8683  * - Sequence for display software to disable LCPLL
8684  * - Sequence for display software to allow package C8+
8685  * The steps implemented here are just the steps that actually touch the LCPLL
8686  * register. Callers should take care of disabling all the display engine
8687  * functions, doing the mode unset, fixing interrupts, etc.
8688  */
8689 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8690                               bool switch_to_fclk, bool allow_power_down)
8691 {
8692         uint32_t val;
8693
8694         assert_can_disable_lcpll(dev_priv);
8695
8696         val = I915_READ(LCPLL_CTL);
8697
8698         if (switch_to_fclk) {
8699                 val |= LCPLL_CD_SOURCE_FCLK;
8700                 I915_WRITE(LCPLL_CTL, val);
8701
8702                 if (wait_for_us(I915_READ(LCPLL_CTL) &
8703                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8704                         DRM_ERROR("Switching to FCLK failed\n");
8705
8706                 val = I915_READ(LCPLL_CTL);
8707         }
8708
8709         val |= LCPLL_PLL_DISABLE;
8710         I915_WRITE(LCPLL_CTL, val);
8711         POSTING_READ(LCPLL_CTL);
8712
8713         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8714                 DRM_ERROR("LCPLL still locked\n");
8715
8716         val = hsw_read_dcomp(dev_priv);
8717         val |= D_COMP_COMP_DISABLE;
8718         hsw_write_dcomp(dev_priv, val);
8719         ndelay(100);
8720
8721         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8722                      1))
8723                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8724
8725         if (allow_power_down) {
8726                 val = I915_READ(LCPLL_CTL);
8727                 val |= LCPLL_POWER_DOWN_ALLOW;
8728                 I915_WRITE(LCPLL_CTL, val);
8729                 POSTING_READ(LCPLL_CTL);
8730         }
8731 }
8732
8733 /*
8734  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8735  * source.
8736  */
8737 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8738 {
8739         uint32_t val;
8740
8741         val = I915_READ(LCPLL_CTL);
8742
8743         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8744                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8745                 return;
8746
8747         /*
8748          * Make sure we're not on PC8 state before disabling PC8, otherwise
8749          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8750          */
8751         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8752
8753         if (val & LCPLL_POWER_DOWN_ALLOW) {
8754                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8755                 I915_WRITE(LCPLL_CTL, val);
8756                 POSTING_READ(LCPLL_CTL);
8757         }
8758
8759         val = hsw_read_dcomp(dev_priv);
8760         val |= D_COMP_COMP_FORCE;
8761         val &= ~D_COMP_COMP_DISABLE;
8762         hsw_write_dcomp(dev_priv, val);
8763
8764         val = I915_READ(LCPLL_CTL);
8765         val &= ~LCPLL_PLL_DISABLE;
8766         I915_WRITE(LCPLL_CTL, val);
8767
8768         if (intel_wait_for_register(dev_priv,
8769                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8770                                     5))
8771                 DRM_ERROR("LCPLL not locked yet\n");
8772
8773         if (val & LCPLL_CD_SOURCE_FCLK) {
8774                 val = I915_READ(LCPLL_CTL);
8775                 val &= ~LCPLL_CD_SOURCE_FCLK;
8776                 I915_WRITE(LCPLL_CTL, val);
8777
8778                 if (wait_for_us((I915_READ(LCPLL_CTL) &
8779                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8780                         DRM_ERROR("Switching back to LCPLL failed\n");
8781         }
8782
8783         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8784         intel_update_cdclk(dev_priv);
8785 }
8786
8787 /*
8788  * Package states C8 and deeper are really deep PC states that can only be
8789  * reached when all the devices on the system allow it, so even if the graphics
8790  * device allows PC8+, it doesn't mean the system will actually get to these
8791  * states. Our driver only allows PC8+ when going into runtime PM.
8792  *
8793  * The requirements for PC8+ are that all the outputs are disabled, the power
8794  * well is disabled and most interrupts are disabled, and these are also
8795  * requirements for runtime PM. When these conditions are met, we manually do
8796  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8797  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8798  * hang the machine.
8799  *
8800  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8801  * the state of some registers, so when we come back from PC8+ we need to
8802  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8803  * need to take care of the registers kept by RC6. Notice that this happens even
8804  * if we don't put the device in PCI D3 state (which is what currently happens
8805  * because of the runtime PM support).
8806  *
8807  * For more, read "Display Sequences for Package C8" on the hardware
8808  * documentation.
8809  */
8810 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8811 {
8812         uint32_t val;
8813
8814         DRM_DEBUG_KMS("Enabling package C8+\n");
8815
8816         if (HAS_PCH_LPT_LP(dev_priv)) {
8817                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8818                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8819                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8820         }
8821
8822         lpt_disable_clkout_dp(dev_priv);
8823         hsw_disable_lcpll(dev_priv, true, true);
8824 }
8825
8826 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8827 {
8828         uint32_t val;
8829
8830         DRM_DEBUG_KMS("Disabling package C8+\n");
8831
8832         hsw_restore_lcpll(dev_priv);
8833         lpt_init_pch_refclk(dev_priv);
8834
8835         if (HAS_PCH_LPT_LP(dev_priv)) {
8836                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8837                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8838                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8839         }
8840 }
8841
8842 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8843                                       struct intel_crtc_state *crtc_state)
8844 {
8845         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8846                 struct intel_encoder *encoder =
8847                         intel_ddi_get_crtc_new_encoder(crtc_state);
8848
8849                 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8850                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8851                                          pipe_name(crtc->pipe));
8852                         return -EINVAL;
8853                 }
8854         }
8855
8856         crtc->lowfreq_avail = false;
8857
8858         return 0;
8859 }
8860
8861 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8862                                 enum port port,
8863                                 struct intel_crtc_state *pipe_config)
8864 {
8865         enum intel_dpll_id id;
8866
8867         switch (port) {
8868         case PORT_A:
8869                 id = DPLL_ID_SKL_DPLL0;
8870                 break;
8871         case PORT_B:
8872                 id = DPLL_ID_SKL_DPLL1;
8873                 break;
8874         case PORT_C:
8875                 id = DPLL_ID_SKL_DPLL2;
8876                 break;
8877         default:
8878                 DRM_ERROR("Incorrect port type\n");
8879                 return;
8880         }
8881
8882         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8883 }
8884
8885 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8886                                 enum port port,
8887                                 struct intel_crtc_state *pipe_config)
8888 {
8889         enum intel_dpll_id id;
8890         u32 temp;
8891
8892         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8893         id = temp >> (port * 3 + 1);
8894
8895         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8896                 return;
8897
8898         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8899 }
8900
8901 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8902                                 enum port port,
8903                                 struct intel_crtc_state *pipe_config)
8904 {
8905         enum intel_dpll_id id;
8906         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8907
8908         switch (ddi_pll_sel) {
8909         case PORT_CLK_SEL_WRPLL1:
8910                 id = DPLL_ID_WRPLL1;
8911                 break;
8912         case PORT_CLK_SEL_WRPLL2:
8913                 id = DPLL_ID_WRPLL2;
8914                 break;
8915         case PORT_CLK_SEL_SPLL:
8916                 id = DPLL_ID_SPLL;
8917                 break;
8918         case PORT_CLK_SEL_LCPLL_810:
8919                 id = DPLL_ID_LCPLL_810;
8920                 break;
8921         case PORT_CLK_SEL_LCPLL_1350:
8922                 id = DPLL_ID_LCPLL_1350;
8923                 break;
8924         case PORT_CLK_SEL_LCPLL_2700:
8925                 id = DPLL_ID_LCPLL_2700;
8926                 break;
8927         default:
8928                 MISSING_CASE(ddi_pll_sel);
8929                 /* fall through */
8930         case PORT_CLK_SEL_NONE:
8931                 return;
8932         }
8933
8934         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8935 }
8936
8937 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8938                                      struct intel_crtc_state *pipe_config,
8939                                      u64 *power_domain_mask)
8940 {
8941         struct drm_device *dev = crtc->base.dev;
8942         struct drm_i915_private *dev_priv = to_i915(dev);
8943         enum intel_display_power_domain power_domain;
8944         u32 tmp;
8945
8946         /*
8947          * The pipe->transcoder mapping is fixed with the exception of the eDP
8948          * transcoder handled below.
8949          */
8950         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8951
8952         /*
8953          * XXX: Do intel_display_power_get_if_enabled before reading this (for
8954          * consistency and less surprising code; it's in always on power).
8955          */
8956         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8957         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8958                 enum pipe trans_edp_pipe;
8959                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8960                 default:
8961                         WARN(1, "unknown pipe linked to edp transcoder\n");
8962                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8963                 case TRANS_DDI_EDP_INPUT_A_ON:
8964                         trans_edp_pipe = PIPE_A;
8965                         break;
8966                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8967                         trans_edp_pipe = PIPE_B;
8968                         break;
8969                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8970                         trans_edp_pipe = PIPE_C;
8971                         break;
8972                 }
8973
8974                 if (trans_edp_pipe == crtc->pipe)
8975                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8976         }
8977
8978         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
8979         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8980                 return false;
8981         *power_domain_mask |= BIT_ULL(power_domain);
8982
8983         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8984
8985         return tmp & PIPECONF_ENABLE;
8986 }
8987
8988 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
8989                                          struct intel_crtc_state *pipe_config,
8990                                          u64 *power_domain_mask)
8991 {
8992         struct drm_device *dev = crtc->base.dev;
8993         struct drm_i915_private *dev_priv = to_i915(dev);
8994         enum intel_display_power_domain power_domain;
8995         enum port port;
8996         enum transcoder cpu_transcoder;
8997         u32 tmp;
8998
8999         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9000                 if (port == PORT_A)
9001                         cpu_transcoder = TRANSCODER_DSI_A;
9002                 else
9003                         cpu_transcoder = TRANSCODER_DSI_C;
9004
9005                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9006                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9007                         continue;
9008                 *power_domain_mask |= BIT_ULL(power_domain);
9009
9010                 /*
9011                  * The PLL needs to be enabled with a valid divider
9012                  * configuration, otherwise accessing DSI registers will hang
9013                  * the machine. See BSpec North Display Engine
9014                  * registers/MIPI[BXT]. We can break out here early, since we
9015                  * need the same DSI PLL to be enabled for both DSI ports.
9016                  */
9017                 if (!intel_dsi_pll_is_enabled(dev_priv))
9018                         break;
9019
9020                 /* XXX: this works for video mode only */
9021                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9022                 if (!(tmp & DPI_ENABLE))
9023                         continue;
9024
9025                 tmp = I915_READ(MIPI_CTRL(port));
9026                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9027                         continue;
9028
9029                 pipe_config->cpu_transcoder = cpu_transcoder;
9030                 break;
9031         }
9032
9033         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9034 }
9035
9036 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9037                                        struct intel_crtc_state *pipe_config)
9038 {
9039         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9040         struct intel_shared_dpll *pll;
9041         enum port port;
9042         uint32_t tmp;
9043
9044         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9045
9046         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9047
9048         if (IS_GEN9_BC(dev_priv))
9049                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9050         else if (IS_GEN9_LP(dev_priv))
9051                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9052         else
9053                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9054
9055         pll = pipe_config->shared_dpll;
9056         if (pll) {
9057                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9058                                                  &pipe_config->dpll_hw_state));
9059         }
9060
9061         /*
9062          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9063          * DDI E. So just check whether this pipe is wired to DDI E and whether
9064          * the PCH transcoder is on.
9065          */
9066         if (INTEL_GEN(dev_priv) < 9 &&
9067             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9068                 pipe_config->has_pch_encoder = true;
9069
9070                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9071                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9072                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9073
9074                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9075         }
9076 }
9077
9078 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9079                                     struct intel_crtc_state *pipe_config)
9080 {
9081         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9082         enum intel_display_power_domain power_domain;
9083         u64 power_domain_mask;
9084         bool active;
9085
9086         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9087         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9088                 return false;
9089         power_domain_mask = BIT_ULL(power_domain);
9090
9091         pipe_config->shared_dpll = NULL;
9092
9093         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9094
9095         if (IS_GEN9_LP(dev_priv) &&
9096             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9097                 WARN_ON(active);
9098                 active = true;
9099         }
9100
9101         if (!active)
9102                 goto out;
9103
9104         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9105                 haswell_get_ddi_port_state(crtc, pipe_config);
9106                 intel_get_pipe_timings(crtc, pipe_config);
9107         }
9108
9109         intel_get_pipe_src_size(crtc, pipe_config);
9110
9111         pipe_config->gamma_mode =
9112                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9113
9114         if (INTEL_GEN(dev_priv) >= 9) {
9115                 intel_crtc_init_scalers(crtc, pipe_config);
9116
9117                 pipe_config->scaler_state.scaler_id = -1;
9118                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9119         }
9120
9121         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9122         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9123                 power_domain_mask |= BIT_ULL(power_domain);
9124                 if (INTEL_GEN(dev_priv) >= 9)
9125                         skylake_get_pfit_config(crtc, pipe_config);
9126                 else
9127                         ironlake_get_pfit_config(crtc, pipe_config);
9128         }
9129
9130         if (IS_HASWELL(dev_priv))
9131                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9132                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9133
9134         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9135             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9136                 pipe_config->pixel_multiplier =
9137                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9138         } else {
9139                 pipe_config->pixel_multiplier = 1;
9140         }
9141
9142 out:
9143         for_each_power_domain(power_domain, power_domain_mask)
9144                 intel_display_power_put(dev_priv, power_domain);
9145
9146         return active;
9147 }
9148
9149 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9150                            const struct intel_plane_state *plane_state)
9151 {
9152         unsigned int width = plane_state->base.crtc_w;
9153         unsigned int stride = roundup_pow_of_two(width) * 4;
9154
9155         switch (stride) {
9156         default:
9157                 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9158                           width, stride);
9159                 stride = 256;
9160                 /* fallthrough */
9161         case 256:
9162         case 512:
9163         case 1024:
9164         case 2048:
9165                 break;
9166         }
9167
9168         return CURSOR_ENABLE |
9169                 CURSOR_GAMMA_ENABLE |
9170                 CURSOR_FORMAT_ARGB |
9171                 CURSOR_STRIDE(stride);
9172 }
9173
9174 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
9175                                const struct intel_plane_state *plane_state)
9176 {
9177         struct drm_device *dev = crtc->dev;
9178         struct drm_i915_private *dev_priv = to_i915(dev);
9179         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9180         uint32_t cntl = 0, size = 0;
9181
9182         if (plane_state && plane_state->base.visible) {
9183                 unsigned int width = plane_state->base.crtc_w;
9184                 unsigned int height = plane_state->base.crtc_h;
9185
9186                 cntl = plane_state->ctl;
9187                 size = (height << 12) | width;
9188         }
9189
9190         if (intel_crtc->cursor_cntl != 0 &&
9191             (intel_crtc->cursor_base != base ||
9192              intel_crtc->cursor_size != size ||
9193              intel_crtc->cursor_cntl != cntl)) {
9194                 /* On these chipsets we can only modify the base/size/stride
9195                  * whilst the cursor is disabled.
9196                  */
9197                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9198                 POSTING_READ_FW(CURCNTR(PIPE_A));
9199                 intel_crtc->cursor_cntl = 0;
9200         }
9201
9202         if (intel_crtc->cursor_base != base) {
9203                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9204                 intel_crtc->cursor_base = base;
9205         }
9206
9207         if (intel_crtc->cursor_size != size) {
9208                 I915_WRITE_FW(CURSIZE, size);
9209                 intel_crtc->cursor_size = size;
9210         }
9211
9212         if (intel_crtc->cursor_cntl != cntl) {
9213                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9214                 POSTING_READ_FW(CURCNTR(PIPE_A));
9215                 intel_crtc->cursor_cntl = cntl;
9216         }
9217 }
9218
9219 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9220                            const struct intel_plane_state *plane_state)
9221 {
9222         struct drm_i915_private *dev_priv =
9223                 to_i915(plane_state->base.plane->dev);
9224         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9225         enum pipe pipe = crtc->pipe;
9226         u32 cntl;
9227
9228         cntl = MCURSOR_GAMMA_ENABLE;
9229
9230         if (HAS_DDI(dev_priv))
9231                 cntl |= CURSOR_PIPE_CSC_ENABLE;
9232
9233         cntl |= pipe << 28; /* Connect to correct pipe */
9234
9235         switch (plane_state->base.crtc_w) {
9236         case 64:
9237                 cntl |= CURSOR_MODE_64_ARGB_AX;
9238                 break;
9239         case 128:
9240                 cntl |= CURSOR_MODE_128_ARGB_AX;
9241                 break;
9242         case 256:
9243                 cntl |= CURSOR_MODE_256_ARGB_AX;
9244                 break;
9245         default:
9246                 MISSING_CASE(plane_state->base.crtc_w);
9247                 return 0;
9248         }
9249
9250         if (plane_state->base.rotation & DRM_ROTATE_180)
9251                 cntl |= CURSOR_ROTATE_180;
9252
9253         return cntl;
9254 }
9255
9256 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
9257                                const struct intel_plane_state *plane_state)
9258 {
9259         struct drm_device *dev = crtc->dev;
9260         struct drm_i915_private *dev_priv = to_i915(dev);
9261         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9262         int pipe = intel_crtc->pipe;
9263         uint32_t cntl = 0;
9264
9265         if (plane_state && plane_state->base.visible)
9266                 cntl = plane_state->ctl;
9267
9268         if (intel_crtc->cursor_cntl != cntl) {
9269                 I915_WRITE_FW(CURCNTR(pipe), cntl);
9270                 POSTING_READ_FW(CURCNTR(pipe));
9271                 intel_crtc->cursor_cntl = cntl;
9272         }
9273
9274         /* and commit changes on next vblank */
9275         I915_WRITE_FW(CURBASE(pipe), base);
9276         POSTING_READ_FW(CURBASE(pipe));
9277
9278         intel_crtc->cursor_base = base;
9279 }
9280
9281 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9282 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9283                                      const struct intel_plane_state *plane_state)
9284 {
9285         struct drm_device *dev = crtc->dev;
9286         struct drm_i915_private *dev_priv = to_i915(dev);
9287         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9288         int pipe = intel_crtc->pipe;
9289         u32 base = intel_crtc->cursor_addr;
9290         unsigned long irqflags;
9291         u32 pos = 0;
9292
9293         if (plane_state) {
9294                 int x = plane_state->base.crtc_x;
9295                 int y = plane_state->base.crtc_y;
9296
9297                 if (x < 0) {
9298                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9299                         x = -x;
9300                 }
9301                 pos |= x << CURSOR_X_SHIFT;
9302
9303                 if (y < 0) {
9304                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9305                         y = -y;
9306                 }
9307                 pos |= y << CURSOR_Y_SHIFT;
9308
9309                 /* ILK+ do this automagically */
9310                 if (HAS_GMCH_DISPLAY(dev_priv) &&
9311                     plane_state->base.rotation & DRM_ROTATE_180) {
9312                         base += (plane_state->base.crtc_h *
9313                                  plane_state->base.crtc_w - 1) * 4;
9314                 }
9315         }
9316
9317         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9318
9319         I915_WRITE_FW(CURPOS(pipe), pos);
9320
9321         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
9322                 i845_update_cursor(crtc, base, plane_state);
9323         else
9324                 i9xx_update_cursor(crtc, base, plane_state);
9325
9326         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9327 }
9328
9329 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
9330                            uint32_t width, uint32_t height)
9331 {
9332         if (width == 0 || height == 0)
9333                 return false;
9334
9335         /*
9336          * 845g/865g are special in that they are only limited by
9337          * the width of their cursors, the height is arbitrary up to
9338          * the precision of the register. Everything else requires
9339          * square cursors, limited to a few power-of-two sizes.
9340          */
9341         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
9342                 if ((width & 63) != 0)
9343                         return false;
9344
9345                 if (width > (IS_I845G(dev_priv) ? 64 : 512))
9346                         return false;
9347
9348                 if (height > 1023)
9349                         return false;
9350         } else {
9351                 switch (width | height) {
9352                 case 256:
9353                 case 128:
9354                         if (IS_GEN2(dev_priv))
9355                                 return false;
9356                 case 64:
9357                         break;
9358                 default:
9359                         return false;
9360                 }
9361         }
9362
9363         return true;
9364 }
9365
9366 /* VESA 640x480x72Hz mode to set on the pipe */
9367 static struct drm_display_mode load_detect_mode = {
9368         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9369                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9370 };
9371
9372 struct drm_framebuffer *
9373 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9374                          struct drm_mode_fb_cmd2 *mode_cmd)
9375 {
9376         struct intel_framebuffer *intel_fb;
9377         int ret;
9378
9379         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9380         if (!intel_fb)
9381                 return ERR_PTR(-ENOMEM);
9382
9383         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9384         if (ret)
9385                 goto err;
9386
9387         return &intel_fb->base;
9388
9389 err:
9390         kfree(intel_fb);
9391         return ERR_PTR(ret);
9392 }
9393
9394 static u32
9395 intel_framebuffer_pitch_for_width(int width, int bpp)
9396 {
9397         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9398         return ALIGN(pitch, 64);
9399 }
9400
9401 static u32
9402 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9403 {
9404         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9405         return PAGE_ALIGN(pitch * mode->vdisplay);
9406 }
9407
9408 static struct drm_framebuffer *
9409 intel_framebuffer_create_for_mode(struct drm_device *dev,
9410                                   struct drm_display_mode *mode,
9411                                   int depth, int bpp)
9412 {
9413         struct drm_framebuffer *fb;
9414         struct drm_i915_gem_object *obj;
9415         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9416
9417         obj = i915_gem_object_create(to_i915(dev),
9418                                     intel_framebuffer_size_for_mode(mode, bpp));
9419         if (IS_ERR(obj))
9420                 return ERR_CAST(obj);
9421
9422         mode_cmd.width = mode->hdisplay;
9423         mode_cmd.height = mode->vdisplay;
9424         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9425                                                                 bpp);
9426         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9427
9428         fb = intel_framebuffer_create(obj, &mode_cmd);
9429         if (IS_ERR(fb))
9430                 i915_gem_object_put(obj);
9431
9432         return fb;
9433 }
9434
9435 static struct drm_framebuffer *
9436 mode_fits_in_fbdev(struct drm_device *dev,
9437                    struct drm_display_mode *mode)
9438 {
9439 #ifdef CONFIG_DRM_FBDEV_EMULATION
9440         struct drm_i915_private *dev_priv = to_i915(dev);
9441         struct drm_i915_gem_object *obj;
9442         struct drm_framebuffer *fb;
9443
9444         if (!dev_priv->fbdev)
9445                 return NULL;
9446
9447         if (!dev_priv->fbdev->fb)
9448                 return NULL;
9449
9450         obj = dev_priv->fbdev->fb->obj;
9451         BUG_ON(!obj);
9452
9453         fb = &dev_priv->fbdev->fb->base;
9454         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9455                                                                fb->format->cpp[0] * 8))
9456                 return NULL;
9457
9458         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9459                 return NULL;
9460
9461         drm_framebuffer_reference(fb);
9462         return fb;
9463 #else
9464         return NULL;
9465 #endif
9466 }
9467
9468 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9469                                            struct drm_crtc *crtc,
9470                                            struct drm_display_mode *mode,
9471                                            struct drm_framebuffer *fb,
9472                                            int x, int y)
9473 {
9474         struct drm_plane_state *plane_state;
9475         int hdisplay, vdisplay;
9476         int ret;
9477
9478         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9479         if (IS_ERR(plane_state))
9480                 return PTR_ERR(plane_state);
9481
9482         if (mode)
9483                 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9484         else
9485                 hdisplay = vdisplay = 0;
9486
9487         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9488         if (ret)
9489                 return ret;
9490         drm_atomic_set_fb_for_plane(plane_state, fb);
9491         plane_state->crtc_x = 0;
9492         plane_state->crtc_y = 0;
9493         plane_state->crtc_w = hdisplay;
9494         plane_state->crtc_h = vdisplay;
9495         plane_state->src_x = x << 16;
9496         plane_state->src_y = y << 16;
9497         plane_state->src_w = hdisplay << 16;
9498         plane_state->src_h = vdisplay << 16;
9499
9500         return 0;
9501 }
9502
9503 int intel_get_load_detect_pipe(struct drm_connector *connector,
9504                                struct drm_display_mode *mode,
9505                                struct intel_load_detect_pipe *old,
9506                                struct drm_modeset_acquire_ctx *ctx)
9507 {
9508         struct intel_crtc *intel_crtc;
9509         struct intel_encoder *intel_encoder =
9510                 intel_attached_encoder(connector);
9511         struct drm_crtc *possible_crtc;
9512         struct drm_encoder *encoder = &intel_encoder->base;
9513         struct drm_crtc *crtc = NULL;
9514         struct drm_device *dev = encoder->dev;
9515         struct drm_i915_private *dev_priv = to_i915(dev);
9516         struct drm_framebuffer *fb;
9517         struct drm_mode_config *config = &dev->mode_config;
9518         struct drm_atomic_state *state = NULL, *restore_state = NULL;
9519         struct drm_connector_state *connector_state;
9520         struct intel_crtc_state *crtc_state;
9521         int ret, i = -1;
9522
9523         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9524                       connector->base.id, connector->name,
9525                       encoder->base.id, encoder->name);
9526
9527         old->restore_state = NULL;
9528
9529         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9530
9531         /*
9532          * Algorithm gets a little messy:
9533          *
9534          *   - if the connector already has an assigned crtc, use it (but make
9535          *     sure it's on first)
9536          *
9537          *   - try to find the first unused crtc that can drive this connector,
9538          *     and use that if we find one
9539          */
9540
9541         /* See if we already have a CRTC for this connector */
9542         if (connector->state->crtc) {
9543                 crtc = connector->state->crtc;
9544
9545                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9546                 if (ret)
9547                         goto fail;
9548
9549                 /* Make sure the crtc and connector are running */
9550                 goto found;
9551         }
9552
9553         /* Find an unused one (if possible) */
9554         for_each_crtc(dev, possible_crtc) {
9555                 i++;
9556                 if (!(encoder->possible_crtcs & (1 << i)))
9557                         continue;
9558
9559                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9560                 if (ret)
9561                         goto fail;
9562
9563                 if (possible_crtc->state->enable) {
9564                         drm_modeset_unlock(&possible_crtc->mutex);
9565                         continue;
9566                 }
9567
9568                 crtc = possible_crtc;
9569                 break;
9570         }
9571
9572         /*
9573          * If we didn't find an unused CRTC, don't use any.
9574          */
9575         if (!crtc) {
9576                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9577                 goto fail;
9578         }
9579
9580 found:
9581         intel_crtc = to_intel_crtc(crtc);
9582
9583         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9584         if (ret)
9585                 goto fail;
9586
9587         state = drm_atomic_state_alloc(dev);
9588         restore_state = drm_atomic_state_alloc(dev);
9589         if (!state || !restore_state) {
9590                 ret = -ENOMEM;
9591                 goto fail;
9592         }
9593
9594         state->acquire_ctx = ctx;
9595         restore_state->acquire_ctx = ctx;
9596
9597         connector_state = drm_atomic_get_connector_state(state, connector);
9598         if (IS_ERR(connector_state)) {
9599                 ret = PTR_ERR(connector_state);
9600                 goto fail;
9601         }
9602
9603         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9604         if (ret)
9605                 goto fail;
9606
9607         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9608         if (IS_ERR(crtc_state)) {
9609                 ret = PTR_ERR(crtc_state);
9610                 goto fail;
9611         }
9612
9613         crtc_state->base.active = crtc_state->base.enable = true;
9614
9615         if (!mode)
9616                 mode = &load_detect_mode;
9617
9618         /* We need a framebuffer large enough to accommodate all accesses
9619          * that the plane may generate whilst we perform load detection.
9620          * We can not rely on the fbcon either being present (we get called
9621          * during its initialisation to detect all boot displays, or it may
9622          * not even exist) or that it is large enough to satisfy the
9623          * requested mode.
9624          */
9625         fb = mode_fits_in_fbdev(dev, mode);
9626         if (fb == NULL) {
9627                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9628                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9629         } else
9630                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9631         if (IS_ERR(fb)) {
9632                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9633                 goto fail;
9634         }
9635
9636         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9637         if (ret)
9638                 goto fail;
9639
9640         drm_framebuffer_unreference(fb);
9641
9642         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9643         if (ret)
9644                 goto fail;
9645
9646         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9647         if (!ret)
9648                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9649         if (!ret)
9650                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9651         if (ret) {
9652                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9653                 goto fail;
9654         }
9655
9656         ret = drm_atomic_commit(state);
9657         if (ret) {
9658                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9659                 goto fail;
9660         }
9661
9662         old->restore_state = restore_state;
9663         drm_atomic_state_put(state);
9664
9665         /* let the connector get through one full cycle before testing */
9666         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9667         return true;
9668
9669 fail:
9670         if (state) {
9671                 drm_atomic_state_put(state);
9672                 state = NULL;
9673         }
9674         if (restore_state) {
9675                 drm_atomic_state_put(restore_state);
9676                 restore_state = NULL;
9677         }
9678
9679         if (ret == -EDEADLK)
9680                 return ret;
9681
9682         return false;
9683 }
9684
9685 void intel_release_load_detect_pipe(struct drm_connector *connector,
9686                                     struct intel_load_detect_pipe *old,
9687                                     struct drm_modeset_acquire_ctx *ctx)
9688 {
9689         struct intel_encoder *intel_encoder =
9690                 intel_attached_encoder(connector);
9691         struct drm_encoder *encoder = &intel_encoder->base;
9692         struct drm_atomic_state *state = old->restore_state;
9693         int ret;
9694
9695         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9696                       connector->base.id, connector->name,
9697                       encoder->base.id, encoder->name);
9698
9699         if (!state)
9700                 return;
9701
9702         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9703         if (ret)
9704                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9705         drm_atomic_state_put(state);
9706 }
9707
9708 static int i9xx_pll_refclk(struct drm_device *dev,
9709                            const struct intel_crtc_state *pipe_config)
9710 {
9711         struct drm_i915_private *dev_priv = to_i915(dev);
9712         u32 dpll = pipe_config->dpll_hw_state.dpll;
9713
9714         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9715                 return dev_priv->vbt.lvds_ssc_freq;
9716         else if (HAS_PCH_SPLIT(dev_priv))
9717                 return 120000;
9718         else if (!IS_GEN2(dev_priv))
9719                 return 96000;
9720         else
9721                 return 48000;
9722 }
9723
9724 /* Returns the clock of the currently programmed mode of the given pipe. */
9725 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9726                                 struct intel_crtc_state *pipe_config)
9727 {
9728         struct drm_device *dev = crtc->base.dev;
9729         struct drm_i915_private *dev_priv = to_i915(dev);
9730         int pipe = pipe_config->cpu_transcoder;
9731         u32 dpll = pipe_config->dpll_hw_state.dpll;
9732         u32 fp;
9733         struct dpll clock;
9734         int port_clock;
9735         int refclk = i9xx_pll_refclk(dev, pipe_config);
9736
9737         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9738                 fp = pipe_config->dpll_hw_state.fp0;
9739         else
9740                 fp = pipe_config->dpll_hw_state.fp1;
9741
9742         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9743         if (IS_PINEVIEW(dev_priv)) {
9744                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9745                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9746         } else {
9747                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9748                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9749         }
9750
9751         if (!IS_GEN2(dev_priv)) {
9752                 if (IS_PINEVIEW(dev_priv))
9753                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9754                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9755                 else
9756                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9757                                DPLL_FPA01_P1_POST_DIV_SHIFT);
9758
9759                 switch (dpll & DPLL_MODE_MASK) {
9760                 case DPLLB_MODE_DAC_SERIAL:
9761                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9762                                 5 : 10;
9763                         break;
9764                 case DPLLB_MODE_LVDS:
9765                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9766                                 7 : 14;
9767                         break;
9768                 default:
9769                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9770                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
9771                         return;
9772                 }
9773
9774                 if (IS_PINEVIEW(dev_priv))
9775                         port_clock = pnv_calc_dpll_params(refclk, &clock);
9776                 else
9777                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
9778         } else {
9779                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9780                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9781
9782                 if (is_lvds) {
9783                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9784                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
9785
9786                         if (lvds & LVDS_CLKB_POWER_UP)
9787                                 clock.p2 = 7;
9788                         else
9789                                 clock.p2 = 14;
9790                 } else {
9791                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
9792                                 clock.p1 = 2;
9793                         else {
9794                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9795                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9796                         }
9797                         if (dpll & PLL_P2_DIVIDE_BY_4)
9798                                 clock.p2 = 4;
9799                         else
9800                                 clock.p2 = 2;
9801                 }
9802
9803                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9804         }
9805
9806         /*
9807          * This value includes pixel_multiplier. We will use
9808          * port_clock to compute adjusted_mode.crtc_clock in the
9809          * encoder's get_config() function.
9810          */
9811         pipe_config->port_clock = port_clock;
9812 }
9813
9814 int intel_dotclock_calculate(int link_freq,
9815                              const struct intel_link_m_n *m_n)
9816 {
9817         /*
9818          * The calculation for the data clock is:
9819          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9820          * But we want to avoid losing precison if possible, so:
9821          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9822          *
9823          * and the link clock is simpler:
9824          * link_clock = (m * link_clock) / n
9825          */
9826
9827         if (!m_n->link_n)
9828                 return 0;
9829
9830         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9831 }
9832
9833 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9834                                    struct intel_crtc_state *pipe_config)
9835 {
9836         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9837
9838         /* read out port_clock from the DPLL */
9839         i9xx_crtc_clock_get(crtc, pipe_config);
9840
9841         /*
9842          * In case there is an active pipe without active ports,
9843          * we may need some idea for the dotclock anyway.
9844          * Calculate one based on the FDI configuration.
9845          */
9846         pipe_config->base.adjusted_mode.crtc_clock =
9847                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
9848                                          &pipe_config->fdi_m_n);
9849 }
9850
9851 /** Returns the currently programmed mode of the given pipe. */
9852 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9853                                              struct drm_crtc *crtc)
9854 {
9855         struct drm_i915_private *dev_priv = to_i915(dev);
9856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9857         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9858         struct drm_display_mode *mode;
9859         struct intel_crtc_state *pipe_config;
9860         int htot = I915_READ(HTOTAL(cpu_transcoder));
9861         int hsync = I915_READ(HSYNC(cpu_transcoder));
9862         int vtot = I915_READ(VTOTAL(cpu_transcoder));
9863         int vsync = I915_READ(VSYNC(cpu_transcoder));
9864         enum pipe pipe = intel_crtc->pipe;
9865
9866         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9867         if (!mode)
9868                 return NULL;
9869
9870         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9871         if (!pipe_config) {
9872                 kfree(mode);
9873                 return NULL;
9874         }
9875
9876         /*
9877          * Construct a pipe_config sufficient for getting the clock info
9878          * back out of crtc_clock_get.
9879          *
9880          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9881          * to use a real value here instead.
9882          */
9883         pipe_config->cpu_transcoder = (enum transcoder) pipe;
9884         pipe_config->pixel_multiplier = 1;
9885         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9886         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9887         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9888         i9xx_crtc_clock_get(intel_crtc, pipe_config);
9889
9890         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
9891         mode->hdisplay = (htot & 0xffff) + 1;
9892         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9893         mode->hsync_start = (hsync & 0xffff) + 1;
9894         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9895         mode->vdisplay = (vtot & 0xffff) + 1;
9896         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9897         mode->vsync_start = (vsync & 0xffff) + 1;
9898         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9899
9900         drm_mode_set_name(mode);
9901
9902         kfree(pipe_config);
9903
9904         return mode;
9905 }
9906
9907 static void intel_crtc_destroy(struct drm_crtc *crtc)
9908 {
9909         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9910         struct drm_device *dev = crtc->dev;
9911         struct intel_flip_work *work;
9912
9913         spin_lock_irq(&dev->event_lock);
9914         work = intel_crtc->flip_work;
9915         intel_crtc->flip_work = NULL;
9916         spin_unlock_irq(&dev->event_lock);
9917
9918         if (work) {
9919                 cancel_work_sync(&work->mmio_work);
9920                 cancel_work_sync(&work->unpin_work);
9921                 kfree(work);
9922         }
9923
9924         drm_crtc_cleanup(crtc);
9925
9926         kfree(intel_crtc);
9927 }
9928
9929 static void intel_unpin_work_fn(struct work_struct *__work)
9930 {
9931         struct intel_flip_work *work =
9932                 container_of(__work, struct intel_flip_work, unpin_work);
9933         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
9934         struct drm_device *dev = crtc->base.dev;
9935         struct drm_plane *primary = crtc->base.primary;
9936
9937         if (is_mmio_work(work))
9938                 flush_work(&work->mmio_work);
9939
9940         mutex_lock(&dev->struct_mutex);
9941         intel_unpin_fb_vma(work->old_vma);
9942         i915_gem_object_put(work->pending_flip_obj);
9943         mutex_unlock(&dev->struct_mutex);
9944
9945         i915_gem_request_put(work->flip_queued_req);
9946
9947         intel_frontbuffer_flip_complete(to_i915(dev),
9948                                         to_intel_plane(primary)->frontbuffer_bit);
9949         intel_fbc_post_update(crtc);
9950         drm_framebuffer_unreference(work->old_fb);
9951
9952         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
9953         atomic_dec(&crtc->unpin_work_count);
9954
9955         kfree(work);
9956 }
9957
9958 /* Is 'a' after or equal to 'b'? */
9959 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9960 {
9961         return !((a - b) & 0x80000000);
9962 }
9963
9964 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
9965                                    struct intel_flip_work *work)
9966 {
9967         struct drm_device *dev = crtc->base.dev;
9968         struct drm_i915_private *dev_priv = to_i915(dev);
9969
9970         if (abort_flip_on_reset(crtc))
9971                 return true;
9972
9973         /*
9974          * The relevant registers doen't exist on pre-ctg.
9975          * As the flip done interrupt doesn't trigger for mmio
9976          * flips on gmch platforms, a flip count check isn't
9977          * really needed there. But since ctg has the registers,
9978          * include it in the check anyway.
9979          */
9980         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
9981                 return true;
9982
9983         /*
9984          * BDW signals flip done immediately if the plane
9985          * is disabled, even if the plane enable is already
9986          * armed to occur at the next vblank :(
9987          */
9988
9989         /*
9990          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9991          * used the same base address. In that case the mmio flip might
9992          * have completed, but the CS hasn't even executed the flip yet.
9993          *
9994          * A flip count check isn't enough as the CS might have updated
9995          * the base address just after start of vblank, but before we
9996          * managed to process the interrupt. This means we'd complete the
9997          * CS flip too soon.
9998          *
9999          * Combining both checks should get us a good enough result. It may
10000          * still happen that the CS flip has been executed, but has not
10001          * yet actually completed. But in case the base address is the same
10002          * anyway, we don't really care.
10003          */
10004         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10005                 crtc->flip_work->gtt_offset &&
10006                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10007                                     crtc->flip_work->flip_count);
10008 }
10009
10010 static bool
10011 __pageflip_finished_mmio(struct intel_crtc *crtc,
10012                                struct intel_flip_work *work)
10013 {
10014         /*
10015          * MMIO work completes when vblank is different from
10016          * flip_queued_vblank.
10017          *
10018          * Reset counter value doesn't matter, this is handled by
10019          * i915_wait_request finishing early, so no need to handle
10020          * reset here.
10021          */
10022         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10023 }
10024
10025
10026 static bool pageflip_finished(struct intel_crtc *crtc,
10027                               struct intel_flip_work *work)
10028 {
10029         if (!atomic_read(&work->pending))
10030                 return false;
10031
10032         smp_rmb();
10033
10034         if (is_mmio_work(work))
10035                 return __pageflip_finished_mmio(crtc, work);
10036         else
10037                 return __pageflip_finished_cs(crtc, work);
10038 }
10039
10040 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10041 {
10042         struct drm_device *dev = &dev_priv->drm;
10043         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10044         struct intel_flip_work *work;
10045         unsigned long flags;
10046
10047         /* Ignore early vblank irqs */
10048         if (!crtc)
10049                 return;
10050
10051         /*
10052          * This is called both by irq handlers and the reset code (to complete
10053          * lost pageflips) so needs the full irqsave spinlocks.
10054          */
10055         spin_lock_irqsave(&dev->event_lock, flags);
10056         work = crtc->flip_work;
10057
10058         if (work != NULL &&
10059             !is_mmio_work(work) &&
10060             pageflip_finished(crtc, work))
10061                 page_flip_completed(crtc);
10062
10063         spin_unlock_irqrestore(&dev->event_lock, flags);
10064 }
10065
10066 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10067 {
10068         struct drm_device *dev = &dev_priv->drm;
10069         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10070         struct intel_flip_work *work;
10071         unsigned long flags;
10072
10073         /* Ignore early vblank irqs */
10074         if (!crtc)
10075                 return;
10076
10077         /*
10078          * This is called both by irq handlers and the reset code (to complete
10079          * lost pageflips) so needs the full irqsave spinlocks.
10080          */
10081         spin_lock_irqsave(&dev->event_lock, flags);
10082         work = crtc->flip_work;
10083
10084         if (work != NULL &&
10085             is_mmio_work(work) &&
10086             pageflip_finished(crtc, work))
10087                 page_flip_completed(crtc);
10088
10089         spin_unlock_irqrestore(&dev->event_lock, flags);
10090 }
10091
10092 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10093                                                struct intel_flip_work *work)
10094 {
10095         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10096
10097         /* Ensure that the work item is consistent when activating it ... */
10098         smp_mb__before_atomic();
10099         atomic_set(&work->pending, 1);
10100 }
10101
10102 static int intel_gen2_queue_flip(struct drm_device *dev,
10103                                  struct drm_crtc *crtc,
10104                                  struct drm_framebuffer *fb,
10105                                  struct drm_i915_gem_object *obj,
10106                                  struct drm_i915_gem_request *req,
10107                                  uint32_t flags)
10108 {
10109         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10110         u32 flip_mask, *cs;
10111
10112         cs = intel_ring_begin(req, 6);
10113         if (IS_ERR(cs))
10114                 return PTR_ERR(cs);
10115
10116         /* Can't queue multiple flips, so wait for the previous
10117          * one to finish before executing the next.
10118          */
10119         if (intel_crtc->plane)
10120                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10121         else
10122                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10123         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10124         *cs++ = MI_NOOP;
10125         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10126         *cs++ = fb->pitches[0];
10127         *cs++ = intel_crtc->flip_work->gtt_offset;
10128         *cs++ = 0; /* aux display base address, unused */
10129
10130         return 0;
10131 }
10132
10133 static int intel_gen3_queue_flip(struct drm_device *dev,
10134                                  struct drm_crtc *crtc,
10135                                  struct drm_framebuffer *fb,
10136                                  struct drm_i915_gem_object *obj,
10137                                  struct drm_i915_gem_request *req,
10138                                  uint32_t flags)
10139 {
10140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10141         u32 flip_mask, *cs;
10142
10143         cs = intel_ring_begin(req, 6);
10144         if (IS_ERR(cs))
10145                 return PTR_ERR(cs);
10146
10147         if (intel_crtc->plane)
10148                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10149         else
10150                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10151         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10152         *cs++ = MI_NOOP;
10153         *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10154         *cs++ = fb->pitches[0];
10155         *cs++ = intel_crtc->flip_work->gtt_offset;
10156         *cs++ = MI_NOOP;
10157
10158         return 0;
10159 }
10160
10161 static int intel_gen4_queue_flip(struct drm_device *dev,
10162                                  struct drm_crtc *crtc,
10163                                  struct drm_framebuffer *fb,
10164                                  struct drm_i915_gem_object *obj,
10165                                  struct drm_i915_gem_request *req,
10166                                  uint32_t flags)
10167 {
10168         struct drm_i915_private *dev_priv = to_i915(dev);
10169         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10170         u32 pf, pipesrc, *cs;
10171
10172         cs = intel_ring_begin(req, 4);
10173         if (IS_ERR(cs))
10174                 return PTR_ERR(cs);
10175
10176         /* i965+ uses the linear or tiled offsets from the
10177          * Display Registers (which do not change across a page-flip)
10178          * so we need only reprogram the base address.
10179          */
10180         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10181         *cs++ = fb->pitches[0];
10182         *cs++ = intel_crtc->flip_work->gtt_offset |
10183                 intel_fb_modifier_to_tiling(fb->modifier);
10184
10185         /* XXX Enabling the panel-fitter across page-flip is so far
10186          * untested on non-native modes, so ignore it for now.
10187          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10188          */
10189         pf = 0;
10190         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10191         *cs++ = pf | pipesrc;
10192
10193         return 0;
10194 }
10195
10196 static int intel_gen6_queue_flip(struct drm_device *dev,
10197                                  struct drm_crtc *crtc,
10198                                  struct drm_framebuffer *fb,
10199                                  struct drm_i915_gem_object *obj,
10200                                  struct drm_i915_gem_request *req,
10201                                  uint32_t flags)
10202 {
10203         struct drm_i915_private *dev_priv = to_i915(dev);
10204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10205         u32 pf, pipesrc, *cs;
10206
10207         cs = intel_ring_begin(req, 4);
10208         if (IS_ERR(cs))
10209                 return PTR_ERR(cs);
10210
10211         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10212         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10213         *cs++ = intel_crtc->flip_work->gtt_offset;
10214
10215         /* Contrary to the suggestions in the documentation,
10216          * "Enable Panel Fitter" does not seem to be required when page
10217          * flipping with a non-native mode, and worse causes a normal
10218          * modeset to fail.
10219          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10220          */
10221         pf = 0;
10222         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10223         *cs++ = pf | pipesrc;
10224
10225         return 0;
10226 }
10227
10228 static int intel_gen7_queue_flip(struct drm_device *dev,
10229                                  struct drm_crtc *crtc,
10230                                  struct drm_framebuffer *fb,
10231                                  struct drm_i915_gem_object *obj,
10232                                  struct drm_i915_gem_request *req,
10233                                  uint32_t flags)
10234 {
10235         struct drm_i915_private *dev_priv = to_i915(dev);
10236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10237         u32 *cs, plane_bit = 0;
10238         int len, ret;
10239
10240         switch (intel_crtc->plane) {
10241         case PLANE_A:
10242                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10243                 break;
10244         case PLANE_B:
10245                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10246                 break;
10247         case PLANE_C:
10248                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10249                 break;
10250         default:
10251                 WARN_ONCE(1, "unknown plane in flip command\n");
10252                 return -ENODEV;
10253         }
10254
10255         len = 4;
10256         if (req->engine->id == RCS) {
10257                 len += 6;
10258                 /*
10259                  * On Gen 8, SRM is now taking an extra dword to accommodate
10260                  * 48bits addresses, and we need a NOOP for the batch size to
10261                  * stay even.
10262                  */
10263                 if (IS_GEN8(dev_priv))
10264                         len += 2;
10265         }
10266
10267         /*
10268          * BSpec MI_DISPLAY_FLIP for IVB:
10269          * "The full packet must be contained within the same cache line."
10270          *
10271          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10272          * cacheline, if we ever start emitting more commands before
10273          * the MI_DISPLAY_FLIP we may need to first emit everything else,
10274          * then do the cacheline alignment, and finally emit the
10275          * MI_DISPLAY_FLIP.
10276          */
10277         ret = intel_ring_cacheline_align(req);
10278         if (ret)
10279                 return ret;
10280
10281         cs = intel_ring_begin(req, len);
10282         if (IS_ERR(cs))
10283                 return PTR_ERR(cs);
10284
10285         /* Unmask the flip-done completion message. Note that the bspec says that
10286          * we should do this for both the BCS and RCS, and that we must not unmask
10287          * more than one flip event at any time (or ensure that one flip message
10288          * can be sent by waiting for flip-done prior to queueing new flips).
10289          * Experimentation says that BCS works despite DERRMR masking all
10290          * flip-done completion events and that unmasking all planes at once
10291          * for the RCS also doesn't appear to drop events. Setting the DERRMR
10292          * to zero does lead to lockups within MI_DISPLAY_FLIP.
10293          */
10294         if (req->engine->id == RCS) {
10295                 *cs++ = MI_LOAD_REGISTER_IMM(1);
10296                 *cs++ = i915_mmio_reg_offset(DERRMR);
10297                 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10298                           DERRMR_PIPEB_PRI_FLIP_DONE |
10299                           DERRMR_PIPEC_PRI_FLIP_DONE);
10300                 if (IS_GEN8(dev_priv))
10301                         *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10302                                 MI_SRM_LRM_GLOBAL_GTT;
10303                 else
10304                         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10305                 *cs++ = i915_mmio_reg_offset(DERRMR);
10306                 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
10307                 if (IS_GEN8(dev_priv)) {
10308                         *cs++ = 0;
10309                         *cs++ = MI_NOOP;
10310                 }
10311         }
10312
10313         *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10314         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10315         *cs++ = intel_crtc->flip_work->gtt_offset;
10316         *cs++ = MI_NOOP;
10317
10318         return 0;
10319 }
10320
10321 static bool use_mmio_flip(struct intel_engine_cs *engine,
10322                           struct drm_i915_gem_object *obj)
10323 {
10324         /*
10325          * This is not being used for older platforms, because
10326          * non-availability of flip done interrupt forces us to use
10327          * CS flips. Older platforms derive flip done using some clever
10328          * tricks involving the flip_pending status bits and vblank irqs.
10329          * So using MMIO flips there would disrupt this mechanism.
10330          */
10331
10332         if (engine == NULL)
10333                 return true;
10334
10335         if (INTEL_GEN(engine->i915) < 5)
10336                 return false;
10337
10338         if (i915.use_mmio_flip < 0)
10339                 return false;
10340         else if (i915.use_mmio_flip > 0)
10341                 return true;
10342         else if (i915.enable_execlists)
10343                 return true;
10344
10345         return engine != i915_gem_object_last_write_engine(obj);
10346 }
10347
10348 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10349                              unsigned int rotation,
10350                              struct intel_flip_work *work)
10351 {
10352         struct drm_device *dev = intel_crtc->base.dev;
10353         struct drm_i915_private *dev_priv = to_i915(dev);
10354         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10355         const enum pipe pipe = intel_crtc->pipe;
10356         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10357
10358         ctl = I915_READ(PLANE_CTL(pipe, 0));
10359         ctl &= ~PLANE_CTL_TILED_MASK;
10360         switch (fb->modifier) {
10361         case DRM_FORMAT_MOD_LINEAR:
10362                 break;
10363         case I915_FORMAT_MOD_X_TILED:
10364                 ctl |= PLANE_CTL_TILED_X;
10365                 break;
10366         case I915_FORMAT_MOD_Y_TILED:
10367                 ctl |= PLANE_CTL_TILED_Y;
10368                 break;
10369         case I915_FORMAT_MOD_Yf_TILED:
10370                 ctl |= PLANE_CTL_TILED_YF;
10371                 break;
10372         default:
10373                 MISSING_CASE(fb->modifier);
10374         }
10375
10376         /*
10377          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10378          * PLANE_SURF updates, the update is then guaranteed to be atomic.
10379          */
10380         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10381         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10382
10383         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10384         POSTING_READ(PLANE_SURF(pipe, 0));
10385 }
10386
10387 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10388                              struct intel_flip_work *work)
10389 {
10390         struct drm_device *dev = intel_crtc->base.dev;
10391         struct drm_i915_private *dev_priv = to_i915(dev);
10392         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10393         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10394         u32 dspcntr;
10395
10396         dspcntr = I915_READ(reg);
10397
10398         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10399                 dspcntr |= DISPPLANE_TILED;
10400         else
10401                 dspcntr &= ~DISPPLANE_TILED;
10402
10403         I915_WRITE(reg, dspcntr);
10404
10405         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10406         POSTING_READ(DSPSURF(intel_crtc->plane));
10407 }
10408
10409 static void intel_mmio_flip_work_func(struct work_struct *w)
10410 {
10411         struct intel_flip_work *work =
10412                 container_of(w, struct intel_flip_work, mmio_work);
10413         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10414         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10415         struct intel_framebuffer *intel_fb =
10416                 to_intel_framebuffer(crtc->base.primary->fb);
10417         struct drm_i915_gem_object *obj = intel_fb->obj;
10418
10419         WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10420
10421         intel_pipe_update_start(crtc);
10422
10423         if (INTEL_GEN(dev_priv) >= 9)
10424                 skl_do_mmio_flip(crtc, work->rotation, work);
10425         else
10426                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10427                 ilk_do_mmio_flip(crtc, work);
10428
10429         intel_pipe_update_end(crtc, work);
10430 }
10431
10432 static int intel_default_queue_flip(struct drm_device *dev,
10433                                     struct drm_crtc *crtc,
10434                                     struct drm_framebuffer *fb,
10435                                     struct drm_i915_gem_object *obj,
10436                                     struct drm_i915_gem_request *req,
10437                                     uint32_t flags)
10438 {
10439         return -ENODEV;
10440 }
10441
10442 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10443                                       struct intel_crtc *intel_crtc,
10444                                       struct intel_flip_work *work)
10445 {
10446         u32 addr, vblank;
10447
10448         if (!atomic_read(&work->pending))
10449                 return false;
10450
10451         smp_rmb();
10452
10453         vblank = intel_crtc_get_vblank_counter(intel_crtc);
10454         if (work->flip_ready_vblank == 0) {
10455                 if (work->flip_queued_req &&
10456                     !i915_gem_request_completed(work->flip_queued_req))
10457                         return false;
10458
10459                 work->flip_ready_vblank = vblank;
10460         }
10461
10462         if (vblank - work->flip_ready_vblank < 3)
10463                 return false;
10464
10465         /* Potential stall - if we see that the flip has happened,
10466          * assume a missed interrupt. */
10467         if (INTEL_GEN(dev_priv) >= 4)
10468                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10469         else
10470                 addr = I915_READ(DSPADDR(intel_crtc->plane));
10471
10472         /* There is a potential issue here with a false positive after a flip
10473          * to the same address. We could address this by checking for a
10474          * non-incrementing frame counter.
10475          */
10476         return addr == work->gtt_offset;
10477 }
10478
10479 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10480 {
10481         struct drm_device *dev = &dev_priv->drm;
10482         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10483         struct intel_flip_work *work;
10484
10485         WARN_ON(!in_interrupt());
10486
10487         if (crtc == NULL)
10488                 return;
10489
10490         spin_lock(&dev->event_lock);
10491         work = crtc->flip_work;
10492
10493         if (work != NULL && !is_mmio_work(work) &&
10494             __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10495                 WARN_ONCE(1,
10496                           "Kicking stuck page flip: queued at %d, now %d\n",
10497                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10498                 page_flip_completed(crtc);
10499                 work = NULL;
10500         }
10501
10502         if (work != NULL && !is_mmio_work(work) &&
10503             intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10504                 intel_queue_rps_boost_for_request(work->flip_queued_req);
10505         spin_unlock(&dev->event_lock);
10506 }
10507
10508 __maybe_unused
10509 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10510                                 struct drm_framebuffer *fb,
10511                                 struct drm_pending_vblank_event *event,
10512                                 uint32_t page_flip_flags)
10513 {
10514         struct drm_device *dev = crtc->dev;
10515         struct drm_i915_private *dev_priv = to_i915(dev);
10516         struct drm_framebuffer *old_fb = crtc->primary->fb;
10517         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10519         struct drm_plane *primary = crtc->primary;
10520         enum pipe pipe = intel_crtc->pipe;
10521         struct intel_flip_work *work;
10522         struct intel_engine_cs *engine;
10523         bool mmio_flip;
10524         struct drm_i915_gem_request *request;
10525         struct i915_vma *vma;
10526         int ret;
10527
10528         /*
10529          * drm_mode_page_flip_ioctl() should already catch this, but double
10530          * check to be safe.  In the future we may enable pageflipping from
10531          * a disabled primary plane.
10532          */
10533         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10534                 return -EBUSY;
10535
10536         /* Can't change pixel format via MI display flips. */
10537         if (fb->format != crtc->primary->fb->format)
10538                 return -EINVAL;
10539
10540         /*
10541          * TILEOFF/LINOFF registers can't be changed via MI display flips.
10542          * Note that pitch changes could also affect these register.
10543          */
10544         if (INTEL_GEN(dev_priv) > 3 &&
10545             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10546              fb->pitches[0] != crtc->primary->fb->pitches[0]))
10547                 return -EINVAL;
10548
10549         if (i915_terminally_wedged(&dev_priv->gpu_error))
10550                 goto out_hang;
10551
10552         work = kzalloc(sizeof(*work), GFP_KERNEL);
10553         if (work == NULL)
10554                 return -ENOMEM;
10555
10556         work->event = event;
10557         work->crtc = crtc;
10558         work->old_fb = old_fb;
10559         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10560
10561         ret = drm_crtc_vblank_get(crtc);
10562         if (ret)
10563                 goto free_work;
10564
10565         /* We borrow the event spin lock for protecting flip_work */
10566         spin_lock_irq(&dev->event_lock);
10567         if (intel_crtc->flip_work) {
10568                 /* Before declaring the flip queue wedged, check if
10569                  * the hardware completed the operation behind our backs.
10570                  */
10571                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10572                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10573                         page_flip_completed(intel_crtc);
10574                 } else {
10575                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10576                         spin_unlock_irq(&dev->event_lock);
10577
10578                         drm_crtc_vblank_put(crtc);
10579                         kfree(work);
10580                         return -EBUSY;
10581                 }
10582         }
10583         intel_crtc->flip_work = work;
10584         spin_unlock_irq(&dev->event_lock);
10585
10586         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10587                 flush_workqueue(dev_priv->wq);
10588
10589         /* Reference the objects for the scheduled work. */
10590         drm_framebuffer_reference(work->old_fb);
10591
10592         crtc->primary->fb = fb;
10593         update_state_fb(crtc->primary);
10594
10595         work->pending_flip_obj = i915_gem_object_get(obj);
10596
10597         ret = i915_mutex_lock_interruptible(dev);
10598         if (ret)
10599                 goto cleanup;
10600
10601         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10602         if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) {
10603                 ret = -EIO;
10604                 goto unlock;
10605         }
10606
10607         atomic_inc(&intel_crtc->unpin_work_count);
10608
10609         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10610                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10611
10612         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10613                 engine = dev_priv->engine[BCS];
10614                 if (fb->modifier != old_fb->modifier)
10615                         /* vlv: DISPLAY_FLIP fails to change tiling */
10616                         engine = NULL;
10617         } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10618                 engine = dev_priv->engine[BCS];
10619         } else if (INTEL_GEN(dev_priv) >= 7) {
10620                 engine = i915_gem_object_last_write_engine(obj);
10621                 if (engine == NULL || engine->id != RCS)
10622                         engine = dev_priv->engine[BCS];
10623         } else {
10624                 engine = dev_priv->engine[RCS];
10625         }
10626
10627         mmio_flip = use_mmio_flip(engine, obj);
10628
10629         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10630         if (IS_ERR(vma)) {
10631                 ret = PTR_ERR(vma);
10632                 goto cleanup_pending;
10633         }
10634
10635         work->old_vma = to_intel_plane_state(primary->state)->vma;
10636         to_intel_plane_state(primary->state)->vma = vma;
10637
10638         work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10639         work->rotation = crtc->primary->state->rotation;
10640
10641         /*
10642          * There's the potential that the next frame will not be compatible with
10643          * FBC, so we want to call pre_update() before the actual page flip.
10644          * The problem is that pre_update() caches some information about the fb
10645          * object, so we want to do this only after the object is pinned. Let's
10646          * be on the safe side and do this immediately before scheduling the
10647          * flip.
10648          */
10649         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10650                              to_intel_plane_state(primary->state));
10651
10652         if (mmio_flip) {
10653                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10654                 queue_work(system_unbound_wq, &work->mmio_work);
10655         } else {
10656                 request = i915_gem_request_alloc(engine,
10657                                                  dev_priv->kernel_context);
10658                 if (IS_ERR(request)) {
10659                         ret = PTR_ERR(request);
10660                         goto cleanup_unpin;
10661                 }
10662
10663                 ret = i915_gem_request_await_object(request, obj, false);
10664                 if (ret)
10665                         goto cleanup_request;
10666
10667                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10668                                                    page_flip_flags);
10669                 if (ret)
10670                         goto cleanup_request;
10671
10672                 intel_mark_page_flip_active(intel_crtc, work);
10673
10674                 work->flip_queued_req = i915_gem_request_get(request);
10675                 i915_add_request(request);
10676         }
10677
10678         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10679         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10680                           to_intel_plane(primary)->frontbuffer_bit);
10681         mutex_unlock(&dev->struct_mutex);
10682
10683         intel_frontbuffer_flip_prepare(to_i915(dev),
10684                                        to_intel_plane(primary)->frontbuffer_bit);
10685
10686         trace_i915_flip_request(intel_crtc->plane, obj);
10687
10688         return 0;
10689
10690 cleanup_request:
10691         i915_add_request(request);
10692 cleanup_unpin:
10693         to_intel_plane_state(primary->state)->vma = work->old_vma;
10694         intel_unpin_fb_vma(vma);
10695 cleanup_pending:
10696         atomic_dec(&intel_crtc->unpin_work_count);
10697 unlock:
10698         mutex_unlock(&dev->struct_mutex);
10699 cleanup:
10700         crtc->primary->fb = old_fb;
10701         update_state_fb(crtc->primary);
10702
10703         i915_gem_object_put(obj);
10704         drm_framebuffer_unreference(work->old_fb);
10705
10706         spin_lock_irq(&dev->event_lock);
10707         intel_crtc->flip_work = NULL;
10708         spin_unlock_irq(&dev->event_lock);
10709
10710         drm_crtc_vblank_put(crtc);
10711 free_work:
10712         kfree(work);
10713
10714         if (ret == -EIO) {
10715                 struct drm_atomic_state *state;
10716                 struct drm_plane_state *plane_state;
10717
10718 out_hang:
10719                 state = drm_atomic_state_alloc(dev);
10720                 if (!state)
10721                         return -ENOMEM;
10722                 state->acquire_ctx = dev->mode_config.acquire_ctx;
10723
10724 retry:
10725                 plane_state = drm_atomic_get_plane_state(state, primary);
10726                 ret = PTR_ERR_OR_ZERO(plane_state);
10727                 if (!ret) {
10728                         drm_atomic_set_fb_for_plane(plane_state, fb);
10729
10730                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10731                         if (!ret)
10732                                 ret = drm_atomic_commit(state);
10733                 }
10734
10735                 if (ret == -EDEADLK) {
10736                         drm_modeset_backoff(state->acquire_ctx);
10737                         drm_atomic_state_clear(state);
10738                         goto retry;
10739                 }
10740
10741                 drm_atomic_state_put(state);
10742
10743                 if (ret == 0 && event) {
10744                         spin_lock_irq(&dev->event_lock);
10745                         drm_crtc_send_vblank_event(crtc, event);
10746                         spin_unlock_irq(&dev->event_lock);
10747                 }
10748         }
10749         return ret;
10750 }
10751
10752
10753 /**
10754  * intel_wm_need_update - Check whether watermarks need updating
10755  * @plane: drm plane
10756  * @state: new plane state
10757  *
10758  * Check current plane state versus the new one to determine whether
10759  * watermarks need to be recalculated.
10760  *
10761  * Returns true or false.
10762  */
10763 static bool intel_wm_need_update(struct drm_plane *plane,
10764                                  struct drm_plane_state *state)
10765 {
10766         struct intel_plane_state *new = to_intel_plane_state(state);
10767         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10768
10769         /* Update watermarks on tiling or size changes. */
10770         if (new->base.visible != cur->base.visible)
10771                 return true;
10772
10773         if (!cur->base.fb || !new->base.fb)
10774                 return false;
10775
10776         if (cur->base.fb->modifier != new->base.fb->modifier ||
10777             cur->base.rotation != new->base.rotation ||
10778             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10779             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10780             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10781             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10782                 return true;
10783
10784         return false;
10785 }
10786
10787 static bool needs_scaling(struct intel_plane_state *state)
10788 {
10789         int src_w = drm_rect_width(&state->base.src) >> 16;
10790         int src_h = drm_rect_height(&state->base.src) >> 16;
10791         int dst_w = drm_rect_width(&state->base.dst);
10792         int dst_h = drm_rect_height(&state->base.dst);
10793
10794         return (src_w != dst_w || src_h != dst_h);
10795 }
10796
10797 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10798                                     struct drm_plane_state *plane_state)
10799 {
10800         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10801         struct drm_crtc *crtc = crtc_state->crtc;
10802         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10803         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10804         struct drm_device *dev = crtc->dev;
10805         struct drm_i915_private *dev_priv = to_i915(dev);
10806         struct intel_plane_state *old_plane_state =
10807                 to_intel_plane_state(plane->base.state);
10808         bool mode_changed = needs_modeset(crtc_state);
10809         bool was_crtc_enabled = crtc->state->active;
10810         bool is_crtc_enabled = crtc_state->active;
10811         bool turn_off, turn_on, visible, was_visible;
10812         struct drm_framebuffer *fb = plane_state->fb;
10813         int ret;
10814
10815         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10816                 ret = skl_update_scaler_plane(
10817                         to_intel_crtc_state(crtc_state),
10818                         to_intel_plane_state(plane_state));
10819                 if (ret)
10820                         return ret;
10821         }
10822
10823         was_visible = old_plane_state->base.visible;
10824         visible = plane_state->visible;
10825
10826         if (!was_crtc_enabled && WARN_ON(was_visible))
10827                 was_visible = false;
10828
10829         /*
10830          * Visibility is calculated as if the crtc was on, but
10831          * after scaler setup everything depends on it being off
10832          * when the crtc isn't active.
10833          *
10834          * FIXME this is wrong for watermarks. Watermarks should also
10835          * be computed as if the pipe would be active. Perhaps move
10836          * per-plane wm computation to the .check_plane() hook, and
10837          * only combine the results from all planes in the current place?
10838          */
10839         if (!is_crtc_enabled) {
10840                 plane_state->visible = visible = false;
10841                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10842         }
10843
10844         if (!was_visible && !visible)
10845                 return 0;
10846
10847         if (fb != old_plane_state->base.fb)
10848                 pipe_config->fb_changed = true;
10849
10850         turn_off = was_visible && (!visible || mode_changed);
10851         turn_on = visible && (!was_visible || mode_changed);
10852
10853         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10854                          intel_crtc->base.base.id, intel_crtc->base.name,
10855                          plane->base.base.id, plane->base.name,
10856                          fb ? fb->base.id : -1);
10857
10858         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10859                          plane->base.base.id, plane->base.name,
10860                          was_visible, visible,
10861                          turn_off, turn_on, mode_changed);
10862
10863         if (turn_on) {
10864                 if (INTEL_GEN(dev_priv) < 5)
10865                         pipe_config->update_wm_pre = true;
10866
10867                 /* must disable cxsr around plane enable/disable */
10868                 if (plane->id != PLANE_CURSOR)
10869                         pipe_config->disable_cxsr = true;
10870         } else if (turn_off) {
10871                 if (INTEL_GEN(dev_priv) < 5)
10872                         pipe_config->update_wm_post = true;
10873
10874                 /* must disable cxsr around plane enable/disable */
10875                 if (plane->id != PLANE_CURSOR)
10876                         pipe_config->disable_cxsr = true;
10877         } else if (intel_wm_need_update(&plane->base, plane_state)) {
10878                 if (INTEL_GEN(dev_priv) < 5) {
10879                         /* FIXME bollocks */
10880                         pipe_config->update_wm_pre = true;
10881                         pipe_config->update_wm_post = true;
10882                 }
10883         }
10884
10885         if (visible || was_visible)
10886                 pipe_config->fb_bits |= plane->frontbuffer_bit;
10887
10888         /*
10889          * WaCxSRDisabledForSpriteScaling:ivb
10890          *
10891          * cstate->update_wm was already set above, so this flag will
10892          * take effect when we commit and program watermarks.
10893          */
10894         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10895             needs_scaling(to_intel_plane_state(plane_state)) &&
10896             !needs_scaling(old_plane_state))
10897                 pipe_config->disable_lp_wm = true;
10898
10899         return 0;
10900 }
10901
10902 static bool encoders_cloneable(const struct intel_encoder *a,
10903                                const struct intel_encoder *b)
10904 {
10905         /* masks could be asymmetric, so check both ways */
10906         return a == b || (a->cloneable & (1 << b->type) &&
10907                           b->cloneable & (1 << a->type));
10908 }
10909
10910 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10911                                          struct intel_crtc *crtc,
10912                                          struct intel_encoder *encoder)
10913 {
10914         struct intel_encoder *source_encoder;
10915         struct drm_connector *connector;
10916         struct drm_connector_state *connector_state;
10917         int i;
10918
10919         for_each_new_connector_in_state(state, connector, connector_state, i) {
10920                 if (connector_state->crtc != &crtc->base)
10921                         continue;
10922
10923                 source_encoder =
10924                         to_intel_encoder(connector_state->best_encoder);
10925                 if (!encoders_cloneable(encoder, source_encoder))
10926                         return false;
10927         }
10928
10929         return true;
10930 }
10931
10932 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10933                                    struct drm_crtc_state *crtc_state)
10934 {
10935         struct drm_device *dev = crtc->dev;
10936         struct drm_i915_private *dev_priv = to_i915(dev);
10937         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10938         struct intel_crtc_state *pipe_config =
10939                 to_intel_crtc_state(crtc_state);
10940         struct drm_atomic_state *state = crtc_state->state;
10941         int ret;
10942         bool mode_changed = needs_modeset(crtc_state);
10943
10944         if (mode_changed && !crtc_state->active)
10945                 pipe_config->update_wm_post = true;
10946
10947         if (mode_changed && crtc_state->enable &&
10948             dev_priv->display.crtc_compute_clock &&
10949             !WARN_ON(pipe_config->shared_dpll)) {
10950                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10951                                                            pipe_config);
10952                 if (ret)
10953                         return ret;
10954         }
10955
10956         if (crtc_state->color_mgmt_changed) {
10957                 ret = intel_color_check(crtc, crtc_state);
10958                 if (ret)
10959                         return ret;
10960
10961                 /*
10962                  * Changing color management on Intel hardware is
10963                  * handled as part of planes update.
10964                  */
10965                 crtc_state->planes_changed = true;
10966         }
10967
10968         ret = 0;
10969         if (dev_priv->display.compute_pipe_wm) {
10970                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10971                 if (ret) {
10972                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10973                         return ret;
10974                 }
10975         }
10976
10977         if (dev_priv->display.compute_intermediate_wm &&
10978             !to_intel_atomic_state(state)->skip_intermediate_wm) {
10979                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10980                         return 0;
10981
10982                 /*
10983                  * Calculate 'intermediate' watermarks that satisfy both the
10984                  * old state and the new state.  We can program these
10985                  * immediately.
10986                  */
10987                 ret = dev_priv->display.compute_intermediate_wm(dev,
10988                                                                 intel_crtc,
10989                                                                 pipe_config);
10990                 if (ret) {
10991                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10992                         return ret;
10993                 }
10994         } else if (dev_priv->display.compute_intermediate_wm) {
10995                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10996                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10997         }
10998
10999         if (INTEL_GEN(dev_priv) >= 9) {
11000                 if (mode_changed)
11001                         ret = skl_update_scaler_crtc(pipe_config);
11002
11003                 if (!ret)
11004                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11005                                                          pipe_config);
11006         }
11007
11008         return ret;
11009 }
11010
11011 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11012         .atomic_begin = intel_begin_crtc_commit,
11013         .atomic_flush = intel_finish_crtc_commit,
11014         .atomic_check = intel_crtc_atomic_check,
11015 };
11016
11017 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11018 {
11019         struct intel_connector *connector;
11020         struct drm_connector_list_iter conn_iter;
11021
11022         drm_connector_list_iter_begin(dev, &conn_iter);
11023         for_each_intel_connector_iter(connector, &conn_iter) {
11024                 if (connector->base.state->crtc)
11025                         drm_connector_unreference(&connector->base);
11026
11027                 if (connector->base.encoder) {
11028                         connector->base.state->best_encoder =
11029                                 connector->base.encoder;
11030                         connector->base.state->crtc =
11031                                 connector->base.encoder->crtc;
11032
11033                         drm_connector_reference(&connector->base);
11034                 } else {
11035                         connector->base.state->best_encoder = NULL;
11036                         connector->base.state->crtc = NULL;
11037                 }
11038         }
11039         drm_connector_list_iter_end(&conn_iter);
11040 }
11041
11042 static void
11043 connected_sink_compute_bpp(struct intel_connector *connector,
11044                            struct intel_crtc_state *pipe_config)
11045 {
11046         const struct drm_display_info *info = &connector->base.display_info;
11047         int bpp = pipe_config->pipe_bpp;
11048
11049         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11050                       connector->base.base.id,
11051                       connector->base.name);
11052
11053         /* Don't use an invalid EDID bpc value */
11054         if (info->bpc != 0 && info->bpc * 3 < bpp) {
11055                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11056                               bpp, info->bpc * 3);
11057                 pipe_config->pipe_bpp = info->bpc * 3;
11058         }
11059
11060         /* Clamp bpp to 8 on screens without EDID 1.4 */
11061         if (info->bpc == 0 && bpp > 24) {
11062                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11063                               bpp);
11064                 pipe_config->pipe_bpp = 24;
11065         }
11066 }
11067
11068 static int
11069 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11070                           struct intel_crtc_state *pipe_config)
11071 {
11072         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11073         struct drm_atomic_state *state;
11074         struct drm_connector *connector;
11075         struct drm_connector_state *connector_state;
11076         int bpp, i;
11077
11078         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11079             IS_CHERRYVIEW(dev_priv)))
11080                 bpp = 10*3;
11081         else if (INTEL_GEN(dev_priv) >= 5)
11082                 bpp = 12*3;
11083         else
11084                 bpp = 8*3;
11085
11086
11087         pipe_config->pipe_bpp = bpp;
11088
11089         state = pipe_config->base.state;
11090
11091         /* Clamp display bpp to EDID value */
11092         for_each_new_connector_in_state(state, connector, connector_state, i) {
11093                 if (connector_state->crtc != &crtc->base)
11094                         continue;
11095
11096                 connected_sink_compute_bpp(to_intel_connector(connector),
11097                                            pipe_config);
11098         }
11099
11100         return bpp;
11101 }
11102
11103 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11104 {
11105         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11106                         "type: 0x%x flags: 0x%x\n",
11107                 mode->crtc_clock,
11108                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11109                 mode->crtc_hsync_end, mode->crtc_htotal,
11110                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11111                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11112 }
11113
11114 static inline void
11115 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11116                       unsigned int lane_count, struct intel_link_m_n *m_n)
11117 {
11118         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11119                       id, lane_count,
11120                       m_n->gmch_m, m_n->gmch_n,
11121                       m_n->link_m, m_n->link_n, m_n->tu);
11122 }
11123
11124 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11125                                    struct intel_crtc_state *pipe_config,
11126                                    const char *context)
11127 {
11128         struct drm_device *dev = crtc->base.dev;
11129         struct drm_i915_private *dev_priv = to_i915(dev);
11130         struct drm_plane *plane;
11131         struct intel_plane *intel_plane;
11132         struct intel_plane_state *state;
11133         struct drm_framebuffer *fb;
11134
11135         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11136                       crtc->base.base.id, crtc->base.name, context);
11137
11138         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11139                       transcoder_name(pipe_config->cpu_transcoder),
11140                       pipe_config->pipe_bpp, pipe_config->dither);
11141
11142         if (pipe_config->has_pch_encoder)
11143                 intel_dump_m_n_config(pipe_config, "fdi",
11144                                       pipe_config->fdi_lanes,
11145                                       &pipe_config->fdi_m_n);
11146
11147         if (intel_crtc_has_dp_encoder(pipe_config)) {
11148                 intel_dump_m_n_config(pipe_config, "dp m_n",
11149                                 pipe_config->lane_count, &pipe_config->dp_m_n);
11150                 if (pipe_config->has_drrs)
11151                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
11152                                               pipe_config->lane_count,
11153                                               &pipe_config->dp_m2_n2);
11154         }
11155
11156         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11157                       pipe_config->has_audio, pipe_config->has_infoframe);
11158
11159         DRM_DEBUG_KMS("requested mode:\n");
11160         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11161         DRM_DEBUG_KMS("adjusted mode:\n");
11162         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11163         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11164         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11165                       pipe_config->port_clock,
11166                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11167                       pipe_config->pixel_rate);
11168
11169         if (INTEL_GEN(dev_priv) >= 9)
11170                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11171                               crtc->num_scalers,
11172                               pipe_config->scaler_state.scaler_users,
11173                               pipe_config->scaler_state.scaler_id);
11174
11175         if (HAS_GMCH_DISPLAY(dev_priv))
11176                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11177                               pipe_config->gmch_pfit.control,
11178                               pipe_config->gmch_pfit.pgm_ratios,
11179                               pipe_config->gmch_pfit.lvds_border_bits);
11180         else
11181                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11182                               pipe_config->pch_pfit.pos,
11183                               pipe_config->pch_pfit.size,
11184                               enableddisabled(pipe_config->pch_pfit.enabled));
11185
11186         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11187                       pipe_config->ips_enabled, pipe_config->double_wide);
11188
11189         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11190
11191         DRM_DEBUG_KMS("planes on this crtc\n");
11192         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11193                 struct drm_format_name_buf format_name;
11194                 intel_plane = to_intel_plane(plane);
11195                 if (intel_plane->pipe != crtc->pipe)
11196                         continue;
11197
11198                 state = to_intel_plane_state(plane->state);
11199                 fb = state->base.fb;
11200                 if (!fb) {
11201                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11202                                       plane->base.id, plane->name, state->scaler_id);
11203                         continue;
11204                 }
11205
11206                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11207                               plane->base.id, plane->name,
11208                               fb->base.id, fb->width, fb->height,
11209                               drm_get_format_name(fb->format->format, &format_name));
11210                 if (INTEL_GEN(dev_priv) >= 9)
11211                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11212                                       state->scaler_id,
11213                                       state->base.src.x1 >> 16,
11214                                       state->base.src.y1 >> 16,
11215                                       drm_rect_width(&state->base.src) >> 16,
11216                                       drm_rect_height(&state->base.src) >> 16,
11217                                       state->base.dst.x1, state->base.dst.y1,
11218                                       drm_rect_width(&state->base.dst),
11219                                       drm_rect_height(&state->base.dst));
11220         }
11221 }
11222
11223 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11224 {
11225         struct drm_device *dev = state->dev;
11226         struct drm_connector *connector;
11227         unsigned int used_ports = 0;
11228         unsigned int used_mst_ports = 0;
11229
11230         /*
11231          * Walk the connector list instead of the encoder
11232          * list to detect the problem on ddi platforms
11233          * where there's just one encoder per digital port.
11234          */
11235         drm_for_each_connector(connector, dev) {
11236                 struct drm_connector_state *connector_state;
11237                 struct intel_encoder *encoder;
11238
11239                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11240                 if (!connector_state)
11241                         connector_state = connector->state;
11242
11243                 if (!connector_state->best_encoder)
11244                         continue;
11245
11246                 encoder = to_intel_encoder(connector_state->best_encoder);
11247
11248                 WARN_ON(!connector_state->crtc);
11249
11250                 switch (encoder->type) {
11251                         unsigned int port_mask;
11252                 case INTEL_OUTPUT_UNKNOWN:
11253                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
11254                                 break;
11255                 case INTEL_OUTPUT_DP:
11256                 case INTEL_OUTPUT_HDMI:
11257                 case INTEL_OUTPUT_EDP:
11258                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11259
11260                         /* the same port mustn't appear more than once */
11261                         if (used_ports & port_mask)
11262                                 return false;
11263
11264                         used_ports |= port_mask;
11265                         break;
11266                 case INTEL_OUTPUT_DP_MST:
11267                         used_mst_ports |=
11268                                 1 << enc_to_mst(&encoder->base)->primary->port;
11269                         break;
11270                 default:
11271                         break;
11272                 }
11273         }
11274
11275         /* can't mix MST and SST/HDMI on the same port */
11276         if (used_ports & used_mst_ports)
11277                 return false;
11278
11279         return true;
11280 }
11281
11282 static void
11283 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11284 {
11285         struct drm_i915_private *dev_priv =
11286                 to_i915(crtc_state->base.crtc->dev);
11287         struct intel_crtc_scaler_state scaler_state;
11288         struct intel_dpll_hw_state dpll_hw_state;
11289         struct intel_shared_dpll *shared_dpll;
11290         struct intel_crtc_wm_state wm_state;
11291         bool force_thru;
11292
11293         /* FIXME: before the switch to atomic started, a new pipe_config was
11294          * kzalloc'd. Code that depends on any field being zero should be
11295          * fixed, so that the crtc_state can be safely duplicated. For now,
11296          * only fields that are know to not cause problems are preserved. */
11297
11298         scaler_state = crtc_state->scaler_state;
11299         shared_dpll = crtc_state->shared_dpll;
11300         dpll_hw_state = crtc_state->dpll_hw_state;
11301         force_thru = crtc_state->pch_pfit.force_thru;
11302         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11303                 wm_state = crtc_state->wm;
11304
11305         /* Keep base drm_crtc_state intact, only clear our extended struct */
11306         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11307         memset(&crtc_state->base + 1, 0,
11308                sizeof(*crtc_state) - sizeof(crtc_state->base));
11309
11310         crtc_state->scaler_state = scaler_state;
11311         crtc_state->shared_dpll = shared_dpll;
11312         crtc_state->dpll_hw_state = dpll_hw_state;
11313         crtc_state->pch_pfit.force_thru = force_thru;
11314         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11315                 crtc_state->wm = wm_state;
11316 }
11317
11318 static int
11319 intel_modeset_pipe_config(struct drm_crtc *crtc,
11320                           struct intel_crtc_state *pipe_config)
11321 {
11322         struct drm_atomic_state *state = pipe_config->base.state;
11323         struct intel_encoder *encoder;
11324         struct drm_connector *connector;
11325         struct drm_connector_state *connector_state;
11326         int base_bpp, ret = -EINVAL;
11327         int i;
11328         bool retry = true;
11329
11330         clear_intel_crtc_state(pipe_config);
11331
11332         pipe_config->cpu_transcoder =
11333                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11334
11335         /*
11336          * Sanitize sync polarity flags based on requested ones. If neither
11337          * positive or negative polarity is requested, treat this as meaning
11338          * negative polarity.
11339          */
11340         if (!(pipe_config->base.adjusted_mode.flags &
11341               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11342                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11343
11344         if (!(pipe_config->base.adjusted_mode.flags &
11345               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11346                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11347
11348         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11349                                              pipe_config);
11350         if (base_bpp < 0)
11351                 goto fail;
11352
11353         /*
11354          * Determine the real pipe dimensions. Note that stereo modes can
11355          * increase the actual pipe size due to the frame doubling and
11356          * insertion of additional space for blanks between the frame. This
11357          * is stored in the crtc timings. We use the requested mode to do this
11358          * computation to clearly distinguish it from the adjusted mode, which
11359          * can be changed by the connectors in the below retry loop.
11360          */
11361         drm_mode_get_hv_timing(&pipe_config->base.mode,
11362                                &pipe_config->pipe_src_w,
11363                                &pipe_config->pipe_src_h);
11364
11365         for_each_new_connector_in_state(state, connector, connector_state, i) {
11366                 if (connector_state->crtc != crtc)
11367                         continue;
11368
11369                 encoder = to_intel_encoder(connector_state->best_encoder);
11370
11371                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11372                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11373                         goto fail;
11374                 }
11375
11376                 /*
11377                  * Determine output_types before calling the .compute_config()
11378                  * hooks so that the hooks can use this information safely.
11379                  */
11380                 pipe_config->output_types |= 1 << encoder->type;
11381         }
11382
11383 encoder_retry:
11384         /* Ensure the port clock defaults are reset when retrying. */
11385         pipe_config->port_clock = 0;
11386         pipe_config->pixel_multiplier = 1;
11387
11388         /* Fill in default crtc timings, allow encoders to overwrite them. */
11389         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11390                               CRTC_STEREO_DOUBLE);
11391
11392         /* Pass our mode to the connectors and the CRTC to give them a chance to
11393          * adjust it according to limitations or connector properties, and also
11394          * a chance to reject the mode entirely.
11395          */
11396         for_each_new_connector_in_state(state, connector, connector_state, i) {
11397                 if (connector_state->crtc != crtc)
11398                         continue;
11399
11400                 encoder = to_intel_encoder(connector_state->best_encoder);
11401
11402                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11403                         DRM_DEBUG_KMS("Encoder config failure\n");
11404                         goto fail;
11405                 }
11406         }
11407
11408         /* Set default port clock if not overwritten by the encoder. Needs to be
11409          * done afterwards in case the encoder adjusts the mode. */
11410         if (!pipe_config->port_clock)
11411                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11412                         * pipe_config->pixel_multiplier;
11413
11414         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11415         if (ret < 0) {
11416                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11417                 goto fail;
11418         }
11419
11420         if (ret == RETRY) {
11421                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11422                         ret = -EINVAL;
11423                         goto fail;
11424                 }
11425
11426                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11427                 retry = false;
11428                 goto encoder_retry;
11429         }
11430
11431         /* Dithering seems to not pass-through bits correctly when it should, so
11432          * only enable it on 6bpc panels and when its not a compliance
11433          * test requesting 6bpc video pattern.
11434          */
11435         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11436                 !pipe_config->dither_force_disable;
11437         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11438                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11439
11440 fail:
11441         return ret;
11442 }
11443
11444 static void
11445 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11446 {
11447         struct drm_crtc *crtc;
11448         struct drm_crtc_state *new_crtc_state;
11449         int i;
11450
11451         /* Double check state. */
11452         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11453                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11454
11455                 /* Update hwmode for vblank functions */
11456                 if (new_crtc_state->active)
11457                         crtc->hwmode = new_crtc_state->adjusted_mode;
11458                 else
11459                         crtc->hwmode.crtc_clock = 0;
11460
11461                 /*
11462                  * Update legacy state to satisfy fbc code. This can
11463                  * be removed when fbc uses the atomic state.
11464                  */
11465                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11466                         struct drm_plane_state *plane_state = crtc->primary->state;
11467
11468                         crtc->primary->fb = plane_state->fb;
11469                         crtc->x = plane_state->src_x >> 16;
11470                         crtc->y = plane_state->src_y >> 16;
11471                 }
11472         }
11473 }
11474
11475 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11476 {
11477         int diff;
11478
11479         if (clock1 == clock2)
11480                 return true;
11481
11482         if (!clock1 || !clock2)
11483                 return false;
11484
11485         diff = abs(clock1 - clock2);
11486
11487         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11488                 return true;
11489
11490         return false;
11491 }
11492
11493 static bool
11494 intel_compare_m_n(unsigned int m, unsigned int n,
11495                   unsigned int m2, unsigned int n2,
11496                   bool exact)
11497 {
11498         if (m == m2 && n == n2)
11499                 return true;
11500
11501         if (exact || !m || !n || !m2 || !n2)
11502                 return false;
11503
11504         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11505
11506         if (n > n2) {
11507                 while (n > n2) {
11508                         m2 <<= 1;
11509                         n2 <<= 1;
11510                 }
11511         } else if (n < n2) {
11512                 while (n < n2) {
11513                         m <<= 1;
11514                         n <<= 1;
11515                 }
11516         }
11517
11518         if (n != n2)
11519                 return false;
11520
11521         return intel_fuzzy_clock_check(m, m2);
11522 }
11523
11524 static bool
11525 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11526                        struct intel_link_m_n *m2_n2,
11527                        bool adjust)
11528 {
11529         if (m_n->tu == m2_n2->tu &&
11530             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11531                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11532             intel_compare_m_n(m_n->link_m, m_n->link_n,
11533                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11534                 if (adjust)
11535                         *m2_n2 = *m_n;
11536
11537                 return true;
11538         }
11539
11540         return false;
11541 }
11542
11543 static void __printf(3, 4)
11544 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11545 {
11546         char *level;
11547         unsigned int category;
11548         struct va_format vaf;
11549         va_list args;
11550
11551         if (adjust) {
11552                 level = KERN_DEBUG;
11553                 category = DRM_UT_KMS;
11554         } else {
11555                 level = KERN_ERR;
11556                 category = DRM_UT_NONE;
11557         }
11558
11559         va_start(args, format);
11560         vaf.fmt = format;
11561         vaf.va = &args;
11562
11563         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11564
11565         va_end(args);
11566 }
11567
11568 static bool
11569 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11570                           struct intel_crtc_state *current_config,
11571                           struct intel_crtc_state *pipe_config,
11572                           bool adjust)
11573 {
11574         bool ret = true;
11575
11576 #define PIPE_CONF_CHECK_X(name) \
11577         if (current_config->name != pipe_config->name) { \
11578                 pipe_config_err(adjust, __stringify(name), \
11579                           "(expected 0x%08x, found 0x%08x)\n", \
11580                           current_config->name, \
11581                           pipe_config->name); \
11582                 ret = false; \
11583         }
11584
11585 #define PIPE_CONF_CHECK_I(name) \
11586         if (current_config->name != pipe_config->name) { \
11587                 pipe_config_err(adjust, __stringify(name), \
11588                           "(expected %i, found %i)\n", \
11589                           current_config->name, \
11590                           pipe_config->name); \
11591                 ret = false; \
11592         }
11593
11594 #define PIPE_CONF_CHECK_P(name) \
11595         if (current_config->name != pipe_config->name) { \
11596                 pipe_config_err(adjust, __stringify(name), \
11597                           "(expected %p, found %p)\n", \
11598                           current_config->name, \
11599                           pipe_config->name); \
11600                 ret = false; \
11601         }
11602
11603 #define PIPE_CONF_CHECK_M_N(name) \
11604         if (!intel_compare_link_m_n(&current_config->name, \
11605                                     &pipe_config->name,\
11606                                     adjust)) { \
11607                 pipe_config_err(adjust, __stringify(name), \
11608                           "(expected tu %i gmch %i/%i link %i/%i, " \
11609                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11610                           current_config->name.tu, \
11611                           current_config->name.gmch_m, \
11612                           current_config->name.gmch_n, \
11613                           current_config->name.link_m, \
11614                           current_config->name.link_n, \
11615                           pipe_config->name.tu, \
11616                           pipe_config->name.gmch_m, \
11617                           pipe_config->name.gmch_n, \
11618                           pipe_config->name.link_m, \
11619                           pipe_config->name.link_n); \
11620                 ret = false; \
11621         }
11622
11623 /* This is required for BDW+ where there is only one set of registers for
11624  * switching between high and low RR.
11625  * This macro can be used whenever a comparison has to be made between one
11626  * hw state and multiple sw state variables.
11627  */
11628 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11629         if (!intel_compare_link_m_n(&current_config->name, \
11630                                     &pipe_config->name, adjust) && \
11631             !intel_compare_link_m_n(&current_config->alt_name, \
11632                                     &pipe_config->name, adjust)) { \
11633                 pipe_config_err(adjust, __stringify(name), \
11634                           "(expected tu %i gmch %i/%i link %i/%i, " \
11635                           "or tu %i gmch %i/%i link %i/%i, " \
11636                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11637                           current_config->name.tu, \
11638                           current_config->name.gmch_m, \
11639                           current_config->name.gmch_n, \
11640                           current_config->name.link_m, \
11641                           current_config->name.link_n, \
11642                           current_config->alt_name.tu, \
11643                           current_config->alt_name.gmch_m, \
11644                           current_config->alt_name.gmch_n, \
11645                           current_config->alt_name.link_m, \
11646                           current_config->alt_name.link_n, \
11647                           pipe_config->name.tu, \
11648                           pipe_config->name.gmch_m, \
11649                           pipe_config->name.gmch_n, \
11650                           pipe_config->name.link_m, \
11651                           pipe_config->name.link_n); \
11652                 ret = false; \
11653         }
11654
11655 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11656         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11657                 pipe_config_err(adjust, __stringify(name), \
11658                           "(%x) (expected %i, found %i)\n", \
11659                           (mask), \
11660                           current_config->name & (mask), \
11661                           pipe_config->name & (mask)); \
11662                 ret = false; \
11663         }
11664
11665 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11666         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11667                 pipe_config_err(adjust, __stringify(name), \
11668                           "(expected %i, found %i)\n", \
11669                           current_config->name, \
11670                           pipe_config->name); \
11671                 ret = false; \
11672         }
11673
11674 #define PIPE_CONF_QUIRK(quirk)  \
11675         ((current_config->quirks | pipe_config->quirks) & (quirk))
11676
11677         PIPE_CONF_CHECK_I(cpu_transcoder);
11678
11679         PIPE_CONF_CHECK_I(has_pch_encoder);
11680         PIPE_CONF_CHECK_I(fdi_lanes);
11681         PIPE_CONF_CHECK_M_N(fdi_m_n);
11682
11683         PIPE_CONF_CHECK_I(lane_count);
11684         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11685
11686         if (INTEL_GEN(dev_priv) < 8) {
11687                 PIPE_CONF_CHECK_M_N(dp_m_n);
11688
11689                 if (current_config->has_drrs)
11690                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11691         } else
11692                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11693
11694         PIPE_CONF_CHECK_X(output_types);
11695
11696         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11697         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11698         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11699         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11700         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11701         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11702
11703         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11704         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11705         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11706         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11707         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11708         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11709
11710         PIPE_CONF_CHECK_I(pixel_multiplier);
11711         PIPE_CONF_CHECK_I(has_hdmi_sink);
11712         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11713             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11714                 PIPE_CONF_CHECK_I(limited_color_range);
11715
11716         PIPE_CONF_CHECK_I(hdmi_scrambling);
11717         PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11718         PIPE_CONF_CHECK_I(has_infoframe);
11719
11720         PIPE_CONF_CHECK_I(has_audio);
11721
11722         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11723                               DRM_MODE_FLAG_INTERLACE);
11724
11725         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11726                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11727                                       DRM_MODE_FLAG_PHSYNC);
11728                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11729                                       DRM_MODE_FLAG_NHSYNC);
11730                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11731                                       DRM_MODE_FLAG_PVSYNC);
11732                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11733                                       DRM_MODE_FLAG_NVSYNC);
11734         }
11735
11736         PIPE_CONF_CHECK_X(gmch_pfit.control);
11737         /* pfit ratios are autocomputed by the hw on gen4+ */
11738         if (INTEL_GEN(dev_priv) < 4)
11739                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11740         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11741
11742         if (!adjust) {
11743                 PIPE_CONF_CHECK_I(pipe_src_w);
11744                 PIPE_CONF_CHECK_I(pipe_src_h);
11745
11746                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11747                 if (current_config->pch_pfit.enabled) {
11748                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11749                         PIPE_CONF_CHECK_X(pch_pfit.size);
11750                 }
11751
11752                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11753                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11754         }
11755
11756         /* BDW+ don't expose a synchronous way to read the state */
11757         if (IS_HASWELL(dev_priv))
11758                 PIPE_CONF_CHECK_I(ips_enabled);
11759
11760         PIPE_CONF_CHECK_I(double_wide);
11761
11762         PIPE_CONF_CHECK_P(shared_dpll);
11763         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11764         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11765         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11766         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11767         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11768         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11769         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11770         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11771         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11772
11773         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11774         PIPE_CONF_CHECK_X(dsi_pll.div);
11775
11776         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11777                 PIPE_CONF_CHECK_I(pipe_bpp);
11778
11779         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11780         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11781
11782 #undef PIPE_CONF_CHECK_X
11783 #undef PIPE_CONF_CHECK_I
11784 #undef PIPE_CONF_CHECK_P
11785 #undef PIPE_CONF_CHECK_FLAGS
11786 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11787 #undef PIPE_CONF_QUIRK
11788
11789         return ret;
11790 }
11791
11792 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11793                                            const struct intel_crtc_state *pipe_config)
11794 {
11795         if (pipe_config->has_pch_encoder) {
11796                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11797                                                             &pipe_config->fdi_m_n);
11798                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11799
11800                 /*
11801                  * FDI already provided one idea for the dotclock.
11802                  * Yell if the encoder disagrees.
11803                  */
11804                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11805                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11806                      fdi_dotclock, dotclock);
11807         }
11808 }
11809
11810 static void verify_wm_state(struct drm_crtc *crtc,
11811                             struct drm_crtc_state *new_state)
11812 {
11813         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11814         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11815         struct skl_pipe_wm hw_wm, *sw_wm;
11816         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11817         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11819         const enum pipe pipe = intel_crtc->pipe;
11820         int plane, level, max_level = ilk_wm_max_level(dev_priv);
11821
11822         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11823                 return;
11824
11825         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11826         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11827
11828         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11829         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11830
11831         /* planes */
11832         for_each_universal_plane(dev_priv, pipe, plane) {
11833                 hw_plane_wm = &hw_wm.planes[plane];
11834                 sw_plane_wm = &sw_wm->planes[plane];
11835
11836                 /* Watermarks */
11837                 for (level = 0; level <= max_level; level++) {
11838                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11839                                                 &sw_plane_wm->wm[level]))
11840                                 continue;
11841
11842                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11843                                   pipe_name(pipe), plane + 1, level,
11844                                   sw_plane_wm->wm[level].plane_en,
11845                                   sw_plane_wm->wm[level].plane_res_b,
11846                                   sw_plane_wm->wm[level].plane_res_l,
11847                                   hw_plane_wm->wm[level].plane_en,
11848                                   hw_plane_wm->wm[level].plane_res_b,
11849                                   hw_plane_wm->wm[level].plane_res_l);
11850                 }
11851
11852                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11853                                          &sw_plane_wm->trans_wm)) {
11854                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11855                                   pipe_name(pipe), plane + 1,
11856                                   sw_plane_wm->trans_wm.plane_en,
11857                                   sw_plane_wm->trans_wm.plane_res_b,
11858                                   sw_plane_wm->trans_wm.plane_res_l,
11859                                   hw_plane_wm->trans_wm.plane_en,
11860                                   hw_plane_wm->trans_wm.plane_res_b,
11861                                   hw_plane_wm->trans_wm.plane_res_l);
11862                 }
11863
11864                 /* DDB */
11865                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11866                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11867
11868                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11869                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11870                                   pipe_name(pipe), plane + 1,
11871                                   sw_ddb_entry->start, sw_ddb_entry->end,
11872                                   hw_ddb_entry->start, hw_ddb_entry->end);
11873                 }
11874         }
11875
11876         /*
11877          * cursor
11878          * If the cursor plane isn't active, we may not have updated it's ddb
11879          * allocation. In that case since the ddb allocation will be updated
11880          * once the plane becomes visible, we can skip this check
11881          */
11882         if (intel_crtc->cursor_addr) {
11883                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11884                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11885
11886                 /* Watermarks */
11887                 for (level = 0; level <= max_level; level++) {
11888                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11889                                                 &sw_plane_wm->wm[level]))
11890                                 continue;
11891
11892                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11893                                   pipe_name(pipe), level,
11894                                   sw_plane_wm->wm[level].plane_en,
11895                                   sw_plane_wm->wm[level].plane_res_b,
11896                                   sw_plane_wm->wm[level].plane_res_l,
11897                                   hw_plane_wm->wm[level].plane_en,
11898                                   hw_plane_wm->wm[level].plane_res_b,
11899                                   hw_plane_wm->wm[level].plane_res_l);
11900                 }
11901
11902                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11903                                          &sw_plane_wm->trans_wm)) {
11904                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11905                                   pipe_name(pipe),
11906                                   sw_plane_wm->trans_wm.plane_en,
11907                                   sw_plane_wm->trans_wm.plane_res_b,
11908                                   sw_plane_wm->trans_wm.plane_res_l,
11909                                   hw_plane_wm->trans_wm.plane_en,
11910                                   hw_plane_wm->trans_wm.plane_res_b,
11911                                   hw_plane_wm->trans_wm.plane_res_l);
11912                 }
11913
11914                 /* DDB */
11915                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11916                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11917
11918                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11919                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11920                                   pipe_name(pipe),
11921                                   sw_ddb_entry->start, sw_ddb_entry->end,
11922                                   hw_ddb_entry->start, hw_ddb_entry->end);
11923                 }
11924         }
11925 }
11926
11927 static void
11928 verify_connector_state(struct drm_device *dev,
11929                        struct drm_atomic_state *state,
11930                        struct drm_crtc *crtc)
11931 {
11932         struct drm_connector *connector;
11933         struct drm_connector_state *new_conn_state;
11934         int i;
11935
11936         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11937                 struct drm_encoder *encoder = connector->encoder;
11938
11939                 if (new_conn_state->crtc != crtc)
11940                         continue;
11941
11942                 intel_connector_verify_state(to_intel_connector(connector));
11943
11944                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11945                      "connector's atomic encoder doesn't match legacy encoder\n");
11946         }
11947 }
11948
11949 static void
11950 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11951 {
11952         struct intel_encoder *encoder;
11953         struct drm_connector *connector;
11954         struct drm_connector_state *old_conn_state, *new_conn_state;
11955         int i;
11956
11957         for_each_intel_encoder(dev, encoder) {
11958                 bool enabled = false, found = false;
11959                 enum pipe pipe;
11960
11961                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11962                               encoder->base.base.id,
11963                               encoder->base.name);
11964
11965                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11966                                                    new_conn_state, i) {
11967                         if (old_conn_state->best_encoder == &encoder->base)
11968                                 found = true;
11969
11970                         if (new_conn_state->best_encoder != &encoder->base)
11971                                 continue;
11972                         found = enabled = true;
11973
11974                         I915_STATE_WARN(new_conn_state->crtc !=
11975                                         encoder->base.crtc,
11976                              "connector's crtc doesn't match encoder crtc\n");
11977                 }
11978
11979                 if (!found)
11980                         continue;
11981
11982                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11983                      "encoder's enabled state mismatch "
11984                      "(expected %i, found %i)\n",
11985                      !!encoder->base.crtc, enabled);
11986
11987                 if (!encoder->base.crtc) {
11988                         bool active;
11989
11990                         active = encoder->get_hw_state(encoder, &pipe);
11991                         I915_STATE_WARN(active,
11992                              "encoder detached but still enabled on pipe %c.\n",
11993                              pipe_name(pipe));
11994                 }
11995         }
11996 }
11997
11998 static void
11999 verify_crtc_state(struct drm_crtc *crtc,
12000                   struct drm_crtc_state *old_crtc_state,
12001                   struct drm_crtc_state *new_crtc_state)
12002 {
12003         struct drm_device *dev = crtc->dev;
12004         struct drm_i915_private *dev_priv = to_i915(dev);
12005         struct intel_encoder *encoder;
12006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12007         struct intel_crtc_state *pipe_config, *sw_config;
12008         struct drm_atomic_state *old_state;
12009         bool active;
12010
12011         old_state = old_crtc_state->state;
12012         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12013         pipe_config = to_intel_crtc_state(old_crtc_state);
12014         memset(pipe_config, 0, sizeof(*pipe_config));
12015         pipe_config->base.crtc = crtc;
12016         pipe_config->base.state = old_state;
12017
12018         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12019
12020         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12021
12022         /* hw state is inconsistent with the pipe quirk */
12023         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12024             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12025                 active = new_crtc_state->active;
12026
12027         I915_STATE_WARN(new_crtc_state->active != active,
12028              "crtc active state doesn't match with hw state "
12029              "(expected %i, found %i)\n", new_crtc_state->active, active);
12030
12031         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12032              "transitional active state does not match atomic hw state "
12033              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12034
12035         for_each_encoder_on_crtc(dev, crtc, encoder) {
12036                 enum pipe pipe;
12037
12038                 active = encoder->get_hw_state(encoder, &pipe);
12039                 I915_STATE_WARN(active != new_crtc_state->active,
12040                         "[ENCODER:%i] active %i with crtc active %i\n",
12041                         encoder->base.base.id, active, new_crtc_state->active);
12042
12043                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12044                                 "Encoder connected to wrong pipe %c\n",
12045                                 pipe_name(pipe));
12046
12047                 if (active) {
12048                         pipe_config->output_types |= 1 << encoder->type;
12049                         encoder->get_config(encoder, pipe_config);
12050                 }
12051         }
12052
12053         intel_crtc_compute_pixel_rate(pipe_config);
12054
12055         if (!new_crtc_state->active)
12056                 return;
12057
12058         intel_pipe_config_sanity_check(dev_priv, pipe_config);
12059
12060         sw_config = to_intel_crtc_state(crtc->state);
12061         if (!intel_pipe_config_compare(dev_priv, sw_config,
12062                                        pipe_config, false)) {
12063                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12064                 intel_dump_pipe_config(intel_crtc, pipe_config,
12065                                        "[hw state]");
12066                 intel_dump_pipe_config(intel_crtc, sw_config,
12067                                        "[sw state]");
12068         }
12069 }
12070
12071 static void
12072 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12073                          struct intel_shared_dpll *pll,
12074                          struct drm_crtc *crtc,
12075                          struct drm_crtc_state *new_state)
12076 {
12077         struct intel_dpll_hw_state dpll_hw_state;
12078         unsigned crtc_mask;
12079         bool active;
12080
12081         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12082
12083         DRM_DEBUG_KMS("%s\n", pll->name);
12084
12085         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12086
12087         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12088                 I915_STATE_WARN(!pll->on && pll->active_mask,
12089                      "pll in active use but not on in sw tracking\n");
12090                 I915_STATE_WARN(pll->on && !pll->active_mask,
12091                      "pll is on but not used by any active crtc\n");
12092                 I915_STATE_WARN(pll->on != active,
12093                      "pll on state mismatch (expected %i, found %i)\n",
12094                      pll->on, active);
12095         }
12096
12097         if (!crtc) {
12098                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12099                                 "more active pll users than references: %x vs %x\n",
12100                                 pll->active_mask, pll->state.crtc_mask);
12101
12102                 return;
12103         }
12104
12105         crtc_mask = 1 << drm_crtc_index(crtc);
12106
12107         if (new_state->active)
12108                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12109                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12110                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12111         else
12112                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12113                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12114                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12115
12116         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12117                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12118                         crtc_mask, pll->state.crtc_mask);
12119
12120         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12121                                           &dpll_hw_state,
12122                                           sizeof(dpll_hw_state)),
12123                         "pll hw state mismatch\n");
12124 }
12125
12126 static void
12127 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12128                          struct drm_crtc_state *old_crtc_state,
12129                          struct drm_crtc_state *new_crtc_state)
12130 {
12131         struct drm_i915_private *dev_priv = to_i915(dev);
12132         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12133         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12134
12135         if (new_state->shared_dpll)
12136                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12137
12138         if (old_state->shared_dpll &&
12139             old_state->shared_dpll != new_state->shared_dpll) {
12140                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12141                 struct intel_shared_dpll *pll = old_state->shared_dpll;
12142
12143                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12144                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12145                                 pipe_name(drm_crtc_index(crtc)));
12146                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12147                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12148                                 pipe_name(drm_crtc_index(crtc)));
12149         }
12150 }
12151
12152 static void
12153 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12154                           struct drm_atomic_state *state,
12155                           struct drm_crtc_state *old_state,
12156                           struct drm_crtc_state *new_state)
12157 {
12158         if (!needs_modeset(new_state) &&
12159             !to_intel_crtc_state(new_state)->update_pipe)
12160                 return;
12161
12162         verify_wm_state(crtc, new_state);
12163         verify_connector_state(crtc->dev, state, crtc);
12164         verify_crtc_state(crtc, old_state, new_state);
12165         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12166 }
12167
12168 static void
12169 verify_disabled_dpll_state(struct drm_device *dev)
12170 {
12171         struct drm_i915_private *dev_priv = to_i915(dev);
12172         int i;
12173
12174         for (i = 0; i < dev_priv->num_shared_dpll; i++)
12175                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12176 }
12177
12178 static void
12179 intel_modeset_verify_disabled(struct drm_device *dev,
12180                               struct drm_atomic_state *state)
12181 {
12182         verify_encoder_state(dev, state);
12183         verify_connector_state(dev, state, NULL);
12184         verify_disabled_dpll_state(dev);
12185 }
12186
12187 static void update_scanline_offset(struct intel_crtc *crtc)
12188 {
12189         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12190
12191         /*
12192          * The scanline counter increments at the leading edge of hsync.
12193          *
12194          * On most platforms it starts counting from vtotal-1 on the
12195          * first active line. That means the scanline counter value is
12196          * always one less than what we would expect. Ie. just after
12197          * start of vblank, which also occurs at start of hsync (on the
12198          * last active line), the scanline counter will read vblank_start-1.
12199          *
12200          * On gen2 the scanline counter starts counting from 1 instead
12201          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12202          * to keep the value positive), instead of adding one.
12203          *
12204          * On HSW+ the behaviour of the scanline counter depends on the output
12205          * type. For DP ports it behaves like most other platforms, but on HDMI
12206          * there's an extra 1 line difference. So we need to add two instead of
12207          * one to the value.
12208          *
12209          * On VLV/CHV DSI the scanline counter would appear to increment
12210          * approx. 1/3 of a scanline before start of vblank. Unfortunately
12211          * that means we can't tell whether we're in vblank or not while
12212          * we're on that particular line. We must still set scanline_offset
12213          * to 1 so that the vblank timestamps come out correct when we query
12214          * the scanline counter from within the vblank interrupt handler.
12215          * However if queried just before the start of vblank we'll get an
12216          * answer that's slightly in the future.
12217          */
12218         if (IS_GEN2(dev_priv)) {
12219                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12220                 int vtotal;
12221
12222                 vtotal = adjusted_mode->crtc_vtotal;
12223                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12224                         vtotal /= 2;
12225
12226                 crtc->scanline_offset = vtotal - 1;
12227         } else if (HAS_DDI(dev_priv) &&
12228                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12229                 crtc->scanline_offset = 2;
12230         } else
12231                 crtc->scanline_offset = 1;
12232 }
12233
12234 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12235 {
12236         struct drm_device *dev = state->dev;
12237         struct drm_i915_private *dev_priv = to_i915(dev);
12238         struct drm_crtc *crtc;
12239         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12240         int i;
12241
12242         if (!dev_priv->display.crtc_compute_clock)
12243                 return;
12244
12245         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12246                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12247                 struct intel_shared_dpll *old_dpll =
12248                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
12249
12250                 if (!needs_modeset(new_crtc_state))
12251                         continue;
12252
12253                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12254
12255                 if (!old_dpll)
12256                         continue;
12257
12258                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12259         }
12260 }
12261
12262 /*
12263  * This implements the workaround described in the "notes" section of the mode
12264  * set sequence documentation. When going from no pipes or single pipe to
12265  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12266  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12267  */
12268 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12269 {
12270         struct drm_crtc_state *crtc_state;
12271         struct intel_crtc *intel_crtc;
12272         struct drm_crtc *crtc;
12273         struct intel_crtc_state *first_crtc_state = NULL;
12274         struct intel_crtc_state *other_crtc_state = NULL;
12275         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12276         int i;
12277
12278         /* look at all crtc's that are going to be enabled in during modeset */
12279         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12280                 intel_crtc = to_intel_crtc(crtc);
12281
12282                 if (!crtc_state->active || !needs_modeset(crtc_state))
12283                         continue;
12284
12285                 if (first_crtc_state) {
12286                         other_crtc_state = to_intel_crtc_state(crtc_state);
12287                         break;
12288                 } else {
12289                         first_crtc_state = to_intel_crtc_state(crtc_state);
12290                         first_pipe = intel_crtc->pipe;
12291                 }
12292         }
12293
12294         /* No workaround needed? */
12295         if (!first_crtc_state)
12296                 return 0;
12297
12298         /* w/a possibly needed, check how many crtc's are already enabled. */
12299         for_each_intel_crtc(state->dev, intel_crtc) {
12300                 struct intel_crtc_state *pipe_config;
12301
12302                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12303                 if (IS_ERR(pipe_config))
12304                         return PTR_ERR(pipe_config);
12305
12306                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12307
12308                 if (!pipe_config->base.active ||
12309                     needs_modeset(&pipe_config->base))
12310                         continue;
12311
12312                 /* 2 or more enabled crtcs means no need for w/a */
12313                 if (enabled_pipe != INVALID_PIPE)
12314                         return 0;
12315
12316                 enabled_pipe = intel_crtc->pipe;
12317         }
12318
12319         if (enabled_pipe != INVALID_PIPE)
12320                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12321         else if (other_crtc_state)
12322                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12323
12324         return 0;
12325 }
12326
12327 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12328 {
12329         struct drm_crtc *crtc;
12330
12331         /* Add all pipes to the state */
12332         for_each_crtc(state->dev, crtc) {
12333                 struct drm_crtc_state *crtc_state;
12334
12335                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12336                 if (IS_ERR(crtc_state))
12337                         return PTR_ERR(crtc_state);
12338         }
12339
12340         return 0;
12341 }
12342
12343 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12344 {
12345         struct drm_crtc *crtc;
12346
12347         /*
12348          * Add all pipes to the state, and force
12349          * a modeset on all the active ones.
12350          */
12351         for_each_crtc(state->dev, crtc) {
12352                 struct drm_crtc_state *crtc_state;
12353                 int ret;
12354
12355                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12356                 if (IS_ERR(crtc_state))
12357                         return PTR_ERR(crtc_state);
12358
12359                 if (!crtc_state->active || needs_modeset(crtc_state))
12360                         continue;
12361
12362                 crtc_state->mode_changed = true;
12363
12364                 ret = drm_atomic_add_affected_connectors(state, crtc);
12365                 if (ret)
12366                         return ret;
12367
12368                 ret = drm_atomic_add_affected_planes(state, crtc);
12369                 if (ret)
12370                         return ret;
12371         }
12372
12373         return 0;
12374 }
12375
12376 static int intel_modeset_checks(struct drm_atomic_state *state)
12377 {
12378         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12379         struct drm_i915_private *dev_priv = to_i915(state->dev);
12380         struct drm_crtc *crtc;
12381         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12382         int ret = 0, i;
12383
12384         if (!check_digital_port_conflicts(state)) {
12385                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12386                 return -EINVAL;
12387         }
12388
12389         intel_state->modeset = true;
12390         intel_state->active_crtcs = dev_priv->active_crtcs;
12391         intel_state->cdclk.logical = dev_priv->cdclk.logical;
12392         intel_state->cdclk.actual = dev_priv->cdclk.actual;
12393
12394         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12395                 if (new_crtc_state->active)
12396                         intel_state->active_crtcs |= 1 << i;
12397                 else
12398                         intel_state->active_crtcs &= ~(1 << i);
12399
12400                 if (old_crtc_state->active != new_crtc_state->active)
12401                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12402         }
12403
12404         /*
12405          * See if the config requires any additional preparation, e.g.
12406          * to adjust global state with pipes off.  We need to do this
12407          * here so we can get the modeset_pipe updated config for the new
12408          * mode set on this crtc.  For other crtcs we need to use the
12409          * adjusted_mode bits in the crtc directly.
12410          */
12411         if (dev_priv->display.modeset_calc_cdclk) {
12412                 ret = dev_priv->display.modeset_calc_cdclk(state);
12413                 if (ret < 0)
12414                         return ret;
12415
12416                 /*
12417                  * Writes to dev_priv->cdclk.logical must protected by
12418                  * holding all the crtc locks, even if we don't end up
12419                  * touching the hardware
12420                  */
12421                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12422                                                &intel_state->cdclk.logical)) {
12423                         ret = intel_lock_all_pipes(state);
12424                         if (ret < 0)
12425                                 return ret;
12426                 }
12427
12428                 /* All pipes must be switched off while we change the cdclk. */
12429                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12430                                                &intel_state->cdclk.actual)) {
12431                         ret = intel_modeset_all_pipes(state);
12432                         if (ret < 0)
12433                                 return ret;
12434                 }
12435
12436                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12437                               intel_state->cdclk.logical.cdclk,
12438                               intel_state->cdclk.actual.cdclk);
12439         } else {
12440                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12441         }
12442
12443         intel_modeset_clear_plls(state);
12444
12445         if (IS_HASWELL(dev_priv))
12446                 return haswell_mode_set_planes_workaround(state);
12447
12448         return 0;
12449 }
12450
12451 /*
12452  * Handle calculation of various watermark data at the end of the atomic check
12453  * phase.  The code here should be run after the per-crtc and per-plane 'check'
12454  * handlers to ensure that all derived state has been updated.
12455  */
12456 static int calc_watermark_data(struct drm_atomic_state *state)
12457 {
12458         struct drm_device *dev = state->dev;
12459         struct drm_i915_private *dev_priv = to_i915(dev);
12460
12461         /* Is there platform-specific watermark information to calculate? */
12462         if (dev_priv->display.compute_global_watermarks)
12463                 return dev_priv->display.compute_global_watermarks(state);
12464
12465         return 0;
12466 }
12467
12468 /**
12469  * intel_atomic_check - validate state object
12470  * @dev: drm device
12471  * @state: state to validate
12472  */
12473 static int intel_atomic_check(struct drm_device *dev,
12474                               struct drm_atomic_state *state)
12475 {
12476         struct drm_i915_private *dev_priv = to_i915(dev);
12477         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12478         struct drm_crtc *crtc;
12479         struct drm_crtc_state *old_crtc_state, *crtc_state;
12480         int ret, i;
12481         bool any_ms = false;
12482
12483         ret = drm_atomic_helper_check_modeset(dev, state);
12484         if (ret)
12485                 return ret;
12486
12487         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12488                 struct intel_crtc_state *pipe_config =
12489                         to_intel_crtc_state(crtc_state);
12490
12491                 /* Catch I915_MODE_FLAG_INHERITED */
12492                 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12493                         crtc_state->mode_changed = true;
12494
12495                 if (!needs_modeset(crtc_state))
12496                         continue;
12497
12498                 if (!crtc_state->enable) {
12499                         any_ms = true;
12500                         continue;
12501                 }
12502
12503                 /* FIXME: For only active_changed we shouldn't need to do any
12504                  * state recomputation at all. */
12505
12506                 ret = drm_atomic_add_affected_connectors(state, crtc);
12507                 if (ret)
12508                         return ret;
12509
12510                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12511                 if (ret) {
12512                         intel_dump_pipe_config(to_intel_crtc(crtc),
12513                                                pipe_config, "[failed]");
12514                         return ret;
12515                 }
12516
12517                 if (i915.fastboot &&
12518                     intel_pipe_config_compare(dev_priv,
12519                                         to_intel_crtc_state(old_crtc_state),
12520                                         pipe_config, true)) {
12521                         crtc_state->mode_changed = false;
12522                         pipe_config->update_pipe = true;
12523                 }
12524
12525                 if (needs_modeset(crtc_state))
12526                         any_ms = true;
12527
12528                 ret = drm_atomic_add_affected_planes(state, crtc);
12529                 if (ret)
12530                         return ret;
12531
12532                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12533                                        needs_modeset(crtc_state) ?
12534                                        "[modeset]" : "[fastset]");
12535         }
12536
12537         if (any_ms) {
12538                 ret = intel_modeset_checks(state);
12539
12540                 if (ret)
12541                         return ret;
12542         } else {
12543                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12544         }
12545
12546         ret = drm_atomic_helper_check_planes(dev, state);
12547         if (ret)
12548                 return ret;
12549
12550         intel_fbc_choose_crtc(dev_priv, state);
12551         return calc_watermark_data(state);
12552 }
12553
12554 static int intel_atomic_prepare_commit(struct drm_device *dev,
12555                                        struct drm_atomic_state *state)
12556 {
12557         struct drm_i915_private *dev_priv = to_i915(dev);
12558         struct drm_crtc_state *crtc_state;
12559         struct drm_crtc *crtc;
12560         int i, ret;
12561
12562         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12563                 if (state->legacy_cursor_update)
12564                         continue;
12565
12566                 ret = intel_crtc_wait_for_pending_flips(crtc);
12567                 if (ret)
12568                         return ret;
12569
12570                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12571                         flush_workqueue(dev_priv->wq);
12572         }
12573
12574         ret = mutex_lock_interruptible(&dev->struct_mutex);
12575         if (ret)
12576                 return ret;
12577
12578         ret = drm_atomic_helper_prepare_planes(dev, state);
12579         mutex_unlock(&dev->struct_mutex);
12580
12581         return ret;
12582 }
12583
12584 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12585 {
12586         struct drm_device *dev = crtc->base.dev;
12587
12588         if (!dev->max_vblank_count)
12589                 return drm_accurate_vblank_count(&crtc->base);
12590
12591         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12592 }
12593
12594 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12595                                           struct drm_i915_private *dev_priv,
12596                                           unsigned crtc_mask)
12597 {
12598         unsigned last_vblank_count[I915_MAX_PIPES];
12599         enum pipe pipe;
12600         int ret;
12601
12602         if (!crtc_mask)
12603                 return;
12604
12605         for_each_pipe(dev_priv, pipe) {
12606                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12607                                                                   pipe);
12608
12609                 if (!((1 << pipe) & crtc_mask))
12610                         continue;
12611
12612                 ret = drm_crtc_vblank_get(&crtc->base);
12613                 if (WARN_ON(ret != 0)) {
12614                         crtc_mask &= ~(1 << pipe);
12615                         continue;
12616                 }
12617
12618                 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12619         }
12620
12621         for_each_pipe(dev_priv, pipe) {
12622                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12623                                                                   pipe);
12624                 long lret;
12625
12626                 if (!((1 << pipe) & crtc_mask))
12627                         continue;
12628
12629                 lret = wait_event_timeout(dev->vblank[pipe].queue,
12630                                 last_vblank_count[pipe] !=
12631                                         drm_crtc_vblank_count(&crtc->base),
12632                                 msecs_to_jiffies(50));
12633
12634                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12635
12636                 drm_crtc_vblank_put(&crtc->base);
12637         }
12638 }
12639
12640 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12641 {
12642         /* fb updated, need to unpin old fb */
12643         if (crtc_state->fb_changed)
12644                 return true;
12645
12646         /* wm changes, need vblank before final wm's */
12647         if (crtc_state->update_wm_post)
12648                 return true;
12649
12650         if (crtc_state->wm.need_postvbl_update)
12651                 return true;
12652
12653         return false;
12654 }
12655
12656 static void intel_update_crtc(struct drm_crtc *crtc,
12657                               struct drm_atomic_state *state,
12658                               struct drm_crtc_state *old_crtc_state,
12659                               struct drm_crtc_state *new_crtc_state,
12660                               unsigned int *crtc_vblank_mask)
12661 {
12662         struct drm_device *dev = crtc->dev;
12663         struct drm_i915_private *dev_priv = to_i915(dev);
12664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12665         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12666         bool modeset = needs_modeset(new_crtc_state);
12667
12668         if (modeset) {
12669                 update_scanline_offset(intel_crtc);
12670                 dev_priv->display.crtc_enable(pipe_config, state);
12671         } else {
12672                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12673                                        pipe_config);
12674         }
12675
12676         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12677                 intel_fbc_enable(
12678                     intel_crtc, pipe_config,
12679                     to_intel_plane_state(crtc->primary->state));
12680         }
12681
12682         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12683
12684         if (needs_vblank_wait(pipe_config))
12685                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12686 }
12687
12688 static void intel_update_crtcs(struct drm_atomic_state *state,
12689                                unsigned int *crtc_vblank_mask)
12690 {
12691         struct drm_crtc *crtc;
12692         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12693         int i;
12694
12695         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12696                 if (!new_crtc_state->active)
12697                         continue;
12698
12699                 intel_update_crtc(crtc, state, old_crtc_state,
12700                                   new_crtc_state, crtc_vblank_mask);
12701         }
12702 }
12703
12704 static void skl_update_crtcs(struct drm_atomic_state *state,
12705                              unsigned int *crtc_vblank_mask)
12706 {
12707         struct drm_i915_private *dev_priv = to_i915(state->dev);
12708         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12709         struct drm_crtc *crtc;
12710         struct intel_crtc *intel_crtc;
12711         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12712         struct intel_crtc_state *cstate;
12713         unsigned int updated = 0;
12714         bool progress;
12715         enum pipe pipe;
12716         int i;
12717
12718         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12719
12720         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12721                 /* ignore allocations for crtc's that have been turned off. */
12722                 if (new_crtc_state->active)
12723                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12724
12725         /*
12726          * Whenever the number of active pipes changes, we need to make sure we
12727          * update the pipes in the right order so that their ddb allocations
12728          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12729          * cause pipe underruns and other bad stuff.
12730          */
12731         do {
12732                 progress = false;
12733
12734                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12735                         bool vbl_wait = false;
12736                         unsigned int cmask = drm_crtc_mask(crtc);
12737
12738                         intel_crtc = to_intel_crtc(crtc);
12739                         cstate = to_intel_crtc_state(crtc->state);
12740                         pipe = intel_crtc->pipe;
12741
12742                         if (updated & cmask || !cstate->base.active)
12743                                 continue;
12744
12745                         if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12746                                 continue;
12747
12748                         updated |= cmask;
12749                         entries[i] = &cstate->wm.skl.ddb;
12750
12751                         /*
12752                          * If this is an already active pipe, it's DDB changed,
12753                          * and this isn't the last pipe that needs updating
12754                          * then we need to wait for a vblank to pass for the
12755                          * new ddb allocation to take effect.
12756                          */
12757                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12758                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12759                             !new_crtc_state->active_changed &&
12760                             intel_state->wm_results.dirty_pipes != updated)
12761                                 vbl_wait = true;
12762
12763                         intel_update_crtc(crtc, state, old_crtc_state,
12764                                           new_crtc_state, crtc_vblank_mask);
12765
12766                         if (vbl_wait)
12767                                 intel_wait_for_vblank(dev_priv, pipe);
12768
12769                         progress = true;
12770                 }
12771         } while (progress);
12772 }
12773
12774 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12775 {
12776         struct intel_atomic_state *state, *next;
12777         struct llist_node *freed;
12778
12779         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12780         llist_for_each_entry_safe(state, next, freed, freed)
12781                 drm_atomic_state_put(&state->base);
12782 }
12783
12784 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12785 {
12786         struct drm_i915_private *dev_priv =
12787                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12788
12789         intel_atomic_helper_free_state(dev_priv);
12790 }
12791
12792 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12793 {
12794         struct drm_device *dev = state->dev;
12795         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12796         struct drm_i915_private *dev_priv = to_i915(dev);
12797         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12798         struct drm_crtc *crtc;
12799         struct intel_crtc_state *intel_cstate;
12800         bool hw_check = intel_state->modeset;
12801         u64 put_domains[I915_MAX_PIPES] = {};
12802         unsigned crtc_vblank_mask = 0;
12803         int i;
12804
12805         drm_atomic_helper_wait_for_dependencies(state);
12806
12807         if (intel_state->modeset)
12808                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12809
12810         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12811                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12812
12813                 if (needs_modeset(new_crtc_state) ||
12814                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
12815                         hw_check = true;
12816
12817                         put_domains[to_intel_crtc(crtc)->pipe] =
12818                                 modeset_get_crtc_power_domains(crtc,
12819                                         to_intel_crtc_state(new_crtc_state));
12820                 }
12821
12822                 if (!needs_modeset(new_crtc_state))
12823                         continue;
12824
12825                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12826                                        to_intel_crtc_state(new_crtc_state));
12827
12828                 if (old_crtc_state->active) {
12829                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12830                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12831                         intel_crtc->active = false;
12832                         intel_fbc_disable(intel_crtc);
12833                         intel_disable_shared_dpll(intel_crtc);
12834
12835                         /*
12836                          * Underruns don't always raise
12837                          * interrupts, so check manually.
12838                          */
12839                         intel_check_cpu_fifo_underruns(dev_priv);
12840                         intel_check_pch_fifo_underruns(dev_priv);
12841
12842                         if (!crtc->state->active) {
12843                                 /*
12844                                  * Make sure we don't call initial_watermarks
12845                                  * for ILK-style watermark updates.
12846                                  *
12847                                  * No clue what this is supposed to achieve.
12848                                  */
12849                                 if (INTEL_GEN(dev_priv) >= 9)
12850                                         dev_priv->display.initial_watermarks(intel_state,
12851                                                                              to_intel_crtc_state(crtc->state));
12852                         }
12853                 }
12854         }
12855
12856         /* Only after disabling all output pipelines that will be changed can we
12857          * update the the output configuration. */
12858         intel_modeset_update_crtc_state(state);
12859
12860         if (intel_state->modeset) {
12861                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12862
12863                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12864
12865                 /*
12866                  * SKL workaround: bspec recommends we disable the SAGV when we
12867                  * have more then one pipe enabled
12868                  */
12869                 if (!intel_can_enable_sagv(state))
12870                         intel_disable_sagv(dev_priv);
12871
12872                 intel_modeset_verify_disabled(dev, state);
12873         }
12874
12875         /* Complete the events for pipes that have now been disabled */
12876         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12877                 bool modeset = needs_modeset(new_crtc_state);
12878
12879                 /* Complete events for now disable pipes here. */
12880                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12881                         spin_lock_irq(&dev->event_lock);
12882                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12883                         spin_unlock_irq(&dev->event_lock);
12884
12885                         new_crtc_state->event = NULL;
12886                 }
12887         }
12888
12889         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12890         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12891
12892         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12893          * already, but still need the state for the delayed optimization. To
12894          * fix this:
12895          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12896          * - schedule that vblank worker _before_ calling hw_done
12897          * - at the start of commit_tail, cancel it _synchrously
12898          * - switch over to the vblank wait helper in the core after that since
12899          *   we don't need out special handling any more.
12900          */
12901         if (!state->legacy_cursor_update)
12902                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12903
12904         /*
12905          * Now that the vblank has passed, we can go ahead and program the
12906          * optimal watermarks on platforms that need two-step watermark
12907          * programming.
12908          *
12909          * TODO: Move this (and other cleanup) to an async worker eventually.
12910          */
12911         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12912                 intel_cstate = to_intel_crtc_state(new_crtc_state);
12913
12914                 if (dev_priv->display.optimize_watermarks)
12915                         dev_priv->display.optimize_watermarks(intel_state,
12916                                                               intel_cstate);
12917         }
12918
12919         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12920                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12921
12922                 if (put_domains[i])
12923                         modeset_put_power_domains(dev_priv, put_domains[i]);
12924
12925                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12926         }
12927
12928         if (intel_state->modeset && intel_can_enable_sagv(state))
12929                 intel_enable_sagv(dev_priv);
12930
12931         drm_atomic_helper_commit_hw_done(state);
12932
12933         if (intel_state->modeset)
12934                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12935
12936         mutex_lock(&dev->struct_mutex);
12937         drm_atomic_helper_cleanup_planes(dev, state);
12938         mutex_unlock(&dev->struct_mutex);
12939
12940         drm_atomic_helper_commit_cleanup_done(state);
12941
12942         drm_atomic_state_put(state);
12943
12944         /* As one of the primary mmio accessors, KMS has a high likelihood
12945          * of triggering bugs in unclaimed access. After we finish
12946          * modesetting, see if an error has been flagged, and if so
12947          * enable debugging for the next modeset - and hope we catch
12948          * the culprit.
12949          *
12950          * XXX note that we assume display power is on at this point.
12951          * This might hold true now but we need to add pm helper to check
12952          * unclaimed only when the hardware is on, as atomic commits
12953          * can happen also when the device is completely off.
12954          */
12955         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12956
12957         intel_atomic_helper_free_state(dev_priv);
12958 }
12959
12960 static void intel_atomic_commit_work(struct work_struct *work)
12961 {
12962         struct drm_atomic_state *state =
12963                 container_of(work, struct drm_atomic_state, commit_work);
12964
12965         intel_atomic_commit_tail(state);
12966 }
12967
12968 static int __i915_sw_fence_call
12969 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12970                           enum i915_sw_fence_notify notify)
12971 {
12972         struct intel_atomic_state *state =
12973                 container_of(fence, struct intel_atomic_state, commit_ready);
12974
12975         switch (notify) {
12976         case FENCE_COMPLETE:
12977                 if (state->base.commit_work.func)
12978                         queue_work(system_unbound_wq, &state->base.commit_work);
12979                 break;
12980
12981         case FENCE_FREE:
12982                 {
12983                         struct intel_atomic_helper *helper =
12984                                 &to_i915(state->base.dev)->atomic_helper;
12985
12986                         if (llist_add(&state->freed, &helper->free_list))
12987                                 schedule_work(&helper->free_work);
12988                         break;
12989                 }
12990         }
12991
12992         return NOTIFY_DONE;
12993 }
12994
12995 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12996 {
12997         struct drm_plane_state *old_plane_state, *new_plane_state;
12998         struct drm_plane *plane;
12999         int i;
13000
13001         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
13002                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13003                                   intel_fb_obj(new_plane_state->fb),
13004                                   to_intel_plane(plane)->frontbuffer_bit);
13005 }
13006
13007 /**
13008  * intel_atomic_commit - commit validated state object
13009  * @dev: DRM device
13010  * @state: the top-level driver state object
13011  * @nonblock: nonblocking commit
13012  *
13013  * This function commits a top-level state object that has been validated
13014  * with drm_atomic_helper_check().
13015  *
13016  * RETURNS
13017  * Zero for success or -errno.
13018  */
13019 static int intel_atomic_commit(struct drm_device *dev,
13020                                struct drm_atomic_state *state,
13021                                bool nonblock)
13022 {
13023         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13024         struct drm_i915_private *dev_priv = to_i915(dev);
13025         int ret = 0;
13026
13027         ret = drm_atomic_helper_setup_commit(state, nonblock);
13028         if (ret)
13029                 return ret;
13030
13031         drm_atomic_state_get(state);
13032         i915_sw_fence_init(&intel_state->commit_ready,
13033                            intel_atomic_commit_ready);
13034
13035         ret = intel_atomic_prepare_commit(dev, state);
13036         if (ret) {
13037                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13038                 i915_sw_fence_commit(&intel_state->commit_ready);
13039                 return ret;
13040         }
13041
13042         /*
13043          * The intel_legacy_cursor_update() fast path takes care
13044          * of avoiding the vblank waits for simple cursor
13045          * movement and flips. For cursor on/off and size changes,
13046          * we want to perform the vblank waits so that watermark
13047          * updates happen during the correct frames. Gen9+ have
13048          * double buffered watermarks and so shouldn't need this.
13049          *
13050          * Do this after drm_atomic_helper_setup_commit() and
13051          * intel_atomic_prepare_commit() because we still want
13052          * to skip the flip and fb cleanup waits. Although that
13053          * does risk yanking the mapping from under the display
13054          * engine.
13055          *
13056          * FIXME doing watermarks and fb cleanup from a vblank worker
13057          * (assuming we had any) would solve these problems.
13058          */
13059         if (INTEL_GEN(dev_priv) < 9)
13060                 state->legacy_cursor_update = false;
13061
13062         drm_atomic_helper_swap_state(state, true);
13063         dev_priv->wm.distrust_bios_wm = false;
13064         intel_shared_dpll_swap_state(state);
13065         intel_atomic_track_fbs(state);
13066
13067         if (intel_state->modeset) {
13068                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13069                        sizeof(intel_state->min_pixclk));
13070                 dev_priv->active_crtcs = intel_state->active_crtcs;
13071                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13072                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13073         }
13074
13075         drm_atomic_state_get(state);
13076         INIT_WORK(&state->commit_work,
13077                   nonblock ? intel_atomic_commit_work : NULL);
13078
13079         i915_sw_fence_commit(&intel_state->commit_ready);
13080         if (!nonblock) {
13081                 i915_sw_fence_wait(&intel_state->commit_ready);
13082                 intel_atomic_commit_tail(state);
13083         }
13084
13085         return 0;
13086 }
13087
13088 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13089 {
13090         struct drm_device *dev = crtc->dev;
13091         struct drm_atomic_state *state;
13092         struct drm_crtc_state *crtc_state;
13093         int ret;
13094
13095         state = drm_atomic_state_alloc(dev);
13096         if (!state) {
13097                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13098                               crtc->base.id, crtc->name);
13099                 return;
13100         }
13101
13102         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
13103
13104 retry:
13105         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13106         ret = PTR_ERR_OR_ZERO(crtc_state);
13107         if (!ret) {
13108                 if (!crtc_state->active)
13109                         goto out;
13110
13111                 crtc_state->mode_changed = true;
13112                 ret = drm_atomic_commit(state);
13113         }
13114
13115         if (ret == -EDEADLK) {
13116                 drm_atomic_state_clear(state);
13117                 drm_modeset_backoff(state->acquire_ctx);
13118                 goto retry;
13119         }
13120
13121 out:
13122         drm_atomic_state_put(state);
13123 }
13124
13125 static const struct drm_crtc_funcs intel_crtc_funcs = {
13126         .gamma_set = drm_atomic_helper_legacy_gamma_set,
13127         .set_config = drm_atomic_helper_set_config,
13128         .set_property = drm_atomic_helper_crtc_set_property,
13129         .destroy = intel_crtc_destroy,
13130         .page_flip = drm_atomic_helper_page_flip,
13131         .atomic_duplicate_state = intel_crtc_duplicate_state,
13132         .atomic_destroy_state = intel_crtc_destroy_state,
13133         .set_crc_source = intel_crtc_set_crc_source,
13134 };
13135
13136 /**
13137  * intel_prepare_plane_fb - Prepare fb for usage on plane
13138  * @plane: drm plane to prepare for
13139  * @fb: framebuffer to prepare for presentation
13140  *
13141  * Prepares a framebuffer for usage on a display plane.  Generally this
13142  * involves pinning the underlying object and updating the frontbuffer tracking
13143  * bits.  Some older platforms need special physical address handling for
13144  * cursor planes.
13145  *
13146  * Must be called with struct_mutex held.
13147  *
13148  * Returns 0 on success, negative error code on failure.
13149  */
13150 int
13151 intel_prepare_plane_fb(struct drm_plane *plane,
13152                        struct drm_plane_state *new_state)
13153 {
13154         struct intel_atomic_state *intel_state =
13155                 to_intel_atomic_state(new_state->state);
13156         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13157         struct drm_framebuffer *fb = new_state->fb;
13158         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13159         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13160         int ret;
13161
13162         if (obj) {
13163                 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13164                     INTEL_INFO(dev_priv)->cursor_needs_physical) {
13165                         const int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13166
13167                         ret = i915_gem_object_attach_phys(obj, align);
13168                         if (ret) {
13169                                 DRM_DEBUG_KMS("failed to attach phys object\n");
13170                                 return ret;
13171                         }
13172                 } else {
13173                         struct i915_vma *vma;
13174
13175                         vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13176                         if (IS_ERR(vma)) {
13177                                 DRM_DEBUG_KMS("failed to pin object\n");
13178                                 return PTR_ERR(vma);
13179                         }
13180
13181                         to_intel_plane_state(new_state)->vma = vma;
13182                 }
13183         }
13184
13185         if (!obj && !old_obj)
13186                 return 0;
13187
13188         if (old_obj) {
13189                 struct drm_crtc_state *crtc_state =
13190                         drm_atomic_get_existing_crtc_state(new_state->state,
13191                                                            plane->state->crtc);
13192
13193                 /* Big Hammer, we also need to ensure that any pending
13194                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13195                  * current scanout is retired before unpinning the old
13196                  * framebuffer. Note that we rely on userspace rendering
13197                  * into the buffer attached to the pipe they are waiting
13198                  * on. If not, userspace generates a GPU hang with IPEHR
13199                  * point to the MI_WAIT_FOR_EVENT.
13200                  *
13201                  * This should only fail upon a hung GPU, in which case we
13202                  * can safely continue.
13203                  */
13204                 if (needs_modeset(crtc_state)) {
13205                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13206                                                               old_obj->resv, NULL,
13207                                                               false, 0,
13208                                                               GFP_KERNEL);
13209                         if (ret < 0)
13210                                 return ret;
13211                 }
13212         }
13213
13214         if (new_state->fence) { /* explicit fencing */
13215                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13216                                                     new_state->fence,
13217                                                     I915_FENCE_TIMEOUT,
13218                                                     GFP_KERNEL);
13219                 if (ret < 0)
13220                         return ret;
13221         }
13222
13223         if (!obj)
13224                 return 0;
13225
13226         if (!new_state->fence) { /* implicit fencing */
13227                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13228                                                       obj->resv, NULL,
13229                                                       false, I915_FENCE_TIMEOUT,
13230                                                       GFP_KERNEL);
13231                 if (ret < 0)
13232                         return ret;
13233
13234                 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13235         }
13236
13237         return 0;
13238 }
13239
13240 /**
13241  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13242  * @plane: drm plane to clean up for
13243  * @fb: old framebuffer that was on plane
13244  *
13245  * Cleans up a framebuffer that has just been removed from a plane.
13246  *
13247  * Must be called with struct_mutex held.
13248  */
13249 void
13250 intel_cleanup_plane_fb(struct drm_plane *plane,
13251                        struct drm_plane_state *old_state)
13252 {
13253         struct i915_vma *vma;
13254
13255         /* Should only be called after a successful intel_prepare_plane_fb()! */
13256         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13257         if (vma)
13258                 intel_unpin_fb_vma(vma);
13259 }
13260
13261 int
13262 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13263 {
13264         struct drm_i915_private *dev_priv;
13265         int max_scale;
13266         int crtc_clock, max_dotclk;
13267
13268         if (!intel_crtc || !crtc_state->base.enable)
13269                 return DRM_PLANE_HELPER_NO_SCALING;
13270
13271         dev_priv = to_i915(intel_crtc->base.dev);
13272
13273         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13274         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13275
13276         if (IS_GEMINILAKE(dev_priv))
13277                 max_dotclk *= 2;
13278
13279         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13280                 return DRM_PLANE_HELPER_NO_SCALING;
13281
13282         /*
13283          * skl max scale is lower of:
13284          *    close to 3 but not 3, -1 is for that purpose
13285          *            or
13286          *    cdclk/crtc_clock
13287          */
13288         max_scale = min((1 << 16) * 3 - 1,
13289                         (1 << 8) * ((max_dotclk << 8) / crtc_clock));
13290
13291         return max_scale;
13292 }
13293
13294 static int
13295 intel_check_primary_plane(struct drm_plane *plane,
13296                           struct intel_crtc_state *crtc_state,
13297                           struct intel_plane_state *state)
13298 {
13299         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13300         struct drm_crtc *crtc = state->base.crtc;
13301         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13302         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13303         bool can_position = false;
13304         int ret;
13305
13306         if (INTEL_GEN(dev_priv) >= 9) {
13307                 /* use scaler when colorkey is not required */
13308                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13309                         min_scale = 1;
13310                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13311                 }
13312                 can_position = true;
13313         }
13314
13315         ret = drm_plane_helper_check_state(&state->base,
13316                                            &state->clip,
13317                                            min_scale, max_scale,
13318                                            can_position, true);
13319         if (ret)
13320                 return ret;
13321
13322         if (!state->base.fb)
13323                 return 0;
13324
13325         if (INTEL_GEN(dev_priv) >= 9) {
13326                 ret = skl_check_plane_surface(state);
13327                 if (ret)
13328                         return ret;
13329
13330                 state->ctl = skl_plane_ctl(crtc_state, state);
13331         } else {
13332                 ret = i9xx_check_plane_surface(state);
13333                 if (ret)
13334                         return ret;
13335
13336                 state->ctl = i9xx_plane_ctl(crtc_state, state);
13337         }
13338
13339         return 0;
13340 }
13341
13342 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13343                                     struct drm_crtc_state *old_crtc_state)
13344 {
13345         struct drm_device *dev = crtc->dev;
13346         struct drm_i915_private *dev_priv = to_i915(dev);
13347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13348         struct intel_crtc_state *intel_cstate =
13349                 to_intel_crtc_state(crtc->state);
13350         struct intel_crtc_state *old_intel_cstate =
13351                 to_intel_crtc_state(old_crtc_state);
13352         struct intel_atomic_state *old_intel_state =
13353                 to_intel_atomic_state(old_crtc_state->state);
13354         bool modeset = needs_modeset(crtc->state);
13355
13356         if (!modeset &&
13357             (intel_cstate->base.color_mgmt_changed ||
13358              intel_cstate->update_pipe)) {
13359                 intel_color_set_csc(crtc->state);
13360                 intel_color_load_luts(crtc->state);
13361         }
13362
13363         /* Perform vblank evasion around commit operation */
13364         intel_pipe_update_start(intel_crtc);
13365
13366         if (modeset)
13367                 goto out;
13368
13369         if (intel_cstate->update_pipe)
13370                 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13371         else if (INTEL_GEN(dev_priv) >= 9)
13372                 skl_detach_scalers(intel_crtc);
13373
13374 out:
13375         if (dev_priv->display.atomic_update_watermarks)
13376                 dev_priv->display.atomic_update_watermarks(old_intel_state,
13377                                                            intel_cstate);
13378 }
13379
13380 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13381                                      struct drm_crtc_state *old_crtc_state)
13382 {
13383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13384
13385         intel_pipe_update_end(intel_crtc, NULL);
13386 }
13387
13388 /**
13389  * intel_plane_destroy - destroy a plane
13390  * @plane: plane to destroy
13391  *
13392  * Common destruction function for all types of planes (primary, cursor,
13393  * sprite).
13394  */
13395 void intel_plane_destroy(struct drm_plane *plane)
13396 {
13397         drm_plane_cleanup(plane);
13398         kfree(to_intel_plane(plane));
13399 }
13400
13401 const struct drm_plane_funcs intel_plane_funcs = {
13402         .update_plane = drm_atomic_helper_update_plane,
13403         .disable_plane = drm_atomic_helper_disable_plane,
13404         .destroy = intel_plane_destroy,
13405         .set_property = drm_atomic_helper_plane_set_property,
13406         .atomic_get_property = intel_plane_atomic_get_property,
13407         .atomic_set_property = intel_plane_atomic_set_property,
13408         .atomic_duplicate_state = intel_plane_duplicate_state,
13409         .atomic_destroy_state = intel_plane_destroy_state,
13410 };
13411
13412 static int
13413 intel_legacy_cursor_update(struct drm_plane *plane,
13414                            struct drm_crtc *crtc,
13415                            struct drm_framebuffer *fb,
13416                            int crtc_x, int crtc_y,
13417                            unsigned int crtc_w, unsigned int crtc_h,
13418                            uint32_t src_x, uint32_t src_y,
13419                            uint32_t src_w, uint32_t src_h,
13420                            struct drm_modeset_acquire_ctx *ctx)
13421 {
13422         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13423         int ret;
13424         struct drm_plane_state *old_plane_state, *new_plane_state;
13425         struct intel_plane *intel_plane = to_intel_plane(plane);
13426         struct drm_framebuffer *old_fb;
13427         struct drm_crtc_state *crtc_state = crtc->state;
13428         struct i915_vma *old_vma;
13429
13430         /*
13431          * When crtc is inactive or there is a modeset pending,
13432          * wait for it to complete in the slowpath
13433          */
13434         if (!crtc_state->active || needs_modeset(crtc_state) ||
13435             to_intel_crtc_state(crtc_state)->update_pipe)
13436                 goto slow;
13437
13438         old_plane_state = plane->state;
13439
13440         /*
13441          * If any parameters change that may affect watermarks,
13442          * take the slowpath. Only changing fb or position should be
13443          * in the fastpath.
13444          */
13445         if (old_plane_state->crtc != crtc ||
13446             old_plane_state->src_w != src_w ||
13447             old_plane_state->src_h != src_h ||
13448             old_plane_state->crtc_w != crtc_w ||
13449             old_plane_state->crtc_h != crtc_h ||
13450             !old_plane_state->fb != !fb)
13451                 goto slow;
13452
13453         new_plane_state = intel_plane_duplicate_state(plane);
13454         if (!new_plane_state)
13455                 return -ENOMEM;
13456
13457         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13458
13459         new_plane_state->src_x = src_x;
13460         new_plane_state->src_y = src_y;
13461         new_plane_state->src_w = src_w;
13462         new_plane_state->src_h = src_h;
13463         new_plane_state->crtc_x = crtc_x;
13464         new_plane_state->crtc_y = crtc_y;
13465         new_plane_state->crtc_w = crtc_w;
13466         new_plane_state->crtc_h = crtc_h;
13467
13468         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13469                                                   to_intel_plane_state(new_plane_state));
13470         if (ret)
13471                 goto out_free;
13472
13473         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13474         if (ret)
13475                 goto out_free;
13476
13477         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13478                 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13479
13480                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13481                 if (ret) {
13482                         DRM_DEBUG_KMS("failed to attach phys object\n");
13483                         goto out_unlock;
13484                 }
13485         } else {
13486                 struct i915_vma *vma;
13487
13488                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13489                 if (IS_ERR(vma)) {
13490                         DRM_DEBUG_KMS("failed to pin object\n");
13491
13492                         ret = PTR_ERR(vma);
13493                         goto out_unlock;
13494                 }
13495
13496                 to_intel_plane_state(new_plane_state)->vma = vma;
13497         }
13498
13499         old_fb = old_plane_state->fb;
13500         old_vma = to_intel_plane_state(old_plane_state)->vma;
13501
13502         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13503                           intel_plane->frontbuffer_bit);
13504
13505         /* Swap plane state */
13506         new_plane_state->fence = old_plane_state->fence;
13507         *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13508         new_plane_state->fence = NULL;
13509         new_plane_state->fb = old_fb;
13510         to_intel_plane_state(new_plane_state)->vma = old_vma;
13511
13512         if (plane->state->visible) {
13513                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13514                 intel_plane->update_plane(plane,
13515                                           to_intel_crtc_state(crtc->state),
13516                                           to_intel_plane_state(plane->state));
13517         } else {
13518                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13519                 intel_plane->disable_plane(plane, crtc);
13520         }
13521
13522         intel_cleanup_plane_fb(plane, new_plane_state);
13523
13524 out_unlock:
13525         mutex_unlock(&dev_priv->drm.struct_mutex);
13526 out_free:
13527         intel_plane_destroy_state(plane, new_plane_state);
13528         return ret;
13529
13530 slow:
13531         return drm_atomic_helper_update_plane(plane, crtc, fb,
13532                                               crtc_x, crtc_y, crtc_w, crtc_h,
13533                                               src_x, src_y, src_w, src_h, ctx);
13534 }
13535
13536 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13537         .update_plane = intel_legacy_cursor_update,
13538         .disable_plane = drm_atomic_helper_disable_plane,
13539         .destroy = intel_plane_destroy,
13540         .set_property = drm_atomic_helper_plane_set_property,
13541         .atomic_get_property = intel_plane_atomic_get_property,
13542         .atomic_set_property = intel_plane_atomic_set_property,
13543         .atomic_duplicate_state = intel_plane_duplicate_state,
13544         .atomic_destroy_state = intel_plane_destroy_state,
13545 };
13546
13547 static struct intel_plane *
13548 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13549 {
13550         struct intel_plane *primary = NULL;
13551         struct intel_plane_state *state = NULL;
13552         const uint32_t *intel_primary_formats;
13553         unsigned int supported_rotations;
13554         unsigned int num_formats;
13555         int ret;
13556
13557         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13558         if (!primary) {
13559                 ret = -ENOMEM;
13560                 goto fail;
13561         }
13562
13563         state = intel_create_plane_state(&primary->base);
13564         if (!state) {
13565                 ret = -ENOMEM;
13566                 goto fail;
13567         }
13568
13569         primary->base.state = &state->base;
13570
13571         primary->can_scale = false;
13572         primary->max_downscale = 1;
13573         if (INTEL_GEN(dev_priv) >= 9) {
13574                 primary->can_scale = true;
13575                 state->scaler_id = -1;
13576         }
13577         primary->pipe = pipe;
13578         /*
13579          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13580          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13581          */
13582         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13583                 primary->plane = (enum plane) !pipe;
13584         else
13585                 primary->plane = (enum plane) pipe;
13586         primary->id = PLANE_PRIMARY;
13587         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13588         primary->check_plane = intel_check_primary_plane;
13589
13590         if (INTEL_GEN(dev_priv) >= 9) {
13591                 intel_primary_formats = skl_primary_formats;
13592                 num_formats = ARRAY_SIZE(skl_primary_formats);
13593
13594                 primary->update_plane = skylake_update_primary_plane;
13595                 primary->disable_plane = skylake_disable_primary_plane;
13596         } else if (INTEL_GEN(dev_priv) >= 4) {
13597                 intel_primary_formats = i965_primary_formats;
13598                 num_formats = ARRAY_SIZE(i965_primary_formats);
13599
13600                 primary->update_plane = i9xx_update_primary_plane;
13601                 primary->disable_plane = i9xx_disable_primary_plane;
13602         } else {
13603                 intel_primary_formats = i8xx_primary_formats;
13604                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13605
13606                 primary->update_plane = i9xx_update_primary_plane;
13607                 primary->disable_plane = i9xx_disable_primary_plane;
13608         }
13609
13610         if (INTEL_GEN(dev_priv) >= 9)
13611                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13612                                                0, &intel_plane_funcs,
13613                                                intel_primary_formats, num_formats,
13614                                                DRM_PLANE_TYPE_PRIMARY,
13615                                                "plane 1%c", pipe_name(pipe));
13616         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13617                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13618                                                0, &intel_plane_funcs,
13619                                                intel_primary_formats, num_formats,
13620                                                DRM_PLANE_TYPE_PRIMARY,
13621                                                "primary %c", pipe_name(pipe));
13622         else
13623                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13624                                                0, &intel_plane_funcs,
13625                                                intel_primary_formats, num_formats,
13626                                                DRM_PLANE_TYPE_PRIMARY,
13627                                                "plane %c", plane_name(primary->plane));
13628         if (ret)
13629                 goto fail;
13630
13631         if (INTEL_GEN(dev_priv) >= 9) {
13632                 supported_rotations =
13633                         DRM_ROTATE_0 | DRM_ROTATE_90 |
13634                         DRM_ROTATE_180 | DRM_ROTATE_270;
13635         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13636                 supported_rotations =
13637                         DRM_ROTATE_0 | DRM_ROTATE_180 |
13638                         DRM_REFLECT_X;
13639         } else if (INTEL_GEN(dev_priv) >= 4) {
13640                 supported_rotations =
13641                         DRM_ROTATE_0 | DRM_ROTATE_180;
13642         } else {
13643                 supported_rotations = DRM_ROTATE_0;
13644         }
13645
13646         if (INTEL_GEN(dev_priv) >= 4)
13647                 drm_plane_create_rotation_property(&primary->base,
13648                                                    DRM_ROTATE_0,
13649                                                    supported_rotations);
13650
13651         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13652
13653         return primary;
13654
13655 fail:
13656         kfree(state);
13657         kfree(primary);
13658
13659         return ERR_PTR(ret);
13660 }
13661
13662 static int
13663 intel_check_cursor_plane(struct drm_plane *plane,
13664                          struct intel_crtc_state *crtc_state,
13665                          struct intel_plane_state *state)
13666 {
13667         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13668         struct drm_framebuffer *fb = state->base.fb;
13669         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13670         enum pipe pipe = to_intel_plane(plane)->pipe;
13671         unsigned stride;
13672         int ret;
13673
13674         ret = drm_plane_helper_check_state(&state->base,
13675                                            &state->clip,
13676                                            DRM_PLANE_HELPER_NO_SCALING,
13677                                            DRM_PLANE_HELPER_NO_SCALING,
13678                                            true, true);
13679         if (ret)
13680                 return ret;
13681
13682         /* if we want to turn off the cursor ignore width and height */
13683         if (!obj)
13684                 return 0;
13685
13686         /* Check for which cursor types we support */
13687         if (!cursor_size_ok(dev_priv, state->base.crtc_w,
13688                             state->base.crtc_h)) {
13689                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13690                           state->base.crtc_w, state->base.crtc_h);
13691                 return -EINVAL;
13692         }
13693
13694         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13695         if (obj->base.size < stride * state->base.crtc_h) {
13696                 DRM_DEBUG_KMS("buffer is too small\n");
13697                 return -ENOMEM;
13698         }
13699
13700         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
13701                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13702                 return -EINVAL;
13703         }
13704
13705         /*
13706          * There's something wrong with the cursor on CHV pipe C.
13707          * If it straddles the left edge of the screen then
13708          * moving it away from the edge or disabling it often
13709          * results in a pipe underrun, and often that can lead to
13710          * dead pipe (constant underrun reported, and it scans
13711          * out just a solid color). To recover from that, the
13712          * display power well must be turned off and on again.
13713          * Refuse the put the cursor into that compromised position.
13714          */
13715         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
13716             state->base.visible && state->base.crtc_x < 0) {
13717                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13718                 return -EINVAL;
13719         }
13720
13721         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
13722                 state->ctl = i845_cursor_ctl(crtc_state, state);
13723         else
13724                 state->ctl = i9xx_cursor_ctl(crtc_state, state);
13725
13726         return 0;
13727 }
13728
13729 static void
13730 intel_disable_cursor_plane(struct drm_plane *plane,
13731                            struct drm_crtc *crtc)
13732 {
13733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13734
13735         intel_crtc->cursor_addr = 0;
13736         intel_crtc_update_cursor(crtc, NULL);
13737 }
13738
13739 static void
13740 intel_update_cursor_plane(struct drm_plane *plane,
13741                           const struct intel_crtc_state *crtc_state,
13742                           const struct intel_plane_state *state)
13743 {
13744         struct drm_crtc *crtc = crtc_state->base.crtc;
13745         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13746         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13747         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13748         uint32_t addr;
13749
13750         if (!obj)
13751                 addr = 0;
13752         else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
13753                 addr = intel_plane_ggtt_offset(state);
13754         else
13755                 addr = obj->phys_handle->busaddr;
13756
13757         intel_crtc->cursor_addr = addr;
13758         intel_crtc_update_cursor(crtc, state);
13759 }
13760
13761 static struct intel_plane *
13762 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13763 {
13764         struct intel_plane *cursor = NULL;
13765         struct intel_plane_state *state = NULL;
13766         int ret;
13767
13768         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13769         if (!cursor) {
13770                 ret = -ENOMEM;
13771                 goto fail;
13772         }
13773
13774         state = intel_create_plane_state(&cursor->base);
13775         if (!state) {
13776                 ret = -ENOMEM;
13777                 goto fail;
13778         }
13779
13780         cursor->base.state = &state->base;
13781
13782         cursor->can_scale = false;
13783         cursor->max_downscale = 1;
13784         cursor->pipe = pipe;
13785         cursor->plane = pipe;
13786         cursor->id = PLANE_CURSOR;
13787         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13788         cursor->check_plane = intel_check_cursor_plane;
13789         cursor->update_plane = intel_update_cursor_plane;
13790         cursor->disable_plane = intel_disable_cursor_plane;
13791
13792         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13793                                        0, &intel_cursor_plane_funcs,
13794                                        intel_cursor_formats,
13795                                        ARRAY_SIZE(intel_cursor_formats),
13796                                        DRM_PLANE_TYPE_CURSOR,
13797                                        "cursor %c", pipe_name(pipe));
13798         if (ret)
13799                 goto fail;
13800
13801         if (INTEL_GEN(dev_priv) >= 4)
13802                 drm_plane_create_rotation_property(&cursor->base,
13803                                                    DRM_ROTATE_0,
13804                                                    DRM_ROTATE_0 |
13805                                                    DRM_ROTATE_180);
13806
13807         if (INTEL_GEN(dev_priv) >= 9)
13808                 state->scaler_id = -1;
13809
13810         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13811
13812         return cursor;
13813
13814 fail:
13815         kfree(state);
13816         kfree(cursor);
13817
13818         return ERR_PTR(ret);
13819 }
13820
13821 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13822                                     struct intel_crtc_state *crtc_state)
13823 {
13824         struct intel_crtc_scaler_state *scaler_state =
13825                 &crtc_state->scaler_state;
13826         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13827         int i;
13828
13829         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13830         if (!crtc->num_scalers)
13831                 return;
13832
13833         for (i = 0; i < crtc->num_scalers; i++) {
13834                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13835
13836                 scaler->in_use = 0;
13837                 scaler->mode = PS_SCALER_MODE_DYN;
13838         }
13839
13840         scaler_state->scaler_id = -1;
13841 }
13842
13843 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13844 {
13845         struct intel_crtc *intel_crtc;
13846         struct intel_crtc_state *crtc_state = NULL;
13847         struct intel_plane *primary = NULL;
13848         struct intel_plane *cursor = NULL;
13849         int sprite, ret;
13850
13851         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13852         if (!intel_crtc)
13853                 return -ENOMEM;
13854
13855         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13856         if (!crtc_state) {
13857                 ret = -ENOMEM;
13858                 goto fail;
13859         }
13860         intel_crtc->config = crtc_state;
13861         intel_crtc->base.state = &crtc_state->base;
13862         crtc_state->base.crtc = &intel_crtc->base;
13863
13864         primary = intel_primary_plane_create(dev_priv, pipe);
13865         if (IS_ERR(primary)) {
13866                 ret = PTR_ERR(primary);
13867                 goto fail;
13868         }
13869         intel_crtc->plane_ids_mask |= BIT(primary->id);
13870
13871         for_each_sprite(dev_priv, pipe, sprite) {
13872                 struct intel_plane *plane;
13873
13874                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13875                 if (IS_ERR(plane)) {
13876                         ret = PTR_ERR(plane);
13877                         goto fail;
13878                 }
13879                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13880         }
13881
13882         cursor = intel_cursor_plane_create(dev_priv, pipe);
13883         if (IS_ERR(cursor)) {
13884                 ret = PTR_ERR(cursor);
13885                 goto fail;
13886         }
13887         intel_crtc->plane_ids_mask |= BIT(cursor->id);
13888
13889         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13890                                         &primary->base, &cursor->base,
13891                                         &intel_crtc_funcs,
13892                                         "pipe %c", pipe_name(pipe));
13893         if (ret)
13894                 goto fail;
13895
13896         intel_crtc->pipe = pipe;
13897         intel_crtc->plane = primary->plane;
13898
13899         intel_crtc->cursor_base = ~0;
13900         intel_crtc->cursor_cntl = ~0;
13901         intel_crtc->cursor_size = ~0;
13902
13903         /* initialize shared scalers */
13904         intel_crtc_init_scalers(intel_crtc, crtc_state);
13905
13906         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13907                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13908         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13909         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13910
13911         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13912
13913         intel_color_init(&intel_crtc->base);
13914
13915         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13916
13917         return 0;
13918
13919 fail:
13920         /*
13921          * drm_mode_config_cleanup() will free up any
13922          * crtcs/planes already initialized.
13923          */
13924         kfree(crtc_state);
13925         kfree(intel_crtc);
13926
13927         return ret;
13928 }
13929
13930 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13931 {
13932         struct drm_device *dev = connector->base.dev;
13933
13934         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13935
13936         if (!connector->base.state->crtc)
13937                 return INVALID_PIPE;
13938
13939         return to_intel_crtc(connector->base.state->crtc)->pipe;
13940 }
13941
13942 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13943                                 struct drm_file *file)
13944 {
13945         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13946         struct drm_crtc *drmmode_crtc;
13947         struct intel_crtc *crtc;
13948
13949         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13950         if (!drmmode_crtc)
13951                 return -ENOENT;
13952
13953         crtc = to_intel_crtc(drmmode_crtc);
13954         pipe_from_crtc_id->pipe = crtc->pipe;
13955
13956         return 0;
13957 }
13958
13959 static int intel_encoder_clones(struct intel_encoder *encoder)
13960 {
13961         struct drm_device *dev = encoder->base.dev;
13962         struct intel_encoder *source_encoder;
13963         int index_mask = 0;
13964         int entry = 0;
13965
13966         for_each_intel_encoder(dev, source_encoder) {
13967                 if (encoders_cloneable(encoder, source_encoder))
13968                         index_mask |= (1 << entry);
13969
13970                 entry++;
13971         }
13972
13973         return index_mask;
13974 }
13975
13976 static bool has_edp_a(struct drm_i915_private *dev_priv)
13977 {
13978         if (!IS_MOBILE(dev_priv))
13979                 return false;
13980
13981         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13982                 return false;
13983
13984         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13985                 return false;
13986
13987         return true;
13988 }
13989
13990 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13991 {
13992         if (INTEL_GEN(dev_priv) >= 9)
13993                 return false;
13994
13995         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13996                 return false;
13997
13998         if (IS_CHERRYVIEW(dev_priv))
13999                 return false;
14000
14001         if (HAS_PCH_LPT_H(dev_priv) &&
14002             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14003                 return false;
14004
14005         /* DDI E can't be used if DDI A requires 4 lanes */
14006         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14007                 return false;
14008
14009         if (!dev_priv->vbt.int_crt_support)
14010                 return false;
14011
14012         return true;
14013 }
14014
14015 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14016 {
14017         int pps_num;
14018         int pps_idx;
14019
14020         if (HAS_DDI(dev_priv))
14021                 return;
14022         /*
14023          * This w/a is needed at least on CPT/PPT, but to be sure apply it
14024          * everywhere where registers can be write protected.
14025          */
14026         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14027                 pps_num = 2;
14028         else
14029                 pps_num = 1;
14030
14031         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14032                 u32 val = I915_READ(PP_CONTROL(pps_idx));
14033
14034                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14035                 I915_WRITE(PP_CONTROL(pps_idx), val);
14036         }
14037 }
14038
14039 static void intel_pps_init(struct drm_i915_private *dev_priv)
14040 {
14041         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14042                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14043         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14044                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14045         else
14046                 dev_priv->pps_mmio_base = PPS_BASE;
14047
14048         intel_pps_unlock_regs_wa(dev_priv);
14049 }
14050
14051 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14052 {
14053         struct intel_encoder *encoder;
14054         bool dpd_is_edp = false;
14055
14056         intel_pps_init(dev_priv);
14057
14058         /*
14059          * intel_edp_init_connector() depends on this completing first, to
14060          * prevent the registeration of both eDP and LVDS and the incorrect
14061          * sharing of the PPS.
14062          */
14063         intel_lvds_init(dev_priv);
14064
14065         if (intel_crt_present(dev_priv))
14066                 intel_crt_init(dev_priv);
14067
14068         if (IS_GEN9_LP(dev_priv)) {
14069                 /*
14070                  * FIXME: Broxton doesn't support port detection via the
14071                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14072                  * detect the ports.
14073                  */
14074                 intel_ddi_init(dev_priv, PORT_A);
14075                 intel_ddi_init(dev_priv, PORT_B);
14076                 intel_ddi_init(dev_priv, PORT_C);
14077
14078                 intel_dsi_init(dev_priv);
14079         } else if (HAS_DDI(dev_priv)) {
14080                 int found;
14081
14082                 /*
14083                  * Haswell uses DDI functions to detect digital outputs.
14084                  * On SKL pre-D0 the strap isn't connected, so we assume
14085                  * it's there.
14086                  */
14087                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14088                 /* WaIgnoreDDIAStrap: skl */
14089                 if (found || IS_GEN9_BC(dev_priv))
14090                         intel_ddi_init(dev_priv, PORT_A);
14091
14092                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14093                  * register */
14094                 found = I915_READ(SFUSE_STRAP);
14095
14096                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14097                         intel_ddi_init(dev_priv, PORT_B);
14098                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14099                         intel_ddi_init(dev_priv, PORT_C);
14100                 if (found & SFUSE_STRAP_DDID_DETECTED)
14101                         intel_ddi_init(dev_priv, PORT_D);
14102                 /*
14103                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14104                  */
14105                 if (IS_GEN9_BC(dev_priv) &&
14106                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14107                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14108                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14109                         intel_ddi_init(dev_priv, PORT_E);
14110
14111         } else if (HAS_PCH_SPLIT(dev_priv)) {
14112                 int found;
14113                 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14114
14115                 if (has_edp_a(dev_priv))
14116                         intel_dp_init(dev_priv, DP_A, PORT_A);
14117
14118                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14119                         /* PCH SDVOB multiplex with HDMIB */
14120                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14121                         if (!found)
14122                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14123                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14124                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14125                 }
14126
14127                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14128                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14129
14130                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14131                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14132
14133                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14134                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14135
14136                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14137                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14138         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14139                 bool has_edp, has_port;
14140
14141                 /*
14142                  * The DP_DETECTED bit is the latched state of the DDC
14143                  * SDA pin at boot. However since eDP doesn't require DDC
14144                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14145                  * eDP ports may have been muxed to an alternate function.
14146                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14147                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14148                  * detect eDP ports.
14149                  *
14150                  * Sadly the straps seem to be missing sometimes even for HDMI
14151                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14152                  * and VBT for the presence of the port. Additionally we can't
14153                  * trust the port type the VBT declares as we've seen at least
14154                  * HDMI ports that the VBT claim are DP or eDP.
14155                  */
14156                 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14157                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14158                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14159                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14160                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14161                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14162
14163                 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14164                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14165                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14166                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14167                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14168                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14169
14170                 if (IS_CHERRYVIEW(dev_priv)) {
14171                         /*
14172                          * eDP not supported on port D,
14173                          * so no need to worry about it
14174                          */
14175                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14176                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14177                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14178                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14179                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14180                 }
14181
14182                 intel_dsi_init(dev_priv);
14183         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14184                 bool found = false;
14185
14186                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14187                         DRM_DEBUG_KMS("probing SDVOB\n");
14188                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14189                         if (!found && IS_G4X(dev_priv)) {
14190                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14191                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14192                         }
14193
14194                         if (!found && IS_G4X(dev_priv))
14195                                 intel_dp_init(dev_priv, DP_B, PORT_B);
14196                 }
14197
14198                 /* Before G4X SDVOC doesn't have its own detect register */
14199
14200                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14201                         DRM_DEBUG_KMS("probing SDVOC\n");
14202                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14203                 }
14204
14205                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14206
14207                         if (IS_G4X(dev_priv)) {
14208                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14209                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14210                         }
14211                         if (IS_G4X(dev_priv))
14212                                 intel_dp_init(dev_priv, DP_C, PORT_C);
14213                 }
14214
14215                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14216                         intel_dp_init(dev_priv, DP_D, PORT_D);
14217         } else if (IS_GEN2(dev_priv))
14218                 intel_dvo_init(dev_priv);
14219
14220         if (SUPPORTS_TV(dev_priv))
14221                 intel_tv_init(dev_priv);
14222
14223         intel_psr_init(dev_priv);
14224
14225         for_each_intel_encoder(&dev_priv->drm, encoder) {
14226                 encoder->base.possible_crtcs = encoder->crtc_mask;
14227                 encoder->base.possible_clones =
14228                         intel_encoder_clones(encoder);
14229         }
14230
14231         intel_init_pch_refclk(dev_priv);
14232
14233         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14234 }
14235
14236 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14237 {
14238         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14239
14240         drm_framebuffer_cleanup(fb);
14241
14242         i915_gem_object_lock(intel_fb->obj);
14243         WARN_ON(!intel_fb->obj->framebuffer_references--);
14244         i915_gem_object_unlock(intel_fb->obj);
14245
14246         i915_gem_object_put(intel_fb->obj);
14247
14248         kfree(intel_fb);
14249 }
14250
14251 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14252                                                 struct drm_file *file,
14253                                                 unsigned int *handle)
14254 {
14255         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14256         struct drm_i915_gem_object *obj = intel_fb->obj;
14257
14258         if (obj->userptr.mm) {
14259                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14260                 return -EINVAL;
14261         }
14262
14263         return drm_gem_handle_create(file, &obj->base, handle);
14264 }
14265
14266 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14267                                         struct drm_file *file,
14268                                         unsigned flags, unsigned color,
14269                                         struct drm_clip_rect *clips,
14270                                         unsigned num_clips)
14271 {
14272         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14273
14274         i915_gem_object_flush_if_display(obj);
14275         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14276
14277         return 0;
14278 }
14279
14280 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14281         .destroy = intel_user_framebuffer_destroy,
14282         .create_handle = intel_user_framebuffer_create_handle,
14283         .dirty = intel_user_framebuffer_dirty,
14284 };
14285
14286 static
14287 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14288                          uint64_t fb_modifier, uint32_t pixel_format)
14289 {
14290         u32 gen = INTEL_GEN(dev_priv);
14291
14292         if (gen >= 9) {
14293                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14294
14295                 /* "The stride in bytes must not exceed the of the size of 8K
14296                  *  pixels and 32K bytes."
14297                  */
14298                 return min(8192 * cpp, 32768);
14299         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14300                 return 32*1024;
14301         } else if (gen >= 4) {
14302                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14303                         return 16*1024;
14304                 else
14305                         return 32*1024;
14306         } else if (gen >= 3) {
14307                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14308                         return 8*1024;
14309                 else
14310                         return 16*1024;
14311         } else {
14312                 /* XXX DSPC is limited to 4k tiled */
14313                 return 8*1024;
14314         }
14315 }
14316
14317 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14318                                   struct drm_i915_gem_object *obj,
14319                                   struct drm_mode_fb_cmd2 *mode_cmd)
14320 {
14321         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14322         struct drm_format_name_buf format_name;
14323         u32 pitch_limit, stride_alignment;
14324         unsigned int tiling, stride;
14325         int ret = -EINVAL;
14326
14327         i915_gem_object_lock(obj);
14328         obj->framebuffer_references++;
14329         tiling = i915_gem_object_get_tiling(obj);
14330         stride = i915_gem_object_get_stride(obj);
14331         i915_gem_object_unlock(obj);
14332
14333         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14334                 /*
14335                  * If there's a fence, enforce that
14336                  * the fb modifier and tiling mode match.
14337                  */
14338                 if (tiling != I915_TILING_NONE &&
14339                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14340                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14341                         goto err;
14342                 }
14343         } else {
14344                 if (tiling == I915_TILING_X) {
14345                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14346                 } else if (tiling == I915_TILING_Y) {
14347                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14348                         goto err;
14349                 }
14350         }
14351
14352         /* Passed in modifier sanity checking. */
14353         switch (mode_cmd->modifier[0]) {
14354         case I915_FORMAT_MOD_Y_TILED:
14355         case I915_FORMAT_MOD_Yf_TILED:
14356                 if (INTEL_GEN(dev_priv) < 9) {
14357                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14358                                       mode_cmd->modifier[0]);
14359                         goto err;
14360                 }
14361         case DRM_FORMAT_MOD_LINEAR:
14362         case I915_FORMAT_MOD_X_TILED:
14363                 break;
14364         default:
14365                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14366                               mode_cmd->modifier[0]);
14367                 goto err;
14368         }
14369
14370         /*
14371          * gen2/3 display engine uses the fence if present,
14372          * so the tiling mode must match the fb modifier exactly.
14373          */
14374         if (INTEL_INFO(dev_priv)->gen < 4 &&
14375             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14376                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14377                 goto err;
14378         }
14379
14380         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14381                                            mode_cmd->pixel_format);
14382         if (mode_cmd->pitches[0] > pitch_limit) {
14383                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14384                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14385                               "tiled" : "linear",
14386                               mode_cmd->pitches[0], pitch_limit);
14387                 goto err;
14388         }
14389
14390         /*
14391          * If there's a fence, enforce that
14392          * the fb pitch and fence stride match.
14393          */
14394         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14395                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14396                               mode_cmd->pitches[0], stride);
14397                 goto err;
14398         }
14399
14400         /* Reject formats not supported by any plane early. */
14401         switch (mode_cmd->pixel_format) {
14402         case DRM_FORMAT_C8:
14403         case DRM_FORMAT_RGB565:
14404         case DRM_FORMAT_XRGB8888:
14405         case DRM_FORMAT_ARGB8888:
14406                 break;
14407         case DRM_FORMAT_XRGB1555:
14408                 if (INTEL_GEN(dev_priv) > 3) {
14409                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14410                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14411                         goto err;
14412                 }
14413                 break;
14414         case DRM_FORMAT_ABGR8888:
14415                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14416                     INTEL_GEN(dev_priv) < 9) {
14417                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14418                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14419                         goto err;
14420                 }
14421                 break;
14422         case DRM_FORMAT_XBGR8888:
14423         case DRM_FORMAT_XRGB2101010:
14424         case DRM_FORMAT_XBGR2101010:
14425                 if (INTEL_GEN(dev_priv) < 4) {
14426                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14427                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14428                         goto err;
14429                 }
14430                 break;
14431         case DRM_FORMAT_ABGR2101010:
14432                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14433                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14434                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14435                         goto err;
14436                 }
14437                 break;
14438         case DRM_FORMAT_YUYV:
14439         case DRM_FORMAT_UYVY:
14440         case DRM_FORMAT_YVYU:
14441         case DRM_FORMAT_VYUY:
14442                 if (INTEL_GEN(dev_priv) < 5) {
14443                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14444                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14445                         goto err;
14446                 }
14447                 break;
14448         default:
14449                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14450                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
14451                 goto err;
14452         }
14453
14454         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14455         if (mode_cmd->offsets[0] != 0)
14456                 goto err;
14457
14458         drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14459                                        &intel_fb->base, mode_cmd);
14460
14461         stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
14462         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14463                 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
14464                               mode_cmd->pitches[0], stride_alignment);
14465                 goto err;
14466         }
14467
14468         intel_fb->obj = obj;
14469
14470         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14471         if (ret)
14472                 goto err;
14473
14474         ret = drm_framebuffer_init(obj->base.dev,
14475                                    &intel_fb->base,
14476                                    &intel_fb_funcs);
14477         if (ret) {
14478                 DRM_ERROR("framebuffer init failed %d\n", ret);
14479                 goto err;
14480         }
14481
14482         return 0;
14483
14484 err:
14485         i915_gem_object_lock(obj);
14486         obj->framebuffer_references--;
14487         i915_gem_object_unlock(obj);
14488         return ret;
14489 }
14490
14491 static struct drm_framebuffer *
14492 intel_user_framebuffer_create(struct drm_device *dev,
14493                               struct drm_file *filp,
14494                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14495 {
14496         struct drm_framebuffer *fb;
14497         struct drm_i915_gem_object *obj;
14498         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14499
14500         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14501         if (!obj)
14502                 return ERR_PTR(-ENOENT);
14503
14504         fb = intel_framebuffer_create(obj, &mode_cmd);
14505         if (IS_ERR(fb))
14506                 i915_gem_object_put(obj);
14507
14508         return fb;
14509 }
14510
14511 static void intel_atomic_state_free(struct drm_atomic_state *state)
14512 {
14513         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14514
14515         drm_atomic_state_default_release(state);
14516
14517         i915_sw_fence_fini(&intel_state->commit_ready);
14518
14519         kfree(state);
14520 }
14521
14522 static const struct drm_mode_config_funcs intel_mode_funcs = {
14523         .fb_create = intel_user_framebuffer_create,
14524         .output_poll_changed = intel_fbdev_output_poll_changed,
14525         .atomic_check = intel_atomic_check,
14526         .atomic_commit = intel_atomic_commit,
14527         .atomic_state_alloc = intel_atomic_state_alloc,
14528         .atomic_state_clear = intel_atomic_state_clear,
14529         .atomic_state_free = intel_atomic_state_free,
14530 };
14531
14532 /**
14533  * intel_init_display_hooks - initialize the display modesetting hooks
14534  * @dev_priv: device private
14535  */
14536 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14537 {
14538         intel_init_cdclk_hooks(dev_priv);
14539
14540         if (INTEL_INFO(dev_priv)->gen >= 9) {
14541                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14542                 dev_priv->display.get_initial_plane_config =
14543                         skylake_get_initial_plane_config;
14544                 dev_priv->display.crtc_compute_clock =
14545                         haswell_crtc_compute_clock;
14546                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14547                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14548         } else if (HAS_DDI(dev_priv)) {
14549                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14550                 dev_priv->display.get_initial_plane_config =
14551                         ironlake_get_initial_plane_config;
14552                 dev_priv->display.crtc_compute_clock =
14553                         haswell_crtc_compute_clock;
14554                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14555                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14556         } else if (HAS_PCH_SPLIT(dev_priv)) {
14557                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14558                 dev_priv->display.get_initial_plane_config =
14559                         ironlake_get_initial_plane_config;
14560                 dev_priv->display.crtc_compute_clock =
14561                         ironlake_crtc_compute_clock;
14562                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14563                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14564         } else if (IS_CHERRYVIEW(dev_priv)) {
14565                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14566                 dev_priv->display.get_initial_plane_config =
14567                         i9xx_get_initial_plane_config;
14568                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14569                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14570                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14571         } else if (IS_VALLEYVIEW(dev_priv)) {
14572                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14573                 dev_priv->display.get_initial_plane_config =
14574                         i9xx_get_initial_plane_config;
14575                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14576                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14577                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14578         } else if (IS_G4X(dev_priv)) {
14579                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14580                 dev_priv->display.get_initial_plane_config =
14581                         i9xx_get_initial_plane_config;
14582                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14583                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14584                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14585         } else if (IS_PINEVIEW(dev_priv)) {
14586                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14587                 dev_priv->display.get_initial_plane_config =
14588                         i9xx_get_initial_plane_config;
14589                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14590                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14591                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14592         } else if (!IS_GEN2(dev_priv)) {
14593                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14594                 dev_priv->display.get_initial_plane_config =
14595                         i9xx_get_initial_plane_config;
14596                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14597                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14598                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14599         } else {
14600                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14601                 dev_priv->display.get_initial_plane_config =
14602                         i9xx_get_initial_plane_config;
14603                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14604                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14605                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14606         }
14607
14608         if (IS_GEN5(dev_priv)) {
14609                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14610         } else if (IS_GEN6(dev_priv)) {
14611                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14612         } else if (IS_IVYBRIDGE(dev_priv)) {
14613                 /* FIXME: detect B0+ stepping and use auto training */
14614                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14615         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14616                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14617         }
14618
14619         if (dev_priv->info.gen >= 9)
14620                 dev_priv->display.update_crtcs = skl_update_crtcs;
14621         else
14622                 dev_priv->display.update_crtcs = intel_update_crtcs;
14623
14624         switch (INTEL_INFO(dev_priv)->gen) {
14625         case 2:
14626                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14627                 break;
14628
14629         case 3:
14630                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14631                 break;
14632
14633         case 4:
14634         case 5:
14635                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14636                 break;
14637
14638         case 6:
14639                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14640                 break;
14641         case 7:
14642         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14643                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14644                 break;
14645         case 9:
14646                 /* Drop through - unsupported since execlist only. */
14647         default:
14648                 /* Default just returns -ENODEV to indicate unsupported */
14649                 dev_priv->display.queue_flip = intel_default_queue_flip;
14650         }
14651 }
14652
14653 /*
14654  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14655  * resume, or other times.  This quirk makes sure that's the case for
14656  * affected systems.
14657  */
14658 static void quirk_pipea_force(struct drm_device *dev)
14659 {
14660         struct drm_i915_private *dev_priv = to_i915(dev);
14661
14662         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14663         DRM_INFO("applying pipe a force quirk\n");
14664 }
14665
14666 static void quirk_pipeb_force(struct drm_device *dev)
14667 {
14668         struct drm_i915_private *dev_priv = to_i915(dev);
14669
14670         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14671         DRM_INFO("applying pipe b force quirk\n");
14672 }
14673
14674 /*
14675  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14676  */
14677 static void quirk_ssc_force_disable(struct drm_device *dev)
14678 {
14679         struct drm_i915_private *dev_priv = to_i915(dev);
14680         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14681         DRM_INFO("applying lvds SSC disable quirk\n");
14682 }
14683
14684 /*
14685  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14686  * brightness value
14687  */
14688 static void quirk_invert_brightness(struct drm_device *dev)
14689 {
14690         struct drm_i915_private *dev_priv = to_i915(dev);
14691         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14692         DRM_INFO("applying inverted panel brightness quirk\n");
14693 }
14694
14695 /* Some VBT's incorrectly indicate no backlight is present */
14696 static void quirk_backlight_present(struct drm_device *dev)
14697 {
14698         struct drm_i915_private *dev_priv = to_i915(dev);
14699         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14700         DRM_INFO("applying backlight present quirk\n");
14701 }
14702
14703 struct intel_quirk {
14704         int device;
14705         int subsystem_vendor;
14706         int subsystem_device;
14707         void (*hook)(struct drm_device *dev);
14708 };
14709
14710 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14711 struct intel_dmi_quirk {
14712         void (*hook)(struct drm_device *dev);
14713         const struct dmi_system_id (*dmi_id_list)[];
14714 };
14715
14716 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14717 {
14718         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14719         return 1;
14720 }
14721
14722 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14723         {
14724                 .dmi_id_list = &(const struct dmi_system_id[]) {
14725                         {
14726                                 .callback = intel_dmi_reverse_brightness,
14727                                 .ident = "NCR Corporation",
14728                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14729                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14730                                 },
14731                         },
14732                         { }  /* terminating entry */
14733                 },
14734                 .hook = quirk_invert_brightness,
14735         },
14736 };
14737
14738 static struct intel_quirk intel_quirks[] = {
14739         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14740         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14741
14742         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14743         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14744
14745         /* 830 needs to leave pipe A & dpll A up */
14746         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14747
14748         /* 830 needs to leave pipe B & dpll B up */
14749         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14750
14751         /* Lenovo U160 cannot use SSC on LVDS */
14752         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14753
14754         /* Sony Vaio Y cannot use SSC on LVDS */
14755         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14756
14757         /* Acer Aspire 5734Z must invert backlight brightness */
14758         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14759
14760         /* Acer/eMachines G725 */
14761         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14762
14763         /* Acer/eMachines e725 */
14764         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14765
14766         /* Acer/Packard Bell NCL20 */
14767         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14768
14769         /* Acer Aspire 4736Z */
14770         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14771
14772         /* Acer Aspire 5336 */
14773         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14774
14775         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14776         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14777
14778         /* Acer C720 Chromebook (Core i3 4005U) */
14779         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14780
14781         /* Apple Macbook 2,1 (Core 2 T7400) */
14782         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14783
14784         /* Apple Macbook 4,1 */
14785         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14786
14787         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14788         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14789
14790         /* HP Chromebook 14 (Celeron 2955U) */
14791         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14792
14793         /* Dell Chromebook 11 */
14794         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14795
14796         /* Dell Chromebook 11 (2015 version) */
14797         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14798 };
14799
14800 static void intel_init_quirks(struct drm_device *dev)
14801 {
14802         struct pci_dev *d = dev->pdev;
14803         int i;
14804
14805         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14806                 struct intel_quirk *q = &intel_quirks[i];
14807
14808                 if (d->device == q->device &&
14809                     (d->subsystem_vendor == q->subsystem_vendor ||
14810                      q->subsystem_vendor == PCI_ANY_ID) &&
14811                     (d->subsystem_device == q->subsystem_device ||
14812                      q->subsystem_device == PCI_ANY_ID))
14813                         q->hook(dev);
14814         }
14815         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14816                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14817                         intel_dmi_quirks[i].hook(dev);
14818         }
14819 }
14820
14821 /* Disable the VGA plane that we never use */
14822 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14823 {
14824         struct pci_dev *pdev = dev_priv->drm.pdev;
14825         u8 sr1;
14826         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14827
14828         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14829         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14830         outb(SR01, VGA_SR_INDEX);
14831         sr1 = inb(VGA_SR_DATA);
14832         outb(sr1 | 1<<5, VGA_SR_DATA);
14833         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14834         udelay(300);
14835
14836         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14837         POSTING_READ(vga_reg);
14838 }
14839
14840 void intel_modeset_init_hw(struct drm_device *dev)
14841 {
14842         struct drm_i915_private *dev_priv = to_i915(dev);
14843
14844         intel_update_cdclk(dev_priv);
14845         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14846
14847         intel_init_clock_gating(dev_priv);
14848 }
14849
14850 /*
14851  * Calculate what we think the watermarks should be for the state we've read
14852  * out of the hardware and then immediately program those watermarks so that
14853  * we ensure the hardware settings match our internal state.
14854  *
14855  * We can calculate what we think WM's should be by creating a duplicate of the
14856  * current state (which was constructed during hardware readout) and running it
14857  * through the atomic check code to calculate new watermark values in the
14858  * state object.
14859  */
14860 static void sanitize_watermarks(struct drm_device *dev)
14861 {
14862         struct drm_i915_private *dev_priv = to_i915(dev);
14863         struct drm_atomic_state *state;
14864         struct intel_atomic_state *intel_state;
14865         struct drm_crtc *crtc;
14866         struct drm_crtc_state *cstate;
14867         struct drm_modeset_acquire_ctx ctx;
14868         int ret;
14869         int i;
14870
14871         /* Only supported on platforms that use atomic watermark design */
14872         if (!dev_priv->display.optimize_watermarks)
14873                 return;
14874
14875         /*
14876          * We need to hold connection_mutex before calling duplicate_state so
14877          * that the connector loop is protected.
14878          */
14879         drm_modeset_acquire_init(&ctx, 0);
14880 retry:
14881         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14882         if (ret == -EDEADLK) {
14883                 drm_modeset_backoff(&ctx);
14884                 goto retry;
14885         } else if (WARN_ON(ret)) {
14886                 goto fail;
14887         }
14888
14889         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14890         if (WARN_ON(IS_ERR(state)))
14891                 goto fail;
14892
14893         intel_state = to_intel_atomic_state(state);
14894
14895         /*
14896          * Hardware readout is the only time we don't want to calculate
14897          * intermediate watermarks (since we don't trust the current
14898          * watermarks).
14899          */
14900         if (!HAS_GMCH_DISPLAY(dev_priv))
14901                 intel_state->skip_intermediate_wm = true;
14902
14903         ret = intel_atomic_check(dev, state);
14904         if (ret) {
14905                 /*
14906                  * If we fail here, it means that the hardware appears to be
14907                  * programmed in a way that shouldn't be possible, given our
14908                  * understanding of watermark requirements.  This might mean a
14909                  * mistake in the hardware readout code or a mistake in the
14910                  * watermark calculations for a given platform.  Raise a WARN
14911                  * so that this is noticeable.
14912                  *
14913                  * If this actually happens, we'll have to just leave the
14914                  * BIOS-programmed watermarks untouched and hope for the best.
14915                  */
14916                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14917                 goto put_state;
14918         }
14919
14920         /* Write calculated watermark values back */
14921         for_each_new_crtc_in_state(state, crtc, cstate, i) {
14922                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14923
14924                 cs->wm.need_postvbl_update = true;
14925                 dev_priv->display.optimize_watermarks(intel_state, cs);
14926         }
14927
14928 put_state:
14929         drm_atomic_state_put(state);
14930 fail:
14931         drm_modeset_drop_locks(&ctx);
14932         drm_modeset_acquire_fini(&ctx);
14933 }
14934
14935 int intel_modeset_init(struct drm_device *dev)
14936 {
14937         struct drm_i915_private *dev_priv = to_i915(dev);
14938         struct i915_ggtt *ggtt = &dev_priv->ggtt;
14939         enum pipe pipe;
14940         struct intel_crtc *crtc;
14941
14942         drm_mode_config_init(dev);
14943
14944         dev->mode_config.min_width = 0;
14945         dev->mode_config.min_height = 0;
14946
14947         dev->mode_config.preferred_depth = 24;
14948         dev->mode_config.prefer_shadow = 1;
14949
14950         dev->mode_config.allow_fb_modifiers = true;
14951
14952         dev->mode_config.funcs = &intel_mode_funcs;
14953
14954         INIT_WORK(&dev_priv->atomic_helper.free_work,
14955                   intel_atomic_helper_free_state_worker);
14956
14957         intel_init_quirks(dev);
14958
14959         intel_init_pm(dev_priv);
14960
14961         if (INTEL_INFO(dev_priv)->num_pipes == 0)
14962                 return 0;
14963
14964         /*
14965          * There may be no VBT; and if the BIOS enabled SSC we can
14966          * just keep using it to avoid unnecessary flicker.  Whereas if the
14967          * BIOS isn't using it, don't assume it will work even if the VBT
14968          * indicates as much.
14969          */
14970         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14971                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14972                                             DREF_SSC1_ENABLE);
14973
14974                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14975                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14976                                      bios_lvds_use_ssc ? "en" : "dis",
14977                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14978                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14979                 }
14980         }
14981
14982         if (IS_GEN2(dev_priv)) {
14983                 dev->mode_config.max_width = 2048;
14984                 dev->mode_config.max_height = 2048;
14985         } else if (IS_GEN3(dev_priv)) {
14986                 dev->mode_config.max_width = 4096;
14987                 dev->mode_config.max_height = 4096;
14988         } else {
14989                 dev->mode_config.max_width = 8192;
14990                 dev->mode_config.max_height = 8192;
14991         }
14992
14993         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14994                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14995                 dev->mode_config.cursor_height = 1023;
14996         } else if (IS_GEN2(dev_priv)) {
14997                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14998                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14999         } else {
15000                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15001                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15002         }
15003
15004         dev->mode_config.fb_base = ggtt->mappable_base;
15005
15006         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15007                       INTEL_INFO(dev_priv)->num_pipes,
15008                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15009
15010         for_each_pipe(dev_priv, pipe) {
15011                 int ret;
15012
15013                 ret = intel_crtc_init(dev_priv, pipe);
15014                 if (ret) {
15015                         drm_mode_config_cleanup(dev);
15016                         return ret;
15017                 }
15018         }
15019
15020         intel_shared_dpll_init(dev);
15021
15022         intel_update_czclk(dev_priv);
15023         intel_modeset_init_hw(dev);
15024
15025         if (dev_priv->max_cdclk_freq == 0)
15026                 intel_update_max_cdclk(dev_priv);
15027
15028         /* Just disable it once at startup */
15029         i915_disable_vga(dev_priv);
15030         intel_setup_outputs(dev_priv);
15031
15032         drm_modeset_lock_all(dev);
15033         intel_modeset_setup_hw_state(dev);
15034         drm_modeset_unlock_all(dev);
15035
15036         for_each_intel_crtc(dev, crtc) {
15037                 struct intel_initial_plane_config plane_config = {};
15038
15039                 if (!crtc->active)
15040                         continue;
15041
15042                 /*
15043                  * Note that reserving the BIOS fb up front prevents us
15044                  * from stuffing other stolen allocations like the ring
15045                  * on top.  This prevents some ugliness at boot time, and
15046                  * can even allow for smooth boot transitions if the BIOS
15047                  * fb is large enough for the active pipe configuration.
15048                  */
15049                 dev_priv->display.get_initial_plane_config(crtc,
15050                                                            &plane_config);
15051
15052                 /*
15053                  * If the fb is shared between multiple heads, we'll
15054                  * just get the first one.
15055                  */
15056                 intel_find_initial_plane_obj(crtc, &plane_config);
15057         }
15058
15059         /*
15060          * Make sure hardware watermarks really match the state we read out.
15061          * Note that we need to do this after reconstructing the BIOS fb's
15062          * since the watermark calculation done here will use pstate->fb.
15063          */
15064         if (!HAS_GMCH_DISPLAY(dev_priv))
15065                 sanitize_watermarks(dev);
15066
15067         return 0;
15068 }
15069
15070 static void intel_enable_pipe_a(struct drm_device *dev)
15071 {
15072         struct intel_connector *connector;
15073         struct drm_connector_list_iter conn_iter;
15074         struct drm_connector *crt = NULL;
15075         struct intel_load_detect_pipe load_detect_temp;
15076         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15077         int ret;
15078
15079         /* We can't just switch on the pipe A, we need to set things up with a
15080          * proper mode and output configuration. As a gross hack, enable pipe A
15081          * by enabling the load detect pipe once. */
15082         drm_connector_list_iter_begin(dev, &conn_iter);
15083         for_each_intel_connector_iter(connector, &conn_iter) {
15084                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15085                         crt = &connector->base;
15086                         break;
15087                 }
15088         }
15089         drm_connector_list_iter_end(&conn_iter);
15090
15091         if (!crt)
15092                 return;
15093
15094         ret = intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx);
15095         WARN(ret < 0, "All modeset mutexes are locked, but intel_get_load_detect_pipe failed\n");
15096
15097         if (ret > 0)
15098                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15099 }
15100
15101 static bool
15102 intel_check_plane_mapping(struct intel_crtc *crtc)
15103 {
15104         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15105         u32 val;
15106
15107         if (INTEL_INFO(dev_priv)->num_pipes == 1)
15108                 return true;
15109
15110         val = I915_READ(DSPCNTR(!crtc->plane));
15111
15112         if ((val & DISPLAY_PLANE_ENABLE) &&
15113             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15114                 return false;
15115
15116         return true;
15117 }
15118
15119 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15120 {
15121         struct drm_device *dev = crtc->base.dev;
15122         struct intel_encoder *encoder;
15123
15124         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15125                 return true;
15126
15127         return false;
15128 }
15129
15130 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15131 {
15132         struct drm_device *dev = encoder->base.dev;
15133         struct intel_connector *connector;
15134
15135         for_each_connector_on_encoder(dev, &encoder->base, connector)
15136                 return connector;
15137
15138         return NULL;
15139 }
15140
15141 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15142                               enum transcoder pch_transcoder)
15143 {
15144         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15145                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15146 }
15147
15148 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15149 {
15150         struct drm_device *dev = crtc->base.dev;
15151         struct drm_i915_private *dev_priv = to_i915(dev);
15152         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15153
15154         /* Clear any frame start delays used for debugging left by the BIOS */
15155         if (!transcoder_is_dsi(cpu_transcoder)) {
15156                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15157
15158                 I915_WRITE(reg,
15159                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15160         }
15161
15162         /* restore vblank interrupts to correct state */
15163         drm_crtc_vblank_reset(&crtc->base);
15164         if (crtc->active) {
15165                 struct intel_plane *plane;
15166
15167                 drm_crtc_vblank_on(&crtc->base);
15168
15169                 /* Disable everything but the primary plane */
15170                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15171                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15172                                 continue;
15173
15174                         trace_intel_disable_plane(&plane->base, crtc);
15175                         plane->disable_plane(&plane->base, &crtc->base);
15176                 }
15177         }
15178
15179         /* We need to sanitize the plane -> pipe mapping first because this will
15180          * disable the crtc (and hence change the state) if it is wrong. Note
15181          * that gen4+ has a fixed plane -> pipe mapping.  */
15182         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15183                 bool plane;
15184
15185                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15186                               crtc->base.base.id, crtc->base.name);
15187
15188                 /* Pipe has the wrong plane attached and the plane is active.
15189                  * Temporarily change the plane mapping and disable everything
15190                  * ...  */
15191                 plane = crtc->plane;
15192                 crtc->base.primary->state->visible = true;
15193                 crtc->plane = !plane;
15194                 intel_crtc_disable_noatomic(&crtc->base);
15195                 crtc->plane = plane;
15196         }
15197
15198         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15199             crtc->pipe == PIPE_A && !crtc->active) {
15200                 /* BIOS forgot to enable pipe A, this mostly happens after
15201                  * resume. Force-enable the pipe to fix this, the update_dpms
15202                  * call below we restore the pipe to the right state, but leave
15203                  * the required bits on. */
15204                 intel_enable_pipe_a(dev);
15205         }
15206
15207         /* Adjust the state of the output pipe according to whether we
15208          * have active connectors/encoders. */
15209         if (crtc->active && !intel_crtc_has_encoders(crtc))
15210                 intel_crtc_disable_noatomic(&crtc->base);
15211
15212         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15213                 /*
15214                  * We start out with underrun reporting disabled to avoid races.
15215                  * For correct bookkeeping mark this on active crtcs.
15216                  *
15217                  * Also on gmch platforms we dont have any hardware bits to
15218                  * disable the underrun reporting. Which means we need to start
15219                  * out with underrun reporting disabled also on inactive pipes,
15220                  * since otherwise we'll complain about the garbage we read when
15221                  * e.g. coming up after runtime pm.
15222                  *
15223                  * No protection against concurrent access is required - at
15224                  * worst a fifo underrun happens which also sets this to false.
15225                  */
15226                 crtc->cpu_fifo_underrun_disabled = true;
15227                 /*
15228                  * We track the PCH trancoder underrun reporting state
15229                  * within the crtc. With crtc for pipe A housing the underrun
15230                  * reporting state for PCH transcoder A, crtc for pipe B housing
15231                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15232                  * and marking underrun reporting as disabled for the non-existing
15233                  * PCH transcoders B and C would prevent enabling the south
15234                  * error interrupt (see cpt_can_enable_serr_int()).
15235                  */
15236                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15237                         crtc->pch_fifo_underrun_disabled = true;
15238         }
15239 }
15240
15241 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15242 {
15243         struct intel_connector *connector;
15244
15245         /* We need to check both for a crtc link (meaning that the
15246          * encoder is active and trying to read from a pipe) and the
15247          * pipe itself being active. */
15248         bool has_active_crtc = encoder->base.crtc &&
15249                 to_intel_crtc(encoder->base.crtc)->active;
15250
15251         connector = intel_encoder_find_connector(encoder);
15252         if (connector && !has_active_crtc) {
15253                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15254                               encoder->base.base.id,
15255                               encoder->base.name);
15256
15257                 /* Connector is active, but has no active pipe. This is
15258                  * fallout from our resume register restoring. Disable
15259                  * the encoder manually again. */
15260                 if (encoder->base.crtc) {
15261                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15262
15263                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15264                                       encoder->base.base.id,
15265                                       encoder->base.name);
15266                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15267                         if (encoder->post_disable)
15268                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15269                 }
15270                 encoder->base.crtc = NULL;
15271
15272                 /* Inconsistent output/port/pipe state happens presumably due to
15273                  * a bug in one of the get_hw_state functions. Or someplace else
15274                  * in our code, like the register restore mess on resume. Clamp
15275                  * things to off as a safer default. */
15276
15277                 connector->base.dpms = DRM_MODE_DPMS_OFF;
15278                 connector->base.encoder = NULL;
15279         }
15280         /* Enabled encoders without active connectors will be fixed in
15281          * the crtc fixup. */
15282 }
15283
15284 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15285 {
15286         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15287
15288         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15289                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15290                 i915_disable_vga(dev_priv);
15291         }
15292 }
15293
15294 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15295 {
15296         /* This function can be called both from intel_modeset_setup_hw_state or
15297          * at a very early point in our resume sequence, where the power well
15298          * structures are not yet restored. Since this function is at a very
15299          * paranoid "someone might have enabled VGA while we were not looking"
15300          * level, just check if the power well is enabled instead of trying to
15301          * follow the "don't touch the power well if we don't need it" policy
15302          * the rest of the driver uses. */
15303         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15304                 return;
15305
15306         i915_redisable_vga_power_on(dev_priv);
15307
15308         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15309 }
15310
15311 static bool primary_get_hw_state(struct intel_plane *plane)
15312 {
15313         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15314
15315         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15316 }
15317
15318 /* FIXME read out full plane state for all planes */
15319 static void readout_plane_state(struct intel_crtc *crtc)
15320 {
15321         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
15322         bool visible;
15323
15324         visible = crtc->active && primary_get_hw_state(primary);
15325
15326         intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
15327                                 to_intel_plane_state(primary->base.state),
15328                                 visible);
15329 }
15330
15331 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15332 {
15333         struct drm_i915_private *dev_priv = to_i915(dev);
15334         enum pipe pipe;
15335         struct intel_crtc *crtc;
15336         struct intel_encoder *encoder;
15337         struct intel_connector *connector;
15338         struct drm_connector_list_iter conn_iter;
15339         int i;
15340
15341         dev_priv->active_crtcs = 0;
15342
15343         for_each_intel_crtc(dev, crtc) {
15344                 struct intel_crtc_state *crtc_state =
15345                         to_intel_crtc_state(crtc->base.state);
15346
15347                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15348                 memset(crtc_state, 0, sizeof(*crtc_state));
15349                 crtc_state->base.crtc = &crtc->base;
15350
15351                 crtc_state->base.active = crtc_state->base.enable =
15352                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15353
15354                 crtc->base.enabled = crtc_state->base.enable;
15355                 crtc->active = crtc_state->base.active;
15356
15357                 if (crtc_state->base.active)
15358                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15359
15360                 readout_plane_state(crtc);
15361
15362                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15363                               crtc->base.base.id, crtc->base.name,
15364                               enableddisabled(crtc_state->base.active));
15365         }
15366
15367         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15368                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15369
15370                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15371                                                   &pll->state.hw_state);
15372                 pll->state.crtc_mask = 0;
15373                 for_each_intel_crtc(dev, crtc) {
15374                         struct intel_crtc_state *crtc_state =
15375                                 to_intel_crtc_state(crtc->base.state);
15376
15377                         if (crtc_state->base.active &&
15378                             crtc_state->shared_dpll == pll)
15379                                 pll->state.crtc_mask |= 1 << crtc->pipe;
15380                 }
15381                 pll->active_mask = pll->state.crtc_mask;
15382
15383                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15384                               pll->name, pll->state.crtc_mask, pll->on);
15385         }
15386
15387         for_each_intel_encoder(dev, encoder) {
15388                 pipe = 0;
15389
15390                 if (encoder->get_hw_state(encoder, &pipe)) {
15391                         struct intel_crtc_state *crtc_state;
15392
15393                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15394                         crtc_state = to_intel_crtc_state(crtc->base.state);
15395
15396                         encoder->base.crtc = &crtc->base;
15397                         crtc_state->output_types |= 1 << encoder->type;
15398                         encoder->get_config(encoder, crtc_state);
15399                 } else {
15400                         encoder->base.crtc = NULL;
15401                 }
15402
15403                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15404                               encoder->base.base.id, encoder->base.name,
15405                               enableddisabled(encoder->base.crtc),
15406                               pipe_name(pipe));
15407         }
15408
15409         drm_connector_list_iter_begin(dev, &conn_iter);
15410         for_each_intel_connector_iter(connector, &conn_iter) {
15411                 if (connector->get_hw_state(connector)) {
15412                         connector->base.dpms = DRM_MODE_DPMS_ON;
15413
15414                         encoder = connector->encoder;
15415                         connector->base.encoder = &encoder->base;
15416
15417                         if (encoder->base.crtc &&
15418                             encoder->base.crtc->state->active) {
15419                                 /*
15420                                  * This has to be done during hardware readout
15421                                  * because anything calling .crtc_disable may
15422                                  * rely on the connector_mask being accurate.
15423                                  */
15424                                 encoder->base.crtc->state->connector_mask |=
15425                                         1 << drm_connector_index(&connector->base);
15426                                 encoder->base.crtc->state->encoder_mask |=
15427                                         1 << drm_encoder_index(&encoder->base);
15428                         }
15429
15430                 } else {
15431                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15432                         connector->base.encoder = NULL;
15433                 }
15434                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15435                               connector->base.base.id, connector->base.name,
15436                               enableddisabled(connector->base.encoder));
15437         }
15438         drm_connector_list_iter_end(&conn_iter);
15439
15440         for_each_intel_crtc(dev, crtc) {
15441                 struct intel_crtc_state *crtc_state =
15442                         to_intel_crtc_state(crtc->base.state);
15443                 int pixclk = 0;
15444
15445                 crtc->base.hwmode = crtc_state->base.adjusted_mode;
15446
15447                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15448                 if (crtc_state->base.active) {
15449                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15450                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15451                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15452
15453                         /*
15454                          * The initial mode needs to be set in order to keep
15455                          * the atomic core happy. It wants a valid mode if the
15456                          * crtc's enabled, so we do the above call.
15457                          *
15458                          * But we don't set all the derived state fully, hence
15459                          * set a flag to indicate that a full recalculation is
15460                          * needed on the next commit.
15461                          */
15462                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15463
15464                         intel_crtc_compute_pixel_rate(crtc_state);
15465
15466                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15467                             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15468                                 pixclk = crtc_state->pixel_rate;
15469                         else
15470                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15471
15472                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15473                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15474                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15475
15476                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15477                         update_scanline_offset(crtc);
15478                 }
15479
15480                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15481
15482                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15483         }
15484 }
15485
15486 static void
15487 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15488 {
15489         struct intel_encoder *encoder;
15490
15491         for_each_intel_encoder(&dev_priv->drm, encoder) {
15492                 u64 get_domains;
15493                 enum intel_display_power_domain domain;
15494
15495                 if (!encoder->get_power_domains)
15496                         continue;
15497
15498                 get_domains = encoder->get_power_domains(encoder);
15499                 for_each_power_domain(domain, get_domains)
15500                         intel_display_power_get(dev_priv, domain);
15501         }
15502 }
15503
15504 /* Scan out the current hw modeset state,
15505  * and sanitizes it to the current state
15506  */
15507 static void
15508 intel_modeset_setup_hw_state(struct drm_device *dev)
15509 {
15510         struct drm_i915_private *dev_priv = to_i915(dev);
15511         enum pipe pipe;
15512         struct intel_crtc *crtc;
15513         struct intel_encoder *encoder;
15514         int i;
15515
15516         intel_modeset_readout_hw_state(dev);
15517
15518         /* HW state is read out, now we need to sanitize this mess. */
15519         get_encoder_power_domains(dev_priv);
15520
15521         for_each_intel_encoder(dev, encoder) {
15522                 intel_sanitize_encoder(encoder);
15523         }
15524
15525         for_each_pipe(dev_priv, pipe) {
15526                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15527
15528                 intel_sanitize_crtc(crtc);
15529                 intel_dump_pipe_config(crtc, crtc->config,
15530                                        "[setup_hw_state]");
15531         }
15532
15533         intel_modeset_update_connector_atomic_state(dev);
15534
15535         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15536                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15537
15538                 if (!pll->on || pll->active_mask)
15539                         continue;
15540
15541                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15542
15543                 pll->funcs.disable(dev_priv, pll);
15544                 pll->on = false;
15545         }
15546
15547         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15548                 vlv_wm_get_hw_state(dev);
15549                 vlv_wm_sanitize(dev_priv);
15550         } else if (IS_GEN9(dev_priv)) {
15551                 skl_wm_get_hw_state(dev);
15552         } else if (HAS_PCH_SPLIT(dev_priv)) {
15553                 ilk_wm_get_hw_state(dev);
15554         }
15555
15556         for_each_intel_crtc(dev, crtc) {
15557                 u64 put_domains;
15558
15559                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15560                 if (WARN_ON(put_domains))
15561                         modeset_put_power_domains(dev_priv, put_domains);
15562         }
15563         intel_display_set_init_power(dev_priv, false);
15564
15565         intel_power_domains_verify_state(dev_priv);
15566
15567         intel_fbc_init_pipe_state(dev_priv);
15568 }
15569
15570 void intel_display_resume(struct drm_device *dev)
15571 {
15572         struct drm_i915_private *dev_priv = to_i915(dev);
15573         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15574         struct drm_modeset_acquire_ctx ctx;
15575         int ret;
15576
15577         dev_priv->modeset_restore_state = NULL;
15578         if (state)
15579                 state->acquire_ctx = &ctx;
15580
15581         /*
15582          * This is a cludge because with real atomic modeset mode_config.mutex
15583          * won't be taken. Unfortunately some probed state like
15584          * audio_codec_enable is still protected by mode_config.mutex, so lock
15585          * it here for now.
15586          */
15587         mutex_lock(&dev->mode_config.mutex);
15588         drm_modeset_acquire_init(&ctx, 0);
15589
15590         while (1) {
15591                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15592                 if (ret != -EDEADLK)
15593                         break;
15594
15595                 drm_modeset_backoff(&ctx);
15596         }
15597
15598         if (!ret)
15599                 ret = __intel_display_resume(dev, state, &ctx);
15600
15601         drm_modeset_drop_locks(&ctx);
15602         drm_modeset_acquire_fini(&ctx);
15603         mutex_unlock(&dev->mode_config.mutex);
15604
15605         if (ret)
15606                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15607         if (state)
15608                 drm_atomic_state_put(state);
15609 }
15610
15611 void intel_modeset_gem_init(struct drm_device *dev)
15612 {
15613         struct drm_i915_private *dev_priv = to_i915(dev);
15614
15615         intel_init_gt_powersave(dev_priv);
15616
15617         intel_setup_overlay(dev_priv);
15618 }
15619
15620 int intel_connector_register(struct drm_connector *connector)
15621 {
15622         struct intel_connector *intel_connector = to_intel_connector(connector);
15623         int ret;
15624
15625         ret = intel_backlight_device_register(intel_connector);
15626         if (ret)
15627                 goto err;
15628
15629         return 0;
15630
15631 err:
15632         return ret;
15633 }
15634
15635 void intel_connector_unregister(struct drm_connector *connector)
15636 {
15637         struct intel_connector *intel_connector = to_intel_connector(connector);
15638
15639         intel_backlight_device_unregister(intel_connector);
15640         intel_panel_destroy_backlight(connector);
15641 }
15642
15643 void intel_modeset_cleanup(struct drm_device *dev)
15644 {
15645         struct drm_i915_private *dev_priv = to_i915(dev);
15646
15647         flush_work(&dev_priv->atomic_helper.free_work);
15648         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15649
15650         intel_disable_gt_powersave(dev_priv);
15651
15652         /*
15653          * Interrupts and polling as the first thing to avoid creating havoc.
15654          * Too much stuff here (turning of connectors, ...) would
15655          * experience fancy races otherwise.
15656          */
15657         intel_irq_uninstall(dev_priv);
15658
15659         /*
15660          * Due to the hpd irq storm handling the hotplug work can re-arm the
15661          * poll handlers. Hence disable polling after hpd handling is shut down.
15662          */
15663         drm_kms_helper_poll_fini(dev);
15664
15665         intel_unregister_dsm_handler();
15666
15667         intel_fbc_global_disable(dev_priv);
15668
15669         /* flush any delayed tasks or pending work */
15670         flush_scheduled_work();
15671
15672         drm_mode_config_cleanup(dev);
15673
15674         intel_cleanup_overlay(dev_priv);
15675
15676         intel_cleanup_gt_powersave(dev_priv);
15677
15678         intel_teardown_gmbus(dev_priv);
15679 }
15680
15681 void intel_connector_attach_encoder(struct intel_connector *connector,
15682                                     struct intel_encoder *encoder)
15683 {
15684         connector->encoder = encoder;
15685         drm_mode_connector_attach_encoder(&connector->base,
15686                                           &encoder->base);
15687 }
15688
15689 /*
15690  * set vga decode state - true == enable VGA decode
15691  */
15692 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15693 {
15694         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15695         u16 gmch_ctrl;
15696
15697         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15698                 DRM_ERROR("failed to read control word\n");
15699                 return -EIO;
15700         }
15701
15702         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15703                 return 0;
15704
15705         if (state)
15706                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15707         else
15708                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15709
15710         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15711                 DRM_ERROR("failed to write control word\n");
15712                 return -EIO;
15713         }
15714
15715         return 0;
15716 }
15717
15718 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15719
15720 struct intel_display_error_state {
15721
15722         u32 power_well_driver;
15723
15724         int num_transcoders;
15725
15726         struct intel_cursor_error_state {
15727                 u32 control;
15728                 u32 position;
15729                 u32 base;
15730                 u32 size;
15731         } cursor[I915_MAX_PIPES];
15732
15733         struct intel_pipe_error_state {
15734                 bool power_domain_on;
15735                 u32 source;
15736                 u32 stat;
15737         } pipe[I915_MAX_PIPES];
15738
15739         struct intel_plane_error_state {
15740                 u32 control;
15741                 u32 stride;
15742                 u32 size;
15743                 u32 pos;
15744                 u32 addr;
15745                 u32 surface;
15746                 u32 tile_offset;
15747         } plane[I915_MAX_PIPES];
15748
15749         struct intel_transcoder_error_state {
15750                 bool power_domain_on;
15751                 enum transcoder cpu_transcoder;
15752
15753                 u32 conf;
15754
15755                 u32 htotal;
15756                 u32 hblank;
15757                 u32 hsync;
15758                 u32 vtotal;
15759                 u32 vblank;
15760                 u32 vsync;
15761         } transcoder[4];
15762 };
15763
15764 struct intel_display_error_state *
15765 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15766 {
15767         struct intel_display_error_state *error;
15768         int transcoders[] = {
15769                 TRANSCODER_A,
15770                 TRANSCODER_B,
15771                 TRANSCODER_C,
15772                 TRANSCODER_EDP,
15773         };
15774         int i;
15775
15776         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15777                 return NULL;
15778
15779         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15780         if (error == NULL)
15781                 return NULL;
15782
15783         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15784                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15785
15786         for_each_pipe(dev_priv, i) {
15787                 error->pipe[i].power_domain_on =
15788                         __intel_display_power_is_enabled(dev_priv,
15789                                                          POWER_DOMAIN_PIPE(i));
15790                 if (!error->pipe[i].power_domain_on)
15791                         continue;
15792
15793                 error->cursor[i].control = I915_READ(CURCNTR(i));
15794                 error->cursor[i].position = I915_READ(CURPOS(i));
15795                 error->cursor[i].base = I915_READ(CURBASE(i));
15796
15797                 error->plane[i].control = I915_READ(DSPCNTR(i));
15798                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15799                 if (INTEL_GEN(dev_priv) <= 3) {
15800                         error->plane[i].size = I915_READ(DSPSIZE(i));
15801                         error->plane[i].pos = I915_READ(DSPPOS(i));
15802                 }
15803                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15804                         error->plane[i].addr = I915_READ(DSPADDR(i));
15805                 if (INTEL_GEN(dev_priv) >= 4) {
15806                         error->plane[i].surface = I915_READ(DSPSURF(i));
15807                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15808                 }
15809
15810                 error->pipe[i].source = I915_READ(PIPESRC(i));
15811
15812                 if (HAS_GMCH_DISPLAY(dev_priv))
15813                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15814         }
15815
15816         /* Note: this does not include DSI transcoders. */
15817         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15818         if (HAS_DDI(dev_priv))
15819                 error->num_transcoders++; /* Account for eDP. */
15820
15821         for (i = 0; i < error->num_transcoders; i++) {
15822                 enum transcoder cpu_transcoder = transcoders[i];
15823
15824                 error->transcoder[i].power_domain_on =
15825                         __intel_display_power_is_enabled(dev_priv,
15826                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15827                 if (!error->transcoder[i].power_domain_on)
15828                         continue;
15829
15830                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15831
15832                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15833                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15834                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15835                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15836                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15837                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15838                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15839         }
15840
15841         return error;
15842 }
15843
15844 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15845
15846 void
15847 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15848                                 struct intel_display_error_state *error)
15849 {
15850         struct drm_i915_private *dev_priv = m->i915;
15851         int i;
15852
15853         if (!error)
15854                 return;
15855
15856         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15857         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15858                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15859                            error->power_well_driver);
15860         for_each_pipe(dev_priv, i) {
15861                 err_printf(m, "Pipe [%d]:\n", i);
15862                 err_printf(m, "  Power: %s\n",
15863                            onoff(error->pipe[i].power_domain_on));
15864                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15865                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15866
15867                 err_printf(m, "Plane [%d]:\n", i);
15868                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15869                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15870                 if (INTEL_GEN(dev_priv) <= 3) {
15871                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15872                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15873                 }
15874                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15875                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15876                 if (INTEL_GEN(dev_priv) >= 4) {
15877                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15878                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15879                 }
15880
15881                 err_printf(m, "Cursor [%d]:\n", i);
15882                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15883                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15884                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15885         }
15886
15887         for (i = 0; i < error->num_transcoders; i++) {
15888                 err_printf(m, "CPU transcoder: %s\n",
15889                            transcoder_name(error->transcoder[i].cpu_transcoder));
15890                 err_printf(m, "  Power: %s\n",
15891                            onoff(error->transcoder[i].power_domain_on));
15892                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15893                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15894                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15895                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15896                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15897                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15898                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15899         }
15900 }
15901
15902 #endif