drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  49                                 struct intel_crtc_config *pipe_config);
  50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  51                                     struct intel_crtc_config *pipe_config);
  52
  53 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  54                           int x, int y, struct drm_framebuffer *old_fb);
  55
  56
  57 typedef struct {
  58         int     min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62         int     dot_limit;
  63         int     p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 typedef struct intel_limit intel_limit_t;
  67 struct intel_limit {
  68         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  69         intel_p2_t          p2;
  70 };
  71
  72 /* FDI */
  73 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  74
  75 int
  76 intel_pch_rawclk(struct drm_device *dev)
  77 {
  78         struct drm_i915_private *dev_priv = dev->dev_private;
  79
  80         WARN_ON(!HAS_PCH_SPLIT(dev));
  81
  82         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  83 }
  84
  85 static inline u32 /* units of 100MHz */
  86 intel_fdi_link_freq(struct drm_device *dev)
  87 {
  88         if (IS_GEN5(dev)) {
  89                 struct drm_i915_private *dev_priv = dev->dev_private;
  90                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  91         } else
  92                 return 27;
  93 }
  94
  95 static const intel_limit_t intel_limits_i8xx_dac = {
  96         .dot = { .min = 25000, .max = 350000 },
  97         .vco = { .min = 930000, .max = 1400000 },
  98         .n = { .min = 3, .max = 16 },
  99         .m = { .min = 96, .max = 140 },
 100         .m1 = { .min = 18, .max = 26 },
 101         .m2 = { .min = 6, .max = 16 },
 102         .p = { .min = 4, .max = 128 },
 103         .p1 = { .min = 2, .max = 33 },
 104         .p2 = { .dot_limit = 165000,
 105                 .p2_slow = 4, .p2_fast = 2 },
 106 };
 107
 108 static const intel_limit_t intel_limits_i8xx_dvo = {
 109         .dot = { .min = 25000, .max = 350000 },
 110         .vco = { .min = 930000, .max = 1400000 },
 111         .n = { .min = 3, .max = 16 },
 112         .m = { .min = 96, .max = 140 },
 113         .m1 = { .min = 18, .max = 26 },
 114         .m2 = { .min = 6, .max = 16 },
 115         .p = { .min = 4, .max = 128 },
 116         .p1 = { .min = 2, .max = 33 },
 117         .p2 = { .dot_limit = 165000,
 118                 .p2_slow = 4, .p2_fast = 4 },
 119 };
 120
 121 static const intel_limit_t intel_limits_i8xx_lvds = {
 122         .dot = { .min = 25000, .max = 350000 },
 123         .vco = { .min = 930000, .max = 1400000 },
 124         .n = { .min = 3, .max = 16 },
 125         .m = { .min = 96, .max = 140 },
 126         .m1 = { .min = 18, .max = 26 },
 127         .m2 = { .min = 6, .max = 16 },
 128         .p = { .min = 4, .max = 128 },
 129         .p1 = { .min = 1, .max = 6 },
 130         .p2 = { .dot_limit = 165000,
 131                 .p2_slow = 14, .p2_fast = 7 },
 132 };
 133
 134 static const intel_limit_t intel_limits_i9xx_sdvo = {
 135         .dot = { .min = 20000, .max = 400000 },
 136         .vco = { .min = 1400000, .max = 2800000 },
 137         .n = { .min = 1, .max = 6 },
 138         .m = { .min = 70, .max = 120 },
 139         .m1 = { .min = 8, .max = 18 },
 140         .m2 = { .min = 3, .max = 7 },
 141         .p = { .min = 5, .max = 80 },
 142         .p1 = { .min = 1, .max = 8 },
 143         .p2 = { .dot_limit = 200000,
 144                 .p2_slow = 10, .p2_fast = 5 },
 145 };
 146
 147 static const intel_limit_t intel_limits_i9xx_lvds = {
 148         .dot = { .min = 20000, .max = 400000 },
 149         .vco = { .min = 1400000, .max = 2800000 },
 150         .n = { .min = 1, .max = 6 },
 151         .m = { .min = 70, .max = 120 },
 152         .m1 = { .min = 8, .max = 18 },
 153         .m2 = { .min = 3, .max = 7 },
 154         .p = { .min = 7, .max = 98 },
 155         .p1 = { .min = 1, .max = 8 },
 156         .p2 = { .dot_limit = 112000,
 157                 .p2_slow = 14, .p2_fast = 7 },
 158 };
 159
 160
 161 static const intel_limit_t intel_limits_g4x_sdvo = {
 162         .dot = { .min = 25000, .max = 270000 },
 163         .vco = { .min = 1750000, .max = 3500000},
 164         .n = { .min = 1, .max = 4 },
 165         .m = { .min = 104, .max = 138 },
 166         .m1 = { .min = 17, .max = 23 },
 167         .m2 = { .min = 5, .max = 11 },
 168         .p = { .min = 10, .max = 30 },
 169         .p1 = { .min = 1, .max = 3},
 170         .p2 = { .dot_limit = 270000,
 171                 .p2_slow = 10,
 172                 .p2_fast = 10
 173         },
 174 };
 175
 176 static const intel_limit_t intel_limits_g4x_hdmi = {
 177         .dot = { .min = 22000, .max = 400000 },
 178         .vco = { .min = 1750000, .max = 3500000},
 179         .n = { .min = 1, .max = 4 },
 180         .m = { .min = 104, .max = 138 },
 181         .m1 = { .min = 16, .max = 23 },
 182         .m2 = { .min = 5, .max = 11 },
 183         .p = { .min = 5, .max = 80 },
 184         .p1 = { .min = 1, .max = 8},
 185         .p2 = { .dot_limit = 165000,
 186                 .p2_slow = 10, .p2_fast = 5 },
 187 };
 188
 189 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 190         .dot = { .min = 20000, .max = 115000 },
 191         .vco = { .min = 1750000, .max = 3500000 },
 192         .n = { .min = 1, .max = 3 },
 193         .m = { .min = 104, .max = 138 },
 194         .m1 = { .min = 17, .max = 23 },
 195         .m2 = { .min = 5, .max = 11 },
 196         .p = { .min = 28, .max = 112 },
 197         .p1 = { .min = 2, .max = 8 },
 198         .p2 = { .dot_limit = 0,
 199                 .p2_slow = 14, .p2_fast = 14
 200         },
 201 };
 202
 203 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 204         .dot = { .min = 80000, .max = 224000 },
 205         .vco = { .min = 1750000, .max = 3500000 },
 206         .n = { .min = 1, .max = 3 },
 207         .m = { .min = 104, .max = 138 },
 208         .m1 = { .min = 17, .max = 23 },
 209         .m2 = { .min = 5, .max = 11 },
 210         .p = { .min = 14, .max = 42 },
 211         .p1 = { .min = 2, .max = 6 },
 212         .p2 = { .dot_limit = 0,
 213                 .p2_slow = 7, .p2_fast = 7
 214         },
 215 };
 216
 217 static const intel_limit_t intel_limits_pineview_sdvo = {
 218         .dot = { .min = 20000, .max = 400000},
 219         .vco = { .min = 1700000, .max = 3500000 },
 220         /* Pineview's Ncounter is a ring counter */
 221         .n = { .min = 3, .max = 6 },
 222         .m = { .min = 2, .max = 256 },
 223         /* Pineview only has one combined m divider, which we treat as m2. */
 224         .m1 = { .min = 0, .max = 0 },
 225         .m2 = { .min = 0, .max = 254 },
 226         .p = { .min = 5, .max = 80 },
 227         .p1 = { .min = 1, .max = 8 },
 228         .p2 = { .dot_limit = 200000,
 229                 .p2_slow = 10, .p2_fast = 5 },
 230 };
 231
 232 static const intel_limit_t intel_limits_pineview_lvds = {
 233         .dot = { .min = 20000, .max = 400000 },
 234         .vco = { .min = 1700000, .max = 3500000 },
 235         .n = { .min = 3, .max = 6 },
 236         .m = { .min = 2, .max = 256 },
 237         .m1 = { .min = 0, .max = 0 },
 238         .m2 = { .min = 0, .max = 254 },
 239         .p = { .min = 7, .max = 112 },
 240         .p1 = { .min = 1, .max = 8 },
 241         .p2 = { .dot_limit = 112000,
 242                 .p2_slow = 14, .p2_fast = 14 },
 243 };
 244
 245 /* Ironlake / Sandybridge
 246  *
 247  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 248  * the range value for them is (actual_value - 2).
 249  */
 250 static const intel_limit_t intel_limits_ironlake_dac = {
 251         .dot = { .min = 25000, .max = 350000 },
 252         .vco = { .min = 1760000, .max = 3510000 },
 253         .n = { .min = 1, .max = 5 },
 254         .m = { .min = 79, .max = 127 },
 255         .m1 = { .min = 12, .max = 22 },
 256         .m2 = { .min = 5, .max = 9 },
 257         .p = { .min = 5, .max = 80 },
 258         .p1 = { .min = 1, .max = 8 },
 259         .p2 = { .dot_limit = 225000,
 260                 .p2_slow = 10, .p2_fast = 5 },
 261 };
 262
 263 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 1760000, .max = 3510000 },
 266         .n = { .min = 1, .max = 3 },
 267         .m = { .min = 79, .max = 118 },
 268         .m1 = { .min = 12, .max = 22 },
 269         .m2 = { .min = 5, .max = 9 },
 270         .p = { .min = 28, .max = 112 },
 271         .p1 = { .min = 2, .max = 8 },
 272         .p2 = { .dot_limit = 225000,
 273                 .p2_slow = 14, .p2_fast = 14 },
 274 };
 275
 276 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 1760000, .max = 3510000 },
 279         .n = { .min = 1, .max = 3 },
 280         .m = { .min = 79, .max = 127 },
 281         .m1 = { .min = 12, .max = 22 },
 282         .m2 = { .min = 5, .max = 9 },
 283         .p = { .min = 14, .max = 56 },
 284         .p1 = { .min = 2, .max = 8 },
 285         .p2 = { .dot_limit = 225000,
 286                 .p2_slow = 7, .p2_fast = 7 },
 287 };
 288
 289 /* LVDS 100mhz refclk limits. */
 290 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 291         .dot = { .min = 25000, .max = 350000 },
 292         .vco = { .min = 1760000, .max = 3510000 },
 293         .n = { .min = 1, .max = 2 },
 294         .m = { .min = 79, .max = 126 },
 295         .m1 = { .min = 12, .max = 22 },
 296         .m2 = { .min = 5, .max = 9 },
 297         .p = { .min = 28, .max = 112 },
 298         .p1 = { .min = 2, .max = 8 },
 299         .p2 = { .dot_limit = 225000,
 300                 .p2_slow = 14, .p2_fast = 14 },
 301 };
 302
 303 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 3 },
 307         .m = { .min = 79, .max = 126 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 14, .max = 42 },
 311         .p1 = { .min = 2, .max = 6 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 7, .p2_fast = 7 },
 314 };
 315
 316 static const intel_limit_t intel_limits_vlv_dac = {
 317         .dot = { .min = 25000, .max = 270000 },
 318         .vco = { .min = 4000000, .max = 6000000 },
 319         .n = { .min = 1, .max = 7 },
 320         .m = { .min = 22, .max = 450 }, /* guess */
 321         .m1 = { .min = 2, .max = 3 },
 322         .m2 = { .min = 11, .max = 156 },
 323         .p = { .min = 10, .max = 30 },
 324         .p1 = { .min = 1, .max = 3 },
 325         .p2 = { .dot_limit = 270000,
 326                 .p2_slow = 2, .p2_fast = 20 },
 327 };
 328
 329 static const intel_limit_t intel_limits_vlv_hdmi = {
 330         .dot = { .min = 25000, .max = 270000 },
 331         .vco = { .min = 4000000, .max = 6000000 },
 332         .n = { .min = 1, .max = 7 },
 333         .m = { .min = 60, .max = 300 }, /* guess */
 334         .m1 = { .min = 2, .max = 3 },
 335         .m2 = { .min = 11, .max = 156 },
 336         .p = { .min = 10, .max = 30 },
 337         .p1 = { .min = 2, .max = 3 },
 338         .p2 = { .dot_limit = 270000,
 339                 .p2_slow = 2, .p2_fast = 20 },
 340 };
 341
 342 static const intel_limit_t intel_limits_vlv_dp = {
 343         .dot = { .min = 25000, .max = 270000 },
 344         .vco = { .min = 4000000, .max = 6000000 },
 345         .n = { .min = 1, .max = 7 },
 346         .m = { .min = 22, .max = 450 },
 347         .m1 = { .min = 2, .max = 3 },
 348         .m2 = { .min = 11, .max = 156 },
 349         .p = { .min = 10, .max = 30 },
 350         .p1 = { .min = 1, .max = 3 },
 351         .p2 = { .dot_limit = 270000,
 352                 .p2_slow = 2, .p2_fast = 20 },
 353 };
 354
 355 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 356                                                 int refclk)
 357 {
 358         struct drm_device *dev = crtc->dev;
 359         const intel_limit_t *limit;
 360
 361         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 362                 if (intel_is_dual_link_lvds(dev)) {
 363                         if (refclk == 100000)
 364                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 365                         else
 366                                 limit = &intel_limits_ironlake_dual_lvds;
 367                 } else {
 368                         if (refclk == 100000)
 369                                 limit = &intel_limits_ironlake_single_lvds_100m;
 370                         else
 371                                 limit = &intel_limits_ironlake_single_lvds;
 372                 }
 373         } else
 374                 limit = &intel_limits_ironlake_dac;
 375
 376         return limit;
 377 }
 378
 379 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 380 {
 381         struct drm_device *dev = crtc->dev;
 382         const intel_limit_t *limit;
 383
 384         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 385                 if (intel_is_dual_link_lvds(dev))
 386                         limit = &intel_limits_g4x_dual_channel_lvds;
 387                 else
 388                         limit = &intel_limits_g4x_single_channel_lvds;
 389         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 390                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 391                 limit = &intel_limits_g4x_hdmi;
 392         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 393                 limit = &intel_limits_g4x_sdvo;
 394         } else /* The option is for other outputs */
 395                 limit = &intel_limits_i9xx_sdvo;
 396
 397         return limit;
 398 }
 399
 400 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 401 {
 402         struct drm_device *dev = crtc->dev;
 403         const intel_limit_t *limit;
 404
 405         if (HAS_PCH_SPLIT(dev))
 406                 limit = intel_ironlake_limit(crtc, refclk);
 407         else if (IS_G4X(dev)) {
 408                 limit = intel_g4x_limit(crtc);
 409         } else if (IS_PINEVIEW(dev)) {
 410                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 411                         limit = &intel_limits_pineview_lvds;
 412                 else
 413                         limit = &intel_limits_pineview_sdvo;
 414         } else if (IS_VALLEYVIEW(dev)) {
 415                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 416                         limit = &intel_limits_vlv_dac;
 417                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 418                         limit = &intel_limits_vlv_hdmi;
 419                 else
 420                         limit = &intel_limits_vlv_dp;
 421         } else if (!IS_GEN2(dev)) {
 422                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 423                         limit = &intel_limits_i9xx_lvds;
 424                 else
 425                         limit = &intel_limits_i9xx_sdvo;
 426         } else {
 427                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 428                         limit = &intel_limits_i8xx_lvds;
 429                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 430                         limit = &intel_limits_i8xx_dvo;
 431                 else
 432                         limit = &intel_limits_i8xx_dac;
 433         }
 434         return limit;
 435 }
 436
 437 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 438 static void pineview_clock(int refclk, intel_clock_t *clock)
 439 {
 440         clock->m = clock->m2 + 2;
 441         clock->p = clock->p1 * clock->p2;
 442         clock->vco = refclk * clock->m / clock->n;
 443         clock->dot = clock->vco / clock->p;
 444 }
 445
 446 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 447 {
 448         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 449 }
 450
 451 static void i9xx_clock(int refclk, intel_clock_t *clock)
 452 {
 453         clock->m = i9xx_dpll_compute_m(clock);
 454         clock->p = clock->p1 * clock->p2;
 455         clock->vco = refclk * clock->m / (clock->n + 2);
 456         clock->dot = clock->vco / clock->p;
 457 }
 458
 459 /**
 460  * Returns whether any output on the specified pipe is of the specified type
 461  */
 462 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 463 {
 464         struct drm_device *dev = crtc->dev;
 465         struct intel_encoder *encoder;
 466
 467         for_each_encoder_on_crtc(dev, crtc, encoder)
 468                 if (encoder->type == type)
 469                         return true;
 470
 471         return false;
 472 }
 473
 474 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 475 /**
 476  * Returns whether the given set of divisors are valid for a given refclk with
 477  * the given connectors.
 478  */
 479
 480 static bool intel_PLL_is_valid(struct drm_device *dev,
 481                                const intel_limit_t *limit,
 482                                const intel_clock_t *clock)
 483 {
 484         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 485                 INTELPllInvalid("p1 out of range\n");
 486         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 487                 INTELPllInvalid("p out of range\n");
 488         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 489                 INTELPllInvalid("m2 out of range\n");
 490         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 491                 INTELPllInvalid("m1 out of range\n");
 492         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 493                 INTELPllInvalid("m1 <= m2\n");
 494         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 495                 INTELPllInvalid("m out of range\n");
 496         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 497                 INTELPllInvalid("n out of range\n");
 498         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 499                 INTELPllInvalid("vco out of range\n");
 500         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 501          * connector, etc., rather than just a single range.
 502          */
 503         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 504                 INTELPllInvalid("dot out of range\n");
 505
 506         return true;
 507 }
 508
 509 static bool
 510 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 511                     int target, int refclk, intel_clock_t *match_clock,
 512                     intel_clock_t *best_clock)
 513 {
 514         struct drm_device *dev = crtc->dev;
 515         intel_clock_t clock;
 516         int err = target;
 517
 518         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 519                 /*
 520                  * For LVDS just rely on its current settings for dual-channel.
 521                  * We haven't figured out how to reliably set up different
 522                  * single/dual channel state, if we even can.
 523                  */
 524                 if (intel_is_dual_link_lvds(dev))
 525                         clock.p2 = limit->p2.p2_fast;
 526                 else
 527                         clock.p2 = limit->p2.p2_slow;
 528         } else {
 529                 if (target < limit->p2.dot_limit)
 530                         clock.p2 = limit->p2.p2_slow;
 531                 else
 532                         clock.p2 = limit->p2.p2_fast;
 533         }
 534
 535         memset(best_clock, 0, sizeof(*best_clock));
 536
 537         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 538              clock.m1++) {
 539                 for (clock.m2 = limit->m2.min;
 540                      clock.m2 <= limit->m2.max; clock.m2++) {
 541                         if (clock.m2 >= clock.m1)
 542                                 break;
 543                         for (clock.n = limit->n.min;
 544                              clock.n <= limit->n.max; clock.n++) {
 545                                 for (clock.p1 = limit->p1.min;
 546                                         clock.p1 <= limit->p1.max; clock.p1++) {
 547                                         int this_err;
 548
 549                                         i9xx_clock(refclk, &clock);
 550                                         if (!intel_PLL_is_valid(dev, limit,
 551                                                                 &clock))
 552                                                 continue;
 553                                         if (match_clock &&
 554                                             clock.p != match_clock->p)
 555                                                 continue;
 556
 557                                         this_err = abs(clock.dot - target);
 558                                         if (this_err < err) {
 559                                                 *best_clock = clock;
 560                                                 err = this_err;
 561                                         }
 562                                 }
 563                         }
 564                 }
 565         }
 566
 567         return (err != target);
 568 }
 569
 570 static bool
 571 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 572                    int target, int refclk, intel_clock_t *match_clock,
 573                    intel_clock_t *best_clock)
 574 {
 575         struct drm_device *dev = crtc->dev;
 576         intel_clock_t clock;
 577         int err = target;
 578
 579         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 580                 /*
 581                  * For LVDS just rely on its current settings for dual-channel.
 582                  * We haven't figured out how to reliably set up different
 583                  * single/dual channel state, if we even can.
 584                  */
 585                 if (intel_is_dual_link_lvds(dev))
 586                         clock.p2 = limit->p2.p2_fast;
 587                 else
 588                         clock.p2 = limit->p2.p2_slow;
 589         } else {
 590                 if (target < limit->p2.dot_limit)
 591                         clock.p2 = limit->p2.p2_slow;
 592                 else
 593                         clock.p2 = limit->p2.p2_fast;
 594         }
 595
 596         memset(best_clock, 0, sizeof(*best_clock));
 597
 598         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 599              clock.m1++) {
 600                 for (clock.m2 = limit->m2.min;
 601                      clock.m2 <= limit->m2.max; clock.m2++) {
 602                         for (clock.n = limit->n.min;
 603                              clock.n <= limit->n.max; clock.n++) {
 604                                 for (clock.p1 = limit->p1.min;
 605                                         clock.p1 <= limit->p1.max; clock.p1++) {
 606                                         int this_err;
 607
 608                                         pineview_clock(refclk, &clock);
 609                                         if (!intel_PLL_is_valid(dev, limit,
 610                                                                 &clock))
 611                                                 continue;
 612                                         if (match_clock &&
 613                                             clock.p != match_clock->p)
 614                                                 continue;
 615
 616                                         this_err = abs(clock.dot - target);
 617                                         if (this_err < err) {
 618                                                 *best_clock = clock;
 619                                                 err = this_err;
 620                                         }
 621                                 }
 622                         }
 623                 }
 624         }
 625
 626         return (err != target);
 627 }
 628
 629 static bool
 630 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 631                    int target, int refclk, intel_clock_t *match_clock,
 632                    intel_clock_t *best_clock)
 633 {
 634         struct drm_device *dev = crtc->dev;
 635         intel_clock_t clock;
 636         int max_n;
 637         bool found;
 638         /* approximately equals target * 0.00585 */
 639         int err_most = (target >> 8) + (target >> 9);
 640         found = false;
 641
 642         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 643                 if (intel_is_dual_link_lvds(dev))
 644                         clock.p2 = limit->p2.p2_fast;
 645                 else
 646                         clock.p2 = limit->p2.p2_slow;
 647         } else {
 648                 if (target < limit->p2.dot_limit)
 649                         clock.p2 = limit->p2.p2_slow;
 650                 else
 651                         clock.p2 = limit->p2.p2_fast;
 652         }
 653
 654         memset(best_clock, 0, sizeof(*best_clock));
 655         max_n = limit->n.max;
 656         /* based on hardware requirement, prefer smaller n to precision */
 657         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 658                 /* based on hardware requirement, prefere larger m1,m2 */
 659                 for (clock.m1 = limit->m1.max;
 660                      clock.m1 >= limit->m1.min; clock.m1--) {
 661                         for (clock.m2 = limit->m2.max;
 662                              clock.m2 >= limit->m2.min; clock.m2--) {
 663                                 for (clock.p1 = limit->p1.max;
 664                                      clock.p1 >= limit->p1.min; clock.p1--) {
 665                                         int this_err;
 666
 667                                         i9xx_clock(refclk, &clock);
 668                                         if (!intel_PLL_is_valid(dev, limit,
 669                                                                 &clock))
 670                                                 continue;
 671
 672                                         this_err = abs(clock.dot - target);
 673                                         if (this_err < err_most) {
 674                                                 *best_clock = clock;
 675                                                 err_most = this_err;
 676                                                 max_n = clock.n;
 677                                                 found = true;
 678                                         }
 679                                 }
 680                         }
 681                 }
 682         }
 683         return found;
 684 }
 685
 686 static bool
 687 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 688                    int target, int refclk, intel_clock_t *match_clock,
 689                    intel_clock_t *best_clock)
 690 {
 691         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 692         u32 m, n, fastclk;
 693         u32 updrate, minupdate, p;
 694         unsigned long bestppm, ppm, absppm;
 695         int dotclk, flag;
 696
 697         flag = 0;
 698         dotclk = target * 1000;
 699         bestppm = 1000000;
 700         ppm = absppm = 0;
 701         fastclk = dotclk / (2*100);
 702         updrate = 0;
 703         minupdate = 19200;
 704         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 705         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 706
 707         /* based on hardware requirement, prefer smaller n to precision */
 708         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 709                 updrate = refclk / n;
 710                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 711                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 712                                 if (p2 > 10)
 713                                         p2 = p2 - 1;
 714                                 p = p1 * p2;
 715                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 716                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 717                                         m2 = (((2*(fastclk * p * n / m1 )) +
 718                                                refclk) / (2*refclk));
 719                                         m = m1 * m2;
 720                                         vco = updrate * m;
 721                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 722                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 723                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 724                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 725                                                         bestppm = 0;
 726                                                         flag = 1;
 727                                                 }
 728                                                 if (absppm < bestppm - 10) {
 729                                                         bestppm = absppm;
 730                                                         flag = 1;
 731                                                 }
 732                                                 if (flag) {
 733                                                         bestn = n;
 734                                                         bestm1 = m1;
 735                                                         bestm2 = m2;
 736                                                         bestp1 = p1;
 737                                                         bestp2 = p2;
 738                                                         flag = 0;
 739                                                 }
 740                                         }
 741                                 }
 742                         }
 743                 }
 744         }
 745         best_clock->n = bestn;
 746         best_clock->m1 = bestm1;
 747         best_clock->m2 = bestm2;
 748         best_clock->p1 = bestp1;
 749         best_clock->p2 = bestp2;
 750
 751         return true;
 752 }
 753
 754 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 755                                              enum pipe pipe)
 756 {
 757         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 759
 760         return intel_crtc->config.cpu_transcoder;
 761 }
 762
 763 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 764 {
 765         struct drm_i915_private *dev_priv = dev->dev_private;
 766         u32 frame, frame_reg = PIPEFRAME(pipe);
 767
 768         frame = I915_READ(frame_reg);
 769
 770         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 771                 DRM_DEBUG_KMS("vblank wait timed out\n");
 772 }
 773
 774 /**
 775  * intel_wait_for_vblank - wait for vblank on a given pipe
 776  * @dev: drm device
 777  * @pipe: pipe to wait for
 778  *
 779  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 780  * mode setting code.
 781  */
 782 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 783 {
 784         struct drm_i915_private *dev_priv = dev->dev_private;
 785         int pipestat_reg = PIPESTAT(pipe);
 786
 787         if (INTEL_INFO(dev)->gen >= 5) {
 788                 ironlake_wait_for_vblank(dev, pipe);
 789                 return;
 790         }
 791
 792         /* Clear existing vblank status. Note this will clear any other
 793          * sticky status fields as well.
 794          *
 795          * This races with i915_driver_irq_handler() with the result
 796          * that either function could miss a vblank event.  Here it is not
 797          * fatal, as we will either wait upon the next vblank interrupt or
 798          * timeout.  Generally speaking intel_wait_for_vblank() is only
 799          * called during modeset at which time the GPU should be idle and
 800          * should *not* be performing page flips and thus not waiting on
 801          * vblanks...
 802          * Currently, the result of us stealing a vblank from the irq
 803          * handler is that a single frame will be skipped during swapbuffers.
 804          */
 805         I915_WRITE(pipestat_reg,
 806                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 807
 808         /* Wait for vblank interrupt bit to set */
 809         if (wait_for(I915_READ(pipestat_reg) &
 810                      PIPE_VBLANK_INTERRUPT_STATUS,
 811                      50))
 812                 DRM_DEBUG_KMS("vblank wait timed out\n");
 813 }
 814
 815 /*
 816  * intel_wait_for_pipe_off - wait for pipe to turn off
 817  * @dev: drm device
 818  * @pipe: pipe to wait for
 819  *
 820  * After disabling a pipe, we can't wait for vblank in the usual way,
 821  * spinning on the vblank interrupt status bit, since we won't actually
 822  * see an interrupt when the pipe is disabled.
 823  *
 824  * On Gen4 and above:
 825  *   wait for the pipe register state bit to turn off
 826  *
 827  * Otherwise:
 828  *   wait for the display line value to settle (it usually
 829  *   ends up stopping at the start of the next frame).
 830  *
 831  */
 832 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 833 {
 834         struct drm_i915_private *dev_priv = dev->dev_private;
 835         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 836                                                                       pipe);
 837
 838         if (INTEL_INFO(dev)->gen >= 4) {
 839                 int reg = PIPECONF(cpu_transcoder);
 840
 841                 /* Wait for the Pipe State to go off */
 842                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 843                              100))
 844                         WARN(1, "pipe_off wait timed out\n");
 845         } else {
 846                 u32 last_line, line_mask;
 847                 int reg = PIPEDSL(pipe);
 848                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 849
 850                 if (IS_GEN2(dev))
 851                         line_mask = DSL_LINEMASK_GEN2;
 852                 else
 853                         line_mask = DSL_LINEMASK_GEN3;
 854
 855                 /* Wait for the display line to settle */
 856                 do {
 857                         last_line = I915_READ(reg) & line_mask;
 858                         mdelay(5);
 859                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 860                          time_after(timeout, jiffies));
 861                 if (time_after(jiffies, timeout))
 862                         WARN(1, "pipe_off wait timed out\n");
 863         }
 864 }
 865
 866 /*
 867  * ibx_digital_port_connected - is the specified port connected?
 868  * @dev_priv: i915 private structure
 869  * @port: the port to test
 870  *
 871  * Returns true if @port is connected, false otherwise.
 872  */
 873 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 874                                 struct intel_digital_port *port)
 875 {
 876         u32 bit;
 877
 878         if (HAS_PCH_IBX(dev_priv->dev)) {
 879                 switch(port->port) {
 880                 case PORT_B:
 881                         bit = SDE_PORTB_HOTPLUG;
 882                         break;
 883                 case PORT_C:
 884                         bit = SDE_PORTC_HOTPLUG;
 885                         break;
 886                 case PORT_D:
 887                         bit = SDE_PORTD_HOTPLUG;
 888                         break;
 889                 default:
 890                         return true;
 891                 }
 892         } else {
 893                 switch(port->port) {
 894                 case PORT_B:
 895                         bit = SDE_PORTB_HOTPLUG_CPT;
 896                         break;
 897                 case PORT_C:
 898                         bit = SDE_PORTC_HOTPLUG_CPT;
 899                         break;
 900                 case PORT_D:
 901                         bit = SDE_PORTD_HOTPLUG_CPT;
 902                         break;
 903                 default:
 904                         return true;
 905                 }
 906         }
 907
 908         return I915_READ(SDEISR) & bit;
 909 }
 910
 911 static const char *state_string(bool enabled)
 912 {
 913         return enabled ? "on" : "off";
 914 }
 915
 916 /* Only for pre-ILK configs */
 917 void assert_pll(struct drm_i915_private *dev_priv,
 918                 enum pipe pipe, bool state)
 919 {
 920         int reg;
 921         u32 val;
 922         bool cur_state;
 923
 924         reg = DPLL(pipe);
 925         val = I915_READ(reg);
 926         cur_state = !!(val & DPLL_VCO_ENABLE);
 927         WARN(cur_state != state,
 928              "PLL state assertion failure (expected %s, current %s)\n",
 929              state_string(state), state_string(cur_state));
 930 }
 931
 932 struct intel_shared_dpll *
 933 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 934 {
 935         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 936
 937         if (crtc->config.shared_dpll < 0)
 938                 return NULL;
 939
 940         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 941 }
 942
 943 /* For ILK+ */
 944 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 945                         struct intel_shared_dpll *pll,
 946                         bool state)
 947 {
 948         bool cur_state;
 949         struct intel_dpll_hw_state hw_state;
 950
 951         if (HAS_PCH_LPT(dev_priv->dev)) {
 952                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 953                 return;
 954         }
 955
 956         if (WARN (!pll,
 957                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 958                 return;
 959
 960         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 961         WARN(cur_state != state,
 962              "%s assertion failure (expected %s, current %s)\n",
 963              pll->name, state_string(state), state_string(cur_state));
 964 }
 965
 966 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 967                           enum pipe pipe, bool state)
 968 {
 969         int reg;
 970         u32 val;
 971         bool cur_state;
 972         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 973                                                                       pipe);
 974
 975         if (HAS_DDI(dev_priv->dev)) {
 976                 /* DDI does not have a specific FDI_TX register */
 977                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 978                 val = I915_READ(reg);
 979                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 980         } else {
 981                 reg = FDI_TX_CTL(pipe);
 982                 val = I915_READ(reg);
 983                 cur_state = !!(val & FDI_TX_ENABLE);
 984         }
 985         WARN(cur_state != state,
 986              "FDI TX state assertion failure (expected %s, current %s)\n",
 987              state_string(state), state_string(cur_state));
 988 }
 989 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 990 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 991
 992 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 993                           enum pipe pipe, bool state)
 994 {
 995         int reg;
 996         u32 val;
 997         bool cur_state;
 998
 999         reg = FDI_RX_CTL(pipe);
1000         val = I915_READ(reg);
1001         cur_state = !!(val & FDI_RX_ENABLE);
1002         WARN(cur_state != state,
1003              "FDI RX state assertion failure (expected %s, current %s)\n",
1004              state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1007 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1008
1009 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1010                                       enum pipe pipe)
1011 {
1012         int reg;
1013         u32 val;
1014
1015         /* ILK FDI PLL is always enabled */
1016         if (dev_priv->info->gen == 5)
1017                 return;
1018
1019         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1020         if (HAS_DDI(dev_priv->dev))
1021                 return;
1022
1023         reg = FDI_TX_CTL(pipe);
1024         val = I915_READ(reg);
1025         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1026 }
1027
1028 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1029                        enum pipe pipe, bool state)
1030 {
1031         int reg;
1032         u32 val;
1033         bool cur_state;
1034
1035         reg = FDI_RX_CTL(pipe);
1036         val = I915_READ(reg);
1037         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1038         WARN(cur_state != state,
1039              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1040              state_string(state), state_string(cur_state));
1041 }
1042
1043 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1044                                   enum pipe pipe)
1045 {
1046         int pp_reg, lvds_reg;
1047         u32 val;
1048         enum pipe panel_pipe = PIPE_A;
1049         bool locked = true;
1050
1051         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1052                 pp_reg = PCH_PP_CONTROL;
1053                 lvds_reg = PCH_LVDS;
1054         } else {
1055                 pp_reg = PP_CONTROL;
1056                 lvds_reg = LVDS;
1057         }
1058
1059         val = I915_READ(pp_reg);
1060         if (!(val & PANEL_POWER_ON) ||
1061             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1062                 locked = false;
1063
1064         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1065                 panel_pipe = PIPE_B;
1066
1067         WARN(panel_pipe == pipe && locked,
1068              "panel assertion failure, pipe %c regs locked\n",
1069              pipe_name(pipe));
1070 }
1071
1072 void assert_pipe(struct drm_i915_private *dev_priv,
1073                  enum pipe pipe, bool state)
1074 {
1075         int reg;
1076         u32 val;
1077         bool cur_state;
1078         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1079                                                                       pipe);
1080
1081         /* if we need the pipe A quirk it must be always on */
1082         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1083                 state = true;
1084
1085         if (!intel_display_power_enabled(dev_priv->dev,
1086                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1087                 cur_state = false;
1088         } else {
1089                 reg = PIPECONF(cpu_transcoder);
1090                 val = I915_READ(reg);
1091                 cur_state = !!(val & PIPECONF_ENABLE);
1092         }
1093
1094         WARN(cur_state != state,
1095              "pipe %c assertion failure (expected %s, current %s)\n",
1096              pipe_name(pipe), state_string(state), state_string(cur_state));
1097 }
1098
1099 static void assert_plane(struct drm_i915_private *dev_priv,
1100                          enum plane plane, bool state)
1101 {
1102         int reg;
1103         u32 val;
1104         bool cur_state;
1105
1106         reg = DSPCNTR(plane);
1107         val = I915_READ(reg);
1108         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1109         WARN(cur_state != state,
1110              "plane %c assertion failure (expected %s, current %s)\n",
1111              plane_name(plane), state_string(state), state_string(cur_state));
1112 }
1113
1114 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1115 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1116
1117 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1118                                    enum pipe pipe)
1119 {
1120         struct drm_device *dev = dev_priv->dev;
1121         int reg, i;
1122         u32 val;
1123         int cur_pipe;
1124
1125         /* Primary planes are fixed to pipes on gen4+ */
1126         if (INTEL_INFO(dev)->gen >= 4) {
1127                 reg = DSPCNTR(pipe);
1128                 val = I915_READ(reg);
1129                 WARN((val & DISPLAY_PLANE_ENABLE),
1130                      "plane %c assertion failure, should be disabled but not\n",
1131                      plane_name(pipe));
1132                 return;
1133         }
1134
1135         /* Need to check both planes against the pipe */
1136         for_each_pipe(i) {
1137                 reg = DSPCNTR(i);
1138                 val = I915_READ(reg);
1139                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1140                         DISPPLANE_SEL_PIPE_SHIFT;
1141                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1142                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1143                      plane_name(i), pipe_name(pipe));
1144         }
1145 }
1146
1147 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1148                                     enum pipe pipe)
1149 {
1150         struct drm_device *dev = dev_priv->dev;
1151         int reg, i;
1152         u32 val;
1153
1154         if (IS_VALLEYVIEW(dev)) {
1155                 for (i = 0; i < dev_priv->num_plane; i++) {
1156                         reg = SPCNTR(pipe, i);
1157                         val = I915_READ(reg);
1158                         WARN((val & SP_ENABLE),
1159                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1160                              sprite_name(pipe, i), pipe_name(pipe));
1161                 }
1162         } else if (INTEL_INFO(dev)->gen >= 7) {
1163                 reg = SPRCTL(pipe);
1164                 val = I915_READ(reg);
1165                 WARN((val & SPRITE_ENABLE),
1166                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1167                      plane_name(pipe), pipe_name(pipe));
1168         } else if (INTEL_INFO(dev)->gen >= 5) {
1169                 reg = DVSCNTR(pipe);
1170                 val = I915_READ(reg);
1171                 WARN((val & DVS_ENABLE),
1172                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1173                      plane_name(pipe), pipe_name(pipe));
1174         }
1175 }
1176
1177 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1178 {
1179         u32 val;
1180         bool enabled;
1181
1182         if (HAS_PCH_LPT(dev_priv->dev)) {
1183                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1184                 return;
1185         }
1186
1187         val = I915_READ(PCH_DREF_CONTROL);
1188         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1189                             DREF_SUPERSPREAD_SOURCE_MASK));
1190         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1191 }
1192
1193 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1194                                            enum pipe pipe)
1195 {
1196         int reg;
1197         u32 val;
1198         bool enabled;
1199
1200         reg = PCH_TRANSCONF(pipe);
1201         val = I915_READ(reg);
1202         enabled = !!(val & TRANS_ENABLE);
1203         WARN(enabled,
1204              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1205              pipe_name(pipe));
1206 }
1207
1208 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1209                             enum pipe pipe, u32 port_sel, u32 val)
1210 {
1211         if ((val & DP_PORT_EN) == 0)
1212                 return false;
1213
1214         if (HAS_PCH_CPT(dev_priv->dev)) {
1215                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1216                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1217                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1218                         return false;
1219         } else {
1220                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1221                         return false;
1222         }
1223         return true;
1224 }
1225
1226 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1227                               enum pipe pipe, u32 val)
1228 {
1229         if ((val & SDVO_ENABLE) == 0)
1230                 return false;
1231
1232         if (HAS_PCH_CPT(dev_priv->dev)) {
1233                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1234                         return false;
1235         } else {
1236                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1237                         return false;
1238         }
1239         return true;
1240 }
1241
1242 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1243                               enum pipe pipe, u32 val)
1244 {
1245         if ((val & LVDS_PORT_EN) == 0)
1246                 return false;
1247
1248         if (HAS_PCH_CPT(dev_priv->dev)) {
1249                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1250                         return false;
1251         } else {
1252                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1253                         return false;
1254         }
1255         return true;
1256 }
1257
1258 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1259                               enum pipe pipe, u32 val)
1260 {
1261         if ((val & ADPA_DAC_ENABLE) == 0)
1262                 return false;
1263         if (HAS_PCH_CPT(dev_priv->dev)) {
1264                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1265                         return false;
1266         } else {
1267                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1268                         return false;
1269         }
1270         return true;
1271 }
1272
1273 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1274                                    enum pipe pipe, int reg, u32 port_sel)
1275 {
1276         u32 val = I915_READ(reg);
1277         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1278              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1279              reg, pipe_name(pipe));
1280
1281         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1282              && (val & DP_PIPEB_SELECT),
1283              "IBX PCH dp port still using transcoder B\n");
1284 }
1285
1286 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1287                                      enum pipe pipe, int reg)
1288 {
1289         u32 val = I915_READ(reg);
1290         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1291              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1292              reg, pipe_name(pipe));
1293
1294         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1295              && (val & SDVO_PIPE_B_SELECT),
1296              "IBX PCH hdmi port still using transcoder B\n");
1297 }
1298
1299 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1300                                       enum pipe pipe)
1301 {
1302         int reg;
1303         u32 val;
1304
1305         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1306         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1307         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1308
1309         reg = PCH_ADPA;
1310         val = I915_READ(reg);
1311         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1312              "PCH VGA enabled on transcoder %c, should be disabled\n",
1313              pipe_name(pipe));
1314
1315         reg = PCH_LVDS;
1316         val = I915_READ(reg);
1317         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1318              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1319              pipe_name(pipe));
1320
1321         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1322         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1323         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1324 }
1325
1326 static void vlv_enable_pll(struct intel_crtc *crtc)
1327 {
1328         struct drm_device *dev = crtc->base.dev;
1329         struct drm_i915_private *dev_priv = dev->dev_private;
1330         int reg = DPLL(crtc->pipe);
1331         u32 dpll = crtc->config.dpll_hw_state.dpll;
1332
1333         assert_pipe_disabled(dev_priv, crtc->pipe);
1334
1335         /* No really, not for ILK+ */
1336         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1337
1338         /* PLL is protected by panel, make sure we can write it */
1339         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1340                 assert_panel_unlocked(dev_priv, crtc->pipe);
1341
1342         I915_WRITE(reg, dpll);
1343         POSTING_READ(reg);
1344         udelay(150);
1345
1346         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1347                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1348
1349         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1350         POSTING_READ(DPLL_MD(crtc->pipe));
1351
1352         /* We do this three times for luck */
1353         I915_WRITE(reg, dpll);
1354         POSTING_READ(reg);
1355         udelay(150); /* wait for warmup */
1356         I915_WRITE(reg, dpll);
1357         POSTING_READ(reg);
1358         udelay(150); /* wait for warmup */
1359         I915_WRITE(reg, dpll);
1360         POSTING_READ(reg);
1361         udelay(150); /* wait for warmup */
1362 }
1363
1364 static void i9xx_enable_pll(struct intel_crtc *crtc)
1365 {
1366         struct drm_device *dev = crtc->base.dev;
1367         struct drm_i915_private *dev_priv = dev->dev_private;
1368         int reg = DPLL(crtc->pipe);
1369         u32 dpll = crtc->config.dpll_hw_state.dpll;
1370
1371         assert_pipe_disabled(dev_priv, crtc->pipe);
1372
1373         /* No really, not for ILK+ */
1374         BUG_ON(dev_priv->info->gen >= 5);
1375
1376         /* PLL is protected by panel, make sure we can write it */
1377         if (IS_MOBILE(dev) && !IS_I830(dev))
1378                 assert_panel_unlocked(dev_priv, crtc->pipe);
1379
1380         I915_WRITE(reg, dpll);
1381
1382         /* Wait for the clocks to stabilize. */
1383         POSTING_READ(reg);
1384         udelay(150);
1385
1386         if (INTEL_INFO(dev)->gen >= 4) {
1387                 I915_WRITE(DPLL_MD(crtc->pipe),
1388                            crtc->config.dpll_hw_state.dpll_md);
1389         } else {
1390                 /* The pixel multiplier can only be updated once the
1391                  * DPLL is enabled and the clocks are stable.
1392                  *
1393                  * So write it again.
1394                  */
1395                 I915_WRITE(reg, dpll);
1396         }
1397
1398         /* We do this three times for luck */
1399         I915_WRITE(reg, dpll);
1400         POSTING_READ(reg);
1401         udelay(150); /* wait for warmup */
1402         I915_WRITE(reg, dpll);
1403         POSTING_READ(reg);
1404         udelay(150); /* wait for warmup */
1405         I915_WRITE(reg, dpll);
1406         POSTING_READ(reg);
1407         udelay(150); /* wait for warmup */
1408 }
1409
1410 /**
1411  * i9xx_disable_pll - disable a PLL
1412  * @dev_priv: i915 private structure
1413  * @pipe: pipe PLL to disable
1414  *
1415  * Disable the PLL for @pipe, making sure the pipe is off first.
1416  *
1417  * Note!  This is for pre-ILK only.
1418  */
1419 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1420 {
1421         /* Don't disable pipe A or pipe A PLLs if needed */
1422         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1423                 return;
1424
1425         /* Make sure the pipe isn't still relying on us */
1426         assert_pipe_disabled(dev_priv, pipe);
1427
1428         I915_WRITE(DPLL(pipe), 0);
1429         POSTING_READ(DPLL(pipe));
1430 }
1431
1432 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1433 {
1434         u32 port_mask;
1435
1436         if (!port)
1437                 port_mask = DPLL_PORTB_READY_MASK;
1438         else
1439                 port_mask = DPLL_PORTC_READY_MASK;
1440
1441         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1442                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1443                      'B' + port, I915_READ(DPLL(0)));
1444 }
1445
1446 /**
1447  * ironlake_enable_shared_dpll - enable PCH PLL
1448  * @dev_priv: i915 private structure
1449  * @pipe: pipe PLL to enable
1450  *
1451  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1452  * drives the transcoder clock.
1453  */
1454 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1455 {
1456         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1457         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1458
1459         /* PCH PLLs only available on ILK, SNB and IVB */
1460         BUG_ON(dev_priv->info->gen < 5);
1461         if (WARN_ON(pll == NULL))
1462                 return;
1463
1464         if (WARN_ON(pll->refcount == 0))
1465                 return;
1466
1467         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1468                       pll->name, pll->active, pll->on,
1469                       crtc->base.base.id);
1470
1471         if (pll->active++) {
1472                 WARN_ON(!pll->on);
1473                 assert_shared_dpll_enabled(dev_priv, pll);
1474                 return;
1475         }
1476         WARN_ON(pll->on);
1477
1478         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1479         pll->enable(dev_priv, pll);
1480         pll->on = true;
1481 }
1482
1483 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1484 {
1485         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1486         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1487
1488         /* PCH only available on ILK+ */
1489         BUG_ON(dev_priv->info->gen < 5);
1490         if (WARN_ON(pll == NULL))
1491                return;
1492
1493         if (WARN_ON(pll->refcount == 0))
1494                 return;
1495
1496         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1497                       pll->name, pll->active, pll->on,
1498                       crtc->base.base.id);
1499
1500         if (WARN_ON(pll->active == 0)) {
1501                 assert_shared_dpll_disabled(dev_priv, pll);
1502                 return;
1503         }
1504
1505         assert_shared_dpll_enabled(dev_priv, pll);
1506         WARN_ON(!pll->on);
1507         if (--pll->active)
1508                 return;
1509
1510         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1511         pll->disable(dev_priv, pll);
1512         pll->on = false;
1513 }
1514
1515 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1516                                            enum pipe pipe)
1517 {
1518         struct drm_device *dev = dev_priv->dev;
1519         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1521         uint32_t reg, val, pipeconf_val;
1522
1523         /* PCH only available on ILK+ */
1524         BUG_ON(dev_priv->info->gen < 5);
1525
1526         /* Make sure PCH DPLL is enabled */
1527         assert_shared_dpll_enabled(dev_priv,
1528                                    intel_crtc_to_shared_dpll(intel_crtc));
1529
1530         /* FDI must be feeding us bits for PCH ports */
1531         assert_fdi_tx_enabled(dev_priv, pipe);
1532         assert_fdi_rx_enabled(dev_priv, pipe);
1533
1534         if (HAS_PCH_CPT(dev)) {
1535                 /* Workaround: Set the timing override bit before enabling the
1536                  * pch transcoder. */
1537                 reg = TRANS_CHICKEN2(pipe);
1538                 val = I915_READ(reg);
1539                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1540                 I915_WRITE(reg, val);
1541         }
1542
1543         reg = PCH_TRANSCONF(pipe);
1544         val = I915_READ(reg);
1545         pipeconf_val = I915_READ(PIPECONF(pipe));
1546
1547         if (HAS_PCH_IBX(dev_priv->dev)) {
1548                 /*
1549                  * make the BPC in transcoder be consistent with
1550                  * that in pipeconf reg.
1551                  */
1552                 val &= ~PIPECONF_BPC_MASK;
1553                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1554         }
1555
1556         val &= ~TRANS_INTERLACE_MASK;
1557         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1558                 if (HAS_PCH_IBX(dev_priv->dev) &&
1559                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1560                         val |= TRANS_LEGACY_INTERLACED_ILK;
1561                 else
1562                         val |= TRANS_INTERLACED;
1563         else
1564                 val |= TRANS_PROGRESSIVE;
1565
1566         I915_WRITE(reg, val | TRANS_ENABLE);
1567         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1568                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1569 }
1570
1571 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1572                                       enum transcoder cpu_transcoder)
1573 {
1574         u32 val, pipeconf_val;
1575
1576         /* PCH only available on ILK+ */
1577         BUG_ON(dev_priv->info->gen < 5);
1578
1579         /* FDI must be feeding us bits for PCH ports */
1580         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1581         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1582
1583         /* Workaround: set timing override bit. */
1584         val = I915_READ(_TRANSA_CHICKEN2);
1585         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1586         I915_WRITE(_TRANSA_CHICKEN2, val);
1587
1588         val = TRANS_ENABLE;
1589         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1590
1591         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1592             PIPECONF_INTERLACED_ILK)
1593                 val |= TRANS_INTERLACED;
1594         else
1595                 val |= TRANS_PROGRESSIVE;
1596
1597         I915_WRITE(LPT_TRANSCONF, val);
1598         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1599                 DRM_ERROR("Failed to enable PCH transcoder\n");
1600 }
1601
1602 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1603                                             enum pipe pipe)
1604 {
1605         struct drm_device *dev = dev_priv->dev;
1606         uint32_t reg, val;
1607
1608         /* FDI relies on the transcoder */
1609         assert_fdi_tx_disabled(dev_priv, pipe);
1610         assert_fdi_rx_disabled(dev_priv, pipe);
1611
1612         /* Ports must be off as well */
1613         assert_pch_ports_disabled(dev_priv, pipe);
1614
1615         reg = PCH_TRANSCONF(pipe);
1616         val = I915_READ(reg);
1617         val &= ~TRANS_ENABLE;
1618         I915_WRITE(reg, val);
1619         /* wait for PCH transcoder off, transcoder state */
1620         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1621                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1622
1623         if (!HAS_PCH_IBX(dev)) {
1624                 /* Workaround: Clear the timing override chicken bit again. */
1625                 reg = TRANS_CHICKEN2(pipe);
1626                 val = I915_READ(reg);
1627                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1628                 I915_WRITE(reg, val);
1629         }
1630 }
1631
1632 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1633 {
1634         u32 val;
1635
1636         val = I915_READ(LPT_TRANSCONF);
1637         val &= ~TRANS_ENABLE;
1638         I915_WRITE(LPT_TRANSCONF, val);
1639         /* wait for PCH transcoder off, transcoder state */
1640         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1641                 DRM_ERROR("Failed to disable PCH transcoder\n");
1642
1643         /* Workaround: clear timing override bit. */
1644         val = I915_READ(_TRANSA_CHICKEN2);
1645         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1646         I915_WRITE(_TRANSA_CHICKEN2, val);
1647 }
1648
1649 /**
1650  * intel_enable_pipe - enable a pipe, asserting requirements
1651  * @dev_priv: i915 private structure
1652  * @pipe: pipe to enable
1653  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1654  *
1655  * Enable @pipe, making sure that various hardware specific requirements
1656  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1657  *
1658  * @pipe should be %PIPE_A or %PIPE_B.
1659  *
1660  * Will wait until the pipe is actually running (i.e. first vblank) before
1661  * returning.
1662  */
1663 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1664                               bool pch_port)
1665 {
1666         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1667                                                                       pipe);
1668         enum pipe pch_transcoder;
1669         int reg;
1670         u32 val;
1671
1672         assert_planes_disabled(dev_priv, pipe);
1673         assert_sprites_disabled(dev_priv, pipe);
1674
1675         if (HAS_PCH_LPT(dev_priv->dev))
1676                 pch_transcoder = TRANSCODER_A;
1677         else
1678                 pch_transcoder = pipe;
1679
1680         /*
1681          * A pipe without a PLL won't actually be able to drive bits from
1682          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1683          * need the check.
1684          */
1685         if (!HAS_PCH_SPLIT(dev_priv->dev))
1686                 assert_pll_enabled(dev_priv, pipe);
1687         else {
1688                 if (pch_port) {
1689                         /* if driving the PCH, we need FDI enabled */
1690                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1691                         assert_fdi_tx_pll_enabled(dev_priv,
1692                                                   (enum pipe) cpu_transcoder);
1693                 }
1694                 /* FIXME: assert CPU port conditions for SNB+ */
1695         }
1696
1697         reg = PIPECONF(cpu_transcoder);
1698         val = I915_READ(reg);
1699         if (val & PIPECONF_ENABLE)
1700                 return;
1701
1702         I915_WRITE(reg, val | PIPECONF_ENABLE);
1703         intel_wait_for_vblank(dev_priv->dev, pipe);
1704 }
1705
1706 /**
1707  * intel_disable_pipe - disable a pipe, asserting requirements
1708  * @dev_priv: i915 private structure
1709  * @pipe: pipe to disable
1710  *
1711  * Disable @pipe, making sure that various hardware specific requirements
1712  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1713  *
1714  * @pipe should be %PIPE_A or %PIPE_B.
1715  *
1716  * Will wait until the pipe has shut down before returning.
1717  */
1718 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1719                                enum pipe pipe)
1720 {
1721         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1722                                                                       pipe);
1723         int reg;
1724         u32 val;
1725
1726         /*
1727          * Make sure planes won't keep trying to pump pixels to us,
1728          * or we might hang the display.
1729          */
1730         assert_planes_disabled(dev_priv, pipe);
1731         assert_sprites_disabled(dev_priv, pipe);
1732
1733         /* Don't disable pipe A or pipe A PLLs if needed */
1734         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1735                 return;
1736
1737         reg = PIPECONF(cpu_transcoder);
1738         val = I915_READ(reg);
1739         if ((val & PIPECONF_ENABLE) == 0)
1740                 return;
1741
1742         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1743         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1744 }
1745
1746 /*
1747  * Plane regs are double buffered, going from enabled->disabled needs a
1748  * trigger in order to latch.  The display address reg provides this.
1749  */
1750 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1751                                       enum plane plane)
1752 {
1753         if (dev_priv->info->gen >= 4)
1754                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1755         else
1756                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1757 }
1758
1759 /**
1760  * intel_enable_plane - enable a display plane on a given pipe
1761  * @dev_priv: i915 private structure
1762  * @plane: plane to enable
1763  * @pipe: pipe being fed
1764  *
1765  * Enable @plane on @pipe, making sure that @pipe is running first.
1766  */
1767 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1768                                enum plane plane, enum pipe pipe)
1769 {
1770         int reg;
1771         u32 val;
1772
1773         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1774         assert_pipe_enabled(dev_priv, pipe);
1775
1776         reg = DSPCNTR(plane);
1777         val = I915_READ(reg);
1778         if (val & DISPLAY_PLANE_ENABLE)
1779                 return;
1780
1781         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1782         intel_flush_display_plane(dev_priv, plane);
1783         intel_wait_for_vblank(dev_priv->dev, pipe);
1784 }
1785
1786 /**
1787  * intel_disable_plane - disable a display plane
1788  * @dev_priv: i915 private structure
1789  * @plane: plane to disable
1790  * @pipe: pipe consuming the data
1791  *
1792  * Disable @plane; should be an independent operation.
1793  */
1794 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1795                                 enum plane plane, enum pipe pipe)
1796 {
1797         int reg;
1798         u32 val;
1799
1800         reg = DSPCNTR(plane);
1801         val = I915_READ(reg);
1802         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1803                 return;
1804
1805         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1806         intel_flush_display_plane(dev_priv, plane);
1807         intel_wait_for_vblank(dev_priv->dev, pipe);
1808 }
1809
1810 static bool need_vtd_wa(struct drm_device *dev)
1811 {
1812 #ifdef CONFIG_INTEL_IOMMU
1813         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1814                 return true;
1815 #endif
1816         return false;
1817 }
1818
1819 int
1820 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1821                            struct drm_i915_gem_object *obj,
1822                            struct intel_ring_buffer *pipelined)
1823 {
1824         struct drm_i915_private *dev_priv = dev->dev_private;
1825         u32 alignment;
1826         int ret;
1827
1828         switch (obj->tiling_mode) {
1829         case I915_TILING_NONE:
1830                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1831                         alignment = 128 * 1024;
1832                 else if (INTEL_INFO(dev)->gen >= 4)
1833                         alignment = 4 * 1024;
1834                 else
1835                         alignment = 64 * 1024;
1836                 break;
1837         case I915_TILING_X:
1838                 /* pin() will align the object as required by fence */
1839                 alignment = 0;
1840                 break;
1841         case I915_TILING_Y:
1842                 /* Despite that we check this in framebuffer_init userspace can
1843                  * screw us over and change the tiling after the fact. Only
1844                  * pinned buffers can't change their tiling. */
1845                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1846                 return -EINVAL;
1847         default:
1848                 BUG();
1849         }
1850
1851         /* Note that the w/a also requires 64 PTE of padding following the
1852          * bo. We currently fill all unused PTE with the shadow page and so
1853          * we should always have valid PTE following the scanout preventing
1854          * the VT-d warning.
1855          */
1856         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1857                 alignment = 256 * 1024;
1858
1859         dev_priv->mm.interruptible = false;
1860         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1861         if (ret)
1862                 goto err_interruptible;
1863
1864         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1865          * fence, whereas 965+ only requires a fence if using
1866          * framebuffer compression.  For simplicity, we always install
1867          * a fence as the cost is not that onerous.
1868          */
1869         ret = i915_gem_object_get_fence(obj);
1870         if (ret)
1871                 goto err_unpin;
1872
1873         i915_gem_object_pin_fence(obj);
1874
1875         dev_priv->mm.interruptible = true;
1876         return 0;
1877
1878 err_unpin:
1879         i915_gem_object_unpin_from_display_plane(obj);
1880 err_interruptible:
1881         dev_priv->mm.interruptible = true;
1882         return ret;
1883 }
1884
1885 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1886 {
1887         i915_gem_object_unpin_fence(obj);
1888         i915_gem_object_unpin_from_display_plane(obj);
1889 }
1890
1891 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1892  * is assumed to be a power-of-two. */
1893 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1894                                              unsigned int tiling_mode,
1895                                              unsigned int cpp,
1896                                              unsigned int pitch)
1897 {
1898         if (tiling_mode != I915_TILING_NONE) {
1899                 unsigned int tile_rows, tiles;
1900
1901                 tile_rows = *y / 8;
1902                 *y %= 8;
1903
1904                 tiles = *x / (512/cpp);
1905                 *x %= 512/cpp;
1906
1907                 return tile_rows * pitch * 8 + tiles * 4096;
1908         } else {
1909                 unsigned int offset;
1910
1911                 offset = *y * pitch + *x * cpp;
1912                 *y = 0;
1913                 *x = (offset & 4095) / cpp;
1914                 return offset & -4096;
1915         }
1916 }
1917
1918 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1919                              int x, int y)
1920 {
1921         struct drm_device *dev = crtc->dev;
1922         struct drm_i915_private *dev_priv = dev->dev_private;
1923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1924         struct intel_framebuffer *intel_fb;
1925         struct drm_i915_gem_object *obj;
1926         int plane = intel_crtc->plane;
1927         unsigned long linear_offset;
1928         u32 dspcntr;
1929         u32 reg;
1930
1931         switch (plane) {
1932         case 0:
1933         case 1:
1934                 break;
1935         default:
1936                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1937                 return -EINVAL;
1938         }
1939
1940         intel_fb = to_intel_framebuffer(fb);
1941         obj = intel_fb->obj;
1942
1943         reg = DSPCNTR(plane);
1944         dspcntr = I915_READ(reg);
1945         /* Mask out pixel format bits in case we change it */
1946         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1947         switch (fb->pixel_format) {
1948         case DRM_FORMAT_C8:
1949                 dspcntr |= DISPPLANE_8BPP;
1950                 break;
1951         case DRM_FORMAT_XRGB1555:
1952         case DRM_FORMAT_ARGB1555:
1953                 dspcntr |= DISPPLANE_BGRX555;
1954                 break;
1955         case DRM_FORMAT_RGB565:
1956                 dspcntr |= DISPPLANE_BGRX565;
1957                 break;
1958         case DRM_FORMAT_XRGB8888:
1959         case DRM_FORMAT_ARGB8888:
1960                 dspcntr |= DISPPLANE_BGRX888;
1961                 break;
1962         case DRM_FORMAT_XBGR8888:
1963         case DRM_FORMAT_ABGR8888:
1964                 dspcntr |= DISPPLANE_RGBX888;
1965                 break;
1966         case DRM_FORMAT_XRGB2101010:
1967         case DRM_FORMAT_ARGB2101010:
1968                 dspcntr |= DISPPLANE_BGRX101010;
1969                 break;
1970         case DRM_FORMAT_XBGR2101010:
1971         case DRM_FORMAT_ABGR2101010:
1972                 dspcntr |= DISPPLANE_RGBX101010;
1973                 break;
1974         default:
1975                 BUG();
1976         }
1977
1978         if (INTEL_INFO(dev)->gen >= 4) {
1979                 if (obj->tiling_mode != I915_TILING_NONE)
1980                         dspcntr |= DISPPLANE_TILED;
1981                 else
1982                         dspcntr &= ~DISPPLANE_TILED;
1983         }
1984
1985         if (IS_G4X(dev))
1986                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1987
1988         I915_WRITE(reg, dspcntr);
1989
1990         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1991
1992         if (INTEL_INFO(dev)->gen >= 4) {
1993                 intel_crtc->dspaddr_offset =
1994                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1995                                                        fb->bits_per_pixel / 8,
1996                                                        fb->pitches[0]);
1997                 linear_offset -= intel_crtc->dspaddr_offset;
1998         } else {
1999                 intel_crtc->dspaddr_offset = linear_offset;
2000         }
2001
2002         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2003                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2004                       fb->pitches[0]);
2005         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2006         if (INTEL_INFO(dev)->gen >= 4) {
2007                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2008                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2009                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2010                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2011         } else
2012                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2013         POSTING_READ(reg);
2014
2015         return 0;
2016 }
2017
2018 static int ironlake_update_plane(struct drm_crtc *crtc,
2019                                  struct drm_framebuffer *fb, int x, int y)
2020 {
2021         struct drm_device *dev = crtc->dev;
2022         struct drm_i915_private *dev_priv = dev->dev_private;
2023         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024         struct intel_framebuffer *intel_fb;
2025         struct drm_i915_gem_object *obj;
2026         int plane = intel_crtc->plane;
2027         unsigned long linear_offset;
2028         u32 dspcntr;
2029         u32 reg;
2030
2031         switch (plane) {
2032         case 0:
2033         case 1:
2034         case 2:
2035                 break;
2036         default:
2037                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2038                 return -EINVAL;
2039         }
2040
2041         intel_fb = to_intel_framebuffer(fb);
2042         obj = intel_fb->obj;
2043
2044         reg = DSPCNTR(plane);
2045         dspcntr = I915_READ(reg);
2046         /* Mask out pixel format bits in case we change it */
2047         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2048         switch (fb->pixel_format) {
2049         case DRM_FORMAT_C8:
2050                 dspcntr |= DISPPLANE_8BPP;
2051                 break;
2052         case DRM_FORMAT_RGB565:
2053                 dspcntr |= DISPPLANE_BGRX565;
2054                 break;
2055         case DRM_FORMAT_XRGB8888:
2056         case DRM_FORMAT_ARGB8888:
2057                 dspcntr |= DISPPLANE_BGRX888;
2058                 break;
2059         case DRM_FORMAT_XBGR8888:
2060         case DRM_FORMAT_ABGR8888:
2061                 dspcntr |= DISPPLANE_RGBX888;
2062                 break;
2063         case DRM_FORMAT_XRGB2101010:
2064         case DRM_FORMAT_ARGB2101010:
2065                 dspcntr |= DISPPLANE_BGRX101010;
2066                 break;
2067         case DRM_FORMAT_XBGR2101010:
2068         case DRM_FORMAT_ABGR2101010:
2069                 dspcntr |= DISPPLANE_RGBX101010;
2070                 break;
2071         default:
2072                 BUG();
2073         }
2074
2075         if (obj->tiling_mode != I915_TILING_NONE)
2076                 dspcntr |= DISPPLANE_TILED;
2077         else
2078                 dspcntr &= ~DISPPLANE_TILED;
2079
2080         if (IS_HASWELL(dev))
2081                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2082         else
2083                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2084
2085         I915_WRITE(reg, dspcntr);
2086
2087         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2088         intel_crtc->dspaddr_offset =
2089                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2090                                                fb->bits_per_pixel / 8,
2091                                                fb->pitches[0]);
2092         linear_offset -= intel_crtc->dspaddr_offset;
2093
2094         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2095                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2096                       fb->pitches[0]);
2097         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2098         I915_MODIFY_DISPBASE(DSPSURF(plane),
2099                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2100         if (IS_HASWELL(dev)) {
2101                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2102         } else {
2103                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2104                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2105         }
2106         POSTING_READ(reg);
2107
2108         return 0;
2109 }
2110
2111 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2112 static int
2113 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2114                            int x, int y, enum mode_set_atomic state)
2115 {
2116         struct drm_device *dev = crtc->dev;
2117         struct drm_i915_private *dev_priv = dev->dev_private;
2118
2119         if (dev_priv->display.disable_fbc)
2120                 dev_priv->display.disable_fbc(dev);
2121         intel_increase_pllclock(crtc);
2122
2123         return dev_priv->display.update_plane(crtc, fb, x, y);
2124 }
2125
2126 void intel_display_handle_reset(struct drm_device *dev)
2127 {
2128         struct drm_i915_private *dev_priv = dev->dev_private;
2129         struct drm_crtc *crtc;
2130
2131         /*
2132          * Flips in the rings have been nuked by the reset,
2133          * so complete all pending flips so that user space
2134          * will get its events and not get stuck.
2135          *
2136          * Also update the base address of all primary
2137          * planes to the the last fb to make sure we're
2138          * showing the correct fb after a reset.
2139          *
2140          * Need to make two loops over the crtcs so that we
2141          * don't try to grab a crtc mutex before the
2142          * pending_flip_queue really got woken up.
2143          */
2144
2145         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2146                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2147                 enum plane plane = intel_crtc->plane;
2148
2149                 intel_prepare_page_flip(dev, plane);
2150                 intel_finish_page_flip_plane(dev, plane);
2151         }
2152
2153         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2154                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2155
2156                 mutex_lock(&crtc->mutex);
2157                 if (intel_crtc->active)
2158                         dev_priv->display.update_plane(crtc, crtc->fb,
2159                                                        crtc->x, crtc->y);
2160                 mutex_unlock(&crtc->mutex);
2161         }
2162 }
2163
2164 static int
2165 intel_finish_fb(struct drm_framebuffer *old_fb)
2166 {
2167         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2168         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2169         bool was_interruptible = dev_priv->mm.interruptible;
2170         int ret;
2171
2172         /* Big Hammer, we also need to ensure that any pending
2173          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2174          * current scanout is retired before unpinning the old
2175          * framebuffer.
2176          *
2177          * This should only fail upon a hung GPU, in which case we
2178          * can safely continue.
2179          */
2180         dev_priv->mm.interruptible = false;
2181         ret = i915_gem_object_finish_gpu(obj);
2182         dev_priv->mm.interruptible = was_interruptible;
2183
2184         return ret;
2185 }
2186
2187 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2188 {
2189         struct drm_device *dev = crtc->dev;
2190         struct drm_i915_master_private *master_priv;
2191         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2192
2193         if (!dev->primary->master)
2194                 return;
2195
2196         master_priv = dev->primary->master->driver_priv;
2197         if (!master_priv->sarea_priv)
2198                 return;
2199
2200         switch (intel_crtc->pipe) {
2201         case 0:
2202                 master_priv->sarea_priv->pipeA_x = x;
2203                 master_priv->sarea_priv->pipeA_y = y;
2204                 break;
2205         case 1:
2206                 master_priv->sarea_priv->pipeB_x = x;
2207                 master_priv->sarea_priv->pipeB_y = y;
2208                 break;
2209         default:
2210                 break;
2211         }
2212 }
2213
2214 static int
2215 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2216                     struct drm_framebuffer *fb)
2217 {
2218         struct drm_device *dev = crtc->dev;
2219         struct drm_i915_private *dev_priv = dev->dev_private;
2220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2221         struct drm_framebuffer *old_fb;
2222         int ret;
2223
2224         /* no fb bound */
2225         if (!fb) {
2226                 DRM_ERROR("No FB bound\n");
2227                 return 0;
2228         }
2229
2230         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2231                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2232                           plane_name(intel_crtc->plane),
2233                           INTEL_INFO(dev)->num_pipes);
2234                 return -EINVAL;
2235         }
2236
2237         mutex_lock(&dev->struct_mutex);
2238         ret = intel_pin_and_fence_fb_obj(dev,
2239                                          to_intel_framebuffer(fb)->obj,
2240                                          NULL);
2241         if (ret != 0) {
2242                 mutex_unlock(&dev->struct_mutex);
2243                 DRM_ERROR("pin & fence failed\n");
2244                 return ret;
2245         }
2246
2247         /* Update pipe size and adjust fitter if needed */
2248         if (i915_fastboot) {
2249                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2250                            ((crtc->mode.hdisplay - 1) << 16) |
2251                            (crtc->mode.vdisplay - 1));
2252                 if (!intel_crtc->config.pch_pfit.enabled &&
2253                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2254                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2255                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2256                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2257                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2258                 }
2259         }
2260
2261         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2262         if (ret) {
2263                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2264                 mutex_unlock(&dev->struct_mutex);
2265                 DRM_ERROR("failed to update base address\n");
2266                 return ret;
2267         }
2268
2269         old_fb = crtc->fb;
2270         crtc->fb = fb;
2271         crtc->x = x;
2272         crtc->y = y;
2273
2274         if (old_fb) {
2275                 if (intel_crtc->active && old_fb != fb)
2276                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2277                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2278         }
2279
2280         intel_update_fbc(dev);
2281         intel_edp_psr_update(dev);
2282         mutex_unlock(&dev->struct_mutex);
2283
2284         intel_crtc_update_sarea_pos(crtc, x, y);
2285
2286         return 0;
2287 }
2288
2289 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2290 {
2291         struct drm_device *dev = crtc->dev;
2292         struct drm_i915_private *dev_priv = dev->dev_private;
2293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2294         int pipe = intel_crtc->pipe;
2295         u32 reg, temp;
2296
2297         /* enable normal train */
2298         reg = FDI_TX_CTL(pipe);
2299         temp = I915_READ(reg);
2300         if (IS_IVYBRIDGE(dev)) {
2301                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2302                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2303         } else {
2304                 temp &= ~FDI_LINK_TRAIN_NONE;
2305                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2306         }
2307         I915_WRITE(reg, temp);
2308
2309         reg = FDI_RX_CTL(pipe);
2310         temp = I915_READ(reg);
2311         if (HAS_PCH_CPT(dev)) {
2312                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2313                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2314         } else {
2315                 temp &= ~FDI_LINK_TRAIN_NONE;
2316                 temp |= FDI_LINK_TRAIN_NONE;
2317         }
2318         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2319
2320         /* wait one idle pattern time */
2321         POSTING_READ(reg);
2322         udelay(1000);
2323
2324         /* IVB wants error correction enabled */
2325         if (IS_IVYBRIDGE(dev))
2326                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2327                            FDI_FE_ERRC_ENABLE);
2328 }
2329
2330 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2331 {
2332         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2333 }
2334
2335 static void ivb_modeset_global_resources(struct drm_device *dev)
2336 {
2337         struct drm_i915_private *dev_priv = dev->dev_private;
2338         struct intel_crtc *pipe_B_crtc =
2339                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2340         struct intel_crtc *pipe_C_crtc =
2341                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2342         uint32_t temp;
2343
2344         /*
2345          * When everything is off disable fdi C so that we could enable fdi B
2346          * with all lanes. Note that we don't care about enabled pipes without
2347          * an enabled pch encoder.
2348          */
2349         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2350             !pipe_has_enabled_pch(pipe_C_crtc)) {
2351                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2352                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2353
2354                 temp = I915_READ(SOUTH_CHICKEN1);
2355                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2356                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2357                 I915_WRITE(SOUTH_CHICKEN1, temp);
2358         }
2359 }
2360
2361 /* The FDI link training functions for ILK/Ibexpeak. */
2362 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2363 {
2364         struct drm_device *dev = crtc->dev;
2365         struct drm_i915_private *dev_priv = dev->dev_private;
2366         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2367         int pipe = intel_crtc->pipe;
2368         int plane = intel_crtc->plane;
2369         u32 reg, temp, tries;
2370
2371         /* FDI needs bits from pipe & plane first */
2372         assert_pipe_enabled(dev_priv, pipe);
2373         assert_plane_enabled(dev_priv, plane);
2374
2375         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2376            for train result */
2377         reg = FDI_RX_IMR(pipe);
2378         temp = I915_READ(reg);
2379         temp &= ~FDI_RX_SYMBOL_LOCK;
2380         temp &= ~FDI_RX_BIT_LOCK;
2381         I915_WRITE(reg, temp);
2382         I915_READ(reg);
2383         udelay(150);
2384
2385         /* enable CPU FDI TX and PCH FDI RX */
2386         reg = FDI_TX_CTL(pipe);
2387         temp = I915_READ(reg);
2388         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2389         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2390         temp &= ~FDI_LINK_TRAIN_NONE;
2391         temp |= FDI_LINK_TRAIN_PATTERN_1;
2392         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2393
2394         reg = FDI_RX_CTL(pipe);
2395         temp = I915_READ(reg);
2396         temp &= ~FDI_LINK_TRAIN_NONE;
2397         temp |= FDI_LINK_TRAIN_PATTERN_1;
2398         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2399
2400         POSTING_READ(reg);
2401         udelay(150);
2402
2403         /* Ironlake workaround, enable clock pointer after FDI enable*/
2404         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2405         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2406                    FDI_RX_PHASE_SYNC_POINTER_EN);
2407
2408         reg = FDI_RX_IIR(pipe);
2409         for (tries = 0; tries < 5; tries++) {
2410                 temp = I915_READ(reg);
2411                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2412
2413                 if ((temp & FDI_RX_BIT_LOCK)) {
2414                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2415                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2416                         break;
2417                 }
2418         }
2419         if (tries == 5)
2420                 DRM_ERROR("FDI train 1 fail!\n");
2421
2422         /* Train 2 */
2423         reg = FDI_TX_CTL(pipe);
2424         temp = I915_READ(reg);
2425         temp &= ~FDI_LINK_TRAIN_NONE;
2426         temp |= FDI_LINK_TRAIN_PATTERN_2;
2427         I915_WRITE(reg, temp);
2428
2429         reg = FDI_RX_CTL(pipe);
2430         temp = I915_READ(reg);
2431         temp &= ~FDI_LINK_TRAIN_NONE;
2432         temp |= FDI_LINK_TRAIN_PATTERN_2;
2433         I915_WRITE(reg, temp);
2434
2435         POSTING_READ(reg);
2436         udelay(150);
2437
2438         reg = FDI_RX_IIR(pipe);
2439         for (tries = 0; tries < 5; tries++) {
2440                 temp = I915_READ(reg);
2441                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2442
2443                 if (temp & FDI_RX_SYMBOL_LOCK) {
2444                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2445                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2446                         break;
2447                 }
2448         }
2449         if (tries == 5)
2450                 DRM_ERROR("FDI train 2 fail!\n");
2451
2452         DRM_DEBUG_KMS("FDI train done\n");
2453
2454 }
2455
2456 static const int snb_b_fdi_train_param[] = {
2457         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2458         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2459         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2460         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2461 };
2462
2463 /* The FDI link training functions for SNB/Cougarpoint. */
2464 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2465 {
2466         struct drm_device *dev = crtc->dev;
2467         struct drm_i915_private *dev_priv = dev->dev_private;
2468         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2469         int pipe = intel_crtc->pipe;
2470         u32 reg, temp, i, retry;
2471
2472         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2473            for train result */
2474         reg = FDI_RX_IMR(pipe);
2475         temp = I915_READ(reg);
2476         temp &= ~FDI_RX_SYMBOL_LOCK;
2477         temp &= ~FDI_RX_BIT_LOCK;
2478         I915_WRITE(reg, temp);
2479
2480         POSTING_READ(reg);
2481         udelay(150);
2482
2483         /* enable CPU FDI TX and PCH FDI RX */
2484         reg = FDI_TX_CTL(pipe);
2485         temp = I915_READ(reg);
2486         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2487         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2488         temp &= ~FDI_LINK_TRAIN_NONE;
2489         temp |= FDI_LINK_TRAIN_PATTERN_1;
2490         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2491         /* SNB-B */
2492         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2493         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2494
2495         I915_WRITE(FDI_RX_MISC(pipe),
2496                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2497
2498         reg = FDI_RX_CTL(pipe);
2499         temp = I915_READ(reg);
2500         if (HAS_PCH_CPT(dev)) {
2501                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503         } else {
2504                 temp &= ~FDI_LINK_TRAIN_NONE;
2505                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506         }
2507         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
2509         POSTING_READ(reg);
2510         udelay(150);
2511
2512         for (i = 0; i < 4; i++) {
2513                 reg = FDI_TX_CTL(pipe);
2514                 temp = I915_READ(reg);
2515                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2516                 temp |= snb_b_fdi_train_param[i];
2517                 I915_WRITE(reg, temp);
2518
2519                 POSTING_READ(reg);
2520                 udelay(500);
2521
2522                 for (retry = 0; retry < 5; retry++) {
2523                         reg = FDI_RX_IIR(pipe);
2524                         temp = I915_READ(reg);
2525                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2526                         if (temp & FDI_RX_BIT_LOCK) {
2527                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2528                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2529                                 break;
2530                         }
2531                         udelay(50);
2532                 }
2533                 if (retry < 5)
2534                         break;
2535         }
2536         if (i == 4)
2537                 DRM_ERROR("FDI train 1 fail!\n");
2538
2539         /* Train 2 */
2540         reg = FDI_TX_CTL(pipe);
2541         temp = I915_READ(reg);
2542         temp &= ~FDI_LINK_TRAIN_NONE;
2543         temp |= FDI_LINK_TRAIN_PATTERN_2;
2544         if (IS_GEN6(dev)) {
2545                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2546                 /* SNB-B */
2547                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2548         }
2549         I915_WRITE(reg, temp);
2550
2551         reg = FDI_RX_CTL(pipe);
2552         temp = I915_READ(reg);
2553         if (HAS_PCH_CPT(dev)) {
2554                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2555                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2556         } else {
2557                 temp &= ~FDI_LINK_TRAIN_NONE;
2558                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2559         }
2560         I915_WRITE(reg, temp);
2561
2562         POSTING_READ(reg);
2563         udelay(150);
2564
2565         for (i = 0; i < 4; i++) {
2566                 reg = FDI_TX_CTL(pipe);
2567                 temp = I915_READ(reg);
2568                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2569                 temp |= snb_b_fdi_train_param[i];
2570                 I915_WRITE(reg, temp);
2571
2572                 POSTING_READ(reg);
2573                 udelay(500);
2574
2575                 for (retry = 0; retry < 5; retry++) {
2576                         reg = FDI_RX_IIR(pipe);
2577                         temp = I915_READ(reg);
2578                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2579                         if (temp & FDI_RX_SYMBOL_LOCK) {
2580                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2581                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2582                                 break;
2583                         }
2584                         udelay(50);
2585                 }
2586                 if (retry < 5)
2587                         break;
2588         }
2589         if (i == 4)
2590                 DRM_ERROR("FDI train 2 fail!\n");
2591
2592         DRM_DEBUG_KMS("FDI train done.\n");
2593 }
2594
2595 /* Manual link training for Ivy Bridge A0 parts */
2596 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2597 {
2598         struct drm_device *dev = crtc->dev;
2599         struct drm_i915_private *dev_priv = dev->dev_private;
2600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601         int pipe = intel_crtc->pipe;
2602         u32 reg, temp, i, j;
2603
2604         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2605            for train result */
2606         reg = FDI_RX_IMR(pipe);
2607         temp = I915_READ(reg);
2608         temp &= ~FDI_RX_SYMBOL_LOCK;
2609         temp &= ~FDI_RX_BIT_LOCK;
2610         I915_WRITE(reg, temp);
2611
2612         POSTING_READ(reg);
2613         udelay(150);
2614
2615         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2616                       I915_READ(FDI_RX_IIR(pipe)));
2617
2618         /* Try each vswing and preemphasis setting twice before moving on */
2619         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2620                 /* disable first in case we need to retry */
2621                 reg = FDI_TX_CTL(pipe);
2622                 temp = I915_READ(reg);
2623                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2624                 temp &= ~FDI_TX_ENABLE;
2625                 I915_WRITE(reg, temp);
2626
2627                 reg = FDI_RX_CTL(pipe);
2628                 temp = I915_READ(reg);
2629                 temp &= ~FDI_LINK_TRAIN_AUTO;
2630                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2631                 temp &= ~FDI_RX_ENABLE;
2632                 I915_WRITE(reg, temp);
2633
2634                 /* enable CPU FDI TX and PCH FDI RX */
2635                 reg = FDI_TX_CTL(pipe);
2636                 temp = I915_READ(reg);
2637                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2638                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2639                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2640                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2641                 temp |= snb_b_fdi_train_param[j/2];
2642                 temp |= FDI_COMPOSITE_SYNC;
2643                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2644
2645                 I915_WRITE(FDI_RX_MISC(pipe),
2646                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2647
2648                 reg = FDI_RX_CTL(pipe);
2649                 temp = I915_READ(reg);
2650                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2651                 temp |= FDI_COMPOSITE_SYNC;
2652                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2653
2654                 POSTING_READ(reg);
2655                 udelay(1); /* should be 0.5us */
2656
2657                 for (i = 0; i < 4; i++) {
2658                         reg = FDI_RX_IIR(pipe);
2659                         temp = I915_READ(reg);
2660                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2661
2662                         if (temp & FDI_RX_BIT_LOCK ||
2663                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2664                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2665                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2666                                               i);
2667                                 break;
2668                         }
2669                         udelay(1); /* should be 0.5us */
2670                 }
2671                 if (i == 4) {
2672                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2673                         continue;
2674                 }
2675
2676                 /* Train 2 */
2677                 reg = FDI_TX_CTL(pipe);
2678                 temp = I915_READ(reg);
2679                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2680                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2681                 I915_WRITE(reg, temp);
2682
2683                 reg = FDI_RX_CTL(pipe);
2684                 temp = I915_READ(reg);
2685                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2686                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2687                 I915_WRITE(reg, temp);
2688
2689                 POSTING_READ(reg);
2690                 udelay(2); /* should be 1.5us */
2691
2692                 for (i = 0; i < 4; i++) {
2693                         reg = FDI_RX_IIR(pipe);
2694                         temp = I915_READ(reg);
2695                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2696
2697                         if (temp & FDI_RX_SYMBOL_LOCK ||
2698                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2699                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2700                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2701                                               i);
2702                                 goto train_done;
2703                         }
2704                         udelay(2); /* should be 1.5us */
2705                 }
2706                 if (i == 4)
2707                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2708         }
2709
2710 train_done:
2711         DRM_DEBUG_KMS("FDI train done.\n");
2712 }
2713
2714 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2715 {
2716         struct drm_device *dev = intel_crtc->base.dev;
2717         struct drm_i915_private *dev_priv = dev->dev_private;
2718         int pipe = intel_crtc->pipe;
2719         u32 reg, temp;
2720
2721
2722         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2723         reg = FDI_RX_CTL(pipe);
2724         temp = I915_READ(reg);
2725         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2726         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2727         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2728         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2729
2730         POSTING_READ(reg);
2731         udelay(200);
2732
2733         /* Switch from Rawclk to PCDclk */
2734         temp = I915_READ(reg);
2735         I915_WRITE(reg, temp | FDI_PCDCLK);
2736
2737         POSTING_READ(reg);
2738         udelay(200);
2739
2740         /* Enable CPU FDI TX PLL, always on for Ironlake */
2741         reg = FDI_TX_CTL(pipe);
2742         temp = I915_READ(reg);
2743         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2744                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2745
2746                 POSTING_READ(reg);
2747                 udelay(100);
2748         }
2749 }
2750
2751 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2752 {
2753         struct drm_device *dev = intel_crtc->base.dev;
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755         int pipe = intel_crtc->pipe;
2756         u32 reg, temp;
2757
2758         /* Switch from PCDclk to Rawclk */
2759         reg = FDI_RX_CTL(pipe);
2760         temp = I915_READ(reg);
2761         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2762
2763         /* Disable CPU FDI TX PLL */
2764         reg = FDI_TX_CTL(pipe);
2765         temp = I915_READ(reg);
2766         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2767
2768         POSTING_READ(reg);
2769         udelay(100);
2770
2771         reg = FDI_RX_CTL(pipe);
2772         temp = I915_READ(reg);
2773         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2774
2775         /* Wait for the clocks to turn off. */
2776         POSTING_READ(reg);
2777         udelay(100);
2778 }
2779
2780 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2781 {
2782         struct drm_device *dev = crtc->dev;
2783         struct drm_i915_private *dev_priv = dev->dev_private;
2784         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2785         int pipe = intel_crtc->pipe;
2786         u32 reg, temp;
2787
2788         /* disable CPU FDI tx and PCH FDI rx */
2789         reg = FDI_TX_CTL(pipe);
2790         temp = I915_READ(reg);
2791         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2792         POSTING_READ(reg);
2793
2794         reg = FDI_RX_CTL(pipe);
2795         temp = I915_READ(reg);
2796         temp &= ~(0x7 << 16);
2797         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2798         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2799
2800         POSTING_READ(reg);
2801         udelay(100);
2802
2803         /* Ironlake workaround, disable clock pointer after downing FDI */
2804         if (HAS_PCH_IBX(dev)) {
2805                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2806         }
2807
2808         /* still set train pattern 1 */
2809         reg = FDI_TX_CTL(pipe);
2810         temp = I915_READ(reg);
2811         temp &= ~FDI_LINK_TRAIN_NONE;
2812         temp |= FDI_LINK_TRAIN_PATTERN_1;
2813         I915_WRITE(reg, temp);
2814
2815         reg = FDI_RX_CTL(pipe);
2816         temp = I915_READ(reg);
2817         if (HAS_PCH_CPT(dev)) {
2818                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2819                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2820         } else {
2821                 temp &= ~FDI_LINK_TRAIN_NONE;
2822                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2823         }
2824         /* BPC in FDI rx is consistent with that in PIPECONF */
2825         temp &= ~(0x07 << 16);
2826         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2827         I915_WRITE(reg, temp);
2828
2829         POSTING_READ(reg);
2830         udelay(100);
2831 }
2832
2833 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2834 {
2835         struct drm_device *dev = crtc->dev;
2836         struct drm_i915_private *dev_priv = dev->dev_private;
2837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2838         unsigned long flags;
2839         bool pending;
2840
2841         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2842             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2843                 return false;
2844
2845         spin_lock_irqsave(&dev->event_lock, flags);
2846         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2847         spin_unlock_irqrestore(&dev->event_lock, flags);
2848
2849         return pending;
2850 }
2851
2852 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2853 {
2854         struct drm_device *dev = crtc->dev;
2855         struct drm_i915_private *dev_priv = dev->dev_private;
2856
2857         if (crtc->fb == NULL)
2858                 return;
2859
2860         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2861
2862         wait_event(dev_priv->pending_flip_queue,
2863                    !intel_crtc_has_pending_flip(crtc));
2864
2865         mutex_lock(&dev->struct_mutex);
2866         intel_finish_fb(crtc->fb);
2867         mutex_unlock(&dev->struct_mutex);
2868 }
2869
2870 /* Program iCLKIP clock to the desired frequency */
2871 static void lpt_program_iclkip(struct drm_crtc *crtc)
2872 {
2873         struct drm_device *dev = crtc->dev;
2874         struct drm_i915_private *dev_priv = dev->dev_private;
2875         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2876         u32 temp;
2877
2878         mutex_lock(&dev_priv->dpio_lock);
2879
2880         /* It is necessary to ungate the pixclk gate prior to programming
2881          * the divisors, and gate it back when it is done.
2882          */
2883         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2884
2885         /* Disable SSCCTL */
2886         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2887                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2888                                 SBI_SSCCTL_DISABLE,
2889                         SBI_ICLK);
2890
2891         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2892         if (crtc->mode.clock == 20000) {
2893                 auxdiv = 1;
2894                 divsel = 0x41;
2895                 phaseinc = 0x20;
2896         } else {
2897                 /* The iCLK virtual clock root frequency is in MHz,
2898                  * but the crtc->mode.clock in in KHz. To get the divisors,
2899                  * it is necessary to divide one by another, so we
2900                  * convert the virtual clock precision to KHz here for higher
2901                  * precision.
2902                  */
2903                 u32 iclk_virtual_root_freq = 172800 * 1000;
2904                 u32 iclk_pi_range = 64;
2905                 u32 desired_divisor, msb_divisor_value, pi_value;
2906
2907                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2908                 msb_divisor_value = desired_divisor / iclk_pi_range;
2909                 pi_value = desired_divisor % iclk_pi_range;
2910
2911                 auxdiv = 0;
2912                 divsel = msb_divisor_value - 2;
2913                 phaseinc = pi_value;
2914         }
2915
2916         /* This should not happen with any sane values */
2917         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2918                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2919         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2920                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2921
2922         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2923                         crtc->mode.clock,
2924                         auxdiv,
2925                         divsel,
2926                         phasedir,
2927                         phaseinc);
2928
2929         /* Program SSCDIVINTPHASE6 */
2930         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2931         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2932         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2933         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2934         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2935         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2936         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2937         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2938
2939         /* Program SSCAUXDIV */
2940         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2941         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2942         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2943         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2944
2945         /* Enable modulator and associated divider */
2946         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2947         temp &= ~SBI_SSCCTL_DISABLE;
2948         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2949
2950         /* Wait for initialization time */
2951         udelay(24);
2952
2953         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2954
2955         mutex_unlock(&dev_priv->dpio_lock);
2956 }
2957
2958 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2959                                                 enum pipe pch_transcoder)
2960 {
2961         struct drm_device *dev = crtc->base.dev;
2962         struct drm_i915_private *dev_priv = dev->dev_private;
2963         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2964
2965         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2966                    I915_READ(HTOTAL(cpu_transcoder)));
2967         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2968                    I915_READ(HBLANK(cpu_transcoder)));
2969         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2970                    I915_READ(HSYNC(cpu_transcoder)));
2971
2972         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2973                    I915_READ(VTOTAL(cpu_transcoder)));
2974         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2975                    I915_READ(VBLANK(cpu_transcoder)));
2976         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2977                    I915_READ(VSYNC(cpu_transcoder)));
2978         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2979                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2980 }
2981
2982 /*
2983  * Enable PCH resources required for PCH ports:
2984  *   - PCH PLLs
2985  *   - FDI training & RX/TX
2986  *   - update transcoder timings
2987  *   - DP transcoding bits
2988  *   - transcoder
2989  */
2990 static void ironlake_pch_enable(struct drm_crtc *crtc)
2991 {
2992         struct drm_device *dev = crtc->dev;
2993         struct drm_i915_private *dev_priv = dev->dev_private;
2994         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2995         int pipe = intel_crtc->pipe;
2996         u32 reg, temp;
2997
2998         assert_pch_transcoder_disabled(dev_priv, pipe);
2999
3000         /* Write the TU size bits before fdi link training, so that error
3001          * detection works. */
3002         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3003                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3004
3005         /* For PCH output, training FDI link */
3006         dev_priv->display.fdi_link_train(crtc);
3007
3008         /* We need to program the right clock selection before writing the pixel
3009          * mutliplier into the DPLL. */
3010         if (HAS_PCH_CPT(dev)) {
3011                 u32 sel;
3012
3013                 temp = I915_READ(PCH_DPLL_SEL);
3014                 temp |= TRANS_DPLL_ENABLE(pipe);
3015                 sel = TRANS_DPLLB_SEL(pipe);
3016                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3017                         temp |= sel;
3018                 else
3019                         temp &= ~sel;
3020                 I915_WRITE(PCH_DPLL_SEL, temp);
3021         }
3022
3023         /* XXX: pch pll's can be enabled any time before we enable the PCH
3024          * transcoder, and we actually should do this to not upset any PCH
3025          * transcoder that already use the clock when we share it.
3026          *
3027          * Note that enable_shared_dpll tries to do the right thing, but
3028          * get_shared_dpll unconditionally resets the pll - we need that to have
3029          * the right LVDS enable sequence. */
3030         ironlake_enable_shared_dpll(intel_crtc);
3031
3032         /* set transcoder timing, panel must allow it */
3033         assert_panel_unlocked(dev_priv, pipe);
3034         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3035
3036         intel_fdi_normal_train(crtc);
3037
3038         /* For PCH DP, enable TRANS_DP_CTL */
3039         if (HAS_PCH_CPT(dev) &&
3040             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3041              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3042                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3043                 reg = TRANS_DP_CTL(pipe);
3044                 temp = I915_READ(reg);
3045                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3046                           TRANS_DP_SYNC_MASK |
3047                           TRANS_DP_BPC_MASK);
3048                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3049                          TRANS_DP_ENH_FRAMING);
3050                 temp |= bpc << 9; /* same format but at 11:9 */
3051
3052                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3053                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3054                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3055                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3056
3057                 switch (intel_trans_dp_port_sel(crtc)) {
3058                 case PCH_DP_B:
3059                         temp |= TRANS_DP_PORT_SEL_B;
3060                         break;
3061                 case PCH_DP_C:
3062                         temp |= TRANS_DP_PORT_SEL_C;
3063                         break;
3064                 case PCH_DP_D:
3065                         temp |= TRANS_DP_PORT_SEL_D;
3066                         break;
3067                 default:
3068                         BUG();
3069                 }
3070
3071                 I915_WRITE(reg, temp);
3072         }
3073
3074         ironlake_enable_pch_transcoder(dev_priv, pipe);
3075 }
3076
3077 static void lpt_pch_enable(struct drm_crtc *crtc)
3078 {
3079         struct drm_device *dev = crtc->dev;
3080         struct drm_i915_private *dev_priv = dev->dev_private;
3081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3082         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3083
3084         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3085
3086         lpt_program_iclkip(crtc);
3087
3088         /* Set transcoder timing. */
3089         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3090
3091         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3092 }
3093
3094 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3095 {
3096         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3097
3098         if (pll == NULL)
3099                 return;
3100
3101         if (pll->refcount == 0) {
3102                 WARN(1, "bad %s refcount\n", pll->name);
3103                 return;
3104         }
3105
3106         if (--pll->refcount == 0) {
3107                 WARN_ON(pll->on);
3108                 WARN_ON(pll->active);
3109         }
3110
3111         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3112 }
3113
3114 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3115 {
3116         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3117         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3118         enum intel_dpll_id i;
3119
3120         if (pll) {
3121                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3122                               crtc->base.base.id, pll->name);
3123                 intel_put_shared_dpll(crtc);
3124         }
3125
3126         if (HAS_PCH_IBX(dev_priv->dev)) {
3127                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3128                 i = (enum intel_dpll_id) crtc->pipe;
3129                 pll = &dev_priv->shared_dplls[i];
3130
3131                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3132                               crtc->base.base.id, pll->name);
3133
3134                 goto found;
3135         }
3136
3137         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3138                 pll = &dev_priv->shared_dplls[i];
3139
3140                 /* Only want to check enabled timings first */
3141                 if (pll->refcount == 0)
3142                         continue;
3143
3144                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3145                            sizeof(pll->hw_state)) == 0) {
3146                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3147                                       crtc->base.base.id,
3148                                       pll->name, pll->refcount, pll->active);
3149
3150                         goto found;
3151                 }
3152         }
3153
3154         /* Ok no matching timings, maybe there's a free one? */
3155         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3156                 pll = &dev_priv->shared_dplls[i];
3157                 if (pll->refcount == 0) {
3158                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3159                                       crtc->base.base.id, pll->name);
3160                         goto found;
3161                 }
3162         }
3163
3164         return NULL;
3165
3166 found:
3167         crtc->config.shared_dpll = i;
3168         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3169                          pipe_name(crtc->pipe));
3170
3171         if (pll->active == 0) {
3172                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3173                        sizeof(pll->hw_state));
3174
3175                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3176                 WARN_ON(pll->on);
3177                 assert_shared_dpll_disabled(dev_priv, pll);
3178
3179                 pll->mode_set(dev_priv, pll);
3180         }
3181         pll->refcount++;
3182
3183         return pll;
3184 }
3185
3186 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3187 {
3188         struct drm_i915_private *dev_priv = dev->dev_private;
3189         int dslreg = PIPEDSL(pipe);
3190         u32 temp;
3191
3192         temp = I915_READ(dslreg);
3193         udelay(500);
3194         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3195                 if (wait_for(I915_READ(dslreg) != temp, 5))
3196                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3197         }
3198 }
3199
3200 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3201 {
3202         struct drm_device *dev = crtc->base.dev;
3203         struct drm_i915_private *dev_priv = dev->dev_private;
3204         int pipe = crtc->pipe;
3205
3206         if (crtc->config.pch_pfit.enabled) {
3207                 /* Force use of hard-coded filter coefficients
3208                  * as some pre-programmed values are broken,
3209                  * e.g. x201.
3210                  */
3211                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3212                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3213                                                  PF_PIPE_SEL_IVB(pipe));
3214                 else
3215                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3216                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3217                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3218         }
3219 }
3220
3221 static void intel_enable_planes(struct drm_crtc *crtc)
3222 {
3223         struct drm_device *dev = crtc->dev;
3224         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3225         struct intel_plane *intel_plane;
3226
3227         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3228                 if (intel_plane->pipe == pipe)
3229                         intel_plane_restore(&intel_plane->base);
3230 }
3231
3232 static void intel_disable_planes(struct drm_crtc *crtc)
3233 {
3234         struct drm_device *dev = crtc->dev;
3235         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3236         struct intel_plane *intel_plane;
3237
3238         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3239                 if (intel_plane->pipe == pipe)
3240                         intel_plane_disable(&intel_plane->base);
3241 }
3242
3243 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3244 {
3245         struct drm_device *dev = crtc->dev;
3246         struct drm_i915_private *dev_priv = dev->dev_private;
3247         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3248         struct intel_encoder *encoder;
3249         int pipe = intel_crtc->pipe;
3250         int plane = intel_crtc->plane;
3251
3252         WARN_ON(!crtc->enabled);
3253
3254         if (intel_crtc->active)
3255                 return;
3256
3257         intel_crtc->active = true;
3258
3259         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3260         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3261
3262         intel_update_watermarks(dev);
3263
3264         for_each_encoder_on_crtc(dev, crtc, encoder)
3265                 if (encoder->pre_enable)
3266                         encoder->pre_enable(encoder);
3267
3268         if (intel_crtc->config.has_pch_encoder) {
3269                 /* Note: FDI PLL enabling _must_ be done before we enable the
3270                  * cpu pipes, hence this is separate from all the other fdi/pch
3271                  * enabling. */
3272                 ironlake_fdi_pll_enable(intel_crtc);
3273         } else {
3274                 assert_fdi_tx_disabled(dev_priv, pipe);
3275                 assert_fdi_rx_disabled(dev_priv, pipe);
3276         }
3277
3278         ironlake_pfit_enable(intel_crtc);
3279
3280         /*
3281          * On ILK+ LUT must be loaded before the pipe is running but with
3282          * clocks enabled
3283          */
3284         intel_crtc_load_lut(crtc);
3285
3286         intel_enable_pipe(dev_priv, pipe,
3287                           intel_crtc->config.has_pch_encoder);
3288         intel_enable_plane(dev_priv, plane, pipe);
3289         intel_enable_planes(crtc);
3290         intel_crtc_update_cursor(crtc, true);
3291
3292         if (intel_crtc->config.has_pch_encoder)
3293                 ironlake_pch_enable(crtc);
3294
3295         mutex_lock(&dev->struct_mutex);
3296         intel_update_fbc(dev);
3297         mutex_unlock(&dev->struct_mutex);
3298
3299         for_each_encoder_on_crtc(dev, crtc, encoder)
3300                 encoder->enable(encoder);
3301
3302         if (HAS_PCH_CPT(dev))
3303                 cpt_verify_modeset(dev, intel_crtc->pipe);
3304
3305         /*
3306          * There seems to be a race in PCH platform hw (at least on some
3307          * outputs) where an enabled pipe still completes any pageflip right
3308          * away (as if the pipe is off) instead of waiting for vblank. As soon
3309          * as the first vblank happend, everything works as expected. Hence just
3310          * wait for one vblank before returning to avoid strange things
3311          * happening.
3312          */
3313         intel_wait_for_vblank(dev, intel_crtc->pipe);
3314 }
3315
3316 /* IPS only exists on ULT machines and is tied to pipe A. */
3317 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3318 {
3319         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3320 }
3321
3322 static void hsw_enable_ips(struct intel_crtc *crtc)
3323 {
3324         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3325
3326         if (!crtc->config.ips_enabled)
3327                 return;
3328
3329         /* We can only enable IPS after we enable a plane and wait for a vblank.
3330          * We guarantee that the plane is enabled by calling intel_enable_ips
3331          * only after intel_enable_plane. And intel_enable_plane already waits
3332          * for a vblank, so all we need to do here is to enable the IPS bit. */
3333         assert_plane_enabled(dev_priv, crtc->plane);
3334         I915_WRITE(IPS_CTL, IPS_ENABLE);
3335 }
3336
3337 static void hsw_disable_ips(struct intel_crtc *crtc)
3338 {
3339         struct drm_device *dev = crtc->base.dev;
3340         struct drm_i915_private *dev_priv = dev->dev_private;
3341
3342         if (!crtc->config.ips_enabled)
3343                 return;
3344
3345         assert_plane_enabled(dev_priv, crtc->plane);
3346         I915_WRITE(IPS_CTL, 0);
3347
3348         /* We need to wait for a vblank before we can disable the plane. */
3349         intel_wait_for_vblank(dev, crtc->pipe);
3350 }
3351
3352 static void haswell_crtc_enable(struct drm_crtc *crtc)
3353 {
3354         struct drm_device *dev = crtc->dev;
3355         struct drm_i915_private *dev_priv = dev->dev_private;
3356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3357         struct intel_encoder *encoder;
3358         int pipe = intel_crtc->pipe;
3359         int plane = intel_crtc->plane;
3360
3361         WARN_ON(!crtc->enabled);
3362
3363         if (intel_crtc->active)
3364                 return;
3365
3366         intel_crtc->active = true;
3367
3368         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3369         if (intel_crtc->config.has_pch_encoder)
3370                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3371
3372         intel_update_watermarks(dev);
3373
3374         if (intel_crtc->config.has_pch_encoder)
3375                 dev_priv->display.fdi_link_train(crtc);
3376
3377         for_each_encoder_on_crtc(dev, crtc, encoder)
3378                 if (encoder->pre_enable)
3379                         encoder->pre_enable(encoder);
3380
3381         intel_ddi_enable_pipe_clock(intel_crtc);
3382
3383         ironlake_pfit_enable(intel_crtc);
3384
3385         /*
3386          * On ILK+ LUT must be loaded before the pipe is running but with
3387          * clocks enabled
3388          */
3389         intel_crtc_load_lut(crtc);
3390
3391         intel_ddi_set_pipe_settings(crtc);
3392         intel_ddi_enable_transcoder_func(crtc);
3393
3394         intel_enable_pipe(dev_priv, pipe,
3395                           intel_crtc->config.has_pch_encoder);
3396         intel_enable_plane(dev_priv, plane, pipe);
3397         intel_enable_planes(crtc);
3398         intel_crtc_update_cursor(crtc, true);
3399
3400         hsw_enable_ips(intel_crtc);
3401
3402         if (intel_crtc->config.has_pch_encoder)
3403                 lpt_pch_enable(crtc);
3404
3405         mutex_lock(&dev->struct_mutex);
3406         intel_update_fbc(dev);
3407         mutex_unlock(&dev->struct_mutex);
3408
3409         for_each_encoder_on_crtc(dev, crtc, encoder)
3410                 encoder->enable(encoder);
3411
3412         /*
3413          * There seems to be a race in PCH platform hw (at least on some
3414          * outputs) where an enabled pipe still completes any pageflip right
3415          * away (as if the pipe is off) instead of waiting for vblank. As soon
3416          * as the first vblank happend, everything works as expected. Hence just
3417          * wait for one vblank before returning to avoid strange things
3418          * happening.
3419          */
3420         intel_wait_for_vblank(dev, intel_crtc->pipe);
3421 }
3422
3423 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3424 {
3425         struct drm_device *dev = crtc->base.dev;
3426         struct drm_i915_private *dev_priv = dev->dev_private;
3427         int pipe = crtc->pipe;
3428
3429         /* To avoid upsetting the power well on haswell only disable the pfit if
3430          * it's in use. The hw state code will make sure we get this right. */
3431         if (crtc->config.pch_pfit.enabled) {
3432                 I915_WRITE(PF_CTL(pipe), 0);
3433                 I915_WRITE(PF_WIN_POS(pipe), 0);
3434                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3435         }
3436 }
3437
3438 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3439 {
3440         struct drm_device *dev = crtc->dev;
3441         struct drm_i915_private *dev_priv = dev->dev_private;
3442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3443         struct intel_encoder *encoder;
3444         int pipe = intel_crtc->pipe;
3445         int plane = intel_crtc->plane;
3446         u32 reg, temp;
3447
3448
3449         if (!intel_crtc->active)
3450                 return;
3451
3452         for_each_encoder_on_crtc(dev, crtc, encoder)
3453                 encoder->disable(encoder);
3454
3455         intel_crtc_wait_for_pending_flips(crtc);
3456         drm_vblank_off(dev, pipe);
3457
3458         if (dev_priv->fbc.plane == plane)
3459                 intel_disable_fbc(dev);
3460
3461         intel_crtc_update_cursor(crtc, false);
3462         intel_disable_planes(crtc);
3463         intel_disable_plane(dev_priv, plane, pipe);
3464
3465         if (intel_crtc->config.has_pch_encoder)
3466                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3467
3468         intel_disable_pipe(dev_priv, pipe);
3469
3470         ironlake_pfit_disable(intel_crtc);
3471
3472         for_each_encoder_on_crtc(dev, crtc, encoder)
3473                 if (encoder->post_disable)
3474                         encoder->post_disable(encoder);
3475
3476         if (intel_crtc->config.has_pch_encoder) {
3477                 ironlake_fdi_disable(crtc);
3478
3479                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3480                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3481
3482                 if (HAS_PCH_CPT(dev)) {
3483                         /* disable TRANS_DP_CTL */
3484                         reg = TRANS_DP_CTL(pipe);
3485                         temp = I915_READ(reg);
3486                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3487                                   TRANS_DP_PORT_SEL_MASK);
3488                         temp |= TRANS_DP_PORT_SEL_NONE;
3489                         I915_WRITE(reg, temp);
3490
3491                         /* disable DPLL_SEL */
3492                         temp = I915_READ(PCH_DPLL_SEL);
3493                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3494                         I915_WRITE(PCH_DPLL_SEL, temp);
3495                 }
3496
3497                 /* disable PCH DPLL */
3498                 intel_disable_shared_dpll(intel_crtc);
3499
3500                 ironlake_fdi_pll_disable(intel_crtc);
3501         }
3502
3503         intel_crtc->active = false;
3504         intel_update_watermarks(dev);
3505
3506         mutex_lock(&dev->struct_mutex);
3507         intel_update_fbc(dev);
3508         mutex_unlock(&dev->struct_mutex);
3509 }
3510
3511 static void haswell_crtc_disable(struct drm_crtc *crtc)
3512 {
3513         struct drm_device *dev = crtc->dev;
3514         struct drm_i915_private *dev_priv = dev->dev_private;
3515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3516         struct intel_encoder *encoder;
3517         int pipe = intel_crtc->pipe;
3518         int plane = intel_crtc->plane;
3519         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3520
3521         if (!intel_crtc->active)
3522                 return;
3523
3524         for_each_encoder_on_crtc(dev, crtc, encoder)
3525                 encoder->disable(encoder);
3526
3527         intel_crtc_wait_for_pending_flips(crtc);
3528         drm_vblank_off(dev, pipe);
3529
3530         /* FBC must be disabled before disabling the plane on HSW. */
3531         if (dev_priv->fbc.plane == plane)
3532                 intel_disable_fbc(dev);
3533
3534         hsw_disable_ips(intel_crtc);
3535
3536         intel_crtc_update_cursor(crtc, false);
3537         intel_disable_planes(crtc);
3538         intel_disable_plane(dev_priv, plane, pipe);
3539
3540         if (intel_crtc->config.has_pch_encoder)
3541                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3542         intel_disable_pipe(dev_priv, pipe);
3543
3544         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3545
3546         ironlake_pfit_disable(intel_crtc);
3547
3548         intel_ddi_disable_pipe_clock(intel_crtc);
3549
3550         for_each_encoder_on_crtc(dev, crtc, encoder)
3551                 if (encoder->post_disable)
3552                         encoder->post_disable(encoder);
3553
3554         if (intel_crtc->config.has_pch_encoder) {
3555                 lpt_disable_pch_transcoder(dev_priv);
3556                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3557                 intel_ddi_fdi_disable(crtc);
3558         }
3559
3560         intel_crtc->active = false;
3561         intel_update_watermarks(dev);
3562
3563         mutex_lock(&dev->struct_mutex);
3564         intel_update_fbc(dev);
3565         mutex_unlock(&dev->struct_mutex);
3566 }
3567
3568 static void ironlake_crtc_off(struct drm_crtc *crtc)
3569 {
3570         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3571         intel_put_shared_dpll(intel_crtc);
3572 }
3573
3574 static void haswell_crtc_off(struct drm_crtc *crtc)
3575 {
3576         intel_ddi_put_crtc_pll(crtc);
3577 }
3578
3579 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3580 {
3581         if (!enable && intel_crtc->overlay) {
3582                 struct drm_device *dev = intel_crtc->base.dev;
3583                 struct drm_i915_private *dev_priv = dev->dev_private;
3584
3585                 mutex_lock(&dev->struct_mutex);
3586                 dev_priv->mm.interruptible = false;
3587                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3588                 dev_priv->mm.interruptible = true;
3589                 mutex_unlock(&dev->struct_mutex);
3590         }
3591
3592         /* Let userspace switch the overlay on again. In most cases userspace
3593          * has to recompute where to put it anyway.
3594          */
3595 }
3596
3597 /**
3598  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3599  * cursor plane briefly if not already running after enabling the display
3600  * plane.
3601  * This workaround avoids occasional blank screens when self refresh is
3602  * enabled.
3603  */
3604 static void
3605 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3606 {
3607         u32 cntl = I915_READ(CURCNTR(pipe));
3608
3609         if ((cntl & CURSOR_MODE) == 0) {
3610                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3611
3612                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3613                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3614                 intel_wait_for_vblank(dev_priv->dev, pipe);
3615                 I915_WRITE(CURCNTR(pipe), cntl);
3616                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3617                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3618         }
3619 }
3620
3621 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3622 {
3623         struct drm_device *dev = crtc->base.dev;
3624         struct drm_i915_private *dev_priv = dev->dev_private;
3625         struct intel_crtc_config *pipe_config = &crtc->config;
3626
3627         if (!crtc->config.gmch_pfit.control)
3628                 return;
3629
3630         /*
3631          * The panel fitter should only be adjusted whilst the pipe is disabled,
3632          * according to register description and PRM.
3633          */
3634         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3635         assert_pipe_disabled(dev_priv, crtc->pipe);
3636
3637         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3638         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3639
3640         /* Border color in case we don't scale up to the full screen. Black by
3641          * default, change to something else for debugging. */
3642         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3643 }
3644
3645 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3646 {
3647         struct drm_device *dev = crtc->dev;
3648         struct drm_i915_private *dev_priv = dev->dev_private;
3649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3650         struct intel_encoder *encoder;
3651         int pipe = intel_crtc->pipe;
3652         int plane = intel_crtc->plane;
3653
3654         WARN_ON(!crtc->enabled);
3655
3656         if (intel_crtc->active)
3657                 return;
3658
3659         intel_crtc->active = true;
3660         intel_update_watermarks(dev);
3661
3662         for_each_encoder_on_crtc(dev, crtc, encoder)
3663                 if (encoder->pre_pll_enable)
3664                         encoder->pre_pll_enable(encoder);
3665
3666         vlv_enable_pll(intel_crtc);
3667
3668         for_each_encoder_on_crtc(dev, crtc, encoder)
3669                 if (encoder->pre_enable)
3670                         encoder->pre_enable(encoder);
3671
3672         i9xx_pfit_enable(intel_crtc);
3673
3674         intel_crtc_load_lut(crtc);
3675
3676         intel_enable_pipe(dev_priv, pipe, false);
3677         intel_enable_plane(dev_priv, plane, pipe);
3678         intel_enable_planes(crtc);
3679         intel_crtc_update_cursor(crtc, true);
3680
3681         intel_update_fbc(dev);
3682
3683         for_each_encoder_on_crtc(dev, crtc, encoder)
3684                 encoder->enable(encoder);
3685 }
3686
3687 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3688 {
3689         struct drm_device *dev = crtc->dev;
3690         struct drm_i915_private *dev_priv = dev->dev_private;
3691         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3692         struct intel_encoder *encoder;
3693         int pipe = intel_crtc->pipe;
3694         int plane = intel_crtc->plane;
3695
3696         WARN_ON(!crtc->enabled);
3697
3698         if (intel_crtc->active)
3699                 return;
3700
3701         intel_crtc->active = true;
3702         intel_update_watermarks(dev);
3703
3704         for_each_encoder_on_crtc(dev, crtc, encoder)
3705                 if (encoder->pre_enable)
3706                         encoder->pre_enable(encoder);
3707
3708         i9xx_enable_pll(intel_crtc);
3709
3710         i9xx_pfit_enable(intel_crtc);
3711
3712         intel_crtc_load_lut(crtc);
3713
3714         intel_enable_pipe(dev_priv, pipe, false);
3715         intel_enable_plane(dev_priv, plane, pipe);
3716         intel_enable_planes(crtc);
3717         /* The fixup needs to happen before cursor is enabled */
3718         if (IS_G4X(dev))
3719                 g4x_fixup_plane(dev_priv, pipe);
3720         intel_crtc_update_cursor(crtc, true);
3721
3722         /* Give the overlay scaler a chance to enable if it's on this pipe */
3723         intel_crtc_dpms_overlay(intel_crtc, true);
3724
3725         intel_update_fbc(dev);
3726
3727         for_each_encoder_on_crtc(dev, crtc, encoder)
3728                 encoder->enable(encoder);
3729 }
3730
3731 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3732 {
3733         struct drm_device *dev = crtc->base.dev;
3734         struct drm_i915_private *dev_priv = dev->dev_private;
3735
3736         if (!crtc->config.gmch_pfit.control)
3737                 return;
3738
3739         assert_pipe_disabled(dev_priv, crtc->pipe);
3740
3741         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3742                          I915_READ(PFIT_CONTROL));
3743         I915_WRITE(PFIT_CONTROL, 0);
3744 }
3745
3746 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3747 {
3748         struct drm_device *dev = crtc->dev;
3749         struct drm_i915_private *dev_priv = dev->dev_private;
3750         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3751         struct intel_encoder *encoder;
3752         int pipe = intel_crtc->pipe;
3753         int plane = intel_crtc->plane;
3754
3755         if (!intel_crtc->active)
3756                 return;
3757
3758         for_each_encoder_on_crtc(dev, crtc, encoder)
3759                 encoder->disable(encoder);
3760
3761         /* Give the overlay scaler a chance to disable if it's on this pipe */
3762         intel_crtc_wait_for_pending_flips(crtc);
3763         drm_vblank_off(dev, pipe);
3764
3765         if (dev_priv->fbc.plane == plane)
3766                 intel_disable_fbc(dev);
3767
3768         intel_crtc_dpms_overlay(intel_crtc, false);
3769         intel_crtc_update_cursor(crtc, false);
3770         intel_disable_planes(crtc);
3771         intel_disable_plane(dev_priv, plane, pipe);
3772
3773         intel_disable_pipe(dev_priv, pipe);
3774
3775         i9xx_pfit_disable(intel_crtc);
3776
3777         for_each_encoder_on_crtc(dev, crtc, encoder)
3778                 if (encoder->post_disable)
3779                         encoder->post_disable(encoder);
3780
3781         i9xx_disable_pll(dev_priv, pipe);
3782
3783         intel_crtc->active = false;
3784         intel_update_fbc(dev);
3785         intel_update_watermarks(dev);
3786 }
3787
3788 static void i9xx_crtc_off(struct drm_crtc *crtc)
3789 {
3790 }
3791
3792 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3793                                     bool enabled)
3794 {
3795         struct drm_device *dev = crtc->dev;
3796         struct drm_i915_master_private *master_priv;
3797         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3798         int pipe = intel_crtc->pipe;
3799
3800         if (!dev->primary->master)
3801                 return;
3802
3803         master_priv = dev->primary->master->driver_priv;
3804         if (!master_priv->sarea_priv)
3805                 return;
3806
3807         switch (pipe) {
3808         case 0:
3809                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3810                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3811                 break;
3812         case 1:
3813                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3814                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3815                 break;
3816         default:
3817                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3818                 break;
3819         }
3820 }
3821
3822 /**
3823  * Sets the power management mode of the pipe and plane.
3824  */
3825 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3826 {
3827         struct drm_device *dev = crtc->dev;
3828         struct drm_i915_private *dev_priv = dev->dev_private;
3829         struct intel_encoder *intel_encoder;
3830         bool enable = false;
3831
3832         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3833                 enable |= intel_encoder->connectors_active;
3834
3835         if (enable)
3836                 dev_priv->display.crtc_enable(crtc);
3837         else
3838                 dev_priv->display.crtc_disable(crtc);
3839
3840         intel_crtc_update_sarea(crtc, enable);
3841 }
3842
3843 static void intel_crtc_disable(struct drm_crtc *crtc)
3844 {
3845         struct drm_device *dev = crtc->dev;
3846         struct drm_connector *connector;
3847         struct drm_i915_private *dev_priv = dev->dev_private;
3848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849
3850         /* crtc should still be enabled when we disable it. */
3851         WARN_ON(!crtc->enabled);
3852
3853         dev_priv->display.crtc_disable(crtc);
3854         intel_crtc->eld_vld = false;
3855         intel_crtc_update_sarea(crtc, false);
3856         dev_priv->display.off(crtc);
3857
3858         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3859         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3860
3861         if (crtc->fb) {
3862                 mutex_lock(&dev->struct_mutex);
3863                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3864                 mutex_unlock(&dev->struct_mutex);
3865                 crtc->fb = NULL;
3866         }
3867
3868         /* Update computed state. */
3869         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3870                 if (!connector->encoder || !connector->encoder->crtc)
3871                         continue;
3872
3873                 if (connector->encoder->crtc != crtc)
3874                         continue;
3875
3876                 connector->dpms = DRM_MODE_DPMS_OFF;
3877                 to_intel_encoder(connector->encoder)->connectors_active = false;
3878         }
3879 }
3880
3881 void intel_encoder_destroy(struct drm_encoder *encoder)
3882 {
3883         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3884
3885         drm_encoder_cleanup(encoder);
3886         kfree(intel_encoder);
3887 }
3888
3889 /* Simple dpms helper for encoders with just one connector, no cloning and only
3890  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3891  * state of the entire output pipe. */
3892 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3893 {
3894         if (mode == DRM_MODE_DPMS_ON) {
3895                 encoder->connectors_active = true;
3896
3897                 intel_crtc_update_dpms(encoder->base.crtc);
3898         } else {
3899                 encoder->connectors_active = false;
3900
3901                 intel_crtc_update_dpms(encoder->base.crtc);
3902         }
3903 }
3904
3905 /* Cross check the actual hw state with our own modeset state tracking (and it's
3906  * internal consistency). */
3907 static void intel_connector_check_state(struct intel_connector *connector)
3908 {
3909         if (connector->get_hw_state(connector)) {
3910                 struct intel_encoder *encoder = connector->encoder;
3911                 struct drm_crtc *crtc;
3912                 bool encoder_enabled;
3913                 enum pipe pipe;
3914
3915                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3916                               connector->base.base.id,
3917                               drm_get_connector_name(&connector->base));
3918
3919                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3920                      "wrong connector dpms state\n");
3921                 WARN(connector->base.encoder != &encoder->base,
3922                      "active connector not linked to encoder\n");
3923                 WARN(!encoder->connectors_active,
3924                      "encoder->connectors_active not set\n");
3925
3926                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3927                 WARN(!encoder_enabled, "encoder not enabled\n");
3928                 if (WARN_ON(!encoder->base.crtc))
3929                         return;
3930
3931                 crtc = encoder->base.crtc;
3932
3933                 WARN(!crtc->enabled, "crtc not enabled\n");
3934                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3935                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3936                      "encoder active on the wrong pipe\n");
3937         }
3938 }
3939
3940 /* Even simpler default implementation, if there's really no special case to
3941  * consider. */
3942 void intel_connector_dpms(struct drm_connector *connector, int mode)
3943 {
3944         struct intel_encoder *encoder = intel_attached_encoder(connector);
3945
3946         /* All the simple cases only support two dpms states. */
3947         if (mode != DRM_MODE_DPMS_ON)
3948                 mode = DRM_MODE_DPMS_OFF;
3949
3950         if (mode == connector->dpms)
3951                 return;
3952
3953         connector->dpms = mode;
3954
3955         /* Only need to change hw state when actually enabled */
3956         if (encoder->base.crtc)
3957                 intel_encoder_dpms(encoder, mode);
3958         else
3959                 WARN_ON(encoder->connectors_active != false);
3960
3961         intel_modeset_check_state(connector->dev);
3962 }
3963
3964 /* Simple connector->get_hw_state implementation for encoders that support only
3965  * one connector and no cloning and hence the encoder state determines the state
3966  * of the connector. */
3967 bool intel_connector_get_hw_state(struct intel_connector *connector)
3968 {
3969         enum pipe pipe = 0;
3970         struct intel_encoder *encoder = connector->encoder;
3971
3972         return encoder->get_hw_state(encoder, &pipe);
3973 }
3974
3975 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3976                                      struct intel_crtc_config *pipe_config)
3977 {
3978         struct drm_i915_private *dev_priv = dev->dev_private;
3979         struct intel_crtc *pipe_B_crtc =
3980                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3981
3982         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3983                       pipe_name(pipe), pipe_config->fdi_lanes);
3984         if (pipe_config->fdi_lanes > 4) {
3985                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3986                               pipe_name(pipe), pipe_config->fdi_lanes);
3987                 return false;
3988         }
3989
3990         if (IS_HASWELL(dev)) {
3991                 if (pipe_config->fdi_lanes > 2) {
3992                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3993                                       pipe_config->fdi_lanes);
3994                         return false;
3995                 } else {
3996                         return true;
3997                 }
3998         }
3999
4000         if (INTEL_INFO(dev)->num_pipes == 2)
4001                 return true;
4002
4003         /* Ivybridge 3 pipe is really complicated */
4004         switch (pipe) {
4005         case PIPE_A:
4006                 return true;
4007         case PIPE_B:
4008                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4009                     pipe_config->fdi_lanes > 2) {
4010                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4011                                       pipe_name(pipe), pipe_config->fdi_lanes);
4012                         return false;
4013                 }
4014                 return true;
4015         case PIPE_C:
4016                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4017                     pipe_B_crtc->config.fdi_lanes <= 2) {
4018                         if (pipe_config->fdi_lanes > 2) {
4019                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4020                                               pipe_name(pipe), pipe_config->fdi_lanes);
4021                                 return false;
4022                         }
4023                 } else {
4024                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4025                         return false;
4026                 }
4027                 return true;
4028         default:
4029                 BUG();
4030         }
4031 }
4032
4033 #define RETRY 1
4034 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4035                                        struct intel_crtc_config *pipe_config)
4036 {
4037         struct drm_device *dev = intel_crtc->base.dev;
4038         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4039         int lane, link_bw, fdi_dotclock;
4040         bool setup_ok, needs_recompute = false;
4041
4042 retry:
4043         /* FDI is a binary signal running at ~2.7GHz, encoding
4044          * each output octet as 10 bits. The actual frequency
4045          * is stored as a divider into a 100MHz clock, and the
4046          * mode pixel clock is stored in units of 1KHz.
4047          * Hence the bw of each lane in terms of the mode signal
4048          * is:
4049          */
4050         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4051
4052         fdi_dotclock = adjusted_mode->clock;
4053         fdi_dotclock /= pipe_config->pixel_multiplier;
4054
4055         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4056                                            pipe_config->pipe_bpp);
4057
4058         pipe_config->fdi_lanes = lane;
4059
4060         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4061                                link_bw, &pipe_config->fdi_m_n);
4062
4063         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4064                                             intel_crtc->pipe, pipe_config);
4065         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4066                 pipe_config->pipe_bpp -= 2*3;
4067                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4068                               pipe_config->pipe_bpp);
4069                 needs_recompute = true;
4070                 pipe_config->bw_constrained = true;
4071
4072                 goto retry;
4073         }
4074
4075         if (needs_recompute)
4076                 return RETRY;
4077
4078         return setup_ok ? 0 : -EINVAL;
4079 }
4080
4081 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4082                                    struct intel_crtc_config *pipe_config)
4083 {
4084         pipe_config->ips_enabled = i915_enable_ips &&
4085                                    hsw_crtc_supports_ips(crtc) &&
4086                                    pipe_config->pipe_bpp <= 24;
4087 }
4088
4089 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4090                                      struct intel_crtc_config *pipe_config)
4091 {
4092         struct drm_device *dev = crtc->base.dev;
4093         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4094
4095         if (HAS_PCH_SPLIT(dev)) {
4096                 /* FDI link clock is fixed at 2.7G */
4097                 if (pipe_config->requested_mode.clock * 3
4098                     > IRONLAKE_FDI_FREQ * 4)
4099                         return -EINVAL;
4100         }
4101
4102         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4103          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4104          */
4105         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4106                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4107                 return -EINVAL;
4108
4109         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4110                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4111         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4112                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4113                  * for lvds. */
4114                 pipe_config->pipe_bpp = 8*3;
4115         }
4116
4117         if (HAS_IPS(dev))
4118                 hsw_compute_ips_config(crtc, pipe_config);
4119
4120         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4121          * clock survives for now. */
4122         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4123                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4124
4125         if (pipe_config->has_pch_encoder)
4126                 return ironlake_fdi_compute_config(crtc, pipe_config);
4127
4128         return 0;
4129 }
4130
4131 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4132 {
4133         return 400000; /* FIXME */
4134 }
4135
4136 static int i945_get_display_clock_speed(struct drm_device *dev)
4137 {
4138         return 400000;
4139 }
4140
4141 static int i915_get_display_clock_speed(struct drm_device *dev)
4142 {
4143         return 333000;
4144 }
4145
4146 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4147 {
4148         return 200000;
4149 }
4150
4151 static int pnv_get_display_clock_speed(struct drm_device *dev)
4152 {
4153         u16 gcfgc = 0;
4154
4155         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4156
4157         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4158         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4159                 return 267000;
4160         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4161                 return 333000;
4162         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4163                 return 444000;
4164         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4165                 return 200000;
4166         default:
4167                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4168         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4169                 return 133000;
4170         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4171                 return 167000;
4172         }
4173 }
4174
4175 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4176 {
4177         u16 gcfgc = 0;
4178
4179         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4180
4181         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4182                 return 133000;
4183         else {
4184                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4185                 case GC_DISPLAY_CLOCK_333_MHZ:
4186                         return 333000;
4187                 default:
4188                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4189                         return 190000;
4190                 }
4191         }
4192 }
4193
4194 static int i865_get_display_clock_speed(struct drm_device *dev)
4195 {
4196         return 266000;
4197 }
4198
4199 static int i855_get_display_clock_speed(struct drm_device *dev)
4200 {
4201         u16 hpllcc = 0;
4202         /* Assume that the hardware is in the high speed state.  This
4203          * should be the default.
4204          */
4205         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4206         case GC_CLOCK_133_200:
4207         case GC_CLOCK_100_200:
4208                 return 200000;
4209         case GC_CLOCK_166_250:
4210                 return 250000;
4211         case GC_CLOCK_100_133:
4212                 return 133000;
4213         }
4214
4215         /* Shouldn't happen */
4216         return 0;
4217 }
4218
4219 static int i830_get_display_clock_speed(struct drm_device *dev)
4220 {
4221         return 133000;
4222 }
4223
4224 static void
4225 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4226 {
4227         while (*num > DATA_LINK_M_N_MASK ||
4228                *den > DATA_LINK_M_N_MASK) {
4229                 *num >>= 1;
4230                 *den >>= 1;
4231         }
4232 }
4233
4234 static void compute_m_n(unsigned int m, unsigned int n,
4235                         uint32_t *ret_m, uint32_t *ret_n)
4236 {
4237         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4238         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4239         intel_reduce_m_n_ratio(ret_m, ret_n);
4240 }
4241
4242 void
4243 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4244                        int pixel_clock, int link_clock,
4245                        struct intel_link_m_n *m_n)
4246 {
4247         m_n->tu = 64;
4248
4249         compute_m_n(bits_per_pixel * pixel_clock,
4250                     link_clock * nlanes * 8,
4251                     &m_n->gmch_m, &m_n->gmch_n);
4252
4253         compute_m_n(pixel_clock, link_clock,
4254                     &m_n->link_m, &m_n->link_n);
4255 }
4256
4257 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4258 {
4259         if (i915_panel_use_ssc >= 0)
4260                 return i915_panel_use_ssc != 0;
4261         return dev_priv->vbt.lvds_use_ssc
4262                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4263 }
4264
4265 static int vlv_get_refclk(struct drm_crtc *crtc)
4266 {
4267         struct drm_device *dev = crtc->dev;
4268         struct drm_i915_private *dev_priv = dev->dev_private;
4269         int refclk = 27000; /* for DP & HDMI */
4270
4271         return 100000; /* only one validated so far */
4272
4273         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4274                 refclk = 96000;
4275         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4276                 if (intel_panel_use_ssc(dev_priv))
4277                         refclk = 100000;
4278                 else
4279                         refclk = 96000;
4280         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4281                 refclk = 100000;
4282         }
4283
4284         return refclk;
4285 }
4286
4287 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4288 {
4289         struct drm_device *dev = crtc->dev;
4290         struct drm_i915_private *dev_priv = dev->dev_private;
4291         int refclk;
4292
4293         if (IS_VALLEYVIEW(dev)) {
4294                 refclk = vlv_get_refclk(crtc);
4295         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4296             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4297                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4298                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4299                               refclk / 1000);
4300         } else if (!IS_GEN2(dev)) {
4301                 refclk = 96000;
4302         } else {
4303                 refclk = 48000;
4304         }
4305
4306         return refclk;
4307 }
4308
4309 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4310 {
4311         return (1 << dpll->n) << 16 | dpll->m2;
4312 }
4313
4314 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4315 {
4316         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4317 }
4318
4319 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4320                                      intel_clock_t *reduced_clock)
4321 {
4322         struct drm_device *dev = crtc->base.dev;
4323         struct drm_i915_private *dev_priv = dev->dev_private;
4324         int pipe = crtc->pipe;
4325         u32 fp, fp2 = 0;
4326
4327         if (IS_PINEVIEW(dev)) {
4328                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4329                 if (reduced_clock)
4330                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4331         } else {
4332                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4333                 if (reduced_clock)
4334                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4335         }
4336
4337         I915_WRITE(FP0(pipe), fp);
4338         crtc->config.dpll_hw_state.fp0 = fp;
4339
4340         crtc->lowfreq_avail = false;
4341         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4342             reduced_clock && i915_powersave) {
4343                 I915_WRITE(FP1(pipe), fp2);
4344                 crtc->config.dpll_hw_state.fp1 = fp2;
4345                 crtc->lowfreq_avail = true;
4346         } else {
4347                 I915_WRITE(FP1(pipe), fp);
4348                 crtc->config.dpll_hw_state.fp1 = fp;
4349         }
4350 }
4351
4352 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4353 {
4354         u32 reg_val;
4355
4356         /*
4357          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4358          * and set it to a reasonable value instead.
4359          */
4360         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4361         reg_val &= 0xffffff00;
4362         reg_val |= 0x00000030;
4363         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4364
4365         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4366         reg_val &= 0x8cffffff;
4367         reg_val = 0x8c000000;
4368         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4369
4370         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4371         reg_val &= 0xffffff00;
4372         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4373
4374         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4375         reg_val &= 0x00ffffff;
4376         reg_val |= 0xb0000000;
4377         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4378 }
4379
4380 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4381                                          struct intel_link_m_n *m_n)
4382 {
4383         struct drm_device *dev = crtc->base.dev;
4384         struct drm_i915_private *dev_priv = dev->dev_private;
4385         int pipe = crtc->pipe;
4386
4387         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4388         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4389         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4390         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4391 }
4392
4393 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4394                                          struct intel_link_m_n *m_n)
4395 {
4396         struct drm_device *dev = crtc->base.dev;
4397         struct drm_i915_private *dev_priv = dev->dev_private;
4398         int pipe = crtc->pipe;
4399         enum transcoder transcoder = crtc->config.cpu_transcoder;
4400
4401         if (INTEL_INFO(dev)->gen >= 5) {
4402                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4403                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4404                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4405                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4406         } else {
4407                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4408                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4409                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4410                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4411         }
4412 }
4413
4414 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4415 {
4416         if (crtc->config.has_pch_encoder)
4417                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4418         else
4419                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4420 }
4421
4422 static void vlv_update_pll(struct intel_crtc *crtc)
4423 {
4424         struct drm_device *dev = crtc->base.dev;
4425         struct drm_i915_private *dev_priv = dev->dev_private;
4426         int pipe = crtc->pipe;
4427         u32 dpll, mdiv;
4428         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4429         u32 coreclk, reg_val, dpll_md;
4430
4431         mutex_lock(&dev_priv->dpio_lock);
4432
4433         bestn = crtc->config.dpll.n;
4434         bestm1 = crtc->config.dpll.m1;
4435         bestm2 = crtc->config.dpll.m2;
4436         bestp1 = crtc->config.dpll.p1;
4437         bestp2 = crtc->config.dpll.p2;
4438
4439         /* See eDP HDMI DPIO driver vbios notes doc */
4440
4441         /* PLL B needs special handling */
4442         if (pipe)
4443                 vlv_pllb_recal_opamp(dev_priv);
4444
4445         /* Set up Tx target for periodic Rcomp update */
4446         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4447
4448         /* Disable target IRef on PLL */
4449         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4450         reg_val &= 0x00ffffff;
4451         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4452
4453         /* Disable fast lock */
4454         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4455
4456         /* Set idtafcrecal before PLL is enabled */
4457         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4458         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4459         mdiv |= ((bestn << DPIO_N_SHIFT));
4460         mdiv |= (1 << DPIO_K_SHIFT);
4461
4462         /*
4463          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4464          * but we don't support that).
4465          * Note: don't use the DAC post divider as it seems unstable.
4466          */
4467         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4468         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4469
4470         mdiv |= DPIO_ENABLE_CALIBRATION;
4471         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4472
4473         /* Set HBR and RBR LPF coefficients */
4474         if (crtc->config.port_clock == 162000 ||
4475             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4476             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4477                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4478                                  0x009f0003);
4479         else
4480                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4481                                  0x00d0000f);
4482
4483         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4484             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4485                 /* Use SSC source */
4486                 if (!pipe)
4487                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4488                                          0x0df40000);
4489                 else
4490                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4491                                          0x0df70000);
4492         } else { /* HDMI or VGA */
4493                 /* Use bend source */
4494                 if (!pipe)
4495                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4496                                          0x0df70000);
4497                 else
4498                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4499                                          0x0df40000);
4500         }
4501
4502         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4503         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4504         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4505             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4506                 coreclk |= 0x01000000;
4507         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4508
4509         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4510
4511         /* Enable DPIO clock input */
4512         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4513                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4514         if (pipe)
4515                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4516
4517         dpll |= DPLL_VCO_ENABLE;
4518         crtc->config.dpll_hw_state.dpll = dpll;
4519
4520         dpll_md = (crtc->config.pixel_multiplier - 1)
4521                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4522         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4523
4524         if (crtc->config.has_dp_encoder)
4525                 intel_dp_set_m_n(crtc);
4526
4527         mutex_unlock(&dev_priv->dpio_lock);
4528 }
4529
4530 static void i9xx_update_pll(struct intel_crtc *crtc,
4531                             intel_clock_t *reduced_clock,
4532                             int num_connectors)
4533 {
4534         struct drm_device *dev = crtc->base.dev;
4535         struct drm_i915_private *dev_priv = dev->dev_private;
4536         u32 dpll;
4537         bool is_sdvo;
4538         struct dpll *clock = &crtc->config.dpll;
4539
4540         i9xx_update_pll_dividers(crtc, reduced_clock);
4541
4542         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4543                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4544
4545         dpll = DPLL_VGA_MODE_DIS;
4546
4547         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4548                 dpll |= DPLLB_MODE_LVDS;
4549         else
4550                 dpll |= DPLLB_MODE_DAC_SERIAL;
4551
4552         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4553                 dpll |= (crtc->config.pixel_multiplier - 1)
4554                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4555         }
4556
4557         if (is_sdvo)
4558                 dpll |= DPLL_SDVO_HIGH_SPEED;
4559
4560         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4561                 dpll |= DPLL_SDVO_HIGH_SPEED;
4562
4563         /* compute bitmask from p1 value */
4564         if (IS_PINEVIEW(dev))
4565                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4566         else {
4567                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4568                 if (IS_G4X(dev) && reduced_clock)
4569                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4570         }
4571         switch (clock->p2) {
4572         case 5:
4573                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4574                 break;
4575         case 7:
4576                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4577                 break;
4578         case 10:
4579                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4580                 break;
4581         case 14:
4582                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4583                 break;
4584         }
4585         if (INTEL_INFO(dev)->gen >= 4)
4586                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4587
4588         if (crtc->config.sdvo_tv_clock)
4589                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4590         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4591                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4592                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4593         else
4594                 dpll |= PLL_REF_INPUT_DREFCLK;
4595
4596         dpll |= DPLL_VCO_ENABLE;
4597         crtc->config.dpll_hw_state.dpll = dpll;
4598
4599         if (INTEL_INFO(dev)->gen >= 4) {
4600                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4601                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4602                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4603         }
4604
4605         if (crtc->config.has_dp_encoder)
4606                 intel_dp_set_m_n(crtc);
4607 }
4608
4609 static void i8xx_update_pll(struct intel_crtc *crtc,
4610                             intel_clock_t *reduced_clock,
4611                             int num_connectors)
4612 {
4613         struct drm_device *dev = crtc->base.dev;
4614         struct drm_i915_private *dev_priv = dev->dev_private;
4615         u32 dpll;
4616         struct dpll *clock = &crtc->config.dpll;
4617
4618         i9xx_update_pll_dividers(crtc, reduced_clock);
4619
4620         dpll = DPLL_VGA_MODE_DIS;
4621
4622         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4623                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4624         } else {
4625                 if (clock->p1 == 2)
4626                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4627                 else
4628                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4629                 if (clock->p2 == 4)
4630                         dpll |= PLL_P2_DIVIDE_BY_4;
4631         }
4632
4633         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4634                 dpll |= DPLL_DVO_2X_MODE;
4635
4636         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4637                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4638                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4639         else
4640                 dpll |= PLL_REF_INPUT_DREFCLK;
4641
4642         dpll |= DPLL_VCO_ENABLE;
4643         crtc->config.dpll_hw_state.dpll = dpll;
4644 }
4645
4646 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4647 {
4648         struct drm_device *dev = intel_crtc->base.dev;
4649         struct drm_i915_private *dev_priv = dev->dev_private;
4650         enum pipe pipe = intel_crtc->pipe;
4651         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4652         struct drm_display_mode *adjusted_mode =
4653                 &intel_crtc->config.adjusted_mode;
4654         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4655         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4656
4657         /* We need to be careful not to changed the adjusted mode, for otherwise
4658          * the hw state checker will get angry at the mismatch. */
4659         crtc_vtotal = adjusted_mode->crtc_vtotal;
4660         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4661
4662         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4663                 /* the chip adds 2 halflines automatically */
4664                 crtc_vtotal -= 1;
4665                 crtc_vblank_end -= 1;
4666                 vsyncshift = adjusted_mode->crtc_hsync_start
4667                              - adjusted_mode->crtc_htotal / 2;
4668         } else {
4669                 vsyncshift = 0;
4670         }
4671
4672         if (INTEL_INFO(dev)->gen > 3)
4673                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4674
4675         I915_WRITE(HTOTAL(cpu_transcoder),
4676                    (adjusted_mode->crtc_hdisplay - 1) |
4677                    ((adjusted_mode->crtc_htotal - 1) << 16));
4678         I915_WRITE(HBLANK(cpu_transcoder),
4679                    (adjusted_mode->crtc_hblank_start - 1) |
4680                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4681         I915_WRITE(HSYNC(cpu_transcoder),
4682                    (adjusted_mode->crtc_hsync_start - 1) |
4683                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4684
4685         I915_WRITE(VTOTAL(cpu_transcoder),
4686                    (adjusted_mode->crtc_vdisplay - 1) |
4687                    ((crtc_vtotal - 1) << 16));
4688         I915_WRITE(VBLANK(cpu_transcoder),
4689                    (adjusted_mode->crtc_vblank_start - 1) |
4690                    ((crtc_vblank_end - 1) << 16));
4691         I915_WRITE(VSYNC(cpu_transcoder),
4692                    (adjusted_mode->crtc_vsync_start - 1) |
4693                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4694
4695         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4696          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4697          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4698          * bits. */
4699         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4700             (pipe == PIPE_B || pipe == PIPE_C))
4701                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4702
4703         /* pipesrc controls the size that is scaled from, which should
4704          * always be the user's requested size.
4705          */
4706         I915_WRITE(PIPESRC(pipe),
4707                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4708 }
4709
4710 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4711                                    struct intel_crtc_config *pipe_config)
4712 {
4713         struct drm_device *dev = crtc->base.dev;
4714         struct drm_i915_private *dev_priv = dev->dev_private;
4715         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4716         uint32_t tmp;
4717
4718         tmp = I915_READ(HTOTAL(cpu_transcoder));
4719         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4720         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4721         tmp = I915_READ(HBLANK(cpu_transcoder));
4722         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4723         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4724         tmp = I915_READ(HSYNC(cpu_transcoder));
4725         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4726         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4727
4728         tmp = I915_READ(VTOTAL(cpu_transcoder));
4729         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4730         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4731         tmp = I915_READ(VBLANK(cpu_transcoder));
4732         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4733         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4734         tmp = I915_READ(VSYNC(cpu_transcoder));
4735         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4736         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4737
4738         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4739                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4740                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4741                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4742         }
4743
4744         tmp = I915_READ(PIPESRC(crtc->pipe));
4745         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4746         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4747 }
4748
4749 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4750                                              struct intel_crtc_config *pipe_config)
4751 {
4752         struct drm_crtc *crtc = &intel_crtc->base;
4753
4754         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4755         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4756         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4757         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4758
4759         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4760         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4761         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4762         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4763
4764         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4765
4766         crtc->mode.clock = pipe_config->adjusted_mode.clock;
4767         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4768 }
4769
4770 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4771 {
4772         struct drm_device *dev = intel_crtc->base.dev;
4773         struct drm_i915_private *dev_priv = dev->dev_private;
4774         uint32_t pipeconf;
4775
4776         pipeconf = 0;
4777
4778         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4779             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4780                 pipeconf |= PIPECONF_ENABLE;
4781
4782         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4783                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4784                  * core speed.
4785                  *
4786                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4787                  * pipe == 0 check?
4788                  */
4789                 if (intel_crtc->config.requested_mode.clock >
4790                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4791                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4792         }
4793
4794         /* only g4x and later have fancy bpc/dither controls */
4795         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4796                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4797                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4798                         pipeconf |= PIPECONF_DITHER_EN |
4799                                     PIPECONF_DITHER_TYPE_SP;
4800
4801                 switch (intel_crtc->config.pipe_bpp) {
4802                 case 18:
4803                         pipeconf |= PIPECONF_6BPC;
4804                         break;
4805                 case 24:
4806                         pipeconf |= PIPECONF_8BPC;
4807                         break;
4808                 case 30:
4809                         pipeconf |= PIPECONF_10BPC;
4810                         break;
4811                 default:
4812                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4813                         BUG();
4814                 }
4815         }
4816
4817         if (HAS_PIPE_CXSR(dev)) {
4818                 if (intel_crtc->lowfreq_avail) {
4819                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4820                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4821                 } else {
4822                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4823                 }
4824         }
4825
4826         if (!IS_GEN2(dev) &&
4827             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4828                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4829         else
4830                 pipeconf |= PIPECONF_PROGRESSIVE;
4831
4832         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4833                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4834
4835         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4836         POSTING_READ(PIPECONF(intel_crtc->pipe));
4837 }
4838
4839 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4840                               int x, int y,
4841                               struct drm_framebuffer *fb)
4842 {
4843         struct drm_device *dev = crtc->dev;
4844         struct drm_i915_private *dev_priv = dev->dev_private;
4845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4846         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4847         int pipe = intel_crtc->pipe;
4848         int plane = intel_crtc->plane;
4849         int refclk, num_connectors = 0;
4850         intel_clock_t clock, reduced_clock;
4851         u32 dspcntr;
4852         bool ok, has_reduced_clock = false;
4853         bool is_lvds = false;
4854         struct intel_encoder *encoder;
4855         const intel_limit_t *limit;
4856         int ret;
4857
4858         for_each_encoder_on_crtc(dev, crtc, encoder) {
4859                 switch (encoder->type) {
4860                 case INTEL_OUTPUT_LVDS:
4861                         is_lvds = true;
4862                         break;
4863                 }
4864
4865                 num_connectors++;
4866         }
4867
4868         refclk = i9xx_get_refclk(crtc, num_connectors);
4869
4870         /*
4871          * Returns a set of divisors for the desired target clock with the given
4872          * refclk, or FALSE.  The returned values represent the clock equation:
4873          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4874          */
4875         limit = intel_limit(crtc, refclk);
4876         ok = dev_priv->display.find_dpll(limit, crtc,
4877                                          intel_crtc->config.port_clock,
4878                                          refclk, NULL, &clock);
4879         if (!ok && !intel_crtc->config.clock_set) {
4880                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4881                 return -EINVAL;
4882         }
4883
4884         if (is_lvds && dev_priv->lvds_downclock_avail) {
4885                 /*
4886                  * Ensure we match the reduced clock's P to the target clock.
4887                  * If the clocks don't match, we can't switch the display clock
4888                  * by using the FP0/FP1. In such case we will disable the LVDS
4889                  * downclock feature.
4890                 */
4891                 has_reduced_clock =
4892                         dev_priv->display.find_dpll(limit, crtc,
4893                                                     dev_priv->lvds_downclock,
4894                                                     refclk, &clock,
4895                                                     &reduced_clock);
4896         }
4897         /* Compat-code for transition, will disappear. */
4898         if (!intel_crtc->config.clock_set) {
4899                 intel_crtc->config.dpll.n = clock.n;
4900                 intel_crtc->config.dpll.m1 = clock.m1;
4901                 intel_crtc->config.dpll.m2 = clock.m2;
4902                 intel_crtc->config.dpll.p1 = clock.p1;
4903                 intel_crtc->config.dpll.p2 = clock.p2;
4904         }
4905
4906         if (IS_GEN2(dev))
4907                 i8xx_update_pll(intel_crtc,
4908                                 has_reduced_clock ? &reduced_clock : NULL,
4909                                 num_connectors);
4910         else if (IS_VALLEYVIEW(dev))
4911                 vlv_update_pll(intel_crtc);
4912         else
4913                 i9xx_update_pll(intel_crtc,
4914                                 has_reduced_clock ? &reduced_clock : NULL,
4915                                 num_connectors);
4916
4917         /* Set up the display plane register */
4918         dspcntr = DISPPLANE_GAMMA_ENABLE;
4919
4920         if (!IS_VALLEYVIEW(dev)) {
4921                 if (pipe == 0)
4922                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4923                 else
4924                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4925         }
4926
4927         intel_set_pipe_timings(intel_crtc);
4928
4929         /* pipesrc and dspsize control the size that is scaled from,
4930          * which should always be the user's requested size.
4931          */
4932         I915_WRITE(DSPSIZE(plane),
4933                    ((mode->vdisplay - 1) << 16) |
4934                    (mode->hdisplay - 1));
4935         I915_WRITE(DSPPOS(plane), 0);
4936
4937         i9xx_set_pipeconf(intel_crtc);
4938
4939         I915_WRITE(DSPCNTR(plane), dspcntr);
4940         POSTING_READ(DSPCNTR(plane));
4941
4942         ret = intel_pipe_set_base(crtc, x, y, fb);
4943
4944         intel_update_watermarks(dev);
4945
4946         return ret;
4947 }
4948
4949 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4950                                  struct intel_crtc_config *pipe_config)
4951 {
4952         struct drm_device *dev = crtc->base.dev;
4953         struct drm_i915_private *dev_priv = dev->dev_private;
4954         uint32_t tmp;
4955
4956         tmp = I915_READ(PFIT_CONTROL);
4957         if (!(tmp & PFIT_ENABLE))
4958                 return;
4959
4960         /* Check whether the pfit is attached to our pipe. */
4961         if (INTEL_INFO(dev)->gen < 4) {
4962                 if (crtc->pipe != PIPE_B)
4963                         return;
4964         } else {
4965                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4966                         return;
4967         }
4968
4969         pipe_config->gmch_pfit.control = tmp;
4970         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4971         if (INTEL_INFO(dev)->gen < 5)
4972                 pipe_config->gmch_pfit.lvds_border_bits =
4973                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4974 }
4975
4976 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4977                                  struct intel_crtc_config *pipe_config)
4978 {
4979         struct drm_device *dev = crtc->base.dev;
4980         struct drm_i915_private *dev_priv = dev->dev_private;
4981         uint32_t tmp;
4982
4983         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
4984         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4985
4986         tmp = I915_READ(PIPECONF(crtc->pipe));
4987         if (!(tmp & PIPECONF_ENABLE))
4988                 return false;
4989
4990         intel_get_pipe_timings(crtc, pipe_config);
4991
4992         i9xx_get_pfit_config(crtc, pipe_config);
4993
4994         if (INTEL_INFO(dev)->gen >= 4) {
4995                 tmp = I915_READ(DPLL_MD(crtc->pipe));
4996                 pipe_config->pixel_multiplier =
4997                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4998                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4999                 pipe_config->dpll_hw_state.dpll_md = tmp;
5000         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5001                 tmp = I915_READ(DPLL(crtc->pipe));
5002                 pipe_config->pixel_multiplier =
5003                         ((tmp & SDVO_MULTIPLIER_MASK)
5004                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5005         } else {
5006                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5007                  * port and will be fixed up in the encoder->get_config
5008                  * function. */
5009                 pipe_config->pixel_multiplier = 1;
5010         }
5011         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5012         if (!IS_VALLEYVIEW(dev)) {
5013                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5014                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5015         } else {
5016                 /* Mask out read-only status bits. */
5017                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5018                                                      DPLL_PORTC_READY_MASK |
5019                                                      DPLL_PORTB_READY_MASK);
5020         }
5021
5022         return true;
5023 }
5024
5025 static void ironlake_init_pch_refclk(struct drm_device *dev)
5026 {
5027         struct drm_i915_private *dev_priv = dev->dev_private;
5028         struct drm_mode_config *mode_config = &dev->mode_config;
5029         struct intel_encoder *encoder;
5030         u32 val, final;
5031         bool has_lvds = false;
5032         bool has_cpu_edp = false;
5033         bool has_panel = false;
5034         bool has_ck505 = false;
5035         bool can_ssc = false;
5036
5037         /* We need to take the global config into account */
5038         list_for_each_entry(encoder, &mode_config->encoder_list,
5039                             base.head) {
5040                 switch (encoder->type) {
5041                 case INTEL_OUTPUT_LVDS:
5042                         has_panel = true;
5043                         has_lvds = true;
5044                         break;
5045                 case INTEL_OUTPUT_EDP:
5046                         has_panel = true;
5047                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5048                                 has_cpu_edp = true;
5049                         break;
5050                 }
5051         }
5052
5053         if (HAS_PCH_IBX(dev)) {
5054                 has_ck505 = dev_priv->vbt.display_clock_mode;
5055                 can_ssc = has_ck505;
5056         } else {
5057                 has_ck505 = false;
5058                 can_ssc = true;
5059         }
5060
5061         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5062                       has_panel, has_lvds, has_ck505);
5063
5064         /* Ironlake: try to setup display ref clock before DPLL
5065          * enabling. This is only under driver's control after
5066          * PCH B stepping, previous chipset stepping should be
5067          * ignoring this setting.
5068          */
5069         val = I915_READ(PCH_DREF_CONTROL);
5070
5071         /* As we must carefully and slowly disable/enable each source in turn,
5072          * compute the final state we want first and check if we need to
5073          * make any changes at all.
5074          */
5075         final = val;
5076         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5077         if (has_ck505)
5078                 final |= DREF_NONSPREAD_CK505_ENABLE;
5079         else
5080                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5081
5082         final &= ~DREF_SSC_SOURCE_MASK;
5083         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5084         final &= ~DREF_SSC1_ENABLE;
5085
5086         if (has_panel) {
5087                 final |= DREF_SSC_SOURCE_ENABLE;
5088
5089                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5090                         final |= DREF_SSC1_ENABLE;
5091
5092                 if (has_cpu_edp) {
5093                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5094                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5095                         else
5096                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5097                 } else
5098                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5099         } else {
5100                 final |= DREF_SSC_SOURCE_DISABLE;
5101                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5102         }
5103
5104         if (final == val)
5105                 return;
5106
5107         /* Always enable nonspread source */
5108         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5109
5110         if (has_ck505)
5111                 val |= DREF_NONSPREAD_CK505_ENABLE;
5112         else
5113                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5114
5115         if (has_panel) {
5116                 val &= ~DREF_SSC_SOURCE_MASK;
5117                 val |= DREF_SSC_SOURCE_ENABLE;
5118
5119                 /* SSC must be turned on before enabling the CPU output  */
5120                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5121                         DRM_DEBUG_KMS("Using SSC on panel\n");
5122                         val |= DREF_SSC1_ENABLE;
5123                 } else
5124                         val &= ~DREF_SSC1_ENABLE;
5125
5126                 /* Get SSC going before enabling the outputs */
5127                 I915_WRITE(PCH_DREF_CONTROL, val);
5128                 POSTING_READ(PCH_DREF_CONTROL);
5129                 udelay(200);
5130
5131                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5132
5133                 /* Enable CPU source on CPU attached eDP */
5134                 if (has_cpu_edp) {
5135                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5136                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5137                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5138                         }
5139                         else
5140                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5141                 } else
5142                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5143
5144                 I915_WRITE(PCH_DREF_CONTROL, val);
5145                 POSTING_READ(PCH_DREF_CONTROL);
5146                 udelay(200);
5147         } else {
5148                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5149
5150                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5151
5152                 /* Turn off CPU output */
5153                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5154
5155                 I915_WRITE(PCH_DREF_CONTROL, val);
5156                 POSTING_READ(PCH_DREF_CONTROL);
5157                 udelay(200);
5158
5159                 /* Turn off the SSC source */
5160                 val &= ~DREF_SSC_SOURCE_MASK;
5161                 val |= DREF_SSC_SOURCE_DISABLE;
5162
5163                 /* Turn off SSC1 */
5164                 val &= ~DREF_SSC1_ENABLE;
5165
5166                 I915_WRITE(PCH_DREF_CONTROL, val);
5167                 POSTING_READ(PCH_DREF_CONTROL);
5168                 udelay(200);
5169         }
5170
5171         BUG_ON(val != final);
5172 }
5173
5174 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5175 {
5176         uint32_t tmp;
5177
5178         tmp = I915_READ(SOUTH_CHICKEN2);
5179         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5180         I915_WRITE(SOUTH_CHICKEN2, tmp);
5181
5182         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5183                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5184                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5185
5186         tmp = I915_READ(SOUTH_CHICKEN2);
5187         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5188         I915_WRITE(SOUTH_CHICKEN2, tmp);
5189
5190         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5191                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5192                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5193 }
5194
5195 /* WaMPhyProgramming:hsw */
5196 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5197 {
5198         uint32_t tmp;
5199
5200         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5201         tmp &= ~(0xFF << 24);
5202         tmp |= (0x12 << 24);
5203         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5204
5205         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5206         tmp |= (1 << 11);
5207         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5208
5209         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5210         tmp |= (1 << 11);
5211         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5212
5213         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5214         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5215         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5216
5217         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5218         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5219         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5220
5221         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5222         tmp &= ~(7 << 13);
5223         tmp |= (5 << 13);
5224         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5225
5226         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5227         tmp &= ~(7 << 13);
5228         tmp |= (5 << 13);
5229         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5230
5231         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5232         tmp &= ~0xFF;
5233         tmp |= 0x1C;
5234         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5235
5236         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5237         tmp &= ~0xFF;
5238         tmp |= 0x1C;
5239         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5240
5241         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5242         tmp &= ~(0xFF << 16);
5243         tmp |= (0x1C << 16);
5244         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5245
5246         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5247         tmp &= ~(0xFF << 16);
5248         tmp |= (0x1C << 16);
5249         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5250
5251         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5252         tmp |= (1 << 27);
5253         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5254
5255         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5256         tmp |= (1 << 27);
5257         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5258
5259         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5260         tmp &= ~(0xF << 28);
5261         tmp |= (4 << 28);
5262         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5263
5264         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5265         tmp &= ~(0xF << 28);
5266         tmp |= (4 << 28);
5267         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5268 }
5269
5270 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5271  * Programming" based on the parameters passed:
5272  * - Sequence to enable CLKOUT_DP
5273  * - Sequence to enable CLKOUT_DP without spread
5274  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5275  */
5276 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5277                                  bool with_fdi)
5278 {
5279         struct drm_i915_private *dev_priv = dev->dev_private;
5280         uint32_t reg, tmp;
5281
5282         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5283                 with_spread = true;
5284         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5285                  with_fdi, "LP PCH doesn't have FDI\n"))
5286                 with_fdi = false;
5287
5288         mutex_lock(&dev_priv->dpio_lock);
5289
5290         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5291         tmp &= ~SBI_SSCCTL_DISABLE;
5292         tmp |= SBI_SSCCTL_PATHALT;
5293         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5294
5295         udelay(24);
5296
5297         if (with_spread) {
5298                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5299                 tmp &= ~SBI_SSCCTL_PATHALT;
5300                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5301
5302                 if (with_fdi) {
5303                         lpt_reset_fdi_mphy(dev_priv);
5304                         lpt_program_fdi_mphy(dev_priv);
5305                 }
5306         }
5307
5308         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5309                SBI_GEN0 : SBI_DBUFF0;
5310         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5311         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5312         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5313
5314         mutex_unlock(&dev_priv->dpio_lock);
5315 }
5316
5317 /* Sequence to disable CLKOUT_DP */
5318 static void lpt_disable_clkout_dp(struct drm_device *dev)
5319 {
5320         struct drm_i915_private *dev_priv = dev->dev_private;
5321         uint32_t reg, tmp;
5322
5323         mutex_lock(&dev_priv->dpio_lock);
5324
5325         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5326                SBI_GEN0 : SBI_DBUFF0;
5327         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5328         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5329         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5330
5331         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5332         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5333                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5334                         tmp |= SBI_SSCCTL_PATHALT;
5335                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5336                         udelay(32);
5337                 }
5338                 tmp |= SBI_SSCCTL_DISABLE;
5339                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5340         }
5341
5342         mutex_unlock(&dev_priv->dpio_lock);
5343 }
5344
5345 static void lpt_init_pch_refclk(struct drm_device *dev)
5346 {
5347         struct drm_mode_config *mode_config = &dev->mode_config;
5348         struct intel_encoder *encoder;
5349         bool has_vga = false;
5350
5351         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5352                 switch (encoder->type) {
5353                 case INTEL_OUTPUT_ANALOG:
5354                         has_vga = true;
5355                         break;
5356                 }
5357         }
5358
5359         if (has_vga)
5360                 lpt_enable_clkout_dp(dev, true, true);
5361         else
5362                 lpt_disable_clkout_dp(dev);
5363 }
5364
5365 /*
5366  * Initialize reference clocks when the driver loads
5367  */
5368 void intel_init_pch_refclk(struct drm_device *dev)
5369 {
5370         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5371                 ironlake_init_pch_refclk(dev);
5372         else if (HAS_PCH_LPT(dev))
5373                 lpt_init_pch_refclk(dev);
5374 }
5375
5376 static int ironlake_get_refclk(struct drm_crtc *crtc)
5377 {
5378         struct drm_device *dev = crtc->dev;
5379         struct drm_i915_private *dev_priv = dev->dev_private;
5380         struct intel_encoder *encoder;
5381         int num_connectors = 0;
5382         bool is_lvds = false;
5383
5384         for_each_encoder_on_crtc(dev, crtc, encoder) {
5385                 switch (encoder->type) {
5386                 case INTEL_OUTPUT_LVDS:
5387                         is_lvds = true;
5388                         break;
5389                 }
5390                 num_connectors++;
5391         }
5392
5393         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5394                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5395                               dev_priv->vbt.lvds_ssc_freq);
5396                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5397         }
5398
5399         return 120000;
5400 }
5401
5402 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5403 {
5404         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5406         int pipe = intel_crtc->pipe;
5407         uint32_t val;
5408
5409         val = 0;
5410
5411         switch (intel_crtc->config.pipe_bpp) {
5412         case 18:
5413                 val |= PIPECONF_6BPC;
5414                 break;
5415         case 24:
5416                 val |= PIPECONF_8BPC;
5417                 break;
5418         case 30:
5419                 val |= PIPECONF_10BPC;
5420                 break;
5421         case 36:
5422                 val |= PIPECONF_12BPC;
5423                 break;
5424         default:
5425                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5426                 BUG();
5427         }
5428
5429         if (intel_crtc->config.dither)
5430                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5431
5432         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5433                 val |= PIPECONF_INTERLACED_ILK;
5434         else
5435                 val |= PIPECONF_PROGRESSIVE;
5436
5437         if (intel_crtc->config.limited_color_range)
5438                 val |= PIPECONF_COLOR_RANGE_SELECT;
5439
5440         I915_WRITE(PIPECONF(pipe), val);
5441         POSTING_READ(PIPECONF(pipe));
5442 }
5443
5444 /*
5445  * Set up the pipe CSC unit.
5446  *
5447  * Currently only full range RGB to limited range RGB conversion
5448  * is supported, but eventually this should handle various
5449  * RGB<->YCbCr scenarios as well.
5450  */
5451 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5452 {
5453         struct drm_device *dev = crtc->dev;
5454         struct drm_i915_private *dev_priv = dev->dev_private;
5455         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5456         int pipe = intel_crtc->pipe;
5457         uint16_t coeff = 0x7800; /* 1.0 */
5458
5459         /*
5460          * TODO: Check what kind of values actually come out of the pipe
5461          * with these coeff/postoff values and adjust to get the best
5462          * accuracy. Perhaps we even need to take the bpc value into
5463          * consideration.
5464          */
5465
5466         if (intel_crtc->config.limited_color_range)
5467                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5468
5469         /*
5470          * GY/GU and RY/RU should be the other way around according
5471          * to BSpec, but reality doesn't agree. Just set them up in
5472          * a way that results in the correct picture.
5473          */
5474         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5475         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5476
5477         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5478         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5479
5480         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5481         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5482
5483         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5484         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5485         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5486
5487         if (INTEL_INFO(dev)->gen > 6) {
5488                 uint16_t postoff = 0;
5489
5490                 if (intel_crtc->config.limited_color_range)
5491                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5492
5493                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5494                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5495                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5496
5497                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5498         } else {
5499                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5500
5501                 if (intel_crtc->config.limited_color_range)
5502                         mode |= CSC_BLACK_SCREEN_OFFSET;
5503
5504                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5505         }
5506 }
5507
5508 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5509 {
5510         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5512         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5513         uint32_t val;
5514
5515         val = 0;
5516
5517         if (intel_crtc->config.dither)
5518                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5519
5520         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5521                 val |= PIPECONF_INTERLACED_ILK;
5522         else
5523                 val |= PIPECONF_PROGRESSIVE;
5524
5525         I915_WRITE(PIPECONF(cpu_transcoder), val);
5526         POSTING_READ(PIPECONF(cpu_transcoder));
5527
5528         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5529         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5530 }
5531
5532 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5533                                     intel_clock_t *clock,
5534                                     bool *has_reduced_clock,
5535                                     intel_clock_t *reduced_clock)
5536 {
5537         struct drm_device *dev = crtc->dev;
5538         struct drm_i915_private *dev_priv = dev->dev_private;
5539         struct intel_encoder *intel_encoder;
5540         int refclk;
5541         const intel_limit_t *limit;
5542         bool ret, is_lvds = false;
5543
5544         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5545                 switch (intel_encoder->type) {
5546                 case INTEL_OUTPUT_LVDS:
5547                         is_lvds = true;
5548                         break;
5549                 }
5550         }
5551
5552         refclk = ironlake_get_refclk(crtc);
5553
5554         /*
5555          * Returns a set of divisors for the desired target clock with the given
5556          * refclk, or FALSE.  The returned values represent the clock equation:
5557          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5558          */
5559         limit = intel_limit(crtc, refclk);
5560         ret = dev_priv->display.find_dpll(limit, crtc,
5561                                           to_intel_crtc(crtc)->config.port_clock,
5562                                           refclk, NULL, clock);
5563         if (!ret)
5564                 return false;
5565
5566         if (is_lvds && dev_priv->lvds_downclock_avail) {
5567                 /*
5568                  * Ensure we match the reduced clock's P to the target clock.
5569                  * If the clocks don't match, we can't switch the display clock
5570                  * by using the FP0/FP1. In such case we will disable the LVDS
5571                  * downclock feature.
5572                 */
5573                 *has_reduced_clock =
5574                         dev_priv->display.find_dpll(limit, crtc,
5575                                                     dev_priv->lvds_downclock,
5576                                                     refclk, clock,
5577                                                     reduced_clock);
5578         }
5579
5580         return true;
5581 }
5582
5583 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5584 {
5585         struct drm_i915_private *dev_priv = dev->dev_private;
5586         uint32_t temp;
5587
5588         temp = I915_READ(SOUTH_CHICKEN1);
5589         if (temp & FDI_BC_BIFURCATION_SELECT)
5590                 return;
5591
5592         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5593         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5594
5595         temp |= FDI_BC_BIFURCATION_SELECT;
5596         DRM_DEBUG_KMS("enabling fdi C rx\n");
5597         I915_WRITE(SOUTH_CHICKEN1, temp);
5598         POSTING_READ(SOUTH_CHICKEN1);
5599 }
5600
5601 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5602 {
5603         struct drm_device *dev = intel_crtc->base.dev;
5604         struct drm_i915_private *dev_priv = dev->dev_private;
5605
5606         switch (intel_crtc->pipe) {
5607         case PIPE_A:
5608                 break;
5609         case PIPE_B:
5610                 if (intel_crtc->config.fdi_lanes > 2)
5611                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5612                 else
5613                         cpt_enable_fdi_bc_bifurcation(dev);
5614
5615                 break;
5616         case PIPE_C:
5617                 cpt_enable_fdi_bc_bifurcation(dev);
5618
5619                 break;
5620         default:
5621                 BUG();
5622         }
5623 }
5624
5625 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5626 {
5627         /*
5628          * Account for spread spectrum to avoid
5629          * oversubscribing the link. Max center spread
5630          * is 2.5%; use 5% for safety's sake.
5631          */
5632         u32 bps = target_clock * bpp * 21 / 20;
5633         return bps / (link_bw * 8) + 1;
5634 }
5635
5636 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5637 {
5638         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5639 }
5640
5641 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5642                                       u32 *fp,
5643                                       intel_clock_t *reduced_clock, u32 *fp2)
5644 {
5645         struct drm_crtc *crtc = &intel_crtc->base;
5646         struct drm_device *dev = crtc->dev;
5647         struct drm_i915_private *dev_priv = dev->dev_private;
5648         struct intel_encoder *intel_encoder;
5649         uint32_t dpll;
5650         int factor, num_connectors = 0;
5651         bool is_lvds = false, is_sdvo = false;
5652
5653         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5654                 switch (intel_encoder->type) {
5655                 case INTEL_OUTPUT_LVDS:
5656                         is_lvds = true;
5657                         break;
5658                 case INTEL_OUTPUT_SDVO:
5659                 case INTEL_OUTPUT_HDMI:
5660                         is_sdvo = true;
5661                         break;
5662                 }
5663
5664                 num_connectors++;
5665         }
5666
5667         /* Enable autotuning of the PLL clock (if permissible) */
5668         factor = 21;
5669         if (is_lvds) {
5670                 if ((intel_panel_use_ssc(dev_priv) &&
5671                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5672                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5673                         factor = 25;
5674         } else if (intel_crtc->config.sdvo_tv_clock)
5675                 factor = 20;
5676
5677         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5678                 *fp |= FP_CB_TUNE;
5679
5680         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5681                 *fp2 |= FP_CB_TUNE;
5682
5683         dpll = 0;
5684
5685         if (is_lvds)
5686                 dpll |= DPLLB_MODE_LVDS;
5687         else
5688                 dpll |= DPLLB_MODE_DAC_SERIAL;
5689
5690         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5691                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5692
5693         if (is_sdvo)
5694                 dpll |= DPLL_SDVO_HIGH_SPEED;
5695         if (intel_crtc->config.has_dp_encoder)
5696                 dpll |= DPLL_SDVO_HIGH_SPEED;
5697
5698         /* compute bitmask from p1 value */
5699         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5700         /* also FPA1 */
5701         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5702
5703         switch (intel_crtc->config.dpll.p2) {
5704         case 5:
5705                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5706                 break;
5707         case 7:
5708                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5709                 break;
5710         case 10:
5711                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5712                 break;
5713         case 14:
5714                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5715                 break;
5716         }
5717
5718         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5719                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5720         else
5721                 dpll |= PLL_REF_INPUT_DREFCLK;
5722
5723         return dpll | DPLL_VCO_ENABLE;
5724 }
5725
5726 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5727                                   int x, int y,
5728                                   struct drm_framebuffer *fb)
5729 {
5730         struct drm_device *dev = crtc->dev;
5731         struct drm_i915_private *dev_priv = dev->dev_private;
5732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5733         int pipe = intel_crtc->pipe;
5734         int plane = intel_crtc->plane;
5735         int num_connectors = 0;
5736         intel_clock_t clock, reduced_clock;
5737         u32 dpll = 0, fp = 0, fp2 = 0;
5738         bool ok, has_reduced_clock = false;
5739         bool is_lvds = false;
5740         struct intel_encoder *encoder;
5741         struct intel_shared_dpll *pll;
5742         int ret;
5743
5744         for_each_encoder_on_crtc(dev, crtc, encoder) {
5745                 switch (encoder->type) {
5746                 case INTEL_OUTPUT_LVDS:
5747                         is_lvds = true;
5748                         break;
5749                 }
5750
5751                 num_connectors++;
5752         }
5753
5754         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5755              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5756
5757         ok = ironlake_compute_clocks(crtc, &clock,
5758                                      &has_reduced_clock, &reduced_clock);
5759         if (!ok && !intel_crtc->config.clock_set) {
5760                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5761                 return -EINVAL;
5762         }
5763         /* Compat-code for transition, will disappear. */
5764         if (!intel_crtc->config.clock_set) {
5765                 intel_crtc->config.dpll.n = clock.n;
5766                 intel_crtc->config.dpll.m1 = clock.m1;
5767                 intel_crtc->config.dpll.m2 = clock.m2;
5768                 intel_crtc->config.dpll.p1 = clock.p1;
5769                 intel_crtc->config.dpll.p2 = clock.p2;
5770         }
5771
5772         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5773         if (intel_crtc->config.has_pch_encoder) {
5774                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5775                 if (has_reduced_clock)
5776                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5777
5778                 dpll = ironlake_compute_dpll(intel_crtc,
5779                                              &fp, &reduced_clock,
5780                                              has_reduced_clock ? &fp2 : NULL);
5781
5782                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5783                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5784                 if (has_reduced_clock)
5785                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5786                 else
5787                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5788
5789                 pll = intel_get_shared_dpll(intel_crtc);
5790                 if (pll == NULL) {
5791                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5792                                          pipe_name(pipe));
5793                         return -EINVAL;
5794                 }
5795         } else
5796                 intel_put_shared_dpll(intel_crtc);
5797
5798         if (intel_crtc->config.has_dp_encoder)
5799                 intel_dp_set_m_n(intel_crtc);
5800
5801         if (is_lvds && has_reduced_clock && i915_powersave)
5802                 intel_crtc->lowfreq_avail = true;
5803         else
5804                 intel_crtc->lowfreq_avail = false;
5805
5806         if (intel_crtc->config.has_pch_encoder) {
5807                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5808
5809         }
5810
5811         intel_set_pipe_timings(intel_crtc);
5812
5813         if (intel_crtc->config.has_pch_encoder) {
5814                 intel_cpu_transcoder_set_m_n(intel_crtc,
5815                                              &intel_crtc->config.fdi_m_n);
5816         }
5817
5818         if (IS_IVYBRIDGE(dev))
5819                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5820
5821         ironlake_set_pipeconf(crtc);
5822
5823         /* Set up the display plane register */
5824         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5825         POSTING_READ(DSPCNTR(plane));
5826
5827         ret = intel_pipe_set_base(crtc, x, y, fb);
5828
5829         intel_update_watermarks(dev);
5830
5831         return ret;
5832 }
5833
5834 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5835                                         struct intel_crtc_config *pipe_config)
5836 {
5837         struct drm_device *dev = crtc->base.dev;
5838         struct drm_i915_private *dev_priv = dev->dev_private;
5839         enum transcoder transcoder = pipe_config->cpu_transcoder;
5840
5841         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5842         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5843         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5844                                         & ~TU_SIZE_MASK;
5845         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5846         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5847                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5848 }
5849
5850 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5851                                      struct intel_crtc_config *pipe_config)
5852 {
5853         struct drm_device *dev = crtc->base.dev;
5854         struct drm_i915_private *dev_priv = dev->dev_private;
5855         uint32_t tmp;
5856
5857         tmp = I915_READ(PF_CTL(crtc->pipe));
5858
5859         if (tmp & PF_ENABLE) {
5860                 pipe_config->pch_pfit.enabled = true;
5861                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5862                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5863
5864                 /* We currently do not free assignements of panel fitters on
5865                  * ivb/hsw (since we don't use the higher upscaling modes which
5866                  * differentiates them) so just WARN about this case for now. */
5867                 if (IS_GEN7(dev)) {
5868                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5869                                 PF_PIPE_SEL_IVB(crtc->pipe));
5870                 }
5871         }
5872 }
5873
5874 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5875                                      struct intel_crtc_config *pipe_config)
5876 {
5877         struct drm_device *dev = crtc->base.dev;
5878         struct drm_i915_private *dev_priv = dev->dev_private;
5879         uint32_t tmp;
5880
5881         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5882         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5883
5884         tmp = I915_READ(PIPECONF(crtc->pipe));
5885         if (!(tmp & PIPECONF_ENABLE))
5886                 return false;
5887
5888         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5889                 struct intel_shared_dpll *pll;
5890
5891                 pipe_config->has_pch_encoder = true;
5892
5893                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5894                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5895                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5896
5897                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5898
5899                 if (HAS_PCH_IBX(dev_priv->dev)) {
5900                         pipe_config->shared_dpll =
5901                                 (enum intel_dpll_id) crtc->pipe;
5902                 } else {
5903                         tmp = I915_READ(PCH_DPLL_SEL);
5904                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5905                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5906                         else
5907                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5908                 }
5909
5910                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5911
5912                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5913                                            &pipe_config->dpll_hw_state));
5914
5915                 tmp = pipe_config->dpll_hw_state.dpll;
5916                 pipe_config->pixel_multiplier =
5917                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5918                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5919         } else {
5920                 pipe_config->pixel_multiplier = 1;
5921         }
5922
5923         intel_get_pipe_timings(crtc, pipe_config);
5924
5925         ironlake_get_pfit_config(crtc, pipe_config);
5926
5927         return true;
5928 }
5929
5930 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5931 {
5932         struct drm_device *dev = dev_priv->dev;
5933         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5934         struct intel_crtc *crtc;
5935         unsigned long irqflags;
5936         uint32_t val;
5937
5938         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5939                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5940                      pipe_name(crtc->pipe));
5941
5942         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5943         WARN(plls->spll_refcount, "SPLL enabled\n");
5944         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5945         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5946         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5947         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5948              "CPU PWM1 enabled\n");
5949         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5950              "CPU PWM2 enabled\n");
5951         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5952              "PCH PWM1 enabled\n");
5953         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5954              "Utility pin enabled\n");
5955         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5956
5957         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5958         val = I915_READ(DEIMR);
5959         WARN((val & ~DE_PCH_EVENT_IVB) != val,
5960              "Unexpected DEIMR bits enabled: 0x%x\n", val);
5961         val = I915_READ(SDEIMR);
5962         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
5963              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5964         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5965 }
5966
5967 /*
5968  * This function implements pieces of two sequences from BSpec:
5969  * - Sequence for display software to disable LCPLL
5970  * - Sequence for display software to allow package C8+
5971  * The steps implemented here are just the steps that actually touch the LCPLL
5972  * register. Callers should take care of disabling all the display engine
5973  * functions, doing the mode unset, fixing interrupts, etc.
5974  */
5975 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
5976                        bool switch_to_fclk, bool allow_power_down)
5977 {
5978         uint32_t val;
5979
5980         assert_can_disable_lcpll(dev_priv);
5981
5982         val = I915_READ(LCPLL_CTL);
5983
5984         if (switch_to_fclk) {
5985                 val |= LCPLL_CD_SOURCE_FCLK;
5986                 I915_WRITE(LCPLL_CTL, val);
5987
5988                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
5989                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
5990                         DRM_ERROR("Switching to FCLK failed\n");
5991
5992                 val = I915_READ(LCPLL_CTL);
5993         }
5994
5995         val |= LCPLL_PLL_DISABLE;
5996         I915_WRITE(LCPLL_CTL, val);
5997         POSTING_READ(LCPLL_CTL);
5998
5999         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6000                 DRM_ERROR("LCPLL still locked\n");
6001
6002         val = I915_READ(D_COMP);
6003         val |= D_COMP_COMP_DISABLE;
6004         I915_WRITE(D_COMP, val);
6005         POSTING_READ(D_COMP);
6006         ndelay(100);
6007
6008         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6009                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6010
6011         if (allow_power_down) {
6012                 val = I915_READ(LCPLL_CTL);
6013                 val |= LCPLL_POWER_DOWN_ALLOW;
6014                 I915_WRITE(LCPLL_CTL, val);
6015                 POSTING_READ(LCPLL_CTL);
6016         }
6017 }
6018
6019 /*
6020  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6021  * source.
6022  */
6023 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6024 {
6025         uint32_t val;
6026
6027         val = I915_READ(LCPLL_CTL);
6028
6029         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6030                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6031                 return;
6032
6033         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6034          * we'll hang the machine! */
6035         dev_priv->uncore.funcs.force_wake_get(dev_priv);
6036
6037         if (val & LCPLL_POWER_DOWN_ALLOW) {
6038                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6039                 I915_WRITE(LCPLL_CTL, val);
6040                 POSTING_READ(LCPLL_CTL);
6041         }
6042
6043         val = I915_READ(D_COMP);
6044         val |= D_COMP_COMP_FORCE;
6045         val &= ~D_COMP_COMP_DISABLE;
6046         I915_WRITE(D_COMP, val);
6047         POSTING_READ(D_COMP);
6048
6049         val = I915_READ(LCPLL_CTL);
6050         val &= ~LCPLL_PLL_DISABLE;
6051         I915_WRITE(LCPLL_CTL, val);
6052
6053         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6054                 DRM_ERROR("LCPLL not locked yet\n");
6055
6056         if (val & LCPLL_CD_SOURCE_FCLK) {
6057                 val = I915_READ(LCPLL_CTL);
6058                 val &= ~LCPLL_CD_SOURCE_FCLK;
6059                 I915_WRITE(LCPLL_CTL, val);
6060
6061                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6062                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6063                         DRM_ERROR("Switching back to LCPLL failed\n");
6064         }
6065
6066         dev_priv->uncore.funcs.force_wake_put(dev_priv);
6067 }
6068
6069 void hsw_enable_pc8_work(struct work_struct *__work)
6070 {
6071         struct drm_i915_private *dev_priv =
6072                 container_of(to_delayed_work(__work), struct drm_i915_private,
6073                              pc8.enable_work);
6074         struct drm_device *dev = dev_priv->dev;
6075         uint32_t val;
6076
6077         if (dev_priv->pc8.enabled)
6078                 return;
6079
6080         DRM_DEBUG_KMS("Enabling package C8+\n");
6081
6082         dev_priv->pc8.enabled = true;
6083
6084         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6085                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6086                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6087                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6088         }
6089
6090         lpt_disable_clkout_dp(dev);
6091         hsw_pc8_disable_interrupts(dev);
6092         hsw_disable_lcpll(dev_priv, true, true);
6093 }
6094
6095 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6096 {
6097         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6098         WARN(dev_priv->pc8.disable_count < 1,
6099              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6100
6101         dev_priv->pc8.disable_count--;
6102         if (dev_priv->pc8.disable_count != 0)
6103                 return;
6104
6105         schedule_delayed_work(&dev_priv->pc8.enable_work,
6106                               msecs_to_jiffies(i915_pc8_timeout));
6107 }
6108
6109 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6110 {
6111         struct drm_device *dev = dev_priv->dev;
6112         uint32_t val;
6113
6114         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6115         WARN(dev_priv->pc8.disable_count < 0,
6116              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6117
6118         dev_priv->pc8.disable_count++;
6119         if (dev_priv->pc8.disable_count != 1)
6120                 return;
6121
6122         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6123         if (!dev_priv->pc8.enabled)
6124                 return;
6125
6126         DRM_DEBUG_KMS("Disabling package C8+\n");
6127
6128         hsw_restore_lcpll(dev_priv);
6129         hsw_pc8_restore_interrupts(dev);
6130         lpt_init_pch_refclk(dev);
6131
6132         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6133                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6134                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6135                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6136         }
6137
6138         intel_prepare_ddi(dev);
6139         i915_gem_init_swizzling(dev);
6140         mutex_lock(&dev_priv->rps.hw_lock);
6141         gen6_update_ring_freq(dev);
6142         mutex_unlock(&dev_priv->rps.hw_lock);
6143         dev_priv->pc8.enabled = false;
6144 }
6145
6146 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6147 {
6148         mutex_lock(&dev_priv->pc8.lock);
6149         __hsw_enable_package_c8(dev_priv);
6150         mutex_unlock(&dev_priv->pc8.lock);
6151 }
6152
6153 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6154 {
6155         mutex_lock(&dev_priv->pc8.lock);
6156         __hsw_disable_package_c8(dev_priv);
6157         mutex_unlock(&dev_priv->pc8.lock);
6158 }
6159
6160 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6161 {
6162         struct drm_device *dev = dev_priv->dev;
6163         struct intel_crtc *crtc;
6164         uint32_t val;
6165
6166         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6167                 if (crtc->base.enabled)
6168                         return false;
6169
6170         /* This case is still possible since we have the i915.disable_power_well
6171          * parameter and also the KVMr or something else might be requesting the
6172          * power well. */
6173         val = I915_READ(HSW_PWR_WELL_DRIVER);
6174         if (val != 0) {
6175                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6176                 return false;
6177         }
6178
6179         return true;
6180 }
6181
6182 /* Since we're called from modeset_global_resources there's no way to
6183  * symmetrically increase and decrease the refcount, so we use
6184  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6185  * or not.
6186  */
6187 static void hsw_update_package_c8(struct drm_device *dev)
6188 {
6189         struct drm_i915_private *dev_priv = dev->dev_private;
6190         bool allow;
6191
6192         if (!i915_enable_pc8)
6193                 return;
6194
6195         mutex_lock(&dev_priv->pc8.lock);
6196
6197         allow = hsw_can_enable_package_c8(dev_priv);
6198
6199         if (allow == dev_priv->pc8.requirements_met)
6200                 goto done;
6201
6202         dev_priv->pc8.requirements_met = allow;
6203
6204         if (allow)
6205                 __hsw_enable_package_c8(dev_priv);
6206         else
6207                 __hsw_disable_package_c8(dev_priv);
6208
6209 done:
6210         mutex_unlock(&dev_priv->pc8.lock);
6211 }
6212
6213 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6214 {
6215         if (!dev_priv->pc8.gpu_idle) {
6216                 dev_priv->pc8.gpu_idle = true;
6217                 hsw_enable_package_c8(dev_priv);
6218         }
6219 }
6220
6221 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6222 {
6223         if (dev_priv->pc8.gpu_idle) {
6224                 dev_priv->pc8.gpu_idle = false;
6225                 hsw_disable_package_c8(dev_priv);
6226         }
6227 }
6228
6229 static void haswell_modeset_global_resources(struct drm_device *dev)
6230 {
6231         bool enable = false;
6232         struct intel_crtc *crtc;
6233
6234         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6235                 if (!crtc->base.enabled)
6236                         continue;
6237
6238                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
6239                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6240                         enable = true;
6241         }
6242
6243         intel_set_power_well(dev, enable);
6244
6245         hsw_update_package_c8(dev);
6246 }
6247
6248 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6249                                  int x, int y,
6250                                  struct drm_framebuffer *fb)
6251 {
6252         struct drm_device *dev = crtc->dev;
6253         struct drm_i915_private *dev_priv = dev->dev_private;
6254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6255         int plane = intel_crtc->plane;
6256         int ret;
6257
6258         if (!intel_ddi_pll_mode_set(crtc))
6259                 return -EINVAL;
6260
6261         if (intel_crtc->config.has_dp_encoder)
6262                 intel_dp_set_m_n(intel_crtc);
6263
6264         intel_crtc->lowfreq_avail = false;
6265
6266         intel_set_pipe_timings(intel_crtc);
6267
6268         if (intel_crtc->config.has_pch_encoder) {
6269                 intel_cpu_transcoder_set_m_n(intel_crtc,
6270                                              &intel_crtc->config.fdi_m_n);
6271         }
6272
6273         haswell_set_pipeconf(crtc);
6274
6275         intel_set_pipe_csc(crtc);
6276
6277         /* Set up the display plane register */
6278         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6279         POSTING_READ(DSPCNTR(plane));
6280
6281         ret = intel_pipe_set_base(crtc, x, y, fb);
6282
6283         intel_update_watermarks(dev);
6284
6285         return ret;
6286 }
6287
6288 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6289                                     struct intel_crtc_config *pipe_config)
6290 {
6291         struct drm_device *dev = crtc->base.dev;
6292         struct drm_i915_private *dev_priv = dev->dev_private;
6293         enum intel_display_power_domain pfit_domain;
6294         uint32_t tmp;
6295
6296         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6297         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6298
6299         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6300         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6301                 enum pipe trans_edp_pipe;
6302                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6303                 default:
6304                         WARN(1, "unknown pipe linked to edp transcoder\n");
6305                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6306                 case TRANS_DDI_EDP_INPUT_A_ON:
6307                         trans_edp_pipe = PIPE_A;
6308                         break;
6309                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6310                         trans_edp_pipe = PIPE_B;
6311                         break;
6312                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6313                         trans_edp_pipe = PIPE_C;
6314                         break;
6315                 }
6316
6317                 if (trans_edp_pipe == crtc->pipe)
6318                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6319         }
6320
6321         if (!intel_display_power_enabled(dev,
6322                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6323                 return false;
6324
6325         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6326         if (!(tmp & PIPECONF_ENABLE))
6327                 return false;
6328
6329         /*
6330          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6331          * DDI E. So just check whether this pipe is wired to DDI E and whether
6332          * the PCH transcoder is on.
6333          */
6334         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6335         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6336             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6337                 pipe_config->has_pch_encoder = true;
6338
6339                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6340                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6341                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6342
6343                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6344         }
6345
6346         intel_get_pipe_timings(crtc, pipe_config);
6347
6348         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6349         if (intel_display_power_enabled(dev, pfit_domain))
6350                 ironlake_get_pfit_config(crtc, pipe_config);
6351
6352         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6353                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6354
6355         pipe_config->pixel_multiplier = 1;
6356
6357         return true;
6358 }
6359
6360 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6361                                int x, int y,
6362                                struct drm_framebuffer *fb)
6363 {
6364         struct drm_device *dev = crtc->dev;
6365         struct drm_i915_private *dev_priv = dev->dev_private;
6366         struct intel_encoder *encoder;
6367         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6368         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6369         int pipe = intel_crtc->pipe;
6370         int ret;
6371
6372         drm_vblank_pre_modeset(dev, pipe);
6373
6374         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6375
6376         drm_vblank_post_modeset(dev, pipe);
6377
6378         if (ret != 0)
6379                 return ret;
6380
6381         for_each_encoder_on_crtc(dev, crtc, encoder) {
6382                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6383                         encoder->base.base.id,
6384                         drm_get_encoder_name(&encoder->base),
6385                         mode->base.id, mode->name);
6386                 encoder->mode_set(encoder);
6387         }
6388
6389         return 0;
6390 }
6391
6392 static bool intel_eld_uptodate(struct drm_connector *connector,
6393                                int reg_eldv, uint32_t bits_eldv,
6394                                int reg_elda, uint32_t bits_elda,
6395                                int reg_edid)
6396 {
6397         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6398         uint8_t *eld = connector->eld;
6399         uint32_t i;
6400
6401         i = I915_READ(reg_eldv);
6402         i &= bits_eldv;
6403
6404         if (!eld[0])
6405                 return !i;
6406
6407         if (!i)
6408                 return false;
6409
6410         i = I915_READ(reg_elda);
6411         i &= ~bits_elda;
6412         I915_WRITE(reg_elda, i);
6413
6414         for (i = 0; i < eld[2]; i++)
6415                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6416                         return false;
6417
6418         return true;
6419 }
6420
6421 static void g4x_write_eld(struct drm_connector *connector,
6422                           struct drm_crtc *crtc)
6423 {
6424         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6425         uint8_t *eld = connector->eld;
6426         uint32_t eldv;
6427         uint32_t len;
6428         uint32_t i;
6429
6430         i = I915_READ(G4X_AUD_VID_DID);
6431
6432         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6433                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6434         else
6435                 eldv = G4X_ELDV_DEVCTG;
6436
6437         if (intel_eld_uptodate(connector,
6438                                G4X_AUD_CNTL_ST, eldv,
6439                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6440                                G4X_HDMIW_HDMIEDID))
6441                 return;
6442
6443         i = I915_READ(G4X_AUD_CNTL_ST);
6444         i &= ~(eldv | G4X_ELD_ADDR);
6445         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6446         I915_WRITE(G4X_AUD_CNTL_ST, i);
6447
6448         if (!eld[0])
6449                 return;
6450
6451         len = min_t(uint8_t, eld[2], len);
6452         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6453         for (i = 0; i < len; i++)
6454                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6455
6456         i = I915_READ(G4X_AUD_CNTL_ST);
6457         i |= eldv;
6458         I915_WRITE(G4X_AUD_CNTL_ST, i);
6459 }
6460
6461 static void haswell_write_eld(struct drm_connector *connector,
6462                                      struct drm_crtc *crtc)
6463 {
6464         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6465         uint8_t *eld = connector->eld;
6466         struct drm_device *dev = crtc->dev;
6467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6468         uint32_t eldv;
6469         uint32_t i;
6470         int len;
6471         int pipe = to_intel_crtc(crtc)->pipe;
6472         int tmp;
6473
6474         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6475         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6476         int aud_config = HSW_AUD_CFG(pipe);
6477         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6478
6479
6480         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6481
6482         /* Audio output enable */
6483         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6484         tmp = I915_READ(aud_cntrl_st2);
6485         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6486         I915_WRITE(aud_cntrl_st2, tmp);
6487
6488         /* Wait for 1 vertical blank */
6489         intel_wait_for_vblank(dev, pipe);
6490
6491         /* Set ELD valid state */
6492         tmp = I915_READ(aud_cntrl_st2);
6493         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6494         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6495         I915_WRITE(aud_cntrl_st2, tmp);
6496         tmp = I915_READ(aud_cntrl_st2);
6497         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6498
6499         /* Enable HDMI mode */
6500         tmp = I915_READ(aud_config);
6501         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6502         /* clear N_programing_enable and N_value_index */
6503         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6504         I915_WRITE(aud_config, tmp);
6505
6506         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6507
6508         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6509         intel_crtc->eld_vld = true;
6510
6511         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6512                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6513                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6514                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6515         } else
6516                 I915_WRITE(aud_config, 0);
6517
6518         if (intel_eld_uptodate(connector,
6519                                aud_cntrl_st2, eldv,
6520                                aud_cntl_st, IBX_ELD_ADDRESS,
6521                                hdmiw_hdmiedid))
6522                 return;
6523
6524         i = I915_READ(aud_cntrl_st2);
6525         i &= ~eldv;
6526         I915_WRITE(aud_cntrl_st2, i);
6527
6528         if (!eld[0])
6529                 return;
6530
6531         i = I915_READ(aud_cntl_st);
6532         i &= ~IBX_ELD_ADDRESS;
6533         I915_WRITE(aud_cntl_st, i);
6534         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6535         DRM_DEBUG_DRIVER("port num:%d\n", i);
6536
6537         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6538         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6539         for (i = 0; i < len; i++)
6540                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6541
6542         i = I915_READ(aud_cntrl_st2);
6543         i |= eldv;
6544         I915_WRITE(aud_cntrl_st2, i);
6545
6546 }
6547
6548 static void ironlake_write_eld(struct drm_connector *connector,
6549                                      struct drm_crtc *crtc)
6550 {
6551         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6552         uint8_t *eld = connector->eld;
6553         uint32_t eldv;
6554         uint32_t i;
6555         int len;
6556         int hdmiw_hdmiedid;
6557         int aud_config;
6558         int aud_cntl_st;
6559         int aud_cntrl_st2;
6560         int pipe = to_intel_crtc(crtc)->pipe;
6561
6562         if (HAS_PCH_IBX(connector->dev)) {
6563                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6564                 aud_config = IBX_AUD_CFG(pipe);
6565                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6566                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6567         } else {
6568                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6569                 aud_config = CPT_AUD_CFG(pipe);
6570                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6571                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6572         }
6573
6574         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6575
6576         i = I915_READ(aud_cntl_st);
6577         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6578         if (!i) {
6579                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6580                 /* operate blindly on all ports */
6581                 eldv = IBX_ELD_VALIDB;
6582                 eldv |= IBX_ELD_VALIDB << 4;
6583                 eldv |= IBX_ELD_VALIDB << 8;
6584         } else {
6585                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6586                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6587         }
6588
6589         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6590                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6591                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6592                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6593         } else
6594                 I915_WRITE(aud_config, 0);
6595
6596         if (intel_eld_uptodate(connector,
6597                                aud_cntrl_st2, eldv,
6598                                aud_cntl_st, IBX_ELD_ADDRESS,
6599                                hdmiw_hdmiedid))
6600                 return;
6601
6602         i = I915_READ(aud_cntrl_st2);
6603         i &= ~eldv;
6604         I915_WRITE(aud_cntrl_st2, i);
6605
6606         if (!eld[0])
6607                 return;
6608
6609         i = I915_READ(aud_cntl_st);
6610         i &= ~IBX_ELD_ADDRESS;
6611         I915_WRITE(aud_cntl_st, i);
6612
6613         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6614         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6615         for (i = 0; i < len; i++)
6616                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6617
6618         i = I915_READ(aud_cntrl_st2);
6619         i |= eldv;
6620         I915_WRITE(aud_cntrl_st2, i);
6621 }
6622
6623 void intel_write_eld(struct drm_encoder *encoder,
6624                      struct drm_display_mode *mode)
6625 {
6626         struct drm_crtc *crtc = encoder->crtc;
6627         struct drm_connector *connector;
6628         struct drm_device *dev = encoder->dev;
6629         struct drm_i915_private *dev_priv = dev->dev_private;
6630
6631         connector = drm_select_eld(encoder, mode);
6632         if (!connector)
6633                 return;
6634
6635         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6636                          connector->base.id,
6637                          drm_get_connector_name(connector),
6638                          connector->encoder->base.id,
6639                          drm_get_encoder_name(connector->encoder));
6640
6641         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6642
6643         if (dev_priv->display.write_eld)
6644                 dev_priv->display.write_eld(connector, crtc);
6645 }
6646
6647 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6648 void intel_crtc_load_lut(struct drm_crtc *crtc)
6649 {
6650         struct drm_device *dev = crtc->dev;
6651         struct drm_i915_private *dev_priv = dev->dev_private;
6652         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6653         enum pipe pipe = intel_crtc->pipe;
6654         int palreg = PALETTE(pipe);
6655         int i;
6656         bool reenable_ips = false;
6657
6658         /* The clocks have to be on to load the palette. */
6659         if (!crtc->enabled || !intel_crtc->active)
6660                 return;
6661
6662         if (!HAS_PCH_SPLIT(dev_priv->dev))
6663                 assert_pll_enabled(dev_priv, pipe);
6664
6665         /* use legacy palette for Ironlake */
6666         if (HAS_PCH_SPLIT(dev))
6667                 palreg = LGC_PALETTE(pipe);
6668
6669         /* Workaround : Do not read or write the pipe palette/gamma data while
6670          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6671          */
6672         if (intel_crtc->config.ips_enabled &&
6673             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6674              GAMMA_MODE_MODE_SPLIT)) {
6675                 hsw_disable_ips(intel_crtc);
6676                 reenable_ips = true;
6677         }
6678
6679         for (i = 0; i < 256; i++) {
6680                 I915_WRITE(palreg + 4 * i,
6681                            (intel_crtc->lut_r[i] << 16) |
6682                            (intel_crtc->lut_g[i] << 8) |
6683                            intel_crtc->lut_b[i]);
6684         }
6685
6686         if (reenable_ips)
6687                 hsw_enable_ips(intel_crtc);
6688 }
6689
6690 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6691 {
6692         struct drm_device *dev = crtc->dev;
6693         struct drm_i915_private *dev_priv = dev->dev_private;
6694         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6695         bool visible = base != 0;
6696         u32 cntl;
6697
6698         if (intel_crtc->cursor_visible == visible)
6699                 return;
6700
6701         cntl = I915_READ(_CURACNTR);
6702         if (visible) {
6703                 /* On these chipsets we can only modify the base whilst
6704                  * the cursor is disabled.
6705                  */
6706                 I915_WRITE(_CURABASE, base);
6707
6708                 cntl &= ~(CURSOR_FORMAT_MASK);
6709                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6710                 cntl |= CURSOR_ENABLE |
6711                         CURSOR_GAMMA_ENABLE |
6712                         CURSOR_FORMAT_ARGB;
6713         } else
6714                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6715         I915_WRITE(_CURACNTR, cntl);
6716
6717         intel_crtc->cursor_visible = visible;
6718 }
6719
6720 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6721 {
6722         struct drm_device *dev = crtc->dev;
6723         struct drm_i915_private *dev_priv = dev->dev_private;
6724         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6725         int pipe = intel_crtc->pipe;
6726         bool visible = base != 0;
6727
6728         if (intel_crtc->cursor_visible != visible) {
6729                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6730                 if (base) {
6731                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6732                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6733                         cntl |= pipe << 28; /* Connect to correct pipe */
6734                 } else {
6735                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6736                         cntl |= CURSOR_MODE_DISABLE;
6737                 }
6738                 I915_WRITE(CURCNTR(pipe), cntl);
6739
6740                 intel_crtc->cursor_visible = visible;
6741         }
6742         /* and commit changes on next vblank */
6743         I915_WRITE(CURBASE(pipe), base);
6744 }
6745
6746 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6747 {
6748         struct drm_device *dev = crtc->dev;
6749         struct drm_i915_private *dev_priv = dev->dev_private;
6750         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6751         int pipe = intel_crtc->pipe;
6752         bool visible = base != 0;
6753
6754         if (intel_crtc->cursor_visible != visible) {
6755                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6756                 if (base) {
6757                         cntl &= ~CURSOR_MODE;
6758                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6759                 } else {
6760                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6761                         cntl |= CURSOR_MODE_DISABLE;
6762                 }
6763                 if (IS_HASWELL(dev)) {
6764                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6765                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6766                 }
6767                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6768
6769                 intel_crtc->cursor_visible = visible;
6770         }
6771         /* and commit changes on next vblank */
6772         I915_WRITE(CURBASE_IVB(pipe), base);
6773 }
6774
6775 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6776 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6777                                      bool on)
6778 {
6779         struct drm_device *dev = crtc->dev;
6780         struct drm_i915_private *dev_priv = dev->dev_private;
6781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6782         int pipe = intel_crtc->pipe;
6783         int x = intel_crtc->cursor_x;
6784         int y = intel_crtc->cursor_y;
6785         u32 base, pos;
6786         bool visible;
6787
6788         pos = 0;
6789
6790         if (on && crtc->enabled && crtc->fb) {
6791                 base = intel_crtc->cursor_addr;
6792                 if (x > (int) crtc->fb->width)
6793                         base = 0;
6794
6795                 if (y > (int) crtc->fb->height)
6796                         base = 0;
6797         } else
6798                 base = 0;
6799
6800         if (x < 0) {
6801                 if (x + intel_crtc->cursor_width < 0)
6802                         base = 0;
6803
6804                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6805                 x = -x;
6806         }
6807         pos |= x << CURSOR_X_SHIFT;
6808
6809         if (y < 0) {
6810                 if (y + intel_crtc->cursor_height < 0)
6811                         base = 0;
6812
6813                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6814                 y = -y;
6815         }
6816         pos |= y << CURSOR_Y_SHIFT;
6817
6818         visible = base != 0;
6819         if (!visible && !intel_crtc->cursor_visible)
6820                 return;
6821
6822         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6823                 I915_WRITE(CURPOS_IVB(pipe), pos);
6824                 ivb_update_cursor(crtc, base);
6825         } else {
6826                 I915_WRITE(CURPOS(pipe), pos);
6827                 if (IS_845G(dev) || IS_I865G(dev))
6828                         i845_update_cursor(crtc, base);
6829                 else
6830                         i9xx_update_cursor(crtc, base);
6831         }
6832 }
6833
6834 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6835                                  struct drm_file *file,
6836                                  uint32_t handle,
6837                                  uint32_t width, uint32_t height)
6838 {
6839         struct drm_device *dev = crtc->dev;
6840         struct drm_i915_private *dev_priv = dev->dev_private;
6841         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6842         struct drm_i915_gem_object *obj;
6843         uint32_t addr;
6844         int ret;
6845
6846         /* if we want to turn off the cursor ignore width and height */
6847         if (!handle) {
6848                 DRM_DEBUG_KMS("cursor off\n");
6849                 addr = 0;
6850                 obj = NULL;
6851                 mutex_lock(&dev->struct_mutex);
6852                 goto finish;
6853         }
6854
6855         /* Currently we only support 64x64 cursors */
6856         if (width != 64 || height != 64) {
6857                 DRM_ERROR("we currently only support 64x64 cursors\n");
6858                 return -EINVAL;
6859         }
6860
6861         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6862         if (&obj->base == NULL)
6863                 return -ENOENT;
6864
6865         if (obj->base.size < width * height * 4) {
6866                 DRM_ERROR("buffer is to small\n");
6867                 ret = -ENOMEM;
6868                 goto fail;
6869         }
6870
6871         /* we only need to pin inside GTT if cursor is non-phy */
6872         mutex_lock(&dev->struct_mutex);
6873         if (!dev_priv->info->cursor_needs_physical) {
6874                 unsigned alignment;
6875
6876                 if (obj->tiling_mode) {
6877                         DRM_ERROR("cursor cannot be tiled\n");
6878                         ret = -EINVAL;
6879                         goto fail_locked;
6880                 }
6881
6882                 /* Note that the w/a also requires 2 PTE of padding following
6883                  * the bo. We currently fill all unused PTE with the shadow
6884                  * page and so we should always have valid PTE following the
6885                  * cursor preventing the VT-d warning.
6886                  */
6887                 alignment = 0;
6888                 if (need_vtd_wa(dev))
6889                         alignment = 64*1024;
6890
6891                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6892                 if (ret) {
6893                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6894                         goto fail_locked;
6895                 }
6896
6897                 ret = i915_gem_object_put_fence(obj);
6898                 if (ret) {
6899                         DRM_ERROR("failed to release fence for cursor");
6900                         goto fail_unpin;
6901                 }
6902
6903                 addr = i915_gem_obj_ggtt_offset(obj);
6904         } else {
6905                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6906                 ret = i915_gem_attach_phys_object(dev, obj,
6907                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6908                                                   align);
6909                 if (ret) {
6910                         DRM_ERROR("failed to attach phys object\n");
6911                         goto fail_locked;
6912                 }
6913                 addr = obj->phys_obj->handle->busaddr;
6914         }
6915
6916         if (IS_GEN2(dev))
6917                 I915_WRITE(CURSIZE, (height << 12) | width);
6918
6919  finish:
6920         if (intel_crtc->cursor_bo) {
6921                 if (dev_priv->info->cursor_needs_physical) {
6922                         if (intel_crtc->cursor_bo != obj)
6923                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6924                 } else
6925                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
6926                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6927         }
6928
6929         mutex_unlock(&dev->struct_mutex);
6930
6931         intel_crtc->cursor_addr = addr;
6932         intel_crtc->cursor_bo = obj;
6933         intel_crtc->cursor_width = width;
6934         intel_crtc->cursor_height = height;
6935
6936         if (intel_crtc->active)
6937                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6938
6939         return 0;
6940 fail_unpin:
6941         i915_gem_object_unpin_from_display_plane(obj);
6942 fail_locked:
6943         mutex_unlock(&dev->struct_mutex);
6944 fail:
6945         drm_gem_object_unreference_unlocked(&obj->base);
6946         return ret;
6947 }
6948
6949 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6950 {
6951         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6952
6953         intel_crtc->cursor_x = x;
6954         intel_crtc->cursor_y = y;
6955
6956         if (intel_crtc->active)
6957                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6958
6959         return 0;
6960 }
6961
6962 /** Sets the color ramps on behalf of RandR */
6963 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6964                                  u16 blue, int regno)
6965 {
6966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6967
6968         intel_crtc->lut_r[regno] = red >> 8;
6969         intel_crtc->lut_g[regno] = green >> 8;
6970         intel_crtc->lut_b[regno] = blue >> 8;
6971 }
6972
6973 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6974                              u16 *blue, int regno)
6975 {
6976         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6977
6978         *red = intel_crtc->lut_r[regno] << 8;
6979         *green = intel_crtc->lut_g[regno] << 8;
6980         *blue = intel_crtc->lut_b[regno] << 8;
6981 }
6982
6983 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6984                                  u16 *blue, uint32_t start, uint32_t size)
6985 {
6986         int end = (start + size > 256) ? 256 : start + size, i;
6987         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6988
6989         for (i = start; i < end; i++) {
6990                 intel_crtc->lut_r[i] = red[i] >> 8;
6991                 intel_crtc->lut_g[i] = green[i] >> 8;
6992                 intel_crtc->lut_b[i] = blue[i] >> 8;
6993         }
6994
6995         intel_crtc_load_lut(crtc);
6996 }
6997
6998 /* VESA 640x480x72Hz mode to set on the pipe */
6999 static struct drm_display_mode load_detect_mode = {
7000         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7001                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7002 };
7003
7004 static struct drm_framebuffer *
7005 intel_framebuffer_create(struct drm_device *dev,
7006                          struct drm_mode_fb_cmd2 *mode_cmd,
7007                          struct drm_i915_gem_object *obj)
7008 {
7009         struct intel_framebuffer *intel_fb;
7010         int ret;
7011
7012         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7013         if (!intel_fb) {
7014                 drm_gem_object_unreference_unlocked(&obj->base);
7015                 return ERR_PTR(-ENOMEM);
7016         }
7017
7018         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7019         if (ret) {
7020                 drm_gem_object_unreference_unlocked(&obj->base);
7021                 kfree(intel_fb);
7022                 return ERR_PTR(ret);
7023         }
7024
7025         return &intel_fb->base;
7026 }
7027
7028 static u32
7029 intel_framebuffer_pitch_for_width(int width, int bpp)
7030 {
7031         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7032         return ALIGN(pitch, 64);
7033 }
7034
7035 static u32
7036 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7037 {
7038         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7039         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7040 }
7041
7042 static struct drm_framebuffer *
7043 intel_framebuffer_create_for_mode(struct drm_device *dev,
7044                                   struct drm_display_mode *mode,
7045                                   int depth, int bpp)
7046 {
7047         struct drm_i915_gem_object *obj;
7048         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7049
7050         obj = i915_gem_alloc_object(dev,
7051                                     intel_framebuffer_size_for_mode(mode, bpp));
7052         if (obj == NULL)
7053                 return ERR_PTR(-ENOMEM);
7054
7055         mode_cmd.width = mode->hdisplay;
7056         mode_cmd.height = mode->vdisplay;
7057         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7058                                                                 bpp);
7059         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7060
7061         return intel_framebuffer_create(dev, &mode_cmd, obj);
7062 }
7063
7064 static struct drm_framebuffer *
7065 mode_fits_in_fbdev(struct drm_device *dev,
7066                    struct drm_display_mode *mode)
7067 {
7068         struct drm_i915_private *dev_priv = dev->dev_private;
7069         struct drm_i915_gem_object *obj;
7070         struct drm_framebuffer *fb;
7071
7072         if (dev_priv->fbdev == NULL)
7073                 return NULL;
7074
7075         obj = dev_priv->fbdev->ifb.obj;
7076         if (obj == NULL)
7077                 return NULL;
7078
7079         fb = &dev_priv->fbdev->ifb.base;
7080         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7081                                                                fb->bits_per_pixel))
7082                 return NULL;
7083
7084         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7085                 return NULL;
7086
7087         return fb;
7088 }
7089
7090 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7091                                 struct drm_display_mode *mode,
7092                                 struct intel_load_detect_pipe *old)
7093 {
7094         struct intel_crtc *intel_crtc;
7095         struct intel_encoder *intel_encoder =
7096                 intel_attached_encoder(connector);
7097         struct drm_crtc *possible_crtc;
7098         struct drm_encoder *encoder = &intel_encoder->base;
7099         struct drm_crtc *crtc = NULL;
7100         struct drm_device *dev = encoder->dev;
7101         struct drm_framebuffer *fb;
7102         int i = -1;
7103
7104         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7105                       connector->base.id, drm_get_connector_name(connector),
7106                       encoder->base.id, drm_get_encoder_name(encoder));
7107
7108         /*
7109          * Algorithm gets a little messy:
7110          *
7111          *   - if the connector already has an assigned crtc, use it (but make
7112          *     sure it's on first)
7113          *
7114          *   - try to find the first unused crtc that can drive this connector,
7115          *     and use that if we find one
7116          */
7117
7118         /* See if we already have a CRTC for this connector */
7119         if (encoder->crtc) {
7120                 crtc = encoder->crtc;
7121
7122                 mutex_lock(&crtc->mutex);
7123
7124                 old->dpms_mode = connector->dpms;
7125                 old->load_detect_temp = false;
7126
7127                 /* Make sure the crtc and connector are running */
7128                 if (connector->dpms != DRM_MODE_DPMS_ON)
7129                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7130
7131                 return true;
7132         }
7133
7134         /* Find an unused one (if possible) */
7135         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7136                 i++;
7137                 if (!(encoder->possible_crtcs & (1 << i)))
7138                         continue;
7139                 if (!possible_crtc->enabled) {
7140                         crtc = possible_crtc;
7141                         break;
7142                 }
7143         }
7144
7145         /*
7146          * If we didn't find an unused CRTC, don't use any.
7147          */
7148         if (!crtc) {
7149                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7150                 return false;
7151         }
7152
7153         mutex_lock(&crtc->mutex);
7154         intel_encoder->new_crtc = to_intel_crtc(crtc);
7155         to_intel_connector(connector)->new_encoder = intel_encoder;
7156
7157         intel_crtc = to_intel_crtc(crtc);
7158         old->dpms_mode = connector->dpms;
7159         old->load_detect_temp = true;
7160         old->release_fb = NULL;
7161
7162         if (!mode)
7163                 mode = &load_detect_mode;
7164
7165         /* We need a framebuffer large enough to accommodate all accesses
7166          * that the plane may generate whilst we perform load detection.
7167          * We can not rely on the fbcon either being present (we get called
7168          * during its initialisation to detect all boot displays, or it may
7169          * not even exist) or that it is large enough to satisfy the
7170          * requested mode.
7171          */
7172         fb = mode_fits_in_fbdev(dev, mode);
7173         if (fb == NULL) {
7174                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7175                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7176                 old->release_fb = fb;
7177         } else
7178                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7179         if (IS_ERR(fb)) {
7180                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7181                 mutex_unlock(&crtc->mutex);
7182                 return false;
7183         }
7184
7185         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7186                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7187                 if (old->release_fb)
7188                         old->release_fb->funcs->destroy(old->release_fb);
7189                 mutex_unlock(&crtc->mutex);
7190                 return false;
7191         }
7192
7193         /* let the connector get through one full cycle before testing */
7194         intel_wait_for_vblank(dev, intel_crtc->pipe);
7195         return true;
7196 }
7197
7198 void intel_release_load_detect_pipe(struct drm_connector *connector,
7199                                     struct intel_load_detect_pipe *old)
7200 {
7201         struct intel_encoder *intel_encoder =
7202                 intel_attached_encoder(connector);
7203         struct drm_encoder *encoder = &intel_encoder->base;
7204         struct drm_crtc *crtc = encoder->crtc;
7205
7206         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7207                       connector->base.id, drm_get_connector_name(connector),
7208                       encoder->base.id, drm_get_encoder_name(encoder));
7209
7210         if (old->load_detect_temp) {
7211                 to_intel_connector(connector)->new_encoder = NULL;
7212                 intel_encoder->new_crtc = NULL;
7213                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7214
7215                 if (old->release_fb) {
7216                         drm_framebuffer_unregister_private(old->release_fb);
7217                         drm_framebuffer_unreference(old->release_fb);
7218                 }
7219
7220                 mutex_unlock(&crtc->mutex);
7221                 return;
7222         }
7223
7224         /* Switch crtc and encoder back off if necessary */
7225         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7226                 connector->funcs->dpms(connector, old->dpms_mode);
7227
7228         mutex_unlock(&crtc->mutex);
7229 }
7230
7231 /* Returns the clock of the currently programmed mode of the given pipe. */
7232 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7233                                 struct intel_crtc_config *pipe_config)
7234 {
7235         struct drm_device *dev = crtc->base.dev;
7236         struct drm_i915_private *dev_priv = dev->dev_private;
7237         int pipe = pipe_config->cpu_transcoder;
7238         u32 dpll = I915_READ(DPLL(pipe));
7239         u32 fp;
7240         intel_clock_t clock;
7241
7242         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7243                 fp = I915_READ(FP0(pipe));
7244         else
7245                 fp = I915_READ(FP1(pipe));
7246
7247         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7248         if (IS_PINEVIEW(dev)) {
7249                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7250                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7251         } else {
7252                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7253                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7254         }
7255
7256         if (!IS_GEN2(dev)) {
7257                 if (IS_PINEVIEW(dev))
7258                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7259                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7260                 else
7261                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7262                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7263
7264                 switch (dpll & DPLL_MODE_MASK) {
7265                 case DPLLB_MODE_DAC_SERIAL:
7266                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7267                                 5 : 10;
7268                         break;
7269                 case DPLLB_MODE_LVDS:
7270                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7271                                 7 : 14;
7272                         break;
7273                 default:
7274                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7275                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7276                         pipe_config->adjusted_mode.clock = 0;
7277                         return;
7278                 }
7279
7280                 if (IS_PINEVIEW(dev))
7281                         pineview_clock(96000, &clock);
7282                 else
7283                         i9xx_clock(96000, &clock);
7284         } else {
7285                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7286
7287                 if (is_lvds) {
7288                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7289                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7290                         clock.p2 = 14;
7291
7292                         if ((dpll & PLL_REF_INPUT_MASK) ==
7293                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7294                                 /* XXX: might not be 66MHz */
7295                                 i9xx_clock(66000, &clock);
7296                         } else
7297                                 i9xx_clock(48000, &clock);
7298                 } else {
7299                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7300                                 clock.p1 = 2;
7301                         else {
7302                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7303                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7304                         }
7305                         if (dpll & PLL_P2_DIVIDE_BY_4)
7306                                 clock.p2 = 4;
7307                         else
7308                                 clock.p2 = 2;
7309
7310                         i9xx_clock(48000, &clock);
7311                 }
7312         }
7313
7314         pipe_config->adjusted_mode.clock = clock.dot;
7315 }
7316
7317 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7318                                     struct intel_crtc_config *pipe_config)
7319 {
7320         struct drm_device *dev = crtc->base.dev;
7321         struct drm_i915_private *dev_priv = dev->dev_private;
7322         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7323         int link_freq, repeat;
7324         u64 clock;
7325         u32 link_m, link_n;
7326
7327         repeat = pipe_config->pixel_multiplier;
7328
7329         /*
7330          * The calculation for the data clock is:
7331          * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7332          * But we want to avoid losing precison if possible, so:
7333          * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7334          *
7335          * and the link clock is simpler:
7336          * link_clock = (m * link_clock * repeat) / n
7337          */
7338
7339         /*
7340          * We need to get the FDI or DP link clock here to derive
7341          * the M/N dividers.
7342          *
7343          * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7344          * For DP, it's either 1.62GHz or 2.7GHz.
7345          * We do our calculations in 10*MHz since we don't need much precison.
7346          */
7347         if (pipe_config->has_pch_encoder)
7348                 link_freq = intel_fdi_link_freq(dev) * 10000;
7349         else
7350                 link_freq = pipe_config->port_clock;
7351
7352         link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7353         link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7354
7355         if (!link_m || !link_n)
7356                 return;
7357
7358         clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7359         do_div(clock, link_n);
7360
7361         pipe_config->adjusted_mode.clock = clock;
7362 }
7363
7364 /** Returns the currently programmed mode of the given pipe. */
7365 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7366                                              struct drm_crtc *crtc)
7367 {
7368         struct drm_i915_private *dev_priv = dev->dev_private;
7369         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7370         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7371         struct drm_display_mode *mode;
7372         struct intel_crtc_config pipe_config;
7373         int htot = I915_READ(HTOTAL(cpu_transcoder));
7374         int hsync = I915_READ(HSYNC(cpu_transcoder));
7375         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7376         int vsync = I915_READ(VSYNC(cpu_transcoder));
7377
7378         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7379         if (!mode)
7380                 return NULL;
7381
7382         /*
7383          * Construct a pipe_config sufficient for getting the clock info
7384          * back out of crtc_clock_get.
7385          *
7386          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7387          * to use a real value here instead.
7388          */
7389         pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7390         pipe_config.pixel_multiplier = 1;
7391         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7392
7393         mode->clock = pipe_config.adjusted_mode.clock;
7394         mode->hdisplay = (htot & 0xffff) + 1;
7395         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7396         mode->hsync_start = (hsync & 0xffff) + 1;
7397         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7398         mode->vdisplay = (vtot & 0xffff) + 1;
7399         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7400         mode->vsync_start = (vsync & 0xffff) + 1;
7401         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7402
7403         drm_mode_set_name(mode);
7404
7405         return mode;
7406 }
7407
7408 static void intel_increase_pllclock(struct drm_crtc *crtc)
7409 {
7410         struct drm_device *dev = crtc->dev;
7411         drm_i915_private_t *dev_priv = dev->dev_private;
7412         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7413         int pipe = intel_crtc->pipe;
7414         int dpll_reg = DPLL(pipe);
7415         int dpll;
7416
7417         if (HAS_PCH_SPLIT(dev))
7418                 return;
7419
7420         if (!dev_priv->lvds_downclock_avail)
7421                 return;
7422
7423         dpll = I915_READ(dpll_reg);
7424         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7425                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7426
7427                 assert_panel_unlocked(dev_priv, pipe);
7428
7429                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7430                 I915_WRITE(dpll_reg, dpll);
7431                 intel_wait_for_vblank(dev, pipe);
7432
7433                 dpll = I915_READ(dpll_reg);
7434                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7435                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7436         }
7437 }
7438
7439 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7440 {
7441         struct drm_device *dev = crtc->dev;
7442         drm_i915_private_t *dev_priv = dev->dev_private;
7443         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7444
7445         if (HAS_PCH_SPLIT(dev))
7446                 return;
7447
7448         if (!dev_priv->lvds_downclock_avail)
7449                 return;
7450
7451         /*
7452          * Since this is called by a timer, we should never get here in
7453          * the manual case.
7454          */
7455         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7456                 int pipe = intel_crtc->pipe;
7457                 int dpll_reg = DPLL(pipe);
7458                 int dpll;
7459
7460                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7461
7462                 assert_panel_unlocked(dev_priv, pipe);
7463
7464                 dpll = I915_READ(dpll_reg);
7465                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7466                 I915_WRITE(dpll_reg, dpll);
7467                 intel_wait_for_vblank(dev, pipe);
7468                 dpll = I915_READ(dpll_reg);
7469                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7470                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7471         }
7472
7473 }
7474
7475 void intel_mark_busy(struct drm_device *dev)
7476 {
7477         struct drm_i915_private *dev_priv = dev->dev_private;
7478
7479         hsw_package_c8_gpu_busy(dev_priv);
7480         i915_update_gfx_val(dev_priv);
7481 }
7482
7483 void intel_mark_idle(struct drm_device *dev)
7484 {
7485         struct drm_i915_private *dev_priv = dev->dev_private;
7486         struct drm_crtc *crtc;
7487
7488         hsw_package_c8_gpu_idle(dev_priv);
7489
7490         if (!i915_powersave)
7491                 return;
7492
7493         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7494                 if (!crtc->fb)
7495                         continue;
7496
7497                 intel_decrease_pllclock(crtc);
7498         }
7499 }
7500
7501 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7502                         struct intel_ring_buffer *ring)
7503 {
7504         struct drm_device *dev = obj->base.dev;
7505         struct drm_crtc *crtc;
7506
7507         if (!i915_powersave)
7508                 return;
7509
7510         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7511                 if (!crtc->fb)
7512                         continue;
7513
7514                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7515                         continue;
7516
7517                 intel_increase_pllclock(crtc);
7518                 if (ring && intel_fbc_enabled(dev))
7519                         ring->fbc_dirty = true;
7520         }
7521 }
7522
7523 static void intel_crtc_destroy(struct drm_crtc *crtc)
7524 {
7525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7526         struct drm_device *dev = crtc->dev;
7527         struct intel_unpin_work *work;
7528         unsigned long flags;
7529
7530         spin_lock_irqsave(&dev->event_lock, flags);
7531         work = intel_crtc->unpin_work;
7532         intel_crtc->unpin_work = NULL;
7533         spin_unlock_irqrestore(&dev->event_lock, flags);
7534
7535         if (work) {
7536                 cancel_work_sync(&work->work);
7537                 kfree(work);
7538         }
7539
7540         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7541
7542         drm_crtc_cleanup(crtc);
7543
7544         kfree(intel_crtc);
7545 }
7546
7547 static void intel_unpin_work_fn(struct work_struct *__work)
7548 {
7549         struct intel_unpin_work *work =
7550                 container_of(__work, struct intel_unpin_work, work);
7551         struct drm_device *dev = work->crtc->dev;
7552
7553         mutex_lock(&dev->struct_mutex);
7554         intel_unpin_fb_obj(work->old_fb_obj);
7555         drm_gem_object_unreference(&work->pending_flip_obj->base);
7556         drm_gem_object_unreference(&work->old_fb_obj->base);
7557
7558         intel_update_fbc(dev);
7559         mutex_unlock(&dev->struct_mutex);
7560
7561         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7562         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7563
7564         kfree(work);
7565 }
7566
7567 static void do_intel_finish_page_flip(struct drm_device *dev,
7568                                       struct drm_crtc *crtc)
7569 {
7570         drm_i915_private_t *dev_priv = dev->dev_private;
7571         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7572         struct intel_unpin_work *work;
7573         unsigned long flags;
7574
7575         /* Ignore early vblank irqs */
7576         if (intel_crtc == NULL)
7577                 return;
7578
7579         spin_lock_irqsave(&dev->event_lock, flags);
7580         work = intel_crtc->unpin_work;
7581
7582         /* Ensure we don't miss a work->pending update ... */
7583         smp_rmb();
7584
7585         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7586                 spin_unlock_irqrestore(&dev->event_lock, flags);
7587                 return;
7588         }
7589
7590         /* and that the unpin work is consistent wrt ->pending. */
7591         smp_rmb();
7592
7593         intel_crtc->unpin_work = NULL;
7594
7595         if (work->event)
7596                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7597
7598         drm_vblank_put(dev, intel_crtc->pipe);
7599
7600         spin_unlock_irqrestore(&dev->event_lock, flags);
7601
7602         wake_up_all(&dev_priv->pending_flip_queue);
7603
7604         queue_work(dev_priv->wq, &work->work);
7605
7606         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7607 }
7608
7609 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7610 {
7611         drm_i915_private_t *dev_priv = dev->dev_private;
7612         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7613
7614         do_intel_finish_page_flip(dev, crtc);
7615 }
7616
7617 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7618 {
7619         drm_i915_private_t *dev_priv = dev->dev_private;
7620         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7621
7622         do_intel_finish_page_flip(dev, crtc);
7623 }
7624
7625 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7626 {
7627         drm_i915_private_t *dev_priv = dev->dev_private;
7628         struct intel_crtc *intel_crtc =
7629                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7630         unsigned long flags;
7631
7632         /* NB: An MMIO update of the plane base pointer will also
7633          * generate a page-flip completion irq, i.e. every modeset
7634          * is also accompanied by a spurious intel_prepare_page_flip().
7635          */
7636         spin_lock_irqsave(&dev->event_lock, flags);
7637         if (intel_crtc->unpin_work)
7638                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7639         spin_unlock_irqrestore(&dev->event_lock, flags);
7640 }
7641
7642 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7643 {
7644         /* Ensure that the work item is consistent when activating it ... */
7645         smp_wmb();
7646         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7647         /* and that it is marked active as soon as the irq could fire. */
7648         smp_wmb();
7649 }
7650
7651 static int intel_gen2_queue_flip(struct drm_device *dev,
7652                                  struct drm_crtc *crtc,
7653                                  struct drm_framebuffer *fb,
7654                                  struct drm_i915_gem_object *obj,
7655                                  uint32_t flags)
7656 {
7657         struct drm_i915_private *dev_priv = dev->dev_private;
7658         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7659         u32 flip_mask;
7660         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7661         int ret;
7662
7663         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7664         if (ret)
7665                 goto err;
7666
7667         ret = intel_ring_begin(ring, 6);
7668         if (ret)
7669                 goto err_unpin;
7670
7671         /* Can't queue multiple flips, so wait for the previous
7672          * one to finish before executing the next.
7673          */
7674         if (intel_crtc->plane)
7675                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7676         else
7677                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7678         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7679         intel_ring_emit(ring, MI_NOOP);
7680         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7681                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7682         intel_ring_emit(ring, fb->pitches[0]);
7683         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7684         intel_ring_emit(ring, 0); /* aux display base address, unused */
7685
7686         intel_mark_page_flip_active(intel_crtc);
7687         intel_ring_advance(ring);
7688         return 0;
7689
7690 err_unpin:
7691         intel_unpin_fb_obj(obj);
7692 err:
7693         return ret;
7694 }
7695
7696 static int intel_gen3_queue_flip(struct drm_device *dev,
7697                                  struct drm_crtc *crtc,
7698                                  struct drm_framebuffer *fb,
7699                                  struct drm_i915_gem_object *obj,
7700                                  uint32_t flags)
7701 {
7702         struct drm_i915_private *dev_priv = dev->dev_private;
7703         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7704         u32 flip_mask;
7705         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7706         int ret;
7707
7708         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7709         if (ret)
7710                 goto err;
7711
7712         ret = intel_ring_begin(ring, 6);
7713         if (ret)
7714                 goto err_unpin;
7715
7716         if (intel_crtc->plane)
7717                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7718         else
7719                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7720         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7721         intel_ring_emit(ring, MI_NOOP);
7722         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7723                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7724         intel_ring_emit(ring, fb->pitches[0]);
7725         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7726         intel_ring_emit(ring, MI_NOOP);
7727
7728         intel_mark_page_flip_active(intel_crtc);
7729         intel_ring_advance(ring);
7730         return 0;
7731
7732 err_unpin:
7733         intel_unpin_fb_obj(obj);
7734 err:
7735         return ret;
7736 }
7737
7738 static int intel_gen4_queue_flip(struct drm_device *dev,
7739                                  struct drm_crtc *crtc,
7740                                  struct drm_framebuffer *fb,
7741                                  struct drm_i915_gem_object *obj,
7742                                  uint32_t flags)
7743 {
7744         struct drm_i915_private *dev_priv = dev->dev_private;
7745         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7746         uint32_t pf, pipesrc;
7747         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7748         int ret;
7749
7750         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7751         if (ret)
7752                 goto err;
7753
7754         ret = intel_ring_begin(ring, 4);
7755         if (ret)
7756                 goto err_unpin;
7757
7758         /* i965+ uses the linear or tiled offsets from the
7759          * Display Registers (which do not change across a page-flip)
7760          * so we need only reprogram the base address.
7761          */
7762         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7763                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7764         intel_ring_emit(ring, fb->pitches[0]);
7765         intel_ring_emit(ring,
7766                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7767                         obj->tiling_mode);
7768
7769         /* XXX Enabling the panel-fitter across page-flip is so far
7770          * untested on non-native modes, so ignore it for now.
7771          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7772          */
7773         pf = 0;
7774         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7775         intel_ring_emit(ring, pf | pipesrc);
7776
7777         intel_mark_page_flip_active(intel_crtc);
7778         intel_ring_advance(ring);
7779         return 0;
7780
7781 err_unpin:
7782         intel_unpin_fb_obj(obj);
7783 err:
7784         return ret;
7785 }
7786
7787 static int intel_gen6_queue_flip(struct drm_device *dev,
7788                                  struct drm_crtc *crtc,
7789                                  struct drm_framebuffer *fb,
7790                                  struct drm_i915_gem_object *obj,
7791                                  uint32_t flags)
7792 {
7793         struct drm_i915_private *dev_priv = dev->dev_private;
7794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7795         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7796         uint32_t pf, pipesrc;
7797         int ret;
7798
7799         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7800         if (ret)
7801                 goto err;
7802
7803         ret = intel_ring_begin(ring, 4);
7804         if (ret)
7805                 goto err_unpin;
7806
7807         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7808                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7809         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7810         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7811
7812         /* Contrary to the suggestions in the documentation,
7813          * "Enable Panel Fitter" does not seem to be required when page
7814          * flipping with a non-native mode, and worse causes a normal
7815          * modeset to fail.
7816          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7817          */
7818         pf = 0;
7819         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7820         intel_ring_emit(ring, pf | pipesrc);
7821
7822         intel_mark_page_flip_active(intel_crtc);
7823         intel_ring_advance(ring);
7824         return 0;
7825
7826 err_unpin:
7827         intel_unpin_fb_obj(obj);
7828 err:
7829         return ret;
7830 }
7831
7832 static int intel_gen7_queue_flip(struct drm_device *dev,
7833                                  struct drm_crtc *crtc,
7834                                  struct drm_framebuffer *fb,
7835                                  struct drm_i915_gem_object *obj,
7836                                  uint32_t flags)
7837 {
7838         struct drm_i915_private *dev_priv = dev->dev_private;
7839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7840         struct intel_ring_buffer *ring;
7841         uint32_t plane_bit = 0;
7842         int len, ret;
7843
7844         ring = obj->ring;
7845         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
7846                 ring = &dev_priv->ring[BCS];
7847
7848         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7849         if (ret)
7850                 goto err;
7851
7852         switch(intel_crtc->plane) {
7853         case PLANE_A:
7854                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7855                 break;
7856         case PLANE_B:
7857                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7858                 break;
7859         case PLANE_C:
7860                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7861                 break;
7862         default:
7863                 WARN_ONCE(1, "unknown plane in flip command\n");
7864                 ret = -ENODEV;
7865                 goto err_unpin;
7866         }
7867
7868         len = 4;
7869         if (ring->id == RCS)
7870                 len += 6;
7871
7872         ret = intel_ring_begin(ring, len);
7873         if (ret)
7874                 goto err_unpin;
7875
7876         /* Unmask the flip-done completion message. Note that the bspec says that
7877          * we should do this for both the BCS and RCS, and that we must not unmask
7878          * more than one flip event at any time (or ensure that one flip message
7879          * can be sent by waiting for flip-done prior to queueing new flips).
7880          * Experimentation says that BCS works despite DERRMR masking all
7881          * flip-done completion events and that unmasking all planes at once
7882          * for the RCS also doesn't appear to drop events. Setting the DERRMR
7883          * to zero does lead to lockups within MI_DISPLAY_FLIP.
7884          */
7885         if (ring->id == RCS) {
7886                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
7887                 intel_ring_emit(ring, DERRMR);
7888                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
7889                                         DERRMR_PIPEB_PRI_FLIP_DONE |
7890                                         DERRMR_PIPEC_PRI_FLIP_DONE));
7891                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
7892                 intel_ring_emit(ring, DERRMR);
7893                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
7894         }
7895
7896         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7897         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7898         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7899         intel_ring_emit(ring, (MI_NOOP));
7900
7901         intel_mark_page_flip_active(intel_crtc);
7902         intel_ring_advance(ring);
7903         return 0;
7904
7905 err_unpin:
7906         intel_unpin_fb_obj(obj);
7907 err:
7908         return ret;
7909 }
7910
7911 static int intel_default_queue_flip(struct drm_device *dev,
7912                                     struct drm_crtc *crtc,
7913                                     struct drm_framebuffer *fb,
7914                                     struct drm_i915_gem_object *obj,
7915                                     uint32_t flags)
7916 {
7917         return -ENODEV;
7918 }
7919
7920 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7921                                 struct drm_framebuffer *fb,
7922                                 struct drm_pending_vblank_event *event,
7923                                 uint32_t page_flip_flags)
7924 {
7925         struct drm_device *dev = crtc->dev;
7926         struct drm_i915_private *dev_priv = dev->dev_private;
7927         struct drm_framebuffer *old_fb = crtc->fb;
7928         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7929         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7930         struct intel_unpin_work *work;
7931         unsigned long flags;
7932         int ret;
7933
7934         /* Can't change pixel format via MI display flips. */
7935         if (fb->pixel_format != crtc->fb->pixel_format)
7936                 return -EINVAL;
7937
7938         /*
7939          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7940          * Note that pitch changes could also affect these register.
7941          */
7942         if (INTEL_INFO(dev)->gen > 3 &&
7943             (fb->offsets[0] != crtc->fb->offsets[0] ||
7944              fb->pitches[0] != crtc->fb->pitches[0]))
7945                 return -EINVAL;
7946
7947         work = kzalloc(sizeof *work, GFP_KERNEL);
7948         if (work == NULL)
7949                 return -ENOMEM;
7950
7951         work->event = event;
7952         work->crtc = crtc;
7953         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7954         INIT_WORK(&work->work, intel_unpin_work_fn);
7955
7956         ret = drm_vblank_get(dev, intel_crtc->pipe);
7957         if (ret)
7958                 goto free_work;
7959
7960         /* We borrow the event spin lock for protecting unpin_work */
7961         spin_lock_irqsave(&dev->event_lock, flags);
7962         if (intel_crtc->unpin_work) {
7963                 spin_unlock_irqrestore(&dev->event_lock, flags);
7964                 kfree(work);
7965                 drm_vblank_put(dev, intel_crtc->pipe);
7966
7967                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7968                 return -EBUSY;
7969         }
7970         intel_crtc->unpin_work = work;
7971         spin_unlock_irqrestore(&dev->event_lock, flags);
7972
7973         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7974                 flush_workqueue(dev_priv->wq);
7975
7976         ret = i915_mutex_lock_interruptible(dev);
7977         if (ret)
7978                 goto cleanup;
7979
7980         /* Reference the objects for the scheduled work. */
7981         drm_gem_object_reference(&work->old_fb_obj->base);
7982         drm_gem_object_reference(&obj->base);
7983
7984         crtc->fb = fb;
7985
7986         work->pending_flip_obj = obj;
7987
7988         work->enable_stall_check = true;
7989
7990         atomic_inc(&intel_crtc->unpin_work_count);
7991         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7992
7993         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
7994         if (ret)
7995                 goto cleanup_pending;
7996
7997         intel_disable_fbc(dev);
7998         intel_mark_fb_busy(obj, NULL);
7999         mutex_unlock(&dev->struct_mutex);
8000
8001         trace_i915_flip_request(intel_crtc->plane, obj);
8002
8003         return 0;
8004
8005 cleanup_pending:
8006         atomic_dec(&intel_crtc->unpin_work_count);
8007         crtc->fb = old_fb;
8008         drm_gem_object_unreference(&work->old_fb_obj->base);
8009         drm_gem_object_unreference(&obj->base);
8010         mutex_unlock(&dev->struct_mutex);
8011
8012 cleanup:
8013         spin_lock_irqsave(&dev->event_lock, flags);
8014         intel_crtc->unpin_work = NULL;
8015         spin_unlock_irqrestore(&dev->event_lock, flags);
8016
8017         drm_vblank_put(dev, intel_crtc->pipe);
8018 free_work:
8019         kfree(work);
8020
8021         return ret;
8022 }
8023
8024 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8025         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8026         .load_lut = intel_crtc_load_lut,
8027 };
8028
8029 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8030                                   struct drm_crtc *crtc)
8031 {
8032         struct drm_device *dev;
8033         struct drm_crtc *tmp;
8034         int crtc_mask = 1;
8035
8036         WARN(!crtc, "checking null crtc?\n");
8037
8038         dev = crtc->dev;
8039
8040         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8041                 if (tmp == crtc)
8042                         break;
8043                 crtc_mask <<= 1;
8044         }
8045
8046         if (encoder->possible_crtcs & crtc_mask)
8047                 return true;
8048         return false;
8049 }
8050
8051 /**
8052  * intel_modeset_update_staged_output_state
8053  *
8054  * Updates the staged output configuration state, e.g. after we've read out the
8055  * current hw state.
8056  */
8057 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8058 {
8059         struct intel_encoder *encoder;
8060         struct intel_connector *connector;
8061
8062         list_for_each_entry(connector, &dev->mode_config.connector_list,
8063                             base.head) {
8064                 connector->new_encoder =
8065                         to_intel_encoder(connector->base.encoder);
8066         }
8067
8068         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8069                             base.head) {
8070                 encoder->new_crtc =
8071                         to_intel_crtc(encoder->base.crtc);
8072         }
8073 }
8074
8075 /**
8076  * intel_modeset_commit_output_state
8077  *
8078  * This function copies the stage display pipe configuration to the real one.
8079  */
8080 static void intel_modeset_commit_output_state(struct drm_device *dev)
8081 {
8082         struct intel_encoder *encoder;
8083         struct intel_connector *connector;
8084
8085         list_for_each_entry(connector, &dev->mode_config.connector_list,
8086                             base.head) {
8087                 connector->base.encoder = &connector->new_encoder->base;
8088         }
8089
8090         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8091                             base.head) {
8092                 encoder->base.crtc = &encoder->new_crtc->base;
8093         }
8094 }
8095
8096 static void
8097 connected_sink_compute_bpp(struct intel_connector * connector,
8098                            struct intel_crtc_config *pipe_config)
8099 {
8100         int bpp = pipe_config->pipe_bpp;
8101
8102         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8103                 connector->base.base.id,
8104                 drm_get_connector_name(&connector->base));
8105
8106         /* Don't use an invalid EDID bpc value */
8107         if (connector->base.display_info.bpc &&
8108             connector->base.display_info.bpc * 3 < bpp) {
8109                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8110                               bpp, connector->base.display_info.bpc*3);
8111                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8112         }
8113
8114         /* Clamp bpp to 8 on screens without EDID 1.4 */
8115         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8116                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8117                               bpp);
8118                 pipe_config->pipe_bpp = 24;
8119         }
8120 }
8121
8122 static int
8123 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8124                           struct drm_framebuffer *fb,
8125                           struct intel_crtc_config *pipe_config)
8126 {
8127         struct drm_device *dev = crtc->base.dev;
8128         struct intel_connector *connector;
8129         int bpp;
8130
8131         switch (fb->pixel_format) {
8132         case DRM_FORMAT_C8:
8133                 bpp = 8*3; /* since we go through a colormap */
8134                 break;
8135         case DRM_FORMAT_XRGB1555:
8136         case DRM_FORMAT_ARGB1555:
8137                 /* checked in intel_framebuffer_init already */
8138                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8139                         return -EINVAL;
8140         case DRM_FORMAT_RGB565:
8141                 bpp = 6*3; /* min is 18bpp */
8142                 break;
8143         case DRM_FORMAT_XBGR8888:
8144         case DRM_FORMAT_ABGR8888:
8145                 /* checked in intel_framebuffer_init already */
8146                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8147                         return -EINVAL;
8148         case DRM_FORMAT_XRGB8888:
8149         case DRM_FORMAT_ARGB8888:
8150                 bpp = 8*3;
8151                 break;
8152         case DRM_FORMAT_XRGB2101010:
8153         case DRM_FORMAT_ARGB2101010:
8154         case DRM_FORMAT_XBGR2101010:
8155         case DRM_FORMAT_ABGR2101010:
8156                 /* checked in intel_framebuffer_init already */
8157                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8158                         return -EINVAL;
8159                 bpp = 10*3;
8160                 break;
8161         /* TODO: gen4+ supports 16 bpc floating point, too. */
8162         default:
8163                 DRM_DEBUG_KMS("unsupported depth\n");
8164                 return -EINVAL;
8165         }
8166
8167         pipe_config->pipe_bpp = bpp;
8168
8169         /* Clamp display bpp to EDID value */
8170         list_for_each_entry(connector, &dev->mode_config.connector_list,
8171                             base.head) {
8172                 if (!connector->new_encoder ||
8173                     connector->new_encoder->new_crtc != crtc)
8174                         continue;
8175
8176                 connected_sink_compute_bpp(connector, pipe_config);
8177         }
8178
8179         return bpp;
8180 }
8181
8182 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8183                                    struct intel_crtc_config *pipe_config,
8184                                    const char *context)
8185 {
8186         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8187                       context, pipe_name(crtc->pipe));
8188
8189         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8190         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8191                       pipe_config->pipe_bpp, pipe_config->dither);
8192         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8193                       pipe_config->has_pch_encoder,
8194                       pipe_config->fdi_lanes,
8195                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8196                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8197                       pipe_config->fdi_m_n.tu);
8198         DRM_DEBUG_KMS("requested mode:\n");
8199         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8200         DRM_DEBUG_KMS("adjusted mode:\n");
8201         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8202         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8203                       pipe_config->gmch_pfit.control,
8204                       pipe_config->gmch_pfit.pgm_ratios,
8205                       pipe_config->gmch_pfit.lvds_border_bits);
8206         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8207                       pipe_config->pch_pfit.pos,
8208                       pipe_config->pch_pfit.size,
8209                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8210         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8211 }
8212
8213 static bool check_encoder_cloning(struct drm_crtc *crtc)
8214 {
8215         int num_encoders = 0;
8216         bool uncloneable_encoders = false;
8217         struct intel_encoder *encoder;
8218
8219         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8220                             base.head) {
8221                 if (&encoder->new_crtc->base != crtc)
8222                         continue;
8223
8224                 num_encoders++;
8225                 if (!encoder->cloneable)
8226                         uncloneable_encoders = true;
8227         }
8228
8229         return !(num_encoders > 1 && uncloneable_encoders);
8230 }
8231
8232 static struct intel_crtc_config *
8233 intel_modeset_pipe_config(struct drm_crtc *crtc,
8234                           struct drm_framebuffer *fb,
8235                           struct drm_display_mode *mode)
8236 {
8237         struct drm_device *dev = crtc->dev;
8238         struct intel_encoder *encoder;
8239         struct intel_crtc_config *pipe_config;
8240         int plane_bpp, ret = -EINVAL;
8241         bool retry = true;
8242
8243         if (!check_encoder_cloning(crtc)) {
8244                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8245                 return ERR_PTR(-EINVAL);
8246         }
8247
8248         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8249         if (!pipe_config)
8250                 return ERR_PTR(-ENOMEM);
8251
8252         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8253         drm_mode_copy(&pipe_config->requested_mode, mode);
8254         pipe_config->cpu_transcoder =
8255                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8256         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8257
8258         /*
8259          * Sanitize sync polarity flags based on requested ones. If neither
8260          * positive or negative polarity is requested, treat this as meaning
8261          * negative polarity.
8262          */
8263         if (!(pipe_config->adjusted_mode.flags &
8264               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8265                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8266
8267         if (!(pipe_config->adjusted_mode.flags &
8268               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8269                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8270
8271         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8272          * plane pixel format and any sink constraints into account. Returns the
8273          * source plane bpp so that dithering can be selected on mismatches
8274          * after encoders and crtc also have had their say. */
8275         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8276                                               fb, pipe_config);
8277         if (plane_bpp < 0)
8278                 goto fail;
8279
8280 encoder_retry:
8281         /* Ensure the port clock defaults are reset when retrying. */
8282         pipe_config->port_clock = 0;
8283         pipe_config->pixel_multiplier = 1;
8284
8285         /* Fill in default crtc timings, allow encoders to overwrite them. */
8286         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8287
8288         /* Pass our mode to the connectors and the CRTC to give them a chance to
8289          * adjust it according to limitations or connector properties, and also
8290          * a chance to reject the mode entirely.
8291          */
8292         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8293                             base.head) {
8294
8295                 if (&encoder->new_crtc->base != crtc)
8296                         continue;
8297
8298                 if (!(encoder->compute_config(encoder, pipe_config))) {
8299                         DRM_DEBUG_KMS("Encoder config failure\n");
8300                         goto fail;
8301                 }
8302         }
8303
8304         /* Set default port clock if not overwritten by the encoder. Needs to be
8305          * done afterwards in case the encoder adjusts the mode. */
8306         if (!pipe_config->port_clock)
8307                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8308
8309         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8310         if (ret < 0) {
8311                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8312                 goto fail;
8313         }
8314
8315         if (ret == RETRY) {
8316                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8317                         ret = -EINVAL;
8318                         goto fail;
8319                 }
8320
8321                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8322                 retry = false;
8323                 goto encoder_retry;
8324         }
8325
8326         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8327         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8328                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8329
8330         return pipe_config;
8331 fail:
8332         kfree(pipe_config);
8333         return ERR_PTR(ret);
8334 }
8335
8336 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8337  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8338 static void
8339 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8340                              unsigned *prepare_pipes, unsigned *disable_pipes)
8341 {
8342         struct intel_crtc *intel_crtc;
8343         struct drm_device *dev = crtc->dev;
8344         struct intel_encoder *encoder;
8345         struct intel_connector *connector;
8346         struct drm_crtc *tmp_crtc;
8347
8348         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8349
8350         /* Check which crtcs have changed outputs connected to them, these need
8351          * to be part of the prepare_pipes mask. We don't (yet) support global
8352          * modeset across multiple crtcs, so modeset_pipes will only have one
8353          * bit set at most. */
8354         list_for_each_entry(connector, &dev->mode_config.connector_list,
8355                             base.head) {
8356                 if (connector->base.encoder == &connector->new_encoder->base)
8357                         continue;
8358
8359                 if (connector->base.encoder) {
8360                         tmp_crtc = connector->base.encoder->crtc;
8361
8362                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8363                 }
8364
8365                 if (connector->new_encoder)
8366                         *prepare_pipes |=
8367                                 1 << connector->new_encoder->new_crtc->pipe;
8368         }
8369
8370         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8371                             base.head) {
8372                 if (encoder->base.crtc == &encoder->new_crtc->base)
8373                         continue;
8374
8375                 if (encoder->base.crtc) {
8376                         tmp_crtc = encoder->base.crtc;
8377
8378                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8379                 }
8380
8381                 if (encoder->new_crtc)
8382                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8383         }
8384
8385         /* Check for any pipes that will be fully disabled ... */
8386         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8387                             base.head) {
8388                 bool used = false;
8389
8390                 /* Don't try to disable disabled crtcs. */
8391                 if (!intel_crtc->base.enabled)
8392                         continue;
8393
8394                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8395                                     base.head) {
8396                         if (encoder->new_crtc == intel_crtc)
8397                                 used = true;
8398                 }
8399
8400                 if (!used)
8401                         *disable_pipes |= 1 << intel_crtc->pipe;
8402         }
8403
8404
8405         /* set_mode is also used to update properties on life display pipes. */
8406         intel_crtc = to_intel_crtc(crtc);
8407         if (crtc->enabled)
8408                 *prepare_pipes |= 1 << intel_crtc->pipe;
8409
8410         /*
8411          * For simplicity do a full modeset on any pipe where the output routing
8412          * changed. We could be more clever, but that would require us to be
8413          * more careful with calling the relevant encoder->mode_set functions.
8414          */
8415         if (*prepare_pipes)
8416                 *modeset_pipes = *prepare_pipes;
8417
8418         /* ... and mask these out. */
8419         *modeset_pipes &= ~(*disable_pipes);
8420         *prepare_pipes &= ~(*disable_pipes);
8421
8422         /*
8423          * HACK: We don't (yet) fully support global modesets. intel_set_config
8424          * obies this rule, but the modeset restore mode of
8425          * intel_modeset_setup_hw_state does not.
8426          */
8427         *modeset_pipes &= 1 << intel_crtc->pipe;
8428         *prepare_pipes &= 1 << intel_crtc->pipe;
8429
8430         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8431                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8432 }
8433
8434 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8435 {
8436         struct drm_encoder *encoder;
8437         struct drm_device *dev = crtc->dev;
8438
8439         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8440                 if (encoder->crtc == crtc)
8441                         return true;
8442
8443         return false;
8444 }
8445
8446 static void
8447 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8448 {
8449         struct intel_encoder *intel_encoder;
8450         struct intel_crtc *intel_crtc;
8451         struct drm_connector *connector;
8452
8453         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8454                             base.head) {
8455                 if (!intel_encoder->base.crtc)
8456                         continue;
8457
8458                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8459
8460                 if (prepare_pipes & (1 << intel_crtc->pipe))
8461                         intel_encoder->connectors_active = false;
8462         }
8463
8464         intel_modeset_commit_output_state(dev);
8465
8466         /* Update computed state. */
8467         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8468                             base.head) {
8469                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8470         }
8471
8472         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8473                 if (!connector->encoder || !connector->encoder->crtc)
8474                         continue;
8475
8476                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8477
8478                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8479                         struct drm_property *dpms_property =
8480                                 dev->mode_config.dpms_property;
8481
8482                         connector->dpms = DRM_MODE_DPMS_ON;
8483                         drm_object_property_set_value(&connector->base,
8484                                                          dpms_property,
8485                                                          DRM_MODE_DPMS_ON);
8486
8487                         intel_encoder = to_intel_encoder(connector->encoder);
8488                         intel_encoder->connectors_active = true;
8489                 }
8490         }
8491
8492 }
8493
8494 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8495                                     struct intel_crtc_config *new)
8496 {
8497         int clock1, clock2, diff;
8498
8499         clock1 = cur->adjusted_mode.clock;
8500         clock2 = new->adjusted_mode.clock;
8501
8502         if (clock1 == clock2)
8503                 return true;
8504
8505         if (!clock1 || !clock2)
8506                 return false;
8507
8508         diff = abs(clock1 - clock2);
8509
8510         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8511                 return true;
8512
8513         return false;
8514 }
8515
8516 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8517         list_for_each_entry((intel_crtc), \
8518                             &(dev)->mode_config.crtc_list, \
8519                             base.head) \
8520                 if (mask & (1 <<(intel_crtc)->pipe))
8521
8522 static bool
8523 intel_pipe_config_compare(struct drm_device *dev,
8524                           struct intel_crtc_config *current_config,
8525                           struct intel_crtc_config *pipe_config)
8526 {
8527 #define PIPE_CONF_CHECK_X(name) \
8528         if (current_config->name != pipe_config->name) { \
8529                 DRM_ERROR("mismatch in " #name " " \
8530                           "(expected 0x%08x, found 0x%08x)\n", \
8531                           current_config->name, \
8532                           pipe_config->name); \
8533                 return false; \
8534         }
8535
8536 #define PIPE_CONF_CHECK_I(name) \
8537         if (current_config->name != pipe_config->name) { \
8538                 DRM_ERROR("mismatch in " #name " " \
8539                           "(expected %i, found %i)\n", \
8540                           current_config->name, \
8541                           pipe_config->name); \
8542                 return false; \
8543         }
8544
8545 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8546         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8547                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8548                           "(expected %i, found %i)\n", \
8549                           current_config->name & (mask), \
8550                           pipe_config->name & (mask)); \
8551                 return false; \
8552         }
8553
8554 #define PIPE_CONF_QUIRK(quirk)  \
8555         ((current_config->quirks | pipe_config->quirks) & (quirk))
8556
8557         PIPE_CONF_CHECK_I(cpu_transcoder);
8558
8559         PIPE_CONF_CHECK_I(has_pch_encoder);
8560         PIPE_CONF_CHECK_I(fdi_lanes);
8561         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8562         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8563         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8564         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8565         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8566
8567         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8568         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8569         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8570         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8571         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8572         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8573
8574         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8575         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8576         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8577         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8578         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8579         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8580
8581         PIPE_CONF_CHECK_I(pixel_multiplier);
8582
8583         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8584                               DRM_MODE_FLAG_INTERLACE);
8585
8586         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8587                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8588                                       DRM_MODE_FLAG_PHSYNC);
8589                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8590                                       DRM_MODE_FLAG_NHSYNC);
8591                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8592                                       DRM_MODE_FLAG_PVSYNC);
8593                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8594                                       DRM_MODE_FLAG_NVSYNC);
8595         }
8596
8597         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8598         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8599
8600         PIPE_CONF_CHECK_I(gmch_pfit.control);
8601         /* pfit ratios are autocomputed by the hw on gen4+ */
8602         if (INTEL_INFO(dev)->gen < 4)
8603                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8604         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8605         PIPE_CONF_CHECK_I(pch_pfit.enabled);
8606         if (current_config->pch_pfit.enabled) {
8607                 PIPE_CONF_CHECK_I(pch_pfit.pos);
8608                 PIPE_CONF_CHECK_I(pch_pfit.size);
8609         }
8610
8611         PIPE_CONF_CHECK_I(ips_enabled);
8612
8613         PIPE_CONF_CHECK_I(shared_dpll);
8614         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8615         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8616         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8617         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8618
8619 #undef PIPE_CONF_CHECK_X
8620 #undef PIPE_CONF_CHECK_I
8621 #undef PIPE_CONF_CHECK_FLAGS
8622 #undef PIPE_CONF_QUIRK
8623
8624         if (!IS_HASWELL(dev)) {
8625                 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8626                         DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8627                                   current_config->adjusted_mode.clock,
8628                                   pipe_config->adjusted_mode.clock);
8629                         return false;
8630                 }
8631         }
8632
8633         return true;
8634 }
8635
8636 static void
8637 check_connector_state(struct drm_device *dev)
8638 {
8639         struct intel_connector *connector;
8640
8641         list_for_each_entry(connector, &dev->mode_config.connector_list,
8642                             base.head) {
8643                 /* This also checks the encoder/connector hw state with the
8644                  * ->get_hw_state callbacks. */
8645                 intel_connector_check_state(connector);
8646
8647                 WARN(&connector->new_encoder->base != connector->base.encoder,
8648                      "connector's staged encoder doesn't match current encoder\n");
8649         }
8650 }
8651
8652 static void
8653 check_encoder_state(struct drm_device *dev)
8654 {
8655         struct intel_encoder *encoder;
8656         struct intel_connector *connector;
8657
8658         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8659                             base.head) {
8660                 bool enabled = false;
8661                 bool active = false;
8662                 enum pipe pipe, tracked_pipe;
8663
8664                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8665                               encoder->base.base.id,
8666                               drm_get_encoder_name(&encoder->base));
8667
8668                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8669                      "encoder's stage crtc doesn't match current crtc\n");
8670                 WARN(encoder->connectors_active && !encoder->base.crtc,
8671                      "encoder's active_connectors set, but no crtc\n");
8672
8673                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8674                                     base.head) {
8675                         if (connector->base.encoder != &encoder->base)
8676                                 continue;
8677                         enabled = true;
8678                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8679                                 active = true;
8680                 }
8681                 WARN(!!encoder->base.crtc != enabled,
8682                      "encoder's enabled state mismatch "
8683                      "(expected %i, found %i)\n",
8684                      !!encoder->base.crtc, enabled);
8685                 WARN(active && !encoder->base.crtc,
8686                      "active encoder with no crtc\n");
8687
8688                 WARN(encoder->connectors_active != active,
8689                      "encoder's computed active state doesn't match tracked active state "
8690                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8691
8692                 active = encoder->get_hw_state(encoder, &pipe);
8693                 WARN(active != encoder->connectors_active,
8694                      "encoder's hw state doesn't match sw tracking "
8695                      "(expected %i, found %i)\n",
8696                      encoder->connectors_active, active);
8697
8698                 if (!encoder->base.crtc)
8699                         continue;
8700
8701                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8702                 WARN(active && pipe != tracked_pipe,
8703                      "active encoder's pipe doesn't match"
8704                      "(expected %i, found %i)\n",
8705                      tracked_pipe, pipe);
8706
8707         }
8708 }
8709
8710 static void
8711 check_crtc_state(struct drm_device *dev)
8712 {
8713         drm_i915_private_t *dev_priv = dev->dev_private;
8714         struct intel_crtc *crtc;
8715         struct intel_encoder *encoder;
8716         struct intel_crtc_config pipe_config;
8717
8718         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8719                             base.head) {
8720                 bool enabled = false;
8721                 bool active = false;
8722
8723                 memset(&pipe_config, 0, sizeof(pipe_config));
8724
8725                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8726                               crtc->base.base.id);
8727
8728                 WARN(crtc->active && !crtc->base.enabled,
8729                      "active crtc, but not enabled in sw tracking\n");
8730
8731                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8732                                     base.head) {
8733                         if (encoder->base.crtc != &crtc->base)
8734                                 continue;
8735                         enabled = true;
8736                         if (encoder->connectors_active)
8737                                 active = true;
8738                 }
8739
8740                 WARN(active != crtc->active,
8741                      "crtc's computed active state doesn't match tracked active state "
8742                      "(expected %i, found %i)\n", active, crtc->active);
8743                 WARN(enabled != crtc->base.enabled,
8744                      "crtc's computed enabled state doesn't match tracked enabled state "
8745                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8746
8747                 active = dev_priv->display.get_pipe_config(crtc,
8748                                                            &pipe_config);
8749
8750                 /* hw state is inconsistent with the pipe A quirk */
8751                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8752                         active = crtc->active;
8753
8754                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8755                                     base.head) {
8756                         enum pipe pipe;
8757                         if (encoder->base.crtc != &crtc->base)
8758                                 continue;
8759                         if (encoder->get_config &&
8760                             encoder->get_hw_state(encoder, &pipe))
8761                                 encoder->get_config(encoder, &pipe_config);
8762                 }
8763
8764                 if (dev_priv->display.get_clock)
8765                         dev_priv->display.get_clock(crtc, &pipe_config);
8766
8767                 WARN(crtc->active != active,
8768                      "crtc active state doesn't match with hw state "
8769                      "(expected %i, found %i)\n", crtc->active, active);
8770
8771                 if (active &&
8772                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8773                         WARN(1, "pipe state doesn't match!\n");
8774                         intel_dump_pipe_config(crtc, &pipe_config,
8775                                                "[hw state]");
8776                         intel_dump_pipe_config(crtc, &crtc->config,
8777                                                "[sw state]");
8778                 }
8779         }
8780 }
8781
8782 static void
8783 check_shared_dpll_state(struct drm_device *dev)
8784 {
8785         drm_i915_private_t *dev_priv = dev->dev_private;
8786         struct intel_crtc *crtc;
8787         struct intel_dpll_hw_state dpll_hw_state;
8788         int i;
8789
8790         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8791                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8792                 int enabled_crtcs = 0, active_crtcs = 0;
8793                 bool active;
8794
8795                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8796
8797                 DRM_DEBUG_KMS("%s\n", pll->name);
8798
8799                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8800
8801                 WARN(pll->active > pll->refcount,
8802                      "more active pll users than references: %i vs %i\n",
8803                      pll->active, pll->refcount);
8804                 WARN(pll->active && !pll->on,
8805                      "pll in active use but not on in sw tracking\n");
8806                 WARN(pll->on && !pll->active,
8807                      "pll in on but not on in use in sw tracking\n");
8808                 WARN(pll->on != active,
8809                      "pll on state mismatch (expected %i, found %i)\n",
8810                      pll->on, active);
8811
8812                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8813                                     base.head) {
8814                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8815                                 enabled_crtcs++;
8816                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8817                                 active_crtcs++;
8818                 }
8819                 WARN(pll->active != active_crtcs,
8820                      "pll active crtcs mismatch (expected %i, found %i)\n",
8821                      pll->active, active_crtcs);
8822                 WARN(pll->refcount != enabled_crtcs,
8823                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8824                      pll->refcount, enabled_crtcs);
8825
8826                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8827                                        sizeof(dpll_hw_state)),
8828                      "pll hw state mismatch\n");
8829         }
8830 }
8831
8832 void
8833 intel_modeset_check_state(struct drm_device *dev)
8834 {
8835         check_connector_state(dev);
8836         check_encoder_state(dev);
8837         check_crtc_state(dev);
8838         check_shared_dpll_state(dev);
8839 }
8840
8841 static int __intel_set_mode(struct drm_crtc *crtc,
8842                             struct drm_display_mode *mode,
8843                             int x, int y, struct drm_framebuffer *fb)
8844 {
8845         struct drm_device *dev = crtc->dev;
8846         drm_i915_private_t *dev_priv = dev->dev_private;
8847         struct drm_display_mode *saved_mode, *saved_hwmode;
8848         struct intel_crtc_config *pipe_config = NULL;
8849         struct intel_crtc *intel_crtc;
8850         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8851         int ret = 0;
8852
8853         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8854         if (!saved_mode)
8855                 return -ENOMEM;
8856         saved_hwmode = saved_mode + 1;
8857
8858         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8859                                      &prepare_pipes, &disable_pipes);
8860
8861         *saved_hwmode = crtc->hwmode;
8862         *saved_mode = crtc->mode;
8863
8864         /* Hack: Because we don't (yet) support global modeset on multiple
8865          * crtcs, we don't keep track of the new mode for more than one crtc.
8866          * Hence simply check whether any bit is set in modeset_pipes in all the
8867          * pieces of code that are not yet converted to deal with mutliple crtcs
8868          * changing their mode at the same time. */
8869         if (modeset_pipes) {
8870                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8871                 if (IS_ERR(pipe_config)) {
8872                         ret = PTR_ERR(pipe_config);
8873                         pipe_config = NULL;
8874
8875                         goto out;
8876                 }
8877                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8878                                        "[modeset]");
8879         }
8880
8881         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8882                 intel_crtc_disable(&intel_crtc->base);
8883
8884         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8885                 if (intel_crtc->base.enabled)
8886                         dev_priv->display.crtc_disable(&intel_crtc->base);
8887         }
8888
8889         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8890          * to set it here already despite that we pass it down the callchain.
8891          */
8892         if (modeset_pipes) {
8893                 crtc->mode = *mode;
8894                 /* mode_set/enable/disable functions rely on a correct pipe
8895                  * config. */
8896                 to_intel_crtc(crtc)->config = *pipe_config;
8897         }
8898
8899         /* Only after disabling all output pipelines that will be changed can we
8900          * update the the output configuration. */
8901         intel_modeset_update_state(dev, prepare_pipes);
8902
8903         if (dev_priv->display.modeset_global_resources)
8904                 dev_priv->display.modeset_global_resources(dev);
8905
8906         /* Set up the DPLL and any encoders state that needs to adjust or depend
8907          * on the DPLL.
8908          */
8909         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8910                 ret = intel_crtc_mode_set(&intel_crtc->base,
8911                                           x, y, fb);
8912                 if (ret)
8913                         goto done;
8914         }
8915
8916         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8917         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8918                 dev_priv->display.crtc_enable(&intel_crtc->base);
8919
8920         if (modeset_pipes) {
8921                 /* Store real post-adjustment hardware mode. */
8922                 crtc->hwmode = pipe_config->adjusted_mode;
8923
8924                 /* Calculate and store various constants which
8925                  * are later needed by vblank and swap-completion
8926                  * timestamping. They are derived from true hwmode.
8927                  */
8928                 drm_calc_timestamping_constants(crtc);
8929         }
8930
8931         /* FIXME: add subpixel order */
8932 done:
8933         if (ret && crtc->enabled) {
8934                 crtc->hwmode = *saved_hwmode;
8935                 crtc->mode = *saved_mode;
8936         }
8937
8938 out:
8939         kfree(pipe_config);
8940         kfree(saved_mode);
8941         return ret;
8942 }
8943
8944 static int intel_set_mode(struct drm_crtc *crtc,
8945                           struct drm_display_mode *mode,
8946                           int x, int y, struct drm_framebuffer *fb)
8947 {
8948         int ret;
8949
8950         ret = __intel_set_mode(crtc, mode, x, y, fb);
8951
8952         if (ret == 0)
8953                 intel_modeset_check_state(crtc->dev);
8954
8955         return ret;
8956 }
8957
8958 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8959 {
8960         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8961 }
8962
8963 #undef for_each_intel_crtc_masked
8964
8965 static void intel_set_config_free(struct intel_set_config *config)
8966 {
8967         if (!config)
8968                 return;
8969
8970         kfree(config->save_connector_encoders);
8971         kfree(config->save_encoder_crtcs);
8972         kfree(config);
8973 }
8974
8975 static int intel_set_config_save_state(struct drm_device *dev,
8976                                        struct intel_set_config *config)
8977 {
8978         struct drm_encoder *encoder;
8979         struct drm_connector *connector;
8980         int count;
8981
8982         config->save_encoder_crtcs =
8983                 kcalloc(dev->mode_config.num_encoder,
8984                         sizeof(struct drm_crtc *), GFP_KERNEL);
8985         if (!config->save_encoder_crtcs)
8986                 return -ENOMEM;
8987
8988         config->save_connector_encoders =
8989                 kcalloc(dev->mode_config.num_connector,
8990                         sizeof(struct drm_encoder *), GFP_KERNEL);
8991         if (!config->save_connector_encoders)
8992                 return -ENOMEM;
8993
8994         /* Copy data. Note that driver private data is not affected.
8995          * Should anything bad happen only the expected state is
8996          * restored, not the drivers personal bookkeeping.
8997          */
8998         count = 0;
8999         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9000                 config->save_encoder_crtcs[count++] = encoder->crtc;
9001         }
9002
9003         count = 0;
9004         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9005                 config->save_connector_encoders[count++] = connector->encoder;
9006         }
9007
9008         return 0;
9009 }
9010
9011 static void intel_set_config_restore_state(struct drm_device *dev,
9012                                            struct intel_set_config *config)
9013 {
9014         struct intel_encoder *encoder;
9015         struct intel_connector *connector;
9016         int count;
9017
9018         count = 0;
9019         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9020                 encoder->new_crtc =
9021                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9022         }
9023
9024         count = 0;
9025         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9026                 connector->new_encoder =
9027                         to_intel_encoder(config->save_connector_encoders[count++]);
9028         }
9029 }
9030
9031 static bool
9032 is_crtc_connector_off(struct drm_mode_set *set)
9033 {
9034         int i;
9035
9036         if (set->num_connectors == 0)
9037                 return false;
9038
9039         if (WARN_ON(set->connectors == NULL))
9040                 return false;
9041
9042         for (i = 0; i < set->num_connectors; i++)
9043                 if (set->connectors[i]->encoder &&
9044                     set->connectors[i]->encoder->crtc == set->crtc &&
9045                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9046                         return true;
9047
9048         return false;
9049 }
9050
9051 static void
9052 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9053                                       struct intel_set_config *config)
9054 {
9055
9056         /* We should be able to check here if the fb has the same properties
9057          * and then just flip_or_move it */
9058         if (is_crtc_connector_off(set)) {
9059                 config->mode_changed = true;
9060         } else if (set->crtc->fb != set->fb) {
9061                 /* If we have no fb then treat it as a full mode set */
9062                 if (set->crtc->fb == NULL) {
9063                         struct intel_crtc *intel_crtc =
9064                                 to_intel_crtc(set->crtc);
9065
9066                         if (intel_crtc->active && i915_fastboot) {
9067                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9068                                 config->fb_changed = true;
9069                         } else {
9070                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9071                                 config->mode_changed = true;
9072                         }
9073                 } else if (set->fb == NULL) {
9074                         config->mode_changed = true;
9075                 } else if (set->fb->pixel_format !=
9076                            set->crtc->fb->pixel_format) {
9077                         config->mode_changed = true;
9078                 } else {
9079                         config->fb_changed = true;
9080                 }
9081         }
9082
9083         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9084                 config->fb_changed = true;
9085
9086         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9087                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9088                 drm_mode_debug_printmodeline(&set->crtc->mode);
9089                 drm_mode_debug_printmodeline(set->mode);
9090                 config->mode_changed = true;
9091         }
9092
9093         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9094                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9095 }
9096
9097 static int
9098 intel_modeset_stage_output_state(struct drm_device *dev,
9099                                  struct drm_mode_set *set,
9100                                  struct intel_set_config *config)
9101 {
9102         struct drm_crtc *new_crtc;
9103         struct intel_connector *connector;
9104         struct intel_encoder *encoder;
9105         int ro;
9106
9107         /* The upper layers ensure that we either disable a crtc or have a list
9108          * of connectors. For paranoia, double-check this. */
9109         WARN_ON(!set->fb && (set->num_connectors != 0));
9110         WARN_ON(set->fb && (set->num_connectors == 0));
9111
9112         list_for_each_entry(connector, &dev->mode_config.connector_list,
9113                             base.head) {
9114                 /* Otherwise traverse passed in connector list and get encoders
9115                  * for them. */
9116                 for (ro = 0; ro < set->num_connectors; ro++) {
9117                         if (set->connectors[ro] == &connector->base) {
9118                                 connector->new_encoder = connector->encoder;
9119                                 break;
9120                         }
9121                 }
9122
9123                 /* If we disable the crtc, disable all its connectors. Also, if
9124                  * the connector is on the changing crtc but not on the new
9125                  * connector list, disable it. */
9126                 if ((!set->fb || ro == set->num_connectors) &&
9127                     connector->base.encoder &&
9128                     connector->base.encoder->crtc == set->crtc) {
9129                         connector->new_encoder = NULL;
9130
9131                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9132                                 connector->base.base.id,
9133                                 drm_get_connector_name(&connector->base));
9134                 }
9135
9136
9137                 if (&connector->new_encoder->base != connector->base.encoder) {
9138                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9139                         config->mode_changed = true;
9140                 }
9141         }
9142         /* connector->new_encoder is now updated for all connectors. */
9143
9144         /* Update crtc of enabled connectors. */
9145         list_for_each_entry(connector, &dev->mode_config.connector_list,
9146                             base.head) {
9147                 if (!connector->new_encoder)
9148                         continue;
9149
9150                 new_crtc = connector->new_encoder->base.crtc;
9151
9152                 for (ro = 0; ro < set->num_connectors; ro++) {
9153                         if (set->connectors[ro] == &connector->base)
9154                                 new_crtc = set->crtc;
9155                 }
9156
9157                 /* Make sure the new CRTC will work with the encoder */
9158                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9159                                            new_crtc)) {
9160                         return -EINVAL;
9161                 }
9162                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9163
9164                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9165                         connector->base.base.id,
9166                         drm_get_connector_name(&connector->base),
9167                         new_crtc->base.id);
9168         }
9169
9170         /* Check for any encoders that needs to be disabled. */
9171         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9172                             base.head) {
9173                 list_for_each_entry(connector,
9174                                     &dev->mode_config.connector_list,
9175                                     base.head) {
9176                         if (connector->new_encoder == encoder) {
9177                                 WARN_ON(!connector->new_encoder->new_crtc);
9178
9179                                 goto next_encoder;
9180                         }
9181                 }
9182                 encoder->new_crtc = NULL;
9183 next_encoder:
9184                 /* Only now check for crtc changes so we don't miss encoders
9185                  * that will be disabled. */
9186                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9187                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9188                         config->mode_changed = true;
9189                 }
9190         }
9191         /* Now we've also updated encoder->new_crtc for all encoders. */
9192
9193         return 0;
9194 }
9195
9196 static int intel_crtc_set_config(struct drm_mode_set *set)
9197 {
9198         struct drm_device *dev;
9199         struct drm_mode_set save_set;
9200         struct intel_set_config *config;
9201         int ret;
9202
9203         BUG_ON(!set);
9204         BUG_ON(!set->crtc);
9205         BUG_ON(!set->crtc->helper_private);
9206
9207         /* Enforce sane interface api - has been abused by the fb helper. */
9208         BUG_ON(!set->mode && set->fb);
9209         BUG_ON(set->fb && set->num_connectors == 0);
9210
9211         if (set->fb) {
9212                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9213                                 set->crtc->base.id, set->fb->base.id,
9214                                 (int)set->num_connectors, set->x, set->y);
9215         } else {
9216                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9217         }
9218
9219         dev = set->crtc->dev;
9220
9221         ret = -ENOMEM;
9222         config = kzalloc(sizeof(*config), GFP_KERNEL);
9223         if (!config)
9224                 goto out_config;
9225
9226         ret = intel_set_config_save_state(dev, config);
9227         if (ret)
9228                 goto out_config;
9229
9230         save_set.crtc = set->crtc;
9231         save_set.mode = &set->crtc->mode;
9232         save_set.x = set->crtc->x;
9233         save_set.y = set->crtc->y;
9234         save_set.fb = set->crtc->fb;
9235
9236         /* Compute whether we need a full modeset, only an fb base update or no
9237          * change at all. In the future we might also check whether only the
9238          * mode changed, e.g. for LVDS where we only change the panel fitter in
9239          * such cases. */
9240         intel_set_config_compute_mode_changes(set, config);
9241
9242         ret = intel_modeset_stage_output_state(dev, set, config);
9243         if (ret)
9244                 goto fail;
9245
9246         if (config->mode_changed) {
9247                 ret = intel_set_mode(set->crtc, set->mode,
9248                                      set->x, set->y, set->fb);
9249         } else if (config->fb_changed) {
9250                 intel_crtc_wait_for_pending_flips(set->crtc);
9251
9252                 ret = intel_pipe_set_base(set->crtc,
9253                                           set->x, set->y, set->fb);
9254         }
9255
9256         if (ret) {
9257                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9258                               set->crtc->base.id, ret);
9259 fail:
9260                 intel_set_config_restore_state(dev, config);
9261
9262                 /* Try to restore the config */
9263                 if (config->mode_changed &&
9264                     intel_set_mode(save_set.crtc, save_set.mode,
9265                                    save_set.x, save_set.y, save_set.fb))
9266                         DRM_ERROR("failed to restore config after modeset failure\n");
9267         }
9268
9269 out_config:
9270         intel_set_config_free(config);
9271         return ret;
9272 }
9273
9274 static const struct drm_crtc_funcs intel_crtc_funcs = {
9275         .cursor_set = intel_crtc_cursor_set,
9276         .cursor_move = intel_crtc_cursor_move,
9277         .gamma_set = intel_crtc_gamma_set,
9278         .set_config = intel_crtc_set_config,
9279         .destroy = intel_crtc_destroy,
9280         .page_flip = intel_crtc_page_flip,
9281 };
9282
9283 static void intel_cpu_pll_init(struct drm_device *dev)
9284 {
9285         if (HAS_DDI(dev))
9286                 intel_ddi_pll_init(dev);
9287 }
9288
9289 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9290                                       struct intel_shared_dpll *pll,
9291                                       struct intel_dpll_hw_state *hw_state)
9292 {
9293         uint32_t val;
9294
9295         val = I915_READ(PCH_DPLL(pll->id));
9296         hw_state->dpll = val;
9297         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9298         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9299
9300         return val & DPLL_VCO_ENABLE;
9301 }
9302
9303 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9304                                   struct intel_shared_dpll *pll)
9305 {
9306         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9307         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9308 }
9309
9310 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9311                                 struct intel_shared_dpll *pll)
9312 {
9313         /* PCH refclock must be enabled first */
9314         assert_pch_refclk_enabled(dev_priv);
9315
9316         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9317
9318         /* Wait for the clocks to stabilize. */
9319         POSTING_READ(PCH_DPLL(pll->id));
9320         udelay(150);
9321
9322         /* The pixel multiplier can only be updated once the
9323          * DPLL is enabled and the clocks are stable.
9324          *
9325          * So write it again.
9326          */
9327         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9328         POSTING_READ(PCH_DPLL(pll->id));
9329         udelay(200);
9330 }
9331
9332 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9333                                  struct intel_shared_dpll *pll)
9334 {
9335         struct drm_device *dev = dev_priv->dev;
9336         struct intel_crtc *crtc;
9337
9338         /* Make sure no transcoder isn't still depending on us. */
9339         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9340                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9341                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9342         }
9343
9344         I915_WRITE(PCH_DPLL(pll->id), 0);
9345         POSTING_READ(PCH_DPLL(pll->id));
9346         udelay(200);
9347 }
9348
9349 static char *ibx_pch_dpll_names[] = {
9350         "PCH DPLL A",
9351         "PCH DPLL B",
9352 };
9353
9354 static void ibx_pch_dpll_init(struct drm_device *dev)
9355 {
9356         struct drm_i915_private *dev_priv = dev->dev_private;
9357         int i;
9358
9359         dev_priv->num_shared_dpll = 2;
9360
9361         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9362                 dev_priv->shared_dplls[i].id = i;
9363                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9364                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9365                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9366                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9367                 dev_priv->shared_dplls[i].get_hw_state =
9368                         ibx_pch_dpll_get_hw_state;
9369         }
9370 }
9371
9372 static void intel_shared_dpll_init(struct drm_device *dev)
9373 {
9374         struct drm_i915_private *dev_priv = dev->dev_private;
9375
9376         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9377                 ibx_pch_dpll_init(dev);
9378         else
9379                 dev_priv->num_shared_dpll = 0;
9380
9381         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9382         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9383                       dev_priv->num_shared_dpll);
9384 }
9385
9386 static void intel_crtc_init(struct drm_device *dev, int pipe)
9387 {
9388         drm_i915_private_t *dev_priv = dev->dev_private;
9389         struct intel_crtc *intel_crtc;
9390         int i;
9391
9392         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9393         if (intel_crtc == NULL)
9394                 return;
9395
9396         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9397
9398         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9399         for (i = 0; i < 256; i++) {
9400                 intel_crtc->lut_r[i] = i;
9401                 intel_crtc->lut_g[i] = i;
9402                 intel_crtc->lut_b[i] = i;
9403         }
9404
9405         /* Swap pipes & planes for FBC on pre-965 */
9406         intel_crtc->pipe = pipe;
9407         intel_crtc->plane = pipe;
9408         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9409                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9410                 intel_crtc->plane = !pipe;
9411         }
9412
9413         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9414                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9415         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9416         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9417
9418         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9419 }
9420
9421 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9422                                 struct drm_file *file)
9423 {
9424         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9425         struct drm_mode_object *drmmode_obj;
9426         struct intel_crtc *crtc;
9427
9428         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9429                 return -ENODEV;
9430
9431         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9432                         DRM_MODE_OBJECT_CRTC);
9433
9434         if (!drmmode_obj) {
9435                 DRM_ERROR("no such CRTC id\n");
9436                 return -EINVAL;
9437         }
9438
9439         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9440         pipe_from_crtc_id->pipe = crtc->pipe;
9441
9442         return 0;
9443 }
9444
9445 static int intel_encoder_clones(struct intel_encoder *encoder)
9446 {
9447         struct drm_device *dev = encoder->base.dev;
9448         struct intel_encoder *source_encoder;
9449         int index_mask = 0;
9450         int entry = 0;
9451
9452         list_for_each_entry(source_encoder,
9453                             &dev->mode_config.encoder_list, base.head) {
9454
9455                 if (encoder == source_encoder)
9456                         index_mask |= (1 << entry);
9457
9458                 /* Intel hw has only one MUX where enocoders could be cloned. */
9459                 if (encoder->cloneable && source_encoder->cloneable)
9460                         index_mask |= (1 << entry);
9461
9462                 entry++;
9463         }
9464
9465         return index_mask;
9466 }
9467
9468 static bool has_edp_a(struct drm_device *dev)
9469 {
9470         struct drm_i915_private *dev_priv = dev->dev_private;
9471
9472         if (!IS_MOBILE(dev))
9473                 return false;
9474
9475         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9476                 return false;
9477
9478         if (IS_GEN5(dev) &&
9479             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9480                 return false;
9481
9482         return true;
9483 }
9484
9485 static void intel_setup_outputs(struct drm_device *dev)
9486 {
9487         struct drm_i915_private *dev_priv = dev->dev_private;
9488         struct intel_encoder *encoder;
9489         bool dpd_is_edp = false;
9490
9491         intel_lvds_init(dev);
9492
9493         if (!IS_ULT(dev))
9494                 intel_crt_init(dev);
9495
9496         if (HAS_DDI(dev)) {
9497                 int found;
9498
9499                 /* Haswell uses DDI functions to detect digital outputs */
9500                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9501                 /* DDI A only supports eDP */
9502                 if (found)
9503                         intel_ddi_init(dev, PORT_A);
9504
9505                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9506                  * register */
9507                 found = I915_READ(SFUSE_STRAP);
9508
9509                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9510                         intel_ddi_init(dev, PORT_B);
9511                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9512                         intel_ddi_init(dev, PORT_C);
9513                 if (found & SFUSE_STRAP_DDID_DETECTED)
9514                         intel_ddi_init(dev, PORT_D);
9515         } else if (HAS_PCH_SPLIT(dev)) {
9516                 int found;
9517                 dpd_is_edp = intel_dpd_is_edp(dev);
9518
9519                 if (has_edp_a(dev))
9520                         intel_dp_init(dev, DP_A, PORT_A);
9521
9522                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9523                         /* PCH SDVOB multiplex with HDMIB */
9524                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9525                         if (!found)
9526                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9527                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9528                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9529                 }
9530
9531                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9532                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9533
9534                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9535                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9536
9537                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9538                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9539
9540                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9541                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9542         } else if (IS_VALLEYVIEW(dev)) {
9543                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9544                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9545                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9546                                         PORT_C);
9547                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9548                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9549                                               PORT_C);
9550                 }
9551
9552                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9553                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9554                                         PORT_B);
9555                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9556                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9557                 }
9558         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9559                 bool found = false;
9560
9561                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9562                         DRM_DEBUG_KMS("probing SDVOB\n");
9563                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9564                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9565                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9566                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9567                         }
9568
9569                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9570                                 intel_dp_init(dev, DP_B, PORT_B);
9571                 }
9572
9573                 /* Before G4X SDVOC doesn't have its own detect register */
9574
9575                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9576                         DRM_DEBUG_KMS("probing SDVOC\n");
9577                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9578                 }
9579
9580                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9581
9582                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9583                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9584                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9585                         }
9586                         if (SUPPORTS_INTEGRATED_DP(dev))
9587                                 intel_dp_init(dev, DP_C, PORT_C);
9588                 }
9589
9590                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9591                     (I915_READ(DP_D) & DP_DETECTED))
9592                         intel_dp_init(dev, DP_D, PORT_D);
9593         } else if (IS_GEN2(dev))
9594                 intel_dvo_init(dev);
9595
9596         if (SUPPORTS_TV(dev))
9597                 intel_tv_init(dev);
9598
9599         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9600                 encoder->base.possible_crtcs = encoder->crtc_mask;
9601                 encoder->base.possible_clones =
9602                         intel_encoder_clones(encoder);
9603         }
9604
9605         intel_init_pch_refclk(dev);
9606
9607         drm_helper_move_panel_connectors_to_head(dev);
9608 }
9609
9610 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9611 {
9612         drm_framebuffer_cleanup(&fb->base);
9613         drm_gem_object_unreference_unlocked(&fb->obj->base);
9614 }
9615
9616 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9617 {
9618         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9619
9620         intel_framebuffer_fini(intel_fb);
9621         kfree(intel_fb);
9622 }
9623
9624 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9625                                                 struct drm_file *file,
9626                                                 unsigned int *handle)
9627 {
9628         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9629         struct drm_i915_gem_object *obj = intel_fb->obj;
9630
9631         return drm_gem_handle_create(file, &obj->base, handle);
9632 }
9633
9634 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9635         .destroy = intel_user_framebuffer_destroy,
9636         .create_handle = intel_user_framebuffer_create_handle,
9637 };
9638
9639 int intel_framebuffer_init(struct drm_device *dev,
9640                            struct intel_framebuffer *intel_fb,
9641                            struct drm_mode_fb_cmd2 *mode_cmd,
9642                            struct drm_i915_gem_object *obj)
9643 {
9644         int pitch_limit;
9645         int ret;
9646
9647         if (obj->tiling_mode == I915_TILING_Y) {
9648                 DRM_DEBUG("hardware does not support tiling Y\n");
9649                 return -EINVAL;
9650         }
9651
9652         if (mode_cmd->pitches[0] & 63) {
9653                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9654                           mode_cmd->pitches[0]);
9655                 return -EINVAL;
9656         }
9657
9658         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9659                 pitch_limit = 32*1024;
9660         } else if (INTEL_INFO(dev)->gen >= 4) {
9661                 if (obj->tiling_mode)
9662                         pitch_limit = 16*1024;
9663                 else
9664                         pitch_limit = 32*1024;
9665         } else if (INTEL_INFO(dev)->gen >= 3) {
9666                 if (obj->tiling_mode)
9667                         pitch_limit = 8*1024;
9668                 else
9669                         pitch_limit = 16*1024;
9670         } else
9671                 /* XXX DSPC is limited to 4k tiled */
9672                 pitch_limit = 8*1024;
9673
9674         if (mode_cmd->pitches[0] > pitch_limit) {
9675                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9676                           obj->tiling_mode ? "tiled" : "linear",
9677                           mode_cmd->pitches[0], pitch_limit);
9678                 return -EINVAL;
9679         }
9680
9681         if (obj->tiling_mode != I915_TILING_NONE &&
9682             mode_cmd->pitches[0] != obj->stride) {
9683                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9684                           mode_cmd->pitches[0], obj->stride);
9685                 return -EINVAL;
9686         }
9687
9688         /* Reject formats not supported by any plane early. */
9689         switch (mode_cmd->pixel_format) {
9690         case DRM_FORMAT_C8:
9691         case DRM_FORMAT_RGB565:
9692         case DRM_FORMAT_XRGB8888:
9693         case DRM_FORMAT_ARGB8888:
9694                 break;
9695         case DRM_FORMAT_XRGB1555:
9696         case DRM_FORMAT_ARGB1555:
9697                 if (INTEL_INFO(dev)->gen > 3) {
9698                         DRM_DEBUG("unsupported pixel format: %s\n",
9699                                   drm_get_format_name(mode_cmd->pixel_format));
9700                         return -EINVAL;
9701                 }
9702                 break;
9703         case DRM_FORMAT_XBGR8888:
9704         case DRM_FORMAT_ABGR8888:
9705         case DRM_FORMAT_XRGB2101010:
9706         case DRM_FORMAT_ARGB2101010:
9707         case DRM_FORMAT_XBGR2101010:
9708         case DRM_FORMAT_ABGR2101010:
9709                 if (INTEL_INFO(dev)->gen < 4) {
9710                         DRM_DEBUG("unsupported pixel format: %s\n",
9711                                   drm_get_format_name(mode_cmd->pixel_format));
9712                         return -EINVAL;
9713                 }
9714                 break;
9715         case DRM_FORMAT_YUYV:
9716         case DRM_FORMAT_UYVY:
9717         case DRM_FORMAT_YVYU:
9718         case DRM_FORMAT_VYUY:
9719                 if (INTEL_INFO(dev)->gen < 5) {
9720                         DRM_DEBUG("unsupported pixel format: %s\n",
9721                                   drm_get_format_name(mode_cmd->pixel_format));
9722                         return -EINVAL;
9723                 }
9724                 break;
9725         default:
9726                 DRM_DEBUG("unsupported pixel format: %s\n",
9727                           drm_get_format_name(mode_cmd->pixel_format));
9728                 return -EINVAL;
9729         }
9730
9731         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9732         if (mode_cmd->offsets[0] != 0)
9733                 return -EINVAL;
9734
9735         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9736         intel_fb->obj = obj;
9737
9738         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9739         if (ret) {
9740                 DRM_ERROR("framebuffer init failed %d\n", ret);
9741                 return ret;
9742         }
9743
9744         return 0;
9745 }
9746
9747 static struct drm_framebuffer *
9748 intel_user_framebuffer_create(struct drm_device *dev,
9749                               struct drm_file *filp,
9750                               struct drm_mode_fb_cmd2 *mode_cmd)
9751 {
9752         struct drm_i915_gem_object *obj;
9753
9754         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9755                                                 mode_cmd->handles[0]));
9756         if (&obj->base == NULL)
9757                 return ERR_PTR(-ENOENT);
9758
9759         return intel_framebuffer_create(dev, mode_cmd, obj);
9760 }
9761
9762 static const struct drm_mode_config_funcs intel_mode_funcs = {
9763         .fb_create = intel_user_framebuffer_create,
9764         .output_poll_changed = intel_fb_output_poll_changed,
9765 };
9766
9767 /* Set up chip specific display functions */
9768 static void intel_init_display(struct drm_device *dev)
9769 {
9770         struct drm_i915_private *dev_priv = dev->dev_private;
9771
9772         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9773                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9774         else if (IS_VALLEYVIEW(dev))
9775                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9776         else if (IS_PINEVIEW(dev))
9777                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9778         else
9779                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9780
9781         if (HAS_DDI(dev)) {
9782                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9783                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9784                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9785                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9786                 dev_priv->display.off = haswell_crtc_off;
9787                 dev_priv->display.update_plane = ironlake_update_plane;
9788         } else if (HAS_PCH_SPLIT(dev)) {
9789                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9790                 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9791                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9792                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9793                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9794                 dev_priv->display.off = ironlake_crtc_off;
9795                 dev_priv->display.update_plane = ironlake_update_plane;
9796         } else if (IS_VALLEYVIEW(dev)) {
9797                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9798                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9799                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9800                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9801                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9802                 dev_priv->display.off = i9xx_crtc_off;
9803                 dev_priv->display.update_plane = i9xx_update_plane;
9804         } else {
9805                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9806                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9807                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9808                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9809                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9810                 dev_priv->display.off = i9xx_crtc_off;
9811                 dev_priv->display.update_plane = i9xx_update_plane;
9812         }
9813
9814         /* Returns the core display clock speed */
9815         if (IS_VALLEYVIEW(dev))
9816                 dev_priv->display.get_display_clock_speed =
9817                         valleyview_get_display_clock_speed;
9818         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9819                 dev_priv->display.get_display_clock_speed =
9820                         i945_get_display_clock_speed;
9821         else if (IS_I915G(dev))
9822                 dev_priv->display.get_display_clock_speed =
9823                         i915_get_display_clock_speed;
9824         else if (IS_I945GM(dev) || IS_845G(dev))
9825                 dev_priv->display.get_display_clock_speed =
9826                         i9xx_misc_get_display_clock_speed;
9827         else if (IS_PINEVIEW(dev))
9828                 dev_priv->display.get_display_clock_speed =
9829                         pnv_get_display_clock_speed;
9830         else if (IS_I915GM(dev))
9831                 dev_priv->display.get_display_clock_speed =
9832                         i915gm_get_display_clock_speed;
9833         else if (IS_I865G(dev))
9834                 dev_priv->display.get_display_clock_speed =
9835                         i865_get_display_clock_speed;
9836         else if (IS_I85X(dev))
9837                 dev_priv->display.get_display_clock_speed =
9838                         i855_get_display_clock_speed;
9839         else /* 852, 830 */
9840                 dev_priv->display.get_display_clock_speed =
9841                         i830_get_display_clock_speed;
9842
9843         if (HAS_PCH_SPLIT(dev)) {
9844                 if (IS_GEN5(dev)) {
9845                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9846                         dev_priv->display.write_eld = ironlake_write_eld;
9847                 } else if (IS_GEN6(dev)) {
9848                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9849                         dev_priv->display.write_eld = ironlake_write_eld;
9850                 } else if (IS_IVYBRIDGE(dev)) {
9851                         /* FIXME: detect B0+ stepping and use auto training */
9852                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9853                         dev_priv->display.write_eld = ironlake_write_eld;
9854                         dev_priv->display.modeset_global_resources =
9855                                 ivb_modeset_global_resources;
9856                 } else if (IS_HASWELL(dev)) {
9857                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9858                         dev_priv->display.write_eld = haswell_write_eld;
9859                         dev_priv->display.modeset_global_resources =
9860                                 haswell_modeset_global_resources;
9861                 }
9862         } else if (IS_G4X(dev)) {
9863                 dev_priv->display.write_eld = g4x_write_eld;
9864         }
9865
9866         /* Default just returns -ENODEV to indicate unsupported */
9867         dev_priv->display.queue_flip = intel_default_queue_flip;
9868
9869         switch (INTEL_INFO(dev)->gen) {
9870         case 2:
9871                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9872                 break;
9873
9874         case 3:
9875                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9876                 break;
9877
9878         case 4:
9879         case 5:
9880                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9881                 break;
9882
9883         case 6:
9884                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9885                 break;
9886         case 7:
9887                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9888                 break;
9889         }
9890 }
9891
9892 /*
9893  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9894  * resume, or other times.  This quirk makes sure that's the case for
9895  * affected systems.
9896  */
9897 static void quirk_pipea_force(struct drm_device *dev)
9898 {
9899         struct drm_i915_private *dev_priv = dev->dev_private;
9900
9901         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9902         DRM_INFO("applying pipe a force quirk\n");
9903 }
9904
9905 /*
9906  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9907  */
9908 static void quirk_ssc_force_disable(struct drm_device *dev)
9909 {
9910         struct drm_i915_private *dev_priv = dev->dev_private;
9911         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9912         DRM_INFO("applying lvds SSC disable quirk\n");
9913 }
9914
9915 /*
9916  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9917  * brightness value
9918  */
9919 static void quirk_invert_brightness(struct drm_device *dev)
9920 {
9921         struct drm_i915_private *dev_priv = dev->dev_private;
9922         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9923         DRM_INFO("applying inverted panel brightness quirk\n");
9924 }
9925
9926 /*
9927  * Some machines (Dell XPS13) suffer broken backlight controls if
9928  * BLM_PCH_PWM_ENABLE is set.
9929  */
9930 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9931 {
9932         struct drm_i915_private *dev_priv = dev->dev_private;
9933         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9934         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9935 }
9936
9937 struct intel_quirk {
9938         int device;
9939         int subsystem_vendor;
9940         int subsystem_device;
9941         void (*hook)(struct drm_device *dev);
9942 };
9943
9944 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9945 struct intel_dmi_quirk {
9946         void (*hook)(struct drm_device *dev);
9947         const struct dmi_system_id (*dmi_id_list)[];
9948 };
9949
9950 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9951 {
9952         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9953         return 1;
9954 }
9955
9956 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9957         {
9958                 .dmi_id_list = &(const struct dmi_system_id[]) {
9959                         {
9960                                 .callback = intel_dmi_reverse_brightness,
9961                                 .ident = "NCR Corporation",
9962                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9963                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9964                                 },
9965                         },
9966                         { }  /* terminating entry */
9967                 },
9968                 .hook = quirk_invert_brightness,
9969         },
9970 };
9971
9972 static struct intel_quirk intel_quirks[] = {
9973         /* HP Mini needs pipe A force quirk (LP: #322104) */
9974         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9975
9976         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9977         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9978
9979         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9980         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9981
9982         /* 830/845 need to leave pipe A & dpll A up */
9983         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9984         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9985
9986         /* Lenovo U160 cannot use SSC on LVDS */
9987         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9988
9989         /* Sony Vaio Y cannot use SSC on LVDS */
9990         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9991
9992         /* Acer Aspire 5734Z must invert backlight brightness */
9993         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9994
9995         /* Acer/eMachines G725 */
9996         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9997
9998         /* Acer/eMachines e725 */
9999         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
10000
10001         /* Acer/Packard Bell NCL20 */
10002         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
10003
10004         /* Acer Aspire 4736Z */
10005         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
10006
10007         /* Dell XPS13 HD Sandy Bridge */
10008         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10009         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10010         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10011 };
10012
10013 static void intel_init_quirks(struct drm_device *dev)
10014 {
10015         struct pci_dev *d = dev->pdev;
10016         int i;
10017
10018         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10019                 struct intel_quirk *q = &intel_quirks[i];
10020
10021                 if (d->device == q->device &&
10022                     (d->subsystem_vendor == q->subsystem_vendor ||
10023                      q->subsystem_vendor == PCI_ANY_ID) &&
10024                     (d->subsystem_device == q->subsystem_device ||
10025                      q->subsystem_device == PCI_ANY_ID))
10026                         q->hook(dev);
10027         }
10028         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10029                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10030                         intel_dmi_quirks[i].hook(dev);
10031         }
10032 }
10033
10034 /* Disable the VGA plane that we never use */
10035 static void i915_disable_vga(struct drm_device *dev)
10036 {
10037         struct drm_i915_private *dev_priv = dev->dev_private;
10038         u8 sr1;
10039         u32 vga_reg = i915_vgacntrl_reg(dev);
10040
10041         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10042         outb(SR01, VGA_SR_INDEX);
10043         sr1 = inb(VGA_SR_DATA);
10044         outb(sr1 | 1<<5, VGA_SR_DATA);
10045         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10046         udelay(300);
10047
10048         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10049         POSTING_READ(vga_reg);
10050 }
10051
10052 static void i915_enable_vga_mem(struct drm_device *dev)
10053 {
10054         /* Enable VGA memory on Intel HD */
10055         if (HAS_PCH_SPLIT(dev)) {
10056                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10057                 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10058                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10059                                                    VGA_RSRC_LEGACY_MEM |
10060                                                    VGA_RSRC_NORMAL_IO |
10061                                                    VGA_RSRC_NORMAL_MEM);
10062                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10063         }
10064 }
10065
10066 void i915_disable_vga_mem(struct drm_device *dev)
10067 {
10068         /* Disable VGA memory on Intel HD */
10069         if (HAS_PCH_SPLIT(dev)) {
10070                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10071                 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10072                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10073                                                    VGA_RSRC_NORMAL_IO |
10074                                                    VGA_RSRC_NORMAL_MEM);
10075                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10076         }
10077 }
10078
10079 void intel_modeset_init_hw(struct drm_device *dev)
10080 {
10081         intel_init_power_well(dev);
10082
10083         intel_prepare_ddi(dev);
10084
10085         intel_init_clock_gating(dev);
10086
10087         mutex_lock(&dev->struct_mutex);
10088         intel_enable_gt_powersave(dev);
10089         mutex_unlock(&dev->struct_mutex);
10090 }
10091
10092 void intel_modeset_suspend_hw(struct drm_device *dev)
10093 {
10094         intel_suspend_hw(dev);
10095 }
10096
10097 void intel_modeset_init(struct drm_device *dev)
10098 {
10099         struct drm_i915_private *dev_priv = dev->dev_private;
10100         int i, j, ret;
10101
10102         drm_mode_config_init(dev);
10103
10104         dev->mode_config.min_width = 0;
10105         dev->mode_config.min_height = 0;
10106
10107         dev->mode_config.preferred_depth = 24;
10108         dev->mode_config.prefer_shadow = 1;
10109
10110         dev->mode_config.funcs = &intel_mode_funcs;
10111
10112         intel_init_quirks(dev);
10113
10114         intel_init_pm(dev);
10115
10116         if (INTEL_INFO(dev)->num_pipes == 0)
10117                 return;
10118
10119         intel_init_display(dev);
10120
10121         if (IS_GEN2(dev)) {
10122                 dev->mode_config.max_width = 2048;
10123                 dev->mode_config.max_height = 2048;
10124         } else if (IS_GEN3(dev)) {
10125                 dev->mode_config.max_width = 4096;
10126                 dev->mode_config.max_height = 4096;
10127         } else {
10128                 dev->mode_config.max_width = 8192;
10129                 dev->mode_config.max_height = 8192;
10130         }
10131         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10132
10133         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10134                       INTEL_INFO(dev)->num_pipes,
10135                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10136
10137         for_each_pipe(i) {
10138                 intel_crtc_init(dev, i);
10139                 for (j = 0; j < dev_priv->num_plane; j++) {
10140                         ret = intel_plane_init(dev, i, j);
10141                         if (ret)
10142                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10143                                               pipe_name(i), sprite_name(i, j), ret);
10144                 }
10145         }
10146
10147         intel_cpu_pll_init(dev);
10148         intel_shared_dpll_init(dev);
10149
10150         /* Just disable it once at startup */
10151         i915_disable_vga(dev);
10152         intel_setup_outputs(dev);
10153
10154         /* Just in case the BIOS is doing something questionable. */
10155         intel_disable_fbc(dev);
10156 }
10157
10158 static void
10159 intel_connector_break_all_links(struct intel_connector *connector)
10160 {
10161         connector->base.dpms = DRM_MODE_DPMS_OFF;
10162         connector->base.encoder = NULL;
10163         connector->encoder->connectors_active = false;
10164         connector->encoder->base.crtc = NULL;
10165 }
10166
10167 static void intel_enable_pipe_a(struct drm_device *dev)
10168 {
10169         struct intel_connector *connector;
10170         struct drm_connector *crt = NULL;
10171         struct intel_load_detect_pipe load_detect_temp;
10172
10173         /* We can't just switch on the pipe A, we need to set things up with a
10174          * proper mode and output configuration. As a gross hack, enable pipe A
10175          * by enabling the load detect pipe once. */
10176         list_for_each_entry(connector,
10177                             &dev->mode_config.connector_list,
10178                             base.head) {
10179                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10180                         crt = &connector->base;
10181                         break;
10182                 }
10183         }
10184
10185         if (!crt)
10186                 return;
10187
10188         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10189                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10190
10191
10192 }
10193
10194 static bool
10195 intel_check_plane_mapping(struct intel_crtc *crtc)
10196 {
10197         struct drm_device *dev = crtc->base.dev;
10198         struct drm_i915_private *dev_priv = dev->dev_private;
10199         u32 reg, val;
10200
10201         if (INTEL_INFO(dev)->num_pipes == 1)
10202                 return true;
10203
10204         reg = DSPCNTR(!crtc->plane);
10205         val = I915_READ(reg);
10206
10207         if ((val & DISPLAY_PLANE_ENABLE) &&
10208             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10209                 return false;
10210
10211         return true;
10212 }
10213
10214 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10215 {
10216         struct drm_device *dev = crtc->base.dev;
10217         struct drm_i915_private *dev_priv = dev->dev_private;
10218         u32 reg;
10219
10220         /* Clear any frame start delays used for debugging left by the BIOS */
10221         reg = PIPECONF(crtc->config.cpu_transcoder);
10222         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10223
10224         /* We need to sanitize the plane -> pipe mapping first because this will
10225          * disable the crtc (and hence change the state) if it is wrong. Note
10226          * that gen4+ has a fixed plane -> pipe mapping.  */
10227         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10228                 struct intel_connector *connector;
10229                 bool plane;
10230
10231                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10232                               crtc->base.base.id);
10233
10234                 /* Pipe has the wrong plane attached and the plane is active.
10235                  * Temporarily change the plane mapping and disable everything
10236                  * ...  */
10237                 plane = crtc->plane;
10238                 crtc->plane = !plane;
10239                 dev_priv->display.crtc_disable(&crtc->base);
10240                 crtc->plane = plane;
10241
10242                 /* ... and break all links. */
10243                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10244                                     base.head) {
10245                         if (connector->encoder->base.crtc != &crtc->base)
10246                                 continue;
10247
10248                         intel_connector_break_all_links(connector);
10249                 }
10250
10251                 WARN_ON(crtc->active);
10252                 crtc->base.enabled = false;
10253         }
10254
10255         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10256             crtc->pipe == PIPE_A && !crtc->active) {
10257                 /* BIOS forgot to enable pipe A, this mostly happens after
10258                  * resume. Force-enable the pipe to fix this, the update_dpms
10259                  * call below we restore the pipe to the right state, but leave
10260                  * the required bits on. */
10261                 intel_enable_pipe_a(dev);
10262         }
10263
10264         /* Adjust the state of the output pipe according to whether we
10265          * have active connectors/encoders. */
10266         intel_crtc_update_dpms(&crtc->base);
10267
10268         if (crtc->active != crtc->base.enabled) {
10269                 struct intel_encoder *encoder;
10270
10271                 /* This can happen either due to bugs in the get_hw_state
10272                  * functions or because the pipe is force-enabled due to the
10273                  * pipe A quirk. */
10274                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10275                               crtc->base.base.id,
10276                               crtc->base.enabled ? "enabled" : "disabled",
10277                               crtc->active ? "enabled" : "disabled");
10278
10279                 crtc->base.enabled = crtc->active;
10280
10281                 /* Because we only establish the connector -> encoder ->
10282                  * crtc links if something is active, this means the
10283                  * crtc is now deactivated. Break the links. connector
10284                  * -> encoder links are only establish when things are
10285                  *  actually up, hence no need to break them. */
10286                 WARN_ON(crtc->active);
10287
10288                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10289                         WARN_ON(encoder->connectors_active);
10290                         encoder->base.crtc = NULL;
10291                 }
10292         }
10293 }
10294
10295 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10296 {
10297         struct intel_connector *connector;
10298         struct drm_device *dev = encoder->base.dev;
10299
10300         /* We need to check both for a crtc link (meaning that the
10301          * encoder is active and trying to read from a pipe) and the
10302          * pipe itself being active. */
10303         bool has_active_crtc = encoder->base.crtc &&
10304                 to_intel_crtc(encoder->base.crtc)->active;
10305
10306         if (encoder->connectors_active && !has_active_crtc) {
10307                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10308                               encoder->base.base.id,
10309                               drm_get_encoder_name(&encoder->base));
10310
10311                 /* Connector is active, but has no active pipe. This is
10312                  * fallout from our resume register restoring. Disable
10313                  * the encoder manually again. */
10314                 if (encoder->base.crtc) {
10315                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10316                                       encoder->base.base.id,
10317                                       drm_get_encoder_name(&encoder->base));
10318                         encoder->disable(encoder);
10319                 }
10320
10321                 /* Inconsistent output/port/pipe state happens presumably due to
10322                  * a bug in one of the get_hw_state functions. Or someplace else
10323                  * in our code, like the register restore mess on resume. Clamp
10324                  * things to off as a safer default. */
10325                 list_for_each_entry(connector,
10326                                     &dev->mode_config.connector_list,
10327                                     base.head) {
10328                         if (connector->encoder != encoder)
10329                                 continue;
10330
10331                         intel_connector_break_all_links(connector);
10332                 }
10333         }
10334         /* Enabled encoders without active connectors will be fixed in
10335          * the crtc fixup. */
10336 }
10337
10338 void i915_redisable_vga(struct drm_device *dev)
10339 {
10340         struct drm_i915_private *dev_priv = dev->dev_private;
10341         u32 vga_reg = i915_vgacntrl_reg(dev);
10342
10343         /* This function can be called both from intel_modeset_setup_hw_state or
10344          * at a very early point in our resume sequence, where the power well
10345          * structures are not yet restored. Since this function is at a very
10346          * paranoid "someone might have enabled VGA while we were not looking"
10347          * level, just check if the power well is enabled instead of trying to
10348          * follow the "don't touch the power well if we don't need it" policy
10349          * the rest of the driver uses. */
10350         if (HAS_POWER_WELL(dev) &&
10351             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10352                 return;
10353
10354         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10355                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10356                 i915_disable_vga(dev);
10357                 i915_disable_vga_mem(dev);
10358         }
10359 }
10360
10361 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10362 {
10363         struct drm_i915_private *dev_priv = dev->dev_private;
10364         enum pipe pipe;
10365         struct intel_crtc *crtc;
10366         struct intel_encoder *encoder;
10367         struct intel_connector *connector;
10368         int i;
10369
10370         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10371                             base.head) {
10372                 memset(&crtc->config, 0, sizeof(crtc->config));
10373
10374                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10375                                                                  &crtc->config);
10376
10377                 crtc->base.enabled = crtc->active;
10378
10379                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10380                               crtc->base.base.id,
10381                               crtc->active ? "enabled" : "disabled");
10382         }
10383
10384         /* FIXME: Smash this into the new shared dpll infrastructure. */
10385         if (HAS_DDI(dev))
10386                 intel_ddi_setup_hw_pll_state(dev);
10387
10388         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10389                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10390
10391                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10392                 pll->active = 0;
10393                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10394                                     base.head) {
10395                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10396                                 pll->active++;
10397                 }
10398                 pll->refcount = pll->active;
10399
10400                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10401                               pll->name, pll->refcount, pll->on);
10402         }
10403
10404         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10405                             base.head) {
10406                 pipe = 0;
10407
10408                 if (encoder->get_hw_state(encoder, &pipe)) {
10409                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10410                         encoder->base.crtc = &crtc->base;
10411                         if (encoder->get_config)
10412                                 encoder->get_config(encoder, &crtc->config);
10413                 } else {
10414                         encoder->base.crtc = NULL;
10415                 }
10416
10417                 encoder->connectors_active = false;
10418                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10419                               encoder->base.base.id,
10420                               drm_get_encoder_name(&encoder->base),
10421                               encoder->base.crtc ? "enabled" : "disabled",
10422                               pipe);
10423         }
10424
10425         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10426                             base.head) {
10427                 if (!crtc->active)
10428                         continue;
10429                 if (dev_priv->display.get_clock)
10430                         dev_priv->display.get_clock(crtc,
10431                                                     &crtc->config);
10432         }
10433
10434         list_for_each_entry(connector, &dev->mode_config.connector_list,
10435                             base.head) {
10436                 if (connector->get_hw_state(connector)) {
10437                         connector->base.dpms = DRM_MODE_DPMS_ON;
10438                         connector->encoder->connectors_active = true;
10439                         connector->base.encoder = &connector->encoder->base;
10440                 } else {
10441                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10442                         connector->base.encoder = NULL;
10443                 }
10444                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10445                               connector->base.base.id,
10446                               drm_get_connector_name(&connector->base),
10447                               connector->base.encoder ? "enabled" : "disabled");
10448         }
10449 }
10450
10451 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10452  * and i915 state tracking structures. */
10453 void intel_modeset_setup_hw_state(struct drm_device *dev,
10454                                   bool force_restore)
10455 {
10456         struct drm_i915_private *dev_priv = dev->dev_private;
10457         enum pipe pipe;
10458         struct drm_plane *plane;
10459         struct intel_crtc *crtc;
10460         struct intel_encoder *encoder;
10461         int i;
10462
10463         intel_modeset_readout_hw_state(dev);
10464
10465         /*
10466          * Now that we have the config, copy it to each CRTC struct
10467          * Note that this could go away if we move to using crtc_config
10468          * checking everywhere.
10469          */
10470         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10471                             base.head) {
10472                 if (crtc->active && i915_fastboot) {
10473                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10474
10475                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10476                                       crtc->base.base.id);
10477                         drm_mode_debug_printmodeline(&crtc->base.mode);
10478                 }
10479         }
10480
10481         /* HW state is read out, now we need to sanitize this mess. */
10482         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10483                             base.head) {
10484                 intel_sanitize_encoder(encoder);
10485         }
10486
10487         for_each_pipe(pipe) {
10488                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10489                 intel_sanitize_crtc(crtc);
10490                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10491         }
10492
10493         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10494                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10495
10496                 if (!pll->on || pll->active)
10497                         continue;
10498
10499                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10500
10501                 pll->disable(dev_priv, pll);
10502                 pll->on = false;
10503         }
10504
10505         if (force_restore) {
10506                 /*
10507                  * We need to use raw interfaces for restoring state to avoid
10508                  * checking (bogus) intermediate states.
10509                  */
10510                 for_each_pipe(pipe) {
10511                         struct drm_crtc *crtc =
10512                                 dev_priv->pipe_to_crtc_mapping[pipe];
10513
10514                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10515                                          crtc->fb);
10516                 }
10517                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10518                         intel_plane_restore(plane);
10519
10520                 i915_redisable_vga(dev);
10521         } else {
10522                 intel_modeset_update_staged_output_state(dev);
10523         }
10524
10525         intel_modeset_check_state(dev);
10526
10527         drm_mode_config_reset(dev);
10528 }
10529
10530 void intel_modeset_gem_init(struct drm_device *dev)
10531 {
10532         intel_modeset_init_hw(dev);
10533
10534         intel_setup_overlay(dev);
10535
10536         intel_modeset_setup_hw_state(dev, false);
10537 }
10538
10539 void intel_modeset_cleanup(struct drm_device *dev)
10540 {
10541         struct drm_i915_private *dev_priv = dev->dev_private;
10542         struct drm_crtc *crtc;
10543
10544         /*
10545          * Interrupts and polling as the first thing to avoid creating havoc.
10546          * Too much stuff here (turning of rps, connectors, ...) would
10547          * experience fancy races otherwise.
10548          */
10549         drm_irq_uninstall(dev);
10550         cancel_work_sync(&dev_priv->hotplug_work);
10551         /*
10552          * Due to the hpd irq storm handling the hotplug work can re-arm the
10553          * poll handlers. Hence disable polling after hpd handling is shut down.
10554          */
10555         drm_kms_helper_poll_fini(dev);
10556
10557         mutex_lock(&dev->struct_mutex);
10558
10559         intel_unregister_dsm_handler();
10560
10561         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10562                 /* Skip inactive CRTCs */
10563                 if (!crtc->fb)
10564                         continue;
10565
10566                 intel_increase_pllclock(crtc);
10567         }
10568
10569         intel_disable_fbc(dev);
10570
10571         i915_enable_vga_mem(dev);
10572
10573         intel_disable_gt_powersave(dev);
10574
10575         ironlake_teardown_rc6(dev);
10576
10577         mutex_unlock(&dev->struct_mutex);
10578
10579         /* flush any delayed tasks or pending work */
10580         flush_scheduled_work();
10581
10582         /* destroy backlight, if any, before the connectors */
10583         intel_panel_destroy_backlight(dev);
10584
10585         drm_mode_config_cleanup(dev);
10586
10587         intel_cleanup_overlay(dev);
10588 }
10589
10590 /*
10591  * Return which encoder is currently attached for connector.
10592  */
10593 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10594 {
10595         return &intel_attached_encoder(connector)->base;
10596 }
10597
10598 void intel_connector_attach_encoder(struct intel_connector *connector,
10599                                     struct intel_encoder *encoder)
10600 {
10601         connector->encoder = encoder;
10602         drm_mode_connector_attach_encoder(&connector->base,
10603                                           &encoder->base);
10604 }
10605
10606 /*
10607  * set vga decode state - true == enable VGA decode
10608  */
10609 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10610 {
10611         struct drm_i915_private *dev_priv = dev->dev_private;
10612         u16 gmch_ctrl;
10613
10614         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10615         if (state)
10616                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10617         else
10618                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10619         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10620         return 0;
10621 }
10622
10623 struct intel_display_error_state {
10624
10625         u32 power_well_driver;
10626
10627         int num_transcoders;
10628
10629         struct intel_cursor_error_state {
10630                 u32 control;
10631                 u32 position;
10632                 u32 base;
10633                 u32 size;
10634         } cursor[I915_MAX_PIPES];
10635
10636         struct intel_pipe_error_state {
10637                 u32 source;
10638         } pipe[I915_MAX_PIPES];
10639
10640         struct intel_plane_error_state {
10641                 u32 control;
10642                 u32 stride;
10643                 u32 size;
10644                 u32 pos;
10645                 u32 addr;
10646                 u32 surface;
10647                 u32 tile_offset;
10648         } plane[I915_MAX_PIPES];
10649
10650         struct intel_transcoder_error_state {
10651                 enum transcoder cpu_transcoder;
10652
10653                 u32 conf;
10654
10655                 u32 htotal;
10656                 u32 hblank;
10657                 u32 hsync;
10658                 u32 vtotal;
10659                 u32 vblank;
10660                 u32 vsync;
10661         } transcoder[4];
10662 };
10663
10664 struct intel_display_error_state *
10665 intel_display_capture_error_state(struct drm_device *dev)
10666 {
10667         drm_i915_private_t *dev_priv = dev->dev_private;
10668         struct intel_display_error_state *error;
10669         int transcoders[] = {
10670                 TRANSCODER_A,
10671                 TRANSCODER_B,
10672                 TRANSCODER_C,
10673                 TRANSCODER_EDP,
10674         };
10675         int i;
10676
10677         if (INTEL_INFO(dev)->num_pipes == 0)
10678                 return NULL;
10679
10680         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10681         if (error == NULL)
10682                 return NULL;
10683
10684         if (HAS_POWER_WELL(dev))
10685                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10686
10687         for_each_pipe(i) {
10688                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10689                         error->cursor[i].control = I915_READ(CURCNTR(i));
10690                         error->cursor[i].position = I915_READ(CURPOS(i));
10691                         error->cursor[i].base = I915_READ(CURBASE(i));
10692                 } else {
10693                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10694                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10695                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10696                 }
10697
10698                 error->plane[i].control = I915_READ(DSPCNTR(i));
10699                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10700                 if (INTEL_INFO(dev)->gen <= 3) {
10701                         error->plane[i].size = I915_READ(DSPSIZE(i));
10702                         error->plane[i].pos = I915_READ(DSPPOS(i));
10703                 }
10704                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10705                         error->plane[i].addr = I915_READ(DSPADDR(i));
10706                 if (INTEL_INFO(dev)->gen >= 4) {
10707                         error->plane[i].surface = I915_READ(DSPSURF(i));
10708                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10709                 }
10710
10711                 error->pipe[i].source = I915_READ(PIPESRC(i));
10712         }
10713
10714         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10715         if (HAS_DDI(dev_priv->dev))
10716                 error->num_transcoders++; /* Account for eDP. */
10717
10718         for (i = 0; i < error->num_transcoders; i++) {
10719                 enum transcoder cpu_transcoder = transcoders[i];
10720
10721                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10722
10723                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10724                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10725                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10726                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10727                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10728                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10729                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10730         }
10731
10732         /* In the code above we read the registers without checking if the power
10733          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10734          * prevent the next I915_WRITE from detecting it and printing an error
10735          * message. */
10736         intel_uncore_clear_errors(dev);
10737
10738         return error;
10739 }
10740
10741 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10742
10743 void
10744 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10745                                 struct drm_device *dev,
10746                                 struct intel_display_error_state *error)
10747 {
10748         int i;
10749
10750         if (!error)
10751                 return;
10752
10753         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10754         if (HAS_POWER_WELL(dev))
10755                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10756                            error->power_well_driver);
10757         for_each_pipe(i) {
10758                 err_printf(m, "Pipe [%d]:\n", i);
10759                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10760
10761                 err_printf(m, "Plane [%d]:\n", i);
10762                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10763                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10764                 if (INTEL_INFO(dev)->gen <= 3) {
10765                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10766                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10767                 }
10768                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10769                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10770                 if (INTEL_INFO(dev)->gen >= 4) {
10771                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10772                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10773                 }
10774
10775                 err_printf(m, "Cursor [%d]:\n", i);
10776                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10777                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10778                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10779         }
10780
10781         for (i = 0; i < error->num_transcoders; i++) {
10782                 err_printf(m, "  CPU transcoder: %c\n",
10783                            transcoder_name(error->transcoder[i].cpu_transcoder));
10784                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
10785                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
10786                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
10787                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
10788                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
10789                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
10790                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
10791         }
10792 }