drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "intel_dsi.h"
  40 #include "i915_trace.h"
  41 #include <drm/drm_atomic.h>
  42 #include <drm/drm_atomic_helper.h>
  43 #include <drm/drm_dp_helper.h>
  44 #include <drm/drm_crtc_helper.h>
  45 #include <drm/drm_plane_helper.h>
  46 #include <drm/drm_rect.h>
  47 #include <linux/dma_remapping.h>
  48 #include <linux/reservation.h>
  49 #include <linux/dma-buf.h>
  50
  51 /* Primary plane formats for gen <= 3 */
  52 static const uint32_t i8xx_primary_formats[] = {
  53         DRM_FORMAT_C8,
  54         DRM_FORMAT_RGB565,
  55         DRM_FORMAT_XRGB1555,
  56         DRM_FORMAT_XRGB8888,
  57 };
  58
  59 /* Primary plane formats for gen >= 4 */
  60 static const uint32_t i965_primary_formats[] = {
  61         DRM_FORMAT_C8,
  62         DRM_FORMAT_RGB565,
  63         DRM_FORMAT_XRGB8888,
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_XBGR2101010,
  67 };
  68
  69 static const uint32_t skl_primary_formats[] = {
  70         DRM_FORMAT_C8,
  71         DRM_FORMAT_RGB565,
  72         DRM_FORMAT_XRGB8888,
  73         DRM_FORMAT_XBGR8888,
  74         DRM_FORMAT_ARGB8888,
  75         DRM_FORMAT_ABGR8888,
  76         DRM_FORMAT_XRGB2101010,
  77         DRM_FORMAT_XBGR2101010,
  78         DRM_FORMAT_YUYV,
  79         DRM_FORMAT_YVYU,
  80         DRM_FORMAT_UYVY,
  81         DRM_FORMAT_VYUY,
  82 };
  83
  84 /* Cursor formats */
  85 static const uint32_t intel_cursor_formats[] = {
  86         DRM_FORMAT_ARGB8888,
  87 };
  88
  89 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  90                                 struct intel_crtc_state *pipe_config);
  91 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  92                                    struct intel_crtc_state *pipe_config);
  93
  94 static int intel_framebuffer_init(struct drm_device *dev,
  95                                   struct intel_framebuffer *ifb,
  96                                   struct drm_mode_fb_cmd2 *mode_cmd,
  97                                   struct drm_i915_gem_object *obj);
  98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 102                                          struct intel_link_m_n *m_n,
 103                                          struct intel_link_m_n *m2_n2);
 104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 107 static void vlv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void chv_prepare_pll(struct intel_crtc *crtc,
 110                             const struct intel_crtc_state *pipe_config);
 111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 114         struct intel_crtc_state *crtc_state);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 120 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 121
 122 struct intel_limit {
 123         struct {
 124                 int min, max;
 125         } dot, vco, n, m, m1, m2, p, p1;
 126
 127         struct {
 128                 int dot_limit;
 129                 int p2_slow, p2_fast;
 130         } p2;
 131 };
 132
 133 /* returns HPLL frequency in kHz */
 134 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 135 {
 136         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 137
 138         /* Obtain SKU information */
 139         mutex_lock(&dev_priv->sb_lock);
 140         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 141                 CCK_FUSE_HPLL_FREQ_MASK;
 142         mutex_unlock(&dev_priv->sb_lock);
 143
 144         return vco_freq[hpll_freq] * 1000;
 145 }
 146
 147 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 148                       const char *name, u32 reg, int ref_freq)
 149 {
 150         u32 val;
 151         int divider;
 152
 153         mutex_lock(&dev_priv->sb_lock);
 154         val = vlv_cck_read(dev_priv, reg);
 155         mutex_unlock(&dev_priv->sb_lock);
 156
 157         divider = val & CCK_FREQUENCY_VALUES;
 158
 159         WARN((val & CCK_FREQUENCY_STATUS) !=
 160              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 161              "%s change in progress\n", name);
 162
 163         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 164 }
 165
 166 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 167                                   const char *name, u32 reg)
 168 {
 169         if (dev_priv->hpll_freq == 0)
 170                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 171
 172         return vlv_get_cck_clock(dev_priv, name, reg,
 173                                  dev_priv->hpll_freq);
 174 }
 175
 176 static int
 177 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 178 {
 179         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 180 }
 181
 182 static int
 183 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 184 {
 185         /* RAWCLK_FREQ_VLV register updated from power well code */
 186         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 187                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 188 }
 189
 190 static int
 191 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 192 {
 193         uint32_t clkcfg;
 194
 195         /* hrawclock is 1/4 the FSB frequency */
 196         clkcfg = I915_READ(CLKCFG);
 197         switch (clkcfg & CLKCFG_FSB_MASK) {
 198         case CLKCFG_FSB_400:
 199                 return 100000;
 200         case CLKCFG_FSB_533:
 201                 return 133333;
 202         case CLKCFG_FSB_667:
 203                 return 166667;
 204         case CLKCFG_FSB_800:
 205                 return 200000;
 206         case CLKCFG_FSB_1067:
 207                 return 266667;
 208         case CLKCFG_FSB_1333:
 209                 return 333333;
 210         /* these two are just a guess; one of them might be right */
 211         case CLKCFG_FSB_1600:
 212         case CLKCFG_FSB_1600_ALT:
 213                 return 400000;
 214         default:
 215                 return 133333;
 216         }
 217 }
 218
 219 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 220 {
 221         if (HAS_PCH_SPLIT(dev_priv))
 222                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 223         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 224                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 225         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 226                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 227         else
 228                 return; /* no rawclk on other platforms, or no need to know it */
 229
 230         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 231 }
 232
 233 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 234 {
 235         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 236                 return;
 237
 238         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 239                                                       CCK_CZ_CLOCK_CONTROL);
 240
 241         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 242 }
 243
 244 static inline u32 /* units of 100MHz */
 245 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 246                     const struct intel_crtc_state *pipe_config)
 247 {
 248         if (HAS_DDI(dev_priv))
 249                 return pipe_config->port_clock; /* SPLL */
 250         else if (IS_GEN5(dev_priv))
 251                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 252         else
 253                 return 270000;
 254 }
 255
 256 static const struct intel_limit intel_limits_i8xx_dac = {
 257         .dot = { .min = 25000, .max = 350000 },
 258         .vco = { .min = 908000, .max = 1512000 },
 259         .n = { .min = 2, .max = 16 },
 260         .m = { .min = 96, .max = 140 },
 261         .m1 = { .min = 18, .max = 26 },
 262         .m2 = { .min = 6, .max = 16 },
 263         .p = { .min = 4, .max = 128 },
 264         .p1 = { .min = 2, .max = 33 },
 265         .p2 = { .dot_limit = 165000,
 266                 .p2_slow = 4, .p2_fast = 2 },
 267 };
 268
 269 static const struct intel_limit intel_limits_i8xx_dvo = {
 270         .dot = { .min = 25000, .max = 350000 },
 271         .vco = { .min = 908000, .max = 1512000 },
 272         .n = { .min = 2, .max = 16 },
 273         .m = { .min = 96, .max = 140 },
 274         .m1 = { .min = 18, .max = 26 },
 275         .m2 = { .min = 6, .max = 16 },
 276         .p = { .min = 4, .max = 128 },
 277         .p1 = { .min = 2, .max = 33 },
 278         .p2 = { .dot_limit = 165000,
 279                 .p2_slow = 4, .p2_fast = 4 },
 280 };
 281
 282 static const struct intel_limit intel_limits_i8xx_lvds = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 908000, .max = 1512000 },
 285         .n = { .min = 2, .max = 16 },
 286         .m = { .min = 96, .max = 140 },
 287         .m1 = { .min = 18, .max = 26 },
 288         .m2 = { .min = 6, .max = 16 },
 289         .p = { .min = 4, .max = 128 },
 290         .p1 = { .min = 1, .max = 6 },
 291         .p2 = { .dot_limit = 165000,
 292                 .p2_slow = 14, .p2_fast = 7 },
 293 };
 294
 295 static const struct intel_limit intel_limits_i9xx_sdvo = {
 296         .dot = { .min = 20000, .max = 400000 },
 297         .vco = { .min = 1400000, .max = 2800000 },
 298         .n = { .min = 1, .max = 6 },
 299         .m = { .min = 70, .max = 120 },
 300         .m1 = { .min = 8, .max = 18 },
 301         .m2 = { .min = 3, .max = 7 },
 302         .p = { .min = 5, .max = 80 },
 303         .p1 = { .min = 1, .max = 8 },
 304         .p2 = { .dot_limit = 200000,
 305                 .p2_slow = 10, .p2_fast = 5 },
 306 };
 307
 308 static const struct intel_limit intel_limits_i9xx_lvds = {
 309         .dot = { .min = 20000, .max = 400000 },
 310         .vco = { .min = 1400000, .max = 2800000 },
 311         .n = { .min = 1, .max = 6 },
 312         .m = { .min = 70, .max = 120 },
 313         .m1 = { .min = 8, .max = 18 },
 314         .m2 = { .min = 3, .max = 7 },
 315         .p = { .min = 7, .max = 98 },
 316         .p1 = { .min = 1, .max = 8 },
 317         .p2 = { .dot_limit = 112000,
 318                 .p2_slow = 14, .p2_fast = 7 },
 319 };
 320
 321
 322 static const struct intel_limit intel_limits_g4x_sdvo = {
 323         .dot = { .min = 25000, .max = 270000 },
 324         .vco = { .min = 1750000, .max = 3500000},
 325         .n = { .min = 1, .max = 4 },
 326         .m = { .min = 104, .max = 138 },
 327         .m1 = { .min = 17, .max = 23 },
 328         .m2 = { .min = 5, .max = 11 },
 329         .p = { .min = 10, .max = 30 },
 330         .p1 = { .min = 1, .max = 3},
 331         .p2 = { .dot_limit = 270000,
 332                 .p2_slow = 10,
 333                 .p2_fast = 10
 334         },
 335 };
 336
 337 static const struct intel_limit intel_limits_g4x_hdmi = {
 338         .dot = { .min = 22000, .max = 400000 },
 339         .vco = { .min = 1750000, .max = 3500000},
 340         .n = { .min = 1, .max = 4 },
 341         .m = { .min = 104, .max = 138 },
 342         .m1 = { .min = 16, .max = 23 },
 343         .m2 = { .min = 5, .max = 11 },
 344         .p = { .min = 5, .max = 80 },
 345         .p1 = { .min = 1, .max = 8},
 346         .p2 = { .dot_limit = 165000,
 347                 .p2_slow = 10, .p2_fast = 5 },
 348 };
 349
 350 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 351         .dot = { .min = 20000, .max = 115000 },
 352         .vco = { .min = 1750000, .max = 3500000 },
 353         .n = { .min = 1, .max = 3 },
 354         .m = { .min = 104, .max = 138 },
 355         .m1 = { .min = 17, .max = 23 },
 356         .m2 = { .min = 5, .max = 11 },
 357         .p = { .min = 28, .max = 112 },
 358         .p1 = { .min = 2, .max = 8 },
 359         .p2 = { .dot_limit = 0,
 360                 .p2_slow = 14, .p2_fast = 14
 361         },
 362 };
 363
 364 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 365         .dot = { .min = 80000, .max = 224000 },
 366         .vco = { .min = 1750000, .max = 3500000 },
 367         .n = { .min = 1, .max = 3 },
 368         .m = { .min = 104, .max = 138 },
 369         .m1 = { .min = 17, .max = 23 },
 370         .m2 = { .min = 5, .max = 11 },
 371         .p = { .min = 14, .max = 42 },
 372         .p1 = { .min = 2, .max = 6 },
 373         .p2 = { .dot_limit = 0,
 374                 .p2_slow = 7, .p2_fast = 7
 375         },
 376 };
 377
 378 static const struct intel_limit intel_limits_pineview_sdvo = {
 379         .dot = { .min = 20000, .max = 400000},
 380         .vco = { .min = 1700000, .max = 3500000 },
 381         /* Pineview's Ncounter is a ring counter */
 382         .n = { .min = 3, .max = 6 },
 383         .m = { .min = 2, .max = 256 },
 384         /* Pineview only has one combined m divider, which we treat as m2. */
 385         .m1 = { .min = 0, .max = 0 },
 386         .m2 = { .min = 0, .max = 254 },
 387         .p = { .min = 5, .max = 80 },
 388         .p1 = { .min = 1, .max = 8 },
 389         .p2 = { .dot_limit = 200000,
 390                 .p2_slow = 10, .p2_fast = 5 },
 391 };
 392
 393 static const struct intel_limit intel_limits_pineview_lvds = {
 394         .dot = { .min = 20000, .max = 400000 },
 395         .vco = { .min = 1700000, .max = 3500000 },
 396         .n = { .min = 3, .max = 6 },
 397         .m = { .min = 2, .max = 256 },
 398         .m1 = { .min = 0, .max = 0 },
 399         .m2 = { .min = 0, .max = 254 },
 400         .p = { .min = 7, .max = 112 },
 401         .p1 = { .min = 1, .max = 8 },
 402         .p2 = { .dot_limit = 112000,
 403                 .p2_slow = 14, .p2_fast = 14 },
 404 };
 405
 406 /* Ironlake / Sandybridge
 407  *
 408  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 409  * the range value for them is (actual_value - 2).
 410  */
 411 static const struct intel_limit intel_limits_ironlake_dac = {
 412         .dot = { .min = 25000, .max = 350000 },
 413         .vco = { .min = 1760000, .max = 3510000 },
 414         .n = { .min = 1, .max = 5 },
 415         .m = { .min = 79, .max = 127 },
 416         .m1 = { .min = 12, .max = 22 },
 417         .m2 = { .min = 5, .max = 9 },
 418         .p = { .min = 5, .max = 80 },
 419         .p1 = { .min = 1, .max = 8 },
 420         .p2 = { .dot_limit = 225000,
 421                 .p2_slow = 10, .p2_fast = 5 },
 422 };
 423
 424 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 425         .dot = { .min = 25000, .max = 350000 },
 426         .vco = { .min = 1760000, .max = 3510000 },
 427         .n = { .min = 1, .max = 3 },
 428         .m = { .min = 79, .max = 118 },
 429         .m1 = { .min = 12, .max = 22 },
 430         .m2 = { .min = 5, .max = 9 },
 431         .p = { .min = 28, .max = 112 },
 432         .p1 = { .min = 2, .max = 8 },
 433         .p2 = { .dot_limit = 225000,
 434                 .p2_slow = 14, .p2_fast = 14 },
 435 };
 436
 437 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 438         .dot = { .min = 25000, .max = 350000 },
 439         .vco = { .min = 1760000, .max = 3510000 },
 440         .n = { .min = 1, .max = 3 },
 441         .m = { .min = 79, .max = 127 },
 442         .m1 = { .min = 12, .max = 22 },
 443         .m2 = { .min = 5, .max = 9 },
 444         .p = { .min = 14, .max = 56 },
 445         .p1 = { .min = 2, .max = 8 },
 446         .p2 = { .dot_limit = 225000,
 447                 .p2_slow = 7, .p2_fast = 7 },
 448 };
 449
 450 /* LVDS 100mhz refclk limits. */
 451 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 452         .dot = { .min = 25000, .max = 350000 },
 453         .vco = { .min = 1760000, .max = 3510000 },
 454         .n = { .min = 1, .max = 2 },
 455         .m = { .min = 79, .max = 126 },
 456         .m1 = { .min = 12, .max = 22 },
 457         .m2 = { .min = 5, .max = 9 },
 458         .p = { .min = 28, .max = 112 },
 459         .p1 = { .min = 2, .max = 8 },
 460         .p2 = { .dot_limit = 225000,
 461                 .p2_slow = 14, .p2_fast = 14 },
 462 };
 463
 464 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 465         .dot = { .min = 25000, .max = 350000 },
 466         .vco = { .min = 1760000, .max = 3510000 },
 467         .n = { .min = 1, .max = 3 },
 468         .m = { .min = 79, .max = 126 },
 469         .m1 = { .min = 12, .max = 22 },
 470         .m2 = { .min = 5, .max = 9 },
 471         .p = { .min = 14, .max = 42 },
 472         .p1 = { .min = 2, .max = 6 },
 473         .p2 = { .dot_limit = 225000,
 474                 .p2_slow = 7, .p2_fast = 7 },
 475 };
 476
 477 static const struct intel_limit intel_limits_vlv = {
 478          /*
 479           * These are the data rate limits (measured in fast clocks)
 480           * since those are the strictest limits we have. The fast
 481           * clock and actual rate limits are more relaxed, so checking
 482           * them would make no difference.
 483           */
 484         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 485         .vco = { .min = 4000000, .max = 6000000 },
 486         .n = { .min = 1, .max = 7 },
 487         .m1 = { .min = 2, .max = 3 },
 488         .m2 = { .min = 11, .max = 156 },
 489         .p1 = { .min = 2, .max = 3 },
 490         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 491 };
 492
 493 static const struct intel_limit intel_limits_chv = {
 494         /*
 495          * These are the data rate limits (measured in fast clocks)
 496          * since those are the strictest limits we have.  The fast
 497          * clock and actual rate limits are more relaxed, so checking
 498          * them would make no difference.
 499          */
 500         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 501         .vco = { .min = 4800000, .max = 6480000 },
 502         .n = { .min = 1, .max = 1 },
 503         .m1 = { .min = 2, .max = 2 },
 504         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 505         .p1 = { .min = 2, .max = 4 },
 506         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 507 };
 508
 509 static const struct intel_limit intel_limits_bxt = {
 510         /* FIXME: find real dot limits */
 511         .dot = { .min = 0, .max = INT_MAX },
 512         .vco = { .min = 4800000, .max = 6700000 },
 513         .n = { .min = 1, .max = 1 },
 514         .m1 = { .min = 2, .max = 2 },
 515         /* FIXME: find real m2 limits */
 516         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 517         .p1 = { .min = 2, .max = 4 },
 518         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 519 };
 520
 521 static bool
 522 needs_modeset(struct drm_crtc_state *state)
 523 {
 524         return drm_atomic_crtc_needs_modeset(state);
 525 }
 526
 527 /**
 528  * Returns whether any output on the specified pipe is of the specified type
 529  */
 530 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 531 {
 532         struct drm_device *dev = crtc->base.dev;
 533         struct intel_encoder *encoder;
 534
 535         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 536                 if (encoder->type == type)
 537                         return true;
 538
 539         return false;
 540 }
 541
 542 /**
 543  * Returns whether any output on the specified pipe will have the specified
 544  * type after a staged modeset is complete, i.e., the same as
 545  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 546  * encoder->crtc.
 547  */
 548 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 549                                       int type)
 550 {
 551         struct drm_atomic_state *state = crtc_state->base.state;
 552         struct drm_connector *connector;
 553         struct drm_connector_state *connector_state;
 554         struct intel_encoder *encoder;
 555         int i, num_connectors = 0;
 556
 557         for_each_connector_in_state(state, connector, connector_state, i) {
 558                 if (connector_state->crtc != crtc_state->base.crtc)
 559                         continue;
 560
 561                 num_connectors++;
 562
 563                 encoder = to_intel_encoder(connector_state->best_encoder);
 564                 if (encoder->type == type)
 565                         return true;
 566         }
 567
 568         WARN_ON(num_connectors == 0);
 569
 570         return false;
 571 }
 572
 573 /*
 574  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 575  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 576  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 577  * The helpers' return value is the rate of the clock that is fed to the
 578  * display engine's pipe which can be the above fast dot clock rate or a
 579  * divided-down version of it.
 580  */
 581 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 582 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 583 {
 584         clock->m = clock->m2 + 2;
 585         clock->p = clock->p1 * clock->p2;
 586         if (WARN_ON(clock->n == 0 || clock->p == 0))
 587                 return 0;
 588         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 589         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 590
 591         return clock->dot;
 592 }
 593
 594 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 595 {
 596         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 597 }
 598
 599 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 600 {
 601         clock->m = i9xx_dpll_compute_m(clock);
 602         clock->p = clock->p1 * clock->p2;
 603         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 604                 return 0;
 605         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 606         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 607
 608         return clock->dot;
 609 }
 610
 611 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 612 {
 613         clock->m = clock->m1 * clock->m2;
 614         clock->p = clock->p1 * clock->p2;
 615         if (WARN_ON(clock->n == 0 || clock->p == 0))
 616                 return 0;
 617         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 618         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 619
 620         return clock->dot / 5;
 621 }
 622
 623 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 624 {
 625         clock->m = clock->m1 * clock->m2;
 626         clock->p = clock->p1 * clock->p2;
 627         if (WARN_ON(clock->n == 0 || clock->p == 0))
 628                 return 0;
 629         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 630                         clock->n << 22);
 631         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 632
 633         return clock->dot / 5;
 634 }
 635
 636 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 637 /**
 638  * Returns whether the given set of divisors are valid for a given refclk with
 639  * the given connectors.
 640  */
 641
 642 static bool intel_PLL_is_valid(struct drm_device *dev,
 643                                const struct intel_limit *limit,
 644                                const struct dpll *clock)
 645 {
 646         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 647                 INTELPllInvalid("n out of range\n");
 648         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 649                 INTELPllInvalid("p1 out of range\n");
 650         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 651                 INTELPllInvalid("m2 out of range\n");
 652         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 653                 INTELPllInvalid("m1 out of range\n");
 654
 655         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 656             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 657                 if (clock->m1 <= clock->m2)
 658                         INTELPllInvalid("m1 <= m2\n");
 659
 660         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 661                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 662                         INTELPllInvalid("p out of range\n");
 663                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 664                         INTELPllInvalid("m out of range\n");
 665         }
 666
 667         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 668                 INTELPllInvalid("vco out of range\n");
 669         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 670          * connector, etc., rather than just a single range.
 671          */
 672         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 673                 INTELPllInvalid("dot out of range\n");
 674
 675         return true;
 676 }
 677
 678 static int
 679 i9xx_select_p2_div(const struct intel_limit *limit,
 680                    const struct intel_crtc_state *crtc_state,
 681                    int target)
 682 {
 683         struct drm_device *dev = crtc_state->base.crtc->dev;
 684
 685         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 686                 /*
 687                  * For LVDS just rely on its current settings for dual-channel.
 688                  * We haven't figured out how to reliably set up different
 689                  * single/dual channel state, if we even can.
 690                  */
 691                 if (intel_is_dual_link_lvds(dev))
 692                         return limit->p2.p2_fast;
 693                 else
 694                         return limit->p2.p2_slow;
 695         } else {
 696                 if (target < limit->p2.dot_limit)
 697                         return limit->p2.p2_slow;
 698                 else
 699                         return limit->p2.p2_fast;
 700         }
 701 }
 702
 703 /*
 704  * Returns a set of divisors for the desired target clock with the given
 705  * refclk, or FALSE.  The returned values represent the clock equation:
 706  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 707  *
 708  * Target and reference clocks are specified in kHz.
 709  *
 710  * If match_clock is provided, then best_clock P divider must match the P
 711  * divider from @match_clock used for LVDS downclocking.
 712  */
 713 static bool
 714 i9xx_find_best_dpll(const struct intel_limit *limit,
 715                     struct intel_crtc_state *crtc_state,
 716                     int target, int refclk, struct dpll *match_clock,
 717                     struct dpll *best_clock)
 718 {
 719         struct drm_device *dev = crtc_state->base.crtc->dev;
 720         struct dpll clock;
 721         int err = target;
 722
 723         memset(best_clock, 0, sizeof(*best_clock));
 724
 725         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 726
 727         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 728              clock.m1++) {
 729                 for (clock.m2 = limit->m2.min;
 730                      clock.m2 <= limit->m2.max; clock.m2++) {
 731                         if (clock.m2 >= clock.m1)
 732                                 break;
 733                         for (clock.n = limit->n.min;
 734                              clock.n <= limit->n.max; clock.n++) {
 735                                 for (clock.p1 = limit->p1.min;
 736                                         clock.p1 <= limit->p1.max; clock.p1++) {
 737                                         int this_err;
 738
 739                                         i9xx_calc_dpll_params(refclk, &clock);
 740                                         if (!intel_PLL_is_valid(dev, limit,
 741                                                                 &clock))
 742                                                 continue;
 743                                         if (match_clock &&
 744                                             clock.p != match_clock->p)
 745                                                 continue;
 746
 747                                         this_err = abs(clock.dot - target);
 748                                         if (this_err < err) {
 749                                                 *best_clock = clock;
 750                                                 err = this_err;
 751                                         }
 752                                 }
 753                         }
 754                 }
 755         }
 756
 757         return (err != target);
 758 }
 759
 760 /*
 761  * Returns a set of divisors for the desired target clock with the given
 762  * refclk, or FALSE.  The returned values represent the clock equation:
 763  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 764  *
 765  * Target and reference clocks are specified in kHz.
 766  *
 767  * If match_clock is provided, then best_clock P divider must match the P
 768  * divider from @match_clock used for LVDS downclocking.
 769  */
 770 static bool
 771 pnv_find_best_dpll(const struct intel_limit *limit,
 772                    struct intel_crtc_state *crtc_state,
 773                    int target, int refclk, struct dpll *match_clock,
 774                    struct dpll *best_clock)
 775 {
 776         struct drm_device *dev = crtc_state->base.crtc->dev;
 777         struct dpll clock;
 778         int err = target;
 779
 780         memset(best_clock, 0, sizeof(*best_clock));
 781
 782         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 783
 784         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 785              clock.m1++) {
 786                 for (clock.m2 = limit->m2.min;
 787                      clock.m2 <= limit->m2.max; clock.m2++) {
 788                         for (clock.n = limit->n.min;
 789                              clock.n <= limit->n.max; clock.n++) {
 790                                 for (clock.p1 = limit->p1.min;
 791                                         clock.p1 <= limit->p1.max; clock.p1++) {
 792                                         int this_err;
 793
 794                                         pnv_calc_dpll_params(refclk, &clock);
 795                                         if (!intel_PLL_is_valid(dev, limit,
 796                                                                 &clock))
 797                                                 continue;
 798                                         if (match_clock &&
 799                                             clock.p != match_clock->p)
 800                                                 continue;
 801
 802                                         this_err = abs(clock.dot - target);
 803                                         if (this_err < err) {
 804                                                 *best_clock = clock;
 805                                                 err = this_err;
 806                                         }
 807                                 }
 808                         }
 809                 }
 810         }
 811
 812         return (err != target);
 813 }
 814
 815 /*
 816  * Returns a set of divisors for the desired target clock with the given
 817  * refclk, or FALSE.  The returned values represent the clock equation:
 818  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 819  *
 820  * Target and reference clocks are specified in kHz.
 821  *
 822  * If match_clock is provided, then best_clock P divider must match the P
 823  * divider from @match_clock used for LVDS downclocking.
 824  */
 825 static bool
 826 g4x_find_best_dpll(const struct intel_limit *limit,
 827                    struct intel_crtc_state *crtc_state,
 828                    int target, int refclk, struct dpll *match_clock,
 829                    struct dpll *best_clock)
 830 {
 831         struct drm_device *dev = crtc_state->base.crtc->dev;
 832         struct dpll clock;
 833         int max_n;
 834         bool found = false;
 835         /* approximately equals target * 0.00585 */
 836         int err_most = (target >> 8) + (target >> 9);
 837
 838         memset(best_clock, 0, sizeof(*best_clock));
 839
 840         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 841
 842         max_n = limit->n.max;
 843         /* based on hardware requirement, prefer smaller n to precision */
 844         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 845                 /* based on hardware requirement, prefere larger m1,m2 */
 846                 for (clock.m1 = limit->m1.max;
 847                      clock.m1 >= limit->m1.min; clock.m1--) {
 848                         for (clock.m2 = limit->m2.max;
 849                              clock.m2 >= limit->m2.min; clock.m2--) {
 850                                 for (clock.p1 = limit->p1.max;
 851                                      clock.p1 >= limit->p1.min; clock.p1--) {
 852                                         int this_err;
 853
 854                                         i9xx_calc_dpll_params(refclk, &clock);
 855                                         if (!intel_PLL_is_valid(dev, limit,
 856                                                                 &clock))
 857                                                 continue;
 858
 859                                         this_err = abs(clock.dot - target);
 860                                         if (this_err < err_most) {
 861                                                 *best_clock = clock;
 862                                                 err_most = this_err;
 863                                                 max_n = clock.n;
 864                                                 found = true;
 865                                         }
 866                                 }
 867                         }
 868                 }
 869         }
 870         return found;
 871 }
 872
 873 /*
 874  * Check if the calculated PLL configuration is more optimal compared to the
 875  * best configuration and error found so far. Return the calculated error.
 876  */
 877 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 878                                const struct dpll *calculated_clock,
 879                                const struct dpll *best_clock,
 880                                unsigned int best_error_ppm,
 881                                unsigned int *error_ppm)
 882 {
 883         /*
 884          * For CHV ignore the error and consider only the P value.
 885          * Prefer a bigger P value based on HW requirements.
 886          */
 887         if (IS_CHERRYVIEW(dev)) {
 888                 *error_ppm = 0;
 889
 890                 return calculated_clock->p > best_clock->p;
 891         }
 892
 893         if (WARN_ON_ONCE(!target_freq))
 894                 return false;
 895
 896         *error_ppm = div_u64(1000000ULL *
 897                                 abs(target_freq - calculated_clock->dot),
 898                              target_freq);
 899         /*
 900          * Prefer a better P value over a better (smaller) error if the error
 901          * is small. Ensure this preference for future configurations too by
 902          * setting the error to 0.
 903          */
 904         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 905                 *error_ppm = 0;
 906
 907                 return true;
 908         }
 909
 910         return *error_ppm + 10 < best_error_ppm;
 911 }
 912
 913 /*
 914  * Returns a set of divisors for the desired target clock with the given
 915  * refclk, or FALSE.  The returned values represent the clock equation:
 916  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 917  */
 918 static bool
 919 vlv_find_best_dpll(const struct intel_limit *limit,
 920                    struct intel_crtc_state *crtc_state,
 921                    int target, int refclk, struct dpll *match_clock,
 922                    struct dpll *best_clock)
 923 {
 924         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 925         struct drm_device *dev = crtc->base.dev;
 926         struct dpll clock;
 927         unsigned int bestppm = 1000000;
 928         /* min update 19.2 MHz */
 929         int max_n = min(limit->n.max, refclk / 19200);
 930         bool found = false;
 931
 932         target *= 5; /* fast clock */
 933
 934         memset(best_clock, 0, sizeof(*best_clock));
 935
 936         /* based on hardware requirement, prefer smaller n to precision */
 937         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 938                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 939                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 940                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 941                                 clock.p = clock.p1 * clock.p2;
 942                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 943                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 944                                         unsigned int ppm;
 945
 946                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 947                                                                      refclk * clock.m1);
 948
 949                                         vlv_calc_dpll_params(refclk, &clock);
 950
 951                                         if (!intel_PLL_is_valid(dev, limit,
 952                                                                 &clock))
 953                                                 continue;
 954
 955                                         if (!vlv_PLL_is_optimal(dev, target,
 956                                                                 &clock,
 957                                                                 best_clock,
 958                                                                 bestppm, &ppm))
 959                                                 continue;
 960
 961                                         *best_clock = clock;
 962                                         bestppm = ppm;
 963                                         found = true;
 964                                 }
 965                         }
 966                 }
 967         }
 968
 969         return found;
 970 }
 971
 972 /*
 973  * Returns a set of divisors for the desired target clock with the given
 974  * refclk, or FALSE.  The returned values represent the clock equation:
 975  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 976  */
 977 static bool
 978 chv_find_best_dpll(const struct intel_limit *limit,
 979                    struct intel_crtc_state *crtc_state,
 980                    int target, int refclk, struct dpll *match_clock,
 981                    struct dpll *best_clock)
 982 {
 983         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 984         struct drm_device *dev = crtc->base.dev;
 985         unsigned int best_error_ppm;
 986         struct dpll clock;
 987         uint64_t m2;
 988         int found = false;
 989
 990         memset(best_clock, 0, sizeof(*best_clock));
 991         best_error_ppm = 1000000;
 992
 993         /*
 994          * Based on hardware doc, the n always set to 1, and m1 always
 995          * set to 2.  If requires to support 200Mhz refclk, we need to
 996          * revisit this because n may not 1 anymore.
 997          */
 998         clock.n = 1, clock.m1 = 2;
 999         target *= 5;    /* fast clock */
1000
1001         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1002                 for (clock.p2 = limit->p2.p2_fast;
1003                                 clock.p2 >= limit->p2.p2_slow;
1004                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1005                         unsigned int error_ppm;
1006
1007                         clock.p = clock.p1 * clock.p2;
1008
1009                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1010                                         clock.n) << 22, refclk * clock.m1);
1011
1012                         if (m2 > INT_MAX/clock.m1)
1013                                 continue;
1014
1015                         clock.m2 = m2;
1016
1017                         chv_calc_dpll_params(refclk, &clock);
1018
1019                         if (!intel_PLL_is_valid(dev, limit, &clock))
1020                                 continue;
1021
1022                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1023                                                 best_error_ppm, &error_ppm))
1024                                 continue;
1025
1026                         *best_clock = clock;
1027                         best_error_ppm = error_ppm;
1028                         found = true;
1029                 }
1030         }
1031
1032         return found;
1033 }
1034
1035 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1036                         struct dpll *best_clock)
1037 {
1038         int refclk = 100000;
1039         const struct intel_limit *limit = &intel_limits_bxt;
1040
1041         return chv_find_best_dpll(limit, crtc_state,
1042                                   target_clock, refclk, NULL, best_clock);
1043 }
1044
1045 bool intel_crtc_active(struct drm_crtc *crtc)
1046 {
1047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1048
1049         /* Be paranoid as we can arrive here with only partial
1050          * state retrieved from the hardware during setup.
1051          *
1052          * We can ditch the adjusted_mode.crtc_clock check as soon
1053          * as Haswell has gained clock readout/fastboot support.
1054          *
1055          * We can ditch the crtc->primary->fb check as soon as we can
1056          * properly reconstruct framebuffers.
1057          *
1058          * FIXME: The intel_crtc->active here should be switched to
1059          * crtc->state->active once we have proper CRTC states wired up
1060          * for atomic.
1061          */
1062         return intel_crtc->active && crtc->primary->state->fb &&
1063                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1064 }
1065
1066 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1067                                              enum pipe pipe)
1068 {
1069         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1071
1072         return intel_crtc->config->cpu_transcoder;
1073 }
1074
1075 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1076 {
1077         struct drm_i915_private *dev_priv = dev->dev_private;
1078         i915_reg_t reg = PIPEDSL(pipe);
1079         u32 line1, line2;
1080         u32 line_mask;
1081
1082         if (IS_GEN2(dev))
1083                 line_mask = DSL_LINEMASK_GEN2;
1084         else
1085                 line_mask = DSL_LINEMASK_GEN3;
1086
1087         line1 = I915_READ(reg) & line_mask;
1088         msleep(5);
1089         line2 = I915_READ(reg) & line_mask;
1090
1091         return line1 == line2;
1092 }
1093
1094 /*
1095  * intel_wait_for_pipe_off - wait for pipe to turn off
1096  * @crtc: crtc whose pipe to wait for
1097  *
1098  * After disabling a pipe, we can't wait for vblank in the usual way,
1099  * spinning on the vblank interrupt status bit, since we won't actually
1100  * see an interrupt when the pipe is disabled.
1101  *
1102  * On Gen4 and above:
1103  *   wait for the pipe register state bit to turn off
1104  *
1105  * Otherwise:
1106  *   wait for the display line value to settle (it usually
1107  *   ends up stopping at the start of the next frame).
1108  *
1109  */
1110 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1111 {
1112         struct drm_device *dev = crtc->base.dev;
1113         struct drm_i915_private *dev_priv = dev->dev_private;
1114         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1115         enum pipe pipe = crtc->pipe;
1116
1117         if (INTEL_INFO(dev)->gen >= 4) {
1118                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1119
1120                 /* Wait for the Pipe State to go off */
1121                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1122                              100))
1123                         WARN(1, "pipe_off wait timed out\n");
1124         } else {
1125                 /* Wait for the display line to settle */
1126                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1127                         WARN(1, "pipe_off wait timed out\n");
1128         }
1129 }
1130
1131 /* Only for pre-ILK configs */
1132 void assert_pll(struct drm_i915_private *dev_priv,
1133                 enum pipe pipe, bool state)
1134 {
1135         u32 val;
1136         bool cur_state;
1137
1138         val = I915_READ(DPLL(pipe));
1139         cur_state = !!(val & DPLL_VCO_ENABLE);
1140         I915_STATE_WARN(cur_state != state,
1141              "PLL state assertion failure (expected %s, current %s)\n",
1142                         onoff(state), onoff(cur_state));
1143 }
1144
1145 /* XXX: the dsi pll is shared between MIPI DSI ports */
1146 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1147 {
1148         u32 val;
1149         bool cur_state;
1150
1151         mutex_lock(&dev_priv->sb_lock);
1152         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1153         mutex_unlock(&dev_priv->sb_lock);
1154
1155         cur_state = val & DSI_PLL_VCO_EN;
1156         I915_STATE_WARN(cur_state != state,
1157              "DSI PLL state assertion failure (expected %s, current %s)\n",
1158                         onoff(state), onoff(cur_state));
1159 }
1160
1161 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1162                           enum pipe pipe, bool state)
1163 {
1164         bool cur_state;
1165         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1166                                                                       pipe);
1167
1168         if (HAS_DDI(dev_priv)) {
1169                 /* DDI does not have a specific FDI_TX register */
1170                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1171                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1172         } else {
1173                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1174                 cur_state = !!(val & FDI_TX_ENABLE);
1175         }
1176         I915_STATE_WARN(cur_state != state,
1177              "FDI TX state assertion failure (expected %s, current %s)\n",
1178                         onoff(state), onoff(cur_state));
1179 }
1180 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1181 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1182
1183 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1184                           enum pipe pipe, bool state)
1185 {
1186         u32 val;
1187         bool cur_state;
1188
1189         val = I915_READ(FDI_RX_CTL(pipe));
1190         cur_state = !!(val & FDI_RX_ENABLE);
1191         I915_STATE_WARN(cur_state != state,
1192              "FDI RX state assertion failure (expected %s, current %s)\n",
1193                         onoff(state), onoff(cur_state));
1194 }
1195 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1196 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1197
1198 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1199                                       enum pipe pipe)
1200 {
1201         u32 val;
1202
1203         /* ILK FDI PLL is always enabled */
1204         if (IS_GEN5(dev_priv))
1205                 return;
1206
1207         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1208         if (HAS_DDI(dev_priv))
1209                 return;
1210
1211         val = I915_READ(FDI_TX_CTL(pipe));
1212         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1213 }
1214
1215 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1216                        enum pipe pipe, bool state)
1217 {
1218         u32 val;
1219         bool cur_state;
1220
1221         val = I915_READ(FDI_RX_CTL(pipe));
1222         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1223         I915_STATE_WARN(cur_state != state,
1224              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1225                         onoff(state), onoff(cur_state));
1226 }
1227
1228 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1229                            enum pipe pipe)
1230 {
1231         struct drm_device *dev = dev_priv->dev;
1232         i915_reg_t pp_reg;
1233         u32 val;
1234         enum pipe panel_pipe = PIPE_A;
1235         bool locked = true;
1236
1237         if (WARN_ON(HAS_DDI(dev)))
1238                 return;
1239
1240         if (HAS_PCH_SPLIT(dev)) {
1241                 u32 port_sel;
1242
1243                 pp_reg = PCH_PP_CONTROL;
1244                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1245
1246                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1247                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1248                         panel_pipe = PIPE_B;
1249                 /* XXX: else fix for eDP */
1250         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1251                 /* presumably write lock depends on pipe, not port select */
1252                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1253                 panel_pipe = pipe;
1254         } else {
1255                 pp_reg = PP_CONTROL;
1256                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1257                         panel_pipe = PIPE_B;
1258         }
1259
1260         val = I915_READ(pp_reg);
1261         if (!(val & PANEL_POWER_ON) ||
1262             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1263                 locked = false;
1264
1265         I915_STATE_WARN(panel_pipe == pipe && locked,
1266              "panel assertion failure, pipe %c regs locked\n",
1267              pipe_name(pipe));
1268 }
1269
1270 static void assert_cursor(struct drm_i915_private *dev_priv,
1271                           enum pipe pipe, bool state)
1272 {
1273         struct drm_device *dev = dev_priv->dev;
1274         bool cur_state;
1275
1276         if (IS_845G(dev) || IS_I865G(dev))
1277                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1278         else
1279                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1280
1281         I915_STATE_WARN(cur_state != state,
1282              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1283                         pipe_name(pipe), onoff(state), onoff(cur_state));
1284 }
1285 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1286 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1287
1288 void assert_pipe(struct drm_i915_private *dev_priv,
1289                  enum pipe pipe, bool state)
1290 {
1291         bool cur_state;
1292         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1293                                                                       pipe);
1294         enum intel_display_power_domain power_domain;
1295
1296         /* if we need the pipe quirk it must be always on */
1297         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1298             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1299                 state = true;
1300
1301         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1302         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1303                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1304                 cur_state = !!(val & PIPECONF_ENABLE);
1305
1306                 intel_display_power_put(dev_priv, power_domain);
1307         } else {
1308                 cur_state = false;
1309         }
1310
1311         I915_STATE_WARN(cur_state != state,
1312              "pipe %c assertion failure (expected %s, current %s)\n",
1313                         pipe_name(pipe), onoff(state), onoff(cur_state));
1314 }
1315
1316 static void assert_plane(struct drm_i915_private *dev_priv,
1317                          enum plane plane, bool state)
1318 {
1319         u32 val;
1320         bool cur_state;
1321
1322         val = I915_READ(DSPCNTR(plane));
1323         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1324         I915_STATE_WARN(cur_state != state,
1325              "plane %c assertion failure (expected %s, current %s)\n",
1326                         plane_name(plane), onoff(state), onoff(cur_state));
1327 }
1328
1329 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1330 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1331
1332 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1333                                    enum pipe pipe)
1334 {
1335         struct drm_device *dev = dev_priv->dev;
1336         int i;
1337
1338         /* Primary planes are fixed to pipes on gen4+ */
1339         if (INTEL_INFO(dev)->gen >= 4) {
1340                 u32 val = I915_READ(DSPCNTR(pipe));
1341                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1342                      "plane %c assertion failure, should be disabled but not\n",
1343                      plane_name(pipe));
1344                 return;
1345         }
1346
1347         /* Need to check both planes against the pipe */
1348         for_each_pipe(dev_priv, i) {
1349                 u32 val = I915_READ(DSPCNTR(i));
1350                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1351                         DISPPLANE_SEL_PIPE_SHIFT;
1352                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1353                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1354                      plane_name(i), pipe_name(pipe));
1355         }
1356 }
1357
1358 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1359                                     enum pipe pipe)
1360 {
1361         struct drm_device *dev = dev_priv->dev;
1362         int sprite;
1363
1364         if (INTEL_INFO(dev)->gen >= 9) {
1365                 for_each_sprite(dev_priv, pipe, sprite) {
1366                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1367                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1368                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1369                              sprite, pipe_name(pipe));
1370                 }
1371         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1372                 for_each_sprite(dev_priv, pipe, sprite) {
1373                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1374                         I915_STATE_WARN(val & SP_ENABLE,
1375                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1376                              sprite_name(pipe, sprite), pipe_name(pipe));
1377                 }
1378         } else if (INTEL_INFO(dev)->gen >= 7) {
1379                 u32 val = I915_READ(SPRCTL(pipe));
1380                 I915_STATE_WARN(val & SPRITE_ENABLE,
1381                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1382                      plane_name(pipe), pipe_name(pipe));
1383         } else if (INTEL_INFO(dev)->gen >= 5) {
1384                 u32 val = I915_READ(DVSCNTR(pipe));
1385                 I915_STATE_WARN(val & DVS_ENABLE,
1386                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1387                      plane_name(pipe), pipe_name(pipe));
1388         }
1389 }
1390
1391 static void assert_vblank_disabled(struct drm_crtc *crtc)
1392 {
1393         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1394                 drm_crtc_vblank_put(crtc);
1395 }
1396
1397 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1398                                     enum pipe pipe)
1399 {
1400         u32 val;
1401         bool enabled;
1402
1403         val = I915_READ(PCH_TRANSCONF(pipe));
1404         enabled = !!(val & TRANS_ENABLE);
1405         I915_STATE_WARN(enabled,
1406              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1407              pipe_name(pipe));
1408 }
1409
1410 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1411                             enum pipe pipe, u32 port_sel, u32 val)
1412 {
1413         if ((val & DP_PORT_EN) == 0)
1414                 return false;
1415
1416         if (HAS_PCH_CPT(dev_priv)) {
1417                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1418                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1419                         return false;
1420         } else if (IS_CHERRYVIEW(dev_priv)) {
1421                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1422                         return false;
1423         } else {
1424                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1425                         return false;
1426         }
1427         return true;
1428 }
1429
1430 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1431                               enum pipe pipe, u32 val)
1432 {
1433         if ((val & SDVO_ENABLE) == 0)
1434                 return false;
1435
1436         if (HAS_PCH_CPT(dev_priv)) {
1437                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1438                         return false;
1439         } else if (IS_CHERRYVIEW(dev_priv)) {
1440                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1441                         return false;
1442         } else {
1443                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1444                         return false;
1445         }
1446         return true;
1447 }
1448
1449 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1450                               enum pipe pipe, u32 val)
1451 {
1452         if ((val & LVDS_PORT_EN) == 0)
1453                 return false;
1454
1455         if (HAS_PCH_CPT(dev_priv)) {
1456                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1457                         return false;
1458         } else {
1459                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1460                         return false;
1461         }
1462         return true;
1463 }
1464
1465 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1466                               enum pipe pipe, u32 val)
1467 {
1468         if ((val & ADPA_DAC_ENABLE) == 0)
1469                 return false;
1470         if (HAS_PCH_CPT(dev_priv)) {
1471                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1472                         return false;
1473         } else {
1474                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1475                         return false;
1476         }
1477         return true;
1478 }
1479
1480 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1481                                    enum pipe pipe, i915_reg_t reg,
1482                                    u32 port_sel)
1483 {
1484         u32 val = I915_READ(reg);
1485         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1486              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1487              i915_mmio_reg_offset(reg), pipe_name(pipe));
1488
1489         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1490              && (val & DP_PIPEB_SELECT),
1491              "IBX PCH dp port still using transcoder B\n");
1492 }
1493
1494 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1495                                      enum pipe pipe, i915_reg_t reg)
1496 {
1497         u32 val = I915_READ(reg);
1498         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1499              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1500              i915_mmio_reg_offset(reg), pipe_name(pipe));
1501
1502         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1503              && (val & SDVO_PIPE_B_SELECT),
1504              "IBX PCH hdmi port still using transcoder B\n");
1505 }
1506
1507 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1508                                       enum pipe pipe)
1509 {
1510         u32 val;
1511
1512         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1513         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1514         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1515
1516         val = I915_READ(PCH_ADPA);
1517         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1518              "PCH VGA enabled on transcoder %c, should be disabled\n",
1519              pipe_name(pipe));
1520
1521         val = I915_READ(PCH_LVDS);
1522         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1523              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1524              pipe_name(pipe));
1525
1526         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1527         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1528         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1529 }
1530
1531 static void _vlv_enable_pll(struct intel_crtc *crtc,
1532                             const struct intel_crtc_state *pipe_config)
1533 {
1534         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1535         enum pipe pipe = crtc->pipe;
1536
1537         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1538         POSTING_READ(DPLL(pipe));
1539         udelay(150);
1540
1541         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1542                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1543 }
1544
1545 static void vlv_enable_pll(struct intel_crtc *crtc,
1546                            const struct intel_crtc_state *pipe_config)
1547 {
1548         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1549         enum pipe pipe = crtc->pipe;
1550
1551         assert_pipe_disabled(dev_priv, pipe);
1552
1553         /* PLL is protected by panel, make sure we can write it */
1554         assert_panel_unlocked(dev_priv, pipe);
1555
1556         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1557                 _vlv_enable_pll(crtc, pipe_config);
1558
1559         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1560         POSTING_READ(DPLL_MD(pipe));
1561 }
1562
1563
1564 static void _chv_enable_pll(struct intel_crtc *crtc,
1565                             const struct intel_crtc_state *pipe_config)
1566 {
1567         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1568         enum pipe pipe = crtc->pipe;
1569         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1570         u32 tmp;
1571
1572         mutex_lock(&dev_priv->sb_lock);
1573
1574         /* Enable back the 10bit clock to display controller */
1575         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1576         tmp |= DPIO_DCLKP_EN;
1577         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1578
1579         mutex_unlock(&dev_priv->sb_lock);
1580
1581         /*
1582          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1583          */
1584         udelay(1);
1585
1586         /* Enable PLL */
1587         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1588
1589         /* Check PLL is locked */
1590         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1591                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1592 }
1593
1594 static void chv_enable_pll(struct intel_crtc *crtc,
1595                            const struct intel_crtc_state *pipe_config)
1596 {
1597         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1598         enum pipe pipe = crtc->pipe;
1599
1600         assert_pipe_disabled(dev_priv, pipe);
1601
1602         /* PLL is protected by panel, make sure we can write it */
1603         assert_panel_unlocked(dev_priv, pipe);
1604
1605         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1606                 _chv_enable_pll(crtc, pipe_config);
1607
1608         if (pipe != PIPE_A) {
1609                 /*
1610                  * WaPixelRepeatModeFixForC0:chv
1611                  *
1612                  * DPLLCMD is AWOL. Use chicken bits to propagate
1613                  * the value from DPLLBMD to either pipe B or C.
1614                  */
1615                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1616                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1617                 I915_WRITE(CBR4_VLV, 0);
1618                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1619
1620                 /*
1621                  * DPLLB VGA mode also seems to cause problems.
1622                  * We should always have it disabled.
1623                  */
1624                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1625         } else {
1626                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1627                 POSTING_READ(DPLL_MD(pipe));
1628         }
1629 }
1630
1631 static int intel_num_dvo_pipes(struct drm_device *dev)
1632 {
1633         struct intel_crtc *crtc;
1634         int count = 0;
1635
1636         for_each_intel_crtc(dev, crtc)
1637                 count += crtc->base.state->active &&
1638                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1639
1640         return count;
1641 }
1642
1643 static void i9xx_enable_pll(struct intel_crtc *crtc)
1644 {
1645         struct drm_device *dev = crtc->base.dev;
1646         struct drm_i915_private *dev_priv = dev->dev_private;
1647         i915_reg_t reg = DPLL(crtc->pipe);
1648         u32 dpll = crtc->config->dpll_hw_state.dpll;
1649
1650         assert_pipe_disabled(dev_priv, crtc->pipe);
1651
1652         /* PLL is protected by panel, make sure we can write it */
1653         if (IS_MOBILE(dev) && !IS_I830(dev))
1654                 assert_panel_unlocked(dev_priv, crtc->pipe);
1655
1656         /* Enable DVO 2x clock on both PLLs if necessary */
1657         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1658                 /*
1659                  * It appears to be important that we don't enable this
1660                  * for the current pipe before otherwise configuring the
1661                  * PLL. No idea how this should be handled if multiple
1662                  * DVO outputs are enabled simultaneosly.
1663                  */
1664                 dpll |= DPLL_DVO_2X_MODE;
1665                 I915_WRITE(DPLL(!crtc->pipe),
1666                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1667         }
1668
1669         /*
1670          * Apparently we need to have VGA mode enabled prior to changing
1671          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1672          * dividers, even though the register value does change.
1673          */
1674         I915_WRITE(reg, 0);
1675
1676         I915_WRITE(reg, dpll);
1677
1678         /* Wait for the clocks to stabilize. */
1679         POSTING_READ(reg);
1680         udelay(150);
1681
1682         if (INTEL_INFO(dev)->gen >= 4) {
1683                 I915_WRITE(DPLL_MD(crtc->pipe),
1684                            crtc->config->dpll_hw_state.dpll_md);
1685         } else {
1686                 /* The pixel multiplier can only be updated once the
1687                  * DPLL is enabled and the clocks are stable.
1688                  *
1689                  * So write it again.
1690                  */
1691                 I915_WRITE(reg, dpll);
1692         }
1693
1694         /* We do this three times for luck */
1695         I915_WRITE(reg, dpll);
1696         POSTING_READ(reg);
1697         udelay(150); /* wait for warmup */
1698         I915_WRITE(reg, dpll);
1699         POSTING_READ(reg);
1700         udelay(150); /* wait for warmup */
1701         I915_WRITE(reg, dpll);
1702         POSTING_READ(reg);
1703         udelay(150); /* wait for warmup */
1704 }
1705
1706 /**
1707  * i9xx_disable_pll - disable a PLL
1708  * @dev_priv: i915 private structure
1709  * @pipe: pipe PLL to disable
1710  *
1711  * Disable the PLL for @pipe, making sure the pipe is off first.
1712  *
1713  * Note!  This is for pre-ILK only.
1714  */
1715 static void i9xx_disable_pll(struct intel_crtc *crtc)
1716 {
1717         struct drm_device *dev = crtc->base.dev;
1718         struct drm_i915_private *dev_priv = dev->dev_private;
1719         enum pipe pipe = crtc->pipe;
1720
1721         /* Disable DVO 2x clock on both PLLs if necessary */
1722         if (IS_I830(dev) &&
1723             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1724             !intel_num_dvo_pipes(dev)) {
1725                 I915_WRITE(DPLL(PIPE_B),
1726                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1727                 I915_WRITE(DPLL(PIPE_A),
1728                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1729         }
1730
1731         /* Don't disable pipe or pipe PLLs if needed */
1732         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1733             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1734                 return;
1735
1736         /* Make sure the pipe isn't still relying on us */
1737         assert_pipe_disabled(dev_priv, pipe);
1738
1739         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1740         POSTING_READ(DPLL(pipe));
1741 }
1742
1743 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1744 {
1745         u32 val;
1746
1747         /* Make sure the pipe isn't still relying on us */
1748         assert_pipe_disabled(dev_priv, pipe);
1749
1750         val = DPLL_INTEGRATED_REF_CLK_VLV |
1751                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1752         if (pipe != PIPE_A)
1753                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1754
1755         I915_WRITE(DPLL(pipe), val);
1756         POSTING_READ(DPLL(pipe));
1757 }
1758
1759 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1760 {
1761         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1762         u32 val;
1763
1764         /* Make sure the pipe isn't still relying on us */
1765         assert_pipe_disabled(dev_priv, pipe);
1766
1767         val = DPLL_SSC_REF_CLK_CHV |
1768                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1769         if (pipe != PIPE_A)
1770                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1771
1772         I915_WRITE(DPLL(pipe), val);
1773         POSTING_READ(DPLL(pipe));
1774
1775         mutex_lock(&dev_priv->sb_lock);
1776
1777         /* Disable 10bit clock to display controller */
1778         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1779         val &= ~DPIO_DCLKP_EN;
1780         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1781
1782         mutex_unlock(&dev_priv->sb_lock);
1783 }
1784
1785 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1786                          struct intel_digital_port *dport,
1787                          unsigned int expected_mask)
1788 {
1789         u32 port_mask;
1790         i915_reg_t dpll_reg;
1791
1792         switch (dport->port) {
1793         case PORT_B:
1794                 port_mask = DPLL_PORTB_READY_MASK;
1795                 dpll_reg = DPLL(0);
1796                 break;
1797         case PORT_C:
1798                 port_mask = DPLL_PORTC_READY_MASK;
1799                 dpll_reg = DPLL(0);
1800                 expected_mask <<= 4;
1801                 break;
1802         case PORT_D:
1803                 port_mask = DPLL_PORTD_READY_MASK;
1804                 dpll_reg = DPIO_PHY_STATUS;
1805                 break;
1806         default:
1807                 BUG();
1808         }
1809
1810         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1811                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1812                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1813 }
1814
1815 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1816                                            enum pipe pipe)
1817 {
1818         struct drm_device *dev = dev_priv->dev;
1819         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1821         i915_reg_t reg;
1822         uint32_t val, pipeconf_val;
1823
1824         /* Make sure PCH DPLL is enabled */
1825         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1826
1827         /* FDI must be feeding us bits for PCH ports */
1828         assert_fdi_tx_enabled(dev_priv, pipe);
1829         assert_fdi_rx_enabled(dev_priv, pipe);
1830
1831         if (HAS_PCH_CPT(dev)) {
1832                 /* Workaround: Set the timing override bit before enabling the
1833                  * pch transcoder. */
1834                 reg = TRANS_CHICKEN2(pipe);
1835                 val = I915_READ(reg);
1836                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1837                 I915_WRITE(reg, val);
1838         }
1839
1840         reg = PCH_TRANSCONF(pipe);
1841         val = I915_READ(reg);
1842         pipeconf_val = I915_READ(PIPECONF(pipe));
1843
1844         if (HAS_PCH_IBX(dev_priv)) {
1845                 /*
1846                  * Make the BPC in transcoder be consistent with
1847                  * that in pipeconf reg. For HDMI we must use 8bpc
1848                  * here for both 8bpc and 12bpc.
1849                  */
1850                 val &= ~PIPECONF_BPC_MASK;
1851                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1852                         val |= PIPECONF_8BPC;
1853                 else
1854                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1855         }
1856
1857         val &= ~TRANS_INTERLACE_MASK;
1858         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1859                 if (HAS_PCH_IBX(dev_priv) &&
1860                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1861                         val |= TRANS_LEGACY_INTERLACED_ILK;
1862                 else
1863                         val |= TRANS_INTERLACED;
1864         else
1865                 val |= TRANS_PROGRESSIVE;
1866
1867         I915_WRITE(reg, val | TRANS_ENABLE);
1868         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1869                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1870 }
1871
1872 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1873                                       enum transcoder cpu_transcoder)
1874 {
1875         u32 val, pipeconf_val;
1876
1877         /* FDI must be feeding us bits for PCH ports */
1878         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1879         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1880
1881         /* Workaround: set timing override bit. */
1882         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1883         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1884         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1885
1886         val = TRANS_ENABLE;
1887         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1888
1889         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1890             PIPECONF_INTERLACED_ILK)
1891                 val |= TRANS_INTERLACED;
1892         else
1893                 val |= TRANS_PROGRESSIVE;
1894
1895         I915_WRITE(LPT_TRANSCONF, val);
1896         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1897                 DRM_ERROR("Failed to enable PCH transcoder\n");
1898 }
1899
1900 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1901                                             enum pipe pipe)
1902 {
1903         struct drm_device *dev = dev_priv->dev;
1904         i915_reg_t reg;
1905         uint32_t val;
1906
1907         /* FDI relies on the transcoder */
1908         assert_fdi_tx_disabled(dev_priv, pipe);
1909         assert_fdi_rx_disabled(dev_priv, pipe);
1910
1911         /* Ports must be off as well */
1912         assert_pch_ports_disabled(dev_priv, pipe);
1913
1914         reg = PCH_TRANSCONF(pipe);
1915         val = I915_READ(reg);
1916         val &= ~TRANS_ENABLE;
1917         I915_WRITE(reg, val);
1918         /* wait for PCH transcoder off, transcoder state */
1919         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1920                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1921
1922         if (HAS_PCH_CPT(dev)) {
1923                 /* Workaround: Clear the timing override chicken bit again. */
1924                 reg = TRANS_CHICKEN2(pipe);
1925                 val = I915_READ(reg);
1926                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1927                 I915_WRITE(reg, val);
1928         }
1929 }
1930
1931 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1932 {
1933         u32 val;
1934
1935         val = I915_READ(LPT_TRANSCONF);
1936         val &= ~TRANS_ENABLE;
1937         I915_WRITE(LPT_TRANSCONF, val);
1938         /* wait for PCH transcoder off, transcoder state */
1939         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1940                 DRM_ERROR("Failed to disable PCH transcoder\n");
1941
1942         /* Workaround: clear timing override bit. */
1943         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1944         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1945         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1946 }
1947
1948 /**
1949  * intel_enable_pipe - enable a pipe, asserting requirements
1950  * @crtc: crtc responsible for the pipe
1951  *
1952  * Enable @crtc's pipe, making sure that various hardware specific requirements
1953  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1954  */
1955 static void intel_enable_pipe(struct intel_crtc *crtc)
1956 {
1957         struct drm_device *dev = crtc->base.dev;
1958         struct drm_i915_private *dev_priv = dev->dev_private;
1959         enum pipe pipe = crtc->pipe;
1960         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1961         enum pipe pch_transcoder;
1962         i915_reg_t reg;
1963         u32 val;
1964
1965         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1966
1967         assert_planes_disabled(dev_priv, pipe);
1968         assert_cursor_disabled(dev_priv, pipe);
1969         assert_sprites_disabled(dev_priv, pipe);
1970
1971         if (HAS_PCH_LPT(dev_priv))
1972                 pch_transcoder = TRANSCODER_A;
1973         else
1974                 pch_transcoder = pipe;
1975
1976         /*
1977          * A pipe without a PLL won't actually be able to drive bits from
1978          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1979          * need the check.
1980          */
1981         if (HAS_GMCH_DISPLAY(dev_priv))
1982                 if (crtc->config->has_dsi_encoder)
1983                         assert_dsi_pll_enabled(dev_priv);
1984                 else
1985                         assert_pll_enabled(dev_priv, pipe);
1986         else {
1987                 if (crtc->config->has_pch_encoder) {
1988                         /* if driving the PCH, we need FDI enabled */
1989                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1990                         assert_fdi_tx_pll_enabled(dev_priv,
1991                                                   (enum pipe) cpu_transcoder);
1992                 }
1993                 /* FIXME: assert CPU port conditions for SNB+ */
1994         }
1995
1996         reg = PIPECONF(cpu_transcoder);
1997         val = I915_READ(reg);
1998         if (val & PIPECONF_ENABLE) {
1999                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2000                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2001                 return;
2002         }
2003
2004         I915_WRITE(reg, val | PIPECONF_ENABLE);
2005         POSTING_READ(reg);
2006
2007         /*
2008          * Until the pipe starts DSL will read as 0, which would cause
2009          * an apparent vblank timestamp jump, which messes up also the
2010          * frame count when it's derived from the timestamps. So let's
2011          * wait for the pipe to start properly before we call
2012          * drm_crtc_vblank_on()
2013          */
2014         if (dev->max_vblank_count == 0 &&
2015             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2016                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2017 }
2018
2019 /**
2020  * intel_disable_pipe - disable a pipe, asserting requirements
2021  * @crtc: crtc whose pipes is to be disabled
2022  *
2023  * Disable the pipe of @crtc, making sure that various hardware
2024  * specific requirements are met, if applicable, e.g. plane
2025  * disabled, panel fitter off, etc.
2026  *
2027  * Will wait until the pipe has shut down before returning.
2028  */
2029 static void intel_disable_pipe(struct intel_crtc *crtc)
2030 {
2031         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2032         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2033         enum pipe pipe = crtc->pipe;
2034         i915_reg_t reg;
2035         u32 val;
2036
2037         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2038
2039         /*
2040          * Make sure planes won't keep trying to pump pixels to us,
2041          * or we might hang the display.
2042          */
2043         assert_planes_disabled(dev_priv, pipe);
2044         assert_cursor_disabled(dev_priv, pipe);
2045         assert_sprites_disabled(dev_priv, pipe);
2046
2047         reg = PIPECONF(cpu_transcoder);
2048         val = I915_READ(reg);
2049         if ((val & PIPECONF_ENABLE) == 0)
2050                 return;
2051
2052         /*
2053          * Double wide has implications for planes
2054          * so best keep it disabled when not needed.
2055          */
2056         if (crtc->config->double_wide)
2057                 val &= ~PIPECONF_DOUBLE_WIDE;
2058
2059         /* Don't disable pipe or pipe PLLs if needed */
2060         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2061             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2062                 val &= ~PIPECONF_ENABLE;
2063
2064         I915_WRITE(reg, val);
2065         if ((val & PIPECONF_ENABLE) == 0)
2066                 intel_wait_for_pipe_off(crtc);
2067 }
2068
2069 static bool need_vtd_wa(struct drm_device *dev)
2070 {
2071 #ifdef CONFIG_INTEL_IOMMU
2072         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2073                 return true;
2074 #endif
2075         return false;
2076 }
2077
2078 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2079 {
2080         return IS_GEN2(dev_priv) ? 2048 : 4096;
2081 }
2082
2083 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2084                                            uint64_t fb_modifier, unsigned int cpp)
2085 {
2086         switch (fb_modifier) {
2087         case DRM_FORMAT_MOD_NONE:
2088                 return cpp;
2089         case I915_FORMAT_MOD_X_TILED:
2090                 if (IS_GEN2(dev_priv))
2091                         return 128;
2092                 else
2093                         return 512;
2094         case I915_FORMAT_MOD_Y_TILED:
2095                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2096                         return 128;
2097                 else
2098                         return 512;
2099         case I915_FORMAT_MOD_Yf_TILED:
2100                 switch (cpp) {
2101                 case 1:
2102                         return 64;
2103                 case 2:
2104                 case 4:
2105                         return 128;
2106                 case 8:
2107                 case 16:
2108                         return 256;
2109                 default:
2110                         MISSING_CASE(cpp);
2111                         return cpp;
2112                 }
2113                 break;
2114         default:
2115                 MISSING_CASE(fb_modifier);
2116                 return cpp;
2117         }
2118 }
2119
2120 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2121                                uint64_t fb_modifier, unsigned int cpp)
2122 {
2123         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2124                 return 1;
2125         else
2126                 return intel_tile_size(dev_priv) /
2127                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2128 }
2129
2130 /* Return the tile dimensions in pixel units */
2131 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2132                             unsigned int *tile_width,
2133                             unsigned int *tile_height,
2134                             uint64_t fb_modifier,
2135                             unsigned int cpp)
2136 {
2137         unsigned int tile_width_bytes =
2138                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2139
2140         *tile_width = tile_width_bytes / cpp;
2141         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2142 }
2143
2144 unsigned int
2145 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2146                       uint32_t pixel_format, uint64_t fb_modifier)
2147 {
2148         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2149         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2150
2151         return ALIGN(height, tile_height);
2152 }
2153
2154 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2155 {
2156         unsigned int size = 0;
2157         int i;
2158
2159         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2160                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2161
2162         return size;
2163 }
2164
2165 static void
2166 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2167                         const struct drm_framebuffer *fb,
2168                         unsigned int rotation)
2169 {
2170         if (intel_rotation_90_or_270(rotation)) {
2171                 *view = i915_ggtt_view_rotated;
2172                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2173         } else {
2174                 *view = i915_ggtt_view_normal;
2175         }
2176 }
2177
2178 static void
2179 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2180                    struct drm_framebuffer *fb)
2181 {
2182         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2183         unsigned int tile_size, tile_width, tile_height, cpp;
2184
2185         tile_size = intel_tile_size(dev_priv);
2186
2187         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2188         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2189                         fb->modifier[0], cpp);
2190
2191         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2192         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2193
2194         if (info->pixel_format == DRM_FORMAT_NV12) {
2195                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2196                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2197                                 fb->modifier[1], cpp);
2198
2199                 info->uv_offset = fb->offsets[1];
2200                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2201                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2202         }
2203 }
2204
2205 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2206 {
2207         if (INTEL_INFO(dev_priv)->gen >= 9)
2208                 return 256 * 1024;
2209         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2210                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2211                 return 128 * 1024;
2212         else if (INTEL_INFO(dev_priv)->gen >= 4)
2213                 return 4 * 1024;
2214         else
2215                 return 0;
2216 }
2217
2218 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2219                                          uint64_t fb_modifier)
2220 {
2221         switch (fb_modifier) {
2222         case DRM_FORMAT_MOD_NONE:
2223                 return intel_linear_alignment(dev_priv);
2224         case I915_FORMAT_MOD_X_TILED:
2225                 if (INTEL_INFO(dev_priv)->gen >= 9)
2226                         return 256 * 1024;
2227                 return 0;
2228         case I915_FORMAT_MOD_Y_TILED:
2229         case I915_FORMAT_MOD_Yf_TILED:
2230                 return 1 * 1024 * 1024;
2231         default:
2232                 MISSING_CASE(fb_modifier);
2233                 return 0;
2234         }
2235 }
2236
2237 int
2238 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2239                            unsigned int rotation)
2240 {
2241         struct drm_device *dev = fb->dev;
2242         struct drm_i915_private *dev_priv = dev->dev_private;
2243         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2244         struct i915_ggtt_view view;
2245         u32 alignment;
2246         int ret;
2247
2248         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2249
2250         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2251
2252         intel_fill_fb_ggtt_view(&view, fb, rotation);
2253
2254         /* Note that the w/a also requires 64 PTE of padding following the
2255          * bo. We currently fill all unused PTE with the shadow page and so
2256          * we should always have valid PTE following the scanout preventing
2257          * the VT-d warning.
2258          */
2259         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2260                 alignment = 256 * 1024;
2261
2262         /*
2263          * Global gtt pte registers are special registers which actually forward
2264          * writes to a chunk of system memory. Which means that there is no risk
2265          * that the register values disappear as soon as we call
2266          * intel_runtime_pm_put(), so it is correct to wrap only the
2267          * pin/unpin/fence and not more.
2268          */
2269         intel_runtime_pm_get(dev_priv);
2270
2271         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2272                                                    &view);
2273         if (ret)
2274                 goto err_pm;
2275
2276         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2277          * fence, whereas 965+ only requires a fence if using
2278          * framebuffer compression.  For simplicity, we always install
2279          * a fence as the cost is not that onerous.
2280          */
2281         if (view.type == I915_GGTT_VIEW_NORMAL) {
2282                 ret = i915_gem_object_get_fence(obj);
2283                 if (ret == -EDEADLK) {
2284                         /*
2285                          * -EDEADLK means there are no free fences
2286                          * no pending flips.
2287                          *
2288                          * This is propagated to atomic, but it uses
2289                          * -EDEADLK to force a locking recovery, so
2290                          * change the returned error to -EBUSY.
2291                          */
2292                         ret = -EBUSY;
2293                         goto err_unpin;
2294                 } else if (ret)
2295                         goto err_unpin;
2296
2297                 i915_gem_object_pin_fence(obj);
2298         }
2299
2300         intel_runtime_pm_put(dev_priv);
2301         return 0;
2302
2303 err_unpin:
2304         i915_gem_object_unpin_from_display_plane(obj, &view);
2305 err_pm:
2306         intel_runtime_pm_put(dev_priv);
2307         return ret;
2308 }
2309
2310 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2311 {
2312         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2313         struct i915_ggtt_view view;
2314
2315         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2316
2317         intel_fill_fb_ggtt_view(&view, fb, rotation);
2318
2319         if (view.type == I915_GGTT_VIEW_NORMAL)
2320                 i915_gem_object_unpin_fence(obj);
2321
2322         i915_gem_object_unpin_from_display_plane(obj, &view);
2323 }
2324
2325 /*
2326  * Adjust the tile offset by moving the difference into
2327  * the x/y offsets.
2328  *
2329  * Input tile dimensions and pitch must already be
2330  * rotated to match x and y, and in pixel units.
2331  */
2332 static u32 intel_adjust_tile_offset(int *x, int *y,
2333                                     unsigned int tile_width,
2334                                     unsigned int tile_height,
2335                                     unsigned int tile_size,
2336                                     unsigned int pitch_tiles,
2337                                     u32 old_offset,
2338                                     u32 new_offset)
2339 {
2340         unsigned int tiles;
2341
2342         WARN_ON(old_offset & (tile_size - 1));
2343         WARN_ON(new_offset & (tile_size - 1));
2344         WARN_ON(new_offset > old_offset);
2345
2346         tiles = (old_offset - new_offset) / tile_size;
2347
2348         *y += tiles / pitch_tiles * tile_height;
2349         *x += tiles % pitch_tiles * tile_width;
2350
2351         return new_offset;
2352 }
2353
2354 /*
2355  * Computes the linear offset to the base tile and adjusts
2356  * x, y. bytes per pixel is assumed to be a power-of-two.
2357  *
2358  * In the 90/270 rotated case, x and y are assumed
2359  * to be already rotated to match the rotated GTT view, and
2360  * pitch is the tile_height aligned framebuffer height.
2361  */
2362 u32 intel_compute_tile_offset(int *x, int *y,
2363                               const struct drm_framebuffer *fb, int plane,
2364                               unsigned int pitch,
2365                               unsigned int rotation)
2366 {
2367         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2368         uint64_t fb_modifier = fb->modifier[plane];
2369         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2370         u32 offset, offset_aligned, alignment;
2371
2372         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2373         if (alignment)
2374                 alignment--;
2375
2376         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2377                 unsigned int tile_size, tile_width, tile_height;
2378                 unsigned int tile_rows, tiles, pitch_tiles;
2379
2380                 tile_size = intel_tile_size(dev_priv);
2381                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2382                                 fb_modifier, cpp);
2383
2384                 if (intel_rotation_90_or_270(rotation)) {
2385                         pitch_tiles = pitch / tile_height;
2386                         swap(tile_width, tile_height);
2387                 } else {
2388                         pitch_tiles = pitch / (tile_width * cpp);
2389                 }
2390
2391                 tile_rows = *y / tile_height;
2392                 *y %= tile_height;
2393
2394                 tiles = *x / tile_width;
2395                 *x %= tile_width;
2396
2397                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2398                 offset_aligned = offset & ~alignment;
2399
2400                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2401                                          tile_size, pitch_tiles,
2402                                          offset, offset_aligned);
2403         } else {
2404                 offset = *y * pitch + *x * cpp;
2405                 offset_aligned = offset & ~alignment;
2406
2407                 *y = (offset & alignment) / pitch;
2408                 *x = ((offset & alignment) - *y * pitch) / cpp;
2409         }
2410
2411         return offset_aligned;
2412 }
2413
2414 static int i9xx_format_to_fourcc(int format)
2415 {
2416         switch (format) {
2417         case DISPPLANE_8BPP:
2418                 return DRM_FORMAT_C8;
2419         case DISPPLANE_BGRX555:
2420                 return DRM_FORMAT_XRGB1555;
2421         case DISPPLANE_BGRX565:
2422                 return DRM_FORMAT_RGB565;
2423         default:
2424         case DISPPLANE_BGRX888:
2425                 return DRM_FORMAT_XRGB8888;
2426         case DISPPLANE_RGBX888:
2427                 return DRM_FORMAT_XBGR8888;
2428         case DISPPLANE_BGRX101010:
2429                 return DRM_FORMAT_XRGB2101010;
2430         case DISPPLANE_RGBX101010:
2431                 return DRM_FORMAT_XBGR2101010;
2432         }
2433 }
2434
2435 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2436 {
2437         switch (format) {
2438         case PLANE_CTL_FORMAT_RGB_565:
2439                 return DRM_FORMAT_RGB565;
2440         default:
2441         case PLANE_CTL_FORMAT_XRGB_8888:
2442                 if (rgb_order) {
2443                         if (alpha)
2444                                 return DRM_FORMAT_ABGR8888;
2445                         else
2446                                 return DRM_FORMAT_XBGR8888;
2447                 } else {
2448                         if (alpha)
2449                                 return DRM_FORMAT_ARGB8888;
2450                         else
2451                                 return DRM_FORMAT_XRGB8888;
2452                 }
2453         case PLANE_CTL_FORMAT_XRGB_2101010:
2454                 if (rgb_order)
2455                         return DRM_FORMAT_XBGR2101010;
2456                 else
2457                         return DRM_FORMAT_XRGB2101010;
2458         }
2459 }
2460
2461 static bool
2462 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2463                               struct intel_initial_plane_config *plane_config)
2464 {
2465         struct drm_device *dev = crtc->base.dev;
2466         struct drm_i915_private *dev_priv = to_i915(dev);
2467         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2468         struct drm_i915_gem_object *obj = NULL;
2469         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2470         struct drm_framebuffer *fb = &plane_config->fb->base;
2471         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2472         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2473                                     PAGE_SIZE);
2474
2475         size_aligned -= base_aligned;
2476
2477         if (plane_config->size == 0)
2478                 return false;
2479
2480         /* If the FB is too big, just don't use it since fbdev is not very
2481          * important and we should probably use that space with FBC or other
2482          * features. */
2483         if (size_aligned * 2 > ggtt->stolen_usable_size)
2484                 return false;
2485
2486         mutex_lock(&dev->struct_mutex);
2487
2488         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2489                                                              base_aligned,
2490                                                              base_aligned,
2491                                                              size_aligned);
2492         if (!obj) {
2493                 mutex_unlock(&dev->struct_mutex);
2494                 return false;
2495         }
2496
2497         obj->tiling_mode = plane_config->tiling;
2498         if (obj->tiling_mode == I915_TILING_X)
2499                 obj->stride = fb->pitches[0];
2500
2501         mode_cmd.pixel_format = fb->pixel_format;
2502         mode_cmd.width = fb->width;
2503         mode_cmd.height = fb->height;
2504         mode_cmd.pitches[0] = fb->pitches[0];
2505         mode_cmd.modifier[0] = fb->modifier[0];
2506         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2507
2508         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2509                                    &mode_cmd, obj)) {
2510                 DRM_DEBUG_KMS("intel fb init failed\n");
2511                 goto out_unref_obj;
2512         }
2513
2514         mutex_unlock(&dev->struct_mutex);
2515
2516         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2517         return true;
2518
2519 out_unref_obj:
2520         drm_gem_object_unreference(&obj->base);
2521         mutex_unlock(&dev->struct_mutex);
2522         return false;
2523 }
2524
2525 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2526 static void
2527 update_state_fb(struct drm_plane *plane)
2528 {
2529         if (plane->fb == plane->state->fb)
2530                 return;
2531
2532         if (plane->state->fb)
2533                 drm_framebuffer_unreference(plane->state->fb);
2534         plane->state->fb = plane->fb;
2535         if (plane->state->fb)
2536                 drm_framebuffer_reference(plane->state->fb);
2537 }
2538
2539 static void
2540 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2541                              struct intel_initial_plane_config *plane_config)
2542 {
2543         struct drm_device *dev = intel_crtc->base.dev;
2544         struct drm_i915_private *dev_priv = dev->dev_private;
2545         struct drm_crtc *c;
2546         struct intel_crtc *i;
2547         struct drm_i915_gem_object *obj;
2548         struct drm_plane *primary = intel_crtc->base.primary;
2549         struct drm_plane_state *plane_state = primary->state;
2550         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2551         struct intel_plane *intel_plane = to_intel_plane(primary);
2552         struct intel_plane_state *intel_state =
2553                 to_intel_plane_state(plane_state);
2554         struct drm_framebuffer *fb;
2555
2556         if (!plane_config->fb)
2557                 return;
2558
2559         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2560                 fb = &plane_config->fb->base;
2561                 goto valid_fb;
2562         }
2563
2564         kfree(plane_config->fb);
2565
2566         /*
2567          * Failed to alloc the obj, check to see if we should share
2568          * an fb with another CRTC instead
2569          */
2570         for_each_crtc(dev, c) {
2571                 i = to_intel_crtc(c);
2572
2573                 if (c == &intel_crtc->base)
2574                         continue;
2575
2576                 if (!i->active)
2577                         continue;
2578
2579                 fb = c->primary->fb;
2580                 if (!fb)
2581                         continue;
2582
2583                 obj = intel_fb_obj(fb);
2584                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2585                         drm_framebuffer_reference(fb);
2586                         goto valid_fb;
2587                 }
2588         }
2589
2590         /*
2591          * We've failed to reconstruct the BIOS FB.  Current display state
2592          * indicates that the primary plane is visible, but has a NULL FB,
2593          * which will lead to problems later if we don't fix it up.  The
2594          * simplest solution is to just disable the primary plane now and
2595          * pretend the BIOS never had it enabled.
2596          */
2597         to_intel_plane_state(plane_state)->visible = false;
2598         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2599         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2600         intel_plane->disable_plane(primary, &intel_crtc->base);
2601
2602         return;
2603
2604 valid_fb:
2605         plane_state->src_x = 0;
2606         plane_state->src_y = 0;
2607         plane_state->src_w = fb->width << 16;
2608         plane_state->src_h = fb->height << 16;
2609
2610         plane_state->crtc_x = 0;
2611         plane_state->crtc_y = 0;
2612         plane_state->crtc_w = fb->width;
2613         plane_state->crtc_h = fb->height;
2614
2615         intel_state->src.x1 = plane_state->src_x;
2616         intel_state->src.y1 = plane_state->src_y;
2617         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2618         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2619         intel_state->dst.x1 = plane_state->crtc_x;
2620         intel_state->dst.y1 = plane_state->crtc_y;
2621         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2622         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2623
2624         obj = intel_fb_obj(fb);
2625         if (obj->tiling_mode != I915_TILING_NONE)
2626                 dev_priv->preserve_bios_swizzle = true;
2627
2628         drm_framebuffer_reference(fb);
2629         primary->fb = primary->state->fb = fb;
2630         primary->crtc = primary->state->crtc = &intel_crtc->base;
2631         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2632         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2633 }
2634
2635 static void i9xx_update_primary_plane(struct drm_plane *primary,
2636                                       const struct intel_crtc_state *crtc_state,
2637                                       const struct intel_plane_state *plane_state)
2638 {
2639         struct drm_device *dev = primary->dev;
2640         struct drm_i915_private *dev_priv = dev->dev_private;
2641         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2642         struct drm_framebuffer *fb = plane_state->base.fb;
2643         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2644         int plane = intel_crtc->plane;
2645         u32 linear_offset;
2646         u32 dspcntr;
2647         i915_reg_t reg = DSPCNTR(plane);
2648         unsigned int rotation = plane_state->base.rotation;
2649         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2650         int x = plane_state->src.x1 >> 16;
2651         int y = plane_state->src.y1 >> 16;
2652
2653         dspcntr = DISPPLANE_GAMMA_ENABLE;
2654
2655         dspcntr |= DISPLAY_PLANE_ENABLE;
2656
2657         if (INTEL_INFO(dev)->gen < 4) {
2658                 if (intel_crtc->pipe == PIPE_B)
2659                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2660
2661                 /* pipesrc and dspsize control the size that is scaled from,
2662                  * which should always be the user's requested size.
2663                  */
2664                 I915_WRITE(DSPSIZE(plane),
2665                            ((crtc_state->pipe_src_h - 1) << 16) |
2666                            (crtc_state->pipe_src_w - 1));
2667                 I915_WRITE(DSPPOS(plane), 0);
2668         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2669                 I915_WRITE(PRIMSIZE(plane),
2670                            ((crtc_state->pipe_src_h - 1) << 16) |
2671                            (crtc_state->pipe_src_w - 1));
2672                 I915_WRITE(PRIMPOS(plane), 0);
2673                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2674         }
2675
2676         switch (fb->pixel_format) {
2677         case DRM_FORMAT_C8:
2678                 dspcntr |= DISPPLANE_8BPP;
2679                 break;
2680         case DRM_FORMAT_XRGB1555:
2681                 dspcntr |= DISPPLANE_BGRX555;
2682                 break;
2683         case DRM_FORMAT_RGB565:
2684                 dspcntr |= DISPPLANE_BGRX565;
2685                 break;
2686         case DRM_FORMAT_XRGB8888:
2687                 dspcntr |= DISPPLANE_BGRX888;
2688                 break;
2689         case DRM_FORMAT_XBGR8888:
2690                 dspcntr |= DISPPLANE_RGBX888;
2691                 break;
2692         case DRM_FORMAT_XRGB2101010:
2693                 dspcntr |= DISPPLANE_BGRX101010;
2694                 break;
2695         case DRM_FORMAT_XBGR2101010:
2696                 dspcntr |= DISPPLANE_RGBX101010;
2697                 break;
2698         default:
2699                 BUG();
2700         }
2701
2702         if (INTEL_INFO(dev)->gen >= 4 &&
2703             obj->tiling_mode != I915_TILING_NONE)
2704                 dspcntr |= DISPPLANE_TILED;
2705
2706         if (IS_G4X(dev))
2707                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2708
2709         linear_offset = y * fb->pitches[0] + x * cpp;
2710
2711         if (INTEL_INFO(dev)->gen >= 4) {
2712                 intel_crtc->dspaddr_offset =
2713                         intel_compute_tile_offset(&x, &y, fb, 0,
2714                                                   fb->pitches[0], rotation);
2715                 linear_offset -= intel_crtc->dspaddr_offset;
2716         } else {
2717                 intel_crtc->dspaddr_offset = linear_offset;
2718         }
2719
2720         if (rotation == BIT(DRM_ROTATE_180)) {
2721                 dspcntr |= DISPPLANE_ROTATE_180;
2722
2723                 x += (crtc_state->pipe_src_w - 1);
2724                 y += (crtc_state->pipe_src_h - 1);
2725
2726                 /* Finding the last pixel of the last line of the display
2727                 data and adding to linear_offset*/
2728                 linear_offset +=
2729                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2730                         (crtc_state->pipe_src_w - 1) * cpp;
2731         }
2732
2733         intel_crtc->adjusted_x = x;
2734         intel_crtc->adjusted_y = y;
2735
2736         I915_WRITE(reg, dspcntr);
2737
2738         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2739         if (INTEL_INFO(dev)->gen >= 4) {
2740                 I915_WRITE(DSPSURF(plane),
2741                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2742                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2743                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2744         } else
2745                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2746         POSTING_READ(reg);
2747 }
2748
2749 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2750                                        struct drm_crtc *crtc)
2751 {
2752         struct drm_device *dev = crtc->dev;
2753         struct drm_i915_private *dev_priv = dev->dev_private;
2754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2755         int plane = intel_crtc->plane;
2756
2757         I915_WRITE(DSPCNTR(plane), 0);
2758         if (INTEL_INFO(dev_priv)->gen >= 4)
2759                 I915_WRITE(DSPSURF(plane), 0);
2760         else
2761                 I915_WRITE(DSPADDR(plane), 0);
2762         POSTING_READ(DSPCNTR(plane));
2763 }
2764
2765 static void ironlake_update_primary_plane(struct drm_plane *primary,
2766                                           const struct intel_crtc_state *crtc_state,
2767                                           const struct intel_plane_state *plane_state)
2768 {
2769         struct drm_device *dev = primary->dev;
2770         struct drm_i915_private *dev_priv = dev->dev_private;
2771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2772         struct drm_framebuffer *fb = plane_state->base.fb;
2773         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2774         int plane = intel_crtc->plane;
2775         u32 linear_offset;
2776         u32 dspcntr;
2777         i915_reg_t reg = DSPCNTR(plane);
2778         unsigned int rotation = plane_state->base.rotation;
2779         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2780         int x = plane_state->src.x1 >> 16;
2781         int y = plane_state->src.y1 >> 16;
2782
2783         dspcntr = DISPPLANE_GAMMA_ENABLE;
2784         dspcntr |= DISPLAY_PLANE_ENABLE;
2785
2786         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2787                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2788
2789         switch (fb->pixel_format) {
2790         case DRM_FORMAT_C8:
2791                 dspcntr |= DISPPLANE_8BPP;
2792                 break;
2793         case DRM_FORMAT_RGB565:
2794                 dspcntr |= DISPPLANE_BGRX565;
2795                 break;
2796         case DRM_FORMAT_XRGB8888:
2797                 dspcntr |= DISPPLANE_BGRX888;
2798                 break;
2799         case DRM_FORMAT_XBGR8888:
2800                 dspcntr |= DISPPLANE_RGBX888;
2801                 break;
2802         case DRM_FORMAT_XRGB2101010:
2803                 dspcntr |= DISPPLANE_BGRX101010;
2804                 break;
2805         case DRM_FORMAT_XBGR2101010:
2806                 dspcntr |= DISPPLANE_RGBX101010;
2807                 break;
2808         default:
2809                 BUG();
2810         }
2811
2812         if (obj->tiling_mode != I915_TILING_NONE)
2813                 dspcntr |= DISPPLANE_TILED;
2814
2815         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2816                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2817
2818         linear_offset = y * fb->pitches[0] + x * cpp;
2819         intel_crtc->dspaddr_offset =
2820                 intel_compute_tile_offset(&x, &y, fb, 0,
2821                                           fb->pitches[0], rotation);
2822         linear_offset -= intel_crtc->dspaddr_offset;
2823         if (rotation == BIT(DRM_ROTATE_180)) {
2824                 dspcntr |= DISPPLANE_ROTATE_180;
2825
2826                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2827                         x += (crtc_state->pipe_src_w - 1);
2828                         y += (crtc_state->pipe_src_h - 1);
2829
2830                         /* Finding the last pixel of the last line of the display
2831                         data and adding to linear_offset*/
2832                         linear_offset +=
2833                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2834                                 (crtc_state->pipe_src_w - 1) * cpp;
2835                 }
2836         }
2837
2838         intel_crtc->adjusted_x = x;
2839         intel_crtc->adjusted_y = y;
2840
2841         I915_WRITE(reg, dspcntr);
2842
2843         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2844         I915_WRITE(DSPSURF(plane),
2845                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2846         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2847                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2848         } else {
2849                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2850                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2851         }
2852         POSTING_READ(reg);
2853 }
2854
2855 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2856                               uint64_t fb_modifier, uint32_t pixel_format)
2857 {
2858         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2859                 return 64;
2860         } else {
2861                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2862
2863                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2864         }
2865 }
2866
2867 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2868                            struct drm_i915_gem_object *obj,
2869                            unsigned int plane)
2870 {
2871         struct i915_ggtt_view view;
2872         struct i915_vma *vma;
2873         u64 offset;
2874
2875         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2876                                 intel_plane->base.state->rotation);
2877
2878         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2879         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2880                 view.type))
2881                 return -1;
2882
2883         offset = vma->node.start;
2884
2885         if (plane == 1) {
2886                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2887                           PAGE_SIZE;
2888         }
2889
2890         WARN_ON(upper_32_bits(offset));
2891
2892         return lower_32_bits(offset);
2893 }
2894
2895 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2896 {
2897         struct drm_device *dev = intel_crtc->base.dev;
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899
2900         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2901         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2902         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2903 }
2904
2905 /*
2906  * This function detaches (aka. unbinds) unused scalers in hardware
2907  */
2908 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2909 {
2910         struct intel_crtc_scaler_state *scaler_state;
2911         int i;
2912
2913         scaler_state = &intel_crtc->config->scaler_state;
2914
2915         /* loop through and disable scalers that aren't in use */
2916         for (i = 0; i < intel_crtc->num_scalers; i++) {
2917                 if (!scaler_state->scalers[i].in_use)
2918                         skl_detach_scaler(intel_crtc, i);
2919         }
2920 }
2921
2922 u32 skl_plane_ctl_format(uint32_t pixel_format)
2923 {
2924         switch (pixel_format) {
2925         case DRM_FORMAT_C8:
2926                 return PLANE_CTL_FORMAT_INDEXED;
2927         case DRM_FORMAT_RGB565:
2928                 return PLANE_CTL_FORMAT_RGB_565;
2929         case DRM_FORMAT_XBGR8888:
2930                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2931         case DRM_FORMAT_XRGB8888:
2932                 return PLANE_CTL_FORMAT_XRGB_8888;
2933         /*
2934          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2935          * to be already pre-multiplied. We need to add a knob (or a different
2936          * DRM_FORMAT) for user-space to configure that.
2937          */
2938         case DRM_FORMAT_ABGR8888:
2939                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2940                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2941         case DRM_FORMAT_ARGB8888:
2942                 return PLANE_CTL_FORMAT_XRGB_8888 |
2943                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2944         case DRM_FORMAT_XRGB2101010:
2945                 return PLANE_CTL_FORMAT_XRGB_2101010;
2946         case DRM_FORMAT_XBGR2101010:
2947                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2948         case DRM_FORMAT_YUYV:
2949                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2950         case DRM_FORMAT_YVYU:
2951                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2952         case DRM_FORMAT_UYVY:
2953                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2954         case DRM_FORMAT_VYUY:
2955                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2956         default:
2957                 MISSING_CASE(pixel_format);
2958         }
2959
2960         return 0;
2961 }
2962
2963 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2964 {
2965         switch (fb_modifier) {
2966         case DRM_FORMAT_MOD_NONE:
2967                 break;
2968         case I915_FORMAT_MOD_X_TILED:
2969                 return PLANE_CTL_TILED_X;
2970         case I915_FORMAT_MOD_Y_TILED:
2971                 return PLANE_CTL_TILED_Y;
2972         case I915_FORMAT_MOD_Yf_TILED:
2973                 return PLANE_CTL_TILED_YF;
2974         default:
2975                 MISSING_CASE(fb_modifier);
2976         }
2977
2978         return 0;
2979 }
2980
2981 u32 skl_plane_ctl_rotation(unsigned int rotation)
2982 {
2983         switch (rotation) {
2984         case BIT(DRM_ROTATE_0):
2985                 break;
2986         /*
2987          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2988          * while i915 HW rotation is clockwise, thats why this swapping.
2989          */
2990         case BIT(DRM_ROTATE_90):
2991                 return PLANE_CTL_ROTATE_270;
2992         case BIT(DRM_ROTATE_180):
2993                 return PLANE_CTL_ROTATE_180;
2994         case BIT(DRM_ROTATE_270):
2995                 return PLANE_CTL_ROTATE_90;
2996         default:
2997                 MISSING_CASE(rotation);
2998         }
2999
3000         return 0;
3001 }
3002
3003 static void skylake_update_primary_plane(struct drm_plane *plane,
3004                                          const struct intel_crtc_state *crtc_state,
3005                                          const struct intel_plane_state *plane_state)
3006 {
3007         struct drm_device *dev = plane->dev;
3008         struct drm_i915_private *dev_priv = dev->dev_private;
3009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3010         struct drm_framebuffer *fb = plane_state->base.fb;
3011         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3012         int pipe = intel_crtc->pipe;
3013         u32 plane_ctl, stride_div, stride;
3014         u32 tile_height, plane_offset, plane_size;
3015         unsigned int rotation = plane_state->base.rotation;
3016         int x_offset, y_offset;
3017         u32 surf_addr;
3018         int scaler_id = plane_state->scaler_id;
3019         int src_x = plane_state->src.x1 >> 16;
3020         int src_y = plane_state->src.y1 >> 16;
3021         int src_w = drm_rect_width(&plane_state->src) >> 16;
3022         int src_h = drm_rect_height(&plane_state->src) >> 16;
3023         int dst_x = plane_state->dst.x1;
3024         int dst_y = plane_state->dst.y1;
3025         int dst_w = drm_rect_width(&plane_state->dst);
3026         int dst_h = drm_rect_height(&plane_state->dst);
3027
3028         plane_ctl = PLANE_CTL_ENABLE |
3029                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3030                     PLANE_CTL_PIPE_CSC_ENABLE;
3031
3032         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3033         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3034         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3035         plane_ctl |= skl_plane_ctl_rotation(rotation);
3036
3037         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3038                                                fb->pixel_format);
3039         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3040
3041         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3042
3043         if (intel_rotation_90_or_270(rotation)) {
3044                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3045
3046                 /* stride = Surface height in tiles */
3047                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3048                 stride = DIV_ROUND_UP(fb->height, tile_height);
3049                 x_offset = stride * tile_height - src_y - src_h;
3050                 y_offset = src_x;
3051                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3052         } else {
3053                 stride = fb->pitches[0] / stride_div;
3054                 x_offset = src_x;
3055                 y_offset = src_y;
3056                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3057         }
3058         plane_offset = y_offset << 16 | x_offset;
3059
3060         intel_crtc->adjusted_x = x_offset;
3061         intel_crtc->adjusted_y = y_offset;
3062
3063         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3064         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3065         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3066         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3067
3068         if (scaler_id >= 0) {
3069                 uint32_t ps_ctrl = 0;
3070
3071                 WARN_ON(!dst_w || !dst_h);
3072                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3073                         crtc_state->scaler_state.scalers[scaler_id].mode;
3074                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3075                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3076                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3077                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3078                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3079         } else {
3080                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3081         }
3082
3083         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3084
3085         POSTING_READ(PLANE_SURF(pipe, 0));
3086 }
3087
3088 static void skylake_disable_primary_plane(struct drm_plane *primary,
3089                                           struct drm_crtc *crtc)
3090 {
3091         struct drm_device *dev = crtc->dev;
3092         struct drm_i915_private *dev_priv = dev->dev_private;
3093         int pipe = to_intel_crtc(crtc)->pipe;
3094
3095         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3096         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3097         POSTING_READ(PLANE_SURF(pipe, 0));
3098 }
3099
3100 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3101 static int
3102 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3103                            int x, int y, enum mode_set_atomic state)
3104 {
3105         /* Support for kgdboc is disabled, this needs a major rework. */
3106         DRM_ERROR("legacy panic handler not supported any more.\n");
3107
3108         return -ENODEV;
3109 }
3110
3111 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3112 {
3113         struct drm_crtc *crtc;
3114
3115         for_each_crtc(dev_priv->dev, crtc) {
3116                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3117                 enum plane plane = intel_crtc->plane;
3118
3119                 intel_prepare_page_flip(dev_priv, plane);
3120                 intel_finish_page_flip_plane(dev_priv, plane);
3121         }
3122 }
3123
3124 static void intel_update_primary_planes(struct drm_device *dev)
3125 {
3126         struct drm_crtc *crtc;
3127
3128         for_each_crtc(dev, crtc) {
3129                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3130                 struct intel_plane_state *plane_state;
3131
3132                 drm_modeset_lock_crtc(crtc, &plane->base);
3133                 plane_state = to_intel_plane_state(plane->base.state);
3134
3135                 if (plane_state->visible)
3136                         plane->update_plane(&plane->base,
3137                                             to_intel_crtc_state(crtc->state),
3138                                             plane_state);
3139
3140                 drm_modeset_unlock_crtc(crtc);
3141         }
3142 }
3143
3144 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3145 {
3146         /* no reset support for gen2 */
3147         if (IS_GEN2(dev_priv))
3148                 return;
3149
3150         /* reset doesn't touch the display */
3151         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3152                 return;
3153
3154         drm_modeset_lock_all(dev_priv->dev);
3155         /*
3156          * Disabling the crtcs gracefully seems nicer. Also the
3157          * g33 docs say we should at least disable all the planes.
3158          */
3159         intel_display_suspend(dev_priv->dev);
3160 }
3161
3162 void intel_finish_reset(struct drm_i915_private *dev_priv)
3163 {
3164         /*
3165          * Flips in the rings will be nuked by the reset,
3166          * so complete all pending flips so that user space
3167          * will get its events and not get stuck.
3168          */
3169         intel_complete_page_flips(dev_priv);
3170
3171         /* no reset support for gen2 */
3172         if (IS_GEN2(dev_priv))
3173                 return;
3174
3175         /* reset doesn't touch the display */
3176         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3177                 /*
3178                  * Flips in the rings have been nuked by the reset,
3179                  * so update the base address of all primary
3180                  * planes to the the last fb to make sure we're
3181                  * showing the correct fb after a reset.
3182                  *
3183                  * FIXME: Atomic will make this obsolete since we won't schedule
3184                  * CS-based flips (which might get lost in gpu resets) any more.
3185                  */
3186                 intel_update_primary_planes(dev_priv->dev);
3187                 return;
3188         }
3189
3190         /*
3191          * The display has been reset as well,
3192          * so need a full re-initialization.
3193          */
3194         intel_runtime_pm_disable_interrupts(dev_priv);
3195         intel_runtime_pm_enable_interrupts(dev_priv);
3196
3197         intel_modeset_init_hw(dev_priv->dev);
3198
3199         spin_lock_irq(&dev_priv->irq_lock);
3200         if (dev_priv->display.hpd_irq_setup)
3201                 dev_priv->display.hpd_irq_setup(dev_priv);
3202         spin_unlock_irq(&dev_priv->irq_lock);
3203
3204         intel_display_resume(dev_priv->dev);
3205
3206         intel_hpd_init(dev_priv);
3207
3208         drm_modeset_unlock_all(dev_priv->dev);
3209 }
3210
3211 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3212 {
3213         struct drm_device *dev = crtc->dev;
3214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3215         unsigned reset_counter;
3216         bool pending;
3217
3218         reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3219         if (intel_crtc->reset_counter != reset_counter)
3220                 return false;
3221
3222         spin_lock_irq(&dev->event_lock);
3223         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3224         spin_unlock_irq(&dev->event_lock);
3225
3226         return pending;
3227 }
3228
3229 static void intel_update_pipe_config(struct intel_crtc *crtc,
3230                                      struct intel_crtc_state *old_crtc_state)
3231 {
3232         struct drm_device *dev = crtc->base.dev;
3233         struct drm_i915_private *dev_priv = dev->dev_private;
3234         struct intel_crtc_state *pipe_config =
3235                 to_intel_crtc_state(crtc->base.state);
3236
3237         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3238         crtc->base.mode = crtc->base.state->mode;
3239
3240         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3241                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3242                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3243
3244         /*
3245          * Update pipe size and adjust fitter if needed: the reason for this is
3246          * that in compute_mode_changes we check the native mode (not the pfit
3247          * mode) to see if we can flip rather than do a full mode set. In the
3248          * fastboot case, we'll flip, but if we don't update the pipesrc and
3249          * pfit state, we'll end up with a big fb scanned out into the wrong
3250          * sized surface.
3251          */
3252
3253         I915_WRITE(PIPESRC(crtc->pipe),
3254                    ((pipe_config->pipe_src_w - 1) << 16) |
3255                    (pipe_config->pipe_src_h - 1));
3256
3257         /* on skylake this is done by detaching scalers */
3258         if (INTEL_INFO(dev)->gen >= 9) {
3259                 skl_detach_scalers(crtc);
3260
3261                 if (pipe_config->pch_pfit.enabled)
3262                         skylake_pfit_enable(crtc);
3263         } else if (HAS_PCH_SPLIT(dev)) {
3264                 if (pipe_config->pch_pfit.enabled)
3265                         ironlake_pfit_enable(crtc);
3266                 else if (old_crtc_state->pch_pfit.enabled)
3267                         ironlake_pfit_disable(crtc, true);
3268         }
3269 }
3270
3271 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3272 {
3273         struct drm_device *dev = crtc->dev;
3274         struct drm_i915_private *dev_priv = dev->dev_private;
3275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3276         int pipe = intel_crtc->pipe;
3277         i915_reg_t reg;
3278         u32 temp;
3279
3280         /* enable normal train */
3281         reg = FDI_TX_CTL(pipe);
3282         temp = I915_READ(reg);
3283         if (IS_IVYBRIDGE(dev)) {
3284                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3285                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3286         } else {
3287                 temp &= ~FDI_LINK_TRAIN_NONE;
3288                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3289         }
3290         I915_WRITE(reg, temp);
3291
3292         reg = FDI_RX_CTL(pipe);
3293         temp = I915_READ(reg);
3294         if (HAS_PCH_CPT(dev)) {
3295                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3296                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3297         } else {
3298                 temp &= ~FDI_LINK_TRAIN_NONE;
3299                 temp |= FDI_LINK_TRAIN_NONE;
3300         }
3301         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3302
3303         /* wait one idle pattern time */
3304         POSTING_READ(reg);
3305         udelay(1000);
3306
3307         /* IVB wants error correction enabled */
3308         if (IS_IVYBRIDGE(dev))
3309                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3310                            FDI_FE_ERRC_ENABLE);
3311 }
3312
3313 /* The FDI link training functions for ILK/Ibexpeak. */
3314 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3315 {
3316         struct drm_device *dev = crtc->dev;
3317         struct drm_i915_private *dev_priv = dev->dev_private;
3318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3319         int pipe = intel_crtc->pipe;
3320         i915_reg_t reg;
3321         u32 temp, tries;
3322
3323         /* FDI needs bits from pipe first */
3324         assert_pipe_enabled(dev_priv, pipe);
3325
3326         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3327            for train result */
3328         reg = FDI_RX_IMR(pipe);
3329         temp = I915_READ(reg);
3330         temp &= ~FDI_RX_SYMBOL_LOCK;
3331         temp &= ~FDI_RX_BIT_LOCK;
3332         I915_WRITE(reg, temp);
3333         I915_READ(reg);
3334         udelay(150);
3335
3336         /* enable CPU FDI TX and PCH FDI RX */
3337         reg = FDI_TX_CTL(pipe);
3338         temp = I915_READ(reg);
3339         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3340         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3341         temp &= ~FDI_LINK_TRAIN_NONE;
3342         temp |= FDI_LINK_TRAIN_PATTERN_1;
3343         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3344
3345         reg = FDI_RX_CTL(pipe);
3346         temp = I915_READ(reg);
3347         temp &= ~FDI_LINK_TRAIN_NONE;
3348         temp |= FDI_LINK_TRAIN_PATTERN_1;
3349         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3350
3351         POSTING_READ(reg);
3352         udelay(150);
3353
3354         /* Ironlake workaround, enable clock pointer after FDI enable*/
3355         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3356         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3357                    FDI_RX_PHASE_SYNC_POINTER_EN);
3358
3359         reg = FDI_RX_IIR(pipe);
3360         for (tries = 0; tries < 5; tries++) {
3361                 temp = I915_READ(reg);
3362                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3363
3364                 if ((temp & FDI_RX_BIT_LOCK)) {
3365                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3366                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3367                         break;
3368                 }
3369         }
3370         if (tries == 5)
3371                 DRM_ERROR("FDI train 1 fail!\n");
3372
3373         /* Train 2 */
3374         reg = FDI_TX_CTL(pipe);
3375         temp = I915_READ(reg);
3376         temp &= ~FDI_LINK_TRAIN_NONE;
3377         temp |= FDI_LINK_TRAIN_PATTERN_2;
3378         I915_WRITE(reg, temp);
3379
3380         reg = FDI_RX_CTL(pipe);
3381         temp = I915_READ(reg);
3382         temp &= ~FDI_LINK_TRAIN_NONE;
3383         temp |= FDI_LINK_TRAIN_PATTERN_2;
3384         I915_WRITE(reg, temp);
3385
3386         POSTING_READ(reg);
3387         udelay(150);
3388
3389         reg = FDI_RX_IIR(pipe);
3390         for (tries = 0; tries < 5; tries++) {
3391                 temp = I915_READ(reg);
3392                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3393
3394                 if (temp & FDI_RX_SYMBOL_LOCK) {
3395                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3396                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3397                         break;
3398                 }
3399         }
3400         if (tries == 5)
3401                 DRM_ERROR("FDI train 2 fail!\n");
3402
3403         DRM_DEBUG_KMS("FDI train done\n");
3404
3405 }
3406
3407 static const int snb_b_fdi_train_param[] = {
3408         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3409         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3410         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3411         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3412 };
3413
3414 /* The FDI link training functions for SNB/Cougarpoint. */
3415 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3416 {
3417         struct drm_device *dev = crtc->dev;
3418         struct drm_i915_private *dev_priv = dev->dev_private;
3419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3420         int pipe = intel_crtc->pipe;
3421         i915_reg_t reg;
3422         u32 temp, i, retry;
3423
3424         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3425            for train result */
3426         reg = FDI_RX_IMR(pipe);
3427         temp = I915_READ(reg);
3428         temp &= ~FDI_RX_SYMBOL_LOCK;
3429         temp &= ~FDI_RX_BIT_LOCK;
3430         I915_WRITE(reg, temp);
3431
3432         POSTING_READ(reg);
3433         udelay(150);
3434
3435         /* enable CPU FDI TX and PCH FDI RX */
3436         reg = FDI_TX_CTL(pipe);
3437         temp = I915_READ(reg);
3438         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3439         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3440         temp &= ~FDI_LINK_TRAIN_NONE;
3441         temp |= FDI_LINK_TRAIN_PATTERN_1;
3442         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3443         /* SNB-B */
3444         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3445         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3446
3447         I915_WRITE(FDI_RX_MISC(pipe),
3448                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3449
3450         reg = FDI_RX_CTL(pipe);
3451         temp = I915_READ(reg);
3452         if (HAS_PCH_CPT(dev)) {
3453                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3454                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3455         } else {
3456                 temp &= ~FDI_LINK_TRAIN_NONE;
3457                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3458         }
3459         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3460
3461         POSTING_READ(reg);
3462         udelay(150);
3463
3464         for (i = 0; i < 4; i++) {
3465                 reg = FDI_TX_CTL(pipe);
3466                 temp = I915_READ(reg);
3467                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3468                 temp |= snb_b_fdi_train_param[i];
3469                 I915_WRITE(reg, temp);
3470
3471                 POSTING_READ(reg);
3472                 udelay(500);
3473
3474                 for (retry = 0; retry < 5; retry++) {
3475                         reg = FDI_RX_IIR(pipe);
3476                         temp = I915_READ(reg);
3477                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3478                         if (temp & FDI_RX_BIT_LOCK) {
3479                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3480                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3481                                 break;
3482                         }
3483                         udelay(50);
3484                 }
3485                 if (retry < 5)
3486                         break;
3487         }
3488         if (i == 4)
3489                 DRM_ERROR("FDI train 1 fail!\n");
3490
3491         /* Train 2 */
3492         reg = FDI_TX_CTL(pipe);
3493         temp = I915_READ(reg);
3494         temp &= ~FDI_LINK_TRAIN_NONE;
3495         temp |= FDI_LINK_TRAIN_PATTERN_2;
3496         if (IS_GEN6(dev)) {
3497                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3498                 /* SNB-B */
3499                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3500         }
3501         I915_WRITE(reg, temp);
3502
3503         reg = FDI_RX_CTL(pipe);
3504         temp = I915_READ(reg);
3505         if (HAS_PCH_CPT(dev)) {
3506                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3507                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3508         } else {
3509                 temp &= ~FDI_LINK_TRAIN_NONE;
3510                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3511         }
3512         I915_WRITE(reg, temp);
3513
3514         POSTING_READ(reg);
3515         udelay(150);
3516
3517         for (i = 0; i < 4; i++) {
3518                 reg = FDI_TX_CTL(pipe);
3519                 temp = I915_READ(reg);
3520                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3521                 temp |= snb_b_fdi_train_param[i];
3522                 I915_WRITE(reg, temp);
3523
3524                 POSTING_READ(reg);
3525                 udelay(500);
3526
3527                 for (retry = 0; retry < 5; retry++) {
3528                         reg = FDI_RX_IIR(pipe);
3529                         temp = I915_READ(reg);
3530                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3531                         if (temp & FDI_RX_SYMBOL_LOCK) {
3532                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3533                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3534                                 break;
3535                         }
3536                         udelay(50);
3537                 }
3538                 if (retry < 5)
3539                         break;
3540         }
3541         if (i == 4)
3542                 DRM_ERROR("FDI train 2 fail!\n");
3543
3544         DRM_DEBUG_KMS("FDI train done.\n");
3545 }
3546
3547 /* Manual link training for Ivy Bridge A0 parts */
3548 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3549 {
3550         struct drm_device *dev = crtc->dev;
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553         int pipe = intel_crtc->pipe;
3554         i915_reg_t reg;
3555         u32 temp, i, j;
3556
3557         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3558            for train result */
3559         reg = FDI_RX_IMR(pipe);
3560         temp = I915_READ(reg);
3561         temp &= ~FDI_RX_SYMBOL_LOCK;
3562         temp &= ~FDI_RX_BIT_LOCK;
3563         I915_WRITE(reg, temp);
3564
3565         POSTING_READ(reg);
3566         udelay(150);
3567
3568         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3569                       I915_READ(FDI_RX_IIR(pipe)));
3570
3571         /* Try each vswing and preemphasis setting twice before moving on */
3572         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3573                 /* disable first in case we need to retry */
3574                 reg = FDI_TX_CTL(pipe);
3575                 temp = I915_READ(reg);
3576                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3577                 temp &= ~FDI_TX_ENABLE;
3578                 I915_WRITE(reg, temp);
3579
3580                 reg = FDI_RX_CTL(pipe);
3581                 temp = I915_READ(reg);
3582                 temp &= ~FDI_LINK_TRAIN_AUTO;
3583                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3584                 temp &= ~FDI_RX_ENABLE;
3585                 I915_WRITE(reg, temp);
3586
3587                 /* enable CPU FDI TX and PCH FDI RX */
3588                 reg = FDI_TX_CTL(pipe);
3589                 temp = I915_READ(reg);
3590                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3591                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3592                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3593                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3594                 temp |= snb_b_fdi_train_param[j/2];
3595                 temp |= FDI_COMPOSITE_SYNC;
3596                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3597
3598                 I915_WRITE(FDI_RX_MISC(pipe),
3599                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3600
3601                 reg = FDI_RX_CTL(pipe);
3602                 temp = I915_READ(reg);
3603                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3604                 temp |= FDI_COMPOSITE_SYNC;
3605                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3606
3607                 POSTING_READ(reg);
3608                 udelay(1); /* should be 0.5us */
3609
3610                 for (i = 0; i < 4; i++) {
3611                         reg = FDI_RX_IIR(pipe);
3612                         temp = I915_READ(reg);
3613                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3614
3615                         if (temp & FDI_RX_BIT_LOCK ||
3616                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3617                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3618                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3619                                               i);
3620                                 break;
3621                         }
3622                         udelay(1); /* should be 0.5us */
3623                 }
3624                 if (i == 4) {
3625                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3626                         continue;
3627                 }
3628
3629                 /* Train 2 */
3630                 reg = FDI_TX_CTL(pipe);
3631                 temp = I915_READ(reg);
3632                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3633                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3634                 I915_WRITE(reg, temp);
3635
3636                 reg = FDI_RX_CTL(pipe);
3637                 temp = I915_READ(reg);
3638                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3639                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3640                 I915_WRITE(reg, temp);
3641
3642                 POSTING_READ(reg);
3643                 udelay(2); /* should be 1.5us */
3644
3645                 for (i = 0; i < 4; i++) {
3646                         reg = FDI_RX_IIR(pipe);
3647                         temp = I915_READ(reg);
3648                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3649
3650                         if (temp & FDI_RX_SYMBOL_LOCK ||
3651                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3652                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3653                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3654                                               i);
3655                                 goto train_done;
3656                         }
3657                         udelay(2); /* should be 1.5us */
3658                 }
3659                 if (i == 4)
3660                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3661         }
3662
3663 train_done:
3664         DRM_DEBUG_KMS("FDI train done.\n");
3665 }
3666
3667 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3668 {
3669         struct drm_device *dev = intel_crtc->base.dev;
3670         struct drm_i915_private *dev_priv = dev->dev_private;
3671         int pipe = intel_crtc->pipe;
3672         i915_reg_t reg;
3673         u32 temp;
3674
3675         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3676         reg = FDI_RX_CTL(pipe);
3677         temp = I915_READ(reg);
3678         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3679         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3680         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3681         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3682
3683         POSTING_READ(reg);
3684         udelay(200);
3685
3686         /* Switch from Rawclk to PCDclk */
3687         temp = I915_READ(reg);
3688         I915_WRITE(reg, temp | FDI_PCDCLK);
3689
3690         POSTING_READ(reg);
3691         udelay(200);
3692
3693         /* Enable CPU FDI TX PLL, always on for Ironlake */
3694         reg = FDI_TX_CTL(pipe);
3695         temp = I915_READ(reg);
3696         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3697                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3698
3699                 POSTING_READ(reg);
3700                 udelay(100);
3701         }
3702 }
3703
3704 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3705 {
3706         struct drm_device *dev = intel_crtc->base.dev;
3707         struct drm_i915_private *dev_priv = dev->dev_private;
3708         int pipe = intel_crtc->pipe;
3709         i915_reg_t reg;
3710         u32 temp;
3711
3712         /* Switch from PCDclk to Rawclk */
3713         reg = FDI_RX_CTL(pipe);
3714         temp = I915_READ(reg);
3715         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3716
3717         /* Disable CPU FDI TX PLL */
3718         reg = FDI_TX_CTL(pipe);
3719         temp = I915_READ(reg);
3720         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3721
3722         POSTING_READ(reg);
3723         udelay(100);
3724
3725         reg = FDI_RX_CTL(pipe);
3726         temp = I915_READ(reg);
3727         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3728
3729         /* Wait for the clocks to turn off. */
3730         POSTING_READ(reg);
3731         udelay(100);
3732 }
3733
3734 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3735 {
3736         struct drm_device *dev = crtc->dev;
3737         struct drm_i915_private *dev_priv = dev->dev_private;
3738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3739         int pipe = intel_crtc->pipe;
3740         i915_reg_t reg;
3741         u32 temp;
3742
3743         /* disable CPU FDI tx and PCH FDI rx */
3744         reg = FDI_TX_CTL(pipe);
3745         temp = I915_READ(reg);
3746         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3747         POSTING_READ(reg);
3748
3749         reg = FDI_RX_CTL(pipe);
3750         temp = I915_READ(reg);
3751         temp &= ~(0x7 << 16);
3752         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3753         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3754
3755         POSTING_READ(reg);
3756         udelay(100);
3757
3758         /* Ironlake workaround, disable clock pointer after downing FDI */
3759         if (HAS_PCH_IBX(dev))
3760                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3761
3762         /* still set train pattern 1 */
3763         reg = FDI_TX_CTL(pipe);
3764         temp = I915_READ(reg);
3765         temp &= ~FDI_LINK_TRAIN_NONE;
3766         temp |= FDI_LINK_TRAIN_PATTERN_1;
3767         I915_WRITE(reg, temp);
3768
3769         reg = FDI_RX_CTL(pipe);
3770         temp = I915_READ(reg);
3771         if (HAS_PCH_CPT(dev)) {
3772                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3773                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3774         } else {
3775                 temp &= ~FDI_LINK_TRAIN_NONE;
3776                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3777         }
3778         /* BPC in FDI rx is consistent with that in PIPECONF */
3779         temp &= ~(0x07 << 16);
3780         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3781         I915_WRITE(reg, temp);
3782
3783         POSTING_READ(reg);
3784         udelay(100);
3785 }
3786
3787 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3788 {
3789         struct intel_crtc *crtc;
3790
3791         /* Note that we don't need to be called with mode_config.lock here
3792          * as our list of CRTC objects is static for the lifetime of the
3793          * device and so cannot disappear as we iterate. Similarly, we can
3794          * happily treat the predicates as racy, atomic checks as userspace
3795          * cannot claim and pin a new fb without at least acquring the
3796          * struct_mutex and so serialising with us.
3797          */
3798         for_each_intel_crtc(dev, crtc) {
3799                 if (atomic_read(&crtc->unpin_work_count) == 0)
3800                         continue;
3801
3802                 if (crtc->unpin_work)
3803                         intel_wait_for_vblank(dev, crtc->pipe);
3804
3805                 return true;
3806         }
3807
3808         return false;
3809 }
3810
3811 static void page_flip_completed(struct intel_crtc *intel_crtc)
3812 {
3813         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3814         struct intel_unpin_work *work = intel_crtc->unpin_work;
3815
3816         /* ensure that the unpin work is consistent wrt ->pending. */
3817         smp_rmb();
3818         intel_crtc->unpin_work = NULL;
3819
3820         if (work->event)
3821                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3822
3823         drm_crtc_vblank_put(&intel_crtc->base);
3824
3825         wake_up_all(&dev_priv->pending_flip_queue);
3826         queue_work(dev_priv->wq, &work->work);
3827
3828         trace_i915_flip_complete(intel_crtc->plane,
3829                                  work->pending_flip_obj);
3830 }
3831
3832 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3833 {
3834         struct drm_device *dev = crtc->dev;
3835         struct drm_i915_private *dev_priv = dev->dev_private;
3836         long ret;
3837
3838         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3839
3840         ret = wait_event_interruptible_timeout(
3841                                         dev_priv->pending_flip_queue,
3842                                         !intel_crtc_has_pending_flip(crtc),
3843                                         60*HZ);
3844
3845         if (ret < 0)
3846                 return ret;
3847
3848         if (ret == 0) {
3849                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3850
3851                 spin_lock_irq(&dev->event_lock);
3852                 if (intel_crtc->unpin_work) {
3853                         WARN_ONCE(1, "Removing stuck page flip\n");
3854                         page_flip_completed(intel_crtc);
3855                 }
3856                 spin_unlock_irq(&dev->event_lock);
3857         }
3858
3859         return 0;
3860 }
3861
3862 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3863 {
3864         u32 temp;
3865
3866         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3867
3868         mutex_lock(&dev_priv->sb_lock);
3869
3870         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3871         temp |= SBI_SSCCTL_DISABLE;
3872         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3873
3874         mutex_unlock(&dev_priv->sb_lock);
3875 }
3876
3877 /* Program iCLKIP clock to the desired frequency */
3878 static void lpt_program_iclkip(struct drm_crtc *crtc)
3879 {
3880         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3881         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3882         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3883         u32 temp;
3884
3885         lpt_disable_iclkip(dev_priv);
3886
3887         /* The iCLK virtual clock root frequency is in MHz,
3888          * but the adjusted_mode->crtc_clock in in KHz. To get the
3889          * divisors, it is necessary to divide one by another, so we
3890          * convert the virtual clock precision to KHz here for higher
3891          * precision.
3892          */
3893         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3894                 u32 iclk_virtual_root_freq = 172800 * 1000;
3895                 u32 iclk_pi_range = 64;
3896                 u32 desired_divisor;
3897
3898                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3899                                                     clock << auxdiv);
3900                 divsel = (desired_divisor / iclk_pi_range) - 2;
3901                 phaseinc = desired_divisor % iclk_pi_range;
3902
3903                 /*
3904                  * Near 20MHz is a corner case which is
3905                  * out of range for the 7-bit divisor
3906                  */
3907                 if (divsel <= 0x7f)
3908                         break;
3909         }
3910
3911         /* This should not happen with any sane values */
3912         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3913                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3914         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3915                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3916
3917         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3918                         clock,
3919                         auxdiv,
3920                         divsel,
3921                         phasedir,
3922                         phaseinc);
3923
3924         mutex_lock(&dev_priv->sb_lock);
3925
3926         /* Program SSCDIVINTPHASE6 */
3927         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3928         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3929         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3930         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3931         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3932         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3933         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3934         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3935
3936         /* Program SSCAUXDIV */
3937         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3938         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3939         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3940         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3941
3942         /* Enable modulator and associated divider */
3943         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3944         temp &= ~SBI_SSCCTL_DISABLE;
3945         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3946
3947         mutex_unlock(&dev_priv->sb_lock);
3948
3949         /* Wait for initialization time */
3950         udelay(24);
3951
3952         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3953 }
3954
3955 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3956 {
3957         u32 divsel, phaseinc, auxdiv;
3958         u32 iclk_virtual_root_freq = 172800 * 1000;
3959         u32 iclk_pi_range = 64;
3960         u32 desired_divisor;
3961         u32 temp;
3962
3963         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3964                 return 0;
3965
3966         mutex_lock(&dev_priv->sb_lock);
3967
3968         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3969         if (temp & SBI_SSCCTL_DISABLE) {
3970                 mutex_unlock(&dev_priv->sb_lock);
3971                 return 0;
3972         }
3973
3974         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3975         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3976                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3977         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3978                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3979
3980         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3981         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3982                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3983
3984         mutex_unlock(&dev_priv->sb_lock);
3985
3986         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3987
3988         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3989                                  desired_divisor << auxdiv);
3990 }
3991
3992 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3993                                                 enum pipe pch_transcoder)
3994 {
3995         struct drm_device *dev = crtc->base.dev;
3996         struct drm_i915_private *dev_priv = dev->dev_private;
3997         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3998
3999         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4000                    I915_READ(HTOTAL(cpu_transcoder)));
4001         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4002                    I915_READ(HBLANK(cpu_transcoder)));
4003         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4004                    I915_READ(HSYNC(cpu_transcoder)));
4005
4006         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4007                    I915_READ(VTOTAL(cpu_transcoder)));
4008         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4009                    I915_READ(VBLANK(cpu_transcoder)));
4010         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4011                    I915_READ(VSYNC(cpu_transcoder)));
4012         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4013                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4014 }
4015
4016 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4017 {
4018         struct drm_i915_private *dev_priv = dev->dev_private;
4019         uint32_t temp;
4020
4021         temp = I915_READ(SOUTH_CHICKEN1);
4022         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4023                 return;
4024
4025         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4026         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4027
4028         temp &= ~FDI_BC_BIFURCATION_SELECT;
4029         if (enable)
4030                 temp |= FDI_BC_BIFURCATION_SELECT;
4031
4032         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4033         I915_WRITE(SOUTH_CHICKEN1, temp);
4034         POSTING_READ(SOUTH_CHICKEN1);
4035 }
4036
4037 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4038 {
4039         struct drm_device *dev = intel_crtc->base.dev;
4040
4041         switch (intel_crtc->pipe) {
4042         case PIPE_A:
4043                 break;
4044         case PIPE_B:
4045                 if (intel_crtc->config->fdi_lanes > 2)
4046                         cpt_set_fdi_bc_bifurcation(dev, false);
4047                 else
4048                         cpt_set_fdi_bc_bifurcation(dev, true);
4049
4050                 break;
4051         case PIPE_C:
4052                 cpt_set_fdi_bc_bifurcation(dev, true);
4053
4054                 break;
4055         default:
4056                 BUG();
4057         }
4058 }
4059
4060 /* Return which DP Port should be selected for Transcoder DP control */
4061 static enum port
4062 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4063 {
4064         struct drm_device *dev = crtc->dev;
4065         struct intel_encoder *encoder;
4066
4067         for_each_encoder_on_crtc(dev, crtc, encoder) {
4068                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4069                     encoder->type == INTEL_OUTPUT_EDP)
4070                         return enc_to_dig_port(&encoder->base)->port;
4071         }
4072
4073         return -1;
4074 }
4075
4076 /*
4077  * Enable PCH resources required for PCH ports:
4078  *   - PCH PLLs
4079  *   - FDI training & RX/TX
4080  *   - update transcoder timings
4081  *   - DP transcoding bits
4082  *   - transcoder
4083  */
4084 static void ironlake_pch_enable(struct drm_crtc *crtc)
4085 {
4086         struct drm_device *dev = crtc->dev;
4087         struct drm_i915_private *dev_priv = dev->dev_private;
4088         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4089         int pipe = intel_crtc->pipe;
4090         u32 temp;
4091
4092         assert_pch_transcoder_disabled(dev_priv, pipe);
4093
4094         if (IS_IVYBRIDGE(dev))
4095                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4096
4097         /* Write the TU size bits before fdi link training, so that error
4098          * detection works. */
4099         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4100                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4101
4102         /* For PCH output, training FDI link */
4103         dev_priv->display.fdi_link_train(crtc);
4104
4105         /* We need to program the right clock selection before writing the pixel
4106          * mutliplier into the DPLL. */
4107         if (HAS_PCH_CPT(dev)) {
4108                 u32 sel;
4109
4110                 temp = I915_READ(PCH_DPLL_SEL);
4111                 temp |= TRANS_DPLL_ENABLE(pipe);
4112                 sel = TRANS_DPLLB_SEL(pipe);
4113                 if (intel_crtc->config->shared_dpll ==
4114                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4115                         temp |= sel;
4116                 else
4117                         temp &= ~sel;
4118                 I915_WRITE(PCH_DPLL_SEL, temp);
4119         }
4120
4121         /* XXX: pch pll's can be enabled any time before we enable the PCH
4122          * transcoder, and we actually should do this to not upset any PCH
4123          * transcoder that already use the clock when we share it.
4124          *
4125          * Note that enable_shared_dpll tries to do the right thing, but
4126          * get_shared_dpll unconditionally resets the pll - we need that to have
4127          * the right LVDS enable sequence. */
4128         intel_enable_shared_dpll(intel_crtc);
4129
4130         /* set transcoder timing, panel must allow it */
4131         assert_panel_unlocked(dev_priv, pipe);
4132         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4133
4134         intel_fdi_normal_train(crtc);
4135
4136         /* For PCH DP, enable TRANS_DP_CTL */
4137         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4138                 const struct drm_display_mode *adjusted_mode =
4139                         &intel_crtc->config->base.adjusted_mode;
4140                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4141                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4142                 temp = I915_READ(reg);
4143                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4144                           TRANS_DP_SYNC_MASK |
4145                           TRANS_DP_BPC_MASK);
4146                 temp |= TRANS_DP_OUTPUT_ENABLE;
4147                 temp |= bpc << 9; /* same format but at 11:9 */
4148
4149                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4150                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4151                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4152                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4153
4154                 switch (intel_trans_dp_port_sel(crtc)) {
4155                 case PORT_B:
4156                         temp |= TRANS_DP_PORT_SEL_B;
4157                         break;
4158                 case PORT_C:
4159                         temp |= TRANS_DP_PORT_SEL_C;
4160                         break;
4161                 case PORT_D:
4162                         temp |= TRANS_DP_PORT_SEL_D;
4163                         break;
4164                 default:
4165                         BUG();
4166                 }
4167
4168                 I915_WRITE(reg, temp);
4169         }
4170
4171         ironlake_enable_pch_transcoder(dev_priv, pipe);
4172 }
4173
4174 static void lpt_pch_enable(struct drm_crtc *crtc)
4175 {
4176         struct drm_device *dev = crtc->dev;
4177         struct drm_i915_private *dev_priv = dev->dev_private;
4178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4179         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4180
4181         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4182
4183         lpt_program_iclkip(crtc);
4184
4185         /* Set transcoder timing. */
4186         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4187
4188         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4189 }
4190
4191 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4192 {
4193         struct drm_i915_private *dev_priv = dev->dev_private;
4194         i915_reg_t dslreg = PIPEDSL(pipe);
4195         u32 temp;
4196
4197         temp = I915_READ(dslreg);
4198         udelay(500);
4199         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4200                 if (wait_for(I915_READ(dslreg) != temp, 5))
4201                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4202         }
4203 }
4204
4205 static int
4206 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4207                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4208                   int src_w, int src_h, int dst_w, int dst_h)
4209 {
4210         struct intel_crtc_scaler_state *scaler_state =
4211                 &crtc_state->scaler_state;
4212         struct intel_crtc *intel_crtc =
4213                 to_intel_crtc(crtc_state->base.crtc);
4214         int need_scaling;
4215
4216         need_scaling = intel_rotation_90_or_270(rotation) ?
4217                 (src_h != dst_w || src_w != dst_h):
4218                 (src_w != dst_w || src_h != dst_h);
4219
4220         /*
4221          * if plane is being disabled or scaler is no more required or force detach
4222          *  - free scaler binded to this plane/crtc
4223          *  - in order to do this, update crtc->scaler_usage
4224          *
4225          * Here scaler state in crtc_state is set free so that
4226          * scaler can be assigned to other user. Actual register
4227          * update to free the scaler is done in plane/panel-fit programming.
4228          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4229          */
4230         if (force_detach || !need_scaling) {
4231                 if (*scaler_id >= 0) {
4232                         scaler_state->scaler_users &= ~(1 << scaler_user);
4233                         scaler_state->scalers[*scaler_id].in_use = 0;
4234
4235                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4236                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4237                                 intel_crtc->pipe, scaler_user, *scaler_id,
4238                                 scaler_state->scaler_users);
4239                         *scaler_id = -1;
4240                 }
4241                 return 0;
4242         }
4243
4244         /* range checks */
4245         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4246                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4247
4248                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4249                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4250                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4251                         "size is out of scaler range\n",
4252                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4253                 return -EINVAL;
4254         }
4255
4256         /* mark this plane as a scaler user in crtc_state */
4257         scaler_state->scaler_users |= (1 << scaler_user);
4258         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4259                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4260                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4261                 scaler_state->scaler_users);
4262
4263         return 0;
4264 }
4265
4266 /**
4267  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4268  *
4269  * @state: crtc's scaler state
4270  *
4271  * Return
4272  *     0 - scaler_usage updated successfully
4273  *    error - requested scaling cannot be supported or other error condition
4274  */
4275 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4276 {
4277         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4278         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4279
4280         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4281                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4282
4283         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4284                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4285                 state->pipe_src_w, state->pipe_src_h,
4286                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4287 }
4288
4289 /**
4290  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4291  *
4292  * @state: crtc's scaler state
4293  * @plane_state: atomic plane state to update
4294  *
4295  * Return
4296  *     0 - scaler_usage updated successfully
4297  *    error - requested scaling cannot be supported or other error condition
4298  */
4299 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4300                                    struct intel_plane_state *plane_state)
4301 {
4302
4303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4304         struct intel_plane *intel_plane =
4305                 to_intel_plane(plane_state->base.plane);
4306         struct drm_framebuffer *fb = plane_state->base.fb;
4307         int ret;
4308
4309         bool force_detach = !fb || !plane_state->visible;
4310
4311         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4312                       intel_plane->base.base.id, intel_crtc->pipe,
4313                       drm_plane_index(&intel_plane->base));
4314
4315         ret = skl_update_scaler(crtc_state, force_detach,
4316                                 drm_plane_index(&intel_plane->base),
4317                                 &plane_state->scaler_id,
4318                                 plane_state->base.rotation,
4319                                 drm_rect_width(&plane_state->src) >> 16,
4320                                 drm_rect_height(&plane_state->src) >> 16,
4321                                 drm_rect_width(&plane_state->dst),
4322                                 drm_rect_height(&plane_state->dst));
4323
4324         if (ret || plane_state->scaler_id < 0)
4325                 return ret;
4326
4327         /* check colorkey */
4328         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4329                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4330                               intel_plane->base.base.id);
4331                 return -EINVAL;
4332         }
4333
4334         /* Check src format */
4335         switch (fb->pixel_format) {
4336         case DRM_FORMAT_RGB565:
4337         case DRM_FORMAT_XBGR8888:
4338         case DRM_FORMAT_XRGB8888:
4339         case DRM_FORMAT_ABGR8888:
4340         case DRM_FORMAT_ARGB8888:
4341         case DRM_FORMAT_XRGB2101010:
4342         case DRM_FORMAT_XBGR2101010:
4343         case DRM_FORMAT_YUYV:
4344         case DRM_FORMAT_YVYU:
4345         case DRM_FORMAT_UYVY:
4346         case DRM_FORMAT_VYUY:
4347                 break;
4348         default:
4349                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4350                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4351                 return -EINVAL;
4352         }
4353
4354         return 0;
4355 }
4356
4357 static void skylake_scaler_disable(struct intel_crtc *crtc)
4358 {
4359         int i;
4360
4361         for (i = 0; i < crtc->num_scalers; i++)
4362                 skl_detach_scaler(crtc, i);
4363 }
4364
4365 static void skylake_pfit_enable(struct intel_crtc *crtc)
4366 {
4367         struct drm_device *dev = crtc->base.dev;
4368         struct drm_i915_private *dev_priv = dev->dev_private;
4369         int pipe = crtc->pipe;
4370         struct intel_crtc_scaler_state *scaler_state =
4371                 &crtc->config->scaler_state;
4372
4373         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4374
4375         if (crtc->config->pch_pfit.enabled) {
4376                 int id;
4377
4378                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4379                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4380                         return;
4381                 }
4382
4383                 id = scaler_state->scaler_id;
4384                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4385                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4386                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4387                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4388
4389                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4390         }
4391 }
4392
4393 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4394 {
4395         struct drm_device *dev = crtc->base.dev;
4396         struct drm_i915_private *dev_priv = dev->dev_private;
4397         int pipe = crtc->pipe;
4398
4399         if (crtc->config->pch_pfit.enabled) {
4400                 /* Force use of hard-coded filter coefficients
4401                  * as some pre-programmed values are broken,
4402                  * e.g. x201.
4403                  */
4404                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4405                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4406                                                  PF_PIPE_SEL_IVB(pipe));
4407                 else
4408                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4409                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4410                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4411         }
4412 }
4413
4414 void hsw_enable_ips(struct intel_crtc *crtc)
4415 {
4416         struct drm_device *dev = crtc->base.dev;
4417         struct drm_i915_private *dev_priv = dev->dev_private;
4418
4419         if (!crtc->config->ips_enabled)
4420                 return;
4421
4422         /*
4423          * We can only enable IPS after we enable a plane and wait for a vblank
4424          * This function is called from post_plane_update, which is run after
4425          * a vblank wait.
4426          */
4427
4428         assert_plane_enabled(dev_priv, crtc->plane);
4429         if (IS_BROADWELL(dev)) {
4430                 mutex_lock(&dev_priv->rps.hw_lock);
4431                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4432                 mutex_unlock(&dev_priv->rps.hw_lock);
4433                 /* Quoting Art Runyan: "its not safe to expect any particular
4434                  * value in IPS_CTL bit 31 after enabling IPS through the
4435                  * mailbox." Moreover, the mailbox may return a bogus state,
4436                  * so we need to just enable it and continue on.
4437                  */
4438         } else {
4439                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4440                 /* The bit only becomes 1 in the next vblank, so this wait here
4441                  * is essentially intel_wait_for_vblank. If we don't have this
4442                  * and don't wait for vblanks until the end of crtc_enable, then
4443                  * the HW state readout code will complain that the expected
4444                  * IPS_CTL value is not the one we read. */
4445                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4446                         DRM_ERROR("Timed out waiting for IPS enable\n");
4447         }
4448 }
4449
4450 void hsw_disable_ips(struct intel_crtc *crtc)
4451 {
4452         struct drm_device *dev = crtc->base.dev;
4453         struct drm_i915_private *dev_priv = dev->dev_private;
4454
4455         if (!crtc->config->ips_enabled)
4456                 return;
4457
4458         assert_plane_enabled(dev_priv, crtc->plane);
4459         if (IS_BROADWELL(dev)) {
4460                 mutex_lock(&dev_priv->rps.hw_lock);
4461                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4462                 mutex_unlock(&dev_priv->rps.hw_lock);
4463                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4464                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4465                         DRM_ERROR("Timed out waiting for IPS disable\n");
4466         } else {
4467                 I915_WRITE(IPS_CTL, 0);
4468                 POSTING_READ(IPS_CTL);
4469         }
4470
4471         /* We need to wait for a vblank before we can disable the plane. */
4472         intel_wait_for_vblank(dev, crtc->pipe);
4473 }
4474
4475 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4476 {
4477         if (intel_crtc->overlay) {
4478                 struct drm_device *dev = intel_crtc->base.dev;
4479                 struct drm_i915_private *dev_priv = dev->dev_private;
4480
4481                 mutex_lock(&dev->struct_mutex);
4482                 dev_priv->mm.interruptible = false;
4483                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4484                 dev_priv->mm.interruptible = true;
4485                 mutex_unlock(&dev->struct_mutex);
4486         }
4487
4488         /* Let userspace switch the overlay on again. In most cases userspace
4489          * has to recompute where to put it anyway.
4490          */
4491 }
4492
4493 /**
4494  * intel_post_enable_primary - Perform operations after enabling primary plane
4495  * @crtc: the CRTC whose primary plane was just enabled
4496  *
4497  * Performs potentially sleeping operations that must be done after the primary
4498  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4499  * called due to an explicit primary plane update, or due to an implicit
4500  * re-enable that is caused when a sprite plane is updated to no longer
4501  * completely hide the primary plane.
4502  */
4503 static void
4504 intel_post_enable_primary(struct drm_crtc *crtc)
4505 {
4506         struct drm_device *dev = crtc->dev;
4507         struct drm_i915_private *dev_priv = dev->dev_private;
4508         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4509         int pipe = intel_crtc->pipe;
4510
4511         /*
4512          * FIXME IPS should be fine as long as one plane is
4513          * enabled, but in practice it seems to have problems
4514          * when going from primary only to sprite only and vice
4515          * versa.
4516          */
4517         hsw_enable_ips(intel_crtc);
4518
4519         /*
4520          * Gen2 reports pipe underruns whenever all planes are disabled.
4521          * So don't enable underrun reporting before at least some planes
4522          * are enabled.
4523          * FIXME: Need to fix the logic to work when we turn off all planes
4524          * but leave the pipe running.
4525          */
4526         if (IS_GEN2(dev))
4527                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4528
4529         /* Underruns don't always raise interrupts, so check manually. */
4530         intel_check_cpu_fifo_underruns(dev_priv);
4531         intel_check_pch_fifo_underruns(dev_priv);
4532 }
4533
4534 /* FIXME move all this to pre_plane_update() with proper state tracking */
4535 static void
4536 intel_pre_disable_primary(struct drm_crtc *crtc)
4537 {
4538         struct drm_device *dev = crtc->dev;
4539         struct drm_i915_private *dev_priv = dev->dev_private;
4540         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4541         int pipe = intel_crtc->pipe;
4542
4543         /*
4544          * Gen2 reports pipe underruns whenever all planes are disabled.
4545          * So diasble underrun reporting before all the planes get disabled.
4546          * FIXME: Need to fix the logic to work when we turn off all planes
4547          * but leave the pipe running.
4548          */
4549         if (IS_GEN2(dev))
4550                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4551
4552         /*
4553          * FIXME IPS should be fine as long as one plane is
4554          * enabled, but in practice it seems to have problems
4555          * when going from primary only to sprite only and vice
4556          * versa.
4557          */
4558         hsw_disable_ips(intel_crtc);
4559 }
4560
4561 /* FIXME get rid of this and use pre_plane_update */
4562 static void
4563 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4564 {
4565         struct drm_device *dev = crtc->dev;
4566         struct drm_i915_private *dev_priv = dev->dev_private;
4567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4568         int pipe = intel_crtc->pipe;
4569
4570         intel_pre_disable_primary(crtc);
4571
4572         /*
4573          * Vblank time updates from the shadow to live plane control register
4574          * are blocked if the memory self-refresh mode is active at that
4575          * moment. So to make sure the plane gets truly disabled, disable
4576          * first the self-refresh mode. The self-refresh enable bit in turn
4577          * will be checked/applied by the HW only at the next frame start
4578          * event which is after the vblank start event, so we need to have a
4579          * wait-for-vblank between disabling the plane and the pipe.
4580          */
4581         if (HAS_GMCH_DISPLAY(dev)) {
4582                 intel_set_memory_cxsr(dev_priv, false);
4583                 dev_priv->wm.vlv.cxsr = false;
4584                 intel_wait_for_vblank(dev, pipe);
4585         }
4586 }
4587
4588 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4589 {
4590         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4591         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4592         struct intel_crtc_state *pipe_config =
4593                 to_intel_crtc_state(crtc->base.state);
4594         struct drm_device *dev = crtc->base.dev;
4595         struct drm_plane *primary = crtc->base.primary;
4596         struct drm_plane_state *old_pri_state =
4597                 drm_atomic_get_existing_plane_state(old_state, primary);
4598
4599         intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4600
4601         crtc->wm.cxsr_allowed = true;
4602
4603         if (pipe_config->update_wm_post && pipe_config->base.active)
4604                 intel_update_watermarks(&crtc->base);
4605
4606         if (old_pri_state) {
4607                 struct intel_plane_state *primary_state =
4608                         to_intel_plane_state(primary->state);
4609                 struct intel_plane_state *old_primary_state =
4610                         to_intel_plane_state(old_pri_state);
4611
4612                 intel_fbc_post_update(crtc);
4613
4614                 if (primary_state->visible &&
4615                     (needs_modeset(&pipe_config->base) ||
4616                      !old_primary_state->visible))
4617                         intel_post_enable_primary(&crtc->base);
4618         }
4619 }
4620
4621 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4622 {
4623         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4624         struct drm_device *dev = crtc->base.dev;
4625         struct drm_i915_private *dev_priv = dev->dev_private;
4626         struct intel_crtc_state *pipe_config =
4627                 to_intel_crtc_state(crtc->base.state);
4628         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4629         struct drm_plane *primary = crtc->base.primary;
4630         struct drm_plane_state *old_pri_state =
4631                 drm_atomic_get_existing_plane_state(old_state, primary);
4632         bool modeset = needs_modeset(&pipe_config->base);
4633
4634         if (old_pri_state) {
4635                 struct intel_plane_state *primary_state =
4636                         to_intel_plane_state(primary->state);
4637                 struct intel_plane_state *old_primary_state =
4638                         to_intel_plane_state(old_pri_state);
4639
4640                 intel_fbc_pre_update(crtc);
4641
4642                 if (old_primary_state->visible &&
4643                     (modeset || !primary_state->visible))
4644                         intel_pre_disable_primary(&crtc->base);
4645         }
4646
4647         if (pipe_config->disable_cxsr) {
4648                 crtc->wm.cxsr_allowed = false;
4649
4650                 /*
4651                  * Vblank time updates from the shadow to live plane control register
4652                  * are blocked if the memory self-refresh mode is active at that
4653                  * moment. So to make sure the plane gets truly disabled, disable
4654                  * first the self-refresh mode. The self-refresh enable bit in turn
4655                  * will be checked/applied by the HW only at the next frame start
4656                  * event which is after the vblank start event, so we need to have a
4657                  * wait-for-vblank between disabling the plane and the pipe.
4658                  */
4659                 if (old_crtc_state->base.active) {
4660                         intel_set_memory_cxsr(dev_priv, false);
4661                         dev_priv->wm.vlv.cxsr = false;
4662                         intel_wait_for_vblank(dev, crtc->pipe);
4663                 }
4664         }
4665
4666         /*
4667          * IVB workaround: must disable low power watermarks for at least
4668          * one frame before enabling scaling.  LP watermarks can be re-enabled
4669          * when scaling is disabled.
4670          *
4671          * WaCxSRDisabledForSpriteScaling:ivb
4672          */
4673         if (pipe_config->disable_lp_wm) {
4674                 ilk_disable_lp_wm(dev);
4675                 intel_wait_for_vblank(dev, crtc->pipe);
4676         }
4677
4678         /*
4679          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4680          * watermark programming here.
4681          */
4682         if (needs_modeset(&pipe_config->base))
4683                 return;
4684
4685         /*
4686          * For platforms that support atomic watermarks, program the
4687          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4688          * will be the intermediate values that are safe for both pre- and
4689          * post- vblank; when vblank happens, the 'active' values will be set
4690          * to the final 'target' values and we'll do this again to get the
4691          * optimal watermarks.  For gen9+ platforms, the values we program here
4692          * will be the final target values which will get automatically latched
4693          * at vblank time; no further programming will be necessary.
4694          *
4695          * If a platform hasn't been transitioned to atomic watermarks yet,
4696          * we'll continue to update watermarks the old way, if flags tell
4697          * us to.
4698          */
4699         if (dev_priv->display.initial_watermarks != NULL)
4700                 dev_priv->display.initial_watermarks(pipe_config);
4701         else if (pipe_config->update_wm_pre)
4702                 intel_update_watermarks(&crtc->base);
4703 }
4704
4705 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4706 {
4707         struct drm_device *dev = crtc->dev;
4708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709         struct drm_plane *p;
4710         int pipe = intel_crtc->pipe;
4711
4712         intel_crtc_dpms_overlay_disable(intel_crtc);
4713
4714         drm_for_each_plane_mask(p, dev, plane_mask)
4715                 to_intel_plane(p)->disable_plane(p, crtc);
4716
4717         /*
4718          * FIXME: Once we grow proper nuclear flip support out of this we need
4719          * to compute the mask of flip planes precisely. For the time being
4720          * consider this a flip to a NULL plane.
4721          */
4722         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4723 }
4724
4725 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4726 {
4727         struct drm_device *dev = crtc->dev;
4728         struct drm_i915_private *dev_priv = dev->dev_private;
4729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4730         struct intel_encoder *encoder;
4731         int pipe = intel_crtc->pipe;
4732         struct intel_crtc_state *pipe_config =
4733                 to_intel_crtc_state(crtc->state);
4734
4735         if (WARN_ON(intel_crtc->active))
4736                 return;
4737
4738         /*
4739          * Sometimes spurious CPU pipe underruns happen during FDI
4740          * training, at least with VGA+HDMI cloning. Suppress them.
4741          *
4742          * On ILK we get an occasional spurious CPU pipe underruns
4743          * between eDP port A enable and vdd enable. Also PCH port
4744          * enable seems to result in the occasional CPU pipe underrun.
4745          *
4746          * Spurious PCH underruns also occur during PCH enabling.
4747          */
4748         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4749                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4750         if (intel_crtc->config->has_pch_encoder)
4751                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4752
4753         if (intel_crtc->config->has_pch_encoder)
4754                 intel_prepare_shared_dpll(intel_crtc);
4755
4756         if (intel_crtc->config->has_dp_encoder)
4757                 intel_dp_set_m_n(intel_crtc, M1_N1);
4758
4759         intel_set_pipe_timings(intel_crtc);
4760         intel_set_pipe_src_size(intel_crtc);
4761
4762         if (intel_crtc->config->has_pch_encoder) {
4763                 intel_cpu_transcoder_set_m_n(intel_crtc,
4764                                      &intel_crtc->config->fdi_m_n, NULL);
4765         }
4766
4767         ironlake_set_pipeconf(crtc);
4768
4769         intel_crtc->active = true;
4770
4771         for_each_encoder_on_crtc(dev, crtc, encoder)
4772                 if (encoder->pre_enable)
4773                         encoder->pre_enable(encoder);
4774
4775         if (intel_crtc->config->has_pch_encoder) {
4776                 /* Note: FDI PLL enabling _must_ be done before we enable the
4777                  * cpu pipes, hence this is separate from all the other fdi/pch
4778                  * enabling. */
4779                 ironlake_fdi_pll_enable(intel_crtc);
4780         } else {
4781                 assert_fdi_tx_disabled(dev_priv, pipe);
4782                 assert_fdi_rx_disabled(dev_priv, pipe);
4783         }
4784
4785         ironlake_pfit_enable(intel_crtc);
4786
4787         /*
4788          * On ILK+ LUT must be loaded before the pipe is running but with
4789          * clocks enabled
4790          */
4791         intel_color_load_luts(&pipe_config->base);
4792
4793         if (dev_priv->display.initial_watermarks != NULL)
4794                 dev_priv->display.initial_watermarks(intel_crtc->config);
4795         intel_enable_pipe(intel_crtc);
4796
4797         if (intel_crtc->config->has_pch_encoder)
4798                 ironlake_pch_enable(crtc);
4799
4800         assert_vblank_disabled(crtc);
4801         drm_crtc_vblank_on(crtc);
4802
4803         for_each_encoder_on_crtc(dev, crtc, encoder)
4804                 encoder->enable(encoder);
4805
4806         if (HAS_PCH_CPT(dev))
4807                 cpt_verify_modeset(dev, intel_crtc->pipe);
4808
4809         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4810         if (intel_crtc->config->has_pch_encoder)
4811                 intel_wait_for_vblank(dev, pipe);
4812         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4813         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4814 }
4815
4816 /* IPS only exists on ULT machines and is tied to pipe A. */
4817 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4818 {
4819         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4820 }
4821
4822 static void haswell_crtc_enable(struct drm_crtc *crtc)
4823 {
4824         struct drm_device *dev = crtc->dev;
4825         struct drm_i915_private *dev_priv = dev->dev_private;
4826         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4827         struct intel_encoder *encoder;
4828         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4829         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4830         struct intel_crtc_state *pipe_config =
4831                 to_intel_crtc_state(crtc->state);
4832
4833         if (WARN_ON(intel_crtc->active))
4834                 return;
4835
4836         if (intel_crtc->config->has_pch_encoder)
4837                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4838                                                       false);
4839
4840         if (intel_crtc->config->shared_dpll)
4841                 intel_enable_shared_dpll(intel_crtc);
4842
4843         if (intel_crtc->config->has_dp_encoder)
4844                 intel_dp_set_m_n(intel_crtc, M1_N1);
4845
4846         if (!intel_crtc->config->has_dsi_encoder)
4847                 intel_set_pipe_timings(intel_crtc);
4848
4849         intel_set_pipe_src_size(intel_crtc);
4850
4851         if (cpu_transcoder != TRANSCODER_EDP &&
4852             !transcoder_is_dsi(cpu_transcoder)) {
4853                 I915_WRITE(PIPE_MULT(cpu_transcoder),
4854                            intel_crtc->config->pixel_multiplier - 1);
4855         }
4856
4857         if (intel_crtc->config->has_pch_encoder) {
4858                 intel_cpu_transcoder_set_m_n(intel_crtc,
4859                                      &intel_crtc->config->fdi_m_n, NULL);
4860         }
4861
4862         if (!intel_crtc->config->has_dsi_encoder)
4863                 haswell_set_pipeconf(crtc);
4864
4865         haswell_set_pipemisc(crtc);
4866
4867         intel_color_set_csc(&pipe_config->base);
4868
4869         intel_crtc->active = true;
4870
4871         if (intel_crtc->config->has_pch_encoder)
4872                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4873         else
4874                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4875
4876         for_each_encoder_on_crtc(dev, crtc, encoder) {
4877                 if (encoder->pre_enable)
4878                         encoder->pre_enable(encoder);
4879         }
4880
4881         if (intel_crtc->config->has_pch_encoder)
4882                 dev_priv->display.fdi_link_train(crtc);
4883
4884         if (!intel_crtc->config->has_dsi_encoder)
4885                 intel_ddi_enable_pipe_clock(intel_crtc);
4886
4887         if (INTEL_INFO(dev)->gen >= 9)
4888                 skylake_pfit_enable(intel_crtc);
4889         else
4890                 ironlake_pfit_enable(intel_crtc);
4891
4892         /*
4893          * On ILK+ LUT must be loaded before the pipe is running but with
4894          * clocks enabled
4895          */
4896         intel_color_load_luts(&pipe_config->base);
4897
4898         intel_ddi_set_pipe_settings(crtc);
4899         if (!intel_crtc->config->has_dsi_encoder)
4900                 intel_ddi_enable_transcoder_func(crtc);
4901
4902         if (dev_priv->display.initial_watermarks != NULL)
4903                 dev_priv->display.initial_watermarks(pipe_config);
4904         else
4905                 intel_update_watermarks(crtc);
4906
4907         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4908         if (!intel_crtc->config->has_dsi_encoder)
4909                 intel_enable_pipe(intel_crtc);
4910
4911         if (intel_crtc->config->has_pch_encoder)
4912                 lpt_pch_enable(crtc);
4913
4914         if (intel_crtc->config->dp_encoder_is_mst)
4915                 intel_ddi_set_vc_payload_alloc(crtc, true);
4916
4917         assert_vblank_disabled(crtc);
4918         drm_crtc_vblank_on(crtc);
4919
4920         for_each_encoder_on_crtc(dev, crtc, encoder) {
4921                 encoder->enable(encoder);
4922                 intel_opregion_notify_encoder(encoder, true);
4923         }
4924
4925         if (intel_crtc->config->has_pch_encoder) {
4926                 intel_wait_for_vblank(dev, pipe);
4927                 intel_wait_for_vblank(dev, pipe);
4928                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4929                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4930                                                       true);
4931         }
4932
4933         /* If we change the relative order between pipe/planes enabling, we need
4934          * to change the workaround. */
4935         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4936         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4937                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4938                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4939         }
4940 }
4941
4942 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4943 {
4944         struct drm_device *dev = crtc->base.dev;
4945         struct drm_i915_private *dev_priv = dev->dev_private;
4946         int pipe = crtc->pipe;
4947
4948         /* To avoid upsetting the power well on haswell only disable the pfit if
4949          * it's in use. The hw state code will make sure we get this right. */
4950         if (force || crtc->config->pch_pfit.enabled) {
4951                 I915_WRITE(PF_CTL(pipe), 0);
4952                 I915_WRITE(PF_WIN_POS(pipe), 0);
4953                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4954         }
4955 }
4956
4957 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4958 {
4959         struct drm_device *dev = crtc->dev;
4960         struct drm_i915_private *dev_priv = dev->dev_private;
4961         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4962         struct intel_encoder *encoder;
4963         int pipe = intel_crtc->pipe;
4964
4965         /*
4966          * Sometimes spurious CPU pipe underruns happen when the
4967          * pipe is already disabled, but FDI RX/TX is still enabled.
4968          * Happens at least with VGA+HDMI cloning. Suppress them.
4969          */
4970         if (intel_crtc->config->has_pch_encoder) {
4971                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4972                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4973         }
4974
4975         for_each_encoder_on_crtc(dev, crtc, encoder)
4976                 encoder->disable(encoder);
4977
4978         drm_crtc_vblank_off(crtc);
4979         assert_vblank_disabled(crtc);
4980
4981         intel_disable_pipe(intel_crtc);
4982
4983         ironlake_pfit_disable(intel_crtc, false);
4984
4985         if (intel_crtc->config->has_pch_encoder)
4986                 ironlake_fdi_disable(crtc);
4987
4988         for_each_encoder_on_crtc(dev, crtc, encoder)
4989                 if (encoder->post_disable)
4990                         encoder->post_disable(encoder);
4991
4992         if (intel_crtc->config->has_pch_encoder) {
4993                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4994
4995                 if (HAS_PCH_CPT(dev)) {
4996                         i915_reg_t reg;
4997                         u32 temp;
4998
4999                         /* disable TRANS_DP_CTL */
5000                         reg = TRANS_DP_CTL(pipe);
5001                         temp = I915_READ(reg);
5002                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5003                                   TRANS_DP_PORT_SEL_MASK);
5004                         temp |= TRANS_DP_PORT_SEL_NONE;
5005                         I915_WRITE(reg, temp);
5006
5007                         /* disable DPLL_SEL */
5008                         temp = I915_READ(PCH_DPLL_SEL);
5009                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5010                         I915_WRITE(PCH_DPLL_SEL, temp);
5011                 }
5012
5013                 ironlake_fdi_pll_disable(intel_crtc);
5014         }
5015
5016         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5017         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5018 }
5019
5020 static void haswell_crtc_disable(struct drm_crtc *crtc)
5021 {
5022         struct drm_device *dev = crtc->dev;
5023         struct drm_i915_private *dev_priv = dev->dev_private;
5024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5025         struct intel_encoder *encoder;
5026         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5027
5028         if (intel_crtc->config->has_pch_encoder)
5029                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5030                                                       false);
5031
5032         for_each_encoder_on_crtc(dev, crtc, encoder) {
5033                 intel_opregion_notify_encoder(encoder, false);
5034                 encoder->disable(encoder);
5035         }
5036
5037         drm_crtc_vblank_off(crtc);
5038         assert_vblank_disabled(crtc);
5039
5040         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5041         if (!intel_crtc->config->has_dsi_encoder)
5042                 intel_disable_pipe(intel_crtc);
5043
5044         if (intel_crtc->config->dp_encoder_is_mst)
5045                 intel_ddi_set_vc_payload_alloc(crtc, false);
5046
5047         if (!intel_crtc->config->has_dsi_encoder)
5048                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5049
5050         if (INTEL_INFO(dev)->gen >= 9)
5051                 skylake_scaler_disable(intel_crtc);
5052         else
5053                 ironlake_pfit_disable(intel_crtc, false);
5054
5055         if (!intel_crtc->config->has_dsi_encoder)
5056                 intel_ddi_disable_pipe_clock(intel_crtc);
5057
5058         for_each_encoder_on_crtc(dev, crtc, encoder)
5059                 if (encoder->post_disable)
5060                         encoder->post_disable(encoder);
5061
5062         if (intel_crtc->config->has_pch_encoder) {
5063                 lpt_disable_pch_transcoder(dev_priv);
5064                 lpt_disable_iclkip(dev_priv);
5065                 intel_ddi_fdi_disable(crtc);
5066
5067                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5068                                                       true);
5069         }
5070 }
5071
5072 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5073 {
5074         struct drm_device *dev = crtc->base.dev;
5075         struct drm_i915_private *dev_priv = dev->dev_private;
5076         struct intel_crtc_state *pipe_config = crtc->config;
5077
5078         if (!pipe_config->gmch_pfit.control)
5079                 return;
5080
5081         /*
5082          * The panel fitter should only be adjusted whilst the pipe is disabled,
5083          * according to register description and PRM.
5084          */
5085         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5086         assert_pipe_disabled(dev_priv, crtc->pipe);
5087
5088         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5089         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5090
5091         /* Border color in case we don't scale up to the full screen. Black by
5092          * default, change to something else for debugging. */
5093         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5094 }
5095
5096 static enum intel_display_power_domain port_to_power_domain(enum port port)
5097 {
5098         switch (port) {
5099         case PORT_A:
5100                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5101         case PORT_B:
5102                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5103         case PORT_C:
5104                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5105         case PORT_D:
5106                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5107         case PORT_E:
5108                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5109         default:
5110                 MISSING_CASE(port);
5111                 return POWER_DOMAIN_PORT_OTHER;
5112         }
5113 }
5114
5115 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5116 {
5117         switch (port) {
5118         case PORT_A:
5119                 return POWER_DOMAIN_AUX_A;
5120         case PORT_B:
5121                 return POWER_DOMAIN_AUX_B;
5122         case PORT_C:
5123                 return POWER_DOMAIN_AUX_C;
5124         case PORT_D:
5125                 return POWER_DOMAIN_AUX_D;
5126         case PORT_E:
5127                 /* FIXME: Check VBT for actual wiring of PORT E */
5128                 return POWER_DOMAIN_AUX_D;
5129         default:
5130                 MISSING_CASE(port);
5131                 return POWER_DOMAIN_AUX_A;
5132         }
5133 }
5134
5135 enum intel_display_power_domain
5136 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5137 {
5138         struct drm_device *dev = intel_encoder->base.dev;
5139         struct intel_digital_port *intel_dig_port;
5140
5141         switch (intel_encoder->type) {
5142         case INTEL_OUTPUT_UNKNOWN:
5143                 /* Only DDI platforms should ever use this output type */
5144                 WARN_ON_ONCE(!HAS_DDI(dev));
5145         case INTEL_OUTPUT_DISPLAYPORT:
5146         case INTEL_OUTPUT_HDMI:
5147         case INTEL_OUTPUT_EDP:
5148                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5149                 return port_to_power_domain(intel_dig_port->port);
5150         case INTEL_OUTPUT_DP_MST:
5151                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5152                 return port_to_power_domain(intel_dig_port->port);
5153         case INTEL_OUTPUT_ANALOG:
5154                 return POWER_DOMAIN_PORT_CRT;
5155         case INTEL_OUTPUT_DSI:
5156                 return POWER_DOMAIN_PORT_DSI;
5157         default:
5158                 return POWER_DOMAIN_PORT_OTHER;
5159         }
5160 }
5161
5162 enum intel_display_power_domain
5163 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5164 {
5165         struct drm_device *dev = intel_encoder->base.dev;
5166         struct intel_digital_port *intel_dig_port;
5167
5168         switch (intel_encoder->type) {
5169         case INTEL_OUTPUT_UNKNOWN:
5170         case INTEL_OUTPUT_HDMI:
5171                 /*
5172                  * Only DDI platforms should ever use these output types.
5173                  * We can get here after the HDMI detect code has already set
5174                  * the type of the shared encoder. Since we can't be sure
5175                  * what's the status of the given connectors, play safe and
5176                  * run the DP detection too.
5177                  */
5178                 WARN_ON_ONCE(!HAS_DDI(dev));
5179         case INTEL_OUTPUT_DISPLAYPORT:
5180         case INTEL_OUTPUT_EDP:
5181                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5182                 return port_to_aux_power_domain(intel_dig_port->port);
5183         case INTEL_OUTPUT_DP_MST:
5184                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5185                 return port_to_aux_power_domain(intel_dig_port->port);
5186         default:
5187                 MISSING_CASE(intel_encoder->type);
5188                 return POWER_DOMAIN_AUX_A;
5189         }
5190 }
5191
5192 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5193                                             struct intel_crtc_state *crtc_state)
5194 {
5195         struct drm_device *dev = crtc->dev;
5196         struct drm_encoder *encoder;
5197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5198         enum pipe pipe = intel_crtc->pipe;
5199         unsigned long mask;
5200         enum transcoder transcoder = crtc_state->cpu_transcoder;
5201
5202         if (!crtc_state->base.active)
5203                 return 0;
5204
5205         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5206         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5207         if (crtc_state->pch_pfit.enabled ||
5208             crtc_state->pch_pfit.force_thru)
5209                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5210
5211         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5212                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5213
5214                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5215         }
5216
5217         if (crtc_state->shared_dpll)
5218                 mask |= BIT(POWER_DOMAIN_PLLS);
5219
5220         return mask;
5221 }
5222
5223 static unsigned long
5224 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5225                                struct intel_crtc_state *crtc_state)
5226 {
5227         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5228         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5229         enum intel_display_power_domain domain;
5230         unsigned long domains, new_domains, old_domains;
5231
5232         old_domains = intel_crtc->enabled_power_domains;
5233         intel_crtc->enabled_power_domains = new_domains =
5234                 get_crtc_power_domains(crtc, crtc_state);
5235
5236         domains = new_domains & ~old_domains;
5237
5238         for_each_power_domain(domain, domains)
5239                 intel_display_power_get(dev_priv, domain);
5240
5241         return old_domains & ~new_domains;
5242 }
5243
5244 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5245                                       unsigned long domains)
5246 {
5247         enum intel_display_power_domain domain;
5248
5249         for_each_power_domain(domain, domains)
5250                 intel_display_power_put(dev_priv, domain);
5251 }
5252
5253 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5254 {
5255         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5256
5257         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5258             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5259                 return max_cdclk_freq;
5260         else if (IS_CHERRYVIEW(dev_priv))
5261                 return max_cdclk_freq*95/100;
5262         else if (INTEL_INFO(dev_priv)->gen < 4)
5263                 return 2*max_cdclk_freq*90/100;
5264         else
5265                 return max_cdclk_freq*90/100;
5266 }
5267
5268 static void intel_update_max_cdclk(struct drm_device *dev)
5269 {
5270         struct drm_i915_private *dev_priv = dev->dev_private;
5271
5272         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5273                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5274
5275                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5276                         dev_priv->max_cdclk_freq = 675000;
5277                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5278                         dev_priv->max_cdclk_freq = 540000;
5279                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5280                         dev_priv->max_cdclk_freq = 450000;
5281                 else
5282                         dev_priv->max_cdclk_freq = 337500;
5283         } else if (IS_BROXTON(dev)) {
5284                 dev_priv->max_cdclk_freq = 624000;
5285         } else if (IS_BROADWELL(dev))  {
5286                 /*
5287                  * FIXME with extra cooling we can allow
5288                  * 540 MHz for ULX and 675 Mhz for ULT.
5289                  * How can we know if extra cooling is
5290                  * available? PCI ID, VTB, something else?
5291                  */
5292                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5293                         dev_priv->max_cdclk_freq = 450000;
5294                 else if (IS_BDW_ULX(dev))
5295                         dev_priv->max_cdclk_freq = 450000;
5296                 else if (IS_BDW_ULT(dev))
5297                         dev_priv->max_cdclk_freq = 540000;
5298                 else
5299                         dev_priv->max_cdclk_freq = 675000;
5300         } else if (IS_CHERRYVIEW(dev)) {
5301                 dev_priv->max_cdclk_freq = 320000;
5302         } else if (IS_VALLEYVIEW(dev)) {
5303                 dev_priv->max_cdclk_freq = 400000;
5304         } else {
5305                 /* otherwise assume cdclk is fixed */
5306                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5307         }
5308
5309         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5310
5311         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5312                          dev_priv->max_cdclk_freq);
5313
5314         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5315                          dev_priv->max_dotclk_freq);
5316 }
5317
5318 static void intel_update_cdclk(struct drm_device *dev)
5319 {
5320         struct drm_i915_private *dev_priv = dev->dev_private;
5321
5322         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5323         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5324                          dev_priv->cdclk_freq);
5325
5326         /*
5327          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5328          * Programmng [sic] note: bit[9:2] should be programmed to the number
5329          * of cdclk that generates 4MHz reference clock freq which is used to
5330          * generate GMBus clock. This will vary with the cdclk freq.
5331          */
5332         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5333                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5334
5335         if (dev_priv->max_cdclk_freq == 0)
5336                 intel_update_max_cdclk(dev);
5337 }
5338
5339 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5340 static int skl_cdclk_decimal(int cdclk)
5341 {
5342         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5343 }
5344
5345 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5346 {
5347         uint32_t divider;
5348         uint32_t ratio;
5349         uint32_t current_cdclk;
5350         int ret;
5351
5352         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5353         switch (cdclk) {
5354         case 144000:
5355                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5356                 ratio = BXT_DE_PLL_RATIO(60);
5357                 break;
5358         case 288000:
5359                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5360                 ratio = BXT_DE_PLL_RATIO(60);
5361                 break;
5362         case 384000:
5363                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5364                 ratio = BXT_DE_PLL_RATIO(60);
5365                 break;
5366         case 576000:
5367                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5368                 ratio = BXT_DE_PLL_RATIO(60);
5369                 break;
5370         case 624000:
5371                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5372                 ratio = BXT_DE_PLL_RATIO(65);
5373                 break;
5374         case 19200:
5375                 /*
5376                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5377                  * to suppress GCC warning.
5378                  */
5379                 ratio = 0;
5380                 divider = 0;
5381                 break;
5382         default:
5383                 DRM_ERROR("unsupported CDCLK freq %d", cdclk);
5384
5385                 return;
5386         }
5387
5388         mutex_lock(&dev_priv->rps.hw_lock);
5389         /* Inform power controller of upcoming frequency change */
5390         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5391                                       0x80000000);
5392         mutex_unlock(&dev_priv->rps.hw_lock);
5393
5394         if (ret) {
5395                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5396                           ret, cdclk);
5397                 return;
5398         }
5399
5400         current_cdclk = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5401         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5402         current_cdclk = current_cdclk * 500 + 1000;
5403
5404         /*
5405          * DE PLL has to be disabled when
5406          * - setting to 19.2MHz (bypass, PLL isn't used)
5407          * - before setting to 624MHz (PLL needs toggling)
5408          * - before setting to any frequency from 624MHz (PLL needs toggling)
5409          */
5410         if (cdclk == 19200 || cdclk == 624000 ||
5411             current_cdclk == 624000) {
5412                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5413                 /* Timeout 200us */
5414                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5415                              1))
5416                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5417         }
5418
5419         if (cdclk != 19200) {
5420                 uint32_t val;
5421
5422                 val = I915_READ(BXT_DE_PLL_CTL);
5423                 val &= ~BXT_DE_PLL_RATIO_MASK;
5424                 val |= ratio;
5425                 I915_WRITE(BXT_DE_PLL_CTL, val);
5426
5427                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5428                 /* Timeout 200us */
5429                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5430                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5431
5432                 val = divider | skl_cdclk_decimal(cdclk);
5433                 /*
5434                  * FIXME if only the cd2x divider needs changing, it could be done
5435                  * without shutting off the pipe (if only one pipe is active).
5436                  */
5437                 val |= BXT_CDCLK_CD2X_PIPE_NONE;
5438                 /*
5439                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5440                  * enable otherwise.
5441                  */
5442                 if (cdclk >= 500000)
5443                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5444                 I915_WRITE(CDCLK_CTL, val);
5445         }
5446
5447         mutex_lock(&dev_priv->rps.hw_lock);
5448         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5449                                       DIV_ROUND_UP(cdclk, 25000));
5450         mutex_unlock(&dev_priv->rps.hw_lock);
5451
5452         if (ret) {
5453                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5454                           ret, cdclk);
5455                 return;
5456         }
5457
5458         intel_update_cdclk(dev_priv->dev);
5459 }
5460
5461 static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
5462 {
5463         if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
5464                 return false;
5465
5466         /* TODO: Check for a valid CDCLK rate */
5467
5468         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
5469                 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
5470
5471                 return false;
5472         }
5473
5474         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
5475                 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
5476
5477                 return false;
5478         }
5479
5480         return true;
5481 }
5482
5483 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
5484 {
5485         return broxton_cdclk_is_enabled(dev_priv);
5486 }
5487
5488 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
5489 {
5490         /* check if cd clock is enabled */
5491         if (broxton_cdclk_is_enabled(dev_priv)) {
5492                 DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
5493                 return;
5494         }
5495
5496         DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
5497
5498         /*
5499          * FIXME:
5500          * - The initial CDCLK needs to be read from VBT.
5501          *   Need to make this change after VBT has changes for BXT.
5502          * - check if setting the max (or any) cdclk freq is really necessary
5503          *   here, it belongs to modeset time
5504          */
5505         broxton_set_cdclk(dev_priv, 624000);
5506
5507         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5508         POSTING_READ(DBUF_CTL);
5509
5510         udelay(10);
5511
5512         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5513                 DRM_ERROR("DBuf power enable timeout!\n");
5514 }
5515
5516 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
5517 {
5518         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5519         POSTING_READ(DBUF_CTL);
5520
5521         udelay(10);
5522
5523         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5524                 DRM_ERROR("DBuf power disable timeout!\n");
5525
5526         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5527         broxton_set_cdclk(dev_priv, 19200);
5528 }
5529
5530 static const struct skl_cdclk_entry {
5531         unsigned int freq;
5532         unsigned int vco;
5533 } skl_cdclk_frequencies[] = {
5534         { .freq = 308570, .vco = 8640 },
5535         { .freq = 337500, .vco = 8100 },
5536         { .freq = 432000, .vco = 8640 },
5537         { .freq = 450000, .vco = 8100 },
5538         { .freq = 540000, .vco = 8100 },
5539         { .freq = 617140, .vco = 8640 },
5540         { .freq = 675000, .vco = 8100 },
5541 };
5542
5543 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5544 {
5545         unsigned int i;
5546
5547         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5548                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5549
5550                 if (e->freq == freq)
5551                         return e->vco;
5552         }
5553
5554         return 8100;
5555 }
5556
5557 static void
5558 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5559 {
5560         int min_cdclk;
5561         u32 val;
5562
5563         /* select the minimum CDCLK before enabling DPLL 0 */
5564         if (vco == 8640)
5565                 min_cdclk = 308570;
5566         else
5567                 min_cdclk = 337500;
5568
5569         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5570         I915_WRITE(CDCLK_CTL, val);
5571         POSTING_READ(CDCLK_CTL);
5572
5573         /*
5574          * We always enable DPLL0 with the lowest link rate possible, but still
5575          * taking into account the VCO required to operate the eDP panel at the
5576          * desired frequency. The usual DP link rates operate with a VCO of
5577          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5578          * The modeset code is responsible for the selection of the exact link
5579          * rate later on, with the constraint of choosing a frequency that
5580          * works with required_vco.
5581          */
5582         val = I915_READ(DPLL_CTRL1);
5583
5584         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5585                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5586         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5587         if (vco == 8640)
5588                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5589                                             SKL_DPLL0);
5590         else
5591                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5592                                             SKL_DPLL0);
5593
5594         I915_WRITE(DPLL_CTRL1, val);
5595         POSTING_READ(DPLL_CTRL1);
5596
5597         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5598
5599         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5600                 DRM_ERROR("DPLL0 not locked\n");
5601 }
5602
5603 static void
5604 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5605 {
5606         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5607         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5608                 DRM_ERROR("Couldn't disable DPLL0\n");
5609 }
5610
5611 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5612 {
5613         int ret;
5614         u32 val;
5615
5616         /* inform PCU we want to change CDCLK */
5617         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5618         mutex_lock(&dev_priv->rps.hw_lock);
5619         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5620         mutex_unlock(&dev_priv->rps.hw_lock);
5621
5622         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5623 }
5624
5625 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5626 {
5627         unsigned int i;
5628
5629         for (i = 0; i < 15; i++) {
5630                 if (skl_cdclk_pcu_ready(dev_priv))
5631                         return true;
5632                 udelay(10);
5633         }
5634
5635         return false;
5636 }
5637
5638 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5639 {
5640         struct drm_device *dev = dev_priv->dev;
5641         u32 freq_select, pcu_ack;
5642
5643         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", cdclk);
5644
5645         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5646                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5647                 return;
5648         }
5649
5650         /* set CDCLK_CTL */
5651         switch (cdclk) {
5652         case 450000:
5653         case 432000:
5654                 freq_select = CDCLK_FREQ_450_432;
5655                 pcu_ack = 1;
5656                 break;
5657         case 540000:
5658                 freq_select = CDCLK_FREQ_540;
5659                 pcu_ack = 2;
5660                 break;
5661         case 308570:
5662         case 337500:
5663         default:
5664                 freq_select = CDCLK_FREQ_337_308;
5665                 pcu_ack = 0;
5666                 break;
5667         case 617140:
5668         case 675000:
5669                 freq_select = CDCLK_FREQ_675_617;
5670                 pcu_ack = 3;
5671                 break;
5672         }
5673
5674         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5675         POSTING_READ(CDCLK_CTL);
5676
5677         /* inform PCU of the change */
5678         mutex_lock(&dev_priv->rps.hw_lock);
5679         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5680         mutex_unlock(&dev_priv->rps.hw_lock);
5681
5682         intel_update_cdclk(dev);
5683 }
5684
5685 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5686 {
5687         /* disable DBUF power */
5688         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5689         POSTING_READ(DBUF_CTL);
5690
5691         udelay(10);
5692
5693         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5694                 DRM_ERROR("DBuf power disable timeout\n");
5695
5696         skl_dpll0_disable(dev_priv);
5697 }
5698
5699 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5700 {
5701         unsigned int vco;
5702
5703         /* DPLL0 not enabled (happens on early BIOS versions) */
5704         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5705                 /* enable DPLL0 */
5706                 vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5707                 skl_dpll0_enable(dev_priv, vco);
5708         }
5709
5710         /* set CDCLK to the frequency the BIOS chose */
5711         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5712
5713         /* enable DBUF power */
5714         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5715         POSTING_READ(DBUF_CTL);
5716
5717         udelay(10);
5718
5719         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5720                 DRM_ERROR("DBuf power enable timeout\n");
5721 }
5722
5723 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5724 {
5725         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5726         uint32_t cdctl = I915_READ(CDCLK_CTL);
5727         int freq = dev_priv->skl_boot_cdclk;
5728
5729         /*
5730          * check if the pre-os intialized the display
5731          * There is SWF18 scratchpad register defined which is set by the
5732          * pre-os which can be used by the OS drivers to check the status
5733          */
5734         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5735                 goto sanitize;
5736
5737         /* Is PLL enabled and locked ? */
5738         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5739                 goto sanitize;
5740
5741         /* DPLL okay; verify the cdclock
5742          *
5743          * Noticed in some instances that the freq selection is correct but
5744          * decimal part is programmed wrong from BIOS where pre-os does not
5745          * enable display. Verify the same as well.
5746          */
5747         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5748                 /* All well; nothing to sanitize */
5749                 return false;
5750 sanitize:
5751         /*
5752          * As of now initialize with max cdclk till
5753          * we get dynamic cdclk support
5754          * */
5755         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5756         skl_init_cdclk(dev_priv);
5757
5758         /* we did have to sanitize */
5759         return true;
5760 }
5761
5762 /* Adjust CDclk dividers to allow high res or save power if possible */
5763 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5764 {
5765         struct drm_i915_private *dev_priv = dev->dev_private;
5766         u32 val, cmd;
5767
5768         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5769                                         != dev_priv->cdclk_freq);
5770
5771         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5772                 cmd = 2;
5773         else if (cdclk == 266667)
5774                 cmd = 1;
5775         else
5776                 cmd = 0;
5777
5778         mutex_lock(&dev_priv->rps.hw_lock);
5779         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5780         val &= ~DSPFREQGUAR_MASK;
5781         val |= (cmd << DSPFREQGUAR_SHIFT);
5782         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5783         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5784                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5785                      50)) {
5786                 DRM_ERROR("timed out waiting for CDclk change\n");
5787         }
5788         mutex_unlock(&dev_priv->rps.hw_lock);
5789
5790         mutex_lock(&dev_priv->sb_lock);
5791
5792         if (cdclk == 400000) {
5793                 u32 divider;
5794
5795                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5796
5797                 /* adjust cdclk divider */
5798                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5799                 val &= ~CCK_FREQUENCY_VALUES;
5800                 val |= divider;
5801                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5802
5803                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5804                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5805                              50))
5806                         DRM_ERROR("timed out waiting for CDclk change\n");
5807         }
5808
5809         /* adjust self-refresh exit latency value */
5810         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5811         val &= ~0x7f;
5812
5813         /*
5814          * For high bandwidth configs, we set a higher latency in the bunit
5815          * so that the core display fetch happens in time to avoid underruns.
5816          */
5817         if (cdclk == 400000)
5818                 val |= 4500 / 250; /* 4.5 usec */
5819         else
5820                 val |= 3000 / 250; /* 3.0 usec */
5821         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5822
5823         mutex_unlock(&dev_priv->sb_lock);
5824
5825         intel_update_cdclk(dev);
5826 }
5827
5828 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5829 {
5830         struct drm_i915_private *dev_priv = dev->dev_private;
5831         u32 val, cmd;
5832
5833         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5834                                                 != dev_priv->cdclk_freq);
5835
5836         switch (cdclk) {
5837         case 333333:
5838         case 320000:
5839         case 266667:
5840         case 200000:
5841                 break;
5842         default:
5843                 MISSING_CASE(cdclk);
5844                 return;
5845         }
5846
5847         /*
5848          * Specs are full of misinformation, but testing on actual
5849          * hardware has shown that we just need to write the desired
5850          * CCK divider into the Punit register.
5851          */
5852         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5853
5854         mutex_lock(&dev_priv->rps.hw_lock);
5855         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5856         val &= ~DSPFREQGUAR_MASK_CHV;
5857         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5858         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5859         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5860                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5861                      50)) {
5862                 DRM_ERROR("timed out waiting for CDclk change\n");
5863         }
5864         mutex_unlock(&dev_priv->rps.hw_lock);
5865
5866         intel_update_cdclk(dev);
5867 }
5868
5869 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5870                                  int max_pixclk)
5871 {
5872         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5873         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5874
5875         /*
5876          * Really only a few cases to deal with, as only 4 CDclks are supported:
5877          *   200MHz
5878          *   267MHz
5879          *   320/333MHz (depends on HPLL freq)
5880          *   400MHz (VLV only)
5881          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5882          * of the lower bin and adjust if needed.
5883          *
5884          * We seem to get an unstable or solid color picture at 200MHz.
5885          * Not sure what's wrong. For now use 200MHz only when all pipes
5886          * are off.
5887          */
5888         if (!IS_CHERRYVIEW(dev_priv) &&
5889             max_pixclk > freq_320*limit/100)
5890                 return 400000;
5891         else if (max_pixclk > 266667*limit/100)
5892                 return freq_320;
5893         else if (max_pixclk > 0)
5894                 return 266667;
5895         else
5896                 return 200000;
5897 }
5898
5899 static int broxton_calc_cdclk(int max_pixclk)
5900 {
5901         /*
5902          * FIXME:
5903          * - set 19.2MHz bypass frequency if there are no active pipes
5904          */
5905         if (max_pixclk > 576000)
5906                 return 624000;
5907         else if (max_pixclk > 384000)
5908                 return 576000;
5909         else if (max_pixclk > 288000)
5910                 return 384000;
5911         else if (max_pixclk > 144000)
5912                 return 288000;
5913         else
5914                 return 144000;
5915 }
5916
5917 /* Compute the max pixel clock for new configuration. */
5918 static int intel_mode_max_pixclk(struct drm_device *dev,
5919                                  struct drm_atomic_state *state)
5920 {
5921         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5922         struct drm_i915_private *dev_priv = dev->dev_private;
5923         struct drm_crtc *crtc;
5924         struct drm_crtc_state *crtc_state;
5925         unsigned max_pixclk = 0, i;
5926         enum pipe pipe;
5927
5928         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5929                sizeof(intel_state->min_pixclk));
5930
5931         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5932                 int pixclk = 0;
5933
5934                 if (crtc_state->enable)
5935                         pixclk = crtc_state->adjusted_mode.crtc_clock;
5936
5937                 intel_state->min_pixclk[i] = pixclk;
5938         }
5939
5940         for_each_pipe(dev_priv, pipe)
5941                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5942
5943         return max_pixclk;
5944 }
5945
5946 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5947 {
5948         struct drm_device *dev = state->dev;
5949         struct drm_i915_private *dev_priv = dev->dev_private;
5950         int max_pixclk = intel_mode_max_pixclk(dev, state);
5951         struct intel_atomic_state *intel_state =
5952                 to_intel_atomic_state(state);
5953
5954         intel_state->cdclk = intel_state->dev_cdclk =
5955                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5956
5957         if (!intel_state->active_crtcs)
5958                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5959
5960         return 0;
5961 }
5962
5963 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5964 {
5965         int max_pixclk = ilk_max_pixel_rate(state);
5966         struct intel_atomic_state *intel_state =
5967                 to_intel_atomic_state(state);
5968
5969         intel_state->cdclk = intel_state->dev_cdclk =
5970                 broxton_calc_cdclk(max_pixclk);
5971
5972         if (!intel_state->active_crtcs)
5973                 intel_state->dev_cdclk = broxton_calc_cdclk(0);
5974
5975         return 0;
5976 }
5977
5978 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5979 {
5980         unsigned int credits, default_credits;
5981
5982         if (IS_CHERRYVIEW(dev_priv))
5983                 default_credits = PFI_CREDIT(12);
5984         else
5985                 default_credits = PFI_CREDIT(8);
5986
5987         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
5988                 /* CHV suggested value is 31 or 63 */
5989                 if (IS_CHERRYVIEW(dev_priv))
5990                         credits = PFI_CREDIT_63;
5991                 else
5992                         credits = PFI_CREDIT(15);
5993         } else {
5994                 credits = default_credits;
5995         }
5996
5997         /*
5998          * WA - write default credits before re-programming
5999          * FIXME: should we also set the resend bit here?
6000          */
6001         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6002                    default_credits);
6003
6004         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6005                    credits | PFI_CREDIT_RESEND);
6006
6007         /*
6008          * FIXME is this guaranteed to clear
6009          * immediately or should we poll for it?
6010          */
6011         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6012 }
6013
6014 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6015 {
6016         struct drm_device *dev = old_state->dev;
6017         struct drm_i915_private *dev_priv = dev->dev_private;
6018         struct intel_atomic_state *old_intel_state =
6019                 to_intel_atomic_state(old_state);
6020         unsigned req_cdclk = old_intel_state->dev_cdclk;
6021
6022         /*
6023          * FIXME: We can end up here with all power domains off, yet
6024          * with a CDCLK frequency other than the minimum. To account
6025          * for this take the PIPE-A power domain, which covers the HW
6026          * blocks needed for the following programming. This can be
6027          * removed once it's guaranteed that we get here either with
6028          * the minimum CDCLK set, or the required power domains
6029          * enabled.
6030          */
6031         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6032
6033         if (IS_CHERRYVIEW(dev))
6034                 cherryview_set_cdclk(dev, req_cdclk);
6035         else
6036                 valleyview_set_cdclk(dev, req_cdclk);
6037
6038         vlv_program_pfi_credits(dev_priv);
6039
6040         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6041 }
6042
6043 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6044 {
6045         struct drm_device *dev = crtc->dev;
6046         struct drm_i915_private *dev_priv = to_i915(dev);
6047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6048         struct intel_encoder *encoder;
6049         struct intel_crtc_state *pipe_config =
6050                 to_intel_crtc_state(crtc->state);
6051         int pipe = intel_crtc->pipe;
6052
6053         if (WARN_ON(intel_crtc->active))
6054                 return;
6055
6056         if (intel_crtc->config->has_dp_encoder)
6057                 intel_dp_set_m_n(intel_crtc, M1_N1);
6058
6059         intel_set_pipe_timings(intel_crtc);
6060         intel_set_pipe_src_size(intel_crtc);
6061
6062         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6063                 struct drm_i915_private *dev_priv = dev->dev_private;
6064
6065                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6066                 I915_WRITE(CHV_CANVAS(pipe), 0);
6067         }
6068
6069         i9xx_set_pipeconf(intel_crtc);
6070
6071         intel_crtc->active = true;
6072
6073         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6074
6075         for_each_encoder_on_crtc(dev, crtc, encoder)
6076                 if (encoder->pre_pll_enable)
6077                         encoder->pre_pll_enable(encoder);
6078
6079         if (IS_CHERRYVIEW(dev)) {
6080                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6081                 chv_enable_pll(intel_crtc, intel_crtc->config);
6082         } else {
6083                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6084                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6085         }
6086
6087         for_each_encoder_on_crtc(dev, crtc, encoder)
6088                 if (encoder->pre_enable)
6089                         encoder->pre_enable(encoder);
6090
6091         i9xx_pfit_enable(intel_crtc);
6092
6093         intel_color_load_luts(&pipe_config->base);
6094
6095         intel_update_watermarks(crtc);
6096         intel_enable_pipe(intel_crtc);
6097
6098         assert_vblank_disabled(crtc);
6099         drm_crtc_vblank_on(crtc);
6100
6101         for_each_encoder_on_crtc(dev, crtc, encoder)
6102                 encoder->enable(encoder);
6103 }
6104
6105 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6106 {
6107         struct drm_device *dev = crtc->base.dev;
6108         struct drm_i915_private *dev_priv = dev->dev_private;
6109
6110         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6111         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6112 }
6113
6114 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6115 {
6116         struct drm_device *dev = crtc->dev;
6117         struct drm_i915_private *dev_priv = to_i915(dev);
6118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6119         struct intel_encoder *encoder;
6120         struct intel_crtc_state *pipe_config =
6121                 to_intel_crtc_state(crtc->state);
6122         enum pipe pipe = intel_crtc->pipe;
6123
6124         if (WARN_ON(intel_crtc->active))
6125                 return;
6126
6127         i9xx_set_pll_dividers(intel_crtc);
6128
6129         if (intel_crtc->config->has_dp_encoder)
6130                 intel_dp_set_m_n(intel_crtc, M1_N1);
6131
6132         intel_set_pipe_timings(intel_crtc);
6133         intel_set_pipe_src_size(intel_crtc);
6134
6135         i9xx_set_pipeconf(intel_crtc);
6136
6137         intel_crtc->active = true;
6138
6139         if (!IS_GEN2(dev))
6140                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6141
6142         for_each_encoder_on_crtc(dev, crtc, encoder)
6143                 if (encoder->pre_enable)
6144                         encoder->pre_enable(encoder);
6145
6146         i9xx_enable_pll(intel_crtc);
6147
6148         i9xx_pfit_enable(intel_crtc);
6149
6150         intel_color_load_luts(&pipe_config->base);
6151
6152         intel_update_watermarks(crtc);
6153         intel_enable_pipe(intel_crtc);
6154
6155         assert_vblank_disabled(crtc);
6156         drm_crtc_vblank_on(crtc);
6157
6158         for_each_encoder_on_crtc(dev, crtc, encoder)
6159                 encoder->enable(encoder);
6160 }
6161
6162 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6163 {
6164         struct drm_device *dev = crtc->base.dev;
6165         struct drm_i915_private *dev_priv = dev->dev_private;
6166
6167         if (!crtc->config->gmch_pfit.control)
6168                 return;
6169
6170         assert_pipe_disabled(dev_priv, crtc->pipe);
6171
6172         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6173                          I915_READ(PFIT_CONTROL));
6174         I915_WRITE(PFIT_CONTROL, 0);
6175 }
6176
6177 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6178 {
6179         struct drm_device *dev = crtc->dev;
6180         struct drm_i915_private *dev_priv = dev->dev_private;
6181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6182         struct intel_encoder *encoder;
6183         int pipe = intel_crtc->pipe;
6184
6185         /*
6186          * On gen2 planes are double buffered but the pipe isn't, so we must
6187          * wait for planes to fully turn off before disabling the pipe.
6188          */
6189         if (IS_GEN2(dev))
6190                 intel_wait_for_vblank(dev, pipe);
6191
6192         for_each_encoder_on_crtc(dev, crtc, encoder)
6193                 encoder->disable(encoder);
6194
6195         drm_crtc_vblank_off(crtc);
6196         assert_vblank_disabled(crtc);
6197
6198         intel_disable_pipe(intel_crtc);
6199
6200         i9xx_pfit_disable(intel_crtc);
6201
6202         for_each_encoder_on_crtc(dev, crtc, encoder)
6203                 if (encoder->post_disable)
6204                         encoder->post_disable(encoder);
6205
6206         if (!intel_crtc->config->has_dsi_encoder) {
6207                 if (IS_CHERRYVIEW(dev))
6208                         chv_disable_pll(dev_priv, pipe);
6209                 else if (IS_VALLEYVIEW(dev))
6210                         vlv_disable_pll(dev_priv, pipe);
6211                 else
6212                         i9xx_disable_pll(intel_crtc);
6213         }
6214
6215         for_each_encoder_on_crtc(dev, crtc, encoder)
6216                 if (encoder->post_pll_disable)
6217                         encoder->post_pll_disable(encoder);
6218
6219         if (!IS_GEN2(dev))
6220                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6221 }
6222
6223 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6224 {
6225         struct intel_encoder *encoder;
6226         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6227         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6228         enum intel_display_power_domain domain;
6229         unsigned long domains;
6230
6231         if (!intel_crtc->active)
6232                 return;
6233
6234         if (to_intel_plane_state(crtc->primary->state)->visible) {
6235                 WARN_ON(intel_crtc->unpin_work);
6236
6237                 intel_pre_disable_primary_noatomic(crtc);
6238
6239                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6240                 to_intel_plane_state(crtc->primary->state)->visible = false;
6241         }
6242
6243         dev_priv->display.crtc_disable(crtc);
6244
6245         DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6246                       crtc->base.id);
6247
6248         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6249         crtc->state->active = false;
6250         intel_crtc->active = false;
6251         crtc->enabled = false;
6252         crtc->state->connector_mask = 0;
6253         crtc->state->encoder_mask = 0;
6254
6255         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6256                 encoder->base.crtc = NULL;
6257
6258         intel_fbc_disable(intel_crtc);
6259         intel_update_watermarks(crtc);
6260         intel_disable_shared_dpll(intel_crtc);
6261
6262         domains = intel_crtc->enabled_power_domains;
6263         for_each_power_domain(domain, domains)
6264                 intel_display_power_put(dev_priv, domain);
6265         intel_crtc->enabled_power_domains = 0;
6266
6267         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6268         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6269 }
6270
6271 /*
6272  * turn all crtc's off, but do not adjust state
6273  * This has to be paired with a call to intel_modeset_setup_hw_state.
6274  */
6275 int intel_display_suspend(struct drm_device *dev)
6276 {
6277         struct drm_i915_private *dev_priv = to_i915(dev);
6278         struct drm_atomic_state *state;
6279         int ret;
6280
6281         state = drm_atomic_helper_suspend(dev);
6282         ret = PTR_ERR_OR_ZERO(state);
6283         if (ret)
6284                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6285         else
6286                 dev_priv->modeset_restore_state = state;
6287         return ret;
6288 }
6289
6290 void intel_encoder_destroy(struct drm_encoder *encoder)
6291 {
6292         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6293
6294         drm_encoder_cleanup(encoder);
6295         kfree(intel_encoder);
6296 }
6297
6298 /* Cross check the actual hw state with our own modeset state tracking (and it's
6299  * internal consistency). */
6300 static void intel_connector_verify_state(struct intel_connector *connector)
6301 {
6302         struct drm_crtc *crtc = connector->base.state->crtc;
6303
6304         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6305                       connector->base.base.id,
6306                       connector->base.name);
6307
6308         if (connector->get_hw_state(connector)) {
6309                 struct intel_encoder *encoder = connector->encoder;
6310                 struct drm_connector_state *conn_state = connector->base.state;
6311
6312                 I915_STATE_WARN(!crtc,
6313                          "connector enabled without attached crtc\n");
6314
6315                 if (!crtc)
6316                         return;
6317
6318                 I915_STATE_WARN(!crtc->state->active,
6319                       "connector is active, but attached crtc isn't\n");
6320
6321                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6322                         return;
6323
6324                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6325                         "atomic encoder doesn't match attached encoder\n");
6326
6327                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6328                         "attached encoder crtc differs from connector crtc\n");
6329         } else {
6330                 I915_STATE_WARN(crtc && crtc->state->active,
6331                         "attached crtc is active, but connector isn't\n");
6332                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6333                         "best encoder set without crtc!\n");
6334         }
6335 }
6336
6337 int intel_connector_init(struct intel_connector *connector)
6338 {
6339         drm_atomic_helper_connector_reset(&connector->base);
6340
6341         if (!connector->base.state)
6342                 return -ENOMEM;
6343
6344         return 0;
6345 }
6346
6347 struct intel_connector *intel_connector_alloc(void)
6348 {
6349         struct intel_connector *connector;
6350
6351         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6352         if (!connector)
6353                 return NULL;
6354
6355         if (intel_connector_init(connector) < 0) {
6356                 kfree(connector);
6357                 return NULL;
6358         }
6359
6360         return connector;
6361 }
6362
6363 /* Simple connector->get_hw_state implementation for encoders that support only
6364  * one connector and no cloning and hence the encoder state determines the state
6365  * of the connector. */
6366 bool intel_connector_get_hw_state(struct intel_connector *connector)
6367 {
6368         enum pipe pipe = 0;
6369         struct intel_encoder *encoder = connector->encoder;
6370
6371         return encoder->get_hw_state(encoder, &pipe);
6372 }
6373
6374 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6375 {
6376         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6377                 return crtc_state->fdi_lanes;
6378
6379         return 0;
6380 }
6381
6382 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6383                                      struct intel_crtc_state *pipe_config)
6384 {
6385         struct drm_atomic_state *state = pipe_config->base.state;
6386         struct intel_crtc *other_crtc;
6387         struct intel_crtc_state *other_crtc_state;
6388
6389         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6390                       pipe_name(pipe), pipe_config->fdi_lanes);
6391         if (pipe_config->fdi_lanes > 4) {
6392                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6393                               pipe_name(pipe), pipe_config->fdi_lanes);
6394                 return -EINVAL;
6395         }
6396
6397         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6398                 if (pipe_config->fdi_lanes > 2) {
6399                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6400                                       pipe_config->fdi_lanes);
6401                         return -EINVAL;
6402                 } else {
6403                         return 0;
6404                 }
6405         }
6406
6407         if (INTEL_INFO(dev)->num_pipes == 2)
6408                 return 0;
6409
6410         /* Ivybridge 3 pipe is really complicated */
6411         switch (pipe) {
6412         case PIPE_A:
6413                 return 0;
6414         case PIPE_B:
6415                 if (pipe_config->fdi_lanes <= 2)
6416                         return 0;
6417
6418                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6419                 other_crtc_state =
6420                         intel_atomic_get_crtc_state(state, other_crtc);
6421                 if (IS_ERR(other_crtc_state))
6422                         return PTR_ERR(other_crtc_state);
6423
6424                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6425                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6426                                       pipe_name(pipe), pipe_config->fdi_lanes);
6427                         return -EINVAL;
6428                 }
6429                 return 0;
6430         case PIPE_C:
6431                 if (pipe_config->fdi_lanes > 2) {
6432                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6433                                       pipe_name(pipe), pipe_config->fdi_lanes);
6434                         return -EINVAL;
6435                 }
6436
6437                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6438                 other_crtc_state =
6439                         intel_atomic_get_crtc_state(state, other_crtc);
6440                 if (IS_ERR(other_crtc_state))
6441                         return PTR_ERR(other_crtc_state);
6442
6443                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6444                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6445                         return -EINVAL;
6446                 }
6447                 return 0;
6448         default:
6449                 BUG();
6450         }
6451 }
6452
6453 #define RETRY 1
6454 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6455                                        struct intel_crtc_state *pipe_config)
6456 {
6457         struct drm_device *dev = intel_crtc->base.dev;
6458         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6459         int lane, link_bw, fdi_dotclock, ret;
6460         bool needs_recompute = false;
6461
6462 retry:
6463         /* FDI is a binary signal running at ~2.7GHz, encoding
6464          * each output octet as 10 bits. The actual frequency
6465          * is stored as a divider into a 100MHz clock, and the
6466          * mode pixel clock is stored in units of 1KHz.
6467          * Hence the bw of each lane in terms of the mode signal
6468          * is:
6469          */
6470         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6471
6472         fdi_dotclock = adjusted_mode->crtc_clock;
6473
6474         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6475                                            pipe_config->pipe_bpp);
6476
6477         pipe_config->fdi_lanes = lane;
6478
6479         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6480                                link_bw, &pipe_config->fdi_m_n);
6481
6482         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6483         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6484                 pipe_config->pipe_bpp -= 2*3;
6485                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6486                               pipe_config->pipe_bpp);
6487                 needs_recompute = true;
6488                 pipe_config->bw_constrained = true;
6489
6490                 goto retry;
6491         }
6492
6493         if (needs_recompute)
6494                 return RETRY;
6495
6496         return ret;
6497 }
6498
6499 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6500                                      struct intel_crtc_state *pipe_config)
6501 {
6502         if (pipe_config->pipe_bpp > 24)
6503                 return false;
6504
6505         /* HSW can handle pixel rate up to cdclk? */
6506         if (IS_HASWELL(dev_priv))
6507                 return true;
6508
6509         /*
6510          * We compare against max which means we must take
6511          * the increased cdclk requirement into account when
6512          * calculating the new cdclk.
6513          *
6514          * Should measure whether using a lower cdclk w/o IPS
6515          */
6516         return ilk_pipe_pixel_rate(pipe_config) <=
6517                 dev_priv->max_cdclk_freq * 95 / 100;
6518 }
6519
6520 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6521                                    struct intel_crtc_state *pipe_config)
6522 {
6523         struct drm_device *dev = crtc->base.dev;
6524         struct drm_i915_private *dev_priv = dev->dev_private;
6525
6526         pipe_config->ips_enabled = i915.enable_ips &&
6527                 hsw_crtc_supports_ips(crtc) &&
6528                 pipe_config_supports_ips(dev_priv, pipe_config);
6529 }
6530
6531 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6532 {
6533         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6534
6535         /* GDG double wide on either pipe, otherwise pipe A only */
6536         return INTEL_INFO(dev_priv)->gen < 4 &&
6537                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6538 }
6539
6540 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6541                                      struct intel_crtc_state *pipe_config)
6542 {
6543         struct drm_device *dev = crtc->base.dev;
6544         struct drm_i915_private *dev_priv = dev->dev_private;
6545         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6546
6547         /* FIXME should check pixel clock limits on all platforms */
6548         if (INTEL_INFO(dev)->gen < 4) {
6549                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6550
6551                 /*
6552                  * Enable double wide mode when the dot clock
6553                  * is > 90% of the (display) core speed.
6554                  */
6555                 if (intel_crtc_supports_double_wide(crtc) &&
6556                     adjusted_mode->crtc_clock > clock_limit) {
6557                         clock_limit *= 2;
6558                         pipe_config->double_wide = true;
6559                 }
6560
6561                 if (adjusted_mode->crtc_clock > clock_limit) {
6562                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6563                                       adjusted_mode->crtc_clock, clock_limit,
6564                                       yesno(pipe_config->double_wide));
6565                         return -EINVAL;
6566                 }
6567         }
6568
6569         /*
6570          * Pipe horizontal size must be even in:
6571          * - DVO ganged mode
6572          * - LVDS dual channel mode
6573          * - Double wide pipe
6574          */
6575         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6576              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6577                 pipe_config->pipe_src_w &= ~1;
6578
6579         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6580          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6581          */
6582         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6583                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6584                 return -EINVAL;
6585
6586         if (HAS_IPS(dev))
6587                 hsw_compute_ips_config(crtc, pipe_config);
6588
6589         if (pipe_config->has_pch_encoder)
6590                 return ironlake_fdi_compute_config(crtc, pipe_config);
6591
6592         return 0;
6593 }
6594
6595 static int skylake_get_display_clock_speed(struct drm_device *dev)
6596 {
6597         struct drm_i915_private *dev_priv = to_i915(dev);
6598         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6599         uint32_t cdctl = I915_READ(CDCLK_CTL);
6600         uint32_t linkrate;
6601
6602         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6603                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6604
6605         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6606                 return 540000;
6607
6608         linkrate = (I915_READ(DPLL_CTRL1) &
6609                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6610
6611         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6612             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6613                 /* vco 8640 */
6614                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6615                 case CDCLK_FREQ_450_432:
6616                         return 432000;
6617                 case CDCLK_FREQ_337_308:
6618                         return 308570;
6619                 case CDCLK_FREQ_675_617:
6620                         return 617140;
6621                 default:
6622                         WARN(1, "Unknown cd freq selection\n");
6623                 }
6624         } else {
6625                 /* vco 8100 */
6626                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6627                 case CDCLK_FREQ_450_432:
6628                         return 450000;
6629                 case CDCLK_FREQ_337_308:
6630                         return 337500;
6631                 case CDCLK_FREQ_675_617:
6632                         return 675000;
6633                 default:
6634                         WARN(1, "Unknown cd freq selection\n");
6635                 }
6636         }
6637
6638         /* error case, do as if DPLL0 isn't enabled */
6639         return 24000;
6640 }
6641
6642 static int broxton_get_display_clock_speed(struct drm_device *dev)
6643 {
6644         struct drm_i915_private *dev_priv = to_i915(dev);
6645         uint32_t cdctl = I915_READ(CDCLK_CTL);
6646         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6647         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6648         int cdclk;
6649
6650         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6651                 return 19200;
6652
6653         cdclk = 19200 * pll_ratio / 2;
6654
6655         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6656         case BXT_CDCLK_CD2X_DIV_SEL_1:
6657                 return cdclk;  /* 576MHz or 624MHz */
6658         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6659                 return cdclk * 2 / 3; /* 384MHz */
6660         case BXT_CDCLK_CD2X_DIV_SEL_2:
6661                 return cdclk / 2; /* 288MHz */
6662         case BXT_CDCLK_CD2X_DIV_SEL_4:
6663                 return cdclk / 4; /* 144MHz */
6664         }
6665
6666         /* error case, do as if DE PLL isn't enabled */
6667         return 19200;
6668 }
6669
6670 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6671 {
6672         struct drm_i915_private *dev_priv = dev->dev_private;
6673         uint32_t lcpll = I915_READ(LCPLL_CTL);
6674         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6675
6676         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6677                 return 800000;
6678         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6679                 return 450000;
6680         else if (freq == LCPLL_CLK_FREQ_450)
6681                 return 450000;
6682         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6683                 return 540000;
6684         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6685                 return 337500;
6686         else
6687                 return 675000;
6688 }
6689
6690 static int haswell_get_display_clock_speed(struct drm_device *dev)
6691 {
6692         struct drm_i915_private *dev_priv = dev->dev_private;
6693         uint32_t lcpll = I915_READ(LCPLL_CTL);
6694         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6695
6696         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6697                 return 800000;
6698         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6699                 return 450000;
6700         else if (freq == LCPLL_CLK_FREQ_450)
6701                 return 450000;
6702         else if (IS_HSW_ULT(dev))
6703                 return 337500;
6704         else
6705                 return 540000;
6706 }
6707
6708 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6709 {
6710         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6711                                       CCK_DISPLAY_CLOCK_CONTROL);
6712 }
6713
6714 static int ilk_get_display_clock_speed(struct drm_device *dev)
6715 {
6716         return 450000;
6717 }
6718
6719 static int i945_get_display_clock_speed(struct drm_device *dev)
6720 {
6721         return 400000;
6722 }
6723
6724 static int i915_get_display_clock_speed(struct drm_device *dev)
6725 {
6726         return 333333;
6727 }
6728
6729 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6730 {
6731         return 200000;
6732 }
6733
6734 static int pnv_get_display_clock_speed(struct drm_device *dev)
6735 {
6736         u16 gcfgc = 0;
6737
6738         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6739
6740         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6741         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6742                 return 266667;
6743         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6744                 return 333333;
6745         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6746                 return 444444;
6747         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6748                 return 200000;
6749         default:
6750                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6751         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6752                 return 133333;
6753         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6754                 return 166667;
6755         }
6756 }
6757
6758 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6759 {
6760         u16 gcfgc = 0;
6761
6762         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6763
6764         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6765                 return 133333;
6766         else {
6767                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6768                 case GC_DISPLAY_CLOCK_333_MHZ:
6769                         return 333333;
6770                 default:
6771                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6772                         return 190000;
6773                 }
6774         }
6775 }
6776
6777 static int i865_get_display_clock_speed(struct drm_device *dev)
6778 {
6779         return 266667;
6780 }
6781
6782 static int i85x_get_display_clock_speed(struct drm_device *dev)
6783 {
6784         u16 hpllcc = 0;
6785
6786         /*
6787          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6788          * encoding is different :(
6789          * FIXME is this the right way to detect 852GM/852GMV?
6790          */
6791         if (dev->pdev->revision == 0x1)
6792                 return 133333;
6793
6794         pci_bus_read_config_word(dev->pdev->bus,
6795                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6796
6797         /* Assume that the hardware is in the high speed state.  This
6798          * should be the default.
6799          */
6800         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6801         case GC_CLOCK_133_200:
6802         case GC_CLOCK_133_200_2:
6803         case GC_CLOCK_100_200:
6804                 return 200000;
6805         case GC_CLOCK_166_250:
6806                 return 250000;
6807         case GC_CLOCK_100_133:
6808                 return 133333;
6809         case GC_CLOCK_133_266:
6810         case GC_CLOCK_133_266_2:
6811         case GC_CLOCK_166_266:
6812                 return 266667;
6813         }
6814
6815         /* Shouldn't happen */
6816         return 0;
6817 }
6818
6819 static int i830_get_display_clock_speed(struct drm_device *dev)
6820 {
6821         return 133333;
6822 }
6823
6824 static unsigned int intel_hpll_vco(struct drm_device *dev)
6825 {
6826         struct drm_i915_private *dev_priv = dev->dev_private;
6827         static const unsigned int blb_vco[8] = {
6828                 [0] = 3200000,
6829                 [1] = 4000000,
6830                 [2] = 5333333,
6831                 [3] = 4800000,
6832                 [4] = 6400000,
6833         };
6834         static const unsigned int pnv_vco[8] = {
6835                 [0] = 3200000,
6836                 [1] = 4000000,
6837                 [2] = 5333333,
6838                 [3] = 4800000,
6839                 [4] = 2666667,
6840         };
6841         static const unsigned int cl_vco[8] = {
6842                 [0] = 3200000,
6843                 [1] = 4000000,
6844                 [2] = 5333333,
6845                 [3] = 6400000,
6846                 [4] = 3333333,
6847                 [5] = 3566667,
6848                 [6] = 4266667,
6849         };
6850         static const unsigned int elk_vco[8] = {
6851                 [0] = 3200000,
6852                 [1] = 4000000,
6853                 [2] = 5333333,
6854                 [3] = 4800000,
6855         };
6856         static const unsigned int ctg_vco[8] = {
6857                 [0] = 3200000,
6858                 [1] = 4000000,
6859                 [2] = 5333333,
6860                 [3] = 6400000,
6861                 [4] = 2666667,
6862                 [5] = 4266667,
6863         };
6864         const unsigned int *vco_table;
6865         unsigned int vco;
6866         uint8_t tmp = 0;
6867
6868         /* FIXME other chipsets? */
6869         if (IS_GM45(dev))
6870                 vco_table = ctg_vco;
6871         else if (IS_G4X(dev))
6872                 vco_table = elk_vco;
6873         else if (IS_CRESTLINE(dev))
6874                 vco_table = cl_vco;
6875         else if (IS_PINEVIEW(dev))
6876                 vco_table = pnv_vco;
6877         else if (IS_G33(dev))
6878                 vco_table = blb_vco;
6879         else
6880                 return 0;
6881
6882         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6883
6884         vco = vco_table[tmp & 0x7];
6885         if (vco == 0)
6886                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6887         else
6888                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6889
6890         return vco;
6891 }
6892
6893 static int gm45_get_display_clock_speed(struct drm_device *dev)
6894 {
6895         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6896         uint16_t tmp = 0;
6897
6898         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6899
6900         cdclk_sel = (tmp >> 12) & 0x1;
6901
6902         switch (vco) {
6903         case 2666667:
6904         case 4000000:
6905         case 5333333:
6906                 return cdclk_sel ? 333333 : 222222;
6907         case 3200000:
6908                 return cdclk_sel ? 320000 : 228571;
6909         default:
6910                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6911                 return 222222;
6912         }
6913 }
6914
6915 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6916 {
6917         static const uint8_t div_3200[] = { 16, 10,  8 };
6918         static const uint8_t div_4000[] = { 20, 12, 10 };
6919         static const uint8_t div_5333[] = { 24, 16, 14 };
6920         const uint8_t *div_table;
6921         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6922         uint16_t tmp = 0;
6923
6924         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6925
6926         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6927
6928         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6929                 goto fail;
6930
6931         switch (vco) {
6932         case 3200000:
6933                 div_table = div_3200;
6934                 break;
6935         case 4000000:
6936                 div_table = div_4000;
6937                 break;
6938         case 5333333:
6939                 div_table = div_5333;
6940                 break;
6941         default:
6942                 goto fail;
6943         }
6944
6945         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6946
6947 fail:
6948         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6949         return 200000;
6950 }
6951
6952 static int g33_get_display_clock_speed(struct drm_device *dev)
6953 {
6954         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6955         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6956         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6957         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6958         const uint8_t *div_table;
6959         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6960         uint16_t tmp = 0;
6961
6962         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6963
6964         cdclk_sel = (tmp >> 4) & 0x7;
6965
6966         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6967                 goto fail;
6968
6969         switch (vco) {
6970         case 3200000:
6971                 div_table = div_3200;
6972                 break;
6973         case 4000000:
6974                 div_table = div_4000;
6975                 break;
6976         case 4800000:
6977                 div_table = div_4800;
6978                 break;
6979         case 5333333:
6980                 div_table = div_5333;
6981                 break;
6982         default:
6983                 goto fail;
6984         }
6985
6986         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6987
6988 fail:
6989         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6990         return 190476;
6991 }
6992
6993 static void
6994 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6995 {
6996         while (*num > DATA_LINK_M_N_MASK ||
6997                *den > DATA_LINK_M_N_MASK) {
6998                 *num >>= 1;
6999                 *den >>= 1;
7000         }
7001 }
7002
7003 static void compute_m_n(unsigned int m, unsigned int n,
7004                         uint32_t *ret_m, uint32_t *ret_n)
7005 {
7006         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7007         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7008         intel_reduce_m_n_ratio(ret_m, ret_n);
7009 }
7010
7011 void
7012 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7013                        int pixel_clock, int link_clock,
7014                        struct intel_link_m_n *m_n)
7015 {
7016         m_n->tu = 64;
7017
7018         compute_m_n(bits_per_pixel * pixel_clock,
7019                     link_clock * nlanes * 8,
7020                     &m_n->gmch_m, &m_n->gmch_n);
7021
7022         compute_m_n(pixel_clock, link_clock,
7023                     &m_n->link_m, &m_n->link_n);
7024 }
7025
7026 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7027 {
7028         if (i915.panel_use_ssc >= 0)
7029                 return i915.panel_use_ssc != 0;
7030         return dev_priv->vbt.lvds_use_ssc
7031                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7032 }
7033
7034 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7035 {
7036         return (1 << dpll->n) << 16 | dpll->m2;
7037 }
7038
7039 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7040 {
7041         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7042 }
7043
7044 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7045                                      struct intel_crtc_state *crtc_state,
7046                                      struct dpll *reduced_clock)
7047 {
7048         struct drm_device *dev = crtc->base.dev;
7049         u32 fp, fp2 = 0;
7050
7051         if (IS_PINEVIEW(dev)) {
7052                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7053                 if (reduced_clock)
7054                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7055         } else {
7056                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7057                 if (reduced_clock)
7058                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7059         }
7060
7061         crtc_state->dpll_hw_state.fp0 = fp;
7062
7063         crtc->lowfreq_avail = false;
7064         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7065             reduced_clock) {
7066                 crtc_state->dpll_hw_state.fp1 = fp2;
7067                 crtc->lowfreq_avail = true;
7068         } else {
7069                 crtc_state->dpll_hw_state.fp1 = fp;
7070         }
7071 }
7072
7073 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7074                 pipe)
7075 {
7076         u32 reg_val;
7077
7078         /*
7079          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7080          * and set it to a reasonable value instead.
7081          */
7082         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7083         reg_val &= 0xffffff00;
7084         reg_val |= 0x00000030;
7085         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7086
7087         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7088         reg_val &= 0x8cffffff;
7089         reg_val = 0x8c000000;
7090         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7091
7092         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7093         reg_val &= 0xffffff00;
7094         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7095
7096         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7097         reg_val &= 0x00ffffff;
7098         reg_val |= 0xb0000000;
7099         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7100 }
7101
7102 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7103                                          struct intel_link_m_n *m_n)
7104 {
7105         struct drm_device *dev = crtc->base.dev;
7106         struct drm_i915_private *dev_priv = dev->dev_private;
7107         int pipe = crtc->pipe;
7108
7109         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7110         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7111         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7112         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7113 }
7114
7115 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7116                                          struct intel_link_m_n *m_n,
7117                                          struct intel_link_m_n *m2_n2)
7118 {
7119         struct drm_device *dev = crtc->base.dev;
7120         struct drm_i915_private *dev_priv = dev->dev_private;
7121         int pipe = crtc->pipe;
7122         enum transcoder transcoder = crtc->config->cpu_transcoder;
7123
7124         if (INTEL_INFO(dev)->gen >= 5) {
7125                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7126                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7127                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7128                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7129                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7130                  * for gen < 8) and if DRRS is supported (to make sure the
7131                  * registers are not unnecessarily accessed).
7132                  */
7133                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7134                         crtc->config->has_drrs) {
7135                         I915_WRITE(PIPE_DATA_M2(transcoder),
7136                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7137                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7138                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7139                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7140                 }
7141         } else {
7142                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7143                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7144                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7145                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7146         }
7147 }
7148
7149 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7150 {
7151         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7152
7153         if (m_n == M1_N1) {
7154                 dp_m_n = &crtc->config->dp_m_n;
7155                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7156         } else if (m_n == M2_N2) {
7157
7158                 /*
7159                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7160                  * needs to be programmed into M1_N1.
7161                  */
7162                 dp_m_n = &crtc->config->dp_m2_n2;
7163         } else {
7164                 DRM_ERROR("Unsupported divider value\n");
7165                 return;
7166         }
7167
7168         if (crtc->config->has_pch_encoder)
7169                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7170         else
7171                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7172 }
7173
7174 static void vlv_compute_dpll(struct intel_crtc *crtc,
7175                              struct intel_crtc_state *pipe_config)
7176 {
7177         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7178                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7179         if (crtc->pipe != PIPE_A)
7180                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7181
7182         /* DPLL not used with DSI, but still need the rest set up */
7183         if (!pipe_config->has_dsi_encoder)
7184                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7185                         DPLL_EXT_BUFFER_ENABLE_VLV;
7186
7187         pipe_config->dpll_hw_state.dpll_md =
7188                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7189 }
7190
7191 static void chv_compute_dpll(struct intel_crtc *crtc,
7192                              struct intel_crtc_state *pipe_config)
7193 {
7194         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7195                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7196         if (crtc->pipe != PIPE_A)
7197                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7198
7199         /* DPLL not used with DSI, but still need the rest set up */
7200         if (!pipe_config->has_dsi_encoder)
7201                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7202
7203         pipe_config->dpll_hw_state.dpll_md =
7204                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7205 }
7206
7207 static void vlv_prepare_pll(struct intel_crtc *crtc,
7208                             const struct intel_crtc_state *pipe_config)
7209 {
7210         struct drm_device *dev = crtc->base.dev;
7211         struct drm_i915_private *dev_priv = dev->dev_private;
7212         enum pipe pipe = crtc->pipe;
7213         u32 mdiv;
7214         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7215         u32 coreclk, reg_val;
7216
7217         /* Enable Refclk */
7218         I915_WRITE(DPLL(pipe),
7219                    pipe_config->dpll_hw_state.dpll &
7220                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7221
7222         /* No need to actually set up the DPLL with DSI */
7223         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7224                 return;
7225
7226         mutex_lock(&dev_priv->sb_lock);
7227
7228         bestn = pipe_config->dpll.n;
7229         bestm1 = pipe_config->dpll.m1;
7230         bestm2 = pipe_config->dpll.m2;
7231         bestp1 = pipe_config->dpll.p1;
7232         bestp2 = pipe_config->dpll.p2;
7233
7234         /* See eDP HDMI DPIO driver vbios notes doc */
7235
7236         /* PLL B needs special handling */
7237         if (pipe == PIPE_B)
7238                 vlv_pllb_recal_opamp(dev_priv, pipe);
7239
7240         /* Set up Tx target for periodic Rcomp update */
7241         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7242
7243         /* Disable target IRef on PLL */
7244         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7245         reg_val &= 0x00ffffff;
7246         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7247
7248         /* Disable fast lock */
7249         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7250
7251         /* Set idtafcrecal before PLL is enabled */
7252         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7253         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7254         mdiv |= ((bestn << DPIO_N_SHIFT));
7255         mdiv |= (1 << DPIO_K_SHIFT);
7256
7257         /*
7258          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7259          * but we don't support that).
7260          * Note: don't use the DAC post divider as it seems unstable.
7261          */
7262         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7263         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7264
7265         mdiv |= DPIO_ENABLE_CALIBRATION;
7266         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7267
7268         /* Set HBR and RBR LPF coefficients */
7269         if (pipe_config->port_clock == 162000 ||
7270             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7271             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7272                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7273                                  0x009f0003);
7274         else
7275                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7276                                  0x00d0000f);
7277
7278         if (pipe_config->has_dp_encoder) {
7279                 /* Use SSC source */
7280                 if (pipe == PIPE_A)
7281                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7282                                          0x0df40000);
7283                 else
7284                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7285                                          0x0df70000);
7286         } else { /* HDMI or VGA */
7287                 /* Use bend source */
7288                 if (pipe == PIPE_A)
7289                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7290                                          0x0df70000);
7291                 else
7292                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7293                                          0x0df40000);
7294         }
7295
7296         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7297         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7298         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7299             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7300                 coreclk |= 0x01000000;
7301         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7302
7303         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7304         mutex_unlock(&dev_priv->sb_lock);
7305 }
7306
7307 static void chv_prepare_pll(struct intel_crtc *crtc,
7308                             const struct intel_crtc_state *pipe_config)
7309 {
7310         struct drm_device *dev = crtc->base.dev;
7311         struct drm_i915_private *dev_priv = dev->dev_private;
7312         enum pipe pipe = crtc->pipe;
7313         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7314         u32 loopfilter, tribuf_calcntr;
7315         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7316         u32 dpio_val;
7317         int vco;
7318
7319         /* Enable Refclk and SSC */
7320         I915_WRITE(DPLL(pipe),
7321                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7322
7323         /* No need to actually set up the DPLL with DSI */
7324         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7325                 return;
7326
7327         bestn = pipe_config->dpll.n;
7328         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7329         bestm1 = pipe_config->dpll.m1;
7330         bestm2 = pipe_config->dpll.m2 >> 22;
7331         bestp1 = pipe_config->dpll.p1;
7332         bestp2 = pipe_config->dpll.p2;
7333         vco = pipe_config->dpll.vco;
7334         dpio_val = 0;
7335         loopfilter = 0;
7336
7337         mutex_lock(&dev_priv->sb_lock);
7338
7339         /* p1 and p2 divider */
7340         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7341                         5 << DPIO_CHV_S1_DIV_SHIFT |
7342                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7343                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7344                         1 << DPIO_CHV_K_DIV_SHIFT);
7345
7346         /* Feedback post-divider - m2 */
7347         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7348
7349         /* Feedback refclk divider - n and m1 */
7350         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7351                         DPIO_CHV_M1_DIV_BY_2 |
7352                         1 << DPIO_CHV_N_DIV_SHIFT);
7353
7354         /* M2 fraction division */
7355         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7356
7357         /* M2 fraction division enable */
7358         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7359         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7360         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7361         if (bestm2_frac)
7362                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7363         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7364
7365         /* Program digital lock detect threshold */
7366         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7367         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7368                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7369         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7370         if (!bestm2_frac)
7371                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7372         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7373
7374         /* Loop filter */
7375         if (vco == 5400000) {
7376                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7377                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7378                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7379                 tribuf_calcntr = 0x9;
7380         } else if (vco <= 6200000) {
7381                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7382                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7383                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7384                 tribuf_calcntr = 0x9;
7385         } else if (vco <= 6480000) {
7386                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7387                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7388                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7389                 tribuf_calcntr = 0x8;
7390         } else {
7391                 /* Not supported. Apply the same limits as in the max case */
7392                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7393                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7394                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7395                 tribuf_calcntr = 0;
7396         }
7397         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7398
7399         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7400         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7401         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7402         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7403
7404         /* AFC Recal */
7405         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7406                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7407                         DPIO_AFC_RECAL);
7408
7409         mutex_unlock(&dev_priv->sb_lock);
7410 }
7411
7412 /**
7413  * vlv_force_pll_on - forcibly enable just the PLL
7414  * @dev_priv: i915 private structure
7415  * @pipe: pipe PLL to enable
7416  * @dpll: PLL configuration
7417  *
7418  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7419  * in cases where we need the PLL enabled even when @pipe is not going to
7420  * be enabled.
7421  */
7422 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7423                      const struct dpll *dpll)
7424 {
7425         struct intel_crtc *crtc =
7426                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7427         struct intel_crtc_state *pipe_config;
7428
7429         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7430         if (!pipe_config)
7431                 return -ENOMEM;
7432
7433         pipe_config->base.crtc = &crtc->base;
7434         pipe_config->pixel_multiplier = 1;
7435         pipe_config->dpll = *dpll;
7436
7437         if (IS_CHERRYVIEW(dev)) {
7438                 chv_compute_dpll(crtc, pipe_config);
7439                 chv_prepare_pll(crtc, pipe_config);
7440                 chv_enable_pll(crtc, pipe_config);
7441         } else {
7442                 vlv_compute_dpll(crtc, pipe_config);
7443                 vlv_prepare_pll(crtc, pipe_config);
7444                 vlv_enable_pll(crtc, pipe_config);
7445         }
7446
7447         kfree(pipe_config);
7448
7449         return 0;
7450 }
7451
7452 /**
7453  * vlv_force_pll_off - forcibly disable just the PLL
7454  * @dev_priv: i915 private structure
7455  * @pipe: pipe PLL to disable
7456  *
7457  * Disable the PLL for @pipe. To be used in cases where we need
7458  * the PLL enabled even when @pipe is not going to be enabled.
7459  */
7460 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7461 {
7462         if (IS_CHERRYVIEW(dev))
7463                 chv_disable_pll(to_i915(dev), pipe);
7464         else
7465                 vlv_disable_pll(to_i915(dev), pipe);
7466 }
7467
7468 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7469                               struct intel_crtc_state *crtc_state,
7470                               struct dpll *reduced_clock)
7471 {
7472         struct drm_device *dev = crtc->base.dev;
7473         struct drm_i915_private *dev_priv = dev->dev_private;
7474         u32 dpll;
7475         bool is_sdvo;
7476         struct dpll *clock = &crtc_state->dpll;
7477
7478         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7479
7480         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7481                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7482
7483         dpll = DPLL_VGA_MODE_DIS;
7484
7485         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7486                 dpll |= DPLLB_MODE_LVDS;
7487         else
7488                 dpll |= DPLLB_MODE_DAC_SERIAL;
7489
7490         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7491                 dpll |= (crtc_state->pixel_multiplier - 1)
7492                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7493         }
7494
7495         if (is_sdvo)
7496                 dpll |= DPLL_SDVO_HIGH_SPEED;
7497
7498         if (crtc_state->has_dp_encoder)
7499                 dpll |= DPLL_SDVO_HIGH_SPEED;
7500
7501         /* compute bitmask from p1 value */
7502         if (IS_PINEVIEW(dev))
7503                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7504         else {
7505                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7506                 if (IS_G4X(dev) && reduced_clock)
7507                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7508         }
7509         switch (clock->p2) {
7510         case 5:
7511                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7512                 break;
7513         case 7:
7514                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7515                 break;
7516         case 10:
7517                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7518                 break;
7519         case 14:
7520                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7521                 break;
7522         }
7523         if (INTEL_INFO(dev)->gen >= 4)
7524                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7525
7526         if (crtc_state->sdvo_tv_clock)
7527                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7528         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7529                  intel_panel_use_ssc(dev_priv))
7530                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7531         else
7532                 dpll |= PLL_REF_INPUT_DREFCLK;
7533
7534         dpll |= DPLL_VCO_ENABLE;
7535         crtc_state->dpll_hw_state.dpll = dpll;
7536
7537         if (INTEL_INFO(dev)->gen >= 4) {
7538                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7539                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7540                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7541         }
7542 }
7543
7544 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7545                               struct intel_crtc_state *crtc_state,
7546                               struct dpll *reduced_clock)
7547 {
7548         struct drm_device *dev = crtc->base.dev;
7549         struct drm_i915_private *dev_priv = dev->dev_private;
7550         u32 dpll;
7551         struct dpll *clock = &crtc_state->dpll;
7552
7553         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7554
7555         dpll = DPLL_VGA_MODE_DIS;
7556
7557         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7558                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7559         } else {
7560                 if (clock->p1 == 2)
7561                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7562                 else
7563                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7564                 if (clock->p2 == 4)
7565                         dpll |= PLL_P2_DIVIDE_BY_4;
7566         }
7567
7568         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7569                 dpll |= DPLL_DVO_2X_MODE;
7570
7571         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7572             intel_panel_use_ssc(dev_priv))
7573                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7574         else
7575                 dpll |= PLL_REF_INPUT_DREFCLK;
7576
7577         dpll |= DPLL_VCO_ENABLE;
7578         crtc_state->dpll_hw_state.dpll = dpll;
7579 }
7580
7581 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7582 {
7583         struct drm_device *dev = intel_crtc->base.dev;
7584         struct drm_i915_private *dev_priv = dev->dev_private;
7585         enum pipe pipe = intel_crtc->pipe;
7586         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7587         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7588         uint32_t crtc_vtotal, crtc_vblank_end;
7589         int vsyncshift = 0;
7590
7591         /* We need to be careful not to changed the adjusted mode, for otherwise
7592          * the hw state checker will get angry at the mismatch. */
7593         crtc_vtotal = adjusted_mode->crtc_vtotal;
7594         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7595
7596         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7597                 /* the chip adds 2 halflines automatically */
7598                 crtc_vtotal -= 1;
7599                 crtc_vblank_end -= 1;
7600
7601                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7602                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7603                 else
7604                         vsyncshift = adjusted_mode->crtc_hsync_start -
7605                                 adjusted_mode->crtc_htotal / 2;
7606                 if (vsyncshift < 0)
7607                         vsyncshift += adjusted_mode->crtc_htotal;
7608         }
7609
7610         if (INTEL_INFO(dev)->gen > 3)
7611                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7612
7613         I915_WRITE(HTOTAL(cpu_transcoder),
7614                    (adjusted_mode->crtc_hdisplay - 1) |
7615                    ((adjusted_mode->crtc_htotal - 1) << 16));
7616         I915_WRITE(HBLANK(cpu_transcoder),
7617                    (adjusted_mode->crtc_hblank_start - 1) |
7618                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7619         I915_WRITE(HSYNC(cpu_transcoder),
7620                    (adjusted_mode->crtc_hsync_start - 1) |
7621                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7622
7623         I915_WRITE(VTOTAL(cpu_transcoder),
7624                    (adjusted_mode->crtc_vdisplay - 1) |
7625                    ((crtc_vtotal - 1) << 16));
7626         I915_WRITE(VBLANK(cpu_transcoder),
7627                    (adjusted_mode->crtc_vblank_start - 1) |
7628                    ((crtc_vblank_end - 1) << 16));
7629         I915_WRITE(VSYNC(cpu_transcoder),
7630                    (adjusted_mode->crtc_vsync_start - 1) |
7631                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7632
7633         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7634          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7635          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7636          * bits. */
7637         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7638             (pipe == PIPE_B || pipe == PIPE_C))
7639                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7640
7641 }
7642
7643 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7644 {
7645         struct drm_device *dev = intel_crtc->base.dev;
7646         struct drm_i915_private *dev_priv = dev->dev_private;
7647         enum pipe pipe = intel_crtc->pipe;
7648
7649         /* pipesrc controls the size that is scaled from, which should
7650          * always be the user's requested size.
7651          */
7652         I915_WRITE(PIPESRC(pipe),
7653                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7654                    (intel_crtc->config->pipe_src_h - 1));
7655 }
7656
7657 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7658                                    struct intel_crtc_state *pipe_config)
7659 {
7660         struct drm_device *dev = crtc->base.dev;
7661         struct drm_i915_private *dev_priv = dev->dev_private;
7662         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7663         uint32_t tmp;
7664
7665         tmp = I915_READ(HTOTAL(cpu_transcoder));
7666         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7667         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7668         tmp = I915_READ(HBLANK(cpu_transcoder));
7669         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7670         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7671         tmp = I915_READ(HSYNC(cpu_transcoder));
7672         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7673         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7674
7675         tmp = I915_READ(VTOTAL(cpu_transcoder));
7676         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7677         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7678         tmp = I915_READ(VBLANK(cpu_transcoder));
7679         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7680         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7681         tmp = I915_READ(VSYNC(cpu_transcoder));
7682         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7683         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7684
7685         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7686                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7687                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7688                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7689         }
7690 }
7691
7692 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7693                                     struct intel_crtc_state *pipe_config)
7694 {
7695         struct drm_device *dev = crtc->base.dev;
7696         struct drm_i915_private *dev_priv = dev->dev_private;
7697         u32 tmp;
7698
7699         tmp = I915_READ(PIPESRC(crtc->pipe));
7700         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7701         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7702
7703         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7704         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7705 }
7706
7707 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7708                                  struct intel_crtc_state *pipe_config)
7709 {
7710         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7711         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7712         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7713         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7714
7715         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7716         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7717         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7718         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7719
7720         mode->flags = pipe_config->base.adjusted_mode.flags;
7721         mode->type = DRM_MODE_TYPE_DRIVER;
7722
7723         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7724         mode->flags |= pipe_config->base.adjusted_mode.flags;
7725
7726         mode->hsync = drm_mode_hsync(mode);
7727         mode->vrefresh = drm_mode_vrefresh(mode);
7728         drm_mode_set_name(mode);
7729 }
7730
7731 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7732 {
7733         struct drm_device *dev = intel_crtc->base.dev;
7734         struct drm_i915_private *dev_priv = dev->dev_private;
7735         uint32_t pipeconf;
7736
7737         pipeconf = 0;
7738
7739         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7740             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7741                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7742
7743         if (intel_crtc->config->double_wide)
7744                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7745
7746         /* only g4x and later have fancy bpc/dither controls */
7747         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7748                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7749                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7750                         pipeconf |= PIPECONF_DITHER_EN |
7751                                     PIPECONF_DITHER_TYPE_SP;
7752
7753                 switch (intel_crtc->config->pipe_bpp) {
7754                 case 18:
7755                         pipeconf |= PIPECONF_6BPC;
7756                         break;
7757                 case 24:
7758                         pipeconf |= PIPECONF_8BPC;
7759                         break;
7760                 case 30:
7761                         pipeconf |= PIPECONF_10BPC;
7762                         break;
7763                 default:
7764                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7765                         BUG();
7766                 }
7767         }
7768
7769         if (HAS_PIPE_CXSR(dev)) {
7770                 if (intel_crtc->lowfreq_avail) {
7771                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7772                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7773                 } else {
7774                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7775                 }
7776         }
7777
7778         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7779                 if (INTEL_INFO(dev)->gen < 4 ||
7780                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7781                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7782                 else
7783                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7784         } else
7785                 pipeconf |= PIPECONF_PROGRESSIVE;
7786
7787         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7788              intel_crtc->config->limited_color_range)
7789                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7790
7791         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7792         POSTING_READ(PIPECONF(intel_crtc->pipe));
7793 }
7794
7795 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7796                                    struct intel_crtc_state *crtc_state)
7797 {
7798         struct drm_device *dev = crtc->base.dev;
7799         struct drm_i915_private *dev_priv = dev->dev_private;
7800         const struct intel_limit *limit;
7801         int refclk = 48000;
7802
7803         memset(&crtc_state->dpll_hw_state, 0,
7804                sizeof(crtc_state->dpll_hw_state));
7805
7806         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7807                 if (intel_panel_use_ssc(dev_priv)) {
7808                         refclk = dev_priv->vbt.lvds_ssc_freq;
7809                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7810                 }
7811
7812                 limit = &intel_limits_i8xx_lvds;
7813         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7814                 limit = &intel_limits_i8xx_dvo;
7815         } else {
7816                 limit = &intel_limits_i8xx_dac;
7817         }
7818
7819         if (!crtc_state->clock_set &&
7820             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7821                                  refclk, NULL, &crtc_state->dpll)) {
7822                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7823                 return -EINVAL;
7824         }
7825
7826         i8xx_compute_dpll(crtc, crtc_state, NULL);
7827
7828         return 0;
7829 }
7830
7831 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7832                                   struct intel_crtc_state *crtc_state)
7833 {
7834         struct drm_device *dev = crtc->base.dev;
7835         struct drm_i915_private *dev_priv = dev->dev_private;
7836         const struct intel_limit *limit;
7837         int refclk = 96000;
7838
7839         memset(&crtc_state->dpll_hw_state, 0,
7840                sizeof(crtc_state->dpll_hw_state));
7841
7842         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7843                 if (intel_panel_use_ssc(dev_priv)) {
7844                         refclk = dev_priv->vbt.lvds_ssc_freq;
7845                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7846                 }
7847
7848                 if (intel_is_dual_link_lvds(dev))
7849                         limit = &intel_limits_g4x_dual_channel_lvds;
7850                 else
7851                         limit = &intel_limits_g4x_single_channel_lvds;
7852         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7853                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7854                 limit = &intel_limits_g4x_hdmi;
7855         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7856                 limit = &intel_limits_g4x_sdvo;
7857         } else {
7858                 /* The option is for other outputs */
7859                 limit = &intel_limits_i9xx_sdvo;
7860         }
7861
7862         if (!crtc_state->clock_set &&
7863             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7864                                 refclk, NULL, &crtc_state->dpll)) {
7865                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7866                 return -EINVAL;
7867         }
7868
7869         i9xx_compute_dpll(crtc, crtc_state, NULL);
7870
7871         return 0;
7872 }
7873
7874 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7875                                   struct intel_crtc_state *crtc_state)
7876 {
7877         struct drm_device *dev = crtc->base.dev;
7878         struct drm_i915_private *dev_priv = dev->dev_private;
7879         const struct intel_limit *limit;
7880         int refclk = 96000;
7881
7882         memset(&crtc_state->dpll_hw_state, 0,
7883                sizeof(crtc_state->dpll_hw_state));
7884
7885         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7886                 if (intel_panel_use_ssc(dev_priv)) {
7887                         refclk = dev_priv->vbt.lvds_ssc_freq;
7888                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7889                 }
7890
7891                 limit = &intel_limits_pineview_lvds;
7892         } else {
7893                 limit = &intel_limits_pineview_sdvo;
7894         }
7895
7896         if (!crtc_state->clock_set &&
7897             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7898                                 refclk, NULL, &crtc_state->dpll)) {
7899                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7900                 return -EINVAL;
7901         }
7902
7903         i9xx_compute_dpll(crtc, crtc_state, NULL);
7904
7905         return 0;
7906 }
7907
7908 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7909                                    struct intel_crtc_state *crtc_state)
7910 {
7911         struct drm_device *dev = crtc->base.dev;
7912         struct drm_i915_private *dev_priv = dev->dev_private;
7913         const struct intel_limit *limit;
7914         int refclk = 96000;
7915
7916         memset(&crtc_state->dpll_hw_state, 0,
7917                sizeof(crtc_state->dpll_hw_state));
7918
7919         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7920                 if (intel_panel_use_ssc(dev_priv)) {
7921                         refclk = dev_priv->vbt.lvds_ssc_freq;
7922                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7923                 }
7924
7925                 limit = &intel_limits_i9xx_lvds;
7926         } else {
7927                 limit = &intel_limits_i9xx_sdvo;
7928         }
7929
7930         if (!crtc_state->clock_set &&
7931             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7932                                  refclk, NULL, &crtc_state->dpll)) {
7933                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7934                 return -EINVAL;
7935         }
7936
7937         i9xx_compute_dpll(crtc, crtc_state, NULL);
7938
7939         return 0;
7940 }
7941
7942 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7943                                   struct intel_crtc_state *crtc_state)
7944 {
7945         int refclk = 100000;
7946         const struct intel_limit *limit = &intel_limits_chv;
7947
7948         memset(&crtc_state->dpll_hw_state, 0,
7949                sizeof(crtc_state->dpll_hw_state));
7950
7951         if (!crtc_state->clock_set &&
7952             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7953                                 refclk, NULL, &crtc_state->dpll)) {
7954                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7955                 return -EINVAL;
7956         }
7957
7958         chv_compute_dpll(crtc, crtc_state);
7959
7960         return 0;
7961 }
7962
7963 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7964                                   struct intel_crtc_state *crtc_state)
7965 {
7966         int refclk = 100000;
7967         const struct intel_limit *limit = &intel_limits_vlv;
7968
7969         memset(&crtc_state->dpll_hw_state, 0,
7970                sizeof(crtc_state->dpll_hw_state));
7971
7972         if (!crtc_state->clock_set &&
7973             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7974                                 refclk, NULL, &crtc_state->dpll)) {
7975                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7976                 return -EINVAL;
7977         }
7978
7979         vlv_compute_dpll(crtc, crtc_state);
7980
7981         return 0;
7982 }
7983
7984 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7985                                  struct intel_crtc_state *pipe_config)
7986 {
7987         struct drm_device *dev = crtc->base.dev;
7988         struct drm_i915_private *dev_priv = dev->dev_private;
7989         uint32_t tmp;
7990
7991         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7992                 return;
7993
7994         tmp = I915_READ(PFIT_CONTROL);
7995         if (!(tmp & PFIT_ENABLE))
7996                 return;
7997
7998         /* Check whether the pfit is attached to our pipe. */
7999         if (INTEL_INFO(dev)->gen < 4) {
8000                 if (crtc->pipe != PIPE_B)
8001                         return;
8002         } else {
8003                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8004                         return;
8005         }
8006
8007         pipe_config->gmch_pfit.control = tmp;
8008         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8009 }
8010
8011 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8012                                struct intel_crtc_state *pipe_config)
8013 {
8014         struct drm_device *dev = crtc->base.dev;
8015         struct drm_i915_private *dev_priv = dev->dev_private;
8016         int pipe = pipe_config->cpu_transcoder;
8017         struct dpll clock;
8018         u32 mdiv;
8019         int refclk = 100000;
8020
8021         /* In case of DSI, DPLL will not be used */
8022         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8023                 return;
8024
8025         mutex_lock(&dev_priv->sb_lock);
8026         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8027         mutex_unlock(&dev_priv->sb_lock);
8028
8029         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8030         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8031         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8032         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8033         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8034
8035         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8036 }
8037
8038 static void
8039 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8040                               struct intel_initial_plane_config *plane_config)
8041 {
8042         struct drm_device *dev = crtc->base.dev;
8043         struct drm_i915_private *dev_priv = dev->dev_private;
8044         u32 val, base, offset;
8045         int pipe = crtc->pipe, plane = crtc->plane;
8046         int fourcc, pixel_format;
8047         unsigned int aligned_height;
8048         struct drm_framebuffer *fb;
8049         struct intel_framebuffer *intel_fb;
8050
8051         val = I915_READ(DSPCNTR(plane));
8052         if (!(val & DISPLAY_PLANE_ENABLE))
8053                 return;
8054
8055         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8056         if (!intel_fb) {
8057                 DRM_DEBUG_KMS("failed to alloc fb\n");
8058                 return;
8059         }
8060
8061         fb = &intel_fb->base;
8062
8063         if (INTEL_INFO(dev)->gen >= 4) {
8064                 if (val & DISPPLANE_TILED) {
8065                         plane_config->tiling = I915_TILING_X;
8066                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8067                 }
8068         }
8069
8070         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8071         fourcc = i9xx_format_to_fourcc(pixel_format);
8072         fb->pixel_format = fourcc;
8073         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8074
8075         if (INTEL_INFO(dev)->gen >= 4) {
8076                 if (plane_config->tiling)
8077                         offset = I915_READ(DSPTILEOFF(plane));
8078                 else
8079                         offset = I915_READ(DSPLINOFF(plane));
8080                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8081         } else {
8082                 base = I915_READ(DSPADDR(plane));
8083         }
8084         plane_config->base = base;
8085
8086         val = I915_READ(PIPESRC(pipe));
8087         fb->width = ((val >> 16) & 0xfff) + 1;
8088         fb->height = ((val >> 0) & 0xfff) + 1;
8089
8090         val = I915_READ(DSPSTRIDE(pipe));
8091         fb->pitches[0] = val & 0xffffffc0;
8092
8093         aligned_height = intel_fb_align_height(dev, fb->height,
8094                                                fb->pixel_format,
8095                                                fb->modifier[0]);
8096
8097         plane_config->size = fb->pitches[0] * aligned_height;
8098
8099         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8100                       pipe_name(pipe), plane, fb->width, fb->height,
8101                       fb->bits_per_pixel, base, fb->pitches[0],
8102                       plane_config->size);
8103
8104         plane_config->fb = intel_fb;
8105 }
8106
8107 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8108                                struct intel_crtc_state *pipe_config)
8109 {
8110         struct drm_device *dev = crtc->base.dev;
8111         struct drm_i915_private *dev_priv = dev->dev_private;
8112         int pipe = pipe_config->cpu_transcoder;
8113         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8114         struct dpll clock;
8115         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8116         int refclk = 100000;
8117
8118         /* In case of DSI, DPLL will not be used */
8119         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8120                 return;
8121
8122         mutex_lock(&dev_priv->sb_lock);
8123         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8124         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8125         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8126         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8127         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8128         mutex_unlock(&dev_priv->sb_lock);
8129
8130         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8131         clock.m2 = (pll_dw0 & 0xff) << 22;
8132         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8133                 clock.m2 |= pll_dw2 & 0x3fffff;
8134         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8135         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8136         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8137
8138         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8139 }
8140
8141 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8142                                  struct intel_crtc_state *pipe_config)
8143 {
8144         struct drm_device *dev = crtc->base.dev;
8145         struct drm_i915_private *dev_priv = dev->dev_private;
8146         enum intel_display_power_domain power_domain;
8147         uint32_t tmp;
8148         bool ret;
8149
8150         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8151         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8152                 return false;
8153
8154         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8155         pipe_config->shared_dpll = NULL;
8156
8157         ret = false;
8158
8159         tmp = I915_READ(PIPECONF(crtc->pipe));
8160         if (!(tmp & PIPECONF_ENABLE))
8161                 goto out;
8162
8163         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8164                 switch (tmp & PIPECONF_BPC_MASK) {
8165                 case PIPECONF_6BPC:
8166                         pipe_config->pipe_bpp = 18;
8167                         break;
8168                 case PIPECONF_8BPC:
8169                         pipe_config->pipe_bpp = 24;
8170                         break;
8171                 case PIPECONF_10BPC:
8172                         pipe_config->pipe_bpp = 30;
8173                         break;
8174                 default:
8175                         break;
8176                 }
8177         }
8178
8179         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8180             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8181                 pipe_config->limited_color_range = true;
8182
8183         if (INTEL_INFO(dev)->gen < 4)
8184                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8185
8186         intel_get_pipe_timings(crtc, pipe_config);
8187         intel_get_pipe_src_size(crtc, pipe_config);
8188
8189         i9xx_get_pfit_config(crtc, pipe_config);
8190
8191         if (INTEL_INFO(dev)->gen >= 4) {
8192                 /* No way to read it out on pipes B and C */
8193                 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8194                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8195                 else
8196                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8197                 pipe_config->pixel_multiplier =
8198                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8199                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8200                 pipe_config->dpll_hw_state.dpll_md = tmp;
8201         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8202                 tmp = I915_READ(DPLL(crtc->pipe));
8203                 pipe_config->pixel_multiplier =
8204                         ((tmp & SDVO_MULTIPLIER_MASK)
8205                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8206         } else {
8207                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8208                  * port and will be fixed up in the encoder->get_config
8209                  * function. */
8210                 pipe_config->pixel_multiplier = 1;
8211         }
8212         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8213         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8214                 /*
8215                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8216                  * on 830. Filter it out here so that we don't
8217                  * report errors due to that.
8218                  */
8219                 if (IS_I830(dev))
8220                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8221
8222                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8223                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8224         } else {
8225                 /* Mask out read-only status bits. */
8226                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8227                                                      DPLL_PORTC_READY_MASK |
8228                                                      DPLL_PORTB_READY_MASK);
8229         }
8230
8231         if (IS_CHERRYVIEW(dev))
8232                 chv_crtc_clock_get(crtc, pipe_config);
8233         else if (IS_VALLEYVIEW(dev))
8234                 vlv_crtc_clock_get(crtc, pipe_config);
8235         else
8236                 i9xx_crtc_clock_get(crtc, pipe_config);
8237
8238         /*
8239          * Normally the dotclock is filled in by the encoder .get_config()
8240          * but in case the pipe is enabled w/o any ports we need a sane
8241          * default.
8242          */
8243         pipe_config->base.adjusted_mode.crtc_clock =
8244                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8245
8246         ret = true;
8247
8248 out:
8249         intel_display_power_put(dev_priv, power_domain);
8250
8251         return ret;
8252 }
8253
8254 static void ironlake_init_pch_refclk(struct drm_device *dev)
8255 {
8256         struct drm_i915_private *dev_priv = dev->dev_private;
8257         struct intel_encoder *encoder;
8258         u32 val, final;
8259         bool has_lvds = false;
8260         bool has_cpu_edp = false;
8261         bool has_panel = false;
8262         bool has_ck505 = false;
8263         bool can_ssc = false;
8264
8265         /* We need to take the global config into account */
8266         for_each_intel_encoder(dev, encoder) {
8267                 switch (encoder->type) {
8268                 case INTEL_OUTPUT_LVDS:
8269                         has_panel = true;
8270                         has_lvds = true;
8271                         break;
8272                 case INTEL_OUTPUT_EDP:
8273                         has_panel = true;
8274                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8275                                 has_cpu_edp = true;
8276                         break;
8277                 default:
8278                         break;
8279                 }
8280         }
8281
8282         if (HAS_PCH_IBX(dev)) {
8283                 has_ck505 = dev_priv->vbt.display_clock_mode;
8284                 can_ssc = has_ck505;
8285         } else {
8286                 has_ck505 = false;
8287                 can_ssc = true;
8288         }
8289
8290         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8291                       has_panel, has_lvds, has_ck505);
8292
8293         /* Ironlake: try to setup display ref clock before DPLL
8294          * enabling. This is only under driver's control after
8295          * PCH B stepping, previous chipset stepping should be
8296          * ignoring this setting.
8297          */
8298         val = I915_READ(PCH_DREF_CONTROL);
8299
8300         /* As we must carefully and slowly disable/enable each source in turn,
8301          * compute the final state we want first and check if we need to
8302          * make any changes at all.
8303          */
8304         final = val;
8305         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8306         if (has_ck505)
8307                 final |= DREF_NONSPREAD_CK505_ENABLE;
8308         else
8309                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8310
8311         final &= ~DREF_SSC_SOURCE_MASK;
8312         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8313         final &= ~DREF_SSC1_ENABLE;
8314
8315         if (has_panel) {
8316                 final |= DREF_SSC_SOURCE_ENABLE;
8317
8318                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8319                         final |= DREF_SSC1_ENABLE;
8320
8321                 if (has_cpu_edp) {
8322                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8323                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8324                         else
8325                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8326                 } else
8327                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8328         } else {
8329                 final |= DREF_SSC_SOURCE_DISABLE;
8330                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8331         }
8332
8333         if (final == val)
8334                 return;
8335
8336         /* Always enable nonspread source */
8337         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8338
8339         if (has_ck505)
8340                 val |= DREF_NONSPREAD_CK505_ENABLE;
8341         else
8342                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8343
8344         if (has_panel) {
8345                 val &= ~DREF_SSC_SOURCE_MASK;
8346                 val |= DREF_SSC_SOURCE_ENABLE;
8347
8348                 /* SSC must be turned on before enabling the CPU output  */
8349                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8350                         DRM_DEBUG_KMS("Using SSC on panel\n");
8351                         val |= DREF_SSC1_ENABLE;
8352                 } else
8353                         val &= ~DREF_SSC1_ENABLE;
8354
8355                 /* Get SSC going before enabling the outputs */
8356                 I915_WRITE(PCH_DREF_CONTROL, val);
8357                 POSTING_READ(PCH_DREF_CONTROL);
8358                 udelay(200);
8359
8360                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8361
8362                 /* Enable CPU source on CPU attached eDP */
8363                 if (has_cpu_edp) {
8364                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8365                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8366                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8367                         } else
8368                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8369                 } else
8370                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8371
8372                 I915_WRITE(PCH_DREF_CONTROL, val);
8373                 POSTING_READ(PCH_DREF_CONTROL);
8374                 udelay(200);
8375         } else {
8376                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8377
8378                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8379
8380                 /* Turn off CPU output */
8381                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8382
8383                 I915_WRITE(PCH_DREF_CONTROL, val);
8384                 POSTING_READ(PCH_DREF_CONTROL);
8385                 udelay(200);
8386
8387                 /* Turn off the SSC source */
8388                 val &= ~DREF_SSC_SOURCE_MASK;
8389                 val |= DREF_SSC_SOURCE_DISABLE;
8390
8391                 /* Turn off SSC1 */
8392                 val &= ~DREF_SSC1_ENABLE;
8393
8394                 I915_WRITE(PCH_DREF_CONTROL, val);
8395                 POSTING_READ(PCH_DREF_CONTROL);
8396                 udelay(200);
8397         }
8398
8399         BUG_ON(val != final);
8400 }
8401
8402 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8403 {
8404         uint32_t tmp;
8405
8406         tmp = I915_READ(SOUTH_CHICKEN2);
8407         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8408         I915_WRITE(SOUTH_CHICKEN2, tmp);
8409
8410         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8411                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8412                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8413
8414         tmp = I915_READ(SOUTH_CHICKEN2);
8415         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8416         I915_WRITE(SOUTH_CHICKEN2, tmp);
8417
8418         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8419                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8420                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8421 }
8422
8423 /* WaMPhyProgramming:hsw */
8424 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8425 {
8426         uint32_t tmp;
8427
8428         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8429         tmp &= ~(0xFF << 24);
8430         tmp |= (0x12 << 24);
8431         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8432
8433         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8434         tmp |= (1 << 11);
8435         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8436
8437         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8438         tmp |= (1 << 11);
8439         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8440
8441         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8442         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8443         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8444
8445         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8446         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8447         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8448
8449         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8450         tmp &= ~(7 << 13);
8451         tmp |= (5 << 13);
8452         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8453
8454         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8455         tmp &= ~(7 << 13);
8456         tmp |= (5 << 13);
8457         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8458
8459         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8460         tmp &= ~0xFF;
8461         tmp |= 0x1C;
8462         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8463
8464         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8465         tmp &= ~0xFF;
8466         tmp |= 0x1C;
8467         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8468
8469         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8470         tmp &= ~(0xFF << 16);
8471         tmp |= (0x1C << 16);
8472         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8473
8474         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8475         tmp &= ~(0xFF << 16);
8476         tmp |= (0x1C << 16);
8477         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8478
8479         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8480         tmp |= (1 << 27);
8481         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8482
8483         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8484         tmp |= (1 << 27);
8485         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8486
8487         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8488         tmp &= ~(0xF << 28);
8489         tmp |= (4 << 28);
8490         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8491
8492         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8493         tmp &= ~(0xF << 28);
8494         tmp |= (4 << 28);
8495         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8496 }
8497
8498 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8499  * Programming" based on the parameters passed:
8500  * - Sequence to enable CLKOUT_DP
8501  * - Sequence to enable CLKOUT_DP without spread
8502  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8503  */
8504 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8505                                  bool with_fdi)
8506 {
8507         struct drm_i915_private *dev_priv = dev->dev_private;
8508         uint32_t reg, tmp;
8509
8510         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8511                 with_spread = true;
8512         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8513                 with_fdi = false;
8514
8515         mutex_lock(&dev_priv->sb_lock);
8516
8517         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8518         tmp &= ~SBI_SSCCTL_DISABLE;
8519         tmp |= SBI_SSCCTL_PATHALT;
8520         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8521
8522         udelay(24);
8523
8524         if (with_spread) {
8525                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8526                 tmp &= ~SBI_SSCCTL_PATHALT;
8527                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8528
8529                 if (with_fdi) {
8530                         lpt_reset_fdi_mphy(dev_priv);
8531                         lpt_program_fdi_mphy(dev_priv);
8532                 }
8533         }
8534
8535         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8536         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8537         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8538         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8539
8540         mutex_unlock(&dev_priv->sb_lock);
8541 }
8542
8543 /* Sequence to disable CLKOUT_DP */
8544 static void lpt_disable_clkout_dp(struct drm_device *dev)
8545 {
8546         struct drm_i915_private *dev_priv = dev->dev_private;
8547         uint32_t reg, tmp;
8548
8549         mutex_lock(&dev_priv->sb_lock);
8550
8551         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8552         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8553         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8554         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8555
8556         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8557         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8558                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8559                         tmp |= SBI_SSCCTL_PATHALT;
8560                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8561                         udelay(32);
8562                 }
8563                 tmp |= SBI_SSCCTL_DISABLE;
8564                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8565         }
8566
8567         mutex_unlock(&dev_priv->sb_lock);
8568 }
8569
8570 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8571
8572 static const uint16_t sscdivintphase[] = {
8573         [BEND_IDX( 50)] = 0x3B23,
8574         [BEND_IDX( 45)] = 0x3B23,
8575         [BEND_IDX( 40)] = 0x3C23,
8576         [BEND_IDX( 35)] = 0x3C23,
8577         [BEND_IDX( 30)] = 0x3D23,
8578         [BEND_IDX( 25)] = 0x3D23,
8579         [BEND_IDX( 20)] = 0x3E23,
8580         [BEND_IDX( 15)] = 0x3E23,
8581         [BEND_IDX( 10)] = 0x3F23,
8582         [BEND_IDX(  5)] = 0x3F23,
8583         [BEND_IDX(  0)] = 0x0025,
8584         [BEND_IDX( -5)] = 0x0025,
8585         [BEND_IDX(-10)] = 0x0125,
8586         [BEND_IDX(-15)] = 0x0125,
8587         [BEND_IDX(-20)] = 0x0225,
8588         [BEND_IDX(-25)] = 0x0225,
8589         [BEND_IDX(-30)] = 0x0325,
8590         [BEND_IDX(-35)] = 0x0325,
8591         [BEND_IDX(-40)] = 0x0425,
8592         [BEND_IDX(-45)] = 0x0425,
8593         [BEND_IDX(-50)] = 0x0525,
8594 };
8595
8596 /*
8597  * Bend CLKOUT_DP
8598  * steps -50 to 50 inclusive, in steps of 5
8599  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8600  * change in clock period = -(steps / 10) * 5.787 ps
8601  */
8602 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8603 {
8604         uint32_t tmp;
8605         int idx = BEND_IDX(steps);
8606
8607         if (WARN_ON(steps % 5 != 0))
8608                 return;
8609
8610         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8611                 return;
8612
8613         mutex_lock(&dev_priv->sb_lock);
8614
8615         if (steps % 10 != 0)
8616                 tmp = 0xAAAAAAAB;
8617         else
8618                 tmp = 0x00000000;
8619         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8620
8621         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8622         tmp &= 0xffff0000;
8623         tmp |= sscdivintphase[idx];
8624         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8625
8626         mutex_unlock(&dev_priv->sb_lock);
8627 }
8628
8629 #undef BEND_IDX
8630
8631 static void lpt_init_pch_refclk(struct drm_device *dev)
8632 {
8633         struct intel_encoder *encoder;
8634         bool has_vga = false;
8635
8636         for_each_intel_encoder(dev, encoder) {
8637                 switch (encoder->type) {
8638                 case INTEL_OUTPUT_ANALOG:
8639                         has_vga = true;
8640                         break;
8641                 default:
8642                         break;
8643                 }
8644         }
8645
8646         if (has_vga) {
8647                 lpt_bend_clkout_dp(to_i915(dev), 0);
8648                 lpt_enable_clkout_dp(dev, true, true);
8649         } else {
8650                 lpt_disable_clkout_dp(dev);
8651         }
8652 }
8653
8654 /*
8655  * Initialize reference clocks when the driver loads
8656  */
8657 void intel_init_pch_refclk(struct drm_device *dev)
8658 {
8659         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8660                 ironlake_init_pch_refclk(dev);
8661         else if (HAS_PCH_LPT(dev))
8662                 lpt_init_pch_refclk(dev);
8663 }
8664
8665 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8666 {
8667         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8668         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8669         int pipe = intel_crtc->pipe;
8670         uint32_t val;
8671
8672         val = 0;
8673
8674         switch (intel_crtc->config->pipe_bpp) {
8675         case 18:
8676                 val |= PIPECONF_6BPC;
8677                 break;
8678         case 24:
8679                 val |= PIPECONF_8BPC;
8680                 break;
8681         case 30:
8682                 val |= PIPECONF_10BPC;
8683                 break;
8684         case 36:
8685                 val |= PIPECONF_12BPC;
8686                 break;
8687         default:
8688                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8689                 BUG();
8690         }
8691
8692         if (intel_crtc->config->dither)
8693                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8694
8695         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8696                 val |= PIPECONF_INTERLACED_ILK;
8697         else
8698                 val |= PIPECONF_PROGRESSIVE;
8699
8700         if (intel_crtc->config->limited_color_range)
8701                 val |= PIPECONF_COLOR_RANGE_SELECT;
8702
8703         I915_WRITE(PIPECONF(pipe), val);
8704         POSTING_READ(PIPECONF(pipe));
8705 }
8706
8707 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8708 {
8709         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8711         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8712         u32 val = 0;
8713
8714         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8715                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8716
8717         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8718                 val |= PIPECONF_INTERLACED_ILK;
8719         else
8720                 val |= PIPECONF_PROGRESSIVE;
8721
8722         I915_WRITE(PIPECONF(cpu_transcoder), val);
8723         POSTING_READ(PIPECONF(cpu_transcoder));
8724 }
8725
8726 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8727 {
8728         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8730
8731         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8732                 u32 val = 0;
8733
8734                 switch (intel_crtc->config->pipe_bpp) {
8735                 case 18:
8736                         val |= PIPEMISC_DITHER_6_BPC;
8737                         break;
8738                 case 24:
8739                         val |= PIPEMISC_DITHER_8_BPC;
8740                         break;
8741                 case 30:
8742                         val |= PIPEMISC_DITHER_10_BPC;
8743                         break;
8744                 case 36:
8745                         val |= PIPEMISC_DITHER_12_BPC;
8746                         break;
8747                 default:
8748                         /* Case prevented by pipe_config_set_bpp. */
8749                         BUG();
8750                 }
8751
8752                 if (intel_crtc->config->dither)
8753                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8754
8755                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8756         }
8757 }
8758
8759 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8760 {
8761         /*
8762          * Account for spread spectrum to avoid
8763          * oversubscribing the link. Max center spread
8764          * is 2.5%; use 5% for safety's sake.
8765          */
8766         u32 bps = target_clock * bpp * 21 / 20;
8767         return DIV_ROUND_UP(bps, link_bw * 8);
8768 }
8769
8770 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8771 {
8772         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8773 }
8774
8775 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8776                                   struct intel_crtc_state *crtc_state,
8777                                   struct dpll *reduced_clock)
8778 {
8779         struct drm_crtc *crtc = &intel_crtc->base;
8780         struct drm_device *dev = crtc->dev;
8781         struct drm_i915_private *dev_priv = dev->dev_private;
8782         struct drm_atomic_state *state = crtc_state->base.state;
8783         struct drm_connector *connector;
8784         struct drm_connector_state *connector_state;
8785         struct intel_encoder *encoder;
8786         u32 dpll, fp, fp2;
8787         int factor, i;
8788         bool is_lvds = false, is_sdvo = false;
8789
8790         for_each_connector_in_state(state, connector, connector_state, i) {
8791                 if (connector_state->crtc != crtc_state->base.crtc)
8792                         continue;
8793
8794                 encoder = to_intel_encoder(connector_state->best_encoder);
8795
8796                 switch (encoder->type) {
8797                 case INTEL_OUTPUT_LVDS:
8798                         is_lvds = true;
8799                         break;
8800                 case INTEL_OUTPUT_SDVO:
8801                 case INTEL_OUTPUT_HDMI:
8802                         is_sdvo = true;
8803                         break;
8804                 default:
8805                         break;
8806                 }
8807         }
8808
8809         /* Enable autotuning of the PLL clock (if permissible) */
8810         factor = 21;
8811         if (is_lvds) {
8812                 if ((intel_panel_use_ssc(dev_priv) &&
8813                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8814                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8815                         factor = 25;
8816         } else if (crtc_state->sdvo_tv_clock)
8817                 factor = 20;
8818
8819         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8820
8821         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8822                 fp |= FP_CB_TUNE;
8823
8824         if (reduced_clock) {
8825                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8826
8827                 if (reduced_clock->m < factor * reduced_clock->n)
8828                         fp2 |= FP_CB_TUNE;
8829         } else {
8830                 fp2 = fp;
8831         }
8832
8833         dpll = 0;
8834
8835         if (is_lvds)
8836                 dpll |= DPLLB_MODE_LVDS;
8837         else
8838                 dpll |= DPLLB_MODE_DAC_SERIAL;
8839
8840         dpll |= (crtc_state->pixel_multiplier - 1)
8841                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8842
8843         if (is_sdvo)
8844                 dpll |= DPLL_SDVO_HIGH_SPEED;
8845         if (crtc_state->has_dp_encoder)
8846                 dpll |= DPLL_SDVO_HIGH_SPEED;
8847
8848         /* compute bitmask from p1 value */
8849         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8850         /* also FPA1 */
8851         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8852
8853         switch (crtc_state->dpll.p2) {
8854         case 5:
8855                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8856                 break;
8857         case 7:
8858                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8859                 break;
8860         case 10:
8861                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8862                 break;
8863         case 14:
8864                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8865                 break;
8866         }
8867
8868         if (is_lvds && intel_panel_use_ssc(dev_priv))
8869                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8870         else
8871                 dpll |= PLL_REF_INPUT_DREFCLK;
8872
8873         dpll |= DPLL_VCO_ENABLE;
8874
8875         crtc_state->dpll_hw_state.dpll = dpll;
8876         crtc_state->dpll_hw_state.fp0 = fp;
8877         crtc_state->dpll_hw_state.fp1 = fp2;
8878 }
8879
8880 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8881                                        struct intel_crtc_state *crtc_state)
8882 {
8883         struct drm_device *dev = crtc->base.dev;
8884         struct drm_i915_private *dev_priv = dev->dev_private;
8885         struct dpll reduced_clock;
8886         bool has_reduced_clock = false;
8887         struct intel_shared_dpll *pll;
8888         const struct intel_limit *limit;
8889         int refclk = 120000;
8890
8891         memset(&crtc_state->dpll_hw_state, 0,
8892                sizeof(crtc_state->dpll_hw_state));
8893
8894         crtc->lowfreq_avail = false;
8895
8896         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8897         if (!crtc_state->has_pch_encoder)
8898                 return 0;
8899
8900         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8901                 if (intel_panel_use_ssc(dev_priv)) {
8902                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8903                                       dev_priv->vbt.lvds_ssc_freq);
8904                         refclk = dev_priv->vbt.lvds_ssc_freq;
8905                 }
8906
8907                 if (intel_is_dual_link_lvds(dev)) {
8908                         if (refclk == 100000)
8909                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8910                         else
8911                                 limit = &intel_limits_ironlake_dual_lvds;
8912                 } else {
8913                         if (refclk == 100000)
8914                                 limit = &intel_limits_ironlake_single_lvds_100m;
8915                         else
8916                                 limit = &intel_limits_ironlake_single_lvds;
8917                 }
8918         } else {
8919                 limit = &intel_limits_ironlake_dac;
8920         }
8921
8922         if (!crtc_state->clock_set &&
8923             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8924                                 refclk, NULL, &crtc_state->dpll)) {
8925                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8926                 return -EINVAL;
8927         }
8928
8929         ironlake_compute_dpll(crtc, crtc_state,
8930                               has_reduced_clock ? &reduced_clock : NULL);
8931
8932         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8933         if (pll == NULL) {
8934                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8935                                  pipe_name(crtc->pipe));
8936                 return -EINVAL;
8937         }
8938
8939         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8940             has_reduced_clock)
8941                 crtc->lowfreq_avail = true;
8942
8943         return 0;
8944 }
8945
8946 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8947                                          struct intel_link_m_n *m_n)
8948 {
8949         struct drm_device *dev = crtc->base.dev;
8950         struct drm_i915_private *dev_priv = dev->dev_private;
8951         enum pipe pipe = crtc->pipe;
8952
8953         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8954         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8955         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8956                 & ~TU_SIZE_MASK;
8957         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8958         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8959                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8960 }
8961
8962 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8963                                          enum transcoder transcoder,
8964                                          struct intel_link_m_n *m_n,
8965                                          struct intel_link_m_n *m2_n2)
8966 {
8967         struct drm_device *dev = crtc->base.dev;
8968         struct drm_i915_private *dev_priv = dev->dev_private;
8969         enum pipe pipe = crtc->pipe;
8970
8971         if (INTEL_INFO(dev)->gen >= 5) {
8972                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8973                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8974                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8975                         & ~TU_SIZE_MASK;
8976                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8977                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8978                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8979                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8980                  * gen < 8) and if DRRS is supported (to make sure the
8981                  * registers are not unnecessarily read).
8982                  */
8983                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8984                         crtc->config->has_drrs) {
8985                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8986                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8987                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8988                                         & ~TU_SIZE_MASK;
8989                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8990                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8991                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8992                 }
8993         } else {
8994                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8995                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8996                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8997                         & ~TU_SIZE_MASK;
8998                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8999                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9000                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9001         }
9002 }
9003
9004 void intel_dp_get_m_n(struct intel_crtc *crtc,
9005                       struct intel_crtc_state *pipe_config)
9006 {
9007         if (pipe_config->has_pch_encoder)
9008                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9009         else
9010                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9011                                              &pipe_config->dp_m_n,
9012                                              &pipe_config->dp_m2_n2);
9013 }
9014
9015 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9016                                         struct intel_crtc_state *pipe_config)
9017 {
9018         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9019                                      &pipe_config->fdi_m_n, NULL);
9020 }
9021
9022 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9023                                     struct intel_crtc_state *pipe_config)
9024 {
9025         struct drm_device *dev = crtc->base.dev;
9026         struct drm_i915_private *dev_priv = dev->dev_private;
9027         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9028         uint32_t ps_ctrl = 0;
9029         int id = -1;
9030         int i;
9031
9032         /* find scaler attached to this pipe */
9033         for (i = 0; i < crtc->num_scalers; i++) {
9034                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9035                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9036                         id = i;
9037                         pipe_config->pch_pfit.enabled = true;
9038                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9039                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9040                         break;
9041                 }
9042         }
9043
9044         scaler_state->scaler_id = id;
9045         if (id >= 0) {
9046                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9047         } else {
9048                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9049         }
9050 }
9051
9052 static void
9053 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9054                                  struct intel_initial_plane_config *plane_config)
9055 {
9056         struct drm_device *dev = crtc->base.dev;
9057         struct drm_i915_private *dev_priv = dev->dev_private;
9058         u32 val, base, offset, stride_mult, tiling;
9059         int pipe = crtc->pipe;
9060         int fourcc, pixel_format;
9061         unsigned int aligned_height;
9062         struct drm_framebuffer *fb;
9063         struct intel_framebuffer *intel_fb;
9064
9065         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9066         if (!intel_fb) {
9067                 DRM_DEBUG_KMS("failed to alloc fb\n");
9068                 return;
9069         }
9070
9071         fb = &intel_fb->base;
9072
9073         val = I915_READ(PLANE_CTL(pipe, 0));
9074         if (!(val & PLANE_CTL_ENABLE))
9075                 goto error;
9076
9077         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9078         fourcc = skl_format_to_fourcc(pixel_format,
9079                                       val & PLANE_CTL_ORDER_RGBX,
9080                                       val & PLANE_CTL_ALPHA_MASK);
9081         fb->pixel_format = fourcc;
9082         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9083
9084         tiling = val & PLANE_CTL_TILED_MASK;
9085         switch (tiling) {
9086         case PLANE_CTL_TILED_LINEAR:
9087                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9088                 break;
9089         case PLANE_CTL_TILED_X:
9090                 plane_config->tiling = I915_TILING_X;
9091                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9092                 break;
9093         case PLANE_CTL_TILED_Y:
9094                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9095                 break;
9096         case PLANE_CTL_TILED_YF:
9097                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9098                 break;
9099         default:
9100                 MISSING_CASE(tiling);
9101                 goto error;
9102         }
9103
9104         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9105         plane_config->base = base;
9106
9107         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9108
9109         val = I915_READ(PLANE_SIZE(pipe, 0));
9110         fb->height = ((val >> 16) & 0xfff) + 1;
9111         fb->width = ((val >> 0) & 0x1fff) + 1;
9112
9113         val = I915_READ(PLANE_STRIDE(pipe, 0));
9114         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9115                                                 fb->pixel_format);
9116         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9117
9118         aligned_height = intel_fb_align_height(dev, fb->height,
9119                                                fb->pixel_format,
9120                                                fb->modifier[0]);
9121
9122         plane_config->size = fb->pitches[0] * aligned_height;
9123
9124         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9125                       pipe_name(pipe), fb->width, fb->height,
9126                       fb->bits_per_pixel, base, fb->pitches[0],
9127                       plane_config->size);
9128
9129         plane_config->fb = intel_fb;
9130         return;
9131
9132 error:
9133         kfree(fb);
9134 }
9135
9136 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9137                                      struct intel_crtc_state *pipe_config)
9138 {
9139         struct drm_device *dev = crtc->base.dev;
9140         struct drm_i915_private *dev_priv = dev->dev_private;
9141         uint32_t tmp;
9142
9143         tmp = I915_READ(PF_CTL(crtc->pipe));
9144
9145         if (tmp & PF_ENABLE) {
9146                 pipe_config->pch_pfit.enabled = true;
9147                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9148                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9149
9150                 /* We currently do not free assignements of panel fitters on
9151                  * ivb/hsw (since we don't use the higher upscaling modes which
9152                  * differentiates them) so just WARN about this case for now. */
9153                 if (IS_GEN7(dev)) {
9154                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9155                                 PF_PIPE_SEL_IVB(crtc->pipe));
9156                 }
9157         }
9158 }
9159
9160 static void
9161 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9162                                   struct intel_initial_plane_config *plane_config)
9163 {
9164         struct drm_device *dev = crtc->base.dev;
9165         struct drm_i915_private *dev_priv = dev->dev_private;
9166         u32 val, base, offset;
9167         int pipe = crtc->pipe;
9168         int fourcc, pixel_format;
9169         unsigned int aligned_height;
9170         struct drm_framebuffer *fb;
9171         struct intel_framebuffer *intel_fb;
9172
9173         val = I915_READ(DSPCNTR(pipe));
9174         if (!(val & DISPLAY_PLANE_ENABLE))
9175                 return;
9176
9177         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9178         if (!intel_fb) {
9179                 DRM_DEBUG_KMS("failed to alloc fb\n");
9180                 return;
9181         }
9182
9183         fb = &intel_fb->base;
9184
9185         if (INTEL_INFO(dev)->gen >= 4) {
9186                 if (val & DISPPLANE_TILED) {
9187                         plane_config->tiling = I915_TILING_X;
9188                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9189                 }
9190         }
9191
9192         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9193         fourcc = i9xx_format_to_fourcc(pixel_format);
9194         fb->pixel_format = fourcc;
9195         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9196
9197         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9198         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9199                 offset = I915_READ(DSPOFFSET(pipe));
9200         } else {
9201                 if (plane_config->tiling)
9202                         offset = I915_READ(DSPTILEOFF(pipe));
9203                 else
9204                         offset = I915_READ(DSPLINOFF(pipe));
9205         }
9206         plane_config->base = base;
9207
9208         val = I915_READ(PIPESRC(pipe));
9209         fb->width = ((val >> 16) & 0xfff) + 1;
9210         fb->height = ((val >> 0) & 0xfff) + 1;
9211
9212         val = I915_READ(DSPSTRIDE(pipe));
9213         fb->pitches[0] = val & 0xffffffc0;
9214
9215         aligned_height = intel_fb_align_height(dev, fb->height,
9216                                                fb->pixel_format,
9217                                                fb->modifier[0]);
9218
9219         plane_config->size = fb->pitches[0] * aligned_height;
9220
9221         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9222                       pipe_name(pipe), fb->width, fb->height,
9223                       fb->bits_per_pixel, base, fb->pitches[0],
9224                       plane_config->size);
9225
9226         plane_config->fb = intel_fb;
9227 }
9228
9229 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9230                                      struct intel_crtc_state *pipe_config)
9231 {
9232         struct drm_device *dev = crtc->base.dev;
9233         struct drm_i915_private *dev_priv = dev->dev_private;
9234         enum intel_display_power_domain power_domain;
9235         uint32_t tmp;
9236         bool ret;
9237
9238         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9239         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9240                 return false;
9241
9242         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9243         pipe_config->shared_dpll = NULL;
9244
9245         ret = false;
9246         tmp = I915_READ(PIPECONF(crtc->pipe));
9247         if (!(tmp & PIPECONF_ENABLE))
9248                 goto out;
9249
9250         switch (tmp & PIPECONF_BPC_MASK) {
9251         case PIPECONF_6BPC:
9252                 pipe_config->pipe_bpp = 18;
9253                 break;
9254         case PIPECONF_8BPC:
9255                 pipe_config->pipe_bpp = 24;
9256                 break;
9257         case PIPECONF_10BPC:
9258                 pipe_config->pipe_bpp = 30;
9259                 break;
9260         case PIPECONF_12BPC:
9261                 pipe_config->pipe_bpp = 36;
9262                 break;
9263         default:
9264                 break;
9265         }
9266
9267         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9268                 pipe_config->limited_color_range = true;
9269
9270         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9271                 struct intel_shared_dpll *pll;
9272                 enum intel_dpll_id pll_id;
9273
9274                 pipe_config->has_pch_encoder = true;
9275
9276                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9277                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9278                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9279
9280                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9281
9282                 if (HAS_PCH_IBX(dev_priv)) {
9283                         /*
9284                          * The pipe->pch transcoder and pch transcoder->pll
9285                          * mapping is fixed.
9286                          */
9287                         pll_id = (enum intel_dpll_id) crtc->pipe;
9288                 } else {
9289                         tmp = I915_READ(PCH_DPLL_SEL);
9290                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9291                                 pll_id = DPLL_ID_PCH_PLL_B;
9292                         else
9293                                 pll_id= DPLL_ID_PCH_PLL_A;
9294                 }
9295
9296                 pipe_config->shared_dpll =
9297                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9298                 pll = pipe_config->shared_dpll;
9299
9300                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9301                                                  &pipe_config->dpll_hw_state));
9302
9303                 tmp = pipe_config->dpll_hw_state.dpll;
9304                 pipe_config->pixel_multiplier =
9305                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9306                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9307
9308                 ironlake_pch_clock_get(crtc, pipe_config);
9309         } else {
9310                 pipe_config->pixel_multiplier = 1;
9311         }
9312
9313         intel_get_pipe_timings(crtc, pipe_config);
9314         intel_get_pipe_src_size(crtc, pipe_config);
9315
9316         ironlake_get_pfit_config(crtc, pipe_config);
9317
9318         ret = true;
9319
9320 out:
9321         intel_display_power_put(dev_priv, power_domain);
9322
9323         return ret;
9324 }
9325
9326 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9327 {
9328         struct drm_device *dev = dev_priv->dev;
9329         struct intel_crtc *crtc;
9330
9331         for_each_intel_crtc(dev, crtc)
9332                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9333                      pipe_name(crtc->pipe));
9334
9335         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9336         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9337         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9338         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9339         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9340         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9341              "CPU PWM1 enabled\n");
9342         if (IS_HASWELL(dev))
9343                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9344                      "CPU PWM2 enabled\n");
9345         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9346              "PCH PWM1 enabled\n");
9347         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9348              "Utility pin enabled\n");
9349         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9350
9351         /*
9352          * In theory we can still leave IRQs enabled, as long as only the HPD
9353          * interrupts remain enabled. We used to check for that, but since it's
9354          * gen-specific and since we only disable LCPLL after we fully disable
9355          * the interrupts, the check below should be enough.
9356          */
9357         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9358 }
9359
9360 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9361 {
9362         struct drm_device *dev = dev_priv->dev;
9363
9364         if (IS_HASWELL(dev))
9365                 return I915_READ(D_COMP_HSW);
9366         else
9367                 return I915_READ(D_COMP_BDW);
9368 }
9369
9370 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9371 {
9372         struct drm_device *dev = dev_priv->dev;
9373
9374         if (IS_HASWELL(dev)) {
9375                 mutex_lock(&dev_priv->rps.hw_lock);
9376                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9377                                             val))
9378                         DRM_ERROR("Failed to write to D_COMP\n");
9379                 mutex_unlock(&dev_priv->rps.hw_lock);
9380         } else {
9381                 I915_WRITE(D_COMP_BDW, val);
9382                 POSTING_READ(D_COMP_BDW);
9383         }
9384 }
9385
9386 /*
9387  * This function implements pieces of two sequences from BSpec:
9388  * - Sequence for display software to disable LCPLL
9389  * - Sequence for display software to allow package C8+
9390  * The steps implemented here are just the steps that actually touch the LCPLL
9391  * register. Callers should take care of disabling all the display engine
9392  * functions, doing the mode unset, fixing interrupts, etc.
9393  */
9394 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9395                               bool switch_to_fclk, bool allow_power_down)
9396 {
9397         uint32_t val;
9398
9399         assert_can_disable_lcpll(dev_priv);
9400
9401         val = I915_READ(LCPLL_CTL);
9402
9403         if (switch_to_fclk) {
9404                 val |= LCPLL_CD_SOURCE_FCLK;
9405                 I915_WRITE(LCPLL_CTL, val);
9406
9407                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9408                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9409                         DRM_ERROR("Switching to FCLK failed\n");
9410
9411                 val = I915_READ(LCPLL_CTL);
9412         }
9413
9414         val |= LCPLL_PLL_DISABLE;
9415         I915_WRITE(LCPLL_CTL, val);
9416         POSTING_READ(LCPLL_CTL);
9417
9418         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9419                 DRM_ERROR("LCPLL still locked\n");
9420
9421         val = hsw_read_dcomp(dev_priv);
9422         val |= D_COMP_COMP_DISABLE;
9423         hsw_write_dcomp(dev_priv, val);
9424         ndelay(100);
9425
9426         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9427                      1))
9428                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9429
9430         if (allow_power_down) {
9431                 val = I915_READ(LCPLL_CTL);
9432                 val |= LCPLL_POWER_DOWN_ALLOW;
9433                 I915_WRITE(LCPLL_CTL, val);
9434                 POSTING_READ(LCPLL_CTL);
9435         }
9436 }
9437
9438 /*
9439  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9440  * source.
9441  */
9442 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9443 {
9444         uint32_t val;
9445
9446         val = I915_READ(LCPLL_CTL);
9447
9448         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9449                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9450                 return;
9451
9452         /*
9453          * Make sure we're not on PC8 state before disabling PC8, otherwise
9454          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9455          */
9456         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9457
9458         if (val & LCPLL_POWER_DOWN_ALLOW) {
9459                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9460                 I915_WRITE(LCPLL_CTL, val);
9461                 POSTING_READ(LCPLL_CTL);
9462         }
9463
9464         val = hsw_read_dcomp(dev_priv);
9465         val |= D_COMP_COMP_FORCE;
9466         val &= ~D_COMP_COMP_DISABLE;
9467         hsw_write_dcomp(dev_priv, val);
9468
9469         val = I915_READ(LCPLL_CTL);
9470         val &= ~LCPLL_PLL_DISABLE;
9471         I915_WRITE(LCPLL_CTL, val);
9472
9473         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9474                 DRM_ERROR("LCPLL not locked yet\n");
9475
9476         if (val & LCPLL_CD_SOURCE_FCLK) {
9477                 val = I915_READ(LCPLL_CTL);
9478                 val &= ~LCPLL_CD_SOURCE_FCLK;
9479                 I915_WRITE(LCPLL_CTL, val);
9480
9481                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9482                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9483                         DRM_ERROR("Switching back to LCPLL failed\n");
9484         }
9485
9486         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9487         intel_update_cdclk(dev_priv->dev);
9488 }
9489
9490 /*
9491  * Package states C8 and deeper are really deep PC states that can only be
9492  * reached when all the devices on the system allow it, so even if the graphics
9493  * device allows PC8+, it doesn't mean the system will actually get to these
9494  * states. Our driver only allows PC8+ when going into runtime PM.
9495  *
9496  * The requirements for PC8+ are that all the outputs are disabled, the power
9497  * well is disabled and most interrupts are disabled, and these are also
9498  * requirements for runtime PM. When these conditions are met, we manually do
9499  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9500  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9501  * hang the machine.
9502  *
9503  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9504  * the state of some registers, so when we come back from PC8+ we need to
9505  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9506  * need to take care of the registers kept by RC6. Notice that this happens even
9507  * if we don't put the device in PCI D3 state (which is what currently happens
9508  * because of the runtime PM support).
9509  *
9510  * For more, read "Display Sequences for Package C8" on the hardware
9511  * documentation.
9512  */
9513 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9514 {
9515         struct drm_device *dev = dev_priv->dev;
9516         uint32_t val;
9517
9518         DRM_DEBUG_KMS("Enabling package C8+\n");
9519
9520         if (HAS_PCH_LPT_LP(dev)) {
9521                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9522                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9523                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9524         }
9525
9526         lpt_disable_clkout_dp(dev);
9527         hsw_disable_lcpll(dev_priv, true, true);
9528 }
9529
9530 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9531 {
9532         struct drm_device *dev = dev_priv->dev;
9533         uint32_t val;
9534
9535         DRM_DEBUG_KMS("Disabling package C8+\n");
9536
9537         hsw_restore_lcpll(dev_priv);
9538         lpt_init_pch_refclk(dev);
9539
9540         if (HAS_PCH_LPT_LP(dev)) {
9541                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9542                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9543                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9544         }
9545 }
9546
9547 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9548 {
9549         struct drm_device *dev = old_state->dev;
9550         struct intel_atomic_state *old_intel_state =
9551                 to_intel_atomic_state(old_state);
9552         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9553
9554         broxton_set_cdclk(to_i915(dev), req_cdclk);
9555 }
9556
9557 /* compute the max rate for new configuration */
9558 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9559 {
9560         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9561         struct drm_i915_private *dev_priv = state->dev->dev_private;
9562         struct drm_crtc *crtc;
9563         struct drm_crtc_state *cstate;
9564         struct intel_crtc_state *crtc_state;
9565         unsigned max_pixel_rate = 0, i;
9566         enum pipe pipe;
9567
9568         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9569                sizeof(intel_state->min_pixclk));
9570
9571         for_each_crtc_in_state(state, crtc, cstate, i) {
9572                 int pixel_rate;
9573
9574                 crtc_state = to_intel_crtc_state(cstate);
9575                 if (!crtc_state->base.enable) {
9576                         intel_state->min_pixclk[i] = 0;
9577                         continue;
9578                 }
9579
9580                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9581
9582                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9583                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9584                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9585
9586                 intel_state->min_pixclk[i] = pixel_rate;
9587         }
9588
9589         for_each_pipe(dev_priv, pipe)
9590                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9591
9592         return max_pixel_rate;
9593 }
9594
9595 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9596 {
9597         struct drm_i915_private *dev_priv = dev->dev_private;
9598         uint32_t val, data;
9599         int ret;
9600
9601         if (WARN((I915_READ(LCPLL_CTL) &
9602                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9603                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9604                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9605                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9606                  "trying to change cdclk frequency with cdclk not enabled\n"))
9607                 return;
9608
9609         mutex_lock(&dev_priv->rps.hw_lock);
9610         ret = sandybridge_pcode_write(dev_priv,
9611                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9612         mutex_unlock(&dev_priv->rps.hw_lock);
9613         if (ret) {
9614                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9615                 return;
9616         }
9617
9618         val = I915_READ(LCPLL_CTL);
9619         val |= LCPLL_CD_SOURCE_FCLK;
9620         I915_WRITE(LCPLL_CTL, val);
9621
9622         if (wait_for_us(I915_READ(LCPLL_CTL) &
9623                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
9624                 DRM_ERROR("Switching to FCLK failed\n");
9625
9626         val = I915_READ(LCPLL_CTL);
9627         val &= ~LCPLL_CLK_FREQ_MASK;
9628
9629         switch (cdclk) {
9630         case 450000:
9631                 val |= LCPLL_CLK_FREQ_450;
9632                 data = 0;
9633                 break;
9634         case 540000:
9635                 val |= LCPLL_CLK_FREQ_54O_BDW;
9636                 data = 1;
9637                 break;
9638         case 337500:
9639                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9640                 data = 2;
9641                 break;
9642         case 675000:
9643                 val |= LCPLL_CLK_FREQ_675_BDW;
9644                 data = 3;
9645                 break;
9646         default:
9647                 WARN(1, "invalid cdclk frequency\n");
9648                 return;
9649         }
9650
9651         I915_WRITE(LCPLL_CTL, val);
9652
9653         val = I915_READ(LCPLL_CTL);
9654         val &= ~LCPLL_CD_SOURCE_FCLK;
9655         I915_WRITE(LCPLL_CTL, val);
9656
9657         if (wait_for_us((I915_READ(LCPLL_CTL) &
9658                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9659                 DRM_ERROR("Switching back to LCPLL failed\n");
9660
9661         mutex_lock(&dev_priv->rps.hw_lock);
9662         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9663         mutex_unlock(&dev_priv->rps.hw_lock);
9664
9665         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9666
9667         intel_update_cdclk(dev);
9668
9669         WARN(cdclk != dev_priv->cdclk_freq,
9670              "cdclk requested %d kHz but got %d kHz\n",
9671              cdclk, dev_priv->cdclk_freq);
9672 }
9673
9674 static int broadwell_calc_cdclk(int max_pixclk)
9675 {
9676         if (max_pixclk > 540000)
9677                 return 675000;
9678         else if (max_pixclk > 450000)
9679                 return 540000;
9680         else if (max_pixclk > 337500)
9681                 return 450000;
9682         else
9683                 return 337500;
9684 }
9685
9686 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9687 {
9688         struct drm_i915_private *dev_priv = to_i915(state->dev);
9689         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9690         int max_pixclk = ilk_max_pixel_rate(state);
9691         int cdclk;
9692
9693         /*
9694          * FIXME should also account for plane ratio
9695          * once 64bpp pixel formats are supported.
9696          */
9697         cdclk = broadwell_calc_cdclk(max_pixclk);
9698
9699         if (cdclk > dev_priv->max_cdclk_freq) {
9700                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9701                               cdclk, dev_priv->max_cdclk_freq);
9702                 return -EINVAL;
9703         }
9704
9705         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9706         if (!intel_state->active_crtcs)
9707                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9708
9709         return 0;
9710 }
9711
9712 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9713 {
9714         struct drm_device *dev = old_state->dev;
9715         struct intel_atomic_state *old_intel_state =
9716                 to_intel_atomic_state(old_state);
9717         unsigned req_cdclk = old_intel_state->dev_cdclk;
9718
9719         broadwell_set_cdclk(dev, req_cdclk);
9720 }
9721
9722 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9723                                       struct intel_crtc_state *crtc_state)
9724 {
9725         struct intel_encoder *intel_encoder =
9726                 intel_ddi_get_crtc_new_encoder(crtc_state);
9727
9728         if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9729                 if (!intel_ddi_pll_select(crtc, crtc_state))
9730                         return -EINVAL;
9731         }
9732
9733         crtc->lowfreq_avail = false;
9734
9735         return 0;
9736 }
9737
9738 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9739                                 enum port port,
9740                                 struct intel_crtc_state *pipe_config)
9741 {
9742         enum intel_dpll_id id;
9743
9744         switch (port) {
9745         case PORT_A:
9746                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9747                 id = DPLL_ID_SKL_DPLL0;
9748                 break;
9749         case PORT_B:
9750                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9751                 id = DPLL_ID_SKL_DPLL1;
9752                 break;
9753         case PORT_C:
9754                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9755                 id = DPLL_ID_SKL_DPLL2;
9756                 break;
9757         default:
9758                 DRM_ERROR("Incorrect port type\n");
9759                 return;
9760         }
9761
9762         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9763 }
9764
9765 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9766                                 enum port port,
9767                                 struct intel_crtc_state *pipe_config)
9768 {
9769         enum intel_dpll_id id;
9770         u32 temp;
9771
9772         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9773         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9774
9775         switch (pipe_config->ddi_pll_sel) {
9776         case SKL_DPLL0:
9777                 id = DPLL_ID_SKL_DPLL0;
9778                 break;
9779         case SKL_DPLL1:
9780                 id = DPLL_ID_SKL_DPLL1;
9781                 break;
9782         case SKL_DPLL2:
9783                 id = DPLL_ID_SKL_DPLL2;
9784                 break;
9785         case SKL_DPLL3:
9786                 id = DPLL_ID_SKL_DPLL3;
9787                 break;
9788         default:
9789                 MISSING_CASE(pipe_config->ddi_pll_sel);
9790                 return;
9791         }
9792
9793         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9794 }
9795
9796 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9797                                 enum port port,
9798                                 struct intel_crtc_state *pipe_config)
9799 {
9800         enum intel_dpll_id id;
9801
9802         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9803
9804         switch (pipe_config->ddi_pll_sel) {
9805         case PORT_CLK_SEL_WRPLL1:
9806                 id = DPLL_ID_WRPLL1;
9807                 break;
9808         case PORT_CLK_SEL_WRPLL2:
9809                 id = DPLL_ID_WRPLL2;
9810                 break;
9811         case PORT_CLK_SEL_SPLL:
9812                 id = DPLL_ID_SPLL;
9813                 break;
9814         case PORT_CLK_SEL_LCPLL_810:
9815                 id = DPLL_ID_LCPLL_810;
9816                 break;
9817         case PORT_CLK_SEL_LCPLL_1350:
9818                 id = DPLL_ID_LCPLL_1350;
9819                 break;
9820         case PORT_CLK_SEL_LCPLL_2700:
9821                 id = DPLL_ID_LCPLL_2700;
9822                 break;
9823         default:
9824                 MISSING_CASE(pipe_config->ddi_pll_sel);
9825                 /* fall through */
9826         case PORT_CLK_SEL_NONE:
9827                 return;
9828         }
9829
9830         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9831 }
9832
9833 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9834                                      struct intel_crtc_state *pipe_config,
9835                                      unsigned long *power_domain_mask)
9836 {
9837         struct drm_device *dev = crtc->base.dev;
9838         struct drm_i915_private *dev_priv = dev->dev_private;
9839         enum intel_display_power_domain power_domain;
9840         u32 tmp;
9841
9842         /*
9843          * The pipe->transcoder mapping is fixed with the exception of the eDP
9844          * transcoder handled below.
9845          */
9846         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9847
9848         /*
9849          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9850          * consistency and less surprising code; it's in always on power).
9851          */
9852         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9853         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9854                 enum pipe trans_edp_pipe;
9855                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9856                 default:
9857                         WARN(1, "unknown pipe linked to edp transcoder\n");
9858                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9859                 case TRANS_DDI_EDP_INPUT_A_ON:
9860                         trans_edp_pipe = PIPE_A;
9861                         break;
9862                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9863                         trans_edp_pipe = PIPE_B;
9864                         break;
9865                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9866                         trans_edp_pipe = PIPE_C;
9867                         break;
9868                 }
9869
9870                 if (trans_edp_pipe == crtc->pipe)
9871                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9872         }
9873
9874         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9875         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9876                 return false;
9877         *power_domain_mask |= BIT(power_domain);
9878
9879         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9880
9881         return tmp & PIPECONF_ENABLE;
9882 }
9883
9884 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9885                                          struct intel_crtc_state *pipe_config,
9886                                          unsigned long *power_domain_mask)
9887 {
9888         struct drm_device *dev = crtc->base.dev;
9889         struct drm_i915_private *dev_priv = dev->dev_private;
9890         enum intel_display_power_domain power_domain;
9891         enum port port;
9892         enum transcoder cpu_transcoder;
9893         u32 tmp;
9894
9895         pipe_config->has_dsi_encoder = false;
9896
9897         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9898                 if (port == PORT_A)
9899                         cpu_transcoder = TRANSCODER_DSI_A;
9900                 else
9901                         cpu_transcoder = TRANSCODER_DSI_C;
9902
9903                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9904                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9905                         continue;
9906                 *power_domain_mask |= BIT(power_domain);
9907
9908                 /*
9909                  * The PLL needs to be enabled with a valid divider
9910                  * configuration, otherwise accessing DSI registers will hang
9911                  * the machine. See BSpec North Display Engine
9912                  * registers/MIPI[BXT]. We can break out here early, since we
9913                  * need the same DSI PLL to be enabled for both DSI ports.
9914                  */
9915                 if (!intel_dsi_pll_is_enabled(dev_priv))
9916                         break;
9917
9918                 /* XXX: this works for video mode only */
9919                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9920                 if (!(tmp & DPI_ENABLE))
9921                         continue;
9922
9923                 tmp = I915_READ(MIPI_CTRL(port));
9924                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9925                         continue;
9926
9927                 pipe_config->cpu_transcoder = cpu_transcoder;
9928                 pipe_config->has_dsi_encoder = true;
9929                 break;
9930         }
9931
9932         return pipe_config->has_dsi_encoder;
9933 }
9934
9935 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9936                                        struct intel_crtc_state *pipe_config)
9937 {
9938         struct drm_device *dev = crtc->base.dev;
9939         struct drm_i915_private *dev_priv = dev->dev_private;
9940         struct intel_shared_dpll *pll;
9941         enum port port;
9942         uint32_t tmp;
9943
9944         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9945
9946         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9947
9948         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9949                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9950         else if (IS_BROXTON(dev))
9951                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9952         else
9953                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9954
9955         pll = pipe_config->shared_dpll;
9956         if (pll) {
9957                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9958                                                  &pipe_config->dpll_hw_state));
9959         }
9960
9961         /*
9962          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9963          * DDI E. So just check whether this pipe is wired to DDI E and whether
9964          * the PCH transcoder is on.
9965          */
9966         if (INTEL_INFO(dev)->gen < 9 &&
9967             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9968                 pipe_config->has_pch_encoder = true;
9969
9970                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9971                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9972                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9973
9974                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9975         }
9976 }
9977
9978 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9979                                     struct intel_crtc_state *pipe_config)
9980 {
9981         struct drm_device *dev = crtc->base.dev;
9982         struct drm_i915_private *dev_priv = dev->dev_private;
9983         enum intel_display_power_domain power_domain;
9984         unsigned long power_domain_mask;
9985         bool active;
9986
9987         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9988         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9989                 return false;
9990         power_domain_mask = BIT(power_domain);
9991
9992         pipe_config->shared_dpll = NULL;
9993
9994         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9995
9996         if (IS_BROXTON(dev_priv)) {
9997                 bxt_get_dsi_transcoder_state(crtc, pipe_config,
9998                                              &power_domain_mask);
9999                 WARN_ON(active && pipe_config->has_dsi_encoder);
10000                 if (pipe_config->has_dsi_encoder)
10001                         active = true;
10002         }
10003
10004         if (!active)
10005                 goto out;
10006
10007         if (!pipe_config->has_dsi_encoder) {
10008                 haswell_get_ddi_port_state(crtc, pipe_config);
10009                 intel_get_pipe_timings(crtc, pipe_config);
10010         }
10011
10012         intel_get_pipe_src_size(crtc, pipe_config);
10013
10014         pipe_config->gamma_mode =
10015                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10016
10017         if (INTEL_INFO(dev)->gen >= 9) {
10018                 skl_init_scalers(dev, crtc, pipe_config);
10019         }
10020
10021         if (INTEL_INFO(dev)->gen >= 9) {
10022                 pipe_config->scaler_state.scaler_id = -1;
10023                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10024         }
10025
10026         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10027         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10028                 power_domain_mask |= BIT(power_domain);
10029                 if (INTEL_INFO(dev)->gen >= 9)
10030                         skylake_get_pfit_config(crtc, pipe_config);
10031                 else
10032                         ironlake_get_pfit_config(crtc, pipe_config);
10033         }
10034
10035         if (IS_HASWELL(dev))
10036                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10037                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10038
10039         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10040             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10041                 pipe_config->pixel_multiplier =
10042                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10043         } else {
10044                 pipe_config->pixel_multiplier = 1;
10045         }
10046
10047 out:
10048         for_each_power_domain(power_domain, power_domain_mask)
10049                 intel_display_power_put(dev_priv, power_domain);
10050
10051         return active;
10052 }
10053
10054 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10055                                const struct intel_plane_state *plane_state)
10056 {
10057         struct drm_device *dev = crtc->dev;
10058         struct drm_i915_private *dev_priv = dev->dev_private;
10059         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10060         uint32_t cntl = 0, size = 0;
10061
10062         if (plane_state && plane_state->visible) {
10063                 unsigned int width = plane_state->base.crtc_w;
10064                 unsigned int height = plane_state->base.crtc_h;
10065                 unsigned int stride = roundup_pow_of_two(width) * 4;
10066
10067                 switch (stride) {
10068                 default:
10069                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10070                                   width, stride);
10071                         stride = 256;
10072                         /* fallthrough */
10073                 case 256:
10074                 case 512:
10075                 case 1024:
10076                 case 2048:
10077                         break;
10078                 }
10079
10080                 cntl |= CURSOR_ENABLE |
10081                         CURSOR_GAMMA_ENABLE |
10082                         CURSOR_FORMAT_ARGB |
10083                         CURSOR_STRIDE(stride);
10084
10085                 size = (height << 12) | width;
10086         }
10087
10088         if (intel_crtc->cursor_cntl != 0 &&
10089             (intel_crtc->cursor_base != base ||
10090              intel_crtc->cursor_size != size ||
10091              intel_crtc->cursor_cntl != cntl)) {
10092                 /* On these chipsets we can only modify the base/size/stride
10093                  * whilst the cursor is disabled.
10094                  */
10095                 I915_WRITE(CURCNTR(PIPE_A), 0);
10096                 POSTING_READ(CURCNTR(PIPE_A));
10097                 intel_crtc->cursor_cntl = 0;
10098         }
10099
10100         if (intel_crtc->cursor_base != base) {
10101                 I915_WRITE(CURBASE(PIPE_A), base);
10102                 intel_crtc->cursor_base = base;
10103         }
10104
10105         if (intel_crtc->cursor_size != size) {
10106                 I915_WRITE(CURSIZE, size);
10107                 intel_crtc->cursor_size = size;
10108         }
10109
10110         if (intel_crtc->cursor_cntl != cntl) {
10111                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10112                 POSTING_READ(CURCNTR(PIPE_A));
10113                 intel_crtc->cursor_cntl = cntl;
10114         }
10115 }
10116
10117 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10118                                const struct intel_plane_state *plane_state)
10119 {
10120         struct drm_device *dev = crtc->dev;
10121         struct drm_i915_private *dev_priv = dev->dev_private;
10122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10123         int pipe = intel_crtc->pipe;
10124         uint32_t cntl = 0;
10125
10126         if (plane_state && plane_state->visible) {
10127                 cntl = MCURSOR_GAMMA_ENABLE;
10128                 switch (plane_state->base.crtc_w) {
10129                         case 64:
10130                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10131                                 break;
10132                         case 128:
10133                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10134                                 break;
10135                         case 256:
10136                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10137                                 break;
10138                         default:
10139                                 MISSING_CASE(plane_state->base.crtc_w);
10140                                 return;
10141                 }
10142                 cntl |= pipe << 28; /* Connect to correct pipe */
10143
10144                 if (HAS_DDI(dev))
10145                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10146
10147                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10148                         cntl |= CURSOR_ROTATE_180;
10149         }
10150
10151         if (intel_crtc->cursor_cntl != cntl) {
10152                 I915_WRITE(CURCNTR(pipe), cntl);
10153                 POSTING_READ(CURCNTR(pipe));
10154                 intel_crtc->cursor_cntl = cntl;
10155         }
10156
10157         /* and commit changes on next vblank */
10158         I915_WRITE(CURBASE(pipe), base);
10159         POSTING_READ(CURBASE(pipe));
10160
10161         intel_crtc->cursor_base = base;
10162 }
10163
10164 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10165 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10166                                      const struct intel_plane_state *plane_state)
10167 {
10168         struct drm_device *dev = crtc->dev;
10169         struct drm_i915_private *dev_priv = dev->dev_private;
10170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10171         int pipe = intel_crtc->pipe;
10172         u32 base = intel_crtc->cursor_addr;
10173         u32 pos = 0;
10174
10175         if (plane_state) {
10176                 int x = plane_state->base.crtc_x;
10177                 int y = plane_state->base.crtc_y;
10178
10179                 if (x < 0) {
10180                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10181                         x = -x;
10182                 }
10183                 pos |= x << CURSOR_X_SHIFT;
10184
10185                 if (y < 0) {
10186                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10187                         y = -y;
10188                 }
10189                 pos |= y << CURSOR_Y_SHIFT;
10190
10191                 /* ILK+ do this automagically */
10192                 if (HAS_GMCH_DISPLAY(dev) &&
10193                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10194                         base += (plane_state->base.crtc_h *
10195                                  plane_state->base.crtc_w - 1) * 4;
10196                 }
10197         }
10198
10199         I915_WRITE(CURPOS(pipe), pos);
10200
10201         if (IS_845G(dev) || IS_I865G(dev))
10202                 i845_update_cursor(crtc, base, plane_state);
10203         else
10204                 i9xx_update_cursor(crtc, base, plane_state);
10205 }
10206
10207 static bool cursor_size_ok(struct drm_device *dev,
10208                            uint32_t width, uint32_t height)
10209 {
10210         if (width == 0 || height == 0)
10211                 return false;
10212
10213         /*
10214          * 845g/865g are special in that they are only limited by
10215          * the width of their cursors, the height is arbitrary up to
10216          * the precision of the register. Everything else requires
10217          * square cursors, limited to a few power-of-two sizes.
10218          */
10219         if (IS_845G(dev) || IS_I865G(dev)) {
10220                 if ((width & 63) != 0)
10221                         return false;
10222
10223                 if (width > (IS_845G(dev) ? 64 : 512))
10224                         return false;
10225
10226                 if (height > 1023)
10227                         return false;
10228         } else {
10229                 switch (width | height) {
10230                 case 256:
10231                 case 128:
10232                         if (IS_GEN2(dev))
10233                                 return false;
10234                 case 64:
10235                         break;
10236                 default:
10237                         return false;
10238                 }
10239         }
10240
10241         return true;
10242 }
10243
10244 /* VESA 640x480x72Hz mode to set on the pipe */
10245 static struct drm_display_mode load_detect_mode = {
10246         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10247                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10248 };
10249
10250 struct drm_framebuffer *
10251 __intel_framebuffer_create(struct drm_device *dev,
10252                            struct drm_mode_fb_cmd2 *mode_cmd,
10253                            struct drm_i915_gem_object *obj)
10254 {
10255         struct intel_framebuffer *intel_fb;
10256         int ret;
10257
10258         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10259         if (!intel_fb)
10260                 return ERR_PTR(-ENOMEM);
10261
10262         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10263         if (ret)
10264                 goto err;
10265
10266         return &intel_fb->base;
10267
10268 err:
10269         kfree(intel_fb);
10270         return ERR_PTR(ret);
10271 }
10272
10273 static struct drm_framebuffer *
10274 intel_framebuffer_create(struct drm_device *dev,
10275                          struct drm_mode_fb_cmd2 *mode_cmd,
10276                          struct drm_i915_gem_object *obj)
10277 {
10278         struct drm_framebuffer *fb;
10279         int ret;
10280
10281         ret = i915_mutex_lock_interruptible(dev);
10282         if (ret)
10283                 return ERR_PTR(ret);
10284         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10285         mutex_unlock(&dev->struct_mutex);
10286
10287         return fb;
10288 }
10289
10290 static u32
10291 intel_framebuffer_pitch_for_width(int width, int bpp)
10292 {
10293         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10294         return ALIGN(pitch, 64);
10295 }
10296
10297 static u32
10298 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10299 {
10300         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10301         return PAGE_ALIGN(pitch * mode->vdisplay);
10302 }
10303
10304 static struct drm_framebuffer *
10305 intel_framebuffer_create_for_mode(struct drm_device *dev,
10306                                   struct drm_display_mode *mode,
10307                                   int depth, int bpp)
10308 {
10309         struct drm_framebuffer *fb;
10310         struct drm_i915_gem_object *obj;
10311         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10312
10313         obj = i915_gem_object_create(dev,
10314                                     intel_framebuffer_size_for_mode(mode, bpp));
10315         if (IS_ERR(obj))
10316                 return ERR_CAST(obj);
10317
10318         mode_cmd.width = mode->hdisplay;
10319         mode_cmd.height = mode->vdisplay;
10320         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10321                                                                 bpp);
10322         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10323
10324         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10325         if (IS_ERR(fb))
10326                 drm_gem_object_unreference_unlocked(&obj->base);
10327
10328         return fb;
10329 }
10330
10331 static struct drm_framebuffer *
10332 mode_fits_in_fbdev(struct drm_device *dev,
10333                    struct drm_display_mode *mode)
10334 {
10335 #ifdef CONFIG_DRM_FBDEV_EMULATION
10336         struct drm_i915_private *dev_priv = dev->dev_private;
10337         struct drm_i915_gem_object *obj;
10338         struct drm_framebuffer *fb;
10339
10340         if (!dev_priv->fbdev)
10341                 return NULL;
10342
10343         if (!dev_priv->fbdev->fb)
10344                 return NULL;
10345
10346         obj = dev_priv->fbdev->fb->obj;
10347         BUG_ON(!obj);
10348
10349         fb = &dev_priv->fbdev->fb->base;
10350         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10351                                                                fb->bits_per_pixel))
10352                 return NULL;
10353
10354         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10355                 return NULL;
10356
10357         drm_framebuffer_reference(fb);
10358         return fb;
10359 #else
10360         return NULL;
10361 #endif
10362 }
10363
10364 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10365                                            struct drm_crtc *crtc,
10366                                            struct drm_display_mode *mode,
10367                                            struct drm_framebuffer *fb,
10368                                            int x, int y)
10369 {
10370         struct drm_plane_state *plane_state;
10371         int hdisplay, vdisplay;
10372         int ret;
10373
10374         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10375         if (IS_ERR(plane_state))
10376                 return PTR_ERR(plane_state);
10377
10378         if (mode)
10379                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10380         else
10381                 hdisplay = vdisplay = 0;
10382
10383         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10384         if (ret)
10385                 return ret;
10386         drm_atomic_set_fb_for_plane(plane_state, fb);
10387         plane_state->crtc_x = 0;
10388         plane_state->crtc_y = 0;
10389         plane_state->crtc_w = hdisplay;
10390         plane_state->crtc_h = vdisplay;
10391         plane_state->src_x = x << 16;
10392         plane_state->src_y = y << 16;
10393         plane_state->src_w = hdisplay << 16;
10394         plane_state->src_h = vdisplay << 16;
10395
10396         return 0;
10397 }
10398
10399 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10400                                 struct drm_display_mode *mode,
10401                                 struct intel_load_detect_pipe *old,
10402                                 struct drm_modeset_acquire_ctx *ctx)
10403 {
10404         struct intel_crtc *intel_crtc;
10405         struct intel_encoder *intel_encoder =
10406                 intel_attached_encoder(connector);
10407         struct drm_crtc *possible_crtc;
10408         struct drm_encoder *encoder = &intel_encoder->base;
10409         struct drm_crtc *crtc = NULL;
10410         struct drm_device *dev = encoder->dev;
10411         struct drm_framebuffer *fb;
10412         struct drm_mode_config *config = &dev->mode_config;
10413         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10414         struct drm_connector_state *connector_state;
10415         struct intel_crtc_state *crtc_state;
10416         int ret, i = -1;
10417
10418         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10419                       connector->base.id, connector->name,
10420                       encoder->base.id, encoder->name);
10421
10422         old->restore_state = NULL;
10423
10424 retry:
10425         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10426         if (ret)
10427                 goto fail;
10428
10429         /*
10430          * Algorithm gets a little messy:
10431          *
10432          *   - if the connector already has an assigned crtc, use it (but make
10433          *     sure it's on first)
10434          *
10435          *   - try to find the first unused crtc that can drive this connector,
10436          *     and use that if we find one
10437          */
10438
10439         /* See if we already have a CRTC for this connector */
10440         if (connector->state->crtc) {
10441                 crtc = connector->state->crtc;
10442
10443                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10444                 if (ret)
10445                         goto fail;
10446
10447                 /* Make sure the crtc and connector are running */
10448                 goto found;
10449         }
10450
10451         /* Find an unused one (if possible) */
10452         for_each_crtc(dev, possible_crtc) {
10453                 i++;
10454                 if (!(encoder->possible_crtcs & (1 << i)))
10455                         continue;
10456
10457                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10458                 if (ret)
10459                         goto fail;
10460
10461                 if (possible_crtc->state->enable) {
10462                         drm_modeset_unlock(&possible_crtc->mutex);
10463                         continue;
10464                 }
10465
10466                 crtc = possible_crtc;
10467                 break;
10468         }
10469
10470         /*
10471          * If we didn't find an unused CRTC, don't use any.
10472          */
10473         if (!crtc) {
10474                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10475                 goto fail;
10476         }
10477
10478 found:
10479         intel_crtc = to_intel_crtc(crtc);
10480
10481         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10482         if (ret)
10483                 goto fail;
10484
10485         state = drm_atomic_state_alloc(dev);
10486         restore_state = drm_atomic_state_alloc(dev);
10487         if (!state || !restore_state) {
10488                 ret = -ENOMEM;
10489                 goto fail;
10490         }
10491
10492         state->acquire_ctx = ctx;
10493         restore_state->acquire_ctx = ctx;
10494
10495         connector_state = drm_atomic_get_connector_state(state, connector);
10496         if (IS_ERR(connector_state)) {
10497                 ret = PTR_ERR(connector_state);
10498                 goto fail;
10499         }
10500
10501         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10502         if (ret)
10503                 goto fail;
10504
10505         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10506         if (IS_ERR(crtc_state)) {
10507                 ret = PTR_ERR(crtc_state);
10508                 goto fail;
10509         }
10510
10511         crtc_state->base.active = crtc_state->base.enable = true;
10512
10513         if (!mode)
10514                 mode = &load_detect_mode;
10515
10516         /* We need a framebuffer large enough to accommodate all accesses
10517          * that the plane may generate whilst we perform load detection.
10518          * We can not rely on the fbcon either being present (we get called
10519          * during its initialisation to detect all boot displays, or it may
10520          * not even exist) or that it is large enough to satisfy the
10521          * requested mode.
10522          */
10523         fb = mode_fits_in_fbdev(dev, mode);
10524         if (fb == NULL) {
10525                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10526                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10527         } else
10528                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10529         if (IS_ERR(fb)) {
10530                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10531                 goto fail;
10532         }
10533
10534         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10535         if (ret)
10536                 goto fail;
10537
10538         drm_framebuffer_unreference(fb);
10539
10540         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10541         if (ret)
10542                 goto fail;
10543
10544         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10545         if (!ret)
10546                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10547         if (!ret)
10548                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10549         if (ret) {
10550                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10551                 goto fail;
10552         }
10553
10554         ret = drm_atomic_commit(state);
10555         if (ret) {
10556                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10557                 goto fail;
10558         }
10559
10560         old->restore_state = restore_state;
10561
10562         /* let the connector get through one full cycle before testing */
10563         intel_wait_for_vblank(dev, intel_crtc->pipe);
10564         return true;
10565
10566 fail:
10567         drm_atomic_state_free(state);
10568         drm_atomic_state_free(restore_state);
10569         restore_state = state = NULL;
10570
10571         if (ret == -EDEADLK) {
10572                 drm_modeset_backoff(ctx);
10573                 goto retry;
10574         }
10575
10576         return false;
10577 }
10578
10579 void intel_release_load_detect_pipe(struct drm_connector *connector,
10580                                     struct intel_load_detect_pipe *old,
10581                                     struct drm_modeset_acquire_ctx *ctx)
10582 {
10583         struct intel_encoder *intel_encoder =
10584                 intel_attached_encoder(connector);
10585         struct drm_encoder *encoder = &intel_encoder->base;
10586         struct drm_atomic_state *state = old->restore_state;
10587         int ret;
10588
10589         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10590                       connector->base.id, connector->name,
10591                       encoder->base.id, encoder->name);
10592
10593         if (!state)
10594                 return;
10595
10596         ret = drm_atomic_commit(state);
10597         if (ret) {
10598                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10599                 drm_atomic_state_free(state);
10600         }
10601 }
10602
10603 static int i9xx_pll_refclk(struct drm_device *dev,
10604                            const struct intel_crtc_state *pipe_config)
10605 {
10606         struct drm_i915_private *dev_priv = dev->dev_private;
10607         u32 dpll = pipe_config->dpll_hw_state.dpll;
10608
10609         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10610                 return dev_priv->vbt.lvds_ssc_freq;
10611         else if (HAS_PCH_SPLIT(dev))
10612                 return 120000;
10613         else if (!IS_GEN2(dev))
10614                 return 96000;
10615         else
10616                 return 48000;
10617 }
10618
10619 /* Returns the clock of the currently programmed mode of the given pipe. */
10620 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10621                                 struct intel_crtc_state *pipe_config)
10622 {
10623         struct drm_device *dev = crtc->base.dev;
10624         struct drm_i915_private *dev_priv = dev->dev_private;
10625         int pipe = pipe_config->cpu_transcoder;
10626         u32 dpll = pipe_config->dpll_hw_state.dpll;
10627         u32 fp;
10628         struct dpll clock;
10629         int port_clock;
10630         int refclk = i9xx_pll_refclk(dev, pipe_config);
10631
10632         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10633                 fp = pipe_config->dpll_hw_state.fp0;
10634         else
10635                 fp = pipe_config->dpll_hw_state.fp1;
10636
10637         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10638         if (IS_PINEVIEW(dev)) {
10639                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10640                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10641         } else {
10642                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10643                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10644         }
10645
10646         if (!IS_GEN2(dev)) {
10647                 if (IS_PINEVIEW(dev))
10648                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10649                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10650                 else
10651                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10652                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10653
10654                 switch (dpll & DPLL_MODE_MASK) {
10655                 case DPLLB_MODE_DAC_SERIAL:
10656                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10657                                 5 : 10;
10658                         break;
10659                 case DPLLB_MODE_LVDS:
10660                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10661                                 7 : 14;
10662                         break;
10663                 default:
10664                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10665                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10666                         return;
10667                 }
10668
10669                 if (IS_PINEVIEW(dev))
10670                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10671                 else
10672                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10673         } else {
10674                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10675                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10676
10677                 if (is_lvds) {
10678                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10679                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10680
10681                         if (lvds & LVDS_CLKB_POWER_UP)
10682                                 clock.p2 = 7;
10683                         else
10684                                 clock.p2 = 14;
10685                 } else {
10686                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10687                                 clock.p1 = 2;
10688                         else {
10689                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10690                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10691                         }
10692                         if (dpll & PLL_P2_DIVIDE_BY_4)
10693                                 clock.p2 = 4;
10694                         else
10695                                 clock.p2 = 2;
10696                 }
10697
10698                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10699         }
10700
10701         /*
10702          * This value includes pixel_multiplier. We will use
10703          * port_clock to compute adjusted_mode.crtc_clock in the
10704          * encoder's get_config() function.
10705          */
10706         pipe_config->port_clock = port_clock;
10707 }
10708
10709 int intel_dotclock_calculate(int link_freq,
10710                              const struct intel_link_m_n *m_n)
10711 {
10712         /*
10713          * The calculation for the data clock is:
10714          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10715          * But we want to avoid losing precison if possible, so:
10716          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10717          *
10718          * and the link clock is simpler:
10719          * link_clock = (m * link_clock) / n
10720          */
10721
10722         if (!m_n->link_n)
10723                 return 0;
10724
10725         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10726 }
10727
10728 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10729                                    struct intel_crtc_state *pipe_config)
10730 {
10731         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10732
10733         /* read out port_clock from the DPLL */
10734         i9xx_crtc_clock_get(crtc, pipe_config);
10735
10736         /*
10737          * In case there is an active pipe without active ports,
10738          * we may need some idea for the dotclock anyway.
10739          * Calculate one based on the FDI configuration.
10740          */
10741         pipe_config->base.adjusted_mode.crtc_clock =
10742                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10743                                          &pipe_config->fdi_m_n);
10744 }
10745
10746 /** Returns the currently programmed mode of the given pipe. */
10747 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10748                                              struct drm_crtc *crtc)
10749 {
10750         struct drm_i915_private *dev_priv = dev->dev_private;
10751         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10752         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10753         struct drm_display_mode *mode;
10754         struct intel_crtc_state *pipe_config;
10755         int htot = I915_READ(HTOTAL(cpu_transcoder));
10756         int hsync = I915_READ(HSYNC(cpu_transcoder));
10757         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10758         int vsync = I915_READ(VSYNC(cpu_transcoder));
10759         enum pipe pipe = intel_crtc->pipe;
10760
10761         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10762         if (!mode)
10763                 return NULL;
10764
10765         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10766         if (!pipe_config) {
10767                 kfree(mode);
10768                 return NULL;
10769         }
10770
10771         /*
10772          * Construct a pipe_config sufficient for getting the clock info
10773          * back out of crtc_clock_get.
10774          *
10775          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10776          * to use a real value here instead.
10777          */
10778         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10779         pipe_config->pixel_multiplier = 1;
10780         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10781         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10782         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10783         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10784
10785         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10786         mode->hdisplay = (htot & 0xffff) + 1;
10787         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10788         mode->hsync_start = (hsync & 0xffff) + 1;
10789         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10790         mode->vdisplay = (vtot & 0xffff) + 1;
10791         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10792         mode->vsync_start = (vsync & 0xffff) + 1;
10793         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10794
10795         drm_mode_set_name(mode);
10796
10797         kfree(pipe_config);
10798
10799         return mode;
10800 }
10801
10802 void intel_mark_busy(struct drm_i915_private *dev_priv)
10803 {
10804         if (dev_priv->mm.busy)
10805                 return;
10806
10807         intel_runtime_pm_get(dev_priv);
10808         i915_update_gfx_val(dev_priv);
10809         if (INTEL_GEN(dev_priv) >= 6)
10810                 gen6_rps_busy(dev_priv);
10811         dev_priv->mm.busy = true;
10812 }
10813
10814 void intel_mark_idle(struct drm_i915_private *dev_priv)
10815 {
10816         if (!dev_priv->mm.busy)
10817                 return;
10818
10819         dev_priv->mm.busy = false;
10820
10821         if (INTEL_GEN(dev_priv) >= 6)
10822                 gen6_rps_idle(dev_priv);
10823
10824         intel_runtime_pm_put(dev_priv);
10825 }
10826
10827 static void intel_crtc_destroy(struct drm_crtc *crtc)
10828 {
10829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10830         struct drm_device *dev = crtc->dev;
10831         struct intel_unpin_work *work;
10832
10833         spin_lock_irq(&dev->event_lock);
10834         work = intel_crtc->unpin_work;
10835         intel_crtc->unpin_work = NULL;
10836         spin_unlock_irq(&dev->event_lock);
10837
10838         if (work) {
10839                 cancel_work_sync(&work->work);
10840                 kfree(work);
10841         }
10842
10843         drm_crtc_cleanup(crtc);
10844
10845         kfree(intel_crtc);
10846 }
10847
10848 static void intel_unpin_work_fn(struct work_struct *__work)
10849 {
10850         struct intel_unpin_work *work =
10851                 container_of(__work, struct intel_unpin_work, work);
10852         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10853         struct drm_device *dev = crtc->base.dev;
10854         struct drm_plane *primary = crtc->base.primary;
10855
10856         mutex_lock(&dev->struct_mutex);
10857         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10858         drm_gem_object_unreference(&work->pending_flip_obj->base);
10859
10860         if (work->flip_queued_req)
10861                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10862         mutex_unlock(&dev->struct_mutex);
10863
10864         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10865         intel_fbc_post_update(crtc);
10866         drm_framebuffer_unreference(work->old_fb);
10867
10868         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10869         atomic_dec(&crtc->unpin_work_count);
10870
10871         kfree(work);
10872 }
10873
10874 static void do_intel_finish_page_flip(struct drm_i915_private *dev_priv,
10875                                       struct drm_crtc *crtc)
10876 {
10877         struct drm_device *dev = dev_priv->dev;
10878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10879         struct intel_unpin_work *work;
10880         unsigned long flags;
10881
10882         /* Ignore early vblank irqs */
10883         if (intel_crtc == NULL)
10884                 return;
10885
10886         /*
10887          * This is called both by irq handlers and the reset code (to complete
10888          * lost pageflips) so needs the full irqsave spinlocks.
10889          */
10890         spin_lock_irqsave(&dev->event_lock, flags);
10891         work = intel_crtc->unpin_work;
10892
10893         /* Ensure we don't miss a work->pending update ... */
10894         smp_rmb();
10895
10896         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10897                 spin_unlock_irqrestore(&dev->event_lock, flags);
10898                 return;
10899         }
10900
10901         page_flip_completed(intel_crtc);
10902
10903         spin_unlock_irqrestore(&dev->event_lock, flags);
10904 }
10905
10906 void intel_finish_page_flip(struct drm_i915_private *dev_priv, int pipe)
10907 {
10908         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10909
10910         do_intel_finish_page_flip(dev_priv, crtc);
10911 }
10912
10913 void intel_finish_page_flip_plane(struct drm_i915_private *dev_priv, int plane)
10914 {
10915         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10916
10917         do_intel_finish_page_flip(dev_priv, crtc);
10918 }
10919
10920 /* Is 'a' after or equal to 'b'? */
10921 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10922 {
10923         return !((a - b) & 0x80000000);
10924 }
10925
10926 static bool page_flip_finished(struct intel_crtc *crtc)
10927 {
10928         struct drm_device *dev = crtc->base.dev;
10929         struct drm_i915_private *dev_priv = dev->dev_private;
10930         unsigned reset_counter;
10931
10932         reset_counter = i915_reset_counter(&dev_priv->gpu_error);
10933         if (crtc->reset_counter != reset_counter)
10934                 return true;
10935
10936         /*
10937          * The relevant registers doen't exist on pre-ctg.
10938          * As the flip done interrupt doesn't trigger for mmio
10939          * flips on gmch platforms, a flip count check isn't
10940          * really needed there. But since ctg has the registers,
10941          * include it in the check anyway.
10942          */
10943         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10944                 return true;
10945
10946         /*
10947          * BDW signals flip done immediately if the plane
10948          * is disabled, even if the plane enable is already
10949          * armed to occur at the next vblank :(
10950          */
10951
10952         /*
10953          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10954          * used the same base address. In that case the mmio flip might
10955          * have completed, but the CS hasn't even executed the flip yet.
10956          *
10957          * A flip count check isn't enough as the CS might have updated
10958          * the base address just after start of vblank, but before we
10959          * managed to process the interrupt. This means we'd complete the
10960          * CS flip too soon.
10961          *
10962          * Combining both checks should get us a good enough result. It may
10963          * still happen that the CS flip has been executed, but has not
10964          * yet actually completed. But in case the base address is the same
10965          * anyway, we don't really care.
10966          */
10967         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10968                 crtc->unpin_work->gtt_offset &&
10969                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10970                                     crtc->unpin_work->flip_count);
10971 }
10972
10973 void intel_prepare_page_flip(struct drm_i915_private *dev_priv, int plane)
10974 {
10975         struct drm_device *dev = dev_priv->dev;
10976         struct intel_crtc *intel_crtc =
10977                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10978         unsigned long flags;
10979
10980
10981         /*
10982          * This is called both by irq handlers and the reset code (to complete
10983          * lost pageflips) so needs the full irqsave spinlocks.
10984          *
10985          * NB: An MMIO update of the plane base pointer will also
10986          * generate a page-flip completion irq, i.e. every modeset
10987          * is also accompanied by a spurious intel_prepare_page_flip().
10988          */
10989         spin_lock_irqsave(&dev->event_lock, flags);
10990         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10991                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10992         spin_unlock_irqrestore(&dev->event_lock, flags);
10993 }
10994
10995 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10996 {
10997         /* Ensure that the work item is consistent when activating it ... */
10998         smp_wmb();
10999         atomic_set(&work->pending, INTEL_FLIP_PENDING);
11000         /* and that it is marked active as soon as the irq could fire. */
11001         smp_wmb();
11002 }
11003
11004 static int intel_gen2_queue_flip(struct drm_device *dev,
11005                                  struct drm_crtc *crtc,
11006                                  struct drm_framebuffer *fb,
11007                                  struct drm_i915_gem_object *obj,
11008                                  struct drm_i915_gem_request *req,
11009                                  uint32_t flags)
11010 {
11011         struct intel_engine_cs *engine = req->engine;
11012         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11013         u32 flip_mask;
11014         int ret;
11015
11016         ret = intel_ring_begin(req, 6);
11017         if (ret)
11018                 return ret;
11019
11020         /* Can't queue multiple flips, so wait for the previous
11021          * one to finish before executing the next.
11022          */
11023         if (intel_crtc->plane)
11024                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11025         else
11026                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11027         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11028         intel_ring_emit(engine, MI_NOOP);
11029         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11030                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11031         intel_ring_emit(engine, fb->pitches[0]);
11032         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11033         intel_ring_emit(engine, 0); /* aux display base address, unused */
11034
11035         intel_mark_page_flip_active(intel_crtc->unpin_work);
11036         return 0;
11037 }
11038
11039 static int intel_gen3_queue_flip(struct drm_device *dev,
11040                                  struct drm_crtc *crtc,
11041                                  struct drm_framebuffer *fb,
11042                                  struct drm_i915_gem_object *obj,
11043                                  struct drm_i915_gem_request *req,
11044                                  uint32_t flags)
11045 {
11046         struct intel_engine_cs *engine = req->engine;
11047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11048         u32 flip_mask;
11049         int ret;
11050
11051         ret = intel_ring_begin(req, 6);
11052         if (ret)
11053                 return ret;
11054
11055         if (intel_crtc->plane)
11056                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11057         else
11058                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11059         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11060         intel_ring_emit(engine, MI_NOOP);
11061         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11062                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11063         intel_ring_emit(engine, fb->pitches[0]);
11064         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11065         intel_ring_emit(engine, MI_NOOP);
11066
11067         intel_mark_page_flip_active(intel_crtc->unpin_work);
11068         return 0;
11069 }
11070
11071 static int intel_gen4_queue_flip(struct drm_device *dev,
11072                                  struct drm_crtc *crtc,
11073                                  struct drm_framebuffer *fb,
11074                                  struct drm_i915_gem_object *obj,
11075                                  struct drm_i915_gem_request *req,
11076                                  uint32_t flags)
11077 {
11078         struct intel_engine_cs *engine = req->engine;
11079         struct drm_i915_private *dev_priv = dev->dev_private;
11080         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11081         uint32_t pf, pipesrc;
11082         int ret;
11083
11084         ret = intel_ring_begin(req, 4);
11085         if (ret)
11086                 return ret;
11087
11088         /* i965+ uses the linear or tiled offsets from the
11089          * Display Registers (which do not change across a page-flip)
11090          * so we need only reprogram the base address.
11091          */
11092         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11093                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11094         intel_ring_emit(engine, fb->pitches[0]);
11095         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset |
11096                         obj->tiling_mode);
11097
11098         /* XXX Enabling the panel-fitter across page-flip is so far
11099          * untested on non-native modes, so ignore it for now.
11100          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11101          */
11102         pf = 0;
11103         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11104         intel_ring_emit(engine, pf | pipesrc);
11105
11106         intel_mark_page_flip_active(intel_crtc->unpin_work);
11107         return 0;
11108 }
11109
11110 static int intel_gen6_queue_flip(struct drm_device *dev,
11111                                  struct drm_crtc *crtc,
11112                                  struct drm_framebuffer *fb,
11113                                  struct drm_i915_gem_object *obj,
11114                                  struct drm_i915_gem_request *req,
11115                                  uint32_t flags)
11116 {
11117         struct intel_engine_cs *engine = req->engine;
11118         struct drm_i915_private *dev_priv = dev->dev_private;
11119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11120         uint32_t pf, pipesrc;
11121         int ret;
11122
11123         ret = intel_ring_begin(req, 4);
11124         if (ret)
11125                 return ret;
11126
11127         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11128                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11129         intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11130         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11131
11132         /* Contrary to the suggestions in the documentation,
11133          * "Enable Panel Fitter" does not seem to be required when page
11134          * flipping with a non-native mode, and worse causes a normal
11135          * modeset to fail.
11136          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11137          */
11138         pf = 0;
11139         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11140         intel_ring_emit(engine, pf | pipesrc);
11141
11142         intel_mark_page_flip_active(intel_crtc->unpin_work);
11143         return 0;
11144 }
11145
11146 static int intel_gen7_queue_flip(struct drm_device *dev,
11147                                  struct drm_crtc *crtc,
11148                                  struct drm_framebuffer *fb,
11149                                  struct drm_i915_gem_object *obj,
11150                                  struct drm_i915_gem_request *req,
11151                                  uint32_t flags)
11152 {
11153         struct intel_engine_cs *engine = req->engine;
11154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11155         uint32_t plane_bit = 0;
11156         int len, ret;
11157
11158         switch (intel_crtc->plane) {
11159         case PLANE_A:
11160                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11161                 break;
11162         case PLANE_B:
11163                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11164                 break;
11165         case PLANE_C:
11166                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11167                 break;
11168         default:
11169                 WARN_ONCE(1, "unknown plane in flip command\n");
11170                 return -ENODEV;
11171         }
11172
11173         len = 4;
11174         if (engine->id == RCS) {
11175                 len += 6;
11176                 /*
11177                  * On Gen 8, SRM is now taking an extra dword to accommodate
11178                  * 48bits addresses, and we need a NOOP for the batch size to
11179                  * stay even.
11180                  */
11181                 if (IS_GEN8(dev))
11182                         len += 2;
11183         }
11184
11185         /*
11186          * BSpec MI_DISPLAY_FLIP for IVB:
11187          * "The full packet must be contained within the same cache line."
11188          *
11189          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11190          * cacheline, if we ever start emitting more commands before
11191          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11192          * then do the cacheline alignment, and finally emit the
11193          * MI_DISPLAY_FLIP.
11194          */
11195         ret = intel_ring_cacheline_align(req);
11196         if (ret)
11197                 return ret;
11198
11199         ret = intel_ring_begin(req, len);
11200         if (ret)
11201                 return ret;
11202
11203         /* Unmask the flip-done completion message. Note that the bspec says that
11204          * we should do this for both the BCS and RCS, and that we must not unmask
11205          * more than one flip event at any time (or ensure that one flip message
11206          * can be sent by waiting for flip-done prior to queueing new flips).
11207          * Experimentation says that BCS works despite DERRMR masking all
11208          * flip-done completion events and that unmasking all planes at once
11209          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11210          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11211          */
11212         if (engine->id == RCS) {
11213                 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11214                 intel_ring_emit_reg(engine, DERRMR);
11215                 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11216                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11217                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11218                 if (IS_GEN8(dev))
11219                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11220                                               MI_SRM_LRM_GLOBAL_GTT);
11221                 else
11222                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11223                                               MI_SRM_LRM_GLOBAL_GTT);
11224                 intel_ring_emit_reg(engine, DERRMR);
11225                 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11226                 if (IS_GEN8(dev)) {
11227                         intel_ring_emit(engine, 0);
11228                         intel_ring_emit(engine, MI_NOOP);
11229                 }
11230         }
11231
11232         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11233         intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11234         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11235         intel_ring_emit(engine, (MI_NOOP));
11236
11237         intel_mark_page_flip_active(intel_crtc->unpin_work);
11238         return 0;
11239 }
11240
11241 static bool use_mmio_flip(struct intel_engine_cs *engine,
11242                           struct drm_i915_gem_object *obj)
11243 {
11244         /*
11245          * This is not being used for older platforms, because
11246          * non-availability of flip done interrupt forces us to use
11247          * CS flips. Older platforms derive flip done using some clever
11248          * tricks involving the flip_pending status bits and vblank irqs.
11249          * So using MMIO flips there would disrupt this mechanism.
11250          */
11251
11252         if (engine == NULL)
11253                 return true;
11254
11255         if (INTEL_GEN(engine->i915) < 5)
11256                 return false;
11257
11258         if (i915.use_mmio_flip < 0)
11259                 return false;
11260         else if (i915.use_mmio_flip > 0)
11261                 return true;
11262         else if (i915.enable_execlists)
11263                 return true;
11264         else if (obj->base.dma_buf &&
11265                  !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11266                                                        false))
11267                 return true;
11268         else
11269                 return engine != i915_gem_request_get_engine(obj->last_write_req);
11270 }
11271
11272 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11273                              unsigned int rotation,
11274                              struct intel_unpin_work *work)
11275 {
11276         struct drm_device *dev = intel_crtc->base.dev;
11277         struct drm_i915_private *dev_priv = dev->dev_private;
11278         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11279         const enum pipe pipe = intel_crtc->pipe;
11280         u32 ctl, stride, tile_height;
11281
11282         ctl = I915_READ(PLANE_CTL(pipe, 0));
11283         ctl &= ~PLANE_CTL_TILED_MASK;
11284         switch (fb->modifier[0]) {
11285         case DRM_FORMAT_MOD_NONE:
11286                 break;
11287         case I915_FORMAT_MOD_X_TILED:
11288                 ctl |= PLANE_CTL_TILED_X;
11289                 break;
11290         case I915_FORMAT_MOD_Y_TILED:
11291                 ctl |= PLANE_CTL_TILED_Y;
11292                 break;
11293         case I915_FORMAT_MOD_Yf_TILED:
11294                 ctl |= PLANE_CTL_TILED_YF;
11295                 break;
11296         default:
11297                 MISSING_CASE(fb->modifier[0]);
11298         }
11299
11300         /*
11301          * The stride is either expressed as a multiple of 64 bytes chunks for
11302          * linear buffers or in number of tiles for tiled buffers.
11303          */
11304         if (intel_rotation_90_or_270(rotation)) {
11305                 /* stride = Surface height in tiles */
11306                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11307                 stride = DIV_ROUND_UP(fb->height, tile_height);
11308         } else {
11309                 stride = fb->pitches[0] /
11310                         intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11311                                                   fb->pixel_format);
11312         }
11313
11314         /*
11315          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11316          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11317          */
11318         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11319         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11320
11321         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11322         POSTING_READ(PLANE_SURF(pipe, 0));
11323 }
11324
11325 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11326                              struct intel_unpin_work *work)
11327 {
11328         struct drm_device *dev = intel_crtc->base.dev;
11329         struct drm_i915_private *dev_priv = dev->dev_private;
11330         struct intel_framebuffer *intel_fb =
11331                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11332         struct drm_i915_gem_object *obj = intel_fb->obj;
11333         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11334         u32 dspcntr;
11335
11336         dspcntr = I915_READ(reg);
11337
11338         if (obj->tiling_mode != I915_TILING_NONE)
11339                 dspcntr |= DISPPLANE_TILED;
11340         else
11341                 dspcntr &= ~DISPPLANE_TILED;
11342
11343         I915_WRITE(reg, dspcntr);
11344
11345         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11346         POSTING_READ(DSPSURF(intel_crtc->plane));
11347 }
11348
11349 /*
11350  * XXX: This is the temporary way to update the plane registers until we get
11351  * around to using the usual plane update functions for MMIO flips
11352  */
11353 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11354 {
11355         struct intel_crtc *crtc = mmio_flip->crtc;
11356         struct intel_unpin_work *work;
11357
11358         spin_lock_irq(&crtc->base.dev->event_lock);
11359         work = crtc->unpin_work;
11360         spin_unlock_irq(&crtc->base.dev->event_lock);
11361         if (work == NULL)
11362                 return;
11363
11364         intel_mark_page_flip_active(work);
11365
11366         intel_pipe_update_start(crtc);
11367
11368         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11369                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11370         else
11371                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11372                 ilk_do_mmio_flip(crtc, work);
11373
11374         intel_pipe_update_end(crtc);
11375 }
11376
11377 static void intel_mmio_flip_work_func(struct work_struct *work)
11378 {
11379         struct intel_mmio_flip *mmio_flip =
11380                 container_of(work, struct intel_mmio_flip, work);
11381         struct intel_framebuffer *intel_fb =
11382                 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11383         struct drm_i915_gem_object *obj = intel_fb->obj;
11384
11385         if (mmio_flip->req) {
11386                 WARN_ON(__i915_wait_request(mmio_flip->req,
11387                                             false, NULL,
11388                                             &mmio_flip->i915->rps.mmioflips));
11389                 i915_gem_request_unreference(mmio_flip->req);
11390         }
11391
11392         /* For framebuffer backed by dmabuf, wait for fence */
11393         if (obj->base.dma_buf)
11394                 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11395                                                             false, false,
11396                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11397
11398         intel_do_mmio_flip(mmio_flip);
11399         kfree(mmio_flip);
11400 }
11401
11402 static int intel_queue_mmio_flip(struct drm_device *dev,
11403                                  struct drm_crtc *crtc,
11404                                  struct drm_i915_gem_object *obj)
11405 {
11406         struct intel_mmio_flip *mmio_flip;
11407
11408         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11409         if (mmio_flip == NULL)
11410                 return -ENOMEM;
11411
11412         mmio_flip->i915 = to_i915(dev);
11413         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11414         mmio_flip->crtc = to_intel_crtc(crtc);
11415         mmio_flip->rotation = crtc->primary->state->rotation;
11416
11417         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11418         schedule_work(&mmio_flip->work);
11419
11420         return 0;
11421 }
11422
11423 static int intel_default_queue_flip(struct drm_device *dev,
11424                                     struct drm_crtc *crtc,
11425                                     struct drm_framebuffer *fb,
11426                                     struct drm_i915_gem_object *obj,
11427                                     struct drm_i915_gem_request *req,
11428                                     uint32_t flags)
11429 {
11430         return -ENODEV;
11431 }
11432
11433 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11434                                          struct drm_crtc *crtc)
11435 {
11436         struct drm_i915_private *dev_priv = dev->dev_private;
11437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11438         struct intel_unpin_work *work = intel_crtc->unpin_work;
11439         u32 addr;
11440
11441         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11442                 return true;
11443
11444         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11445                 return false;
11446
11447         if (!work->enable_stall_check)
11448                 return false;
11449
11450         if (work->flip_ready_vblank == 0) {
11451                 if (work->flip_queued_req &&
11452                     !i915_gem_request_completed(work->flip_queued_req, true))
11453                         return false;
11454
11455                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11456         }
11457
11458         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11459                 return false;
11460
11461         /* Potential stall - if we see that the flip has happened,
11462          * assume a missed interrupt. */
11463         if (INTEL_INFO(dev)->gen >= 4)
11464                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11465         else
11466                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11467
11468         /* There is a potential issue here with a false positive after a flip
11469          * to the same address. We could address this by checking for a
11470          * non-incrementing frame counter.
11471          */
11472         return addr == work->gtt_offset;
11473 }
11474
11475 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11476 {
11477         struct drm_device *dev = dev_priv->dev;
11478         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11479         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11480         struct intel_unpin_work *work;
11481
11482         WARN_ON(!in_interrupt());
11483
11484         if (crtc == NULL)
11485                 return;
11486
11487         spin_lock(&dev->event_lock);
11488         work = intel_crtc->unpin_work;
11489         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11490                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11491                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11492                 page_flip_completed(intel_crtc);
11493                 work = NULL;
11494         }
11495         if (work != NULL &&
11496             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11497                 intel_queue_rps_boost_for_request(work->flip_queued_req);
11498         spin_unlock(&dev->event_lock);
11499 }
11500
11501 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11502                                 struct drm_framebuffer *fb,
11503                                 struct drm_pending_vblank_event *event,
11504                                 uint32_t page_flip_flags)
11505 {
11506         struct drm_device *dev = crtc->dev;
11507         struct drm_i915_private *dev_priv = dev->dev_private;
11508         struct drm_framebuffer *old_fb = crtc->primary->fb;
11509         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11511         struct drm_plane *primary = crtc->primary;
11512         enum pipe pipe = intel_crtc->pipe;
11513         struct intel_unpin_work *work;
11514         struct intel_engine_cs *engine;
11515         bool mmio_flip;
11516         struct drm_i915_gem_request *request = NULL;
11517         int ret;
11518
11519         /*
11520          * drm_mode_page_flip_ioctl() should already catch this, but double
11521          * check to be safe.  In the future we may enable pageflipping from
11522          * a disabled primary plane.
11523          */
11524         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11525                 return -EBUSY;
11526
11527         /* Can't change pixel format via MI display flips. */
11528         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11529                 return -EINVAL;
11530
11531         /*
11532          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11533          * Note that pitch changes could also affect these register.
11534          */
11535         if (INTEL_INFO(dev)->gen > 3 &&
11536             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11537              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11538                 return -EINVAL;
11539
11540         if (i915_terminally_wedged(&dev_priv->gpu_error))
11541                 goto out_hang;
11542
11543         work = kzalloc(sizeof(*work), GFP_KERNEL);
11544         if (work == NULL)
11545                 return -ENOMEM;
11546
11547         work->event = event;
11548         work->crtc = crtc;
11549         work->old_fb = old_fb;
11550         INIT_WORK(&work->work, intel_unpin_work_fn);
11551
11552         ret = drm_crtc_vblank_get(crtc);
11553         if (ret)
11554                 goto free_work;
11555
11556         /* We borrow the event spin lock for protecting unpin_work */
11557         spin_lock_irq(&dev->event_lock);
11558         if (intel_crtc->unpin_work) {
11559                 /* Before declaring the flip queue wedged, check if
11560                  * the hardware completed the operation behind our backs.
11561                  */
11562                 if (__intel_pageflip_stall_check(dev, crtc)) {
11563                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11564                         page_flip_completed(intel_crtc);
11565                 } else {
11566                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11567                         spin_unlock_irq(&dev->event_lock);
11568
11569                         drm_crtc_vblank_put(crtc);
11570                         kfree(work);
11571                         return -EBUSY;
11572                 }
11573         }
11574         intel_crtc->unpin_work = work;
11575         spin_unlock_irq(&dev->event_lock);
11576
11577         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11578                 flush_workqueue(dev_priv->wq);
11579
11580         /* Reference the objects for the scheduled work. */
11581         drm_framebuffer_reference(work->old_fb);
11582         drm_gem_object_reference(&obj->base);
11583
11584         crtc->primary->fb = fb;
11585         update_state_fb(crtc->primary);
11586         intel_fbc_pre_update(intel_crtc);
11587
11588         work->pending_flip_obj = obj;
11589
11590         ret = i915_mutex_lock_interruptible(dev);
11591         if (ret)
11592                 goto cleanup;
11593
11594         intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11595         if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11596                 ret = -EIO;
11597                 goto cleanup;
11598         }
11599
11600         atomic_inc(&intel_crtc->unpin_work_count);
11601
11602         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11603                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11604
11605         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11606                 engine = &dev_priv->engine[BCS];
11607                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11608                         /* vlv: DISPLAY_FLIP fails to change tiling */
11609                         engine = NULL;
11610         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11611                 engine = &dev_priv->engine[BCS];
11612         } else if (INTEL_INFO(dev)->gen >= 7) {
11613                 engine = i915_gem_request_get_engine(obj->last_write_req);
11614                 if (engine == NULL || engine->id != RCS)
11615                         engine = &dev_priv->engine[BCS];
11616         } else {
11617                 engine = &dev_priv->engine[RCS];
11618         }
11619
11620         mmio_flip = use_mmio_flip(engine, obj);
11621
11622         /* When using CS flips, we want to emit semaphores between rings.
11623          * However, when using mmio flips we will create a task to do the
11624          * synchronisation, so all we want here is to pin the framebuffer
11625          * into the display plane and skip any waits.
11626          */
11627         if (!mmio_flip) {
11628                 ret = i915_gem_object_sync(obj, engine, &request);
11629                 if (ret)
11630                         goto cleanup_pending;
11631         }
11632
11633         ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11634         if (ret)
11635                 goto cleanup_pending;
11636
11637         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11638                                                   obj, 0);
11639         work->gtt_offset += intel_crtc->dspaddr_offset;
11640
11641         if (mmio_flip) {
11642                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11643                 if (ret)
11644                         goto cleanup_unpin;
11645
11646                 i915_gem_request_assign(&work->flip_queued_req,
11647                                         obj->last_write_req);
11648         } else {
11649                 if (!request) {
11650                         request = i915_gem_request_alloc(engine, NULL);
11651                         if (IS_ERR(request)) {
11652                                 ret = PTR_ERR(request);
11653                                 goto cleanup_unpin;
11654                         }
11655                 }
11656
11657                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11658                                                    page_flip_flags);
11659                 if (ret)
11660                         goto cleanup_unpin;
11661
11662                 i915_gem_request_assign(&work->flip_queued_req, request);
11663         }
11664
11665         if (request)
11666                 i915_add_request_no_flush(request);
11667
11668         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11669         work->enable_stall_check = true;
11670
11671         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11672                           to_intel_plane(primary)->frontbuffer_bit);
11673         mutex_unlock(&dev->struct_mutex);
11674
11675         intel_frontbuffer_flip_prepare(dev,
11676                                        to_intel_plane(primary)->frontbuffer_bit);
11677
11678         trace_i915_flip_request(intel_crtc->plane, obj);
11679
11680         return 0;
11681
11682 cleanup_unpin:
11683         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11684 cleanup_pending:
11685         if (!IS_ERR_OR_NULL(request))
11686                 i915_add_request_no_flush(request);
11687         atomic_dec(&intel_crtc->unpin_work_count);
11688         mutex_unlock(&dev->struct_mutex);
11689 cleanup:
11690         crtc->primary->fb = old_fb;
11691         update_state_fb(crtc->primary);
11692
11693         drm_gem_object_unreference_unlocked(&obj->base);
11694         drm_framebuffer_unreference(work->old_fb);
11695
11696         spin_lock_irq(&dev->event_lock);
11697         intel_crtc->unpin_work = NULL;
11698         spin_unlock_irq(&dev->event_lock);
11699
11700         drm_crtc_vblank_put(crtc);
11701 free_work:
11702         kfree(work);
11703
11704         if (ret == -EIO) {
11705                 struct drm_atomic_state *state;
11706                 struct drm_plane_state *plane_state;
11707
11708 out_hang:
11709                 state = drm_atomic_state_alloc(dev);
11710                 if (!state)
11711                         return -ENOMEM;
11712                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11713
11714 retry:
11715                 plane_state = drm_atomic_get_plane_state(state, primary);
11716                 ret = PTR_ERR_OR_ZERO(plane_state);
11717                 if (!ret) {
11718                         drm_atomic_set_fb_for_plane(plane_state, fb);
11719
11720                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11721                         if (!ret)
11722                                 ret = drm_atomic_commit(state);
11723                 }
11724
11725                 if (ret == -EDEADLK) {
11726                         drm_modeset_backoff(state->acquire_ctx);
11727                         drm_atomic_state_clear(state);
11728                         goto retry;
11729                 }
11730
11731                 if (ret)
11732                         drm_atomic_state_free(state);
11733
11734                 if (ret == 0 && event) {
11735                         spin_lock_irq(&dev->event_lock);
11736                         drm_crtc_send_vblank_event(crtc, event);
11737                         spin_unlock_irq(&dev->event_lock);
11738                 }
11739         }
11740         return ret;
11741 }
11742
11743
11744 /**
11745  * intel_wm_need_update - Check whether watermarks need updating
11746  * @plane: drm plane
11747  * @state: new plane state
11748  *
11749  * Check current plane state versus the new one to determine whether
11750  * watermarks need to be recalculated.
11751  *
11752  * Returns true or false.
11753  */
11754 static bool intel_wm_need_update(struct drm_plane *plane,
11755                                  struct drm_plane_state *state)
11756 {
11757         struct intel_plane_state *new = to_intel_plane_state(state);
11758         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11759
11760         /* Update watermarks on tiling or size changes. */
11761         if (new->visible != cur->visible)
11762                 return true;
11763
11764         if (!cur->base.fb || !new->base.fb)
11765                 return false;
11766
11767         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11768             cur->base.rotation != new->base.rotation ||
11769             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11770             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11771             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11772             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11773                 return true;
11774
11775         return false;
11776 }
11777
11778 static bool needs_scaling(struct intel_plane_state *state)
11779 {
11780         int src_w = drm_rect_width(&state->src) >> 16;
11781         int src_h = drm_rect_height(&state->src) >> 16;
11782         int dst_w = drm_rect_width(&state->dst);
11783         int dst_h = drm_rect_height(&state->dst);
11784
11785         return (src_w != dst_w || src_h != dst_h);
11786 }
11787
11788 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11789                                     struct drm_plane_state *plane_state)
11790 {
11791         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11792         struct drm_crtc *crtc = crtc_state->crtc;
11793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11794         struct drm_plane *plane = plane_state->plane;
11795         struct drm_device *dev = crtc->dev;
11796         struct drm_i915_private *dev_priv = to_i915(dev);
11797         struct intel_plane_state *old_plane_state =
11798                 to_intel_plane_state(plane->state);
11799         int idx = intel_crtc->base.base.id, ret;
11800         bool mode_changed = needs_modeset(crtc_state);
11801         bool was_crtc_enabled = crtc->state->active;
11802         bool is_crtc_enabled = crtc_state->active;
11803         bool turn_off, turn_on, visible, was_visible;
11804         struct drm_framebuffer *fb = plane_state->fb;
11805
11806         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11807             plane->type != DRM_PLANE_TYPE_CURSOR) {
11808                 ret = skl_update_scaler_plane(
11809                         to_intel_crtc_state(crtc_state),
11810                         to_intel_plane_state(plane_state));
11811                 if (ret)
11812                         return ret;
11813         }
11814
11815         was_visible = old_plane_state->visible;
11816         visible = to_intel_plane_state(plane_state)->visible;
11817
11818         if (!was_crtc_enabled && WARN_ON(was_visible))
11819                 was_visible = false;
11820
11821         /*
11822          * Visibility is calculated as if the crtc was on, but
11823          * after scaler setup everything depends on it being off
11824          * when the crtc isn't active.
11825          *
11826          * FIXME this is wrong for watermarks. Watermarks should also
11827          * be computed as if the pipe would be active. Perhaps move
11828          * per-plane wm computation to the .check_plane() hook, and
11829          * only combine the results from all planes in the current place?
11830          */
11831         if (!is_crtc_enabled)
11832                 to_intel_plane_state(plane_state)->visible = visible = false;
11833
11834         if (!was_visible && !visible)
11835                 return 0;
11836
11837         if (fb != old_plane_state->base.fb)
11838                 pipe_config->fb_changed = true;
11839
11840         turn_off = was_visible && (!visible || mode_changed);
11841         turn_on = visible && (!was_visible || mode_changed);
11842
11843         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11844                          plane->base.id, fb ? fb->base.id : -1);
11845
11846         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11847                          plane->base.id, was_visible, visible,
11848                          turn_off, turn_on, mode_changed);
11849
11850         if (turn_on) {
11851                 pipe_config->update_wm_pre = true;
11852
11853                 /* must disable cxsr around plane enable/disable */
11854                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11855                         pipe_config->disable_cxsr = true;
11856         } else if (turn_off) {
11857                 pipe_config->update_wm_post = true;
11858
11859                 /* must disable cxsr around plane enable/disable */
11860                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11861                         pipe_config->disable_cxsr = true;
11862         } else if (intel_wm_need_update(plane, plane_state)) {
11863                 /* FIXME bollocks */
11864                 pipe_config->update_wm_pre = true;
11865                 pipe_config->update_wm_post = true;
11866         }
11867
11868         /* Pre-gen9 platforms need two-step watermark updates */
11869         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11870             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11871                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11872
11873         if (visible || was_visible)
11874                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11875
11876         /*
11877          * WaCxSRDisabledForSpriteScaling:ivb
11878          *
11879          * cstate->update_wm was already set above, so this flag will
11880          * take effect when we commit and program watermarks.
11881          */
11882         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11883             needs_scaling(to_intel_plane_state(plane_state)) &&
11884             !needs_scaling(old_plane_state))
11885                 pipe_config->disable_lp_wm = true;
11886
11887         return 0;
11888 }
11889
11890 static bool encoders_cloneable(const struct intel_encoder *a,
11891                                const struct intel_encoder *b)
11892 {
11893         /* masks could be asymmetric, so check both ways */
11894         return a == b || (a->cloneable & (1 << b->type) &&
11895                           b->cloneable & (1 << a->type));
11896 }
11897
11898 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11899                                          struct intel_crtc *crtc,
11900                                          struct intel_encoder *encoder)
11901 {
11902         struct intel_encoder *source_encoder;
11903         struct drm_connector *connector;
11904         struct drm_connector_state *connector_state;
11905         int i;
11906
11907         for_each_connector_in_state(state, connector, connector_state, i) {
11908                 if (connector_state->crtc != &crtc->base)
11909                         continue;
11910
11911                 source_encoder =
11912                         to_intel_encoder(connector_state->best_encoder);
11913                 if (!encoders_cloneable(encoder, source_encoder))
11914                         return false;
11915         }
11916
11917         return true;
11918 }
11919
11920 static bool check_encoder_cloning(struct drm_atomic_state *state,
11921                                   struct intel_crtc *crtc)
11922 {
11923         struct intel_encoder *encoder;
11924         struct drm_connector *connector;
11925         struct drm_connector_state *connector_state;
11926         int i;
11927
11928         for_each_connector_in_state(state, connector, connector_state, i) {
11929                 if (connector_state->crtc != &crtc->base)
11930                         continue;
11931
11932                 encoder = to_intel_encoder(connector_state->best_encoder);
11933                 if (!check_single_encoder_cloning(state, crtc, encoder))
11934                         return false;
11935         }
11936
11937         return true;
11938 }
11939
11940 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11941                                    struct drm_crtc_state *crtc_state)
11942 {
11943         struct drm_device *dev = crtc->dev;
11944         struct drm_i915_private *dev_priv = dev->dev_private;
11945         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11946         struct intel_crtc_state *pipe_config =
11947                 to_intel_crtc_state(crtc_state);
11948         struct drm_atomic_state *state = crtc_state->state;
11949         int ret;
11950         bool mode_changed = needs_modeset(crtc_state);
11951
11952         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11953                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11954                 return -EINVAL;
11955         }
11956
11957         if (mode_changed && !crtc_state->active)
11958                 pipe_config->update_wm_post = true;
11959
11960         if (mode_changed && crtc_state->enable &&
11961             dev_priv->display.crtc_compute_clock &&
11962             !WARN_ON(pipe_config->shared_dpll)) {
11963                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11964                                                            pipe_config);
11965                 if (ret)
11966                         return ret;
11967         }
11968
11969         if (crtc_state->color_mgmt_changed) {
11970                 ret = intel_color_check(crtc, crtc_state);
11971                 if (ret)
11972                         return ret;
11973         }
11974
11975         ret = 0;
11976         if (dev_priv->display.compute_pipe_wm) {
11977                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11978                 if (ret) {
11979                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11980                         return ret;
11981                 }
11982         }
11983
11984         if (dev_priv->display.compute_intermediate_wm &&
11985             !to_intel_atomic_state(state)->skip_intermediate_wm) {
11986                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11987                         return 0;
11988
11989                 /*
11990                  * Calculate 'intermediate' watermarks that satisfy both the
11991                  * old state and the new state.  We can program these
11992                  * immediately.
11993                  */
11994                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11995                                                                 intel_crtc,
11996                                                                 pipe_config);
11997                 if (ret) {
11998                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11999                         return ret;
12000                 }
12001         }
12002
12003         if (INTEL_INFO(dev)->gen >= 9) {
12004                 if (mode_changed)
12005                         ret = skl_update_scaler_crtc(pipe_config);
12006
12007                 if (!ret)
12008                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12009                                                          pipe_config);
12010         }
12011
12012         return ret;
12013 }
12014
12015 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12016         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12017         .atomic_begin = intel_begin_crtc_commit,
12018         .atomic_flush = intel_finish_crtc_commit,
12019         .atomic_check = intel_crtc_atomic_check,
12020 };
12021
12022 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12023 {
12024         struct intel_connector *connector;
12025
12026         for_each_intel_connector(dev, connector) {
12027                 if (connector->base.encoder) {
12028                         connector->base.state->best_encoder =
12029                                 connector->base.encoder;
12030                         connector->base.state->crtc =
12031                                 connector->base.encoder->crtc;
12032                 } else {
12033                         connector->base.state->best_encoder = NULL;
12034                         connector->base.state->crtc = NULL;
12035                 }
12036         }
12037 }
12038
12039 static void
12040 connected_sink_compute_bpp(struct intel_connector *connector,
12041                            struct intel_crtc_state *pipe_config)
12042 {
12043         int bpp = pipe_config->pipe_bpp;
12044
12045         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12046                 connector->base.base.id,
12047                 connector->base.name);
12048
12049         /* Don't use an invalid EDID bpc value */
12050         if (connector->base.display_info.bpc &&
12051             connector->base.display_info.bpc * 3 < bpp) {
12052                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12053                               bpp, connector->base.display_info.bpc*3);
12054                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12055         }
12056
12057         /* Clamp bpp to default limit on screens without EDID 1.4 */
12058         if (connector->base.display_info.bpc == 0) {
12059                 int type = connector->base.connector_type;
12060                 int clamp_bpp = 24;
12061
12062                 /* Fall back to 18 bpp when DP sink capability is unknown. */
12063                 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12064                     type == DRM_MODE_CONNECTOR_eDP)
12065                         clamp_bpp = 18;
12066
12067                 if (bpp > clamp_bpp) {
12068                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12069                                       bpp, clamp_bpp);
12070                         pipe_config->pipe_bpp = clamp_bpp;
12071                 }
12072         }
12073 }
12074
12075 static int
12076 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12077                           struct intel_crtc_state *pipe_config)
12078 {
12079         struct drm_device *dev = crtc->base.dev;
12080         struct drm_atomic_state *state;
12081         struct drm_connector *connector;
12082         struct drm_connector_state *connector_state;
12083         int bpp, i;
12084
12085         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12086                 bpp = 10*3;
12087         else if (INTEL_INFO(dev)->gen >= 5)
12088                 bpp = 12*3;
12089         else
12090                 bpp = 8*3;
12091
12092
12093         pipe_config->pipe_bpp = bpp;
12094
12095         state = pipe_config->base.state;
12096
12097         /* Clamp display bpp to EDID value */
12098         for_each_connector_in_state(state, connector, connector_state, i) {
12099                 if (connector_state->crtc != &crtc->base)
12100                         continue;
12101
12102                 connected_sink_compute_bpp(to_intel_connector(connector),
12103                                            pipe_config);
12104         }
12105
12106         return bpp;
12107 }
12108
12109 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12110 {
12111         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12112                         "type: 0x%x flags: 0x%x\n",
12113                 mode->crtc_clock,
12114                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12115                 mode->crtc_hsync_end, mode->crtc_htotal,
12116                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12117                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12118 }
12119
12120 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12121                                    struct intel_crtc_state *pipe_config,
12122                                    const char *context)
12123 {
12124         struct drm_device *dev = crtc->base.dev;
12125         struct drm_plane *plane;
12126         struct intel_plane *intel_plane;
12127         struct intel_plane_state *state;
12128         struct drm_framebuffer *fb;
12129
12130         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12131                       context, pipe_config, pipe_name(crtc->pipe));
12132
12133         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12134         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12135                       pipe_config->pipe_bpp, pipe_config->dither);
12136         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12137                       pipe_config->has_pch_encoder,
12138                       pipe_config->fdi_lanes,
12139                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12140                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12141                       pipe_config->fdi_m_n.tu);
12142         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12143                       pipe_config->has_dp_encoder,
12144                       pipe_config->lane_count,
12145                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12146                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12147                       pipe_config->dp_m_n.tu);
12148
12149         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12150                       pipe_config->has_dp_encoder,
12151                       pipe_config->lane_count,
12152                       pipe_config->dp_m2_n2.gmch_m,
12153                       pipe_config->dp_m2_n2.gmch_n,
12154                       pipe_config->dp_m2_n2.link_m,
12155                       pipe_config->dp_m2_n2.link_n,
12156                       pipe_config->dp_m2_n2.tu);
12157
12158         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12159                       pipe_config->has_audio,
12160                       pipe_config->has_infoframe);
12161
12162         DRM_DEBUG_KMS("requested mode:\n");
12163         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12164         DRM_DEBUG_KMS("adjusted mode:\n");
12165         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12166         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12167         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12168         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12169                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12170         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12171                       crtc->num_scalers,
12172                       pipe_config->scaler_state.scaler_users,
12173                       pipe_config->scaler_state.scaler_id);
12174         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12175                       pipe_config->gmch_pfit.control,
12176                       pipe_config->gmch_pfit.pgm_ratios,
12177                       pipe_config->gmch_pfit.lvds_border_bits);
12178         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12179                       pipe_config->pch_pfit.pos,
12180                       pipe_config->pch_pfit.size,
12181                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12182         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12183         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12184
12185         if (IS_BROXTON(dev)) {
12186                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12187                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12188                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12189                               pipe_config->ddi_pll_sel,
12190                               pipe_config->dpll_hw_state.ebb0,
12191                               pipe_config->dpll_hw_state.ebb4,
12192                               pipe_config->dpll_hw_state.pll0,
12193                               pipe_config->dpll_hw_state.pll1,
12194                               pipe_config->dpll_hw_state.pll2,
12195                               pipe_config->dpll_hw_state.pll3,
12196                               pipe_config->dpll_hw_state.pll6,
12197                               pipe_config->dpll_hw_state.pll8,
12198                               pipe_config->dpll_hw_state.pll9,
12199                               pipe_config->dpll_hw_state.pll10,
12200                               pipe_config->dpll_hw_state.pcsdw12);
12201         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12202                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12203                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12204                               pipe_config->ddi_pll_sel,
12205                               pipe_config->dpll_hw_state.ctrl1,
12206                               pipe_config->dpll_hw_state.cfgcr1,
12207                               pipe_config->dpll_hw_state.cfgcr2);
12208         } else if (HAS_DDI(dev)) {
12209                 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12210                               pipe_config->ddi_pll_sel,
12211                               pipe_config->dpll_hw_state.wrpll,
12212                               pipe_config->dpll_hw_state.spll);
12213         } else {
12214                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12215                               "fp0: 0x%x, fp1: 0x%x\n",
12216                               pipe_config->dpll_hw_state.dpll,
12217                               pipe_config->dpll_hw_state.dpll_md,
12218                               pipe_config->dpll_hw_state.fp0,
12219                               pipe_config->dpll_hw_state.fp1);
12220         }
12221
12222         DRM_DEBUG_KMS("planes on this crtc\n");
12223         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12224                 intel_plane = to_intel_plane(plane);
12225                 if (intel_plane->pipe != crtc->pipe)
12226                         continue;
12227
12228                 state = to_intel_plane_state(plane->state);
12229                 fb = state->base.fb;
12230                 if (!fb) {
12231                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12232                                 "disabled, scaler_id = %d\n",
12233                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12234                                 plane->base.id, intel_plane->pipe,
12235                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12236                                 drm_plane_index(plane), state->scaler_id);
12237                         continue;
12238                 }
12239
12240                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12241                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12242                         plane->base.id, intel_plane->pipe,
12243                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12244                         drm_plane_index(plane));
12245                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12246                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12247                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12248                         state->scaler_id,
12249                         state->src.x1 >> 16, state->src.y1 >> 16,
12250                         drm_rect_width(&state->src) >> 16,
12251                         drm_rect_height(&state->src) >> 16,
12252                         state->dst.x1, state->dst.y1,
12253                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12254         }
12255 }
12256
12257 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12258 {
12259         struct drm_device *dev = state->dev;
12260         struct drm_connector *connector;
12261         unsigned int used_ports = 0;
12262
12263         /*
12264          * Walk the connector list instead of the encoder
12265          * list to detect the problem on ddi platforms
12266          * where there's just one encoder per digital port.
12267          */
12268         drm_for_each_connector(connector, dev) {
12269                 struct drm_connector_state *connector_state;
12270                 struct intel_encoder *encoder;
12271
12272                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12273                 if (!connector_state)
12274                         connector_state = connector->state;
12275
12276                 if (!connector_state->best_encoder)
12277                         continue;
12278
12279                 encoder = to_intel_encoder(connector_state->best_encoder);
12280
12281                 WARN_ON(!connector_state->crtc);
12282
12283                 switch (encoder->type) {
12284                         unsigned int port_mask;
12285                 case INTEL_OUTPUT_UNKNOWN:
12286                         if (WARN_ON(!HAS_DDI(dev)))
12287                                 break;
12288                 case INTEL_OUTPUT_DISPLAYPORT:
12289                 case INTEL_OUTPUT_HDMI:
12290                 case INTEL_OUTPUT_EDP:
12291                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12292
12293                         /* the same port mustn't appear more than once */
12294                         if (used_ports & port_mask)
12295                                 return false;
12296
12297                         used_ports |= port_mask;
12298                 default:
12299                         break;
12300                 }
12301         }
12302
12303         return true;
12304 }
12305
12306 static void
12307 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12308 {
12309         struct drm_crtc_state tmp_state;
12310         struct intel_crtc_scaler_state scaler_state;
12311         struct intel_dpll_hw_state dpll_hw_state;
12312         struct intel_shared_dpll *shared_dpll;
12313         uint32_t ddi_pll_sel;
12314         bool force_thru;
12315
12316         /* FIXME: before the switch to atomic started, a new pipe_config was
12317          * kzalloc'd. Code that depends on any field being zero should be
12318          * fixed, so that the crtc_state can be safely duplicated. For now,
12319          * only fields that are know to not cause problems are preserved. */
12320
12321         tmp_state = crtc_state->base;
12322         scaler_state = crtc_state->scaler_state;
12323         shared_dpll = crtc_state->shared_dpll;
12324         dpll_hw_state = crtc_state->dpll_hw_state;
12325         ddi_pll_sel = crtc_state->ddi_pll_sel;
12326         force_thru = crtc_state->pch_pfit.force_thru;
12327
12328         memset(crtc_state, 0, sizeof *crtc_state);
12329
12330         crtc_state->base = tmp_state;
12331         crtc_state->scaler_state = scaler_state;
12332         crtc_state->shared_dpll = shared_dpll;
12333         crtc_state->dpll_hw_state = dpll_hw_state;
12334         crtc_state->ddi_pll_sel = ddi_pll_sel;
12335         crtc_state->pch_pfit.force_thru = force_thru;
12336 }
12337
12338 static int
12339 intel_modeset_pipe_config(struct drm_crtc *crtc,
12340                           struct intel_crtc_state *pipe_config)
12341 {
12342         struct drm_atomic_state *state = pipe_config->base.state;
12343         struct intel_encoder *encoder;
12344         struct drm_connector *connector;
12345         struct drm_connector_state *connector_state;
12346         int base_bpp, ret = -EINVAL;
12347         int i;
12348         bool retry = true;
12349
12350         clear_intel_crtc_state(pipe_config);
12351
12352         pipe_config->cpu_transcoder =
12353                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12354
12355         /*
12356          * Sanitize sync polarity flags based on requested ones. If neither
12357          * positive or negative polarity is requested, treat this as meaning
12358          * negative polarity.
12359          */
12360         if (!(pipe_config->base.adjusted_mode.flags &
12361               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12362                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12363
12364         if (!(pipe_config->base.adjusted_mode.flags &
12365               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12366                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12367
12368         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12369                                              pipe_config);
12370         if (base_bpp < 0)
12371                 goto fail;
12372
12373         /*
12374          * Determine the real pipe dimensions. Note that stereo modes can
12375          * increase the actual pipe size due to the frame doubling and
12376          * insertion of additional space for blanks between the frame. This
12377          * is stored in the crtc timings. We use the requested mode to do this
12378          * computation to clearly distinguish it from the adjusted mode, which
12379          * can be changed by the connectors in the below retry loop.
12380          */
12381         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12382                                &pipe_config->pipe_src_w,
12383                                &pipe_config->pipe_src_h);
12384
12385 encoder_retry:
12386         /* Ensure the port clock defaults are reset when retrying. */
12387         pipe_config->port_clock = 0;
12388         pipe_config->pixel_multiplier = 1;
12389
12390         /* Fill in default crtc timings, allow encoders to overwrite them. */
12391         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12392                               CRTC_STEREO_DOUBLE);
12393
12394         /* Pass our mode to the connectors and the CRTC to give them a chance to
12395          * adjust it according to limitations or connector properties, and also
12396          * a chance to reject the mode entirely.
12397          */
12398         for_each_connector_in_state(state, connector, connector_state, i) {
12399                 if (connector_state->crtc != crtc)
12400                         continue;
12401
12402                 encoder = to_intel_encoder(connector_state->best_encoder);
12403
12404                 if (!(encoder->compute_config(encoder, pipe_config))) {
12405                         DRM_DEBUG_KMS("Encoder config failure\n");
12406                         goto fail;
12407                 }
12408         }
12409
12410         /* Set default port clock if not overwritten by the encoder. Needs to be
12411          * done afterwards in case the encoder adjusts the mode. */
12412         if (!pipe_config->port_clock)
12413                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12414                         * pipe_config->pixel_multiplier;
12415
12416         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12417         if (ret < 0) {
12418                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12419                 goto fail;
12420         }
12421
12422         if (ret == RETRY) {
12423                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12424                         ret = -EINVAL;
12425                         goto fail;
12426                 }
12427
12428                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12429                 retry = false;
12430                 goto encoder_retry;
12431         }
12432
12433         /* Dithering seems to not pass-through bits correctly when it should, so
12434          * only enable it on 6bpc panels. */
12435         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12436         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12437                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12438
12439 fail:
12440         return ret;
12441 }
12442
12443 static void
12444 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12445 {
12446         struct drm_crtc *crtc;
12447         struct drm_crtc_state *crtc_state;
12448         int i;
12449
12450         /* Double check state. */
12451         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12452                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12453
12454                 /* Update hwmode for vblank functions */
12455                 if (crtc->state->active)
12456                         crtc->hwmode = crtc->state->adjusted_mode;
12457                 else
12458                         crtc->hwmode.crtc_clock = 0;
12459
12460                 /*
12461                  * Update legacy state to satisfy fbc code. This can
12462                  * be removed when fbc uses the atomic state.
12463                  */
12464                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12465                         struct drm_plane_state *plane_state = crtc->primary->state;
12466
12467                         crtc->primary->fb = plane_state->fb;
12468                         crtc->x = plane_state->src_x >> 16;
12469                         crtc->y = plane_state->src_y >> 16;
12470                 }
12471         }
12472 }
12473
12474 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12475 {
12476         int diff;
12477
12478         if (clock1 == clock2)
12479                 return true;
12480
12481         if (!clock1 || !clock2)
12482                 return false;
12483
12484         diff = abs(clock1 - clock2);
12485
12486         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12487                 return true;
12488
12489         return false;
12490 }
12491
12492 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12493         list_for_each_entry((intel_crtc), \
12494                             &(dev)->mode_config.crtc_list, \
12495                             base.head) \
12496                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12497
12498 static bool
12499 intel_compare_m_n(unsigned int m, unsigned int n,
12500                   unsigned int m2, unsigned int n2,
12501                   bool exact)
12502 {
12503         if (m == m2 && n == n2)
12504                 return true;
12505
12506         if (exact || !m || !n || !m2 || !n2)
12507                 return false;
12508
12509         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12510
12511         if (n > n2) {
12512                 while (n > n2) {
12513                         m2 <<= 1;
12514                         n2 <<= 1;
12515                 }
12516         } else if (n < n2) {
12517                 while (n < n2) {
12518                         m <<= 1;
12519                         n <<= 1;
12520                 }
12521         }
12522
12523         if (n != n2)
12524                 return false;
12525
12526         return intel_fuzzy_clock_check(m, m2);
12527 }
12528
12529 static bool
12530 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12531                        struct intel_link_m_n *m2_n2,
12532                        bool adjust)
12533 {
12534         if (m_n->tu == m2_n2->tu &&
12535             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12536                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12537             intel_compare_m_n(m_n->link_m, m_n->link_n,
12538                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12539                 if (adjust)
12540                         *m2_n2 = *m_n;
12541
12542                 return true;
12543         }
12544
12545         return false;
12546 }
12547
12548 static bool
12549 intel_pipe_config_compare(struct drm_device *dev,
12550                           struct intel_crtc_state *current_config,
12551                           struct intel_crtc_state *pipe_config,
12552                           bool adjust)
12553 {
12554         bool ret = true;
12555
12556 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12557         do { \
12558                 if (!adjust) \
12559                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12560                 else \
12561                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12562         } while (0)
12563
12564 #define PIPE_CONF_CHECK_X(name) \
12565         if (current_config->name != pipe_config->name) { \
12566                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12567                           "(expected 0x%08x, found 0x%08x)\n", \
12568                           current_config->name, \
12569                           pipe_config->name); \
12570                 ret = false; \
12571         }
12572
12573 #define PIPE_CONF_CHECK_I(name) \
12574         if (current_config->name != pipe_config->name) { \
12575                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12576                           "(expected %i, found %i)\n", \
12577                           current_config->name, \
12578                           pipe_config->name); \
12579                 ret = false; \
12580         }
12581
12582 #define PIPE_CONF_CHECK_P(name) \
12583         if (current_config->name != pipe_config->name) { \
12584                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12585                           "(expected %p, found %p)\n", \
12586                           current_config->name, \
12587                           pipe_config->name); \
12588                 ret = false; \
12589         }
12590
12591 #define PIPE_CONF_CHECK_M_N(name) \
12592         if (!intel_compare_link_m_n(&current_config->name, \
12593                                     &pipe_config->name,\
12594                                     adjust)) { \
12595                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12596                           "(expected tu %i gmch %i/%i link %i/%i, " \
12597                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12598                           current_config->name.tu, \
12599                           current_config->name.gmch_m, \
12600                           current_config->name.gmch_n, \
12601                           current_config->name.link_m, \
12602                           current_config->name.link_n, \
12603                           pipe_config->name.tu, \
12604                           pipe_config->name.gmch_m, \
12605                           pipe_config->name.gmch_n, \
12606                           pipe_config->name.link_m, \
12607                           pipe_config->name.link_n); \
12608                 ret = false; \
12609         }
12610
12611 /* This is required for BDW+ where there is only one set of registers for
12612  * switching between high and low RR.
12613  * This macro can be used whenever a comparison has to be made between one
12614  * hw state and multiple sw state variables.
12615  */
12616 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12617         if (!intel_compare_link_m_n(&current_config->name, \
12618                                     &pipe_config->name, adjust) && \
12619             !intel_compare_link_m_n(&current_config->alt_name, \
12620                                     &pipe_config->name, adjust)) { \
12621                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12622                           "(expected tu %i gmch %i/%i link %i/%i, " \
12623                           "or tu %i gmch %i/%i link %i/%i, " \
12624                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12625                           current_config->name.tu, \
12626                           current_config->name.gmch_m, \
12627                           current_config->name.gmch_n, \
12628                           current_config->name.link_m, \
12629                           current_config->name.link_n, \
12630                           current_config->alt_name.tu, \
12631                           current_config->alt_name.gmch_m, \
12632                           current_config->alt_name.gmch_n, \
12633                           current_config->alt_name.link_m, \
12634                           current_config->alt_name.link_n, \
12635                           pipe_config->name.tu, \
12636                           pipe_config->name.gmch_m, \
12637                           pipe_config->name.gmch_n, \
12638                           pipe_config->name.link_m, \
12639                           pipe_config->name.link_n); \
12640                 ret = false; \
12641         }
12642
12643 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12644         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12645                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12646                           "(expected %i, found %i)\n", \
12647                           current_config->name & (mask), \
12648                           pipe_config->name & (mask)); \
12649                 ret = false; \
12650         }
12651
12652 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12653         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12654                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12655                           "(expected %i, found %i)\n", \
12656                           current_config->name, \
12657                           pipe_config->name); \
12658                 ret = false; \
12659         }
12660
12661 #define PIPE_CONF_QUIRK(quirk)  \
12662         ((current_config->quirks | pipe_config->quirks) & (quirk))
12663
12664         PIPE_CONF_CHECK_I(cpu_transcoder);
12665
12666         PIPE_CONF_CHECK_I(has_pch_encoder);
12667         PIPE_CONF_CHECK_I(fdi_lanes);
12668         PIPE_CONF_CHECK_M_N(fdi_m_n);
12669
12670         PIPE_CONF_CHECK_I(has_dp_encoder);
12671         PIPE_CONF_CHECK_I(lane_count);
12672
12673         if (INTEL_INFO(dev)->gen < 8) {
12674                 PIPE_CONF_CHECK_M_N(dp_m_n);
12675
12676                 if (current_config->has_drrs)
12677                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12678         } else
12679                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12680
12681         PIPE_CONF_CHECK_I(has_dsi_encoder);
12682
12683         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12684         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12685         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12686         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12687         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12688         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12689
12690         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12691         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12692         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12693         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12694         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12695         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12696
12697         PIPE_CONF_CHECK_I(pixel_multiplier);
12698         PIPE_CONF_CHECK_I(has_hdmi_sink);
12699         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12700             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12701                 PIPE_CONF_CHECK_I(limited_color_range);
12702         PIPE_CONF_CHECK_I(has_infoframe);
12703
12704         PIPE_CONF_CHECK_I(has_audio);
12705
12706         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12707                               DRM_MODE_FLAG_INTERLACE);
12708
12709         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12710                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12711                                       DRM_MODE_FLAG_PHSYNC);
12712                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12713                                       DRM_MODE_FLAG_NHSYNC);
12714                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12715                                       DRM_MODE_FLAG_PVSYNC);
12716                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12717                                       DRM_MODE_FLAG_NVSYNC);
12718         }
12719
12720         PIPE_CONF_CHECK_X(gmch_pfit.control);
12721         /* pfit ratios are autocomputed by the hw on gen4+ */
12722         if (INTEL_INFO(dev)->gen < 4)
12723                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12724         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12725
12726         if (!adjust) {
12727                 PIPE_CONF_CHECK_I(pipe_src_w);
12728                 PIPE_CONF_CHECK_I(pipe_src_h);
12729
12730                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12731                 if (current_config->pch_pfit.enabled) {
12732                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12733                         PIPE_CONF_CHECK_X(pch_pfit.size);
12734                 }
12735
12736                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12737         }
12738
12739         /* BDW+ don't expose a synchronous way to read the state */
12740         if (IS_HASWELL(dev))
12741                 PIPE_CONF_CHECK_I(ips_enabled);
12742
12743         PIPE_CONF_CHECK_I(double_wide);
12744
12745         PIPE_CONF_CHECK_X(ddi_pll_sel);
12746
12747         PIPE_CONF_CHECK_P(shared_dpll);
12748         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12749         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12750         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12751         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12752         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12753         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12754         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12755         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12756         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12757
12758         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12759         PIPE_CONF_CHECK_X(dsi_pll.div);
12760
12761         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12762                 PIPE_CONF_CHECK_I(pipe_bpp);
12763
12764         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12765         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12766
12767 #undef PIPE_CONF_CHECK_X
12768 #undef PIPE_CONF_CHECK_I
12769 #undef PIPE_CONF_CHECK_P
12770 #undef PIPE_CONF_CHECK_FLAGS
12771 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12772 #undef PIPE_CONF_QUIRK
12773 #undef INTEL_ERR_OR_DBG_KMS
12774
12775         return ret;
12776 }
12777
12778 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12779                                            const struct intel_crtc_state *pipe_config)
12780 {
12781         if (pipe_config->has_pch_encoder) {
12782                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12783                                                             &pipe_config->fdi_m_n);
12784                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12785
12786                 /*
12787                  * FDI already provided one idea for the dotclock.
12788                  * Yell if the encoder disagrees.
12789                  */
12790                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12791                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12792                      fdi_dotclock, dotclock);
12793         }
12794 }
12795
12796 static void verify_wm_state(struct drm_crtc *crtc,
12797                             struct drm_crtc_state *new_state)
12798 {
12799         struct drm_device *dev = crtc->dev;
12800         struct drm_i915_private *dev_priv = dev->dev_private;
12801         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12802         struct skl_ddb_entry *hw_entry, *sw_entry;
12803         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12804         const enum pipe pipe = intel_crtc->pipe;
12805         int plane;
12806
12807         if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12808                 return;
12809
12810         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12811         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12812
12813         /* planes */
12814         for_each_plane(dev_priv, pipe, plane) {
12815                 hw_entry = &hw_ddb.plane[pipe][plane];
12816                 sw_entry = &sw_ddb->plane[pipe][plane];
12817
12818                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12819                         continue;
12820
12821                 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12822                           "(expected (%u,%u), found (%u,%u))\n",
12823                           pipe_name(pipe), plane + 1,
12824                           sw_entry->start, sw_entry->end,
12825                           hw_entry->start, hw_entry->end);
12826         }
12827
12828         /* cursor */
12829         hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12830         sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12831
12832         if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12833                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12834                           "(expected (%u,%u), found (%u,%u))\n",
12835                           pipe_name(pipe),
12836                           sw_entry->start, sw_entry->end,
12837                           hw_entry->start, hw_entry->end);
12838         }
12839 }
12840
12841 static void
12842 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12843 {
12844         struct drm_connector *connector;
12845
12846         drm_for_each_connector(connector, dev) {
12847                 struct drm_encoder *encoder = connector->encoder;
12848                 struct drm_connector_state *state = connector->state;
12849
12850                 if (state->crtc != crtc)
12851                         continue;
12852
12853                 intel_connector_verify_state(to_intel_connector(connector));
12854
12855                 I915_STATE_WARN(state->best_encoder != encoder,
12856                      "connector's atomic encoder doesn't match legacy encoder\n");
12857         }
12858 }
12859
12860 static void
12861 verify_encoder_state(struct drm_device *dev)
12862 {
12863         struct intel_encoder *encoder;
12864         struct intel_connector *connector;
12865
12866         for_each_intel_encoder(dev, encoder) {
12867                 bool enabled = false;
12868                 enum pipe pipe;
12869
12870                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12871                               encoder->base.base.id,
12872                               encoder->base.name);
12873
12874                 for_each_intel_connector(dev, connector) {
12875                         if (connector->base.state->best_encoder != &encoder->base)
12876                                 continue;
12877                         enabled = true;
12878
12879                         I915_STATE_WARN(connector->base.state->crtc !=
12880                                         encoder->base.crtc,
12881                              "connector's crtc doesn't match encoder crtc\n");
12882                 }
12883
12884                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12885                      "encoder's enabled state mismatch "
12886                      "(expected %i, found %i)\n",
12887                      !!encoder->base.crtc, enabled);
12888
12889                 if (!encoder->base.crtc) {
12890                         bool active;
12891
12892                         active = encoder->get_hw_state(encoder, &pipe);
12893                         I915_STATE_WARN(active,
12894                              "encoder detached but still enabled on pipe %c.\n",
12895                              pipe_name(pipe));
12896                 }
12897         }
12898 }
12899
12900 static void
12901 verify_crtc_state(struct drm_crtc *crtc,
12902                   struct drm_crtc_state *old_crtc_state,
12903                   struct drm_crtc_state *new_crtc_state)
12904 {
12905         struct drm_device *dev = crtc->dev;
12906         struct drm_i915_private *dev_priv = dev->dev_private;
12907         struct intel_encoder *encoder;
12908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12909         struct intel_crtc_state *pipe_config, *sw_config;
12910         struct drm_atomic_state *old_state;
12911         bool active;
12912
12913         old_state = old_crtc_state->state;
12914         __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12915         pipe_config = to_intel_crtc_state(old_crtc_state);
12916         memset(pipe_config, 0, sizeof(*pipe_config));
12917         pipe_config->base.crtc = crtc;
12918         pipe_config->base.state = old_state;
12919
12920         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
12921
12922         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12923
12924         /* hw state is inconsistent with the pipe quirk */
12925         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12926             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12927                 active = new_crtc_state->active;
12928
12929         I915_STATE_WARN(new_crtc_state->active != active,
12930              "crtc active state doesn't match with hw state "
12931              "(expected %i, found %i)\n", new_crtc_state->active, active);
12932
12933         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12934              "transitional active state does not match atomic hw state "
12935              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12936
12937         for_each_encoder_on_crtc(dev, crtc, encoder) {
12938                 enum pipe pipe;
12939
12940                 active = encoder->get_hw_state(encoder, &pipe);
12941                 I915_STATE_WARN(active != new_crtc_state->active,
12942                         "[ENCODER:%i] active %i with crtc active %i\n",
12943                         encoder->base.base.id, active, new_crtc_state->active);
12944
12945                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12946                                 "Encoder connected to wrong pipe %c\n",
12947                                 pipe_name(pipe));
12948
12949                 if (active)
12950                         encoder->get_config(encoder, pipe_config);
12951         }
12952
12953         if (!new_crtc_state->active)
12954                 return;
12955
12956         intel_pipe_config_sanity_check(dev_priv, pipe_config);
12957
12958         sw_config = to_intel_crtc_state(crtc->state);
12959         if (!intel_pipe_config_compare(dev, sw_config,
12960                                        pipe_config, false)) {
12961                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12962                 intel_dump_pipe_config(intel_crtc, pipe_config,
12963                                        "[hw state]");
12964                 intel_dump_pipe_config(intel_crtc, sw_config,
12965                                        "[sw state]");
12966         }
12967 }
12968
12969 static void
12970 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12971                          struct intel_shared_dpll *pll,
12972                          struct drm_crtc *crtc,
12973                          struct drm_crtc_state *new_state)
12974 {
12975         struct intel_dpll_hw_state dpll_hw_state;
12976         unsigned crtc_mask;
12977         bool active;
12978
12979         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12980
12981         DRM_DEBUG_KMS("%s\n", pll->name);
12982
12983         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12984
12985         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12986                 I915_STATE_WARN(!pll->on && pll->active_mask,
12987                      "pll in active use but not on in sw tracking\n");
12988                 I915_STATE_WARN(pll->on && !pll->active_mask,
12989                      "pll is on but not used by any active crtc\n");
12990                 I915_STATE_WARN(pll->on != active,
12991                      "pll on state mismatch (expected %i, found %i)\n",
12992                      pll->on, active);
12993         }
12994
12995         if (!crtc) {
12996                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12997                                 "more active pll users than references: %x vs %x\n",
12998                                 pll->active_mask, pll->config.crtc_mask);
12999
13000                 return;
13001         }
13002
13003         crtc_mask = 1 << drm_crtc_index(crtc);
13004
13005         if (new_state->active)
13006                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13007                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13008                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13009         else
13010                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13011                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13012                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13013
13014         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13015                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13016                         crtc_mask, pll->config.crtc_mask);
13017
13018         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13019                                           &dpll_hw_state,
13020                                           sizeof(dpll_hw_state)),
13021                         "pll hw state mismatch\n");
13022 }
13023
13024 static void
13025 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13026                          struct drm_crtc_state *old_crtc_state,
13027                          struct drm_crtc_state *new_crtc_state)
13028 {
13029         struct drm_i915_private *dev_priv = dev->dev_private;
13030         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13031         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13032
13033         if (new_state->shared_dpll)
13034                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13035
13036         if (old_state->shared_dpll &&
13037             old_state->shared_dpll != new_state->shared_dpll) {
13038                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13039                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13040
13041                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13042                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13043                                 pipe_name(drm_crtc_index(crtc)));
13044                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13045                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13046                                 pipe_name(drm_crtc_index(crtc)));
13047         }
13048 }
13049
13050 static void
13051 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13052                          struct drm_crtc_state *old_state,
13053                          struct drm_crtc_state *new_state)
13054 {
13055         if (!needs_modeset(new_state) &&
13056             !to_intel_crtc_state(new_state)->update_pipe)
13057                 return;
13058
13059         verify_wm_state(crtc, new_state);
13060         verify_connector_state(crtc->dev, crtc);
13061         verify_crtc_state(crtc, old_state, new_state);
13062         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13063 }
13064
13065 static void
13066 verify_disabled_dpll_state(struct drm_device *dev)
13067 {
13068         struct drm_i915_private *dev_priv = dev->dev_private;
13069         int i;
13070
13071         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13072                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13073 }
13074
13075 static void
13076 intel_modeset_verify_disabled(struct drm_device *dev)
13077 {
13078         verify_encoder_state(dev);
13079         verify_connector_state(dev, NULL);
13080         verify_disabled_dpll_state(dev);
13081 }
13082
13083 static void update_scanline_offset(struct intel_crtc *crtc)
13084 {
13085         struct drm_device *dev = crtc->base.dev;
13086
13087         /*
13088          * The scanline counter increments at the leading edge of hsync.
13089          *
13090          * On most platforms it starts counting from vtotal-1 on the
13091          * first active line. That means the scanline counter value is
13092          * always one less than what we would expect. Ie. just after
13093          * start of vblank, which also occurs at start of hsync (on the
13094          * last active line), the scanline counter will read vblank_start-1.
13095          *
13096          * On gen2 the scanline counter starts counting from 1 instead
13097          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13098          * to keep the value positive), instead of adding one.
13099          *
13100          * On HSW+ the behaviour of the scanline counter depends on the output
13101          * type. For DP ports it behaves like most other platforms, but on HDMI
13102          * there's an extra 1 line difference. So we need to add two instead of
13103          * one to the value.
13104          */
13105         if (IS_GEN2(dev)) {
13106                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13107                 int vtotal;
13108
13109                 vtotal = adjusted_mode->crtc_vtotal;
13110                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13111                         vtotal /= 2;
13112
13113                 crtc->scanline_offset = vtotal - 1;
13114         } else if (HAS_DDI(dev) &&
13115                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13116                 crtc->scanline_offset = 2;
13117         } else
13118                 crtc->scanline_offset = 1;
13119 }
13120
13121 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13122 {
13123         struct drm_device *dev = state->dev;
13124         struct drm_i915_private *dev_priv = to_i915(dev);
13125         struct intel_shared_dpll_config *shared_dpll = NULL;
13126         struct drm_crtc *crtc;
13127         struct drm_crtc_state *crtc_state;
13128         int i;
13129
13130         if (!dev_priv->display.crtc_compute_clock)
13131                 return;
13132
13133         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13134                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13135                 struct intel_shared_dpll *old_dpll =
13136                         to_intel_crtc_state(crtc->state)->shared_dpll;
13137
13138                 if (!needs_modeset(crtc_state))
13139                         continue;
13140
13141                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13142
13143                 if (!old_dpll)
13144                         continue;
13145
13146                 if (!shared_dpll)
13147                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13148
13149                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13150         }
13151 }
13152
13153 /*
13154  * This implements the workaround described in the "notes" section of the mode
13155  * set sequence documentation. When going from no pipes or single pipe to
13156  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13157  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13158  */
13159 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13160 {
13161         struct drm_crtc_state *crtc_state;
13162         struct intel_crtc *intel_crtc;
13163         struct drm_crtc *crtc;
13164         struct intel_crtc_state *first_crtc_state = NULL;
13165         struct intel_crtc_state *other_crtc_state = NULL;
13166         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13167         int i;
13168
13169         /* look at all crtc's that are going to be enabled in during modeset */
13170         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13171                 intel_crtc = to_intel_crtc(crtc);
13172
13173                 if (!crtc_state->active || !needs_modeset(crtc_state))
13174                         continue;
13175
13176                 if (first_crtc_state) {
13177                         other_crtc_state = to_intel_crtc_state(crtc_state);
13178                         break;
13179                 } else {
13180                         first_crtc_state = to_intel_crtc_state(crtc_state);
13181                         first_pipe = intel_crtc->pipe;
13182                 }
13183         }
13184
13185         /* No workaround needed? */
13186         if (!first_crtc_state)
13187                 return 0;
13188
13189         /* w/a possibly needed, check how many crtc's are already enabled. */
13190         for_each_intel_crtc(state->dev, intel_crtc) {
13191                 struct intel_crtc_state *pipe_config;
13192
13193                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13194                 if (IS_ERR(pipe_config))
13195                         return PTR_ERR(pipe_config);
13196
13197                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13198
13199                 if (!pipe_config->base.active ||
13200                     needs_modeset(&pipe_config->base))
13201                         continue;
13202
13203                 /* 2 or more enabled crtcs means no need for w/a */
13204                 if (enabled_pipe != INVALID_PIPE)
13205                         return 0;
13206
13207                 enabled_pipe = intel_crtc->pipe;
13208         }
13209
13210         if (enabled_pipe != INVALID_PIPE)
13211                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13212         else if (other_crtc_state)
13213                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13214
13215         return 0;
13216 }
13217
13218 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13219 {
13220         struct drm_crtc *crtc;
13221         struct drm_crtc_state *crtc_state;
13222         int ret = 0;
13223
13224         /* add all active pipes to the state */
13225         for_each_crtc(state->dev, crtc) {
13226                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13227                 if (IS_ERR(crtc_state))
13228                         return PTR_ERR(crtc_state);
13229
13230                 if (!crtc_state->active || needs_modeset(crtc_state))
13231                         continue;
13232
13233                 crtc_state->mode_changed = true;
13234
13235                 ret = drm_atomic_add_affected_connectors(state, crtc);
13236                 if (ret)
13237                         break;
13238
13239                 ret = drm_atomic_add_affected_planes(state, crtc);
13240                 if (ret)
13241                         break;
13242         }
13243
13244         return ret;
13245 }
13246
13247 static int intel_modeset_checks(struct drm_atomic_state *state)
13248 {
13249         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13250         struct drm_i915_private *dev_priv = state->dev->dev_private;
13251         struct drm_crtc *crtc;
13252         struct drm_crtc_state *crtc_state;
13253         int ret = 0, i;
13254
13255         if (!check_digital_port_conflicts(state)) {
13256                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13257                 return -EINVAL;
13258         }
13259
13260         intel_state->modeset = true;
13261         intel_state->active_crtcs = dev_priv->active_crtcs;
13262
13263         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13264                 if (crtc_state->active)
13265                         intel_state->active_crtcs |= 1 << i;
13266                 else
13267                         intel_state->active_crtcs &= ~(1 << i);
13268
13269                 if (crtc_state->active != crtc->state->active)
13270                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13271         }
13272
13273         /*
13274          * See if the config requires any additional preparation, e.g.
13275          * to adjust global state with pipes off.  We need to do this
13276          * here so we can get the modeset_pipe updated config for the new
13277          * mode set on this crtc.  For other crtcs we need to use the
13278          * adjusted_mode bits in the crtc directly.
13279          */
13280         if (dev_priv->display.modeset_calc_cdclk) {
13281                 ret = dev_priv->display.modeset_calc_cdclk(state);
13282
13283                 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13284                         ret = intel_modeset_all_pipes(state);
13285
13286                 if (ret < 0)
13287                         return ret;
13288
13289                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13290                               intel_state->cdclk, intel_state->dev_cdclk);
13291         } else
13292                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13293
13294         intel_modeset_clear_plls(state);
13295
13296         if (IS_HASWELL(dev_priv))
13297                 return haswell_mode_set_planes_workaround(state);
13298
13299         return 0;
13300 }
13301
13302 /*
13303  * Handle calculation of various watermark data at the end of the atomic check
13304  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13305  * handlers to ensure that all derived state has been updated.
13306  */
13307 static int calc_watermark_data(struct drm_atomic_state *state)
13308 {
13309         struct drm_device *dev = state->dev;
13310         struct drm_i915_private *dev_priv = to_i915(dev);
13311
13312         /* Is there platform-specific watermark information to calculate? */
13313         if (dev_priv->display.compute_global_watermarks)
13314                 return dev_priv->display.compute_global_watermarks(state);
13315
13316         return 0;
13317 }
13318
13319 /**
13320  * intel_atomic_check - validate state object
13321  * @dev: drm device
13322  * @state: state to validate
13323  */
13324 static int intel_atomic_check(struct drm_device *dev,
13325                               struct drm_atomic_state *state)
13326 {
13327         struct drm_i915_private *dev_priv = to_i915(dev);
13328         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13329         struct drm_crtc *crtc;
13330         struct drm_crtc_state *crtc_state;
13331         int ret, i;
13332         bool any_ms = false;
13333
13334         ret = drm_atomic_helper_check_modeset(dev, state);
13335         if (ret)
13336                 return ret;
13337
13338         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13339                 struct intel_crtc_state *pipe_config =
13340                         to_intel_crtc_state(crtc_state);
13341
13342                 /* Catch I915_MODE_FLAG_INHERITED */
13343                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13344                         crtc_state->mode_changed = true;
13345
13346                 if (!crtc_state->enable) {
13347                         if (needs_modeset(crtc_state))
13348                                 any_ms = true;
13349                         continue;
13350                 }
13351
13352                 if (!needs_modeset(crtc_state))
13353                         continue;
13354
13355                 /* FIXME: For only active_changed we shouldn't need to do any
13356                  * state recomputation at all. */
13357
13358                 ret = drm_atomic_add_affected_connectors(state, crtc);
13359                 if (ret)
13360                         return ret;
13361
13362                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13363                 if (ret) {
13364                         intel_dump_pipe_config(to_intel_crtc(crtc),
13365                                                pipe_config, "[failed]");
13366                         return ret;
13367                 }
13368
13369                 if (i915.fastboot &&
13370                     intel_pipe_config_compare(dev,
13371                                         to_intel_crtc_state(crtc->state),
13372                                         pipe_config, true)) {
13373                         crtc_state->mode_changed = false;
13374                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13375                 }
13376
13377                 if (needs_modeset(crtc_state)) {
13378                         any_ms = true;
13379
13380                         ret = drm_atomic_add_affected_planes(state, crtc);
13381                         if (ret)
13382                                 return ret;
13383                 }
13384
13385                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13386                                        needs_modeset(crtc_state) ?
13387                                        "[modeset]" : "[fastset]");
13388         }
13389
13390         if (any_ms) {
13391                 ret = intel_modeset_checks(state);
13392
13393                 if (ret)
13394                         return ret;
13395         } else
13396                 intel_state->cdclk = dev_priv->cdclk_freq;
13397
13398         ret = drm_atomic_helper_check_planes(dev, state);
13399         if (ret)
13400                 return ret;
13401
13402         intel_fbc_choose_crtc(dev_priv, state);
13403         return calc_watermark_data(state);
13404 }
13405
13406 static int intel_atomic_prepare_commit(struct drm_device *dev,
13407                                        struct drm_atomic_state *state,
13408                                        bool async)
13409 {
13410         struct drm_i915_private *dev_priv = dev->dev_private;
13411         struct drm_plane_state *plane_state;
13412         struct drm_crtc_state *crtc_state;
13413         struct drm_plane *plane;
13414         struct drm_crtc *crtc;
13415         int i, ret;
13416
13417         if (async) {
13418                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13419                 return -EINVAL;
13420         }
13421
13422         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13423                 if (state->legacy_cursor_update)
13424                         continue;
13425
13426                 ret = intel_crtc_wait_for_pending_flips(crtc);
13427                 if (ret)
13428                         return ret;
13429
13430                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13431                         flush_workqueue(dev_priv->wq);
13432         }
13433
13434         ret = mutex_lock_interruptible(&dev->struct_mutex);
13435         if (ret)
13436                 return ret;
13437
13438         ret = drm_atomic_helper_prepare_planes(dev, state);
13439         mutex_unlock(&dev->struct_mutex);
13440
13441         if (!ret && !async) {
13442                 for_each_plane_in_state(state, plane, plane_state, i) {
13443                         struct intel_plane_state *intel_plane_state =
13444                                 to_intel_plane_state(plane_state);
13445
13446                         if (!intel_plane_state->wait_req)
13447                                 continue;
13448
13449                         ret = __i915_wait_request(intel_plane_state->wait_req,
13450                                                   true, NULL, NULL);
13451                         if (ret) {
13452                                 /* Any hang should be swallowed by the wait */
13453                                 WARN_ON(ret == -EIO);
13454                                 mutex_lock(&dev->struct_mutex);
13455                                 drm_atomic_helper_cleanup_planes(dev, state);
13456                                 mutex_unlock(&dev->struct_mutex);
13457                                 break;
13458                         }
13459                 }
13460         }
13461
13462         return ret;
13463 }
13464
13465 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13466                                           struct drm_i915_private *dev_priv,
13467                                           unsigned crtc_mask)
13468 {
13469         unsigned last_vblank_count[I915_MAX_PIPES];
13470         enum pipe pipe;
13471         int ret;
13472
13473         if (!crtc_mask)
13474                 return;
13475
13476         for_each_pipe(dev_priv, pipe) {
13477                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13478
13479                 if (!((1 << pipe) & crtc_mask))
13480                         continue;
13481
13482                 ret = drm_crtc_vblank_get(crtc);
13483                 if (WARN_ON(ret != 0)) {
13484                         crtc_mask &= ~(1 << pipe);
13485                         continue;
13486                 }
13487
13488                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13489         }
13490
13491         for_each_pipe(dev_priv, pipe) {
13492                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13493                 long lret;
13494
13495                 if (!((1 << pipe) & crtc_mask))
13496                         continue;
13497
13498                 lret = wait_event_timeout(dev->vblank[pipe].queue,
13499                                 last_vblank_count[pipe] !=
13500                                         drm_crtc_vblank_count(crtc),
13501                                 msecs_to_jiffies(50));
13502
13503                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13504
13505                 drm_crtc_vblank_put(crtc);
13506         }
13507 }
13508
13509 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13510 {
13511         /* fb updated, need to unpin old fb */
13512         if (crtc_state->fb_changed)
13513                 return true;
13514
13515         /* wm changes, need vblank before final wm's */
13516         if (crtc_state->update_wm_post)
13517                 return true;
13518
13519         /*
13520          * cxsr is re-enabled after vblank.
13521          * This is already handled by crtc_state->update_wm_post,
13522          * but added for clarity.
13523          */
13524         if (crtc_state->disable_cxsr)
13525                 return true;
13526
13527         return false;
13528 }
13529
13530 /**
13531  * intel_atomic_commit - commit validated state object
13532  * @dev: DRM device
13533  * @state: the top-level driver state object
13534  * @async: asynchronous commit
13535  *
13536  * This function commits a top-level state object that has been validated
13537  * with drm_atomic_helper_check().
13538  *
13539  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13540  * we can only handle plane-related operations and do not yet support
13541  * asynchronous commit.
13542  *
13543  * RETURNS
13544  * Zero for success or -errno.
13545  */
13546 static int intel_atomic_commit(struct drm_device *dev,
13547                                struct drm_atomic_state *state,
13548                                bool async)
13549 {
13550         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13551         struct drm_i915_private *dev_priv = dev->dev_private;
13552         struct drm_crtc_state *old_crtc_state;
13553         struct drm_crtc *crtc;
13554         struct intel_crtc_state *intel_cstate;
13555         int ret = 0, i;
13556         bool hw_check = intel_state->modeset;
13557         unsigned long put_domains[I915_MAX_PIPES] = {};
13558         unsigned crtc_vblank_mask = 0;
13559
13560         ret = intel_atomic_prepare_commit(dev, state, async);
13561         if (ret) {
13562                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13563                 return ret;
13564         }
13565
13566         drm_atomic_helper_swap_state(dev, state);
13567         dev_priv->wm.distrust_bios_wm = false;
13568         dev_priv->wm.skl_results = intel_state->wm_results;
13569         intel_shared_dpll_commit(state);
13570
13571         if (intel_state->modeset) {
13572                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13573                        sizeof(intel_state->min_pixclk));
13574                 dev_priv->active_crtcs = intel_state->active_crtcs;
13575                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13576
13577                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13578         }
13579
13580         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13581                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13582
13583                 if (needs_modeset(crtc->state) ||
13584                     to_intel_crtc_state(crtc->state)->update_pipe) {
13585                         hw_check = true;
13586
13587                         put_domains[to_intel_crtc(crtc)->pipe] =
13588                                 modeset_get_crtc_power_domains(crtc,
13589                                         to_intel_crtc_state(crtc->state));
13590                 }
13591
13592                 if (!needs_modeset(crtc->state))
13593                         continue;
13594
13595                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13596
13597                 if (old_crtc_state->active) {
13598                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13599                         dev_priv->display.crtc_disable(crtc);
13600                         intel_crtc->active = false;
13601                         intel_fbc_disable(intel_crtc);
13602                         intel_disable_shared_dpll(intel_crtc);
13603
13604                         /*
13605                          * Underruns don't always raise
13606                          * interrupts, so check manually.
13607                          */
13608                         intel_check_cpu_fifo_underruns(dev_priv);
13609                         intel_check_pch_fifo_underruns(dev_priv);
13610
13611                         if (!crtc->state->active)
13612                                 intel_update_watermarks(crtc);
13613                 }
13614         }
13615
13616         /* Only after disabling all output pipelines that will be changed can we
13617          * update the the output configuration. */
13618         intel_modeset_update_crtc_state(state);
13619
13620         if (intel_state->modeset) {
13621                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13622
13623                 if (dev_priv->display.modeset_commit_cdclk &&
13624                     intel_state->dev_cdclk != dev_priv->cdclk_freq)
13625                         dev_priv->display.modeset_commit_cdclk(state);
13626
13627                 intel_modeset_verify_disabled(dev);
13628         }
13629
13630         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13631         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13632                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13633                 bool modeset = needs_modeset(crtc->state);
13634                 struct intel_crtc_state *pipe_config =
13635                         to_intel_crtc_state(crtc->state);
13636                 bool update_pipe = !modeset && pipe_config->update_pipe;
13637
13638                 if (modeset && crtc->state->active) {
13639                         update_scanline_offset(to_intel_crtc(crtc));
13640                         dev_priv->display.crtc_enable(crtc);
13641                 }
13642
13643                 if (!modeset)
13644                         intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13645
13646                 if (crtc->state->active &&
13647                     drm_atomic_get_existing_plane_state(state, crtc->primary))
13648                         intel_fbc_enable(intel_crtc);
13649
13650                 if (crtc->state->active &&
13651                     (crtc->state->planes_changed || update_pipe))
13652                         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13653
13654                 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13655                         crtc_vblank_mask |= 1 << i;
13656         }
13657
13658         /* FIXME: add subpixel order */
13659
13660         if (!state->legacy_cursor_update)
13661                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13662
13663         /*
13664          * Now that the vblank has passed, we can go ahead and program the
13665          * optimal watermarks on platforms that need two-step watermark
13666          * programming.
13667          *
13668          * TODO: Move this (and other cleanup) to an async worker eventually.
13669          */
13670         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13671                 intel_cstate = to_intel_crtc_state(crtc->state);
13672
13673                 if (dev_priv->display.optimize_watermarks)
13674                         dev_priv->display.optimize_watermarks(intel_cstate);
13675         }
13676
13677         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13678                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13679
13680                 if (put_domains[i])
13681                         modeset_put_power_domains(dev_priv, put_domains[i]);
13682
13683                 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13684         }
13685
13686         if (intel_state->modeset)
13687                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13688
13689         mutex_lock(&dev->struct_mutex);
13690         drm_atomic_helper_cleanup_planes(dev, state);
13691         mutex_unlock(&dev->struct_mutex);
13692
13693         drm_atomic_state_free(state);
13694
13695         /* As one of the primary mmio accessors, KMS has a high likelihood
13696          * of triggering bugs in unclaimed access. After we finish
13697          * modesetting, see if an error has been flagged, and if so
13698          * enable debugging for the next modeset - and hope we catch
13699          * the culprit.
13700          *
13701          * XXX note that we assume display power is on at this point.
13702          * This might hold true now but we need to add pm helper to check
13703          * unclaimed only when the hardware is on, as atomic commits
13704          * can happen also when the device is completely off.
13705          */
13706         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13707
13708         return 0;
13709 }
13710
13711 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13712 {
13713         struct drm_device *dev = crtc->dev;
13714         struct drm_atomic_state *state;
13715         struct drm_crtc_state *crtc_state;
13716         int ret;
13717
13718         state = drm_atomic_state_alloc(dev);
13719         if (!state) {
13720                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13721                               crtc->base.id);
13722                 return;
13723         }
13724
13725         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13726
13727 retry:
13728         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13729         ret = PTR_ERR_OR_ZERO(crtc_state);
13730         if (!ret) {
13731                 if (!crtc_state->active)
13732                         goto out;
13733
13734                 crtc_state->mode_changed = true;
13735                 ret = drm_atomic_commit(state);
13736         }
13737
13738         if (ret == -EDEADLK) {
13739                 drm_atomic_state_clear(state);
13740                 drm_modeset_backoff(state->acquire_ctx);
13741                 goto retry;
13742         }
13743
13744         if (ret)
13745 out:
13746                 drm_atomic_state_free(state);
13747 }
13748
13749 #undef for_each_intel_crtc_masked
13750
13751 static const struct drm_crtc_funcs intel_crtc_funcs = {
13752         .gamma_set = drm_atomic_helper_legacy_gamma_set,
13753         .set_config = drm_atomic_helper_set_config,
13754         .set_property = drm_atomic_helper_crtc_set_property,
13755         .destroy = intel_crtc_destroy,
13756         .page_flip = intel_crtc_page_flip,
13757         .atomic_duplicate_state = intel_crtc_duplicate_state,
13758         .atomic_destroy_state = intel_crtc_destroy_state,
13759 };
13760
13761 /**
13762  * intel_prepare_plane_fb - Prepare fb for usage on plane
13763  * @plane: drm plane to prepare for
13764  * @fb: framebuffer to prepare for presentation
13765  *
13766  * Prepares a framebuffer for usage on a display plane.  Generally this
13767  * involves pinning the underlying object and updating the frontbuffer tracking
13768  * bits.  Some older platforms need special physical address handling for
13769  * cursor planes.
13770  *
13771  * Must be called with struct_mutex held.
13772  *
13773  * Returns 0 on success, negative error code on failure.
13774  */
13775 int
13776 intel_prepare_plane_fb(struct drm_plane *plane,
13777                        const struct drm_plane_state *new_state)
13778 {
13779         struct drm_device *dev = plane->dev;
13780         struct drm_framebuffer *fb = new_state->fb;
13781         struct intel_plane *intel_plane = to_intel_plane(plane);
13782         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13783         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13784         int ret = 0;
13785
13786         if (!obj && !old_obj)
13787                 return 0;
13788
13789         if (old_obj) {
13790                 struct drm_crtc_state *crtc_state =
13791                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13792
13793                 /* Big Hammer, we also need to ensure that any pending
13794                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13795                  * current scanout is retired before unpinning the old
13796                  * framebuffer. Note that we rely on userspace rendering
13797                  * into the buffer attached to the pipe they are waiting
13798                  * on. If not, userspace generates a GPU hang with IPEHR
13799                  * point to the MI_WAIT_FOR_EVENT.
13800                  *
13801                  * This should only fail upon a hung GPU, in which case we
13802                  * can safely continue.
13803                  */
13804                 if (needs_modeset(crtc_state))
13805                         ret = i915_gem_object_wait_rendering(old_obj, true);
13806                 if (ret) {
13807                         /* GPU hangs should have been swallowed by the wait */
13808                         WARN_ON(ret == -EIO);
13809                         return ret;
13810                 }
13811         }
13812
13813         /* For framebuffer backed by dmabuf, wait for fence */
13814         if (obj && obj->base.dma_buf) {
13815                 long lret;
13816
13817                 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13818                                                            false, true,
13819                                                            MAX_SCHEDULE_TIMEOUT);
13820                 if (lret == -ERESTARTSYS)
13821                         return lret;
13822
13823                 WARN(lret < 0, "waiting returns %li\n", lret);
13824         }
13825
13826         if (!obj) {
13827                 ret = 0;
13828         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13829             INTEL_INFO(dev)->cursor_needs_physical) {
13830                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13831                 ret = i915_gem_object_attach_phys(obj, align);
13832                 if (ret)
13833                         DRM_DEBUG_KMS("failed to attach phys object\n");
13834         } else {
13835                 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13836         }
13837
13838         if (ret == 0) {
13839                 if (obj) {
13840                         struct intel_plane_state *plane_state =
13841                                 to_intel_plane_state(new_state);
13842
13843                         i915_gem_request_assign(&plane_state->wait_req,
13844                                                 obj->last_write_req);
13845                 }
13846
13847                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13848         }
13849
13850         return ret;
13851 }
13852
13853 /**
13854  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13855  * @plane: drm plane to clean up for
13856  * @fb: old framebuffer that was on plane
13857  *
13858  * Cleans up a framebuffer that has just been removed from a plane.
13859  *
13860  * Must be called with struct_mutex held.
13861  */
13862 void
13863 intel_cleanup_plane_fb(struct drm_plane *plane,
13864                        const struct drm_plane_state *old_state)
13865 {
13866         struct drm_device *dev = plane->dev;
13867         struct intel_plane *intel_plane = to_intel_plane(plane);
13868         struct intel_plane_state *old_intel_state;
13869         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13870         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13871
13872         old_intel_state = to_intel_plane_state(old_state);
13873
13874         if (!obj && !old_obj)
13875                 return;
13876
13877         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13878             !INTEL_INFO(dev)->cursor_needs_physical))
13879                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13880
13881         /* prepare_fb aborted? */
13882         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13883             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13884                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13885
13886         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13887 }
13888
13889 int
13890 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13891 {
13892         int max_scale;
13893         struct drm_device *dev;
13894         struct drm_i915_private *dev_priv;
13895         int crtc_clock, cdclk;
13896
13897         if (!intel_crtc || !crtc_state->base.enable)
13898                 return DRM_PLANE_HELPER_NO_SCALING;
13899
13900         dev = intel_crtc->base.dev;
13901         dev_priv = dev->dev_private;
13902         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13903         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13904
13905         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13906                 return DRM_PLANE_HELPER_NO_SCALING;
13907
13908         /*
13909          * skl max scale is lower of:
13910          *    close to 3 but not 3, -1 is for that purpose
13911          *            or
13912          *    cdclk/crtc_clock
13913          */
13914         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13915
13916         return max_scale;
13917 }
13918
13919 static int
13920 intel_check_primary_plane(struct drm_plane *plane,
13921                           struct intel_crtc_state *crtc_state,
13922                           struct intel_plane_state *state)
13923 {
13924         struct drm_crtc *crtc = state->base.crtc;
13925         struct drm_framebuffer *fb = state->base.fb;
13926         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13927         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13928         bool can_position = false;
13929
13930         if (INTEL_INFO(plane->dev)->gen >= 9) {
13931                 /* use scaler when colorkey is not required */
13932                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13933                         min_scale = 1;
13934                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13935                 }
13936                 can_position = true;
13937         }
13938
13939         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13940                                              &state->dst, &state->clip,
13941                                              min_scale, max_scale,
13942                                              can_position, true,
13943                                              &state->visible);
13944 }
13945
13946 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13947                                     struct drm_crtc_state *old_crtc_state)
13948 {
13949         struct drm_device *dev = crtc->dev;
13950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13951         struct intel_crtc_state *old_intel_state =
13952                 to_intel_crtc_state(old_crtc_state);
13953         bool modeset = needs_modeset(crtc->state);
13954
13955         /* Perform vblank evasion around commit operation */
13956         intel_pipe_update_start(intel_crtc);
13957
13958         if (modeset)
13959                 return;
13960
13961         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
13962                 intel_color_set_csc(crtc->state);
13963                 intel_color_load_luts(crtc->state);
13964         }
13965
13966         if (to_intel_crtc_state(crtc->state)->update_pipe)
13967                 intel_update_pipe_config(intel_crtc, old_intel_state);
13968         else if (INTEL_INFO(dev)->gen >= 9)
13969                 skl_detach_scalers(intel_crtc);
13970 }
13971
13972 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13973                                      struct drm_crtc_state *old_crtc_state)
13974 {
13975         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13976
13977         intel_pipe_update_end(intel_crtc);
13978 }
13979
13980 /**
13981  * intel_plane_destroy - destroy a plane
13982  * @plane: plane to destroy
13983  *
13984  * Common destruction function for all types of planes (primary, cursor,
13985  * sprite).
13986  */
13987 void intel_plane_destroy(struct drm_plane *plane)
13988 {
13989         struct intel_plane *intel_plane = to_intel_plane(plane);
13990         drm_plane_cleanup(plane);
13991         kfree(intel_plane);
13992 }
13993
13994 const struct drm_plane_funcs intel_plane_funcs = {
13995         .update_plane = drm_atomic_helper_update_plane,
13996         .disable_plane = drm_atomic_helper_disable_plane,
13997         .destroy = intel_plane_destroy,
13998         .set_property = drm_atomic_helper_plane_set_property,
13999         .atomic_get_property = intel_plane_atomic_get_property,
14000         .atomic_set_property = intel_plane_atomic_set_property,
14001         .atomic_duplicate_state = intel_plane_duplicate_state,
14002         .atomic_destroy_state = intel_plane_destroy_state,
14003
14004 };
14005
14006 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14007                                                     int pipe)
14008 {
14009         struct intel_plane *primary = NULL;
14010         struct intel_plane_state *state = NULL;
14011         const uint32_t *intel_primary_formats;
14012         unsigned int num_formats;
14013         int ret;
14014
14015         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14016         if (!primary)
14017                 goto fail;
14018
14019         state = intel_create_plane_state(&primary->base);
14020         if (!state)
14021                 goto fail;
14022         primary->base.state = &state->base;
14023
14024         primary->can_scale = false;
14025         primary->max_downscale = 1;
14026         if (INTEL_INFO(dev)->gen >= 9) {
14027                 primary->can_scale = true;
14028                 state->scaler_id = -1;
14029         }
14030         primary->pipe = pipe;
14031         primary->plane = pipe;
14032         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14033         primary->check_plane = intel_check_primary_plane;
14034         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14035                 primary->plane = !pipe;
14036
14037         if (INTEL_INFO(dev)->gen >= 9) {
14038                 intel_primary_formats = skl_primary_formats;
14039                 num_formats = ARRAY_SIZE(skl_primary_formats);
14040
14041                 primary->update_plane = skylake_update_primary_plane;
14042                 primary->disable_plane = skylake_disable_primary_plane;
14043         } else if (HAS_PCH_SPLIT(dev)) {
14044                 intel_primary_formats = i965_primary_formats;
14045                 num_formats = ARRAY_SIZE(i965_primary_formats);
14046
14047                 primary->update_plane = ironlake_update_primary_plane;
14048                 primary->disable_plane = i9xx_disable_primary_plane;
14049         } else if (INTEL_INFO(dev)->gen >= 4) {
14050                 intel_primary_formats = i965_primary_formats;
14051                 num_formats = ARRAY_SIZE(i965_primary_formats);
14052
14053                 primary->update_plane = i9xx_update_primary_plane;
14054                 primary->disable_plane = i9xx_disable_primary_plane;
14055         } else {
14056                 intel_primary_formats = i8xx_primary_formats;
14057                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14058
14059                 primary->update_plane = i9xx_update_primary_plane;
14060                 primary->disable_plane = i9xx_disable_primary_plane;
14061         }
14062
14063         ret = drm_universal_plane_init(dev, &primary->base, 0,
14064                                        &intel_plane_funcs,
14065                                        intel_primary_formats, num_formats,
14066                                        DRM_PLANE_TYPE_PRIMARY, NULL);
14067         if (ret)
14068                 goto fail;
14069
14070         if (INTEL_INFO(dev)->gen >= 4)
14071                 intel_create_rotation_property(dev, primary);
14072
14073         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14074
14075         return &primary->base;
14076
14077 fail:
14078         kfree(state);
14079         kfree(primary);
14080
14081         return NULL;
14082 }
14083
14084 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14085 {
14086         if (!dev->mode_config.rotation_property) {
14087                 unsigned long flags = BIT(DRM_ROTATE_0) |
14088                         BIT(DRM_ROTATE_180);
14089
14090                 if (INTEL_INFO(dev)->gen >= 9)
14091                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14092
14093                 dev->mode_config.rotation_property =
14094                         drm_mode_create_rotation_property(dev, flags);
14095         }
14096         if (dev->mode_config.rotation_property)
14097                 drm_object_attach_property(&plane->base.base,
14098                                 dev->mode_config.rotation_property,
14099                                 plane->base.state->rotation);
14100 }
14101
14102 static int
14103 intel_check_cursor_plane(struct drm_plane *plane,
14104                          struct intel_crtc_state *crtc_state,
14105                          struct intel_plane_state *state)
14106 {
14107         struct drm_crtc *crtc = crtc_state->base.crtc;
14108         struct drm_framebuffer *fb = state->base.fb;
14109         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14110         enum pipe pipe = to_intel_plane(plane)->pipe;
14111         unsigned stride;
14112         int ret;
14113
14114         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14115                                             &state->dst, &state->clip,
14116                                             DRM_PLANE_HELPER_NO_SCALING,
14117                                             DRM_PLANE_HELPER_NO_SCALING,
14118                                             true, true, &state->visible);
14119         if (ret)
14120                 return ret;
14121
14122         /* if we want to turn off the cursor ignore width and height */
14123         if (!obj)
14124                 return 0;
14125
14126         /* Check for which cursor types we support */
14127         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14128                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14129                           state->base.crtc_w, state->base.crtc_h);
14130                 return -EINVAL;
14131         }
14132
14133         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14134         if (obj->base.size < stride * state->base.crtc_h) {
14135                 DRM_DEBUG_KMS("buffer is too small\n");
14136                 return -ENOMEM;
14137         }
14138
14139         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14140                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14141                 return -EINVAL;
14142         }
14143
14144         /*
14145          * There's something wrong with the cursor on CHV pipe C.
14146          * If it straddles the left edge of the screen then
14147          * moving it away from the edge or disabling it often
14148          * results in a pipe underrun, and often that can lead to
14149          * dead pipe (constant underrun reported, and it scans
14150          * out just a solid color). To recover from that, the
14151          * display power well must be turned off and on again.
14152          * Refuse the put the cursor into that compromised position.
14153          */
14154         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14155             state->visible && state->base.crtc_x < 0) {
14156                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14157                 return -EINVAL;
14158         }
14159
14160         return 0;
14161 }
14162
14163 static void
14164 intel_disable_cursor_plane(struct drm_plane *plane,
14165                            struct drm_crtc *crtc)
14166 {
14167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14168
14169         intel_crtc->cursor_addr = 0;
14170         intel_crtc_update_cursor(crtc, NULL);
14171 }
14172
14173 static void
14174 intel_update_cursor_plane(struct drm_plane *plane,
14175                           const struct intel_crtc_state *crtc_state,
14176                           const struct intel_plane_state *state)
14177 {
14178         struct drm_crtc *crtc = crtc_state->base.crtc;
14179         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14180         struct drm_device *dev = plane->dev;
14181         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14182         uint32_t addr;
14183
14184         if (!obj)
14185                 addr = 0;
14186         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14187                 addr = i915_gem_obj_ggtt_offset(obj);
14188         else
14189                 addr = obj->phys_handle->busaddr;
14190
14191         intel_crtc->cursor_addr = addr;
14192         intel_crtc_update_cursor(crtc, state);
14193 }
14194
14195 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14196                                                    int pipe)
14197 {
14198         struct intel_plane *cursor = NULL;
14199         struct intel_plane_state *state = NULL;
14200         int ret;
14201
14202         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14203         if (!cursor)
14204                 goto fail;
14205
14206         state = intel_create_plane_state(&cursor->base);
14207         if (!state)
14208                 goto fail;
14209         cursor->base.state = &state->base;
14210
14211         cursor->can_scale = false;
14212         cursor->max_downscale = 1;
14213         cursor->pipe = pipe;
14214         cursor->plane = pipe;
14215         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14216         cursor->check_plane = intel_check_cursor_plane;
14217         cursor->update_plane = intel_update_cursor_plane;
14218         cursor->disable_plane = intel_disable_cursor_plane;
14219
14220         ret = drm_universal_plane_init(dev, &cursor->base, 0,
14221                                        &intel_plane_funcs,
14222                                        intel_cursor_formats,
14223                                        ARRAY_SIZE(intel_cursor_formats),
14224                                        DRM_PLANE_TYPE_CURSOR, NULL);
14225         if (ret)
14226                 goto fail;
14227
14228         if (INTEL_INFO(dev)->gen >= 4) {
14229                 if (!dev->mode_config.rotation_property)
14230                         dev->mode_config.rotation_property =
14231                                 drm_mode_create_rotation_property(dev,
14232                                                         BIT(DRM_ROTATE_0) |
14233                                                         BIT(DRM_ROTATE_180));
14234                 if (dev->mode_config.rotation_property)
14235                         drm_object_attach_property(&cursor->base.base,
14236                                 dev->mode_config.rotation_property,
14237                                 state->base.rotation);
14238         }
14239
14240         if (INTEL_INFO(dev)->gen >=9)
14241                 state->scaler_id = -1;
14242
14243         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14244
14245         return &cursor->base;
14246
14247 fail:
14248         kfree(state);
14249         kfree(cursor);
14250
14251         return NULL;
14252 }
14253
14254 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14255         struct intel_crtc_state *crtc_state)
14256 {
14257         int i;
14258         struct intel_scaler *intel_scaler;
14259         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14260
14261         for (i = 0; i < intel_crtc->num_scalers; i++) {
14262                 intel_scaler = &scaler_state->scalers[i];
14263                 intel_scaler->in_use = 0;
14264                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14265         }
14266
14267         scaler_state->scaler_id = -1;
14268 }
14269
14270 static void intel_crtc_init(struct drm_device *dev, int pipe)
14271 {
14272         struct drm_i915_private *dev_priv = dev->dev_private;
14273         struct intel_crtc *intel_crtc;
14274         struct intel_crtc_state *crtc_state = NULL;
14275         struct drm_plane *primary = NULL;
14276         struct drm_plane *cursor = NULL;
14277         int ret;
14278
14279         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14280         if (intel_crtc == NULL)
14281                 return;
14282
14283         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14284         if (!crtc_state)
14285                 goto fail;
14286         intel_crtc->config = crtc_state;
14287         intel_crtc->base.state = &crtc_state->base;
14288         crtc_state->base.crtc = &intel_crtc->base;
14289
14290         /* initialize shared scalers */
14291         if (INTEL_INFO(dev)->gen >= 9) {
14292                 if (pipe == PIPE_C)
14293                         intel_crtc->num_scalers = 1;
14294                 else
14295                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14296
14297                 skl_init_scalers(dev, intel_crtc, crtc_state);
14298         }
14299
14300         primary = intel_primary_plane_create(dev, pipe);
14301         if (!primary)
14302                 goto fail;
14303
14304         cursor = intel_cursor_plane_create(dev, pipe);
14305         if (!cursor)
14306                 goto fail;
14307
14308         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14309                                         cursor, &intel_crtc_funcs, NULL);
14310         if (ret)
14311                 goto fail;
14312
14313         /*
14314          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14315          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14316          */
14317         intel_crtc->pipe = pipe;
14318         intel_crtc->plane = pipe;
14319         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14320                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14321                 intel_crtc->plane = !pipe;
14322         }
14323
14324         intel_crtc->cursor_base = ~0;
14325         intel_crtc->cursor_cntl = ~0;
14326         intel_crtc->cursor_size = ~0;
14327
14328         intel_crtc->wm.cxsr_allowed = true;
14329
14330         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14331                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14332         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14333         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14334
14335         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14336
14337         intel_color_init(&intel_crtc->base);
14338
14339         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14340         return;
14341
14342 fail:
14343         if (primary)
14344                 drm_plane_cleanup(primary);
14345         if (cursor)
14346                 drm_plane_cleanup(cursor);
14347         kfree(crtc_state);
14348         kfree(intel_crtc);
14349 }
14350
14351 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14352 {
14353         struct drm_encoder *encoder = connector->base.encoder;
14354         struct drm_device *dev = connector->base.dev;
14355
14356         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14357
14358         if (!encoder || WARN_ON(!encoder->crtc))
14359                 return INVALID_PIPE;
14360
14361         return to_intel_crtc(encoder->crtc)->pipe;
14362 }
14363
14364 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14365                                 struct drm_file *file)
14366 {
14367         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14368         struct drm_crtc *drmmode_crtc;
14369         struct intel_crtc *crtc;
14370
14371         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14372
14373         if (!drmmode_crtc) {
14374                 DRM_ERROR("no such CRTC id\n");
14375                 return -ENOENT;
14376         }
14377
14378         crtc = to_intel_crtc(drmmode_crtc);
14379         pipe_from_crtc_id->pipe = crtc->pipe;
14380
14381         return 0;
14382 }
14383
14384 static int intel_encoder_clones(struct intel_encoder *encoder)
14385 {
14386         struct drm_device *dev = encoder->base.dev;
14387         struct intel_encoder *source_encoder;
14388         int index_mask = 0;
14389         int entry = 0;
14390
14391         for_each_intel_encoder(dev, source_encoder) {
14392                 if (encoders_cloneable(encoder, source_encoder))
14393                         index_mask |= (1 << entry);
14394
14395                 entry++;
14396         }
14397
14398         return index_mask;
14399 }
14400
14401 static bool has_edp_a(struct drm_device *dev)
14402 {
14403         struct drm_i915_private *dev_priv = dev->dev_private;
14404
14405         if (!IS_MOBILE(dev))
14406                 return false;
14407
14408         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14409                 return false;
14410
14411         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14412                 return false;
14413
14414         return true;
14415 }
14416
14417 static bool intel_crt_present(struct drm_device *dev)
14418 {
14419         struct drm_i915_private *dev_priv = dev->dev_private;
14420
14421         if (INTEL_INFO(dev)->gen >= 9)
14422                 return false;
14423
14424         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14425                 return false;
14426
14427         if (IS_CHERRYVIEW(dev))
14428                 return false;
14429
14430         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14431                 return false;
14432
14433         /* DDI E can't be used if DDI A requires 4 lanes */
14434         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14435                 return false;
14436
14437         if (!dev_priv->vbt.int_crt_support)
14438                 return false;
14439
14440         return true;
14441 }
14442
14443 static void intel_setup_outputs(struct drm_device *dev)
14444 {
14445         struct drm_i915_private *dev_priv = dev->dev_private;
14446         struct intel_encoder *encoder;
14447         bool dpd_is_edp = false;
14448
14449         intel_lvds_init(dev);
14450
14451         if (intel_crt_present(dev))
14452                 intel_crt_init(dev);
14453
14454         if (IS_BROXTON(dev)) {
14455                 /*
14456                  * FIXME: Broxton doesn't support port detection via the
14457                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14458                  * detect the ports.
14459                  */
14460                 intel_ddi_init(dev, PORT_A);
14461                 intel_ddi_init(dev, PORT_B);
14462                 intel_ddi_init(dev, PORT_C);
14463
14464                 intel_dsi_init(dev);
14465         } else if (HAS_DDI(dev)) {
14466                 int found;
14467
14468                 /*
14469                  * Haswell uses DDI functions to detect digital outputs.
14470                  * On SKL pre-D0 the strap isn't connected, so we assume
14471                  * it's there.
14472                  */
14473                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14474                 /* WaIgnoreDDIAStrap: skl */
14475                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14476                         intel_ddi_init(dev, PORT_A);
14477
14478                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14479                  * register */
14480                 found = I915_READ(SFUSE_STRAP);
14481
14482                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14483                         intel_ddi_init(dev, PORT_B);
14484                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14485                         intel_ddi_init(dev, PORT_C);
14486                 if (found & SFUSE_STRAP_DDID_DETECTED)
14487                         intel_ddi_init(dev, PORT_D);
14488                 /*
14489                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14490                  */
14491                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14492                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14493                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14494                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14495                         intel_ddi_init(dev, PORT_E);
14496
14497         } else if (HAS_PCH_SPLIT(dev)) {
14498                 int found;
14499                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14500
14501                 if (has_edp_a(dev))
14502                         intel_dp_init(dev, DP_A, PORT_A);
14503
14504                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14505                         /* PCH SDVOB multiplex with HDMIB */
14506                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14507                         if (!found)
14508                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14509                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14510                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14511                 }
14512
14513                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14514                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14515
14516                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14517                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14518
14519                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14520                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14521
14522                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14523                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14524         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14525                 /*
14526                  * The DP_DETECTED bit is the latched state of the DDC
14527                  * SDA pin at boot. However since eDP doesn't require DDC
14528                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14529                  * eDP ports may have been muxed to an alternate function.
14530                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14531                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14532                  * detect eDP ports.
14533                  */
14534                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14535                     !intel_dp_is_edp(dev, PORT_B))
14536                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14537                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14538                     intel_dp_is_edp(dev, PORT_B))
14539                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14540
14541                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14542                     !intel_dp_is_edp(dev, PORT_C))
14543                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14544                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14545                     intel_dp_is_edp(dev, PORT_C))
14546                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14547
14548                 if (IS_CHERRYVIEW(dev)) {
14549                         /* eDP not supported on port D, so don't check VBT */
14550                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14551                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14552                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14553                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14554                 }
14555
14556                 intel_dsi_init(dev);
14557         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14558                 bool found = false;
14559
14560                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14561                         DRM_DEBUG_KMS("probing SDVOB\n");
14562                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14563                         if (!found && IS_G4X(dev)) {
14564                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14565                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14566                         }
14567
14568                         if (!found && IS_G4X(dev))
14569                                 intel_dp_init(dev, DP_B, PORT_B);
14570                 }
14571
14572                 /* Before G4X SDVOC doesn't have its own detect register */
14573
14574                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14575                         DRM_DEBUG_KMS("probing SDVOC\n");
14576                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14577                 }
14578
14579                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14580
14581                         if (IS_G4X(dev)) {
14582                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14583                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14584                         }
14585                         if (IS_G4X(dev))
14586                                 intel_dp_init(dev, DP_C, PORT_C);
14587                 }
14588
14589                 if (IS_G4X(dev) &&
14590                     (I915_READ(DP_D) & DP_DETECTED))
14591                         intel_dp_init(dev, DP_D, PORT_D);
14592         } else if (IS_GEN2(dev))
14593                 intel_dvo_init(dev);
14594
14595         if (SUPPORTS_TV(dev))
14596                 intel_tv_init(dev);
14597
14598         intel_psr_init(dev);
14599
14600         for_each_intel_encoder(dev, encoder) {
14601                 encoder->base.possible_crtcs = encoder->crtc_mask;
14602                 encoder->base.possible_clones =
14603                         intel_encoder_clones(encoder);
14604         }
14605
14606         intel_init_pch_refclk(dev);
14607
14608         drm_helper_move_panel_connectors_to_head(dev);
14609 }
14610
14611 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14612 {
14613         struct drm_device *dev = fb->dev;
14614         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14615
14616         drm_framebuffer_cleanup(fb);
14617         mutex_lock(&dev->struct_mutex);
14618         WARN_ON(!intel_fb->obj->framebuffer_references--);
14619         drm_gem_object_unreference(&intel_fb->obj->base);
14620         mutex_unlock(&dev->struct_mutex);
14621         kfree(intel_fb);
14622 }
14623
14624 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14625                                                 struct drm_file *file,
14626                                                 unsigned int *handle)
14627 {
14628         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14629         struct drm_i915_gem_object *obj = intel_fb->obj;
14630
14631         if (obj->userptr.mm) {
14632                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14633                 return -EINVAL;
14634         }
14635
14636         return drm_gem_handle_create(file, &obj->base, handle);
14637 }
14638
14639 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14640                                         struct drm_file *file,
14641                                         unsigned flags, unsigned color,
14642                                         struct drm_clip_rect *clips,
14643                                         unsigned num_clips)
14644 {
14645         struct drm_device *dev = fb->dev;
14646         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14647         struct drm_i915_gem_object *obj = intel_fb->obj;
14648
14649         mutex_lock(&dev->struct_mutex);
14650         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14651         mutex_unlock(&dev->struct_mutex);
14652
14653         return 0;
14654 }
14655
14656 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14657         .destroy = intel_user_framebuffer_destroy,
14658         .create_handle = intel_user_framebuffer_create_handle,
14659         .dirty = intel_user_framebuffer_dirty,
14660 };
14661
14662 static
14663 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14664                          uint32_t pixel_format)
14665 {
14666         u32 gen = INTEL_INFO(dev)->gen;
14667
14668         if (gen >= 9) {
14669                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14670
14671                 /* "The stride in bytes must not exceed the of the size of 8K
14672                  *  pixels and 32K bytes."
14673                  */
14674                 return min(8192 * cpp, 32768);
14675         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14676                 return 32*1024;
14677         } else if (gen >= 4) {
14678                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14679                         return 16*1024;
14680                 else
14681                         return 32*1024;
14682         } else if (gen >= 3) {
14683                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14684                         return 8*1024;
14685                 else
14686                         return 16*1024;
14687         } else {
14688                 /* XXX DSPC is limited to 4k tiled */
14689                 return 8*1024;
14690         }
14691 }
14692
14693 static int intel_framebuffer_init(struct drm_device *dev,
14694                                   struct intel_framebuffer *intel_fb,
14695                                   struct drm_mode_fb_cmd2 *mode_cmd,
14696                                   struct drm_i915_gem_object *obj)
14697 {
14698         struct drm_i915_private *dev_priv = to_i915(dev);
14699         unsigned int aligned_height;
14700         int ret;
14701         u32 pitch_limit, stride_alignment;
14702
14703         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14704
14705         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14706                 /* Enforce that fb modifier and tiling mode match, but only for
14707                  * X-tiled. This is needed for FBC. */
14708                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14709                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14710                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14711                         return -EINVAL;
14712                 }
14713         } else {
14714                 if (obj->tiling_mode == I915_TILING_X)
14715                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14716                 else if (obj->tiling_mode == I915_TILING_Y) {
14717                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14718                         return -EINVAL;
14719                 }
14720         }
14721
14722         /* Passed in modifier sanity checking. */
14723         switch (mode_cmd->modifier[0]) {
14724         case I915_FORMAT_MOD_Y_TILED:
14725         case I915_FORMAT_MOD_Yf_TILED:
14726                 if (INTEL_INFO(dev)->gen < 9) {
14727                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14728                                   mode_cmd->modifier[0]);
14729                         return -EINVAL;
14730                 }
14731         case DRM_FORMAT_MOD_NONE:
14732         case I915_FORMAT_MOD_X_TILED:
14733                 break;
14734         default:
14735                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14736                           mode_cmd->modifier[0]);
14737                 return -EINVAL;
14738         }
14739
14740         stride_alignment = intel_fb_stride_alignment(dev_priv,
14741                                                      mode_cmd->modifier[0],
14742                                                      mode_cmd->pixel_format);
14743         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14744                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14745                           mode_cmd->pitches[0], stride_alignment);
14746                 return -EINVAL;
14747         }
14748
14749         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14750                                            mode_cmd->pixel_format);
14751         if (mode_cmd->pitches[0] > pitch_limit) {
14752                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14753                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14754                           "tiled" : "linear",
14755                           mode_cmd->pitches[0], pitch_limit);
14756                 return -EINVAL;
14757         }
14758
14759         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14760             mode_cmd->pitches[0] != obj->stride) {
14761                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14762                           mode_cmd->pitches[0], obj->stride);
14763                 return -EINVAL;
14764         }
14765
14766         /* Reject formats not supported by any plane early. */
14767         switch (mode_cmd->pixel_format) {
14768         case DRM_FORMAT_C8:
14769         case DRM_FORMAT_RGB565:
14770         case DRM_FORMAT_XRGB8888:
14771         case DRM_FORMAT_ARGB8888:
14772                 break;
14773         case DRM_FORMAT_XRGB1555:
14774                 if (INTEL_INFO(dev)->gen > 3) {
14775                         DRM_DEBUG("unsupported pixel format: %s\n",
14776                                   drm_get_format_name(mode_cmd->pixel_format));
14777                         return -EINVAL;
14778                 }
14779                 break;
14780         case DRM_FORMAT_ABGR8888:
14781                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14782                     INTEL_INFO(dev)->gen < 9) {
14783                         DRM_DEBUG("unsupported pixel format: %s\n",
14784                                   drm_get_format_name(mode_cmd->pixel_format));
14785                         return -EINVAL;
14786                 }
14787                 break;
14788         case DRM_FORMAT_XBGR8888:
14789         case DRM_FORMAT_XRGB2101010:
14790         case DRM_FORMAT_XBGR2101010:
14791                 if (INTEL_INFO(dev)->gen < 4) {
14792                         DRM_DEBUG("unsupported pixel format: %s\n",
14793                                   drm_get_format_name(mode_cmd->pixel_format));
14794                         return -EINVAL;
14795                 }
14796                 break;
14797         case DRM_FORMAT_ABGR2101010:
14798                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14799                         DRM_DEBUG("unsupported pixel format: %s\n",
14800                                   drm_get_format_name(mode_cmd->pixel_format));
14801                         return -EINVAL;
14802                 }
14803                 break;
14804         case DRM_FORMAT_YUYV:
14805         case DRM_FORMAT_UYVY:
14806         case DRM_FORMAT_YVYU:
14807         case DRM_FORMAT_VYUY:
14808                 if (INTEL_INFO(dev)->gen < 5) {
14809                         DRM_DEBUG("unsupported pixel format: %s\n",
14810                                   drm_get_format_name(mode_cmd->pixel_format));
14811                         return -EINVAL;
14812                 }
14813                 break;
14814         default:
14815                 DRM_DEBUG("unsupported pixel format: %s\n",
14816                           drm_get_format_name(mode_cmd->pixel_format));
14817                 return -EINVAL;
14818         }
14819
14820         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14821         if (mode_cmd->offsets[0] != 0)
14822                 return -EINVAL;
14823
14824         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14825                                                mode_cmd->pixel_format,
14826                                                mode_cmd->modifier[0]);
14827         /* FIXME drm helper for size checks (especially planar formats)? */
14828         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14829                 return -EINVAL;
14830
14831         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14832         intel_fb->obj = obj;
14833
14834         intel_fill_fb_info(dev_priv, &intel_fb->base);
14835
14836         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14837         if (ret) {
14838                 DRM_ERROR("framebuffer init failed %d\n", ret);
14839                 return ret;
14840         }
14841
14842         intel_fb->obj->framebuffer_references++;
14843
14844         return 0;
14845 }
14846
14847 static struct drm_framebuffer *
14848 intel_user_framebuffer_create(struct drm_device *dev,
14849                               struct drm_file *filp,
14850                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14851 {
14852         struct drm_framebuffer *fb;
14853         struct drm_i915_gem_object *obj;
14854         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14855
14856         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14857                                                 mode_cmd.handles[0]));
14858         if (&obj->base == NULL)
14859                 return ERR_PTR(-ENOENT);
14860
14861         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14862         if (IS_ERR(fb))
14863                 drm_gem_object_unreference_unlocked(&obj->base);
14864
14865         return fb;
14866 }
14867
14868 #ifndef CONFIG_DRM_FBDEV_EMULATION
14869 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14870 {
14871 }
14872 #endif
14873
14874 static const struct drm_mode_config_funcs intel_mode_funcs = {
14875         .fb_create = intel_user_framebuffer_create,
14876         .output_poll_changed = intel_fbdev_output_poll_changed,
14877         .atomic_check = intel_atomic_check,
14878         .atomic_commit = intel_atomic_commit,
14879         .atomic_state_alloc = intel_atomic_state_alloc,
14880         .atomic_state_clear = intel_atomic_state_clear,
14881 };
14882
14883 /**
14884  * intel_init_display_hooks - initialize the display modesetting hooks
14885  * @dev_priv: device private
14886  */
14887 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14888 {
14889         if (INTEL_INFO(dev_priv)->gen >= 9) {
14890                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14891                 dev_priv->display.get_initial_plane_config =
14892                         skylake_get_initial_plane_config;
14893                 dev_priv->display.crtc_compute_clock =
14894                         haswell_crtc_compute_clock;
14895                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14896                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14897         } else if (HAS_DDI(dev_priv)) {
14898                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14899                 dev_priv->display.get_initial_plane_config =
14900                         ironlake_get_initial_plane_config;
14901                 dev_priv->display.crtc_compute_clock =
14902                         haswell_crtc_compute_clock;
14903                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14904                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14905         } else if (HAS_PCH_SPLIT(dev_priv)) {
14906                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14907                 dev_priv->display.get_initial_plane_config =
14908                         ironlake_get_initial_plane_config;
14909                 dev_priv->display.crtc_compute_clock =
14910                         ironlake_crtc_compute_clock;
14911                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14912                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14913         } else if (IS_CHERRYVIEW(dev_priv)) {
14914                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14915                 dev_priv->display.get_initial_plane_config =
14916                         i9xx_get_initial_plane_config;
14917                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14918                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14919                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14920         } else if (IS_VALLEYVIEW(dev_priv)) {
14921                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14922                 dev_priv->display.get_initial_plane_config =
14923                         i9xx_get_initial_plane_config;
14924                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14925                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14926                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14927         } else if (IS_G4X(dev_priv)) {
14928                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14929                 dev_priv->display.get_initial_plane_config =
14930                         i9xx_get_initial_plane_config;
14931                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14932                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14933                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14934         } else if (IS_PINEVIEW(dev_priv)) {
14935                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14936                 dev_priv->display.get_initial_plane_config =
14937                         i9xx_get_initial_plane_config;
14938                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14939                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14940                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14941         } else if (!IS_GEN2(dev_priv)) {
14942                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14943                 dev_priv->display.get_initial_plane_config =
14944                         i9xx_get_initial_plane_config;
14945                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14946                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14947                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14948         } else {
14949                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14950                 dev_priv->display.get_initial_plane_config =
14951                         i9xx_get_initial_plane_config;
14952                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14953                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14954                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14955         }
14956
14957         /* Returns the core display clock speed */
14958         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14959                 dev_priv->display.get_display_clock_speed =
14960                         skylake_get_display_clock_speed;
14961         else if (IS_BROXTON(dev_priv))
14962                 dev_priv->display.get_display_clock_speed =
14963                         broxton_get_display_clock_speed;
14964         else if (IS_BROADWELL(dev_priv))
14965                 dev_priv->display.get_display_clock_speed =
14966                         broadwell_get_display_clock_speed;
14967         else if (IS_HASWELL(dev_priv))
14968                 dev_priv->display.get_display_clock_speed =
14969                         haswell_get_display_clock_speed;
14970         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14971                 dev_priv->display.get_display_clock_speed =
14972                         valleyview_get_display_clock_speed;
14973         else if (IS_GEN5(dev_priv))
14974                 dev_priv->display.get_display_clock_speed =
14975                         ilk_get_display_clock_speed;
14976         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14977                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
14978                 dev_priv->display.get_display_clock_speed =
14979                         i945_get_display_clock_speed;
14980         else if (IS_GM45(dev_priv))
14981                 dev_priv->display.get_display_clock_speed =
14982                         gm45_get_display_clock_speed;
14983         else if (IS_CRESTLINE(dev_priv))
14984                 dev_priv->display.get_display_clock_speed =
14985                         i965gm_get_display_clock_speed;
14986         else if (IS_PINEVIEW(dev_priv))
14987                 dev_priv->display.get_display_clock_speed =
14988                         pnv_get_display_clock_speed;
14989         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
14990                 dev_priv->display.get_display_clock_speed =
14991                         g33_get_display_clock_speed;
14992         else if (IS_I915G(dev_priv))
14993                 dev_priv->display.get_display_clock_speed =
14994                         i915_get_display_clock_speed;
14995         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
14996                 dev_priv->display.get_display_clock_speed =
14997                         i9xx_misc_get_display_clock_speed;
14998         else if (IS_I915GM(dev_priv))
14999                 dev_priv->display.get_display_clock_speed =
15000                         i915gm_get_display_clock_speed;
15001         else if (IS_I865G(dev_priv))
15002                 dev_priv->display.get_display_clock_speed =
15003                         i865_get_display_clock_speed;
15004         else if (IS_I85X(dev_priv))
15005                 dev_priv->display.get_display_clock_speed =
15006                         i85x_get_display_clock_speed;
15007         else { /* 830 */
15008                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15009                 dev_priv->display.get_display_clock_speed =
15010                         i830_get_display_clock_speed;
15011         }
15012
15013         if (IS_GEN5(dev_priv)) {
15014                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15015         } else if (IS_GEN6(dev_priv)) {
15016                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15017         } else if (IS_IVYBRIDGE(dev_priv)) {
15018                 /* FIXME: detect B0+ stepping and use auto training */
15019                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15020         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15021                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15022         }
15023
15024         if (IS_BROADWELL(dev_priv)) {
15025                 dev_priv->display.modeset_commit_cdclk =
15026                         broadwell_modeset_commit_cdclk;
15027                 dev_priv->display.modeset_calc_cdclk =
15028                         broadwell_modeset_calc_cdclk;
15029         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15030                 dev_priv->display.modeset_commit_cdclk =
15031                         valleyview_modeset_commit_cdclk;
15032                 dev_priv->display.modeset_calc_cdclk =
15033                         valleyview_modeset_calc_cdclk;
15034         } else if (IS_BROXTON(dev_priv)) {
15035                 dev_priv->display.modeset_commit_cdclk =
15036                         broxton_modeset_commit_cdclk;
15037                 dev_priv->display.modeset_calc_cdclk =
15038                         broxton_modeset_calc_cdclk;
15039         }
15040
15041         switch (INTEL_INFO(dev_priv)->gen) {
15042         case 2:
15043                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15044                 break;
15045
15046         case 3:
15047                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15048                 break;
15049
15050         case 4:
15051         case 5:
15052                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15053                 break;
15054
15055         case 6:
15056                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15057                 break;
15058         case 7:
15059         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15060                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15061                 break;
15062         case 9:
15063                 /* Drop through - unsupported since execlist only. */
15064         default:
15065                 /* Default just returns -ENODEV to indicate unsupported */
15066                 dev_priv->display.queue_flip = intel_default_queue_flip;
15067         }
15068 }
15069
15070 /*
15071  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15072  * resume, or other times.  This quirk makes sure that's the case for
15073  * affected systems.
15074  */
15075 static void quirk_pipea_force(struct drm_device *dev)
15076 {
15077         struct drm_i915_private *dev_priv = dev->dev_private;
15078
15079         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15080         DRM_INFO("applying pipe a force quirk\n");
15081 }
15082
15083 static void quirk_pipeb_force(struct drm_device *dev)
15084 {
15085         struct drm_i915_private *dev_priv = dev->dev_private;
15086
15087         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15088         DRM_INFO("applying pipe b force quirk\n");
15089 }
15090
15091 /*
15092  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15093  */
15094 static void quirk_ssc_force_disable(struct drm_device *dev)
15095 {
15096         struct drm_i915_private *dev_priv = dev->dev_private;
15097         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15098         DRM_INFO("applying lvds SSC disable quirk\n");
15099 }
15100
15101 /*
15102  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15103  * brightness value
15104  */
15105 static void quirk_invert_brightness(struct drm_device *dev)
15106 {
15107         struct drm_i915_private *dev_priv = dev->dev_private;
15108         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15109         DRM_INFO("applying inverted panel brightness quirk\n");
15110 }
15111
15112 /* Some VBT's incorrectly indicate no backlight is present */
15113 static void quirk_backlight_present(struct drm_device *dev)
15114 {
15115         struct drm_i915_private *dev_priv = dev->dev_private;
15116         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15117         DRM_INFO("applying backlight present quirk\n");
15118 }
15119
15120 struct intel_quirk {
15121         int device;
15122         int subsystem_vendor;
15123         int subsystem_device;
15124         void (*hook)(struct drm_device *dev);
15125 };
15126
15127 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15128 struct intel_dmi_quirk {
15129         void (*hook)(struct drm_device *dev);
15130         const struct dmi_system_id (*dmi_id_list)[];
15131 };
15132
15133 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15134 {
15135         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15136         return 1;
15137 }
15138
15139 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15140         {
15141                 .dmi_id_list = &(const struct dmi_system_id[]) {
15142                         {
15143                                 .callback = intel_dmi_reverse_brightness,
15144                                 .ident = "NCR Corporation",
15145                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15146                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15147                                 },
15148                         },
15149                         { }  /* terminating entry */
15150                 },
15151                 .hook = quirk_invert_brightness,
15152         },
15153 };
15154
15155 static struct intel_quirk intel_quirks[] = {
15156         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15157         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15158
15159         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15160         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15161
15162         /* 830 needs to leave pipe A & dpll A up */
15163         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15164
15165         /* 830 needs to leave pipe B & dpll B up */
15166         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15167
15168         /* Lenovo U160 cannot use SSC on LVDS */
15169         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15170
15171         /* Sony Vaio Y cannot use SSC on LVDS */
15172         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15173
15174         /* Acer Aspire 5734Z must invert backlight brightness */
15175         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15176
15177         /* Acer/eMachines G725 */
15178         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15179
15180         /* Acer/eMachines e725 */
15181         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15182
15183         /* Acer/Packard Bell NCL20 */
15184         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15185
15186         /* Acer Aspire 4736Z */
15187         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15188
15189         /* Acer Aspire 5336 */
15190         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15191
15192         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15193         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15194
15195         /* Acer C720 Chromebook (Core i3 4005U) */
15196         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15197
15198         /* Apple Macbook 2,1 (Core 2 T7400) */
15199         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15200
15201         /* Apple Macbook 4,1 */
15202         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15203
15204         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15205         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15206
15207         /* HP Chromebook 14 (Celeron 2955U) */
15208         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15209
15210         /* Dell Chromebook 11 */
15211         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15212
15213         /* Dell Chromebook 11 (2015 version) */
15214         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15215 };
15216
15217 static void intel_init_quirks(struct drm_device *dev)
15218 {
15219         struct pci_dev *d = dev->pdev;
15220         int i;
15221
15222         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15223                 struct intel_quirk *q = &intel_quirks[i];
15224
15225                 if (d->device == q->device &&
15226                     (d->subsystem_vendor == q->subsystem_vendor ||
15227                      q->subsystem_vendor == PCI_ANY_ID) &&
15228                     (d->subsystem_device == q->subsystem_device ||
15229                      q->subsystem_device == PCI_ANY_ID))
15230                         q->hook(dev);
15231         }
15232         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15233                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15234                         intel_dmi_quirks[i].hook(dev);
15235         }
15236 }
15237
15238 /* Disable the VGA plane that we never use */
15239 static void i915_disable_vga(struct drm_device *dev)
15240 {
15241         struct drm_i915_private *dev_priv = dev->dev_private;
15242         u8 sr1;
15243         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15244
15245         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15246         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15247         outb(SR01, VGA_SR_INDEX);
15248         sr1 = inb(VGA_SR_DATA);
15249         outb(sr1 | 1<<5, VGA_SR_DATA);
15250         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15251         udelay(300);
15252
15253         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15254         POSTING_READ(vga_reg);
15255 }
15256
15257 void intel_modeset_init_hw(struct drm_device *dev)
15258 {
15259         struct drm_i915_private *dev_priv = dev->dev_private;
15260
15261         intel_update_cdclk(dev);
15262
15263         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15264
15265         intel_init_clock_gating(dev);
15266         intel_enable_gt_powersave(dev_priv);
15267 }
15268
15269 /*
15270  * Calculate what we think the watermarks should be for the state we've read
15271  * out of the hardware and then immediately program those watermarks so that
15272  * we ensure the hardware settings match our internal state.
15273  *
15274  * We can calculate what we think WM's should be by creating a duplicate of the
15275  * current state (which was constructed during hardware readout) and running it
15276  * through the atomic check code to calculate new watermark values in the
15277  * state object.
15278  */
15279 static void sanitize_watermarks(struct drm_device *dev)
15280 {
15281         struct drm_i915_private *dev_priv = to_i915(dev);
15282         struct drm_atomic_state *state;
15283         struct drm_crtc *crtc;
15284         struct drm_crtc_state *cstate;
15285         struct drm_modeset_acquire_ctx ctx;
15286         int ret;
15287         int i;
15288
15289         /* Only supported on platforms that use atomic watermark design */
15290         if (!dev_priv->display.optimize_watermarks)
15291                 return;
15292
15293         /*
15294          * We need to hold connection_mutex before calling duplicate_state so
15295          * that the connector loop is protected.
15296          */
15297         drm_modeset_acquire_init(&ctx, 0);
15298 retry:
15299         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15300         if (ret == -EDEADLK) {
15301                 drm_modeset_backoff(&ctx);
15302                 goto retry;
15303         } else if (WARN_ON(ret)) {
15304                 goto fail;
15305         }
15306
15307         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15308         if (WARN_ON(IS_ERR(state)))
15309                 goto fail;
15310
15311         /*
15312          * Hardware readout is the only time we don't want to calculate
15313          * intermediate watermarks (since we don't trust the current
15314          * watermarks).
15315          */
15316         to_intel_atomic_state(state)->skip_intermediate_wm = true;
15317
15318         ret = intel_atomic_check(dev, state);
15319         if (ret) {
15320                 /*
15321                  * If we fail here, it means that the hardware appears to be
15322                  * programmed in a way that shouldn't be possible, given our
15323                  * understanding of watermark requirements.  This might mean a
15324                  * mistake in the hardware readout code or a mistake in the
15325                  * watermark calculations for a given platform.  Raise a WARN
15326                  * so that this is noticeable.
15327                  *
15328                  * If this actually happens, we'll have to just leave the
15329                  * BIOS-programmed watermarks untouched and hope for the best.
15330                  */
15331                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15332                 goto fail;
15333         }
15334
15335         /* Write calculated watermark values back */
15336         for_each_crtc_in_state(state, crtc, cstate, i) {
15337                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15338
15339                 cs->wm.need_postvbl_update = true;
15340                 dev_priv->display.optimize_watermarks(cs);
15341         }
15342
15343         drm_atomic_state_free(state);
15344 fail:
15345         drm_modeset_drop_locks(&ctx);
15346         drm_modeset_acquire_fini(&ctx);
15347 }
15348
15349 void intel_modeset_init(struct drm_device *dev)
15350 {
15351         struct drm_i915_private *dev_priv = to_i915(dev);
15352         struct i915_ggtt *ggtt = &dev_priv->ggtt;
15353         int sprite, ret;
15354         enum pipe pipe;
15355         struct intel_crtc *crtc;
15356
15357         drm_mode_config_init(dev);
15358
15359         dev->mode_config.min_width = 0;
15360         dev->mode_config.min_height = 0;
15361
15362         dev->mode_config.preferred_depth = 24;
15363         dev->mode_config.prefer_shadow = 1;
15364
15365         dev->mode_config.allow_fb_modifiers = true;
15366
15367         dev->mode_config.funcs = &intel_mode_funcs;
15368
15369         intel_init_quirks(dev);
15370
15371         intel_init_pm(dev);
15372
15373         if (INTEL_INFO(dev)->num_pipes == 0)
15374                 return;
15375
15376         /*
15377          * There may be no VBT; and if the BIOS enabled SSC we can
15378          * just keep using it to avoid unnecessary flicker.  Whereas if the
15379          * BIOS isn't using it, don't assume it will work even if the VBT
15380          * indicates as much.
15381          */
15382         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15383                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15384                                             DREF_SSC1_ENABLE);
15385
15386                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15387                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15388                                      bios_lvds_use_ssc ? "en" : "dis",
15389                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15390                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15391                 }
15392         }
15393
15394         if (IS_GEN2(dev)) {
15395                 dev->mode_config.max_width = 2048;
15396                 dev->mode_config.max_height = 2048;
15397         } else if (IS_GEN3(dev)) {
15398                 dev->mode_config.max_width = 4096;
15399                 dev->mode_config.max_height = 4096;
15400         } else {
15401                 dev->mode_config.max_width = 8192;
15402                 dev->mode_config.max_height = 8192;
15403         }
15404
15405         if (IS_845G(dev) || IS_I865G(dev)) {
15406                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15407                 dev->mode_config.cursor_height = 1023;
15408         } else if (IS_GEN2(dev)) {
15409                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15410                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15411         } else {
15412                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15413                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15414         }
15415
15416         dev->mode_config.fb_base = ggtt->mappable_base;
15417
15418         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15419                       INTEL_INFO(dev)->num_pipes,
15420                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15421
15422         for_each_pipe(dev_priv, pipe) {
15423                 intel_crtc_init(dev, pipe);
15424                 for_each_sprite(dev_priv, pipe, sprite) {
15425                         ret = intel_plane_init(dev, pipe, sprite);
15426                         if (ret)
15427                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15428                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15429                 }
15430         }
15431
15432         intel_update_czclk(dev_priv);
15433         intel_update_cdclk(dev);
15434
15435         intel_shared_dpll_init(dev);
15436
15437         /* Just disable it once at startup */
15438         i915_disable_vga(dev);
15439         intel_setup_outputs(dev);
15440
15441         drm_modeset_lock_all(dev);
15442         intel_modeset_setup_hw_state(dev);
15443         drm_modeset_unlock_all(dev);
15444
15445         for_each_intel_crtc(dev, crtc) {
15446                 struct intel_initial_plane_config plane_config = {};
15447
15448                 if (!crtc->active)
15449                         continue;
15450
15451                 /*
15452                  * Note that reserving the BIOS fb up front prevents us
15453                  * from stuffing other stolen allocations like the ring
15454                  * on top.  This prevents some ugliness at boot time, and
15455                  * can even allow for smooth boot transitions if the BIOS
15456                  * fb is large enough for the active pipe configuration.
15457                  */
15458                 dev_priv->display.get_initial_plane_config(crtc,
15459                                                            &plane_config);
15460
15461                 /*
15462                  * If the fb is shared between multiple heads, we'll
15463                  * just get the first one.
15464                  */
15465                 intel_find_initial_plane_obj(crtc, &plane_config);
15466         }
15467
15468         /*
15469          * Make sure hardware watermarks really match the state we read out.
15470          * Note that we need to do this after reconstructing the BIOS fb's
15471          * since the watermark calculation done here will use pstate->fb.
15472          */
15473         sanitize_watermarks(dev);
15474 }
15475
15476 static void intel_enable_pipe_a(struct drm_device *dev)
15477 {
15478         struct intel_connector *connector;
15479         struct drm_connector *crt = NULL;
15480         struct intel_load_detect_pipe load_detect_temp;
15481         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15482
15483         /* We can't just switch on the pipe A, we need to set things up with a
15484          * proper mode and output configuration. As a gross hack, enable pipe A
15485          * by enabling the load detect pipe once. */
15486         for_each_intel_connector(dev, connector) {
15487                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15488                         crt = &connector->base;
15489                         break;
15490                 }
15491         }
15492
15493         if (!crt)
15494                 return;
15495
15496         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15497                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15498 }
15499
15500 static bool
15501 intel_check_plane_mapping(struct intel_crtc *crtc)
15502 {
15503         struct drm_device *dev = crtc->base.dev;
15504         struct drm_i915_private *dev_priv = dev->dev_private;
15505         u32 val;
15506
15507         if (INTEL_INFO(dev)->num_pipes == 1)
15508                 return true;
15509
15510         val = I915_READ(DSPCNTR(!crtc->plane));
15511
15512         if ((val & DISPLAY_PLANE_ENABLE) &&
15513             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15514                 return false;
15515
15516         return true;
15517 }
15518
15519 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15520 {
15521         struct drm_device *dev = crtc->base.dev;
15522         struct intel_encoder *encoder;
15523
15524         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15525                 return true;
15526
15527         return false;
15528 }
15529
15530 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15531 {
15532         struct drm_device *dev = encoder->base.dev;
15533         struct intel_connector *connector;
15534
15535         for_each_connector_on_encoder(dev, &encoder->base, connector)
15536                 return true;
15537
15538         return false;
15539 }
15540
15541 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15542 {
15543         struct drm_device *dev = crtc->base.dev;
15544         struct drm_i915_private *dev_priv = dev->dev_private;
15545         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15546
15547         /* Clear any frame start delays used for debugging left by the BIOS */
15548         if (!transcoder_is_dsi(cpu_transcoder)) {
15549                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15550
15551                 I915_WRITE(reg,
15552                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15553         }
15554
15555         /* restore vblank interrupts to correct state */
15556         drm_crtc_vblank_reset(&crtc->base);
15557         if (crtc->active) {
15558                 struct intel_plane *plane;
15559
15560                 drm_crtc_vblank_on(&crtc->base);
15561
15562                 /* Disable everything but the primary plane */
15563                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15564                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15565                                 continue;
15566
15567                         plane->disable_plane(&plane->base, &crtc->base);
15568                 }
15569         }
15570
15571         /* We need to sanitize the plane -> pipe mapping first because this will
15572          * disable the crtc (and hence change the state) if it is wrong. Note
15573          * that gen4+ has a fixed plane -> pipe mapping.  */
15574         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15575                 bool plane;
15576
15577                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15578                               crtc->base.base.id);
15579
15580                 /* Pipe has the wrong plane attached and the plane is active.
15581                  * Temporarily change the plane mapping and disable everything
15582                  * ...  */
15583                 plane = crtc->plane;
15584                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15585                 crtc->plane = !plane;
15586                 intel_crtc_disable_noatomic(&crtc->base);
15587                 crtc->plane = plane;
15588         }
15589
15590         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15591             crtc->pipe == PIPE_A && !crtc->active) {
15592                 /* BIOS forgot to enable pipe A, this mostly happens after
15593                  * resume. Force-enable the pipe to fix this, the update_dpms
15594                  * call below we restore the pipe to the right state, but leave
15595                  * the required bits on. */
15596                 intel_enable_pipe_a(dev);
15597         }
15598
15599         /* Adjust the state of the output pipe according to whether we
15600          * have active connectors/encoders. */
15601         if (crtc->active && !intel_crtc_has_encoders(crtc))
15602                 intel_crtc_disable_noatomic(&crtc->base);
15603
15604         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15605                 /*
15606                  * We start out with underrun reporting disabled to avoid races.
15607                  * For correct bookkeeping mark this on active crtcs.
15608                  *
15609                  * Also on gmch platforms we dont have any hardware bits to
15610                  * disable the underrun reporting. Which means we need to start
15611                  * out with underrun reporting disabled also on inactive pipes,
15612                  * since otherwise we'll complain about the garbage we read when
15613                  * e.g. coming up after runtime pm.
15614                  *
15615                  * No protection against concurrent access is required - at
15616                  * worst a fifo underrun happens which also sets this to false.
15617                  */
15618                 crtc->cpu_fifo_underrun_disabled = true;
15619                 crtc->pch_fifo_underrun_disabled = true;
15620         }
15621 }
15622
15623 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15624 {
15625         struct intel_connector *connector;
15626         struct drm_device *dev = encoder->base.dev;
15627
15628         /* We need to check both for a crtc link (meaning that the
15629          * encoder is active and trying to read from a pipe) and the
15630          * pipe itself being active. */
15631         bool has_active_crtc = encoder->base.crtc &&
15632                 to_intel_crtc(encoder->base.crtc)->active;
15633
15634         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15635                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15636                               encoder->base.base.id,
15637                               encoder->base.name);
15638
15639                 /* Connector is active, but has no active pipe. This is
15640                  * fallout from our resume register restoring. Disable
15641                  * the encoder manually again. */
15642                 if (encoder->base.crtc) {
15643                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15644                                       encoder->base.base.id,
15645                                       encoder->base.name);
15646                         encoder->disable(encoder);
15647                         if (encoder->post_disable)
15648                                 encoder->post_disable(encoder);
15649                 }
15650                 encoder->base.crtc = NULL;
15651
15652                 /* Inconsistent output/port/pipe state happens presumably due to
15653                  * a bug in one of the get_hw_state functions. Or someplace else
15654                  * in our code, like the register restore mess on resume. Clamp
15655                  * things to off as a safer default. */
15656                 for_each_intel_connector(dev, connector) {
15657                         if (connector->encoder != encoder)
15658                                 continue;
15659                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15660                         connector->base.encoder = NULL;
15661                 }
15662         }
15663         /* Enabled encoders without active connectors will be fixed in
15664          * the crtc fixup. */
15665 }
15666
15667 void i915_redisable_vga_power_on(struct drm_device *dev)
15668 {
15669         struct drm_i915_private *dev_priv = dev->dev_private;
15670         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15671
15672         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15673                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15674                 i915_disable_vga(dev);
15675         }
15676 }
15677
15678 void i915_redisable_vga(struct drm_device *dev)
15679 {
15680         struct drm_i915_private *dev_priv = dev->dev_private;
15681
15682         /* This function can be called both from intel_modeset_setup_hw_state or
15683          * at a very early point in our resume sequence, where the power well
15684          * structures are not yet restored. Since this function is at a very
15685          * paranoid "someone might have enabled VGA while we were not looking"
15686          * level, just check if the power well is enabled instead of trying to
15687          * follow the "don't touch the power well if we don't need it" policy
15688          * the rest of the driver uses. */
15689         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15690                 return;
15691
15692         i915_redisable_vga_power_on(dev);
15693
15694         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15695 }
15696
15697 static bool primary_get_hw_state(struct intel_plane *plane)
15698 {
15699         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15700
15701         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15702 }
15703
15704 /* FIXME read out full plane state for all planes */
15705 static void readout_plane_state(struct intel_crtc *crtc)
15706 {
15707         struct drm_plane *primary = crtc->base.primary;
15708         struct intel_plane_state *plane_state =
15709                 to_intel_plane_state(primary->state);
15710
15711         plane_state->visible = crtc->active &&
15712                 primary_get_hw_state(to_intel_plane(primary));
15713
15714         if (plane_state->visible)
15715                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15716 }
15717
15718 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15719 {
15720         struct drm_i915_private *dev_priv = dev->dev_private;
15721         enum pipe pipe;
15722         struct intel_crtc *crtc;
15723         struct intel_encoder *encoder;
15724         struct intel_connector *connector;
15725         int i;
15726
15727         dev_priv->active_crtcs = 0;
15728
15729         for_each_intel_crtc(dev, crtc) {
15730                 struct intel_crtc_state *crtc_state = crtc->config;
15731                 int pixclk = 0;
15732
15733                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15734                 memset(crtc_state, 0, sizeof(*crtc_state));
15735                 crtc_state->base.crtc = &crtc->base;
15736
15737                 crtc_state->base.active = crtc_state->base.enable =
15738                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15739
15740                 crtc->base.enabled = crtc_state->base.enable;
15741                 crtc->active = crtc_state->base.active;
15742
15743                 if (crtc_state->base.active) {
15744                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15745
15746                         if (IS_BROADWELL(dev_priv)) {
15747                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
15748
15749                                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15750                                 if (crtc_state->ips_enabled)
15751                                         pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15752                         } else if (IS_VALLEYVIEW(dev_priv) ||
15753                                    IS_CHERRYVIEW(dev_priv) ||
15754                                    IS_BROXTON(dev_priv))
15755                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15756                         else
15757                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15758                 }
15759
15760                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15761
15762                 readout_plane_state(crtc);
15763
15764                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15765                               crtc->base.base.id,
15766                               crtc->active ? "enabled" : "disabled");
15767         }
15768
15769         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15770                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15771
15772                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15773                                                   &pll->config.hw_state);
15774                 pll->config.crtc_mask = 0;
15775                 for_each_intel_crtc(dev, crtc) {
15776                         if (crtc->active && crtc->config->shared_dpll == pll)
15777                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15778                 }
15779                 pll->active_mask = pll->config.crtc_mask;
15780
15781                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15782                               pll->name, pll->config.crtc_mask, pll->on);
15783         }
15784
15785         for_each_intel_encoder(dev, encoder) {
15786                 pipe = 0;
15787
15788                 if (encoder->get_hw_state(encoder, &pipe)) {
15789                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15790                         encoder->base.crtc = &crtc->base;
15791                         encoder->get_config(encoder, crtc->config);
15792                 } else {
15793                         encoder->base.crtc = NULL;
15794                 }
15795
15796                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15797                               encoder->base.base.id,
15798                               encoder->base.name,
15799                               encoder->base.crtc ? "enabled" : "disabled",
15800                               pipe_name(pipe));
15801         }
15802
15803         for_each_intel_connector(dev, connector) {
15804                 if (connector->get_hw_state(connector)) {
15805                         connector->base.dpms = DRM_MODE_DPMS_ON;
15806
15807                         encoder = connector->encoder;
15808                         connector->base.encoder = &encoder->base;
15809
15810                         if (encoder->base.crtc &&
15811                             encoder->base.crtc->state->active) {
15812                                 /*
15813                                  * This has to be done during hardware readout
15814                                  * because anything calling .crtc_disable may
15815                                  * rely on the connector_mask being accurate.
15816                                  */
15817                                 encoder->base.crtc->state->connector_mask |=
15818                                         1 << drm_connector_index(&connector->base);
15819                                 encoder->base.crtc->state->encoder_mask |=
15820                                         1 << drm_encoder_index(&encoder->base);
15821                         }
15822
15823                 } else {
15824                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15825                         connector->base.encoder = NULL;
15826                 }
15827                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15828                               connector->base.base.id,
15829                               connector->base.name,
15830                               connector->base.encoder ? "enabled" : "disabled");
15831         }
15832
15833         for_each_intel_crtc(dev, crtc) {
15834                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15835
15836                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15837                 if (crtc->base.state->active) {
15838                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15839                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15840                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15841
15842                         /*
15843                          * The initial mode needs to be set in order to keep
15844                          * the atomic core happy. It wants a valid mode if the
15845                          * crtc's enabled, so we do the above call.
15846                          *
15847                          * At this point some state updated by the connectors
15848                          * in their ->detect() callback has not run yet, so
15849                          * no recalculation can be done yet.
15850                          *
15851                          * Even if we could do a recalculation and modeset
15852                          * right now it would cause a double modeset if
15853                          * fbdev or userspace chooses a different initial mode.
15854                          *
15855                          * If that happens, someone indicated they wanted a
15856                          * mode change, which means it's safe to do a full
15857                          * recalculation.
15858                          */
15859                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15860
15861                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15862                         update_scanline_offset(crtc);
15863                 }
15864
15865                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15866         }
15867 }
15868
15869 /* Scan out the current hw modeset state,
15870  * and sanitizes it to the current state
15871  */
15872 static void
15873 intel_modeset_setup_hw_state(struct drm_device *dev)
15874 {
15875         struct drm_i915_private *dev_priv = dev->dev_private;
15876         enum pipe pipe;
15877         struct intel_crtc *crtc;
15878         struct intel_encoder *encoder;
15879         int i;
15880
15881         intel_modeset_readout_hw_state(dev);
15882
15883         /* HW state is read out, now we need to sanitize this mess. */
15884         for_each_intel_encoder(dev, encoder) {
15885                 intel_sanitize_encoder(encoder);
15886         }
15887
15888         for_each_pipe(dev_priv, pipe) {
15889                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15890                 intel_sanitize_crtc(crtc);
15891                 intel_dump_pipe_config(crtc, crtc->config,
15892                                        "[setup_hw_state]");
15893         }
15894
15895         intel_modeset_update_connector_atomic_state(dev);
15896
15897         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15898                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15899
15900                 if (!pll->on || pll->active_mask)
15901                         continue;
15902
15903                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15904
15905                 pll->funcs.disable(dev_priv, pll);
15906                 pll->on = false;
15907         }
15908
15909         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15910                 vlv_wm_get_hw_state(dev);
15911         else if (IS_GEN9(dev))
15912                 skl_wm_get_hw_state(dev);
15913         else if (HAS_PCH_SPLIT(dev))
15914                 ilk_wm_get_hw_state(dev);
15915
15916         for_each_intel_crtc(dev, crtc) {
15917                 unsigned long put_domains;
15918
15919                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15920                 if (WARN_ON(put_domains))
15921                         modeset_put_power_domains(dev_priv, put_domains);
15922         }
15923         intel_display_set_init_power(dev_priv, false);
15924
15925         intel_fbc_init_pipe_state(dev_priv);
15926 }
15927
15928 void intel_display_resume(struct drm_device *dev)
15929 {
15930         struct drm_i915_private *dev_priv = to_i915(dev);
15931         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15932         struct drm_modeset_acquire_ctx ctx;
15933         int ret;
15934         bool setup = false;
15935
15936         dev_priv->modeset_restore_state = NULL;
15937
15938         /*
15939          * This is a cludge because with real atomic modeset mode_config.mutex
15940          * won't be taken. Unfortunately some probed state like
15941          * audio_codec_enable is still protected by mode_config.mutex, so lock
15942          * it here for now.
15943          */
15944         mutex_lock(&dev->mode_config.mutex);
15945         drm_modeset_acquire_init(&ctx, 0);
15946
15947 retry:
15948         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15949
15950         if (ret == 0 && !setup) {
15951                 setup = true;
15952
15953                 intel_modeset_setup_hw_state(dev);
15954                 i915_redisable_vga(dev);
15955         }
15956
15957         if (ret == 0 && state) {
15958                 struct drm_crtc_state *crtc_state;
15959                 struct drm_crtc *crtc;
15960                 int i;
15961
15962                 state->acquire_ctx = &ctx;
15963
15964                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15965                         /*
15966                          * Force recalculation even if we restore
15967                          * current state. With fast modeset this may not result
15968                          * in a modeset when the state is compatible.
15969                          */
15970                         crtc_state->mode_changed = true;
15971                 }
15972
15973                 ret = drm_atomic_commit(state);
15974         }
15975
15976         if (ret == -EDEADLK) {
15977                 drm_modeset_backoff(&ctx);
15978                 goto retry;
15979         }
15980
15981         drm_modeset_drop_locks(&ctx);
15982         drm_modeset_acquire_fini(&ctx);
15983         mutex_unlock(&dev->mode_config.mutex);
15984
15985         if (ret) {
15986                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15987                 drm_atomic_state_free(state);
15988         }
15989 }
15990
15991 void intel_modeset_gem_init(struct drm_device *dev)
15992 {
15993         struct drm_i915_private *dev_priv = to_i915(dev);
15994         struct drm_crtc *c;
15995         struct drm_i915_gem_object *obj;
15996         int ret;
15997
15998         intel_init_gt_powersave(dev_priv);
15999
16000         intel_modeset_init_hw(dev);
16001
16002         intel_setup_overlay(dev_priv);
16003
16004         /*
16005          * Make sure any fbs we allocated at startup are properly
16006          * pinned & fenced.  When we do the allocation it's too early
16007          * for this.
16008          */
16009         for_each_crtc(dev, c) {
16010                 obj = intel_fb_obj(c->primary->fb);
16011                 if (obj == NULL)
16012                         continue;
16013
16014                 mutex_lock(&dev->struct_mutex);
16015                 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16016                                                  c->primary->state->rotation);
16017                 mutex_unlock(&dev->struct_mutex);
16018                 if (ret) {
16019                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
16020                                   to_intel_crtc(c)->pipe);
16021                         drm_framebuffer_unreference(c->primary->fb);
16022                         c->primary->fb = NULL;
16023                         c->primary->crtc = c->primary->state->crtc = NULL;
16024                         update_state_fb(c->primary);
16025                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16026                 }
16027         }
16028
16029         intel_backlight_register(dev);
16030 }
16031
16032 void intel_connector_unregister(struct intel_connector *intel_connector)
16033 {
16034         struct drm_connector *connector = &intel_connector->base;
16035
16036         intel_panel_destroy_backlight(connector);
16037         drm_connector_unregister(connector);
16038 }
16039
16040 void intel_modeset_cleanup(struct drm_device *dev)
16041 {
16042         struct drm_i915_private *dev_priv = dev->dev_private;
16043         struct intel_connector *connector;
16044
16045         intel_disable_gt_powersave(dev_priv);
16046
16047         intel_backlight_unregister(dev);
16048
16049         /*
16050          * Interrupts and polling as the first thing to avoid creating havoc.
16051          * Too much stuff here (turning of connectors, ...) would
16052          * experience fancy races otherwise.
16053          */
16054         intel_irq_uninstall(dev_priv);
16055
16056         /*
16057          * Due to the hpd irq storm handling the hotplug work can re-arm the
16058          * poll handlers. Hence disable polling after hpd handling is shut down.
16059          */
16060         drm_kms_helper_poll_fini(dev);
16061
16062         intel_unregister_dsm_handler();
16063
16064         intel_fbc_global_disable(dev_priv);
16065
16066         /* flush any delayed tasks or pending work */
16067         flush_scheduled_work();
16068
16069         /* destroy the backlight and sysfs files before encoders/connectors */
16070         for_each_intel_connector(dev, connector)
16071                 connector->unregister(connector);
16072
16073         drm_mode_config_cleanup(dev);
16074
16075         intel_cleanup_overlay(dev_priv);
16076
16077         intel_cleanup_gt_powersave(dev_priv);
16078
16079         intel_teardown_gmbus(dev);
16080 }
16081
16082 /*
16083  * Return which encoder is currently attached for connector.
16084  */
16085 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16086 {
16087         return &intel_attached_encoder(connector)->base;
16088 }
16089
16090 void intel_connector_attach_encoder(struct intel_connector *connector,
16091                                     struct intel_encoder *encoder)
16092 {
16093         connector->encoder = encoder;
16094         drm_mode_connector_attach_encoder(&connector->base,
16095                                           &encoder->base);
16096 }
16097
16098 /*
16099  * set vga decode state - true == enable VGA decode
16100  */
16101 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16102 {
16103         struct drm_i915_private *dev_priv = dev->dev_private;
16104         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16105         u16 gmch_ctrl;
16106
16107         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16108                 DRM_ERROR("failed to read control word\n");
16109                 return -EIO;
16110         }
16111
16112         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16113                 return 0;
16114
16115         if (state)
16116                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16117         else
16118                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16119
16120         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16121                 DRM_ERROR("failed to write control word\n");
16122                 return -EIO;
16123         }
16124
16125         return 0;
16126 }
16127
16128 struct intel_display_error_state {
16129
16130         u32 power_well_driver;
16131
16132         int num_transcoders;
16133
16134         struct intel_cursor_error_state {
16135                 u32 control;
16136                 u32 position;
16137                 u32 base;
16138                 u32 size;
16139         } cursor[I915_MAX_PIPES];
16140
16141         struct intel_pipe_error_state {
16142                 bool power_domain_on;
16143                 u32 source;
16144                 u32 stat;
16145         } pipe[I915_MAX_PIPES];
16146
16147         struct intel_plane_error_state {
16148                 u32 control;
16149                 u32 stride;
16150                 u32 size;
16151                 u32 pos;
16152                 u32 addr;
16153                 u32 surface;
16154                 u32 tile_offset;
16155         } plane[I915_MAX_PIPES];
16156
16157         struct intel_transcoder_error_state {
16158                 bool power_domain_on;
16159                 enum transcoder cpu_transcoder;
16160
16161                 u32 conf;
16162
16163                 u32 htotal;
16164                 u32 hblank;
16165                 u32 hsync;
16166                 u32 vtotal;
16167                 u32 vblank;
16168                 u32 vsync;
16169         } transcoder[4];
16170 };
16171
16172 struct intel_display_error_state *
16173 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16174 {
16175         struct intel_display_error_state *error;
16176         int transcoders[] = {
16177                 TRANSCODER_A,
16178                 TRANSCODER_B,
16179                 TRANSCODER_C,
16180                 TRANSCODER_EDP,
16181         };
16182         int i;
16183
16184         if (INTEL_INFO(dev_priv)->num_pipes == 0)
16185                 return NULL;
16186
16187         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16188         if (error == NULL)
16189                 return NULL;
16190
16191         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16192                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16193
16194         for_each_pipe(dev_priv, i) {
16195                 error->pipe[i].power_domain_on =
16196                         __intel_display_power_is_enabled(dev_priv,
16197                                                          POWER_DOMAIN_PIPE(i));
16198                 if (!error->pipe[i].power_domain_on)
16199                         continue;
16200
16201                 error->cursor[i].control = I915_READ(CURCNTR(i));
16202                 error->cursor[i].position = I915_READ(CURPOS(i));
16203                 error->cursor[i].base = I915_READ(CURBASE(i));
16204
16205                 error->plane[i].control = I915_READ(DSPCNTR(i));
16206                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16207                 if (INTEL_GEN(dev_priv) <= 3) {
16208                         error->plane[i].size = I915_READ(DSPSIZE(i));
16209                         error->plane[i].pos = I915_READ(DSPPOS(i));
16210                 }
16211                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16212                         error->plane[i].addr = I915_READ(DSPADDR(i));
16213                 if (INTEL_GEN(dev_priv) >= 4) {
16214                         error->plane[i].surface = I915_READ(DSPSURF(i));
16215                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16216                 }
16217
16218                 error->pipe[i].source = I915_READ(PIPESRC(i));
16219
16220                 if (HAS_GMCH_DISPLAY(dev_priv))
16221                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16222         }
16223
16224         /* Note: this does not include DSI transcoders. */
16225         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16226         if (HAS_DDI(dev_priv))
16227                 error->num_transcoders++; /* Account for eDP. */
16228
16229         for (i = 0; i < error->num_transcoders; i++) {
16230                 enum transcoder cpu_transcoder = transcoders[i];
16231
16232                 error->transcoder[i].power_domain_on =
16233                         __intel_display_power_is_enabled(dev_priv,
16234                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16235                 if (!error->transcoder[i].power_domain_on)
16236                         continue;
16237
16238                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16239
16240                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16241                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16242                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16243                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16244                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16245                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16246                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16247         }
16248
16249         return error;
16250 }
16251
16252 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16253
16254 void
16255 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16256                                 struct drm_device *dev,
16257                                 struct intel_display_error_state *error)
16258 {
16259         struct drm_i915_private *dev_priv = dev->dev_private;
16260         int i;
16261
16262         if (!error)
16263                 return;
16264
16265         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16266         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16267                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16268                            error->power_well_driver);
16269         for_each_pipe(dev_priv, i) {
16270                 err_printf(m, "Pipe [%d]:\n", i);
16271                 err_printf(m, "  Power: %s\n",
16272                            onoff(error->pipe[i].power_domain_on));
16273                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16274                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16275
16276                 err_printf(m, "Plane [%d]:\n", i);
16277                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16278                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16279                 if (INTEL_INFO(dev)->gen <= 3) {
16280                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16281                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16282                 }
16283                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16284                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16285                 if (INTEL_INFO(dev)->gen >= 4) {
16286                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16287                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16288                 }
16289
16290                 err_printf(m, "Cursor [%d]:\n", i);
16291                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16292                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16293                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16294         }
16295
16296         for (i = 0; i < error->num_transcoders; i++) {
16297                 err_printf(m, "CPU transcoder: %s\n",
16298                            transcoder_name(error->transcoder[i].cpu_transcoder));
16299                 err_printf(m, "  Power: %s\n",
16300                            onoff(error->transcoder[i].power_domain_on));
16301                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16302                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16303                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16304                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16305                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16306                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16307                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16308         }
16309 }