drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  49                                 struct intel_crtc_config *pipe_config);
  50 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  51                                    struct intel_crtc_config *pipe_config);
  52
  53 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  54                           int x, int y, struct drm_framebuffer *old_fb);
  55
  56
  57 typedef struct {
  58         int     min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62         int     dot_limit;
  63         int     p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 typedef struct intel_limit intel_limit_t;
  67 struct intel_limit {
  68         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  69         intel_p2_t          p2;
  70 };
  71
  72 int
  73 intel_pch_rawclk(struct drm_device *dev)
  74 {
  75         struct drm_i915_private *dev_priv = dev->dev_private;
  76
  77         WARN_ON(!HAS_PCH_SPLIT(dev));
  78
  79         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  80 }
  81
  82 static inline u32 /* units of 100MHz */
  83 intel_fdi_link_freq(struct drm_device *dev)
  84 {
  85         if (IS_GEN5(dev)) {
  86                 struct drm_i915_private *dev_priv = dev->dev_private;
  87                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  88         } else
  89                 return 27;
  90 }
  91
  92 static const intel_limit_t intel_limits_i8xx_dac = {
  93         .dot = { .min = 25000, .max = 350000 },
  94         .vco = { .min = 930000, .max = 1400000 },
  95         .n = { .min = 3, .max = 16 },
  96         .m = { .min = 96, .max = 140 },
  97         .m1 = { .min = 18, .max = 26 },
  98         .m2 = { .min = 6, .max = 16 },
  99         .p = { .min = 4, .max = 128 },
 100         .p1 = { .min = 2, .max = 33 },
 101         .p2 = { .dot_limit = 165000,
 102                 .p2_slow = 4, .p2_fast = 2 },
 103 };
 104
 105 static const intel_limit_t intel_limits_i8xx_dvo = {
 106         .dot = { .min = 25000, .max = 350000 },
 107         .vco = { .min = 930000, .max = 1400000 },
 108         .n = { .min = 3, .max = 16 },
 109         .m = { .min = 96, .max = 140 },
 110         .m1 = { .min = 18, .max = 26 },
 111         .m2 = { .min = 6, .max = 16 },
 112         .p = { .min = 4, .max = 128 },
 113         .p1 = { .min = 2, .max = 33 },
 114         .p2 = { .dot_limit = 165000,
 115                 .p2_slow = 4, .p2_fast = 4 },
 116 };
 117
 118 static const intel_limit_t intel_limits_i8xx_lvds = {
 119         .dot = { .min = 25000, .max = 350000 },
 120         .vco = { .min = 930000, .max = 1400000 },
 121         .n = { .min = 3, .max = 16 },
 122         .m = { .min = 96, .max = 140 },
 123         .m1 = { .min = 18, .max = 26 },
 124         .m2 = { .min = 6, .max = 16 },
 125         .p = { .min = 4, .max = 128 },
 126         .p1 = { .min = 1, .max = 6 },
 127         .p2 = { .dot_limit = 165000,
 128                 .p2_slow = 14, .p2_fast = 7 },
 129 };
 130
 131 static const intel_limit_t intel_limits_i9xx_sdvo = {
 132         .dot = { .min = 20000, .max = 400000 },
 133         .vco = { .min = 1400000, .max = 2800000 },
 134         .n = { .min = 1, .max = 6 },
 135         .m = { .min = 70, .max = 120 },
 136         .m1 = { .min = 8, .max = 18 },
 137         .m2 = { .min = 3, .max = 7 },
 138         .p = { .min = 5, .max = 80 },
 139         .p1 = { .min = 1, .max = 8 },
 140         .p2 = { .dot_limit = 200000,
 141                 .p2_slow = 10, .p2_fast = 5 },
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_lvds = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 8, .max = 18 },
 150         .m2 = { .min = 3, .max = 7 },
 151         .p = { .min = 7, .max = 98 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 112000,
 154                 .p2_slow = 14, .p2_fast = 7 },
 155 };
 156
 157
 158 static const intel_limit_t intel_limits_g4x_sdvo = {
 159         .dot = { .min = 25000, .max = 270000 },
 160         .vco = { .min = 1750000, .max = 3500000},
 161         .n = { .min = 1, .max = 4 },
 162         .m = { .min = 104, .max = 138 },
 163         .m1 = { .min = 17, .max = 23 },
 164         .m2 = { .min = 5, .max = 11 },
 165         .p = { .min = 10, .max = 30 },
 166         .p1 = { .min = 1, .max = 3},
 167         .p2 = { .dot_limit = 270000,
 168                 .p2_slow = 10,
 169                 .p2_fast = 10
 170         },
 171 };
 172
 173 static const intel_limit_t intel_limits_g4x_hdmi = {
 174         .dot = { .min = 22000, .max = 400000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 16, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 5, .max = 80 },
 181         .p1 = { .min = 1, .max = 8},
 182         .p2 = { .dot_limit = 165000,
 183                 .p2_slow = 10, .p2_fast = 5 },
 184 };
 185
 186 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 187         .dot = { .min = 20000, .max = 115000 },
 188         .vco = { .min = 1750000, .max = 3500000 },
 189         .n = { .min = 1, .max = 3 },
 190         .m = { .min = 104, .max = 138 },
 191         .m1 = { .min = 17, .max = 23 },
 192         .m2 = { .min = 5, .max = 11 },
 193         .p = { .min = 28, .max = 112 },
 194         .p1 = { .min = 2, .max = 8 },
 195         .p2 = { .dot_limit = 0,
 196                 .p2_slow = 14, .p2_fast = 14
 197         },
 198 };
 199
 200 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 201         .dot = { .min = 80000, .max = 224000 },
 202         .vco = { .min = 1750000, .max = 3500000 },
 203         .n = { .min = 1, .max = 3 },
 204         .m = { .min = 104, .max = 138 },
 205         .m1 = { .min = 17, .max = 23 },
 206         .m2 = { .min = 5, .max = 11 },
 207         .p = { .min = 14, .max = 42 },
 208         .p1 = { .min = 2, .max = 6 },
 209         .p2 = { .dot_limit = 0,
 210                 .p2_slow = 7, .p2_fast = 7
 211         },
 212 };
 213
 214 static const intel_limit_t intel_limits_pineview_sdvo = {
 215         .dot = { .min = 20000, .max = 400000},
 216         .vco = { .min = 1700000, .max = 3500000 },
 217         /* Pineview's Ncounter is a ring counter */
 218         .n = { .min = 3, .max = 6 },
 219         .m = { .min = 2, .max = 256 },
 220         /* Pineview only has one combined m divider, which we treat as m2. */
 221         .m1 = { .min = 0, .max = 0 },
 222         .m2 = { .min = 0, .max = 254 },
 223         .p = { .min = 5, .max = 80 },
 224         .p1 = { .min = 1, .max = 8 },
 225         .p2 = { .dot_limit = 200000,
 226                 .p2_slow = 10, .p2_fast = 5 },
 227 };
 228
 229 static const intel_limit_t intel_limits_pineview_lvds = {
 230         .dot = { .min = 20000, .max = 400000 },
 231         .vco = { .min = 1700000, .max = 3500000 },
 232         .n = { .min = 3, .max = 6 },
 233         .m = { .min = 2, .max = 256 },
 234         .m1 = { .min = 0, .max = 0 },
 235         .m2 = { .min = 0, .max = 254 },
 236         .p = { .min = 7, .max = 112 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 112000,
 239                 .p2_slow = 14, .p2_fast = 14 },
 240 };
 241
 242 /* Ironlake / Sandybridge
 243  *
 244  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 245  * the range value for them is (actual_value - 2).
 246  */
 247 static const intel_limit_t intel_limits_ironlake_dac = {
 248         .dot = { .min = 25000, .max = 350000 },
 249         .vco = { .min = 1760000, .max = 3510000 },
 250         .n = { .min = 1, .max = 5 },
 251         .m = { .min = 79, .max = 127 },
 252         .m1 = { .min = 12, .max = 22 },
 253         .m2 = { .min = 5, .max = 9 },
 254         .p = { .min = 5, .max = 80 },
 255         .p1 = { .min = 1, .max = 8 },
 256         .p2 = { .dot_limit = 225000,
 257                 .p2_slow = 10, .p2_fast = 5 },
 258 };
 259
 260 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 261         .dot = { .min = 25000, .max = 350000 },
 262         .vco = { .min = 1760000, .max = 3510000 },
 263         .n = { .min = 1, .max = 3 },
 264         .m = { .min = 79, .max = 118 },
 265         .m1 = { .min = 12, .max = 22 },
 266         .m2 = { .min = 5, .max = 9 },
 267         .p = { .min = 28, .max = 112 },
 268         .p1 = { .min = 2, .max = 8 },
 269         .p2 = { .dot_limit = 225000,
 270                 .p2_slow = 14, .p2_fast = 14 },
 271 };
 272
 273 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 274         .dot = { .min = 25000, .max = 350000 },
 275         .vco = { .min = 1760000, .max = 3510000 },
 276         .n = { .min = 1, .max = 3 },
 277         .m = { .min = 79, .max = 127 },
 278         .m1 = { .min = 12, .max = 22 },
 279         .m2 = { .min = 5, .max = 9 },
 280         .p = { .min = 14, .max = 56 },
 281         .p1 = { .min = 2, .max = 8 },
 282         .p2 = { .dot_limit = 225000,
 283                 .p2_slow = 7, .p2_fast = 7 },
 284 };
 285
 286 /* LVDS 100mhz refclk limits. */
 287 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 2 },
 291         .m = { .min = 79, .max = 126 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 28, .max = 112 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298 };
 299
 300 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 3 },
 304         .m = { .min = 79, .max = 126 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 14, .max = 42 },
 308         .p1 = { .min = 2, .max = 6 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 7, .p2_fast = 7 },
 311 };
 312
 313 static const intel_limit_t intel_limits_vlv_dac = {
 314         .dot = { .min = 25000, .max = 270000 },
 315         .vco = { .min = 4000000, .max = 6000000 },
 316         .n = { .min = 1, .max = 7 },
 317         .m = { .min = 22, .max = 450 }, /* guess */
 318         .m1 = { .min = 2, .max = 3 },
 319         .m2 = { .min = 11, .max = 156 },
 320         .p = { .min = 10, .max = 30 },
 321         .p1 = { .min = 1, .max = 3 },
 322         .p2 = { .dot_limit = 270000,
 323                 .p2_slow = 2, .p2_fast = 20 },
 324 };
 325
 326 static const intel_limit_t intel_limits_vlv_hdmi = {
 327         .dot = { .min = 25000, .max = 270000 },
 328         .vco = { .min = 4000000, .max = 6000000 },
 329         .n = { .min = 1, .max = 7 },
 330         .m = { .min = 60, .max = 300 }, /* guess */
 331         .m1 = { .min = 2, .max = 3 },
 332         .m2 = { .min = 11, .max = 156 },
 333         .p = { .min = 10, .max = 30 },
 334         .p1 = { .min = 2, .max = 3 },
 335         .p2 = { .dot_limit = 270000,
 336                 .p2_slow = 2, .p2_fast = 20 },
 337 };
 338
 339 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 340                                                 int refclk)
 341 {
 342         struct drm_device *dev = crtc->dev;
 343         const intel_limit_t *limit;
 344
 345         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 346                 if (intel_is_dual_link_lvds(dev)) {
 347                         if (refclk == 100000)
 348                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 349                         else
 350                                 limit = &intel_limits_ironlake_dual_lvds;
 351                 } else {
 352                         if (refclk == 100000)
 353                                 limit = &intel_limits_ironlake_single_lvds_100m;
 354                         else
 355                                 limit = &intel_limits_ironlake_single_lvds;
 356                 }
 357         } else
 358                 limit = &intel_limits_ironlake_dac;
 359
 360         return limit;
 361 }
 362
 363 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 364 {
 365         struct drm_device *dev = crtc->dev;
 366         const intel_limit_t *limit;
 367
 368         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 369                 if (intel_is_dual_link_lvds(dev))
 370                         limit = &intel_limits_g4x_dual_channel_lvds;
 371                 else
 372                         limit = &intel_limits_g4x_single_channel_lvds;
 373         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 374                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 375                 limit = &intel_limits_g4x_hdmi;
 376         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 377                 limit = &intel_limits_g4x_sdvo;
 378         } else /* The option is for other outputs */
 379                 limit = &intel_limits_i9xx_sdvo;
 380
 381         return limit;
 382 }
 383
 384 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 385 {
 386         struct drm_device *dev = crtc->dev;
 387         const intel_limit_t *limit;
 388
 389         if (HAS_PCH_SPLIT(dev))
 390                 limit = intel_ironlake_limit(crtc, refclk);
 391         else if (IS_G4X(dev)) {
 392                 limit = intel_g4x_limit(crtc);
 393         } else if (IS_PINEVIEW(dev)) {
 394                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 395                         limit = &intel_limits_pineview_lvds;
 396                 else
 397                         limit = &intel_limits_pineview_sdvo;
 398         } else if (IS_VALLEYVIEW(dev)) {
 399                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 400                         limit = &intel_limits_vlv_dac;
 401                 else
 402                         limit = &intel_limits_vlv_hdmi;
 403         } else if (!IS_GEN2(dev)) {
 404                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 405                         limit = &intel_limits_i9xx_lvds;
 406                 else
 407                         limit = &intel_limits_i9xx_sdvo;
 408         } else {
 409                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 410                         limit = &intel_limits_i8xx_lvds;
 411                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 412                         limit = &intel_limits_i8xx_dvo;
 413                 else
 414                         limit = &intel_limits_i8xx_dac;
 415         }
 416         return limit;
 417 }
 418
 419 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 420 static void pineview_clock(int refclk, intel_clock_t *clock)
 421 {
 422         clock->m = clock->m2 + 2;
 423         clock->p = clock->p1 * clock->p2;
 424         clock->vco = refclk * clock->m / clock->n;
 425         clock->dot = clock->vco / clock->p;
 426 }
 427
 428 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 429 {
 430         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 431 }
 432
 433 static void i9xx_clock(int refclk, intel_clock_t *clock)
 434 {
 435         clock->m = i9xx_dpll_compute_m(clock);
 436         clock->p = clock->p1 * clock->p2;
 437         clock->vco = refclk * clock->m / (clock->n + 2);
 438         clock->dot = clock->vco / clock->p;
 439 }
 440
 441 /**
 442  * Returns whether any output on the specified pipe is of the specified type
 443  */
 444 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 445 {
 446         struct drm_device *dev = crtc->dev;
 447         struct intel_encoder *encoder;
 448
 449         for_each_encoder_on_crtc(dev, crtc, encoder)
 450                 if (encoder->type == type)
 451                         return true;
 452
 453         return false;
 454 }
 455
 456 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 457 /**
 458  * Returns whether the given set of divisors are valid for a given refclk with
 459  * the given connectors.
 460  */
 461
 462 static bool intel_PLL_is_valid(struct drm_device *dev,
 463                                const intel_limit_t *limit,
 464                                const intel_clock_t *clock)
 465 {
 466         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 467                 INTELPllInvalid("p1 out of range\n");
 468         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 469                 INTELPllInvalid("p out of range\n");
 470         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 471                 INTELPllInvalid("m2 out of range\n");
 472         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 473                 INTELPllInvalid("m1 out of range\n");
 474         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 475                 INTELPllInvalid("m1 <= m2\n");
 476         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 477                 INTELPllInvalid("m out of range\n");
 478         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 479                 INTELPllInvalid("n out of range\n");
 480         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 481                 INTELPllInvalid("vco out of range\n");
 482         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 483          * connector, etc., rather than just a single range.
 484          */
 485         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 486                 INTELPllInvalid("dot out of range\n");
 487
 488         return true;
 489 }
 490
 491 static bool
 492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 493                     int target, int refclk, intel_clock_t *match_clock,
 494                     intel_clock_t *best_clock)
 495 {
 496         struct drm_device *dev = crtc->dev;
 497         intel_clock_t clock;
 498         int err = target;
 499
 500         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 501                 /*
 502                  * For LVDS just rely on its current settings for dual-channel.
 503                  * We haven't figured out how to reliably set up different
 504                  * single/dual channel state, if we even can.
 505                  */
 506                 if (intel_is_dual_link_lvds(dev))
 507                         clock.p2 = limit->p2.p2_fast;
 508                 else
 509                         clock.p2 = limit->p2.p2_slow;
 510         } else {
 511                 if (target < limit->p2.dot_limit)
 512                         clock.p2 = limit->p2.p2_slow;
 513                 else
 514                         clock.p2 = limit->p2.p2_fast;
 515         }
 516
 517         memset(best_clock, 0, sizeof(*best_clock));
 518
 519         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 520              clock.m1++) {
 521                 for (clock.m2 = limit->m2.min;
 522                      clock.m2 <= limit->m2.max; clock.m2++) {
 523                         if (clock.m2 >= clock.m1)
 524                                 break;
 525                         for (clock.n = limit->n.min;
 526                              clock.n <= limit->n.max; clock.n++) {
 527                                 for (clock.p1 = limit->p1.min;
 528                                         clock.p1 <= limit->p1.max; clock.p1++) {
 529                                         int this_err;
 530
 531                                         i9xx_clock(refclk, &clock);
 532                                         if (!intel_PLL_is_valid(dev, limit,
 533                                                                 &clock))
 534                                                 continue;
 535                                         if (match_clock &&
 536                                             clock.p != match_clock->p)
 537                                                 continue;
 538
 539                                         this_err = abs(clock.dot - target);
 540                                         if (this_err < err) {
 541                                                 *best_clock = clock;
 542                                                 err = this_err;
 543                                         }
 544                                 }
 545                         }
 546                 }
 547         }
 548
 549         return (err != target);
 550 }
 551
 552 static bool
 553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 554                    int target, int refclk, intel_clock_t *match_clock,
 555                    intel_clock_t *best_clock)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         intel_clock_t clock;
 559         int err = target;
 560
 561         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 562                 /*
 563                  * For LVDS just rely on its current settings for dual-channel.
 564                  * We haven't figured out how to reliably set up different
 565                  * single/dual channel state, if we even can.
 566                  */
 567                 if (intel_is_dual_link_lvds(dev))
 568                         clock.p2 = limit->p2.p2_fast;
 569                 else
 570                         clock.p2 = limit->p2.p2_slow;
 571         } else {
 572                 if (target < limit->p2.dot_limit)
 573                         clock.p2 = limit->p2.p2_slow;
 574                 else
 575                         clock.p2 = limit->p2.p2_fast;
 576         }
 577
 578         memset(best_clock, 0, sizeof(*best_clock));
 579
 580         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 581              clock.m1++) {
 582                 for (clock.m2 = limit->m2.min;
 583                      clock.m2 <= limit->m2.max; clock.m2++) {
 584                         for (clock.n = limit->n.min;
 585                              clock.n <= limit->n.max; clock.n++) {
 586                                 for (clock.p1 = limit->p1.min;
 587                                         clock.p1 <= limit->p1.max; clock.p1++) {
 588                                         int this_err;
 589
 590                                         pineview_clock(refclk, &clock);
 591                                         if (!intel_PLL_is_valid(dev, limit,
 592                                                                 &clock))
 593                                                 continue;
 594                                         if (match_clock &&
 595                                             clock.p != match_clock->p)
 596                                                 continue;
 597
 598                                         this_err = abs(clock.dot - target);
 599                                         if (this_err < err) {
 600                                                 *best_clock = clock;
 601                                                 err = this_err;
 602                                         }
 603                                 }
 604                         }
 605                 }
 606         }
 607
 608         return (err != target);
 609 }
 610
 611 static bool
 612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 613                    int target, int refclk, intel_clock_t *match_clock,
 614                    intel_clock_t *best_clock)
 615 {
 616         struct drm_device *dev = crtc->dev;
 617         intel_clock_t clock;
 618         int max_n;
 619         bool found;
 620         /* approximately equals target * 0.00585 */
 621         int err_most = (target >> 8) + (target >> 9);
 622         found = false;
 623
 624         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 625                 if (intel_is_dual_link_lvds(dev))
 626                         clock.p2 = limit->p2.p2_fast;
 627                 else
 628                         clock.p2 = limit->p2.p2_slow;
 629         } else {
 630                 if (target < limit->p2.dot_limit)
 631                         clock.p2 = limit->p2.p2_slow;
 632                 else
 633                         clock.p2 = limit->p2.p2_fast;
 634         }
 635
 636         memset(best_clock, 0, sizeof(*best_clock));
 637         max_n = limit->n.max;
 638         /* based on hardware requirement, prefer smaller n to precision */
 639         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 640                 /* based on hardware requirement, prefere larger m1,m2 */
 641                 for (clock.m1 = limit->m1.max;
 642                      clock.m1 >= limit->m1.min; clock.m1--) {
 643                         for (clock.m2 = limit->m2.max;
 644                              clock.m2 >= limit->m2.min; clock.m2--) {
 645                                 for (clock.p1 = limit->p1.max;
 646                                      clock.p1 >= limit->p1.min; clock.p1--) {
 647                                         int this_err;
 648
 649                                         i9xx_clock(refclk, &clock);
 650                                         if (!intel_PLL_is_valid(dev, limit,
 651                                                                 &clock))
 652                                                 continue;
 653
 654                                         this_err = abs(clock.dot - target);
 655                                         if (this_err < err_most) {
 656                                                 *best_clock = clock;
 657                                                 err_most = this_err;
 658                                                 max_n = clock.n;
 659                                                 found = true;
 660                                         }
 661                                 }
 662                         }
 663                 }
 664         }
 665         return found;
 666 }
 667
 668 static bool
 669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                    int target, int refclk, intel_clock_t *match_clock,
 671                    intel_clock_t *best_clock)
 672 {
 673         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 674         u32 m, n, fastclk;
 675         u32 updrate, minupdate, p;
 676         unsigned long bestppm, ppm, absppm;
 677         int dotclk, flag;
 678
 679         flag = 0;
 680         dotclk = target * 1000;
 681         bestppm = 1000000;
 682         ppm = absppm = 0;
 683         fastclk = dotclk / (2*100);
 684         updrate = 0;
 685         minupdate = 19200;
 686         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 687         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 688
 689         /* based on hardware requirement, prefer smaller n to precision */
 690         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 691                 updrate = refclk / n;
 692                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 693                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 694                                 if (p2 > 10)
 695                                         p2 = p2 - 1;
 696                                 p = p1 * p2;
 697                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 698                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 699                                         m2 = (((2*(fastclk * p * n / m1 )) +
 700                                                refclk) / (2*refclk));
 701                                         m = m1 * m2;
 702                                         vco = updrate * m;
 703                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 704                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 705                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 706                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 707                                                         bestppm = 0;
 708                                                         flag = 1;
 709                                                 }
 710                                                 if (absppm < bestppm - 10) {
 711                                                         bestppm = absppm;
 712                                                         flag = 1;
 713                                                 }
 714                                                 if (flag) {
 715                                                         bestn = n;
 716                                                         bestm1 = m1;
 717                                                         bestm2 = m2;
 718                                                         bestp1 = p1;
 719                                                         bestp2 = p2;
 720                                                         flag = 0;
 721                                                 }
 722                                         }
 723                                 }
 724                         }
 725                 }
 726         }
 727         best_clock->n = bestn;
 728         best_clock->m1 = bestm1;
 729         best_clock->m2 = bestm2;
 730         best_clock->p1 = bestp1;
 731         best_clock->p2 = bestp2;
 732
 733         return true;
 734 }
 735
 736 bool intel_crtc_active(struct drm_crtc *crtc)
 737 {
 738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 739
 740         /* Be paranoid as we can arrive here with only partial
 741          * state retrieved from the hardware during setup.
 742          *
 743          * We can ditch the adjusted_mode.clock check as soon
 744          * as Haswell has gained clock readout/fastboot support.
 745          *
 746          * We can ditch the crtc->fb check as soon as we can
 747          * properly reconstruct framebuffers.
 748          */
 749         return intel_crtc->active && crtc->fb &&
 750                 intel_crtc->config.adjusted_mode.clock;
 751 }
 752
 753 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 754                                              enum pipe pipe)
 755 {
 756         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 758
 759         return intel_crtc->config.cpu_transcoder;
 760 }
 761
 762 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 763 {
 764         struct drm_i915_private *dev_priv = dev->dev_private;
 765         u32 frame, frame_reg = PIPEFRAME(pipe);
 766
 767         frame = I915_READ(frame_reg);
 768
 769         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 770                 DRM_DEBUG_KMS("vblank wait timed out\n");
 771 }
 772
 773 /**
 774  * intel_wait_for_vblank - wait for vblank on a given pipe
 775  * @dev: drm device
 776  * @pipe: pipe to wait for
 777  *
 778  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 779  * mode setting code.
 780  */
 781 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 782 {
 783         struct drm_i915_private *dev_priv = dev->dev_private;
 784         int pipestat_reg = PIPESTAT(pipe);
 785
 786         if (INTEL_INFO(dev)->gen >= 5) {
 787                 ironlake_wait_for_vblank(dev, pipe);
 788                 return;
 789         }
 790
 791         /* Clear existing vblank status. Note this will clear any other
 792          * sticky status fields as well.
 793          *
 794          * This races with i915_driver_irq_handler() with the result
 795          * that either function could miss a vblank event.  Here it is not
 796          * fatal, as we will either wait upon the next vblank interrupt or
 797          * timeout.  Generally speaking intel_wait_for_vblank() is only
 798          * called during modeset at which time the GPU should be idle and
 799          * should *not* be performing page flips and thus not waiting on
 800          * vblanks...
 801          * Currently, the result of us stealing a vblank from the irq
 802          * handler is that a single frame will be skipped during swapbuffers.
 803          */
 804         I915_WRITE(pipestat_reg,
 805                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 806
 807         /* Wait for vblank interrupt bit to set */
 808         if (wait_for(I915_READ(pipestat_reg) &
 809                      PIPE_VBLANK_INTERRUPT_STATUS,
 810                      50))
 811                 DRM_DEBUG_KMS("vblank wait timed out\n");
 812 }
 813
 814 /*
 815  * intel_wait_for_pipe_off - wait for pipe to turn off
 816  * @dev: drm device
 817  * @pipe: pipe to wait for
 818  *
 819  * After disabling a pipe, we can't wait for vblank in the usual way,
 820  * spinning on the vblank interrupt status bit, since we won't actually
 821  * see an interrupt when the pipe is disabled.
 822  *
 823  * On Gen4 and above:
 824  *   wait for the pipe register state bit to turn off
 825  *
 826  * Otherwise:
 827  *   wait for the display line value to settle (it usually
 828  *   ends up stopping at the start of the next frame).
 829  *
 830  */
 831 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 832 {
 833         struct drm_i915_private *dev_priv = dev->dev_private;
 834         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 835                                                                       pipe);
 836
 837         if (INTEL_INFO(dev)->gen >= 4) {
 838                 int reg = PIPECONF(cpu_transcoder);
 839
 840                 /* Wait for the Pipe State to go off */
 841                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 842                              100))
 843                         WARN(1, "pipe_off wait timed out\n");
 844         } else {
 845                 u32 last_line, line_mask;
 846                 int reg = PIPEDSL(pipe);
 847                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 848
 849                 if (IS_GEN2(dev))
 850                         line_mask = DSL_LINEMASK_GEN2;
 851                 else
 852                         line_mask = DSL_LINEMASK_GEN3;
 853
 854                 /* Wait for the display line to settle */
 855                 do {
 856                         last_line = I915_READ(reg) & line_mask;
 857                         mdelay(5);
 858                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 859                          time_after(timeout, jiffies));
 860                 if (time_after(jiffies, timeout))
 861                         WARN(1, "pipe_off wait timed out\n");
 862         }
 863 }
 864
 865 /*
 866  * ibx_digital_port_connected - is the specified port connected?
 867  * @dev_priv: i915 private structure
 868  * @port: the port to test
 869  *
 870  * Returns true if @port is connected, false otherwise.
 871  */
 872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 873                                 struct intel_digital_port *port)
 874 {
 875         u32 bit;
 876
 877         if (HAS_PCH_IBX(dev_priv->dev)) {
 878                 switch(port->port) {
 879                 case PORT_B:
 880                         bit = SDE_PORTB_HOTPLUG;
 881                         break;
 882                 case PORT_C:
 883                         bit = SDE_PORTC_HOTPLUG;
 884                         break;
 885                 case PORT_D:
 886                         bit = SDE_PORTD_HOTPLUG;
 887                         break;
 888                 default:
 889                         return true;
 890                 }
 891         } else {
 892                 switch(port->port) {
 893                 case PORT_B:
 894                         bit = SDE_PORTB_HOTPLUG_CPT;
 895                         break;
 896                 case PORT_C:
 897                         bit = SDE_PORTC_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_D:
 900                         bit = SDE_PORTD_HOTPLUG_CPT;
 901                         break;
 902                 default:
 903                         return true;
 904                 }
 905         }
 906
 907         return I915_READ(SDEISR) & bit;
 908 }
 909
 910 static const char *state_string(bool enabled)
 911 {
 912         return enabled ? "on" : "off";
 913 }
 914
 915 /* Only for pre-ILK configs */
 916 void assert_pll(struct drm_i915_private *dev_priv,
 917                 enum pipe pipe, bool state)
 918 {
 919         int reg;
 920         u32 val;
 921         bool cur_state;
 922
 923         reg = DPLL(pipe);
 924         val = I915_READ(reg);
 925         cur_state = !!(val & DPLL_VCO_ENABLE);
 926         WARN(cur_state != state,
 927              "PLL state assertion failure (expected %s, current %s)\n",
 928              state_string(state), state_string(cur_state));
 929 }
 930
 931 /* XXX: the dsi pll is shared between MIPI DSI ports */
 932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 933 {
 934         u32 val;
 935         bool cur_state;
 936
 937         mutex_lock(&dev_priv->dpio_lock);
 938         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 939         mutex_unlock(&dev_priv->dpio_lock);
 940
 941         cur_state = val & DSI_PLL_VCO_EN;
 942         WARN(cur_state != state,
 943              "DSI PLL state assertion failure (expected %s, current %s)\n",
 944              state_string(state), state_string(cur_state));
 945 }
 946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 948
 949 struct intel_shared_dpll *
 950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 951 {
 952         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 953
 954         if (crtc->config.shared_dpll < 0)
 955                 return NULL;
 956
 957         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 958 }
 959
 960 /* For ILK+ */
 961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 962                         struct intel_shared_dpll *pll,
 963                         bool state)
 964 {
 965         bool cur_state;
 966         struct intel_dpll_hw_state hw_state;
 967
 968         if (HAS_PCH_LPT(dev_priv->dev)) {
 969                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 970                 return;
 971         }
 972
 973         if (WARN (!pll,
 974                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 975                 return;
 976
 977         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 978         WARN(cur_state != state,
 979              "%s assertion failure (expected %s, current %s)\n",
 980              pll->name, state_string(state), state_string(cur_state));
 981 }
 982
 983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 984                           enum pipe pipe, bool state)
 985 {
 986         int reg;
 987         u32 val;
 988         bool cur_state;
 989         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 990                                                                       pipe);
 991
 992         if (HAS_DDI(dev_priv->dev)) {
 993                 /* DDI does not have a specific FDI_TX register */
 994                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 995                 val = I915_READ(reg);
 996                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 997         } else {
 998                 reg = FDI_TX_CTL(pipe);
 999                 val = I915_READ(reg);
1000                 cur_state = !!(val & FDI_TX_ENABLE);
1001         }
1002         WARN(cur_state != state,
1003              "FDI TX state assertion failure (expected %s, current %s)\n",
1004              state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010                           enum pipe pipe, bool state)
1011 {
1012         int reg;
1013         u32 val;
1014         bool cur_state;
1015
1016         reg = FDI_RX_CTL(pipe);
1017         val = I915_READ(reg);
1018         cur_state = !!(val & FDI_RX_ENABLE);
1019         WARN(cur_state != state,
1020              "FDI RX state assertion failure (expected %s, current %s)\n",
1021              state_string(state), state_string(cur_state));
1022 }
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027                                       enum pipe pipe)
1028 {
1029         int reg;
1030         u32 val;
1031
1032         /* ILK FDI PLL is always enabled */
1033         if (dev_priv->info->gen == 5)
1034                 return;
1035
1036         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037         if (HAS_DDI(dev_priv->dev))
1038                 return;
1039
1040         reg = FDI_TX_CTL(pipe);
1041         val = I915_READ(reg);
1042         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043 }
1044
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046                        enum pipe pipe, bool state)
1047 {
1048         int reg;
1049         u32 val;
1050         bool cur_state;
1051
1052         reg = FDI_RX_CTL(pipe);
1053         val = I915_READ(reg);
1054         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055         WARN(cur_state != state,
1056              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057              state_string(state), state_string(cur_state));
1058 }
1059
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061                                   enum pipe pipe)
1062 {
1063         int pp_reg, lvds_reg;
1064         u32 val;
1065         enum pipe panel_pipe = PIPE_A;
1066         bool locked = true;
1067
1068         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069                 pp_reg = PCH_PP_CONTROL;
1070                 lvds_reg = PCH_LVDS;
1071         } else {
1072                 pp_reg = PP_CONTROL;
1073                 lvds_reg = LVDS;
1074         }
1075
1076         val = I915_READ(pp_reg);
1077         if (!(val & PANEL_POWER_ON) ||
1078             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079                 locked = false;
1080
1081         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082                 panel_pipe = PIPE_B;
1083
1084         WARN(panel_pipe == pipe && locked,
1085              "panel assertion failure, pipe %c regs locked\n",
1086              pipe_name(pipe));
1087 }
1088
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090                           enum pipe pipe, bool state)
1091 {
1092         struct drm_device *dev = dev_priv->dev;
1093         bool cur_state;
1094
1095         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097         else if (IS_845G(dev) || IS_I865G(dev))
1098                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099         else
1100                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102         WARN(cur_state != state,
1103              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104              pipe_name(pipe), state_string(state), state_string(cur_state));
1105 }
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110                  enum pipe pipe, bool state)
1111 {
1112         int reg;
1113         u32 val;
1114         bool cur_state;
1115         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116                                                                       pipe);
1117
1118         /* if we need the pipe A quirk it must be always on */
1119         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120                 state = true;
1121
1122         if (!intel_display_power_enabled(dev_priv->dev,
1123                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1124                 cur_state = false;
1125         } else {
1126                 reg = PIPECONF(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & PIPECONF_ENABLE);
1129         }
1130
1131         WARN(cur_state != state,
1132              "pipe %c assertion failure (expected %s, current %s)\n",
1133              pipe_name(pipe), state_string(state), state_string(cur_state));
1134 }
1135
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137                          enum plane plane, bool state)
1138 {
1139         int reg;
1140         u32 val;
1141         bool cur_state;
1142
1143         reg = DSPCNTR(plane);
1144         val = I915_READ(reg);
1145         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146         WARN(cur_state != state,
1147              "plane %c assertion failure (expected %s, current %s)\n",
1148              plane_name(plane), state_string(state), state_string(cur_state));
1149 }
1150
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155                                    enum pipe pipe)
1156 {
1157         struct drm_device *dev = dev_priv->dev;
1158         int reg, i;
1159         u32 val;
1160         int cur_pipe;
1161
1162         /* Primary planes are fixed to pipes on gen4+ */
1163         if (INTEL_INFO(dev)->gen >= 4) {
1164                 reg = DSPCNTR(pipe);
1165                 val = I915_READ(reg);
1166                 WARN((val & DISPLAY_PLANE_ENABLE),
1167                      "plane %c assertion failure, should be disabled but not\n",
1168                      plane_name(pipe));
1169                 return;
1170         }
1171
1172         /* Need to check both planes against the pipe */
1173         for_each_pipe(i) {
1174                 reg = DSPCNTR(i);
1175                 val = I915_READ(reg);
1176                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177                         DISPPLANE_SEL_PIPE_SHIFT;
1178                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180                      plane_name(i), pipe_name(pipe));
1181         }
1182 }
1183
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185                                     enum pipe pipe)
1186 {
1187         struct drm_device *dev = dev_priv->dev;
1188         int reg, i;
1189         u32 val;
1190
1191         if (IS_VALLEYVIEW(dev)) {
1192                 for (i = 0; i < dev_priv->num_plane; i++) {
1193                         reg = SPCNTR(pipe, i);
1194                         val = I915_READ(reg);
1195                         WARN((val & SP_ENABLE),
1196                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197                              sprite_name(pipe, i), pipe_name(pipe));
1198                 }
1199         } else if (INTEL_INFO(dev)->gen >= 7) {
1200                 reg = SPRCTL(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & SPRITE_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         } else if (INTEL_INFO(dev)->gen >= 5) {
1206                 reg = DVSCNTR(pipe);
1207                 val = I915_READ(reg);
1208                 WARN((val & DVS_ENABLE),
1209                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210                      plane_name(pipe), pipe_name(pipe));
1211         }
1212 }
1213
1214 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215 {
1216         u32 val;
1217         bool enabled;
1218
1219         if (HAS_PCH_LPT(dev_priv->dev)) {
1220                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221                 return;
1222         }
1223
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void vlv_enable_pll(struct intel_crtc *crtc)
1364 {
1365         struct drm_device *dev = crtc->base.dev;
1366         struct drm_i915_private *dev_priv = dev->dev_private;
1367         int reg = DPLL(crtc->pipe);
1368         u32 dpll = crtc->config.dpll_hw_state.dpll;
1369
1370         assert_pipe_disabled(dev_priv, crtc->pipe);
1371
1372         /* No really, not for ILK+ */
1373         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1374
1375         /* PLL is protected by panel, make sure we can write it */
1376         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1377                 assert_panel_unlocked(dev_priv, crtc->pipe);
1378
1379         I915_WRITE(reg, dpll);
1380         POSTING_READ(reg);
1381         udelay(150);
1382
1383         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1384                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1385
1386         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1387         POSTING_READ(DPLL_MD(crtc->pipe));
1388
1389         /* We do this three times for luck */
1390         I915_WRITE(reg, dpll);
1391         POSTING_READ(reg);
1392         udelay(150); /* wait for warmup */
1393         I915_WRITE(reg, dpll);
1394         POSTING_READ(reg);
1395         udelay(150); /* wait for warmup */
1396         I915_WRITE(reg, dpll);
1397         POSTING_READ(reg);
1398         udelay(150); /* wait for warmup */
1399 }
1400
1401 static void i9xx_enable_pll(struct intel_crtc *crtc)
1402 {
1403         struct drm_device *dev = crtc->base.dev;
1404         struct drm_i915_private *dev_priv = dev->dev_private;
1405         int reg = DPLL(crtc->pipe);
1406         u32 dpll = crtc->config.dpll_hw_state.dpll;
1407
1408         assert_pipe_disabled(dev_priv, crtc->pipe);
1409
1410         /* No really, not for ILK+ */
1411         BUG_ON(dev_priv->info->gen >= 5);
1412
1413         /* PLL is protected by panel, make sure we can write it */
1414         if (IS_MOBILE(dev) && !IS_I830(dev))
1415                 assert_panel_unlocked(dev_priv, crtc->pipe);
1416
1417         I915_WRITE(reg, dpll);
1418
1419         /* Wait for the clocks to stabilize. */
1420         POSTING_READ(reg);
1421         udelay(150);
1422
1423         if (INTEL_INFO(dev)->gen >= 4) {
1424                 I915_WRITE(DPLL_MD(crtc->pipe),
1425                            crtc->config.dpll_hw_state.dpll_md);
1426         } else {
1427                 /* The pixel multiplier can only be updated once the
1428                  * DPLL is enabled and the clocks are stable.
1429                  *
1430                  * So write it again.
1431                  */
1432                 I915_WRITE(reg, dpll);
1433         }
1434
1435         /* We do this three times for luck */
1436         I915_WRITE(reg, dpll);
1437         POSTING_READ(reg);
1438         udelay(150); /* wait for warmup */
1439         I915_WRITE(reg, dpll);
1440         POSTING_READ(reg);
1441         udelay(150); /* wait for warmup */
1442         I915_WRITE(reg, dpll);
1443         POSTING_READ(reg);
1444         udelay(150); /* wait for warmup */
1445 }
1446
1447 /**
1448  * i9xx_disable_pll - disable a PLL
1449  * @dev_priv: i915 private structure
1450  * @pipe: pipe PLL to disable
1451  *
1452  * Disable the PLL for @pipe, making sure the pipe is off first.
1453  *
1454  * Note!  This is for pre-ILK only.
1455  */
1456 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1457 {
1458         /* Don't disable pipe A or pipe A PLLs if needed */
1459         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1460                 return;
1461
1462         /* Make sure the pipe isn't still relying on us */
1463         assert_pipe_disabled(dev_priv, pipe);
1464
1465         I915_WRITE(DPLL(pipe), 0);
1466         POSTING_READ(DPLL(pipe));
1467 }
1468
1469 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1470 {
1471         u32 port_mask;
1472
1473         if (!port)
1474                 port_mask = DPLL_PORTB_READY_MASK;
1475         else
1476                 port_mask = DPLL_PORTC_READY_MASK;
1477
1478         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1479                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1480                      'B' + port, I915_READ(DPLL(0)));
1481 }
1482
1483 /**
1484  * ironlake_enable_shared_dpll - enable PCH PLL
1485  * @dev_priv: i915 private structure
1486  * @pipe: pipe PLL to enable
1487  *
1488  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1489  * drives the transcoder clock.
1490  */
1491 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1492 {
1493         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1494         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1495
1496         /* PCH PLLs only available on ILK, SNB and IVB */
1497         BUG_ON(dev_priv->info->gen < 5);
1498         if (WARN_ON(pll == NULL))
1499                 return;
1500
1501         if (WARN_ON(pll->refcount == 0))
1502                 return;
1503
1504         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1505                       pll->name, pll->active, pll->on,
1506                       crtc->base.base.id);
1507
1508         if (pll->active++) {
1509                 WARN_ON(!pll->on);
1510                 assert_shared_dpll_enabled(dev_priv, pll);
1511                 return;
1512         }
1513         WARN_ON(pll->on);
1514
1515         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1516         pll->enable(dev_priv, pll);
1517         pll->on = true;
1518 }
1519
1520 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1521 {
1522         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1523         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1524
1525         /* PCH only available on ILK+ */
1526         BUG_ON(dev_priv->info->gen < 5);
1527         if (WARN_ON(pll == NULL))
1528                return;
1529
1530         if (WARN_ON(pll->refcount == 0))
1531                 return;
1532
1533         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1534                       pll->name, pll->active, pll->on,
1535                       crtc->base.base.id);
1536
1537         if (WARN_ON(pll->active == 0)) {
1538                 assert_shared_dpll_disabled(dev_priv, pll);
1539                 return;
1540         }
1541
1542         assert_shared_dpll_enabled(dev_priv, pll);
1543         WARN_ON(!pll->on);
1544         if (--pll->active)
1545                 return;
1546
1547         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1548         pll->disable(dev_priv, pll);
1549         pll->on = false;
1550 }
1551
1552 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1553                                            enum pipe pipe)
1554 {
1555         struct drm_device *dev = dev_priv->dev;
1556         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1558         uint32_t reg, val, pipeconf_val;
1559
1560         /* PCH only available on ILK+ */
1561         BUG_ON(dev_priv->info->gen < 5);
1562
1563         /* Make sure PCH DPLL is enabled */
1564         assert_shared_dpll_enabled(dev_priv,
1565                                    intel_crtc_to_shared_dpll(intel_crtc));
1566
1567         /* FDI must be feeding us bits for PCH ports */
1568         assert_fdi_tx_enabled(dev_priv, pipe);
1569         assert_fdi_rx_enabled(dev_priv, pipe);
1570
1571         if (HAS_PCH_CPT(dev)) {
1572                 /* Workaround: Set the timing override bit before enabling the
1573                  * pch transcoder. */
1574                 reg = TRANS_CHICKEN2(pipe);
1575                 val = I915_READ(reg);
1576                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1577                 I915_WRITE(reg, val);
1578         }
1579
1580         reg = PCH_TRANSCONF(pipe);
1581         val = I915_READ(reg);
1582         pipeconf_val = I915_READ(PIPECONF(pipe));
1583
1584         if (HAS_PCH_IBX(dev_priv->dev)) {
1585                 /*
1586                  * make the BPC in transcoder be consistent with
1587                  * that in pipeconf reg.
1588                  */
1589                 val &= ~PIPECONF_BPC_MASK;
1590                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1591         }
1592
1593         val &= ~TRANS_INTERLACE_MASK;
1594         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1595                 if (HAS_PCH_IBX(dev_priv->dev) &&
1596                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1597                         val |= TRANS_LEGACY_INTERLACED_ILK;
1598                 else
1599                         val |= TRANS_INTERLACED;
1600         else
1601                 val |= TRANS_PROGRESSIVE;
1602
1603         I915_WRITE(reg, val | TRANS_ENABLE);
1604         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1605                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1606 }
1607
1608 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1609                                       enum transcoder cpu_transcoder)
1610 {
1611         u32 val, pipeconf_val;
1612
1613         /* PCH only available on ILK+ */
1614         BUG_ON(dev_priv->info->gen < 5);
1615
1616         /* FDI must be feeding us bits for PCH ports */
1617         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1618         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1619
1620         /* Workaround: set timing override bit. */
1621         val = I915_READ(_TRANSA_CHICKEN2);
1622         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1623         I915_WRITE(_TRANSA_CHICKEN2, val);
1624
1625         val = TRANS_ENABLE;
1626         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1627
1628         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1629             PIPECONF_INTERLACED_ILK)
1630                 val |= TRANS_INTERLACED;
1631         else
1632                 val |= TRANS_PROGRESSIVE;
1633
1634         I915_WRITE(LPT_TRANSCONF, val);
1635         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1636                 DRM_ERROR("Failed to enable PCH transcoder\n");
1637 }
1638
1639 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1640                                             enum pipe pipe)
1641 {
1642         struct drm_device *dev = dev_priv->dev;
1643         uint32_t reg, val;
1644
1645         /* FDI relies on the transcoder */
1646         assert_fdi_tx_disabled(dev_priv, pipe);
1647         assert_fdi_rx_disabled(dev_priv, pipe);
1648
1649         /* Ports must be off as well */
1650         assert_pch_ports_disabled(dev_priv, pipe);
1651
1652         reg = PCH_TRANSCONF(pipe);
1653         val = I915_READ(reg);
1654         val &= ~TRANS_ENABLE;
1655         I915_WRITE(reg, val);
1656         /* wait for PCH transcoder off, transcoder state */
1657         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1658                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1659
1660         if (!HAS_PCH_IBX(dev)) {
1661                 /* Workaround: Clear the timing override chicken bit again. */
1662                 reg = TRANS_CHICKEN2(pipe);
1663                 val = I915_READ(reg);
1664                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1665                 I915_WRITE(reg, val);
1666         }
1667 }
1668
1669 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1670 {
1671         u32 val;
1672
1673         val = I915_READ(LPT_TRANSCONF);
1674         val &= ~TRANS_ENABLE;
1675         I915_WRITE(LPT_TRANSCONF, val);
1676         /* wait for PCH transcoder off, transcoder state */
1677         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1678                 DRM_ERROR("Failed to disable PCH transcoder\n");
1679
1680         /* Workaround: clear timing override bit. */
1681         val = I915_READ(_TRANSA_CHICKEN2);
1682         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1683         I915_WRITE(_TRANSA_CHICKEN2, val);
1684 }
1685
1686 /**
1687  * intel_enable_pipe - enable a pipe, asserting requirements
1688  * @dev_priv: i915 private structure
1689  * @pipe: pipe to enable
1690  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1691  *
1692  * Enable @pipe, making sure that various hardware specific requirements
1693  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1694  *
1695  * @pipe should be %PIPE_A or %PIPE_B.
1696  *
1697  * Will wait until the pipe is actually running (i.e. first vblank) before
1698  * returning.
1699  */
1700 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1701                               bool pch_port, bool dsi)
1702 {
1703         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1704                                                                       pipe);
1705         enum pipe pch_transcoder;
1706         int reg;
1707         u32 val;
1708
1709         assert_planes_disabled(dev_priv, pipe);
1710         assert_cursor_disabled(dev_priv, pipe);
1711         assert_sprites_disabled(dev_priv, pipe);
1712
1713         if (HAS_PCH_LPT(dev_priv->dev))
1714                 pch_transcoder = TRANSCODER_A;
1715         else
1716                 pch_transcoder = pipe;
1717
1718         /*
1719          * A pipe without a PLL won't actually be able to drive bits from
1720          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1721          * need the check.
1722          */
1723         if (!HAS_PCH_SPLIT(dev_priv->dev))
1724                 if (dsi)
1725                         assert_dsi_pll_enabled(dev_priv);
1726                 else
1727                         assert_pll_enabled(dev_priv, pipe);
1728         else {
1729                 if (pch_port) {
1730                         /* if driving the PCH, we need FDI enabled */
1731                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1732                         assert_fdi_tx_pll_enabled(dev_priv,
1733                                                   (enum pipe) cpu_transcoder);
1734                 }
1735                 /* FIXME: assert CPU port conditions for SNB+ */
1736         }
1737
1738         reg = PIPECONF(cpu_transcoder);
1739         val = I915_READ(reg);
1740         if (val & PIPECONF_ENABLE)
1741                 return;
1742
1743         I915_WRITE(reg, val | PIPECONF_ENABLE);
1744         intel_wait_for_vblank(dev_priv->dev, pipe);
1745 }
1746
1747 /**
1748  * intel_disable_pipe - disable a pipe, asserting requirements
1749  * @dev_priv: i915 private structure
1750  * @pipe: pipe to disable
1751  *
1752  * Disable @pipe, making sure that various hardware specific requirements
1753  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1754  *
1755  * @pipe should be %PIPE_A or %PIPE_B.
1756  *
1757  * Will wait until the pipe has shut down before returning.
1758  */
1759 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1760                                enum pipe pipe)
1761 {
1762         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763                                                                       pipe);
1764         int reg;
1765         u32 val;
1766
1767         /*
1768          * Make sure planes won't keep trying to pump pixels to us,
1769          * or we might hang the display.
1770          */
1771         assert_planes_disabled(dev_priv, pipe);
1772         assert_cursor_disabled(dev_priv, pipe);
1773         assert_sprites_disabled(dev_priv, pipe);
1774
1775         /* Don't disable pipe A or pipe A PLLs if needed */
1776         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1777                 return;
1778
1779         reg = PIPECONF(cpu_transcoder);
1780         val = I915_READ(reg);
1781         if ((val & PIPECONF_ENABLE) == 0)
1782                 return;
1783
1784         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1785         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1786 }
1787
1788 /*
1789  * Plane regs are double buffered, going from enabled->disabled needs a
1790  * trigger in order to latch.  The display address reg provides this.
1791  */
1792 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1793                                       enum plane plane)
1794 {
1795         if (dev_priv->info->gen >= 4)
1796                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1797         else
1798                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1799 }
1800
1801 /**
1802  * intel_enable_plane - enable a display plane on a given pipe
1803  * @dev_priv: i915 private structure
1804  * @plane: plane to enable
1805  * @pipe: pipe being fed
1806  *
1807  * Enable @plane on @pipe, making sure that @pipe is running first.
1808  */
1809 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1810                                enum plane plane, enum pipe pipe)
1811 {
1812         int reg;
1813         u32 val;
1814
1815         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1816         assert_pipe_enabled(dev_priv, pipe);
1817
1818         reg = DSPCNTR(plane);
1819         val = I915_READ(reg);
1820         if (val & DISPLAY_PLANE_ENABLE)
1821                 return;
1822
1823         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1824         intel_flush_display_plane(dev_priv, plane);
1825         intel_wait_for_vblank(dev_priv->dev, pipe);
1826 }
1827
1828 /**
1829  * intel_disable_plane - disable a display plane
1830  * @dev_priv: i915 private structure
1831  * @plane: plane to disable
1832  * @pipe: pipe consuming the data
1833  *
1834  * Disable @plane; should be an independent operation.
1835  */
1836 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1837                                 enum plane plane, enum pipe pipe)
1838 {
1839         int reg;
1840         u32 val;
1841
1842         reg = DSPCNTR(plane);
1843         val = I915_READ(reg);
1844         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1845                 return;
1846
1847         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1848         intel_flush_display_plane(dev_priv, plane);
1849         intel_wait_for_vblank(dev_priv->dev, pipe);
1850 }
1851
1852 static bool need_vtd_wa(struct drm_device *dev)
1853 {
1854 #ifdef CONFIG_INTEL_IOMMU
1855         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1856                 return true;
1857 #endif
1858         return false;
1859 }
1860
1861 int
1862 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1863                            struct drm_i915_gem_object *obj,
1864                            struct intel_ring_buffer *pipelined)
1865 {
1866         struct drm_i915_private *dev_priv = dev->dev_private;
1867         u32 alignment;
1868         int ret;
1869
1870         switch (obj->tiling_mode) {
1871         case I915_TILING_NONE:
1872                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1873                         alignment = 128 * 1024;
1874                 else if (INTEL_INFO(dev)->gen >= 4)
1875                         alignment = 4 * 1024;
1876                 else
1877                         alignment = 64 * 1024;
1878                 break;
1879         case I915_TILING_X:
1880                 /* pin() will align the object as required by fence */
1881                 alignment = 0;
1882                 break;
1883         case I915_TILING_Y:
1884                 /* Despite that we check this in framebuffer_init userspace can
1885                  * screw us over and change the tiling after the fact. Only
1886                  * pinned buffers can't change their tiling. */
1887                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1888                 return -EINVAL;
1889         default:
1890                 BUG();
1891         }
1892
1893         /* Note that the w/a also requires 64 PTE of padding following the
1894          * bo. We currently fill all unused PTE with the shadow page and so
1895          * we should always have valid PTE following the scanout preventing
1896          * the VT-d warning.
1897          */
1898         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1899                 alignment = 256 * 1024;
1900
1901         dev_priv->mm.interruptible = false;
1902         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1903         if (ret)
1904                 goto err_interruptible;
1905
1906         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1907          * fence, whereas 965+ only requires a fence if using
1908          * framebuffer compression.  For simplicity, we always install
1909          * a fence as the cost is not that onerous.
1910          */
1911         ret = i915_gem_object_get_fence(obj);
1912         if (ret)
1913                 goto err_unpin;
1914
1915         i915_gem_object_pin_fence(obj);
1916
1917         dev_priv->mm.interruptible = true;
1918         return 0;
1919
1920 err_unpin:
1921         i915_gem_object_unpin_from_display_plane(obj);
1922 err_interruptible:
1923         dev_priv->mm.interruptible = true;
1924         return ret;
1925 }
1926
1927 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1928 {
1929         i915_gem_object_unpin_fence(obj);
1930         i915_gem_object_unpin_from_display_plane(obj);
1931 }
1932
1933 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1934  * is assumed to be a power-of-two. */
1935 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1936                                              unsigned int tiling_mode,
1937                                              unsigned int cpp,
1938                                              unsigned int pitch)
1939 {
1940         if (tiling_mode != I915_TILING_NONE) {
1941                 unsigned int tile_rows, tiles;
1942
1943                 tile_rows = *y / 8;
1944                 *y %= 8;
1945
1946                 tiles = *x / (512/cpp);
1947                 *x %= 512/cpp;
1948
1949                 return tile_rows * pitch * 8 + tiles * 4096;
1950         } else {
1951                 unsigned int offset;
1952
1953                 offset = *y * pitch + *x * cpp;
1954                 *y = 0;
1955                 *x = (offset & 4095) / cpp;
1956                 return offset & -4096;
1957         }
1958 }
1959
1960 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1961                              int x, int y)
1962 {
1963         struct drm_device *dev = crtc->dev;
1964         struct drm_i915_private *dev_priv = dev->dev_private;
1965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966         struct intel_framebuffer *intel_fb;
1967         struct drm_i915_gem_object *obj;
1968         int plane = intel_crtc->plane;
1969         unsigned long linear_offset;
1970         u32 dspcntr;
1971         u32 reg;
1972
1973         switch (plane) {
1974         case 0:
1975         case 1:
1976                 break;
1977         default:
1978                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1979                 return -EINVAL;
1980         }
1981
1982         intel_fb = to_intel_framebuffer(fb);
1983         obj = intel_fb->obj;
1984
1985         reg = DSPCNTR(plane);
1986         dspcntr = I915_READ(reg);
1987         /* Mask out pixel format bits in case we change it */
1988         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1989         switch (fb->pixel_format) {
1990         case DRM_FORMAT_C8:
1991                 dspcntr |= DISPPLANE_8BPP;
1992                 break;
1993         case DRM_FORMAT_XRGB1555:
1994         case DRM_FORMAT_ARGB1555:
1995                 dspcntr |= DISPPLANE_BGRX555;
1996                 break;
1997         case DRM_FORMAT_RGB565:
1998                 dspcntr |= DISPPLANE_BGRX565;
1999                 break;
2000         case DRM_FORMAT_XRGB8888:
2001         case DRM_FORMAT_ARGB8888:
2002                 dspcntr |= DISPPLANE_BGRX888;
2003                 break;
2004         case DRM_FORMAT_XBGR8888:
2005         case DRM_FORMAT_ABGR8888:
2006                 dspcntr |= DISPPLANE_RGBX888;
2007                 break;
2008         case DRM_FORMAT_XRGB2101010:
2009         case DRM_FORMAT_ARGB2101010:
2010                 dspcntr |= DISPPLANE_BGRX101010;
2011                 break;
2012         case DRM_FORMAT_XBGR2101010:
2013         case DRM_FORMAT_ABGR2101010:
2014                 dspcntr |= DISPPLANE_RGBX101010;
2015                 break;
2016         default:
2017                 BUG();
2018         }
2019
2020         if (INTEL_INFO(dev)->gen >= 4) {
2021                 if (obj->tiling_mode != I915_TILING_NONE)
2022                         dspcntr |= DISPPLANE_TILED;
2023                 else
2024                         dspcntr &= ~DISPPLANE_TILED;
2025         }
2026
2027         if (IS_G4X(dev))
2028                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2029
2030         I915_WRITE(reg, dspcntr);
2031
2032         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2033
2034         if (INTEL_INFO(dev)->gen >= 4) {
2035                 intel_crtc->dspaddr_offset =
2036                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2037                                                        fb->bits_per_pixel / 8,
2038                                                        fb->pitches[0]);
2039                 linear_offset -= intel_crtc->dspaddr_offset;
2040         } else {
2041                 intel_crtc->dspaddr_offset = linear_offset;
2042         }
2043
2044         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2045                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2046                       fb->pitches[0]);
2047         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2048         if (INTEL_INFO(dev)->gen >= 4) {
2049                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2050                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2051                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2052                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2053         } else
2054                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2055         POSTING_READ(reg);
2056
2057         return 0;
2058 }
2059
2060 static int ironlake_update_plane(struct drm_crtc *crtc,
2061                                  struct drm_framebuffer *fb, int x, int y)
2062 {
2063         struct drm_device *dev = crtc->dev;
2064         struct drm_i915_private *dev_priv = dev->dev_private;
2065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2066         struct intel_framebuffer *intel_fb;
2067         struct drm_i915_gem_object *obj;
2068         int plane = intel_crtc->plane;
2069         unsigned long linear_offset;
2070         u32 dspcntr;
2071         u32 reg;
2072
2073         switch (plane) {
2074         case 0:
2075         case 1:
2076         case 2:
2077                 break;
2078         default:
2079                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2080                 return -EINVAL;
2081         }
2082
2083         intel_fb = to_intel_framebuffer(fb);
2084         obj = intel_fb->obj;
2085
2086         reg = DSPCNTR(plane);
2087         dspcntr = I915_READ(reg);
2088         /* Mask out pixel format bits in case we change it */
2089         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2090         switch (fb->pixel_format) {
2091         case DRM_FORMAT_C8:
2092                 dspcntr |= DISPPLANE_8BPP;
2093                 break;
2094         case DRM_FORMAT_RGB565:
2095                 dspcntr |= DISPPLANE_BGRX565;
2096                 break;
2097         case DRM_FORMAT_XRGB8888:
2098         case DRM_FORMAT_ARGB8888:
2099                 dspcntr |= DISPPLANE_BGRX888;
2100                 break;
2101         case DRM_FORMAT_XBGR8888:
2102         case DRM_FORMAT_ABGR8888:
2103                 dspcntr |= DISPPLANE_RGBX888;
2104                 break;
2105         case DRM_FORMAT_XRGB2101010:
2106         case DRM_FORMAT_ARGB2101010:
2107                 dspcntr |= DISPPLANE_BGRX101010;
2108                 break;
2109         case DRM_FORMAT_XBGR2101010:
2110         case DRM_FORMAT_ABGR2101010:
2111                 dspcntr |= DISPPLANE_RGBX101010;
2112                 break;
2113         default:
2114                 BUG();
2115         }
2116
2117         if (obj->tiling_mode != I915_TILING_NONE)
2118                 dspcntr |= DISPPLANE_TILED;
2119         else
2120                 dspcntr &= ~DISPPLANE_TILED;
2121
2122         if (IS_HASWELL(dev))
2123                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2124         else
2125                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2126
2127         I915_WRITE(reg, dspcntr);
2128
2129         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2130         intel_crtc->dspaddr_offset =
2131                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2132                                                fb->bits_per_pixel / 8,
2133                                                fb->pitches[0]);
2134         linear_offset -= intel_crtc->dspaddr_offset;
2135
2136         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2138                       fb->pitches[0]);
2139         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2140         I915_MODIFY_DISPBASE(DSPSURF(plane),
2141                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2142         if (IS_HASWELL(dev)) {
2143                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2144         } else {
2145                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2146                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2147         }
2148         POSTING_READ(reg);
2149
2150         return 0;
2151 }
2152
2153 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2154 static int
2155 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2156                            int x, int y, enum mode_set_atomic state)
2157 {
2158         struct drm_device *dev = crtc->dev;
2159         struct drm_i915_private *dev_priv = dev->dev_private;
2160
2161         if (dev_priv->display.disable_fbc)
2162                 dev_priv->display.disable_fbc(dev);
2163         intel_increase_pllclock(crtc);
2164
2165         return dev_priv->display.update_plane(crtc, fb, x, y);
2166 }
2167
2168 void intel_display_handle_reset(struct drm_device *dev)
2169 {
2170         struct drm_i915_private *dev_priv = dev->dev_private;
2171         struct drm_crtc *crtc;
2172
2173         /*
2174          * Flips in the rings have been nuked by the reset,
2175          * so complete all pending flips so that user space
2176          * will get its events and not get stuck.
2177          *
2178          * Also update the base address of all primary
2179          * planes to the the last fb to make sure we're
2180          * showing the correct fb after a reset.
2181          *
2182          * Need to make two loops over the crtcs so that we
2183          * don't try to grab a crtc mutex before the
2184          * pending_flip_queue really got woken up.
2185          */
2186
2187         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2188                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2189                 enum plane plane = intel_crtc->plane;
2190
2191                 intel_prepare_page_flip(dev, plane);
2192                 intel_finish_page_flip_plane(dev, plane);
2193         }
2194
2195         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2196                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2197
2198                 mutex_lock(&crtc->mutex);
2199                 if (intel_crtc->active)
2200                         dev_priv->display.update_plane(crtc, crtc->fb,
2201                                                        crtc->x, crtc->y);
2202                 mutex_unlock(&crtc->mutex);
2203         }
2204 }
2205
2206 static int
2207 intel_finish_fb(struct drm_framebuffer *old_fb)
2208 {
2209         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2210         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2211         bool was_interruptible = dev_priv->mm.interruptible;
2212         int ret;
2213
2214         /* Big Hammer, we also need to ensure that any pending
2215          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2216          * current scanout is retired before unpinning the old
2217          * framebuffer.
2218          *
2219          * This should only fail upon a hung GPU, in which case we
2220          * can safely continue.
2221          */
2222         dev_priv->mm.interruptible = false;
2223         ret = i915_gem_object_finish_gpu(obj);
2224         dev_priv->mm.interruptible = was_interruptible;
2225
2226         return ret;
2227 }
2228
2229 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2230 {
2231         struct drm_device *dev = crtc->dev;
2232         struct drm_i915_master_private *master_priv;
2233         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235         if (!dev->primary->master)
2236                 return;
2237
2238         master_priv = dev->primary->master->driver_priv;
2239         if (!master_priv->sarea_priv)
2240                 return;
2241
2242         switch (intel_crtc->pipe) {
2243         case 0:
2244                 master_priv->sarea_priv->pipeA_x = x;
2245                 master_priv->sarea_priv->pipeA_y = y;
2246                 break;
2247         case 1:
2248                 master_priv->sarea_priv->pipeB_x = x;
2249                 master_priv->sarea_priv->pipeB_y = y;
2250                 break;
2251         default:
2252                 break;
2253         }
2254 }
2255
2256 static int
2257 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2258                     struct drm_framebuffer *fb)
2259 {
2260         struct drm_device *dev = crtc->dev;
2261         struct drm_i915_private *dev_priv = dev->dev_private;
2262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2263         struct drm_framebuffer *old_fb;
2264         int ret;
2265
2266         /* no fb bound */
2267         if (!fb) {
2268                 DRM_ERROR("No FB bound\n");
2269                 return 0;
2270         }
2271
2272         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2273                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2274                           plane_name(intel_crtc->plane),
2275                           INTEL_INFO(dev)->num_pipes);
2276                 return -EINVAL;
2277         }
2278
2279         mutex_lock(&dev->struct_mutex);
2280         ret = intel_pin_and_fence_fb_obj(dev,
2281                                          to_intel_framebuffer(fb)->obj,
2282                                          NULL);
2283         if (ret != 0) {
2284                 mutex_unlock(&dev->struct_mutex);
2285                 DRM_ERROR("pin & fence failed\n");
2286                 return ret;
2287         }
2288
2289         /* Update pipe size and adjust fitter if needed */
2290         if (i915_fastboot) {
2291                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2292                            ((crtc->mode.hdisplay - 1) << 16) |
2293                            (crtc->mode.vdisplay - 1));
2294                 if (!intel_crtc->config.pch_pfit.size &&
2295                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2296                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2297                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2298                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2299                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2300                 }
2301         }
2302
2303         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2304         if (ret) {
2305                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2306                 mutex_unlock(&dev->struct_mutex);
2307                 DRM_ERROR("failed to update base address\n");
2308                 return ret;
2309         }
2310
2311         old_fb = crtc->fb;
2312         crtc->fb = fb;
2313         crtc->x = x;
2314         crtc->y = y;
2315
2316         if (old_fb) {
2317                 if (intel_crtc->active && old_fb != fb)
2318                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2319                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2320         }
2321
2322         intel_update_fbc(dev);
2323         intel_edp_psr_update(dev);
2324         mutex_unlock(&dev->struct_mutex);
2325
2326         intel_crtc_update_sarea_pos(crtc, x, y);
2327
2328         return 0;
2329 }
2330
2331 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332 {
2333         struct drm_device *dev = crtc->dev;
2334         struct drm_i915_private *dev_priv = dev->dev_private;
2335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336         int pipe = intel_crtc->pipe;
2337         u32 reg, temp;
2338
2339         /* enable normal train */
2340         reg = FDI_TX_CTL(pipe);
2341         temp = I915_READ(reg);
2342         if (IS_IVYBRIDGE(dev)) {
2343                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2345         } else {
2346                 temp &= ~FDI_LINK_TRAIN_NONE;
2347                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2348         }
2349         I915_WRITE(reg, temp);
2350
2351         reg = FDI_RX_CTL(pipe);
2352         temp = I915_READ(reg);
2353         if (HAS_PCH_CPT(dev)) {
2354                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356         } else {
2357                 temp &= ~FDI_LINK_TRAIN_NONE;
2358                 temp |= FDI_LINK_TRAIN_NONE;
2359         }
2360         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362         /* wait one idle pattern time */
2363         POSTING_READ(reg);
2364         udelay(1000);
2365
2366         /* IVB wants error correction enabled */
2367         if (IS_IVYBRIDGE(dev))
2368                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369                            FDI_FE_ERRC_ENABLE);
2370 }
2371
2372 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373 {
2374         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375 }
2376
2377 static void ivb_modeset_global_resources(struct drm_device *dev)
2378 {
2379         struct drm_i915_private *dev_priv = dev->dev_private;
2380         struct intel_crtc *pipe_B_crtc =
2381                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382         struct intel_crtc *pipe_C_crtc =
2383                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384         uint32_t temp;
2385
2386         /*
2387          * When everything is off disable fdi C so that we could enable fdi B
2388          * with all lanes. Note that we don't care about enabled pipes without
2389          * an enabled pch encoder.
2390          */
2391         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392             !pipe_has_enabled_pch(pipe_C_crtc)) {
2393                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396                 temp = I915_READ(SOUTH_CHICKEN1);
2397                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399                 I915_WRITE(SOUTH_CHICKEN1, temp);
2400         }
2401 }
2402
2403 /* The FDI link training functions for ILK/Ibexpeak. */
2404 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405 {
2406         struct drm_device *dev = crtc->dev;
2407         struct drm_i915_private *dev_priv = dev->dev_private;
2408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409         int pipe = intel_crtc->pipe;
2410         int plane = intel_crtc->plane;
2411         u32 reg, temp, tries;
2412
2413         /* FDI needs bits from pipe & plane first */
2414         assert_pipe_enabled(dev_priv, pipe);
2415         assert_plane_enabled(dev_priv, plane);
2416
2417         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418            for train result */
2419         reg = FDI_RX_IMR(pipe);
2420         temp = I915_READ(reg);
2421         temp &= ~FDI_RX_SYMBOL_LOCK;
2422         temp &= ~FDI_RX_BIT_LOCK;
2423         I915_WRITE(reg, temp);
2424         I915_READ(reg);
2425         udelay(150);
2426
2427         /* enable CPU FDI TX and PCH FDI RX */
2428         reg = FDI_TX_CTL(pipe);
2429         temp = I915_READ(reg);
2430         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2432         temp &= ~FDI_LINK_TRAIN_NONE;
2433         temp |= FDI_LINK_TRAIN_PATTERN_1;
2434         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2435
2436         reg = FDI_RX_CTL(pipe);
2437         temp = I915_READ(reg);
2438         temp &= ~FDI_LINK_TRAIN_NONE;
2439         temp |= FDI_LINK_TRAIN_PATTERN_1;
2440         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442         POSTING_READ(reg);
2443         udelay(150);
2444
2445         /* Ironlake workaround, enable clock pointer after FDI enable*/
2446         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448                    FDI_RX_PHASE_SYNC_POINTER_EN);
2449
2450         reg = FDI_RX_IIR(pipe);
2451         for (tries = 0; tries < 5; tries++) {
2452                 temp = I915_READ(reg);
2453                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455                 if ((temp & FDI_RX_BIT_LOCK)) {
2456                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2457                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2458                         break;
2459                 }
2460         }
2461         if (tries == 5)
2462                 DRM_ERROR("FDI train 1 fail!\n");
2463
2464         /* Train 2 */
2465         reg = FDI_TX_CTL(pipe);
2466         temp = I915_READ(reg);
2467         temp &= ~FDI_LINK_TRAIN_NONE;
2468         temp |= FDI_LINK_TRAIN_PATTERN_2;
2469         I915_WRITE(reg, temp);
2470
2471         reg = FDI_RX_CTL(pipe);
2472         temp = I915_READ(reg);
2473         temp &= ~FDI_LINK_TRAIN_NONE;
2474         temp |= FDI_LINK_TRAIN_PATTERN_2;
2475         I915_WRITE(reg, temp);
2476
2477         POSTING_READ(reg);
2478         udelay(150);
2479
2480         reg = FDI_RX_IIR(pipe);
2481         for (tries = 0; tries < 5; tries++) {
2482                 temp = I915_READ(reg);
2483                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485                 if (temp & FDI_RX_SYMBOL_LOCK) {
2486                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2487                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2488                         break;
2489                 }
2490         }
2491         if (tries == 5)
2492                 DRM_ERROR("FDI train 2 fail!\n");
2493
2494         DRM_DEBUG_KMS("FDI train done\n");
2495
2496 }
2497
2498 static const int snb_b_fdi_train_param[] = {
2499         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503 };
2504
2505 /* The FDI link training functions for SNB/Cougarpoint. */
2506 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507 {
2508         struct drm_device *dev = crtc->dev;
2509         struct drm_i915_private *dev_priv = dev->dev_private;
2510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511         int pipe = intel_crtc->pipe;
2512         u32 reg, temp, i, retry;
2513
2514         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515            for train result */
2516         reg = FDI_RX_IMR(pipe);
2517         temp = I915_READ(reg);
2518         temp &= ~FDI_RX_SYMBOL_LOCK;
2519         temp &= ~FDI_RX_BIT_LOCK;
2520         I915_WRITE(reg, temp);
2521
2522         POSTING_READ(reg);
2523         udelay(150);
2524
2525         /* enable CPU FDI TX and PCH FDI RX */
2526         reg = FDI_TX_CTL(pipe);
2527         temp = I915_READ(reg);
2528         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2530         temp &= ~FDI_LINK_TRAIN_NONE;
2531         temp |= FDI_LINK_TRAIN_PATTERN_1;
2532         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533         /* SNB-B */
2534         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2535         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2536
2537         I915_WRITE(FDI_RX_MISC(pipe),
2538                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
2540         reg = FDI_RX_CTL(pipe);
2541         temp = I915_READ(reg);
2542         if (HAS_PCH_CPT(dev)) {
2543                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545         } else {
2546                 temp &= ~FDI_LINK_TRAIN_NONE;
2547                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548         }
2549         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551         POSTING_READ(reg);
2552         udelay(150);
2553
2554         for (i = 0; i < 4; i++) {
2555                 reg = FDI_TX_CTL(pipe);
2556                 temp = I915_READ(reg);
2557                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558                 temp |= snb_b_fdi_train_param[i];
2559                 I915_WRITE(reg, temp);
2560
2561                 POSTING_READ(reg);
2562                 udelay(500);
2563
2564                 for (retry = 0; retry < 5; retry++) {
2565                         reg = FDI_RX_IIR(pipe);
2566                         temp = I915_READ(reg);
2567                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568                         if (temp & FDI_RX_BIT_LOCK) {
2569                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571                                 break;
2572                         }
2573                         udelay(50);
2574                 }
2575                 if (retry < 5)
2576                         break;
2577         }
2578         if (i == 4)
2579                 DRM_ERROR("FDI train 1 fail!\n");
2580
2581         /* Train 2 */
2582         reg = FDI_TX_CTL(pipe);
2583         temp = I915_READ(reg);
2584         temp &= ~FDI_LINK_TRAIN_NONE;
2585         temp |= FDI_LINK_TRAIN_PATTERN_2;
2586         if (IS_GEN6(dev)) {
2587                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588                 /* SNB-B */
2589                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590         }
2591         I915_WRITE(reg, temp);
2592
2593         reg = FDI_RX_CTL(pipe);
2594         temp = I915_READ(reg);
2595         if (HAS_PCH_CPT(dev)) {
2596                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598         } else {
2599                 temp &= ~FDI_LINK_TRAIN_NONE;
2600                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601         }
2602         I915_WRITE(reg, temp);
2603
2604         POSTING_READ(reg);
2605         udelay(150);
2606
2607         for (i = 0; i < 4; i++) {
2608                 reg = FDI_TX_CTL(pipe);
2609                 temp = I915_READ(reg);
2610                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611                 temp |= snb_b_fdi_train_param[i];
2612                 I915_WRITE(reg, temp);
2613
2614                 POSTING_READ(reg);
2615                 udelay(500);
2616
2617                 for (retry = 0; retry < 5; retry++) {
2618                         reg = FDI_RX_IIR(pipe);
2619                         temp = I915_READ(reg);
2620                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621                         if (temp & FDI_RX_SYMBOL_LOCK) {
2622                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624                                 break;
2625                         }
2626                         udelay(50);
2627                 }
2628                 if (retry < 5)
2629                         break;
2630         }
2631         if (i == 4)
2632                 DRM_ERROR("FDI train 2 fail!\n");
2633
2634         DRM_DEBUG_KMS("FDI train done.\n");
2635 }
2636
2637 /* Manual link training for Ivy Bridge A0 parts */
2638 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639 {
2640         struct drm_device *dev = crtc->dev;
2641         struct drm_i915_private *dev_priv = dev->dev_private;
2642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643         int pipe = intel_crtc->pipe;
2644         u32 reg, temp, i, j;
2645
2646         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647            for train result */
2648         reg = FDI_RX_IMR(pipe);
2649         temp = I915_READ(reg);
2650         temp &= ~FDI_RX_SYMBOL_LOCK;
2651         temp &= ~FDI_RX_BIT_LOCK;
2652         I915_WRITE(reg, temp);
2653
2654         POSTING_READ(reg);
2655         udelay(150);
2656
2657         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658                       I915_READ(FDI_RX_IIR(pipe)));
2659
2660         /* Try each vswing and preemphasis setting twice before moving on */
2661         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2662                 /* disable first in case we need to retry */
2663                 reg = FDI_TX_CTL(pipe);
2664                 temp = I915_READ(reg);
2665                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666                 temp &= ~FDI_TX_ENABLE;
2667                 I915_WRITE(reg, temp);
2668
2669                 reg = FDI_RX_CTL(pipe);
2670                 temp = I915_READ(reg);
2671                 temp &= ~FDI_LINK_TRAIN_AUTO;
2672                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673                 temp &= ~FDI_RX_ENABLE;
2674                 I915_WRITE(reg, temp);
2675
2676                 /* enable CPU FDI TX and PCH FDI RX */
2677                 reg = FDI_TX_CTL(pipe);
2678                 temp = I915_READ(reg);
2679                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2680                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2681                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2682                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2683                 temp |= snb_b_fdi_train_param[j/2];
2684                 temp |= FDI_COMPOSITE_SYNC;
2685                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2686
2687                 I915_WRITE(FDI_RX_MISC(pipe),
2688                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2689
2690                 reg = FDI_RX_CTL(pipe);
2691                 temp = I915_READ(reg);
2692                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2693                 temp |= FDI_COMPOSITE_SYNC;
2694                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2695
2696                 POSTING_READ(reg);
2697                 udelay(1); /* should be 0.5us */
2698
2699                 for (i = 0; i < 4; i++) {
2700                         reg = FDI_RX_IIR(pipe);
2701                         temp = I915_READ(reg);
2702                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2703
2704                         if (temp & FDI_RX_BIT_LOCK ||
2705                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2706                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2707                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2708                                               i);
2709                                 break;
2710                         }
2711                         udelay(1); /* should be 0.5us */
2712                 }
2713                 if (i == 4) {
2714                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2715                         continue;
2716                 }
2717
2718                 /* Train 2 */
2719                 reg = FDI_TX_CTL(pipe);
2720                 temp = I915_READ(reg);
2721                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2722                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2723                 I915_WRITE(reg, temp);
2724
2725                 reg = FDI_RX_CTL(pipe);
2726                 temp = I915_READ(reg);
2727                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2728                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2729                 I915_WRITE(reg, temp);
2730
2731                 POSTING_READ(reg);
2732                 udelay(2); /* should be 1.5us */
2733
2734                 for (i = 0; i < 4; i++) {
2735                         reg = FDI_RX_IIR(pipe);
2736                         temp = I915_READ(reg);
2737                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2738
2739                         if (temp & FDI_RX_SYMBOL_LOCK ||
2740                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2741                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2742                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2743                                               i);
2744                                 goto train_done;
2745                         }
2746                         udelay(2); /* should be 1.5us */
2747                 }
2748                 if (i == 4)
2749                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2750         }
2751
2752 train_done:
2753         DRM_DEBUG_KMS("FDI train done.\n");
2754 }
2755
2756 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2757 {
2758         struct drm_device *dev = intel_crtc->base.dev;
2759         struct drm_i915_private *dev_priv = dev->dev_private;
2760         int pipe = intel_crtc->pipe;
2761         u32 reg, temp;
2762
2763
2764         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2765         reg = FDI_RX_CTL(pipe);
2766         temp = I915_READ(reg);
2767         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2768         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2769         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2770         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2771
2772         POSTING_READ(reg);
2773         udelay(200);
2774
2775         /* Switch from Rawclk to PCDclk */
2776         temp = I915_READ(reg);
2777         I915_WRITE(reg, temp | FDI_PCDCLK);
2778
2779         POSTING_READ(reg);
2780         udelay(200);
2781
2782         /* Enable CPU FDI TX PLL, always on for Ironlake */
2783         reg = FDI_TX_CTL(pipe);
2784         temp = I915_READ(reg);
2785         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2786                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2787
2788                 POSTING_READ(reg);
2789                 udelay(100);
2790         }
2791 }
2792
2793 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2794 {
2795         struct drm_device *dev = intel_crtc->base.dev;
2796         struct drm_i915_private *dev_priv = dev->dev_private;
2797         int pipe = intel_crtc->pipe;
2798         u32 reg, temp;
2799
2800         /* Switch from PCDclk to Rawclk */
2801         reg = FDI_RX_CTL(pipe);
2802         temp = I915_READ(reg);
2803         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2804
2805         /* Disable CPU FDI TX PLL */
2806         reg = FDI_TX_CTL(pipe);
2807         temp = I915_READ(reg);
2808         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2809
2810         POSTING_READ(reg);
2811         udelay(100);
2812
2813         reg = FDI_RX_CTL(pipe);
2814         temp = I915_READ(reg);
2815         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2816
2817         /* Wait for the clocks to turn off. */
2818         POSTING_READ(reg);
2819         udelay(100);
2820 }
2821
2822 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2823 {
2824         struct drm_device *dev = crtc->dev;
2825         struct drm_i915_private *dev_priv = dev->dev_private;
2826         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2827         int pipe = intel_crtc->pipe;
2828         u32 reg, temp;
2829
2830         /* disable CPU FDI tx and PCH FDI rx */
2831         reg = FDI_TX_CTL(pipe);
2832         temp = I915_READ(reg);
2833         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2834         POSTING_READ(reg);
2835
2836         reg = FDI_RX_CTL(pipe);
2837         temp = I915_READ(reg);
2838         temp &= ~(0x7 << 16);
2839         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2840         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2841
2842         POSTING_READ(reg);
2843         udelay(100);
2844
2845         /* Ironlake workaround, disable clock pointer after downing FDI */
2846         if (HAS_PCH_IBX(dev)) {
2847                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2848         }
2849
2850         /* still set train pattern 1 */
2851         reg = FDI_TX_CTL(pipe);
2852         temp = I915_READ(reg);
2853         temp &= ~FDI_LINK_TRAIN_NONE;
2854         temp |= FDI_LINK_TRAIN_PATTERN_1;
2855         I915_WRITE(reg, temp);
2856
2857         reg = FDI_RX_CTL(pipe);
2858         temp = I915_READ(reg);
2859         if (HAS_PCH_CPT(dev)) {
2860                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2861                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2862         } else {
2863                 temp &= ~FDI_LINK_TRAIN_NONE;
2864                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2865         }
2866         /* BPC in FDI rx is consistent with that in PIPECONF */
2867         temp &= ~(0x07 << 16);
2868         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2869         I915_WRITE(reg, temp);
2870
2871         POSTING_READ(reg);
2872         udelay(100);
2873 }
2874
2875 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2876 {
2877         struct drm_device *dev = crtc->dev;
2878         struct drm_i915_private *dev_priv = dev->dev_private;
2879         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880         unsigned long flags;
2881         bool pending;
2882
2883         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2884             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2885                 return false;
2886
2887         spin_lock_irqsave(&dev->event_lock, flags);
2888         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2889         spin_unlock_irqrestore(&dev->event_lock, flags);
2890
2891         return pending;
2892 }
2893
2894 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2895 {
2896         struct drm_device *dev = crtc->dev;
2897         struct drm_i915_private *dev_priv = dev->dev_private;
2898
2899         if (crtc->fb == NULL)
2900                 return;
2901
2902         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2903
2904         wait_event(dev_priv->pending_flip_queue,
2905                    !intel_crtc_has_pending_flip(crtc));
2906
2907         mutex_lock(&dev->struct_mutex);
2908         intel_finish_fb(crtc->fb);
2909         mutex_unlock(&dev->struct_mutex);
2910 }
2911
2912 /* Program iCLKIP clock to the desired frequency */
2913 static void lpt_program_iclkip(struct drm_crtc *crtc)
2914 {
2915         struct drm_device *dev = crtc->dev;
2916         struct drm_i915_private *dev_priv = dev->dev_private;
2917         int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
2918         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2919         u32 temp;
2920
2921         mutex_lock(&dev_priv->dpio_lock);
2922
2923         /* It is necessary to ungate the pixclk gate prior to programming
2924          * the divisors, and gate it back when it is done.
2925          */
2926         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2927
2928         /* Disable SSCCTL */
2929         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2930                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2931                                 SBI_SSCCTL_DISABLE,
2932                         SBI_ICLK);
2933
2934         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2935         if (clock == 20000) {
2936                 auxdiv = 1;
2937                 divsel = 0x41;
2938                 phaseinc = 0x20;
2939         } else {
2940                 /* The iCLK virtual clock root frequency is in MHz,
2941                  * but the adjusted_mode->clock in in KHz. To get the divisors,
2942                  * it is necessary to divide one by another, so we
2943                  * convert the virtual clock precision to KHz here for higher
2944                  * precision.
2945                  */
2946                 u32 iclk_virtual_root_freq = 172800 * 1000;
2947                 u32 iclk_pi_range = 64;
2948                 u32 desired_divisor, msb_divisor_value, pi_value;
2949
2950                 desired_divisor = (iclk_virtual_root_freq / clock);
2951                 msb_divisor_value = desired_divisor / iclk_pi_range;
2952                 pi_value = desired_divisor % iclk_pi_range;
2953
2954                 auxdiv = 0;
2955                 divsel = msb_divisor_value - 2;
2956                 phaseinc = pi_value;
2957         }
2958
2959         /* This should not happen with any sane values */
2960         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2961                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2962         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2963                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2964
2965         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2966                         clock,
2967                         auxdiv,
2968                         divsel,
2969                         phasedir,
2970                         phaseinc);
2971
2972         /* Program SSCDIVINTPHASE6 */
2973         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2974         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2975         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2976         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2977         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2978         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2979         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2980         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2981
2982         /* Program SSCAUXDIV */
2983         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2984         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2985         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2986         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2987
2988         /* Enable modulator and associated divider */
2989         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2990         temp &= ~SBI_SSCCTL_DISABLE;
2991         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2992
2993         /* Wait for initialization time */
2994         udelay(24);
2995
2996         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2997
2998         mutex_unlock(&dev_priv->dpio_lock);
2999 }
3000
3001 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3002                                                 enum pipe pch_transcoder)
3003 {
3004         struct drm_device *dev = crtc->base.dev;
3005         struct drm_i915_private *dev_priv = dev->dev_private;
3006         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3007
3008         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3009                    I915_READ(HTOTAL(cpu_transcoder)));
3010         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3011                    I915_READ(HBLANK(cpu_transcoder)));
3012         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3013                    I915_READ(HSYNC(cpu_transcoder)));
3014
3015         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3016                    I915_READ(VTOTAL(cpu_transcoder)));
3017         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3018                    I915_READ(VBLANK(cpu_transcoder)));
3019         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3020                    I915_READ(VSYNC(cpu_transcoder)));
3021         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3022                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3023 }
3024
3025 /*
3026  * Enable PCH resources required for PCH ports:
3027  *   - PCH PLLs
3028  *   - FDI training & RX/TX
3029  *   - update transcoder timings
3030  *   - DP transcoding bits
3031  *   - transcoder
3032  */
3033 static void ironlake_pch_enable(struct drm_crtc *crtc)
3034 {
3035         struct drm_device *dev = crtc->dev;
3036         struct drm_i915_private *dev_priv = dev->dev_private;
3037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038         int pipe = intel_crtc->pipe;
3039         u32 reg, temp;
3040
3041         assert_pch_transcoder_disabled(dev_priv, pipe);
3042
3043         /* Write the TU size bits before fdi link training, so that error
3044          * detection works. */
3045         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3046                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3047
3048         /* For PCH output, training FDI link */
3049         dev_priv->display.fdi_link_train(crtc);
3050
3051         /* We need to program the right clock selection before writing the pixel
3052          * mutliplier into the DPLL. */
3053         if (HAS_PCH_CPT(dev)) {
3054                 u32 sel;
3055
3056                 temp = I915_READ(PCH_DPLL_SEL);
3057                 temp |= TRANS_DPLL_ENABLE(pipe);
3058                 sel = TRANS_DPLLB_SEL(pipe);
3059                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3060                         temp |= sel;
3061                 else
3062                         temp &= ~sel;
3063                 I915_WRITE(PCH_DPLL_SEL, temp);
3064         }
3065
3066         /* XXX: pch pll's can be enabled any time before we enable the PCH
3067          * transcoder, and we actually should do this to not upset any PCH
3068          * transcoder that already use the clock when we share it.
3069          *
3070          * Note that enable_shared_dpll tries to do the right thing, but
3071          * get_shared_dpll unconditionally resets the pll - we need that to have
3072          * the right LVDS enable sequence. */
3073         ironlake_enable_shared_dpll(intel_crtc);
3074
3075         /* set transcoder timing, panel must allow it */
3076         assert_panel_unlocked(dev_priv, pipe);
3077         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3078
3079         intel_fdi_normal_train(crtc);
3080
3081         /* For PCH DP, enable TRANS_DP_CTL */
3082         if (HAS_PCH_CPT(dev) &&
3083             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3084              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3085                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3086                 reg = TRANS_DP_CTL(pipe);
3087                 temp = I915_READ(reg);
3088                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3089                           TRANS_DP_SYNC_MASK |
3090                           TRANS_DP_BPC_MASK);
3091                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3092                          TRANS_DP_ENH_FRAMING);
3093                 temp |= bpc << 9; /* same format but at 11:9 */
3094
3095                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3096                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3097                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3098                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3099
3100                 switch (intel_trans_dp_port_sel(crtc)) {
3101                 case PCH_DP_B:
3102                         temp |= TRANS_DP_PORT_SEL_B;
3103                         break;
3104                 case PCH_DP_C:
3105                         temp |= TRANS_DP_PORT_SEL_C;
3106                         break;
3107                 case PCH_DP_D:
3108                         temp |= TRANS_DP_PORT_SEL_D;
3109                         break;
3110                 default:
3111                         BUG();
3112                 }
3113
3114                 I915_WRITE(reg, temp);
3115         }
3116
3117         ironlake_enable_pch_transcoder(dev_priv, pipe);
3118 }
3119
3120 static void lpt_pch_enable(struct drm_crtc *crtc)
3121 {
3122         struct drm_device *dev = crtc->dev;
3123         struct drm_i915_private *dev_priv = dev->dev_private;
3124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3125         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3126
3127         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3128
3129         lpt_program_iclkip(crtc);
3130
3131         /* Set transcoder timing. */
3132         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3133
3134         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3135 }
3136
3137 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3138 {
3139         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3140
3141         if (pll == NULL)
3142                 return;
3143
3144         if (pll->refcount == 0) {
3145                 WARN(1, "bad %s refcount\n", pll->name);
3146                 return;
3147         }
3148
3149         if (--pll->refcount == 0) {
3150                 WARN_ON(pll->on);
3151                 WARN_ON(pll->active);
3152         }
3153
3154         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3155 }
3156
3157 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3158 {
3159         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3160         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3161         enum intel_dpll_id i;
3162
3163         if (pll) {
3164                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3165                               crtc->base.base.id, pll->name);
3166                 intel_put_shared_dpll(crtc);
3167         }
3168
3169         if (HAS_PCH_IBX(dev_priv->dev)) {
3170                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3171                 i = (enum intel_dpll_id) crtc->pipe;
3172                 pll = &dev_priv->shared_dplls[i];
3173
3174                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3175                               crtc->base.base.id, pll->name);
3176
3177                 goto found;
3178         }
3179
3180         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3181                 pll = &dev_priv->shared_dplls[i];
3182
3183                 /* Only want to check enabled timings first */
3184                 if (pll->refcount == 0)
3185                         continue;
3186
3187                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3188                            sizeof(pll->hw_state)) == 0) {
3189                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3190                                       crtc->base.base.id,
3191                                       pll->name, pll->refcount, pll->active);
3192
3193                         goto found;
3194                 }
3195         }
3196
3197         /* Ok no matching timings, maybe there's a free one? */
3198         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3199                 pll = &dev_priv->shared_dplls[i];
3200                 if (pll->refcount == 0) {
3201                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3202                                       crtc->base.base.id, pll->name);
3203                         goto found;
3204                 }
3205         }
3206
3207         return NULL;
3208
3209 found:
3210         crtc->config.shared_dpll = i;
3211         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3212                          pipe_name(crtc->pipe));
3213
3214         if (pll->active == 0) {
3215                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3216                        sizeof(pll->hw_state));
3217
3218                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3219                 WARN_ON(pll->on);
3220                 assert_shared_dpll_disabled(dev_priv, pll);
3221
3222                 pll->mode_set(dev_priv, pll);
3223         }
3224         pll->refcount++;
3225
3226         return pll;
3227 }
3228
3229 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3230 {
3231         struct drm_i915_private *dev_priv = dev->dev_private;
3232         int dslreg = PIPEDSL(pipe);
3233         u32 temp;
3234
3235         temp = I915_READ(dslreg);
3236         udelay(500);
3237         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3238                 if (wait_for(I915_READ(dslreg) != temp, 5))
3239                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3240         }
3241 }
3242
3243 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3244 {
3245         struct drm_device *dev = crtc->base.dev;
3246         struct drm_i915_private *dev_priv = dev->dev_private;
3247         int pipe = crtc->pipe;
3248
3249         if (crtc->config.pch_pfit.size) {
3250                 /* Force use of hard-coded filter coefficients
3251                  * as some pre-programmed values are broken,
3252                  * e.g. x201.
3253                  */
3254                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3255                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3256                                                  PF_PIPE_SEL_IVB(pipe));
3257                 else
3258                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3259                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3260                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3261         }
3262 }
3263
3264 static void intel_enable_planes(struct drm_crtc *crtc)
3265 {
3266         struct drm_device *dev = crtc->dev;
3267         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3268         struct intel_plane *intel_plane;
3269
3270         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3271                 if (intel_plane->pipe == pipe)
3272                         intel_plane_restore(&intel_plane->base);
3273 }
3274
3275 static void intel_disable_planes(struct drm_crtc *crtc)
3276 {
3277         struct drm_device *dev = crtc->dev;
3278         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3279         struct intel_plane *intel_plane;
3280
3281         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3282                 if (intel_plane->pipe == pipe)
3283                         intel_plane_disable(&intel_plane->base);
3284 }
3285
3286 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3287 {
3288         struct drm_device *dev = crtc->dev;
3289         struct drm_i915_private *dev_priv = dev->dev_private;
3290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3291         struct intel_encoder *encoder;
3292         int pipe = intel_crtc->pipe;
3293         int plane = intel_crtc->plane;
3294
3295         WARN_ON(!crtc->enabled);
3296
3297         if (intel_crtc->active)
3298                 return;
3299
3300         intel_crtc->active = true;
3301
3302         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3303         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3304
3305         for_each_encoder_on_crtc(dev, crtc, encoder)
3306                 if (encoder->pre_enable)
3307                         encoder->pre_enable(encoder);
3308
3309         if (intel_crtc->config.has_pch_encoder) {
3310                 /* Note: FDI PLL enabling _must_ be done before we enable the
3311                  * cpu pipes, hence this is separate from all the other fdi/pch
3312                  * enabling. */
3313                 ironlake_fdi_pll_enable(intel_crtc);
3314         } else {
3315                 assert_fdi_tx_disabled(dev_priv, pipe);
3316                 assert_fdi_rx_disabled(dev_priv, pipe);
3317         }
3318
3319         ironlake_pfit_enable(intel_crtc);
3320
3321         /*
3322          * On ILK+ LUT must be loaded before the pipe is running but with
3323          * clocks enabled
3324          */
3325         intel_crtc_load_lut(crtc);
3326
3327         intel_update_watermarks(crtc);
3328         intel_enable_pipe(dev_priv, pipe,
3329                           intel_crtc->config.has_pch_encoder, false);
3330         intel_enable_plane(dev_priv, plane, pipe);
3331         intel_enable_planes(crtc);
3332         intel_crtc_update_cursor(crtc, true);
3333
3334         if (intel_crtc->config.has_pch_encoder)
3335                 ironlake_pch_enable(crtc);
3336
3337         mutex_lock(&dev->struct_mutex);
3338         intel_update_fbc(dev);
3339         mutex_unlock(&dev->struct_mutex);
3340
3341         for_each_encoder_on_crtc(dev, crtc, encoder)
3342                 encoder->enable(encoder);
3343
3344         if (HAS_PCH_CPT(dev))
3345                 cpt_verify_modeset(dev, intel_crtc->pipe);
3346
3347         /*
3348          * There seems to be a race in PCH platform hw (at least on some
3349          * outputs) where an enabled pipe still completes any pageflip right
3350          * away (as if the pipe is off) instead of waiting for vblank. As soon
3351          * as the first vblank happend, everything works as expected. Hence just
3352          * wait for one vblank before returning to avoid strange things
3353          * happening.
3354          */
3355         intel_wait_for_vblank(dev, intel_crtc->pipe);
3356 }
3357
3358 /* IPS only exists on ULT machines and is tied to pipe A. */
3359 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3360 {
3361         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3362 }
3363
3364 static void hsw_enable_ips(struct intel_crtc *crtc)
3365 {
3366         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3367
3368         if (!crtc->config.ips_enabled)
3369                 return;
3370
3371         /* We can only enable IPS after we enable a plane and wait for a vblank.
3372          * We guarantee that the plane is enabled by calling intel_enable_ips
3373          * only after intel_enable_plane. And intel_enable_plane already waits
3374          * for a vblank, so all we need to do here is to enable the IPS bit. */
3375         assert_plane_enabled(dev_priv, crtc->plane);
3376         I915_WRITE(IPS_CTL, IPS_ENABLE);
3377 }
3378
3379 static void hsw_disable_ips(struct intel_crtc *crtc)
3380 {
3381         struct drm_device *dev = crtc->base.dev;
3382         struct drm_i915_private *dev_priv = dev->dev_private;
3383
3384         if (!crtc->config.ips_enabled)
3385                 return;
3386
3387         assert_plane_enabled(dev_priv, crtc->plane);
3388         I915_WRITE(IPS_CTL, 0);
3389
3390         /* We need to wait for a vblank before we can disable the plane. */
3391         intel_wait_for_vblank(dev, crtc->pipe);
3392 }
3393
3394 static void haswell_crtc_enable(struct drm_crtc *crtc)
3395 {
3396         struct drm_device *dev = crtc->dev;
3397         struct drm_i915_private *dev_priv = dev->dev_private;
3398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399         struct intel_encoder *encoder;
3400         int pipe = intel_crtc->pipe;
3401         int plane = intel_crtc->plane;
3402
3403         WARN_ON(!crtc->enabled);
3404
3405         if (intel_crtc->active)
3406                 return;
3407
3408         intel_crtc->active = true;
3409
3410         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3411         if (intel_crtc->config.has_pch_encoder)
3412                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3413
3414         if (intel_crtc->config.has_pch_encoder)
3415                 dev_priv->display.fdi_link_train(crtc);
3416
3417         for_each_encoder_on_crtc(dev, crtc, encoder)
3418                 if (encoder->pre_enable)
3419                         encoder->pre_enable(encoder);
3420
3421         intel_ddi_enable_pipe_clock(intel_crtc);
3422
3423         ironlake_pfit_enable(intel_crtc);
3424
3425         /*
3426          * On ILK+ LUT must be loaded before the pipe is running but with
3427          * clocks enabled
3428          */
3429         intel_crtc_load_lut(crtc);
3430
3431         intel_ddi_set_pipe_settings(crtc);
3432         intel_ddi_enable_transcoder_func(crtc);
3433
3434         intel_update_watermarks(crtc);
3435         intel_enable_pipe(dev_priv, pipe,
3436                           intel_crtc->config.has_pch_encoder, false);
3437         intel_enable_plane(dev_priv, plane, pipe);
3438         intel_enable_planes(crtc);
3439         intel_crtc_update_cursor(crtc, true);
3440
3441         hsw_enable_ips(intel_crtc);
3442
3443         if (intel_crtc->config.has_pch_encoder)
3444                 lpt_pch_enable(crtc);
3445
3446         mutex_lock(&dev->struct_mutex);
3447         intel_update_fbc(dev);
3448         mutex_unlock(&dev->struct_mutex);
3449
3450         for_each_encoder_on_crtc(dev, crtc, encoder) {
3451                 encoder->enable(encoder);
3452                 intel_opregion_notify_encoder(encoder, true);
3453         }
3454
3455         /*
3456          * There seems to be a race in PCH platform hw (at least on some
3457          * outputs) where an enabled pipe still completes any pageflip right
3458          * away (as if the pipe is off) instead of waiting for vblank. As soon
3459          * as the first vblank happend, everything works as expected. Hence just
3460          * wait for one vblank before returning to avoid strange things
3461          * happening.
3462          */
3463         intel_wait_for_vblank(dev, intel_crtc->pipe);
3464 }
3465
3466 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3467 {
3468         struct drm_device *dev = crtc->base.dev;
3469         struct drm_i915_private *dev_priv = dev->dev_private;
3470         int pipe = crtc->pipe;
3471
3472         /* To avoid upsetting the power well on haswell only disable the pfit if
3473          * it's in use. The hw state code will make sure we get this right. */
3474         if (crtc->config.pch_pfit.size) {
3475                 I915_WRITE(PF_CTL(pipe), 0);
3476                 I915_WRITE(PF_WIN_POS(pipe), 0);
3477                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3478         }
3479 }
3480
3481 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3482 {
3483         struct drm_device *dev = crtc->dev;
3484         struct drm_i915_private *dev_priv = dev->dev_private;
3485         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3486         struct intel_encoder *encoder;
3487         int pipe = intel_crtc->pipe;
3488         int plane = intel_crtc->plane;
3489         u32 reg, temp;
3490
3491
3492         if (!intel_crtc->active)
3493                 return;
3494
3495         for_each_encoder_on_crtc(dev, crtc, encoder)
3496                 encoder->disable(encoder);
3497
3498         intel_crtc_wait_for_pending_flips(crtc);
3499         drm_vblank_off(dev, pipe);
3500
3501         if (dev_priv->fbc.plane == plane)
3502                 intel_disable_fbc(dev);
3503
3504         intel_crtc_update_cursor(crtc, false);
3505         intel_disable_planes(crtc);
3506         intel_disable_plane(dev_priv, plane, pipe);
3507
3508         if (intel_crtc->config.has_pch_encoder)
3509                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3510
3511         intel_disable_pipe(dev_priv, pipe);
3512
3513         ironlake_pfit_disable(intel_crtc);
3514
3515         for_each_encoder_on_crtc(dev, crtc, encoder)
3516                 if (encoder->post_disable)
3517                         encoder->post_disable(encoder);
3518
3519         if (intel_crtc->config.has_pch_encoder) {
3520                 ironlake_fdi_disable(crtc);
3521
3522                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3523                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3524
3525                 if (HAS_PCH_CPT(dev)) {
3526                         /* disable TRANS_DP_CTL */
3527                         reg = TRANS_DP_CTL(pipe);
3528                         temp = I915_READ(reg);
3529                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3530                                   TRANS_DP_PORT_SEL_MASK);
3531                         temp |= TRANS_DP_PORT_SEL_NONE;
3532                         I915_WRITE(reg, temp);
3533
3534                         /* disable DPLL_SEL */
3535                         temp = I915_READ(PCH_DPLL_SEL);
3536                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3537                         I915_WRITE(PCH_DPLL_SEL, temp);
3538                 }
3539
3540                 /* disable PCH DPLL */
3541                 intel_disable_shared_dpll(intel_crtc);
3542
3543                 ironlake_fdi_pll_disable(intel_crtc);
3544         }
3545
3546         intel_crtc->active = false;
3547         intel_update_watermarks(crtc);
3548
3549         mutex_lock(&dev->struct_mutex);
3550         intel_update_fbc(dev);
3551         mutex_unlock(&dev->struct_mutex);
3552 }
3553
3554 static void haswell_crtc_disable(struct drm_crtc *crtc)
3555 {
3556         struct drm_device *dev = crtc->dev;
3557         struct drm_i915_private *dev_priv = dev->dev_private;
3558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3559         struct intel_encoder *encoder;
3560         int pipe = intel_crtc->pipe;
3561         int plane = intel_crtc->plane;
3562         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3563
3564         if (!intel_crtc->active)
3565                 return;
3566
3567         for_each_encoder_on_crtc(dev, crtc, encoder) {
3568                 intel_opregion_notify_encoder(encoder, false);
3569                 encoder->disable(encoder);
3570         }
3571
3572         intel_crtc_wait_for_pending_flips(crtc);
3573         drm_vblank_off(dev, pipe);
3574
3575         /* FBC must be disabled before disabling the plane on HSW. */
3576         if (dev_priv->fbc.plane == plane)
3577                 intel_disable_fbc(dev);
3578
3579         hsw_disable_ips(intel_crtc);
3580
3581         intel_crtc_update_cursor(crtc, false);
3582         intel_disable_planes(crtc);
3583         intel_disable_plane(dev_priv, plane, pipe);
3584
3585         if (intel_crtc->config.has_pch_encoder)
3586                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3587         intel_disable_pipe(dev_priv, pipe);
3588
3589         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3590
3591         ironlake_pfit_disable(intel_crtc);
3592
3593         intel_ddi_disable_pipe_clock(intel_crtc);
3594
3595         for_each_encoder_on_crtc(dev, crtc, encoder)
3596                 if (encoder->post_disable)
3597                         encoder->post_disable(encoder);
3598
3599         if (intel_crtc->config.has_pch_encoder) {
3600                 lpt_disable_pch_transcoder(dev_priv);
3601                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3602                 intel_ddi_fdi_disable(crtc);
3603         }
3604
3605         intel_crtc->active = false;
3606         intel_update_watermarks(crtc);
3607
3608         mutex_lock(&dev->struct_mutex);
3609         intel_update_fbc(dev);
3610         mutex_unlock(&dev->struct_mutex);
3611 }
3612
3613 static void ironlake_crtc_off(struct drm_crtc *crtc)
3614 {
3615         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3616         intel_put_shared_dpll(intel_crtc);
3617 }
3618
3619 static void haswell_crtc_off(struct drm_crtc *crtc)
3620 {
3621         intel_ddi_put_crtc_pll(crtc);
3622 }
3623
3624 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3625 {
3626         if (!enable && intel_crtc->overlay) {
3627                 struct drm_device *dev = intel_crtc->base.dev;
3628                 struct drm_i915_private *dev_priv = dev->dev_private;
3629
3630                 mutex_lock(&dev->struct_mutex);
3631                 dev_priv->mm.interruptible = false;
3632                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3633                 dev_priv->mm.interruptible = true;
3634                 mutex_unlock(&dev->struct_mutex);
3635         }
3636
3637         /* Let userspace switch the overlay on again. In most cases userspace
3638          * has to recompute where to put it anyway.
3639          */
3640 }
3641
3642 /**
3643  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3644  * cursor plane briefly if not already running after enabling the display
3645  * plane.
3646  * This workaround avoids occasional blank screens when self refresh is
3647  * enabled.
3648  */
3649 static void
3650 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3651 {
3652         u32 cntl = I915_READ(CURCNTR(pipe));
3653
3654         if ((cntl & CURSOR_MODE) == 0) {
3655                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3656
3657                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3658                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3659                 intel_wait_for_vblank(dev_priv->dev, pipe);
3660                 I915_WRITE(CURCNTR(pipe), cntl);
3661                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3662                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3663         }
3664 }
3665
3666 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3667 {
3668         struct drm_device *dev = crtc->base.dev;
3669         struct drm_i915_private *dev_priv = dev->dev_private;
3670         struct intel_crtc_config *pipe_config = &crtc->config;
3671
3672         if (!crtc->config.gmch_pfit.control)
3673                 return;
3674
3675         /*
3676          * The panel fitter should only be adjusted whilst the pipe is disabled,
3677          * according to register description and PRM.
3678          */
3679         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3680         assert_pipe_disabled(dev_priv, crtc->pipe);
3681
3682         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3683         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3684
3685         /* Border color in case we don't scale up to the full screen. Black by
3686          * default, change to something else for debugging. */
3687         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3688 }
3689
3690 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3691 {
3692         struct drm_device *dev = crtc->dev;
3693         struct drm_i915_private *dev_priv = dev->dev_private;
3694         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3695         struct intel_encoder *encoder;
3696         int pipe = intel_crtc->pipe;
3697         int plane = intel_crtc->plane;
3698         bool is_dsi;
3699
3700         WARN_ON(!crtc->enabled);
3701
3702         if (intel_crtc->active)
3703                 return;
3704
3705         intel_crtc->active = true;
3706
3707         for_each_encoder_on_crtc(dev, crtc, encoder)
3708                 if (encoder->pre_pll_enable)
3709                         encoder->pre_pll_enable(encoder);
3710
3711         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3712
3713         if (!is_dsi)
3714                 vlv_enable_pll(intel_crtc);
3715
3716         for_each_encoder_on_crtc(dev, crtc, encoder)
3717                 if (encoder->pre_enable)
3718                         encoder->pre_enable(encoder);
3719
3720         i9xx_pfit_enable(intel_crtc);
3721
3722         intel_crtc_load_lut(crtc);
3723
3724         intel_update_watermarks(crtc);
3725         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3726         intel_enable_plane(dev_priv, plane, pipe);
3727         intel_enable_planes(crtc);
3728         intel_crtc_update_cursor(crtc, true);
3729
3730         intel_update_fbc(dev);
3731
3732         for_each_encoder_on_crtc(dev, crtc, encoder)
3733                 encoder->enable(encoder);
3734 }
3735
3736 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3737 {
3738         struct drm_device *dev = crtc->dev;
3739         struct drm_i915_private *dev_priv = dev->dev_private;
3740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741         struct intel_encoder *encoder;
3742         int pipe = intel_crtc->pipe;
3743         int plane = intel_crtc->plane;
3744
3745         WARN_ON(!crtc->enabled);
3746
3747         if (intel_crtc->active)
3748                 return;
3749
3750         intel_crtc->active = true;
3751
3752         for_each_encoder_on_crtc(dev, crtc, encoder)
3753                 if (encoder->pre_enable)
3754                         encoder->pre_enable(encoder);
3755
3756         i9xx_enable_pll(intel_crtc);
3757
3758         i9xx_pfit_enable(intel_crtc);
3759
3760         intel_crtc_load_lut(crtc);
3761
3762         intel_update_watermarks(crtc);
3763         intel_enable_pipe(dev_priv, pipe, false, false);
3764         intel_enable_plane(dev_priv, plane, pipe);
3765         intel_enable_planes(crtc);
3766         /* The fixup needs to happen before cursor is enabled */
3767         if (IS_G4X(dev))
3768                 g4x_fixup_plane(dev_priv, pipe);
3769         intel_crtc_update_cursor(crtc, true);
3770
3771         /* Give the overlay scaler a chance to enable if it's on this pipe */
3772         intel_crtc_dpms_overlay(intel_crtc, true);
3773
3774         intel_update_fbc(dev);
3775
3776         for_each_encoder_on_crtc(dev, crtc, encoder)
3777                 encoder->enable(encoder);
3778 }
3779
3780 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3781 {
3782         struct drm_device *dev = crtc->base.dev;
3783         struct drm_i915_private *dev_priv = dev->dev_private;
3784
3785         if (!crtc->config.gmch_pfit.control)
3786                 return;
3787
3788         assert_pipe_disabled(dev_priv, crtc->pipe);
3789
3790         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3791                          I915_READ(PFIT_CONTROL));
3792         I915_WRITE(PFIT_CONTROL, 0);
3793 }
3794
3795 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3796 {
3797         struct drm_device *dev = crtc->dev;
3798         struct drm_i915_private *dev_priv = dev->dev_private;
3799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3800         struct intel_encoder *encoder;
3801         int pipe = intel_crtc->pipe;
3802         int plane = intel_crtc->plane;
3803
3804         if (!intel_crtc->active)
3805                 return;
3806
3807         for_each_encoder_on_crtc(dev, crtc, encoder)
3808                 encoder->disable(encoder);
3809
3810         /* Give the overlay scaler a chance to disable if it's on this pipe */
3811         intel_crtc_wait_for_pending_flips(crtc);
3812         drm_vblank_off(dev, pipe);
3813
3814         if (dev_priv->fbc.plane == plane)
3815                 intel_disable_fbc(dev);
3816
3817         intel_crtc_dpms_overlay(intel_crtc, false);
3818         intel_crtc_update_cursor(crtc, false);
3819         intel_disable_planes(crtc);
3820         intel_disable_plane(dev_priv, plane, pipe);
3821
3822         intel_disable_pipe(dev_priv, pipe);
3823
3824         i9xx_pfit_disable(intel_crtc);
3825
3826         for_each_encoder_on_crtc(dev, crtc, encoder)
3827                 if (encoder->post_disable)
3828                         encoder->post_disable(encoder);
3829
3830         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3831                 i9xx_disable_pll(dev_priv, pipe);
3832
3833         intel_crtc->active = false;
3834         intel_update_watermarks(crtc);
3835
3836         intel_update_fbc(dev);
3837 }
3838
3839 static void i9xx_crtc_off(struct drm_crtc *crtc)
3840 {
3841 }
3842
3843 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3844                                     bool enabled)
3845 {
3846         struct drm_device *dev = crtc->dev;
3847         struct drm_i915_master_private *master_priv;
3848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849         int pipe = intel_crtc->pipe;
3850
3851         if (!dev->primary->master)
3852                 return;
3853
3854         master_priv = dev->primary->master->driver_priv;
3855         if (!master_priv->sarea_priv)
3856                 return;
3857
3858         switch (pipe) {
3859         case 0:
3860                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3861                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3862                 break;
3863         case 1:
3864                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3865                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3866                 break;
3867         default:
3868                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3869                 break;
3870         }
3871 }
3872
3873 /**
3874  * Sets the power management mode of the pipe and plane.
3875  */
3876 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3877 {
3878         struct drm_device *dev = crtc->dev;
3879         struct drm_i915_private *dev_priv = dev->dev_private;
3880         struct intel_encoder *intel_encoder;
3881         bool enable = false;
3882
3883         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3884                 enable |= intel_encoder->connectors_active;
3885
3886         if (enable)
3887                 dev_priv->display.crtc_enable(crtc);
3888         else
3889                 dev_priv->display.crtc_disable(crtc);
3890
3891         intel_crtc_update_sarea(crtc, enable);
3892 }
3893
3894 static void intel_crtc_disable(struct drm_crtc *crtc)
3895 {
3896         struct drm_device *dev = crtc->dev;
3897         struct drm_connector *connector;
3898         struct drm_i915_private *dev_priv = dev->dev_private;
3899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3900
3901         /* crtc should still be enabled when we disable it. */
3902         WARN_ON(!crtc->enabled);
3903
3904         dev_priv->display.crtc_disable(crtc);
3905         intel_crtc->eld_vld = false;
3906         intel_crtc_update_sarea(crtc, false);
3907         dev_priv->display.off(crtc);
3908
3909         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3910         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
3911         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3912
3913         if (crtc->fb) {
3914                 mutex_lock(&dev->struct_mutex);
3915                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3916                 mutex_unlock(&dev->struct_mutex);
3917                 crtc->fb = NULL;
3918         }
3919
3920         /* Update computed state. */
3921         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3922                 if (!connector->encoder || !connector->encoder->crtc)
3923                         continue;
3924
3925                 if (connector->encoder->crtc != crtc)
3926                         continue;
3927
3928                 connector->dpms = DRM_MODE_DPMS_OFF;
3929                 to_intel_encoder(connector->encoder)->connectors_active = false;
3930         }
3931 }
3932
3933 void intel_encoder_destroy(struct drm_encoder *encoder)
3934 {
3935         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3936
3937         drm_encoder_cleanup(encoder);
3938         kfree(intel_encoder);
3939 }
3940
3941 /* Simple dpms helper for encoders with just one connector, no cloning and only
3942  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3943  * state of the entire output pipe. */
3944 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3945 {
3946         if (mode == DRM_MODE_DPMS_ON) {
3947                 encoder->connectors_active = true;
3948
3949                 intel_crtc_update_dpms(encoder->base.crtc);
3950         } else {
3951                 encoder->connectors_active = false;
3952
3953                 intel_crtc_update_dpms(encoder->base.crtc);
3954         }
3955 }
3956
3957 /* Cross check the actual hw state with our own modeset state tracking (and it's
3958  * internal consistency). */
3959 static void intel_connector_check_state(struct intel_connector *connector)
3960 {
3961         if (connector->get_hw_state(connector)) {
3962                 struct intel_encoder *encoder = connector->encoder;
3963                 struct drm_crtc *crtc;
3964                 bool encoder_enabled;
3965                 enum pipe pipe;
3966
3967                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3968                               connector->base.base.id,
3969                               drm_get_connector_name(&connector->base));
3970
3971                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3972                      "wrong connector dpms state\n");
3973                 WARN(connector->base.encoder != &encoder->base,
3974                      "active connector not linked to encoder\n");
3975                 WARN(!encoder->connectors_active,
3976                      "encoder->connectors_active not set\n");
3977
3978                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3979                 WARN(!encoder_enabled, "encoder not enabled\n");
3980                 if (WARN_ON(!encoder->base.crtc))
3981                         return;
3982
3983                 crtc = encoder->base.crtc;
3984
3985                 WARN(!crtc->enabled, "crtc not enabled\n");
3986                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3987                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3988                      "encoder active on the wrong pipe\n");
3989         }
3990 }
3991
3992 /* Even simpler default implementation, if there's really no special case to
3993  * consider. */
3994 void intel_connector_dpms(struct drm_connector *connector, int mode)
3995 {
3996         struct intel_encoder *encoder = intel_attached_encoder(connector);
3997
3998         /* All the simple cases only support two dpms states. */
3999         if (mode != DRM_MODE_DPMS_ON)
4000                 mode = DRM_MODE_DPMS_OFF;
4001
4002         if (mode == connector->dpms)
4003                 return;
4004
4005         connector->dpms = mode;
4006
4007         /* Only need to change hw state when actually enabled */
4008         if (encoder->base.crtc)
4009                 intel_encoder_dpms(encoder, mode);
4010         else
4011                 WARN_ON(encoder->connectors_active != false);
4012
4013         intel_modeset_check_state(connector->dev);
4014 }
4015
4016 /* Simple connector->get_hw_state implementation for encoders that support only
4017  * one connector and no cloning and hence the encoder state determines the state
4018  * of the connector. */
4019 bool intel_connector_get_hw_state(struct intel_connector *connector)
4020 {
4021         enum pipe pipe = 0;
4022         struct intel_encoder *encoder = connector->encoder;
4023
4024         return encoder->get_hw_state(encoder, &pipe);
4025 }
4026
4027 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4028                                      struct intel_crtc_config *pipe_config)
4029 {
4030         struct drm_i915_private *dev_priv = dev->dev_private;
4031         struct intel_crtc *pipe_B_crtc =
4032                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4033
4034         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4035                       pipe_name(pipe), pipe_config->fdi_lanes);
4036         if (pipe_config->fdi_lanes > 4) {
4037                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4038                               pipe_name(pipe), pipe_config->fdi_lanes);
4039                 return false;
4040         }
4041
4042         if (IS_HASWELL(dev)) {
4043                 if (pipe_config->fdi_lanes > 2) {
4044                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4045                                       pipe_config->fdi_lanes);
4046                         return false;
4047                 } else {
4048                         return true;
4049                 }
4050         }
4051
4052         if (INTEL_INFO(dev)->num_pipes == 2)
4053                 return true;
4054
4055         /* Ivybridge 3 pipe is really complicated */
4056         switch (pipe) {
4057         case PIPE_A:
4058                 return true;
4059         case PIPE_B:
4060                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4061                     pipe_config->fdi_lanes > 2) {
4062                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4063                                       pipe_name(pipe), pipe_config->fdi_lanes);
4064                         return false;
4065                 }
4066                 return true;
4067         case PIPE_C:
4068                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4069                     pipe_B_crtc->config.fdi_lanes <= 2) {
4070                         if (pipe_config->fdi_lanes > 2) {
4071                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4072                                               pipe_name(pipe), pipe_config->fdi_lanes);
4073                                 return false;
4074                         }
4075                 } else {
4076                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4077                         return false;
4078                 }
4079                 return true;
4080         default:
4081                 BUG();
4082         }
4083 }
4084
4085 #define RETRY 1
4086 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4087                                        struct intel_crtc_config *pipe_config)
4088 {
4089         struct drm_device *dev = intel_crtc->base.dev;
4090         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4091         int lane, link_bw, fdi_dotclock;
4092         bool setup_ok, needs_recompute = false;
4093
4094 retry:
4095         /* FDI is a binary signal running at ~2.7GHz, encoding
4096          * each output octet as 10 bits. The actual frequency
4097          * is stored as a divider into a 100MHz clock, and the
4098          * mode pixel clock is stored in units of 1KHz.
4099          * Hence the bw of each lane in terms of the mode signal
4100          * is:
4101          */
4102         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4103
4104         fdi_dotclock = adjusted_mode->clock;
4105
4106         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4107                                            pipe_config->pipe_bpp);
4108
4109         pipe_config->fdi_lanes = lane;
4110
4111         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4112                                link_bw, &pipe_config->fdi_m_n);
4113
4114         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4115                                             intel_crtc->pipe, pipe_config);
4116         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4117                 pipe_config->pipe_bpp -= 2*3;
4118                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4119                               pipe_config->pipe_bpp);
4120                 needs_recompute = true;
4121                 pipe_config->bw_constrained = true;
4122
4123                 goto retry;
4124         }
4125
4126         if (needs_recompute)
4127                 return RETRY;
4128
4129         return setup_ok ? 0 : -EINVAL;
4130 }
4131
4132 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4133                                    struct intel_crtc_config *pipe_config)
4134 {
4135         pipe_config->ips_enabled = i915_enable_ips &&
4136                                    hsw_crtc_supports_ips(crtc) &&
4137                                    pipe_config->pipe_bpp <= 24;
4138 }
4139
4140 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4141                                      struct intel_crtc_config *pipe_config)
4142 {
4143         struct drm_device *dev = crtc->base.dev;
4144         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4145
4146         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4147          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4148          */
4149         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4150                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4151                 return -EINVAL;
4152
4153         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4154                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4155         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4156                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4157                  * for lvds. */
4158                 pipe_config->pipe_bpp = 8*3;
4159         }
4160
4161         if (HAS_IPS(dev))
4162                 hsw_compute_ips_config(crtc, pipe_config);
4163
4164         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4165          * clock survives for now. */
4166         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4167                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4168
4169         if (pipe_config->has_pch_encoder)
4170                 return ironlake_fdi_compute_config(crtc, pipe_config);
4171
4172         return 0;
4173 }
4174
4175 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4176 {
4177         return 400000; /* FIXME */
4178 }
4179
4180 static int i945_get_display_clock_speed(struct drm_device *dev)
4181 {
4182         return 400000;
4183 }
4184
4185 static int i915_get_display_clock_speed(struct drm_device *dev)
4186 {
4187         return 333000;
4188 }
4189
4190 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4191 {
4192         return 200000;
4193 }
4194
4195 static int pnv_get_display_clock_speed(struct drm_device *dev)
4196 {
4197         u16 gcfgc = 0;
4198
4199         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4200
4201         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4202         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4203                 return 267000;
4204         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4205                 return 333000;
4206         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4207                 return 444000;
4208         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4209                 return 200000;
4210         default:
4211                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4212         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4213                 return 133000;
4214         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4215                 return 167000;
4216         }
4217 }
4218
4219 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4220 {
4221         u16 gcfgc = 0;
4222
4223         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4224
4225         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4226                 return 133000;
4227         else {
4228                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4229                 case GC_DISPLAY_CLOCK_333_MHZ:
4230                         return 333000;
4231                 default:
4232                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4233                         return 190000;
4234                 }
4235         }
4236 }
4237
4238 static int i865_get_display_clock_speed(struct drm_device *dev)
4239 {
4240         return 266000;
4241 }
4242
4243 static int i855_get_display_clock_speed(struct drm_device *dev)
4244 {
4245         u16 hpllcc = 0;
4246         /* Assume that the hardware is in the high speed state.  This
4247          * should be the default.
4248          */
4249         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4250         case GC_CLOCK_133_200:
4251         case GC_CLOCK_100_200:
4252                 return 200000;
4253         case GC_CLOCK_166_250:
4254                 return 250000;
4255         case GC_CLOCK_100_133:
4256                 return 133000;
4257         }
4258
4259         /* Shouldn't happen */
4260         return 0;
4261 }
4262
4263 static int i830_get_display_clock_speed(struct drm_device *dev)
4264 {
4265         return 133000;
4266 }
4267
4268 static void
4269 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4270 {
4271         while (*num > DATA_LINK_M_N_MASK ||
4272                *den > DATA_LINK_M_N_MASK) {
4273                 *num >>= 1;
4274                 *den >>= 1;
4275         }
4276 }
4277
4278 static void compute_m_n(unsigned int m, unsigned int n,
4279                         uint32_t *ret_m, uint32_t *ret_n)
4280 {
4281         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4282         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4283         intel_reduce_m_n_ratio(ret_m, ret_n);
4284 }
4285
4286 void
4287 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4288                        int pixel_clock, int link_clock,
4289                        struct intel_link_m_n *m_n)
4290 {
4291         m_n->tu = 64;
4292
4293         compute_m_n(bits_per_pixel * pixel_clock,
4294                     link_clock * nlanes * 8,
4295                     &m_n->gmch_m, &m_n->gmch_n);
4296
4297         compute_m_n(pixel_clock, link_clock,
4298                     &m_n->link_m, &m_n->link_n);
4299 }
4300
4301 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4302 {
4303         if (i915_panel_use_ssc >= 0)
4304                 return i915_panel_use_ssc != 0;
4305         return dev_priv->vbt.lvds_use_ssc
4306                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4307 }
4308
4309 static int vlv_get_refclk(struct drm_crtc *crtc)
4310 {
4311         struct drm_device *dev = crtc->dev;
4312         struct drm_i915_private *dev_priv = dev->dev_private;
4313         int refclk = 27000; /* for DP & HDMI */
4314
4315         return 100000; /* only one validated so far */
4316
4317         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4318                 refclk = 96000;
4319         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4320                 if (intel_panel_use_ssc(dev_priv))
4321                         refclk = 100000;
4322                 else
4323                         refclk = 96000;
4324         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4325                 refclk = 100000;
4326         }
4327
4328         return refclk;
4329 }
4330
4331 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4332 {
4333         struct drm_device *dev = crtc->dev;
4334         struct drm_i915_private *dev_priv = dev->dev_private;
4335         int refclk;
4336
4337         if (IS_VALLEYVIEW(dev)) {
4338                 refclk = vlv_get_refclk(crtc);
4339         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4340             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4341                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4342                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4343                               refclk / 1000);
4344         } else if (!IS_GEN2(dev)) {
4345                 refclk = 96000;
4346         } else {
4347                 refclk = 48000;
4348         }
4349
4350         return refclk;
4351 }
4352
4353 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4354 {
4355         return (1 << dpll->n) << 16 | dpll->m2;
4356 }
4357
4358 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4359 {
4360         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4361 }
4362
4363 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4364                                      intel_clock_t *reduced_clock)
4365 {
4366         struct drm_device *dev = crtc->base.dev;
4367         struct drm_i915_private *dev_priv = dev->dev_private;
4368         int pipe = crtc->pipe;
4369         u32 fp, fp2 = 0;
4370
4371         if (IS_PINEVIEW(dev)) {
4372                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4373                 if (reduced_clock)
4374                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4375         } else {
4376                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4377                 if (reduced_clock)
4378                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4379         }
4380
4381         I915_WRITE(FP0(pipe), fp);
4382         crtc->config.dpll_hw_state.fp0 = fp;
4383
4384         crtc->lowfreq_avail = false;
4385         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4386             reduced_clock && i915_powersave) {
4387                 I915_WRITE(FP1(pipe), fp2);
4388                 crtc->config.dpll_hw_state.fp1 = fp2;
4389                 crtc->lowfreq_avail = true;
4390         } else {
4391                 I915_WRITE(FP1(pipe), fp);
4392                 crtc->config.dpll_hw_state.fp1 = fp;
4393         }
4394 }
4395
4396 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4397                 pipe)
4398 {
4399         u32 reg_val;
4400
4401         /*
4402          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4403          * and set it to a reasonable value instead.
4404          */
4405         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4406         reg_val &= 0xffffff00;
4407         reg_val |= 0x00000030;
4408         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4409
4410         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4411         reg_val &= 0x8cffffff;
4412         reg_val = 0x8c000000;
4413         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4414
4415         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4416         reg_val &= 0xffffff00;
4417         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4418
4419         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4420         reg_val &= 0x00ffffff;
4421         reg_val |= 0xb0000000;
4422         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4423 }
4424
4425 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4426                                          struct intel_link_m_n *m_n)
4427 {
4428         struct drm_device *dev = crtc->base.dev;
4429         struct drm_i915_private *dev_priv = dev->dev_private;
4430         int pipe = crtc->pipe;
4431
4432         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4433         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4434         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4435         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4436 }
4437
4438 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4439                                          struct intel_link_m_n *m_n)
4440 {
4441         struct drm_device *dev = crtc->base.dev;
4442         struct drm_i915_private *dev_priv = dev->dev_private;
4443         int pipe = crtc->pipe;
4444         enum transcoder transcoder = crtc->config.cpu_transcoder;
4445
4446         if (INTEL_INFO(dev)->gen >= 5) {
4447                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4448                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4449                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4450                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4451         } else {
4452                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4453                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4454                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4455                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4456         }
4457 }
4458
4459 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4460 {
4461         if (crtc->config.has_pch_encoder)
4462                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4463         else
4464                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4465 }
4466
4467 static void vlv_update_pll(struct intel_crtc *crtc)
4468 {
4469         struct drm_device *dev = crtc->base.dev;
4470         struct drm_i915_private *dev_priv = dev->dev_private;
4471         int pipe = crtc->pipe;
4472         u32 dpll, mdiv;
4473         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4474         u32 coreclk, reg_val, dpll_md;
4475
4476         mutex_lock(&dev_priv->dpio_lock);
4477
4478         bestn = crtc->config.dpll.n;
4479         bestm1 = crtc->config.dpll.m1;
4480         bestm2 = crtc->config.dpll.m2;
4481         bestp1 = crtc->config.dpll.p1;
4482         bestp2 = crtc->config.dpll.p2;
4483
4484         /* See eDP HDMI DPIO driver vbios notes doc */
4485
4486         /* PLL B needs special handling */
4487         if (pipe)
4488                 vlv_pllb_recal_opamp(dev_priv, pipe);
4489
4490         /* Set up Tx target for periodic Rcomp update */
4491         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4492
4493         /* Disable target IRef on PLL */
4494         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4495         reg_val &= 0x00ffffff;
4496         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4497
4498         /* Disable fast lock */
4499         vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4500
4501         /* Set idtafcrecal before PLL is enabled */
4502         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4503         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4504         mdiv |= ((bestn << DPIO_N_SHIFT));
4505         mdiv |= (1 << DPIO_K_SHIFT);
4506
4507         /*
4508          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4509          * but we don't support that).
4510          * Note: don't use the DAC post divider as it seems unstable.
4511          */
4512         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4513         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4514
4515         mdiv |= DPIO_ENABLE_CALIBRATION;
4516         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4517
4518         /* Set HBR and RBR LPF coefficients */
4519         if (crtc->config.port_clock == 162000 ||
4520             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4521             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4522                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4523                                  0x009f0003);
4524         else
4525                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4526                                  0x00d0000f);
4527
4528         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4529             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4530                 /* Use SSC source */
4531                 if (!pipe)
4532                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4533                                          0x0df40000);
4534                 else
4535                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4536                                          0x0df70000);
4537         } else { /* HDMI or VGA */
4538                 /* Use bend source */
4539                 if (!pipe)
4540                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4541                                          0x0df70000);
4542                 else
4543                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4544                                          0x0df40000);
4545         }
4546
4547         coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4548         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4549         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4550             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4551                 coreclk |= 0x01000000;
4552         vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4553
4554         vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4555
4556         /* Enable DPIO clock input */
4557         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4558                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4559         if (pipe)
4560                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4561
4562         dpll |= DPLL_VCO_ENABLE;
4563         crtc->config.dpll_hw_state.dpll = dpll;
4564
4565         dpll_md = (crtc->config.pixel_multiplier - 1)
4566                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4567         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4568
4569         if (crtc->config.has_dp_encoder)
4570                 intel_dp_set_m_n(crtc);
4571
4572         mutex_unlock(&dev_priv->dpio_lock);
4573 }
4574
4575 static void i9xx_update_pll(struct intel_crtc *crtc,
4576                             intel_clock_t *reduced_clock,
4577                             int num_connectors)
4578 {
4579         struct drm_device *dev = crtc->base.dev;
4580         struct drm_i915_private *dev_priv = dev->dev_private;
4581         u32 dpll;
4582         bool is_sdvo;
4583         struct dpll *clock = &crtc->config.dpll;
4584
4585         i9xx_update_pll_dividers(crtc, reduced_clock);
4586
4587         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4588                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4589
4590         dpll = DPLL_VGA_MODE_DIS;
4591
4592         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4593                 dpll |= DPLLB_MODE_LVDS;
4594         else
4595                 dpll |= DPLLB_MODE_DAC_SERIAL;
4596
4597         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4598                 dpll |= (crtc->config.pixel_multiplier - 1)
4599                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4600         }
4601
4602         if (is_sdvo)
4603                 dpll |= DPLL_SDVO_HIGH_SPEED;
4604
4605         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4606                 dpll |= DPLL_SDVO_HIGH_SPEED;
4607
4608         /* compute bitmask from p1 value */
4609         if (IS_PINEVIEW(dev))
4610                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4611         else {
4612                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4613                 if (IS_G4X(dev) && reduced_clock)
4614                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4615         }
4616         switch (clock->p2) {
4617         case 5:
4618                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4619                 break;
4620         case 7:
4621                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4622                 break;
4623         case 10:
4624                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4625                 break;
4626         case 14:
4627                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4628                 break;
4629         }
4630         if (INTEL_INFO(dev)->gen >= 4)
4631                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4632
4633         if (crtc->config.sdvo_tv_clock)
4634                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4635         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4636                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4637                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4638         else
4639                 dpll |= PLL_REF_INPUT_DREFCLK;
4640
4641         dpll |= DPLL_VCO_ENABLE;
4642         crtc->config.dpll_hw_state.dpll = dpll;
4643
4644         if (INTEL_INFO(dev)->gen >= 4) {
4645                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4646                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4647                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4648         }
4649
4650         if (crtc->config.has_dp_encoder)
4651                 intel_dp_set_m_n(crtc);
4652 }
4653
4654 static void i8xx_update_pll(struct intel_crtc *crtc,
4655                             intel_clock_t *reduced_clock,
4656                             int num_connectors)
4657 {
4658         struct drm_device *dev = crtc->base.dev;
4659         struct drm_i915_private *dev_priv = dev->dev_private;
4660         u32 dpll;
4661         struct dpll *clock = &crtc->config.dpll;
4662
4663         i9xx_update_pll_dividers(crtc, reduced_clock);
4664
4665         dpll = DPLL_VGA_MODE_DIS;
4666
4667         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4668                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4669         } else {
4670                 if (clock->p1 == 2)
4671                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4672                 else
4673                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4674                 if (clock->p2 == 4)
4675                         dpll |= PLL_P2_DIVIDE_BY_4;
4676         }
4677
4678         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4679                 dpll |= DPLL_DVO_2X_MODE;
4680
4681         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4682                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4683                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4684         else
4685                 dpll |= PLL_REF_INPUT_DREFCLK;
4686
4687         dpll |= DPLL_VCO_ENABLE;
4688         crtc->config.dpll_hw_state.dpll = dpll;
4689 }
4690
4691 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4692 {
4693         struct drm_device *dev = intel_crtc->base.dev;
4694         struct drm_i915_private *dev_priv = dev->dev_private;
4695         enum pipe pipe = intel_crtc->pipe;
4696         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4697         struct drm_display_mode *adjusted_mode =
4698                 &intel_crtc->config.adjusted_mode;
4699         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4700
4701         /* We need to be careful not to changed the adjusted mode, for otherwise
4702          * the hw state checker will get angry at the mismatch. */
4703         crtc_vtotal = adjusted_mode->crtc_vtotal;
4704         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4705
4706         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4707                 /* the chip adds 2 halflines automatically */
4708                 crtc_vtotal -= 1;
4709                 crtc_vblank_end -= 1;
4710                 vsyncshift = adjusted_mode->crtc_hsync_start
4711                              - adjusted_mode->crtc_htotal / 2;
4712         } else {
4713                 vsyncshift = 0;
4714         }
4715
4716         if (INTEL_INFO(dev)->gen > 3)
4717                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4718
4719         I915_WRITE(HTOTAL(cpu_transcoder),
4720                    (adjusted_mode->crtc_hdisplay - 1) |
4721                    ((adjusted_mode->crtc_htotal - 1) << 16));
4722         I915_WRITE(HBLANK(cpu_transcoder),
4723                    (adjusted_mode->crtc_hblank_start - 1) |
4724                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4725         I915_WRITE(HSYNC(cpu_transcoder),
4726                    (adjusted_mode->crtc_hsync_start - 1) |
4727                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4728
4729         I915_WRITE(VTOTAL(cpu_transcoder),
4730                    (adjusted_mode->crtc_vdisplay - 1) |
4731                    ((crtc_vtotal - 1) << 16));
4732         I915_WRITE(VBLANK(cpu_transcoder),
4733                    (adjusted_mode->crtc_vblank_start - 1) |
4734                    ((crtc_vblank_end - 1) << 16));
4735         I915_WRITE(VSYNC(cpu_transcoder),
4736                    (adjusted_mode->crtc_vsync_start - 1) |
4737                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4738
4739         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4740          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4741          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4742          * bits. */
4743         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4744             (pipe == PIPE_B || pipe == PIPE_C))
4745                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4746
4747         /* pipesrc controls the size that is scaled from, which should
4748          * always be the user's requested size.
4749          */
4750         I915_WRITE(PIPESRC(pipe),
4751                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
4752                    (intel_crtc->config.pipe_src_h - 1));
4753 }
4754
4755 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4756                                    struct intel_crtc_config *pipe_config)
4757 {
4758         struct drm_device *dev = crtc->base.dev;
4759         struct drm_i915_private *dev_priv = dev->dev_private;
4760         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4761         uint32_t tmp;
4762
4763         tmp = I915_READ(HTOTAL(cpu_transcoder));
4764         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4765         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4766         tmp = I915_READ(HBLANK(cpu_transcoder));
4767         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4768         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4769         tmp = I915_READ(HSYNC(cpu_transcoder));
4770         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4771         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4772
4773         tmp = I915_READ(VTOTAL(cpu_transcoder));
4774         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4775         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4776         tmp = I915_READ(VBLANK(cpu_transcoder));
4777         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4778         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4779         tmp = I915_READ(VSYNC(cpu_transcoder));
4780         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4781         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4782
4783         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4784                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4785                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4786                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4787         }
4788
4789         tmp = I915_READ(PIPESRC(crtc->pipe));
4790         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4791         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4792
4793         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4794         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
4795 }
4796
4797 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4798                                              struct intel_crtc_config *pipe_config)
4799 {
4800         struct drm_crtc *crtc = &intel_crtc->base;
4801
4802         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4803         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4804         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4805         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4806
4807         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4808         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4809         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4810         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4811
4812         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4813
4814         crtc->mode.clock = pipe_config->adjusted_mode.clock;
4815         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4816 }
4817
4818 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4819 {
4820         struct drm_device *dev = intel_crtc->base.dev;
4821         struct drm_i915_private *dev_priv = dev->dev_private;
4822         uint32_t pipeconf;
4823
4824         pipeconf = 0;
4825
4826         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4827                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4828                  * core speed.
4829                  *
4830                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4831                  * pipe == 0 check?
4832                  */
4833                 if (intel_crtc->config.adjusted_mode.clock >
4834                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4835                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4836         }
4837
4838         /* only g4x and later have fancy bpc/dither controls */
4839         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4840                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4841                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4842                         pipeconf |= PIPECONF_DITHER_EN |
4843                                     PIPECONF_DITHER_TYPE_SP;
4844
4845                 switch (intel_crtc->config.pipe_bpp) {
4846                 case 18:
4847                         pipeconf |= PIPECONF_6BPC;
4848                         break;
4849                 case 24:
4850                         pipeconf |= PIPECONF_8BPC;
4851                         break;
4852                 case 30:
4853                         pipeconf |= PIPECONF_10BPC;
4854                         break;
4855                 default:
4856                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4857                         BUG();
4858                 }
4859         }
4860
4861         if (HAS_PIPE_CXSR(dev)) {
4862                 if (intel_crtc->lowfreq_avail) {
4863                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4864                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4865                 } else {
4866                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4867                 }
4868         }
4869
4870         if (!IS_GEN2(dev) &&
4871             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4872                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4873         else
4874                 pipeconf |= PIPECONF_PROGRESSIVE;
4875
4876         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4877                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4878
4879         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4880         POSTING_READ(PIPECONF(intel_crtc->pipe));
4881 }
4882
4883 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4884                               int x, int y,
4885                               struct drm_framebuffer *fb)
4886 {
4887         struct drm_device *dev = crtc->dev;
4888         struct drm_i915_private *dev_priv = dev->dev_private;
4889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4890         int pipe = intel_crtc->pipe;
4891         int plane = intel_crtc->plane;
4892         int refclk, num_connectors = 0;
4893         intel_clock_t clock, reduced_clock;
4894         u32 dspcntr;
4895         bool ok, has_reduced_clock = false;
4896         bool is_lvds = false, is_dsi = false;
4897         struct intel_encoder *encoder;
4898         const intel_limit_t *limit;
4899         int ret;
4900
4901         for_each_encoder_on_crtc(dev, crtc, encoder) {
4902                 switch (encoder->type) {
4903                 case INTEL_OUTPUT_LVDS:
4904                         is_lvds = true;
4905                         break;
4906                 case INTEL_OUTPUT_DSI:
4907                         is_dsi = true;
4908                         break;
4909                 }
4910
4911                 num_connectors++;
4912         }
4913
4914         refclk = i9xx_get_refclk(crtc, num_connectors);
4915
4916         if (!is_dsi && !intel_crtc->config.clock_set) {
4917                 /*
4918                  * Returns a set of divisors for the desired target clock with
4919                  * the given refclk, or FALSE.  The returned values represent
4920                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4921                  * 2) / p1 / p2.
4922                  */
4923                 limit = intel_limit(crtc, refclk);
4924                 ok = dev_priv->display.find_dpll(limit, crtc,
4925                                                  intel_crtc->config.port_clock,
4926                                                  refclk, NULL, &clock);
4927                 if (!ok && !intel_crtc->config.clock_set) {
4928                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
4929                         return -EINVAL;
4930                 }
4931         }
4932
4933         /* Ensure that the cursor is valid for the new mode before changing... */
4934         intel_crtc_update_cursor(crtc, true);
4935
4936         if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
4937                 /*
4938                  * Ensure we match the reduced clock's P to the target clock.
4939                  * If the clocks don't match, we can't switch the display clock
4940                  * by using the FP0/FP1. In such case we will disable the LVDS
4941                  * downclock feature.
4942                 */
4943                 limit = intel_limit(crtc, refclk);
4944                 has_reduced_clock =
4945                         dev_priv->display.find_dpll(limit, crtc,
4946                                                     dev_priv->lvds_downclock,
4947                                                     refclk, &clock,
4948                                                     &reduced_clock);
4949         }
4950         /* Compat-code for transition, will disappear. */
4951         if (!intel_crtc->config.clock_set) {
4952                 intel_crtc->config.dpll.n = clock.n;
4953                 intel_crtc->config.dpll.m1 = clock.m1;
4954                 intel_crtc->config.dpll.m2 = clock.m2;
4955                 intel_crtc->config.dpll.p1 = clock.p1;
4956                 intel_crtc->config.dpll.p2 = clock.p2;
4957         }
4958
4959         if (IS_GEN2(dev)) {
4960                 i8xx_update_pll(intel_crtc,
4961                                 has_reduced_clock ? &reduced_clock : NULL,
4962                                 num_connectors);
4963         } else if (IS_VALLEYVIEW(dev)) {
4964                 if (!is_dsi)
4965                         vlv_update_pll(intel_crtc);
4966         } else {
4967                 i9xx_update_pll(intel_crtc,
4968                                 has_reduced_clock ? &reduced_clock : NULL,
4969                                 num_connectors);
4970         }
4971
4972         /* Set up the display plane register */
4973         dspcntr = DISPPLANE_GAMMA_ENABLE;
4974
4975         if (!IS_VALLEYVIEW(dev)) {
4976                 if (pipe == 0)
4977                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4978                 else
4979                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4980         }
4981
4982         intel_set_pipe_timings(intel_crtc);
4983
4984         /* pipesrc and dspsize control the size that is scaled from,
4985          * which should always be the user's requested size.
4986          */
4987         I915_WRITE(DSPSIZE(plane),
4988                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4989                    (intel_crtc->config.pipe_src_w - 1));
4990         I915_WRITE(DSPPOS(plane), 0);
4991
4992         i9xx_set_pipeconf(intel_crtc);
4993
4994         I915_WRITE(DSPCNTR(plane), dspcntr);
4995         POSTING_READ(DSPCNTR(plane));
4996
4997         ret = intel_pipe_set_base(crtc, x, y, fb);
4998
4999         return ret;
5000 }
5001
5002 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5003                                  struct intel_crtc_config *pipe_config)
5004 {
5005         struct drm_device *dev = crtc->base.dev;
5006         struct drm_i915_private *dev_priv = dev->dev_private;
5007         uint32_t tmp;
5008
5009         tmp = I915_READ(PFIT_CONTROL);
5010         if (!(tmp & PFIT_ENABLE))
5011                 return;
5012
5013         /* Check whether the pfit is attached to our pipe. */
5014         if (INTEL_INFO(dev)->gen < 4) {
5015                 if (crtc->pipe != PIPE_B)
5016                         return;
5017         } else {
5018                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5019                         return;
5020         }
5021
5022         pipe_config->gmch_pfit.control = tmp;
5023         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5024         if (INTEL_INFO(dev)->gen < 5)
5025                 pipe_config->gmch_pfit.lvds_border_bits =
5026                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5027 }
5028
5029 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5030                                  struct intel_crtc_config *pipe_config)
5031 {
5032         struct drm_device *dev = crtc->base.dev;
5033         struct drm_i915_private *dev_priv = dev->dev_private;
5034         uint32_t tmp;
5035
5036         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5037         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5038
5039         tmp = I915_READ(PIPECONF(crtc->pipe));
5040         if (!(tmp & PIPECONF_ENABLE))
5041                 return false;
5042
5043         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5044                 switch (tmp & PIPECONF_BPC_MASK) {
5045                 case PIPECONF_6BPC:
5046                         pipe_config->pipe_bpp = 18;
5047                         break;
5048                 case PIPECONF_8BPC:
5049                         pipe_config->pipe_bpp = 24;
5050                         break;
5051                 case PIPECONF_10BPC:
5052                         pipe_config->pipe_bpp = 30;
5053                         break;
5054                 default:
5055                         break;
5056                 }
5057         }
5058
5059         intel_get_pipe_timings(crtc, pipe_config);
5060
5061         i9xx_get_pfit_config(crtc, pipe_config);
5062
5063         if (INTEL_INFO(dev)->gen >= 4) {
5064                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5065                 pipe_config->pixel_multiplier =
5066                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5067                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5068                 pipe_config->dpll_hw_state.dpll_md = tmp;
5069         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5070                 tmp = I915_READ(DPLL(crtc->pipe));
5071                 pipe_config->pixel_multiplier =
5072                         ((tmp & SDVO_MULTIPLIER_MASK)
5073                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5074         } else {
5075                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5076                  * port and will be fixed up in the encoder->get_config
5077                  * function. */
5078                 pipe_config->pixel_multiplier = 1;
5079         }
5080         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5081         if (!IS_VALLEYVIEW(dev)) {
5082                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5083                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5084         } else {
5085                 /* Mask out read-only status bits. */
5086                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5087                                                      DPLL_PORTC_READY_MASK |
5088                                                      DPLL_PORTB_READY_MASK);
5089         }
5090
5091         i9xx_crtc_clock_get(crtc, pipe_config);
5092
5093         return true;
5094 }
5095
5096 static void ironlake_init_pch_refclk(struct drm_device *dev)
5097 {
5098         struct drm_i915_private *dev_priv = dev->dev_private;
5099         struct drm_mode_config *mode_config = &dev->mode_config;
5100         struct intel_encoder *encoder;
5101         u32 val, final;
5102         bool has_lvds = false;
5103         bool has_cpu_edp = false;
5104         bool has_panel = false;
5105         bool has_ck505 = false;
5106         bool can_ssc = false;
5107
5108         /* We need to take the global config into account */
5109         list_for_each_entry(encoder, &mode_config->encoder_list,
5110                             base.head) {
5111                 switch (encoder->type) {
5112                 case INTEL_OUTPUT_LVDS:
5113                         has_panel = true;
5114                         has_lvds = true;
5115                         break;
5116                 case INTEL_OUTPUT_EDP:
5117                         has_panel = true;
5118                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5119                                 has_cpu_edp = true;
5120                         break;
5121                 }
5122         }
5123
5124         if (HAS_PCH_IBX(dev)) {
5125                 has_ck505 = dev_priv->vbt.display_clock_mode;
5126                 can_ssc = has_ck505;
5127         } else {
5128                 has_ck505 = false;
5129                 can_ssc = true;
5130         }
5131
5132         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5133                       has_panel, has_lvds, has_ck505);
5134
5135         /* Ironlake: try to setup display ref clock before DPLL
5136          * enabling. This is only under driver's control after
5137          * PCH B stepping, previous chipset stepping should be
5138          * ignoring this setting.
5139          */
5140         val = I915_READ(PCH_DREF_CONTROL);
5141
5142         /* As we must carefully and slowly disable/enable each source in turn,
5143          * compute the final state we want first and check if we need to
5144          * make any changes at all.
5145          */
5146         final = val;
5147         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5148         if (has_ck505)
5149                 final |= DREF_NONSPREAD_CK505_ENABLE;
5150         else
5151                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5152
5153         final &= ~DREF_SSC_SOURCE_MASK;
5154         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5155         final &= ~DREF_SSC1_ENABLE;
5156
5157         if (has_panel) {
5158                 final |= DREF_SSC_SOURCE_ENABLE;
5159
5160                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5161                         final |= DREF_SSC1_ENABLE;
5162
5163                 if (has_cpu_edp) {
5164                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5165                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5166                         else
5167                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5168                 } else
5169                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5170         } else {
5171                 final |= DREF_SSC_SOURCE_DISABLE;
5172                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5173         }
5174
5175         if (final == val)
5176                 return;
5177
5178         /* Always enable nonspread source */
5179         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5180
5181         if (has_ck505)
5182                 val |= DREF_NONSPREAD_CK505_ENABLE;
5183         else
5184                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5185
5186         if (has_panel) {
5187                 val &= ~DREF_SSC_SOURCE_MASK;
5188                 val |= DREF_SSC_SOURCE_ENABLE;
5189
5190                 /* SSC must be turned on before enabling the CPU output  */
5191                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5192                         DRM_DEBUG_KMS("Using SSC on panel\n");
5193                         val |= DREF_SSC1_ENABLE;
5194                 } else
5195                         val &= ~DREF_SSC1_ENABLE;
5196
5197                 /* Get SSC going before enabling the outputs */
5198                 I915_WRITE(PCH_DREF_CONTROL, val);
5199                 POSTING_READ(PCH_DREF_CONTROL);
5200                 udelay(200);
5201
5202                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5203
5204                 /* Enable CPU source on CPU attached eDP */
5205                 if (has_cpu_edp) {
5206                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5207                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5208                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5209                         }
5210                         else
5211                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5212                 } else
5213                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5214
5215                 I915_WRITE(PCH_DREF_CONTROL, val);
5216                 POSTING_READ(PCH_DREF_CONTROL);
5217                 udelay(200);
5218         } else {
5219                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5220
5221                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5222
5223                 /* Turn off CPU output */
5224                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5225
5226                 I915_WRITE(PCH_DREF_CONTROL, val);
5227                 POSTING_READ(PCH_DREF_CONTROL);
5228                 udelay(200);
5229
5230                 /* Turn off the SSC source */
5231                 val &= ~DREF_SSC_SOURCE_MASK;
5232                 val |= DREF_SSC_SOURCE_DISABLE;
5233
5234                 /* Turn off SSC1 */
5235                 val &= ~DREF_SSC1_ENABLE;
5236
5237                 I915_WRITE(PCH_DREF_CONTROL, val);
5238                 POSTING_READ(PCH_DREF_CONTROL);
5239                 udelay(200);
5240         }
5241
5242         BUG_ON(val != final);
5243 }
5244
5245 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5246 {
5247         uint32_t tmp;
5248
5249         tmp = I915_READ(SOUTH_CHICKEN2);
5250         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5251         I915_WRITE(SOUTH_CHICKEN2, tmp);
5252
5253         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5254                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5255                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5256
5257         tmp = I915_READ(SOUTH_CHICKEN2);
5258         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5259         I915_WRITE(SOUTH_CHICKEN2, tmp);
5260
5261         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5262                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5263                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5264 }
5265
5266 /* WaMPhyProgramming:hsw */
5267 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5268 {
5269         uint32_t tmp;
5270
5271         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5272         tmp &= ~(0xFF << 24);
5273         tmp |= (0x12 << 24);
5274         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5275
5276         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5277         tmp |= (1 << 11);
5278         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5279
5280         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5281         tmp |= (1 << 11);
5282         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5283
5284         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5285         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5286         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5287
5288         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5289         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5290         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5291
5292         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5293         tmp &= ~(7 << 13);
5294         tmp |= (5 << 13);
5295         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5296
5297         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5298         tmp &= ~(7 << 13);
5299         tmp |= (5 << 13);
5300         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5301
5302         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5303         tmp &= ~0xFF;
5304         tmp |= 0x1C;
5305         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5306
5307         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5308         tmp &= ~0xFF;
5309         tmp |= 0x1C;
5310         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5311
5312         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5313         tmp &= ~(0xFF << 16);
5314         tmp |= (0x1C << 16);
5315         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5316
5317         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5318         tmp &= ~(0xFF << 16);
5319         tmp |= (0x1C << 16);
5320         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5321
5322         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5323         tmp |= (1 << 27);
5324         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5325
5326         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5327         tmp |= (1 << 27);
5328         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5329
5330         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5331         tmp &= ~(0xF << 28);
5332         tmp |= (4 << 28);
5333         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5334
5335         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5336         tmp &= ~(0xF << 28);
5337         tmp |= (4 << 28);
5338         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5339 }
5340
5341 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5342  * Programming" based on the parameters passed:
5343  * - Sequence to enable CLKOUT_DP
5344  * - Sequence to enable CLKOUT_DP without spread
5345  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5346  */
5347 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5348                                  bool with_fdi)
5349 {
5350         struct drm_i915_private *dev_priv = dev->dev_private;
5351         uint32_t reg, tmp;
5352
5353         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5354                 with_spread = true;
5355         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5356                  with_fdi, "LP PCH doesn't have FDI\n"))
5357                 with_fdi = false;
5358
5359         mutex_lock(&dev_priv->dpio_lock);
5360
5361         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5362         tmp &= ~SBI_SSCCTL_DISABLE;
5363         tmp |= SBI_SSCCTL_PATHALT;
5364         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5365
5366         udelay(24);
5367
5368         if (with_spread) {
5369                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5370                 tmp &= ~SBI_SSCCTL_PATHALT;
5371                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5372
5373                 if (with_fdi) {
5374                         lpt_reset_fdi_mphy(dev_priv);
5375                         lpt_program_fdi_mphy(dev_priv);
5376                 }
5377         }
5378
5379         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5380                SBI_GEN0 : SBI_DBUFF0;
5381         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5382         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5383         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5384
5385         mutex_unlock(&dev_priv->dpio_lock);
5386 }
5387
5388 /* Sequence to disable CLKOUT_DP */
5389 static void lpt_disable_clkout_dp(struct drm_device *dev)
5390 {
5391         struct drm_i915_private *dev_priv = dev->dev_private;
5392         uint32_t reg, tmp;
5393
5394         mutex_lock(&dev_priv->dpio_lock);
5395
5396         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5397                SBI_GEN0 : SBI_DBUFF0;
5398         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5399         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5400         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5401
5402         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5403         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5404                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5405                         tmp |= SBI_SSCCTL_PATHALT;
5406                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5407                         udelay(32);
5408                 }
5409                 tmp |= SBI_SSCCTL_DISABLE;
5410                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5411         }
5412
5413         mutex_unlock(&dev_priv->dpio_lock);
5414 }
5415
5416 static void lpt_init_pch_refclk(struct drm_device *dev)
5417 {
5418         struct drm_mode_config *mode_config = &dev->mode_config;
5419         struct intel_encoder *encoder;
5420         bool has_vga = false;
5421
5422         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5423                 switch (encoder->type) {
5424                 case INTEL_OUTPUT_ANALOG:
5425                         has_vga = true;
5426                         break;
5427                 }
5428         }
5429
5430         if (has_vga)
5431                 lpt_enable_clkout_dp(dev, true, true);
5432         else
5433                 lpt_disable_clkout_dp(dev);
5434 }
5435
5436 /*
5437  * Initialize reference clocks when the driver loads
5438  */
5439 void intel_init_pch_refclk(struct drm_device *dev)
5440 {
5441         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5442                 ironlake_init_pch_refclk(dev);
5443         else if (HAS_PCH_LPT(dev))
5444                 lpt_init_pch_refclk(dev);
5445 }
5446
5447 static int ironlake_get_refclk(struct drm_crtc *crtc)
5448 {
5449         struct drm_device *dev = crtc->dev;
5450         struct drm_i915_private *dev_priv = dev->dev_private;
5451         struct intel_encoder *encoder;
5452         int num_connectors = 0;
5453         bool is_lvds = false;
5454
5455         for_each_encoder_on_crtc(dev, crtc, encoder) {
5456                 switch (encoder->type) {
5457                 case INTEL_OUTPUT_LVDS:
5458                         is_lvds = true;
5459                         break;
5460                 }
5461                 num_connectors++;
5462         }
5463
5464         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5465                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5466                               dev_priv->vbt.lvds_ssc_freq);
5467                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5468         }
5469
5470         return 120000;
5471 }
5472
5473 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5474 {
5475         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5476         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5477         int pipe = intel_crtc->pipe;
5478         uint32_t val;
5479
5480         val = 0;
5481
5482         switch (intel_crtc->config.pipe_bpp) {
5483         case 18:
5484                 val |= PIPECONF_6BPC;
5485                 break;
5486         case 24:
5487                 val |= PIPECONF_8BPC;
5488                 break;
5489         case 30:
5490                 val |= PIPECONF_10BPC;
5491                 break;
5492         case 36:
5493                 val |= PIPECONF_12BPC;
5494                 break;
5495         default:
5496                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5497                 BUG();
5498         }
5499
5500         if (intel_crtc->config.dither)
5501                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5502
5503         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5504                 val |= PIPECONF_INTERLACED_ILK;
5505         else
5506                 val |= PIPECONF_PROGRESSIVE;
5507
5508         if (intel_crtc->config.limited_color_range)
5509                 val |= PIPECONF_COLOR_RANGE_SELECT;
5510
5511         I915_WRITE(PIPECONF(pipe), val);
5512         POSTING_READ(PIPECONF(pipe));
5513 }
5514
5515 /*
5516  * Set up the pipe CSC unit.
5517  *
5518  * Currently only full range RGB to limited range RGB conversion
5519  * is supported, but eventually this should handle various
5520  * RGB<->YCbCr scenarios as well.
5521  */
5522 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5523 {
5524         struct drm_device *dev = crtc->dev;
5525         struct drm_i915_private *dev_priv = dev->dev_private;
5526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5527         int pipe = intel_crtc->pipe;
5528         uint16_t coeff = 0x7800; /* 1.0 */
5529
5530         /*
5531          * TODO: Check what kind of values actually come out of the pipe
5532          * with these coeff/postoff values and adjust to get the best
5533          * accuracy. Perhaps we even need to take the bpc value into
5534          * consideration.
5535          */
5536
5537         if (intel_crtc->config.limited_color_range)
5538                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5539
5540         /*
5541          * GY/GU and RY/RU should be the other way around according
5542          * to BSpec, but reality doesn't agree. Just set them up in
5543          * a way that results in the correct picture.
5544          */
5545         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5546         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5547
5548         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5549         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5550
5551         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5552         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5553
5554         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5555         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5556         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5557
5558         if (INTEL_INFO(dev)->gen > 6) {
5559                 uint16_t postoff = 0;
5560
5561                 if (intel_crtc->config.limited_color_range)
5562                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5563
5564                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5565                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5566                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5567
5568                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5569         } else {
5570                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5571
5572                 if (intel_crtc->config.limited_color_range)
5573                         mode |= CSC_BLACK_SCREEN_OFFSET;
5574
5575                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5576         }
5577 }
5578
5579 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5580 {
5581         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5582         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5583         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5584         uint32_t val;
5585
5586         val = 0;
5587
5588         if (intel_crtc->config.dither)
5589                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5590
5591         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5592                 val |= PIPECONF_INTERLACED_ILK;
5593         else
5594                 val |= PIPECONF_PROGRESSIVE;
5595
5596         I915_WRITE(PIPECONF(cpu_transcoder), val);
5597         POSTING_READ(PIPECONF(cpu_transcoder));
5598
5599         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5600         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5601 }
5602
5603 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5604                                     intel_clock_t *clock,
5605                                     bool *has_reduced_clock,
5606                                     intel_clock_t *reduced_clock)
5607 {
5608         struct drm_device *dev = crtc->dev;
5609         struct drm_i915_private *dev_priv = dev->dev_private;
5610         struct intel_encoder *intel_encoder;
5611         int refclk;
5612         const intel_limit_t *limit;
5613         bool ret, is_lvds = false;
5614
5615         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5616                 switch (intel_encoder->type) {
5617                 case INTEL_OUTPUT_LVDS:
5618                         is_lvds = true;
5619                         break;
5620                 }
5621         }
5622
5623         refclk = ironlake_get_refclk(crtc);
5624
5625         /*
5626          * Returns a set of divisors for the desired target clock with the given
5627          * refclk, or FALSE.  The returned values represent the clock equation:
5628          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5629          */
5630         limit = intel_limit(crtc, refclk);
5631         ret = dev_priv->display.find_dpll(limit, crtc,
5632                                           to_intel_crtc(crtc)->config.port_clock,
5633                                           refclk, NULL, clock);
5634         if (!ret)
5635                 return false;
5636
5637         if (is_lvds && dev_priv->lvds_downclock_avail) {
5638                 /*
5639                  * Ensure we match the reduced clock's P to the target clock.
5640                  * If the clocks don't match, we can't switch the display clock
5641                  * by using the FP0/FP1. In such case we will disable the LVDS
5642                  * downclock feature.
5643                 */
5644                 *has_reduced_clock =
5645                         dev_priv->display.find_dpll(limit, crtc,
5646                                                     dev_priv->lvds_downclock,
5647                                                     refclk, clock,
5648                                                     reduced_clock);
5649         }
5650
5651         return true;
5652 }
5653
5654 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5655 {
5656         struct drm_i915_private *dev_priv = dev->dev_private;
5657         uint32_t temp;
5658
5659         temp = I915_READ(SOUTH_CHICKEN1);
5660         if (temp & FDI_BC_BIFURCATION_SELECT)
5661                 return;
5662
5663         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5664         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5665
5666         temp |= FDI_BC_BIFURCATION_SELECT;
5667         DRM_DEBUG_KMS("enabling fdi C rx\n");
5668         I915_WRITE(SOUTH_CHICKEN1, temp);
5669         POSTING_READ(SOUTH_CHICKEN1);
5670 }
5671
5672 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5673 {
5674         struct drm_device *dev = intel_crtc->base.dev;
5675         struct drm_i915_private *dev_priv = dev->dev_private;
5676
5677         switch (intel_crtc->pipe) {
5678         case PIPE_A:
5679                 break;
5680         case PIPE_B:
5681                 if (intel_crtc->config.fdi_lanes > 2)
5682                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5683                 else
5684                         cpt_enable_fdi_bc_bifurcation(dev);
5685
5686                 break;
5687         case PIPE_C:
5688                 cpt_enable_fdi_bc_bifurcation(dev);
5689
5690                 break;
5691         default:
5692                 BUG();
5693         }
5694 }
5695
5696 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5697 {
5698         /*
5699          * Account for spread spectrum to avoid
5700          * oversubscribing the link. Max center spread
5701          * is 2.5%; use 5% for safety's sake.
5702          */
5703         u32 bps = target_clock * bpp * 21 / 20;
5704         return bps / (link_bw * 8) + 1;
5705 }
5706
5707 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5708 {
5709         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5710 }
5711
5712 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5713                                       u32 *fp,
5714                                       intel_clock_t *reduced_clock, u32 *fp2)
5715 {
5716         struct drm_crtc *crtc = &intel_crtc->base;
5717         struct drm_device *dev = crtc->dev;
5718         struct drm_i915_private *dev_priv = dev->dev_private;
5719         struct intel_encoder *intel_encoder;
5720         uint32_t dpll;
5721         int factor, num_connectors = 0;
5722         bool is_lvds = false, is_sdvo = false;
5723
5724         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5725                 switch (intel_encoder->type) {
5726                 case INTEL_OUTPUT_LVDS:
5727                         is_lvds = true;
5728                         break;
5729                 case INTEL_OUTPUT_SDVO:
5730                 case INTEL_OUTPUT_HDMI:
5731                         is_sdvo = true;
5732                         break;
5733                 }
5734
5735                 num_connectors++;
5736         }
5737
5738         /* Enable autotuning of the PLL clock (if permissible) */
5739         factor = 21;
5740         if (is_lvds) {
5741                 if ((intel_panel_use_ssc(dev_priv) &&
5742                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5743                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5744                         factor = 25;
5745         } else if (intel_crtc->config.sdvo_tv_clock)
5746                 factor = 20;
5747
5748         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5749                 *fp |= FP_CB_TUNE;
5750
5751         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5752                 *fp2 |= FP_CB_TUNE;
5753
5754         dpll = 0;
5755
5756         if (is_lvds)
5757                 dpll |= DPLLB_MODE_LVDS;
5758         else
5759                 dpll |= DPLLB_MODE_DAC_SERIAL;
5760
5761         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5762                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5763
5764         if (is_sdvo)
5765                 dpll |= DPLL_SDVO_HIGH_SPEED;
5766         if (intel_crtc->config.has_dp_encoder)
5767                 dpll |= DPLL_SDVO_HIGH_SPEED;
5768
5769         /* compute bitmask from p1 value */
5770         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5771         /* also FPA1 */
5772         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5773
5774         switch (intel_crtc->config.dpll.p2) {
5775         case 5:
5776                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5777                 break;
5778         case 7:
5779                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5780                 break;
5781         case 10:
5782                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5783                 break;
5784         case 14:
5785                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5786                 break;
5787         }
5788
5789         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5790                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5791         else
5792                 dpll |= PLL_REF_INPUT_DREFCLK;
5793
5794         return dpll | DPLL_VCO_ENABLE;
5795 }
5796
5797 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5798                                   int x, int y,
5799                                   struct drm_framebuffer *fb)
5800 {
5801         struct drm_device *dev = crtc->dev;
5802         struct drm_i915_private *dev_priv = dev->dev_private;
5803         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5804         int pipe = intel_crtc->pipe;
5805         int plane = intel_crtc->plane;
5806         int num_connectors = 0;
5807         intel_clock_t clock, reduced_clock;
5808         u32 dpll = 0, fp = 0, fp2 = 0;
5809         bool ok, has_reduced_clock = false;
5810         bool is_lvds = false;
5811         struct intel_encoder *encoder;
5812         struct intel_shared_dpll *pll;
5813         int ret;
5814
5815         for_each_encoder_on_crtc(dev, crtc, encoder) {
5816                 switch (encoder->type) {
5817                 case INTEL_OUTPUT_LVDS:
5818                         is_lvds = true;
5819                         break;
5820                 }
5821
5822                 num_connectors++;
5823         }
5824
5825         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5826              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5827
5828         ok = ironlake_compute_clocks(crtc, &clock,
5829                                      &has_reduced_clock, &reduced_clock);
5830         if (!ok && !intel_crtc->config.clock_set) {
5831                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5832                 return -EINVAL;
5833         }
5834         /* Compat-code for transition, will disappear. */
5835         if (!intel_crtc->config.clock_set) {
5836                 intel_crtc->config.dpll.n = clock.n;
5837                 intel_crtc->config.dpll.m1 = clock.m1;
5838                 intel_crtc->config.dpll.m2 = clock.m2;
5839                 intel_crtc->config.dpll.p1 = clock.p1;
5840                 intel_crtc->config.dpll.p2 = clock.p2;
5841         }
5842
5843         /* Ensure that the cursor is valid for the new mode before changing... */
5844         intel_crtc_update_cursor(crtc, true);
5845
5846         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5847         if (intel_crtc->config.has_pch_encoder) {
5848                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5849                 if (has_reduced_clock)
5850                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5851
5852                 dpll = ironlake_compute_dpll(intel_crtc,
5853                                              &fp, &reduced_clock,
5854                                              has_reduced_clock ? &fp2 : NULL);
5855
5856                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5857                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5858                 if (has_reduced_clock)
5859                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5860                 else
5861                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5862
5863                 pll = intel_get_shared_dpll(intel_crtc);
5864                 if (pll == NULL) {
5865                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5866                                          pipe_name(pipe));
5867                         return -EINVAL;
5868                 }
5869         } else
5870                 intel_put_shared_dpll(intel_crtc);
5871
5872         if (intel_crtc->config.has_dp_encoder)
5873                 intel_dp_set_m_n(intel_crtc);
5874
5875         if (is_lvds && has_reduced_clock && i915_powersave)
5876                 intel_crtc->lowfreq_avail = true;
5877         else
5878                 intel_crtc->lowfreq_avail = false;
5879
5880         if (intel_crtc->config.has_pch_encoder) {
5881                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5882
5883         }
5884
5885         intel_set_pipe_timings(intel_crtc);
5886
5887         if (intel_crtc->config.has_pch_encoder) {
5888                 intel_cpu_transcoder_set_m_n(intel_crtc,
5889                                              &intel_crtc->config.fdi_m_n);
5890         }
5891
5892         if (IS_IVYBRIDGE(dev))
5893                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5894
5895         ironlake_set_pipeconf(crtc);
5896
5897         /* Set up the display plane register */
5898         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5899         POSTING_READ(DSPCNTR(plane));
5900
5901         ret = intel_pipe_set_base(crtc, x, y, fb);
5902
5903         return ret;
5904 }
5905
5906 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5907                                          struct intel_link_m_n *m_n)
5908 {
5909         struct drm_device *dev = crtc->base.dev;
5910         struct drm_i915_private *dev_priv = dev->dev_private;
5911         enum pipe pipe = crtc->pipe;
5912
5913         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5914         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5915         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5916                 & ~TU_SIZE_MASK;
5917         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5918         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
5919                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5920 }
5921
5922 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5923                                          enum transcoder transcoder,
5924                                          struct intel_link_m_n *m_n)
5925 {
5926         struct drm_device *dev = crtc->base.dev;
5927         struct drm_i915_private *dev_priv = dev->dev_private;
5928         enum pipe pipe = crtc->pipe;
5929
5930         if (INTEL_INFO(dev)->gen >= 5) {
5931                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
5932                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
5933                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5934                         & ~TU_SIZE_MASK;
5935                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5936                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5937                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5938         } else {
5939                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
5940                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
5941                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
5942                         & ~TU_SIZE_MASK;
5943                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
5944                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
5945                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5946         }
5947 }
5948
5949 void intel_dp_get_m_n(struct intel_crtc *crtc,
5950                       struct intel_crtc_config *pipe_config)
5951 {
5952         if (crtc->config.has_pch_encoder)
5953                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5954         else
5955                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5956                                              &pipe_config->dp_m_n);
5957 }
5958
5959 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5960                                         struct intel_crtc_config *pipe_config)
5961 {
5962         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5963                                      &pipe_config->fdi_m_n);
5964 }
5965
5966 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5967                                      struct intel_crtc_config *pipe_config)
5968 {
5969         struct drm_device *dev = crtc->base.dev;
5970         struct drm_i915_private *dev_priv = dev->dev_private;
5971         uint32_t tmp;
5972
5973         tmp = I915_READ(PF_CTL(crtc->pipe));
5974
5975         if (tmp & PF_ENABLE) {
5976                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5977                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5978
5979                 /* We currently do not free assignements of panel fitters on
5980                  * ivb/hsw (since we don't use the higher upscaling modes which
5981                  * differentiates them) so just WARN about this case for now. */
5982                 if (IS_GEN7(dev)) {
5983                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5984                                 PF_PIPE_SEL_IVB(crtc->pipe));
5985                 }
5986         }
5987 }
5988
5989 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5990                                      struct intel_crtc_config *pipe_config)
5991 {
5992         struct drm_device *dev = crtc->base.dev;
5993         struct drm_i915_private *dev_priv = dev->dev_private;
5994         uint32_t tmp;
5995
5996         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5997         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5998
5999         tmp = I915_READ(PIPECONF(crtc->pipe));
6000         if (!(tmp & PIPECONF_ENABLE))
6001                 return false;
6002
6003         switch (tmp & PIPECONF_BPC_MASK) {
6004         case PIPECONF_6BPC:
6005                 pipe_config->pipe_bpp = 18;
6006                 break;
6007         case PIPECONF_8BPC:
6008                 pipe_config->pipe_bpp = 24;
6009                 break;
6010         case PIPECONF_10BPC:
6011                 pipe_config->pipe_bpp = 30;
6012                 break;
6013         case PIPECONF_12BPC:
6014                 pipe_config->pipe_bpp = 36;
6015                 break;
6016         default:
6017                 break;
6018         }
6019
6020         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6021                 struct intel_shared_dpll *pll;
6022
6023                 pipe_config->has_pch_encoder = true;
6024
6025                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6026                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6027                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6028
6029                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6030
6031                 if (HAS_PCH_IBX(dev_priv->dev)) {
6032                         pipe_config->shared_dpll =
6033                                 (enum intel_dpll_id) crtc->pipe;
6034                 } else {
6035                         tmp = I915_READ(PCH_DPLL_SEL);
6036                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6037                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6038                         else
6039                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6040                 }
6041
6042                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6043
6044                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6045                                            &pipe_config->dpll_hw_state));
6046
6047                 tmp = pipe_config->dpll_hw_state.dpll;
6048                 pipe_config->pixel_multiplier =
6049                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6050                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6051
6052                 ironlake_pch_clock_get(crtc, pipe_config);
6053         } else {
6054                 pipe_config->pixel_multiplier = 1;
6055         }
6056
6057         intel_get_pipe_timings(crtc, pipe_config);
6058
6059         ironlake_get_pfit_config(crtc, pipe_config);
6060
6061         return true;
6062 }
6063
6064 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6065 {
6066         struct drm_device *dev = dev_priv->dev;
6067         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6068         struct intel_crtc *crtc;
6069         unsigned long irqflags;
6070         uint32_t val;
6071
6072         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6073                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6074                      pipe_name(crtc->pipe));
6075
6076         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6077         WARN(plls->spll_refcount, "SPLL enabled\n");
6078         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6079         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6080         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6081         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6082              "CPU PWM1 enabled\n");
6083         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6084              "CPU PWM2 enabled\n");
6085         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6086              "PCH PWM1 enabled\n");
6087         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6088              "Utility pin enabled\n");
6089         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6090
6091         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6092         val = I915_READ(DEIMR);
6093         WARN((val & ~DE_PCH_EVENT_IVB) != val,
6094              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6095         val = I915_READ(SDEIMR);
6096         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6097              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6098         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6099 }
6100
6101 /*
6102  * This function implements pieces of two sequences from BSpec:
6103  * - Sequence for display software to disable LCPLL
6104  * - Sequence for display software to allow package C8+
6105  * The steps implemented here are just the steps that actually touch the LCPLL
6106  * register. Callers should take care of disabling all the display engine
6107  * functions, doing the mode unset, fixing interrupts, etc.
6108  */
6109 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6110                        bool switch_to_fclk, bool allow_power_down)
6111 {
6112         uint32_t val;
6113
6114         assert_can_disable_lcpll(dev_priv);
6115
6116         val = I915_READ(LCPLL_CTL);
6117
6118         if (switch_to_fclk) {
6119                 val |= LCPLL_CD_SOURCE_FCLK;
6120                 I915_WRITE(LCPLL_CTL, val);
6121
6122                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6123                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6124                         DRM_ERROR("Switching to FCLK failed\n");
6125
6126                 val = I915_READ(LCPLL_CTL);
6127         }
6128
6129         val |= LCPLL_PLL_DISABLE;
6130         I915_WRITE(LCPLL_CTL, val);
6131         POSTING_READ(LCPLL_CTL);
6132
6133         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6134                 DRM_ERROR("LCPLL still locked\n");
6135
6136         val = I915_READ(D_COMP);
6137         val |= D_COMP_COMP_DISABLE;
6138         I915_WRITE(D_COMP, val);
6139         POSTING_READ(D_COMP);
6140         ndelay(100);
6141
6142         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6143                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6144
6145         if (allow_power_down) {
6146                 val = I915_READ(LCPLL_CTL);
6147                 val |= LCPLL_POWER_DOWN_ALLOW;
6148                 I915_WRITE(LCPLL_CTL, val);
6149                 POSTING_READ(LCPLL_CTL);
6150         }
6151 }
6152
6153 /*
6154  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6155  * source.
6156  */
6157 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6158 {
6159         uint32_t val;
6160
6161         val = I915_READ(LCPLL_CTL);
6162
6163         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6164                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6165                 return;
6166
6167         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6168          * we'll hang the machine! */
6169         dev_priv->uncore.funcs.force_wake_get(dev_priv);
6170
6171         if (val & LCPLL_POWER_DOWN_ALLOW) {
6172                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6173                 I915_WRITE(LCPLL_CTL, val);
6174                 POSTING_READ(LCPLL_CTL);
6175         }
6176
6177         val = I915_READ(D_COMP);
6178         val |= D_COMP_COMP_FORCE;
6179         val &= ~D_COMP_COMP_DISABLE;
6180         I915_WRITE(D_COMP, val);
6181         POSTING_READ(D_COMP);
6182
6183         val = I915_READ(LCPLL_CTL);
6184         val &= ~LCPLL_PLL_DISABLE;
6185         I915_WRITE(LCPLL_CTL, val);
6186
6187         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6188                 DRM_ERROR("LCPLL not locked yet\n");
6189
6190         if (val & LCPLL_CD_SOURCE_FCLK) {
6191                 val = I915_READ(LCPLL_CTL);
6192                 val &= ~LCPLL_CD_SOURCE_FCLK;
6193                 I915_WRITE(LCPLL_CTL, val);
6194
6195                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6196                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6197                         DRM_ERROR("Switching back to LCPLL failed\n");
6198         }
6199
6200         dev_priv->uncore.funcs.force_wake_put(dev_priv);
6201 }
6202
6203 void hsw_enable_pc8_work(struct work_struct *__work)
6204 {
6205         struct drm_i915_private *dev_priv =
6206                 container_of(to_delayed_work(__work), struct drm_i915_private,
6207                              pc8.enable_work);
6208         struct drm_device *dev = dev_priv->dev;
6209         uint32_t val;
6210
6211         if (dev_priv->pc8.enabled)
6212                 return;
6213
6214         DRM_DEBUG_KMS("Enabling package C8+\n");
6215
6216         dev_priv->pc8.enabled = true;
6217
6218         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6219                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6220                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6221                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6222         }
6223
6224         lpt_disable_clkout_dp(dev);
6225         hsw_pc8_disable_interrupts(dev);
6226         hsw_disable_lcpll(dev_priv, true, true);
6227 }
6228
6229 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6230 {
6231         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6232         WARN(dev_priv->pc8.disable_count < 1,
6233              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6234
6235         dev_priv->pc8.disable_count--;
6236         if (dev_priv->pc8.disable_count != 0)
6237                 return;
6238
6239         schedule_delayed_work(&dev_priv->pc8.enable_work,
6240                               msecs_to_jiffies(i915_pc8_timeout));
6241 }
6242
6243 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6244 {
6245         struct drm_device *dev = dev_priv->dev;
6246         uint32_t val;
6247
6248         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6249         WARN(dev_priv->pc8.disable_count < 0,
6250              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6251
6252         dev_priv->pc8.disable_count++;
6253         if (dev_priv->pc8.disable_count != 1)
6254                 return;
6255
6256         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6257         if (!dev_priv->pc8.enabled)
6258                 return;
6259
6260         DRM_DEBUG_KMS("Disabling package C8+\n");
6261
6262         hsw_restore_lcpll(dev_priv);
6263         hsw_pc8_restore_interrupts(dev);
6264         lpt_init_pch_refclk(dev);
6265
6266         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6267                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6268                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6269                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6270         }
6271
6272         intel_prepare_ddi(dev);
6273         i915_gem_init_swizzling(dev);
6274         mutex_lock(&dev_priv->rps.hw_lock);
6275         gen6_update_ring_freq(dev);
6276         mutex_unlock(&dev_priv->rps.hw_lock);
6277         dev_priv->pc8.enabled = false;
6278 }
6279
6280 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6281 {
6282         mutex_lock(&dev_priv->pc8.lock);
6283         __hsw_enable_package_c8(dev_priv);
6284         mutex_unlock(&dev_priv->pc8.lock);
6285 }
6286
6287 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6288 {
6289         mutex_lock(&dev_priv->pc8.lock);
6290         __hsw_disable_package_c8(dev_priv);
6291         mutex_unlock(&dev_priv->pc8.lock);
6292 }
6293
6294 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6295 {
6296         struct drm_device *dev = dev_priv->dev;
6297         struct intel_crtc *crtc;
6298         uint32_t val;
6299
6300         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6301                 if (crtc->base.enabled)
6302                         return false;
6303
6304         /* This case is still possible since we have the i915.disable_power_well
6305          * parameter and also the KVMr or something else might be requesting the
6306          * power well. */
6307         val = I915_READ(HSW_PWR_WELL_DRIVER);
6308         if (val != 0) {
6309                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6310                 return false;
6311         }
6312
6313         return true;
6314 }
6315
6316 /* Since we're called from modeset_global_resources there's no way to
6317  * symmetrically increase and decrease the refcount, so we use
6318  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6319  * or not.
6320  */
6321 static void hsw_update_package_c8(struct drm_device *dev)
6322 {
6323         struct drm_i915_private *dev_priv = dev->dev_private;
6324         bool allow;
6325
6326         if (!i915_enable_pc8)
6327                 return;
6328
6329         mutex_lock(&dev_priv->pc8.lock);
6330
6331         allow = hsw_can_enable_package_c8(dev_priv);
6332
6333         if (allow == dev_priv->pc8.requirements_met)
6334                 goto done;
6335
6336         dev_priv->pc8.requirements_met = allow;
6337
6338         if (allow)
6339                 __hsw_enable_package_c8(dev_priv);
6340         else
6341                 __hsw_disable_package_c8(dev_priv);
6342
6343 done:
6344         mutex_unlock(&dev_priv->pc8.lock);
6345 }
6346
6347 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6348 {
6349         if (!dev_priv->pc8.gpu_idle) {
6350                 dev_priv->pc8.gpu_idle = true;
6351                 hsw_enable_package_c8(dev_priv);
6352         }
6353 }
6354
6355 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6356 {
6357         if (dev_priv->pc8.gpu_idle) {
6358                 dev_priv->pc8.gpu_idle = false;
6359                 hsw_disable_package_c8(dev_priv);
6360         }
6361 }
6362
6363 static void haswell_modeset_global_resources(struct drm_device *dev)
6364 {
6365         bool enable = false;
6366         struct intel_crtc *crtc;
6367
6368         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6369                 if (!crtc->base.enabled)
6370                         continue;
6371
6372                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6373                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6374                         enable = true;
6375         }
6376
6377         intel_set_power_well(dev, enable);
6378
6379         hsw_update_package_c8(dev);
6380 }
6381
6382 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6383                                  int x, int y,
6384                                  struct drm_framebuffer *fb)
6385 {
6386         struct drm_device *dev = crtc->dev;
6387         struct drm_i915_private *dev_priv = dev->dev_private;
6388         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6389         int plane = intel_crtc->plane;
6390         int ret;
6391
6392         if (!intel_ddi_pll_mode_set(crtc))
6393                 return -EINVAL;
6394
6395         /* Ensure that the cursor is valid for the new mode before changing... */
6396         intel_crtc_update_cursor(crtc, true);
6397
6398         if (intel_crtc->config.has_dp_encoder)
6399                 intel_dp_set_m_n(intel_crtc);
6400
6401         intel_crtc->lowfreq_avail = false;
6402
6403         intel_set_pipe_timings(intel_crtc);
6404
6405         if (intel_crtc->config.has_pch_encoder) {
6406                 intel_cpu_transcoder_set_m_n(intel_crtc,
6407                                              &intel_crtc->config.fdi_m_n);
6408         }
6409
6410         haswell_set_pipeconf(crtc);
6411
6412         intel_set_pipe_csc(crtc);
6413
6414         /* Set up the display plane register */
6415         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6416         POSTING_READ(DSPCNTR(plane));
6417
6418         ret = intel_pipe_set_base(crtc, x, y, fb);
6419
6420         return ret;
6421 }
6422
6423 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6424                                     struct intel_crtc_config *pipe_config)
6425 {
6426         struct drm_device *dev = crtc->base.dev;
6427         struct drm_i915_private *dev_priv = dev->dev_private;
6428         enum intel_display_power_domain pfit_domain;
6429         uint32_t tmp;
6430
6431         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6432         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6433
6434         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6435         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6436                 enum pipe trans_edp_pipe;
6437                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6438                 default:
6439                         WARN(1, "unknown pipe linked to edp transcoder\n");
6440                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6441                 case TRANS_DDI_EDP_INPUT_A_ON:
6442                         trans_edp_pipe = PIPE_A;
6443                         break;
6444                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6445                         trans_edp_pipe = PIPE_B;
6446                         break;
6447                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6448                         trans_edp_pipe = PIPE_C;
6449                         break;
6450                 }
6451
6452                 if (trans_edp_pipe == crtc->pipe)
6453                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6454         }
6455
6456         if (!intel_display_power_enabled(dev,
6457                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6458                 return false;
6459
6460         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6461         if (!(tmp & PIPECONF_ENABLE))
6462                 return false;
6463
6464         /*
6465          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6466          * DDI E. So just check whether this pipe is wired to DDI E and whether
6467          * the PCH transcoder is on.
6468          */
6469         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6470         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6471             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6472                 pipe_config->has_pch_encoder = true;
6473
6474                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6475                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6476                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6477
6478                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6479         }
6480
6481         intel_get_pipe_timings(crtc, pipe_config);
6482
6483         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6484         if (intel_display_power_enabled(dev, pfit_domain))
6485                 ironlake_get_pfit_config(crtc, pipe_config);
6486
6487         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6488                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6489
6490         pipe_config->pixel_multiplier = 1;
6491
6492         return true;
6493 }
6494
6495 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6496                                int x, int y,
6497                                struct drm_framebuffer *fb)
6498 {
6499         struct drm_device *dev = crtc->dev;
6500         struct drm_i915_private *dev_priv = dev->dev_private;
6501         struct intel_encoder *encoder;
6502         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6503         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6504         int pipe = intel_crtc->pipe;
6505         int ret;
6506
6507         drm_vblank_pre_modeset(dev, pipe);
6508
6509         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6510
6511         drm_vblank_post_modeset(dev, pipe);
6512
6513         if (ret != 0)
6514                 return ret;
6515
6516         for_each_encoder_on_crtc(dev, crtc, encoder) {
6517                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6518                         encoder->base.base.id,
6519                         drm_get_encoder_name(&encoder->base),
6520                         mode->base.id, mode->name);
6521                 encoder->mode_set(encoder);
6522         }
6523
6524         return 0;
6525 }
6526
6527 static bool intel_eld_uptodate(struct drm_connector *connector,
6528                                int reg_eldv, uint32_t bits_eldv,
6529                                int reg_elda, uint32_t bits_elda,
6530                                int reg_edid)
6531 {
6532         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6533         uint8_t *eld = connector->eld;
6534         uint32_t i;
6535
6536         i = I915_READ(reg_eldv);
6537         i &= bits_eldv;
6538
6539         if (!eld[0])
6540                 return !i;
6541
6542         if (!i)
6543                 return false;
6544
6545         i = I915_READ(reg_elda);
6546         i &= ~bits_elda;
6547         I915_WRITE(reg_elda, i);
6548
6549         for (i = 0; i < eld[2]; i++)
6550                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6551                         return false;
6552
6553         return true;
6554 }
6555
6556 static void g4x_write_eld(struct drm_connector *connector,
6557                           struct drm_crtc *crtc)
6558 {
6559         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6560         uint8_t *eld = connector->eld;
6561         uint32_t eldv;
6562         uint32_t len;
6563         uint32_t i;
6564
6565         i = I915_READ(G4X_AUD_VID_DID);
6566
6567         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6568                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6569         else
6570                 eldv = G4X_ELDV_DEVCTG;
6571
6572         if (intel_eld_uptodate(connector,
6573                                G4X_AUD_CNTL_ST, eldv,
6574                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6575                                G4X_HDMIW_HDMIEDID))
6576                 return;
6577
6578         i = I915_READ(G4X_AUD_CNTL_ST);
6579         i &= ~(eldv | G4X_ELD_ADDR);
6580         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6581         I915_WRITE(G4X_AUD_CNTL_ST, i);
6582
6583         if (!eld[0])
6584                 return;
6585
6586         len = min_t(uint8_t, eld[2], len);
6587         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6588         for (i = 0; i < len; i++)
6589                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6590
6591         i = I915_READ(G4X_AUD_CNTL_ST);
6592         i |= eldv;
6593         I915_WRITE(G4X_AUD_CNTL_ST, i);
6594 }
6595
6596 static void haswell_write_eld(struct drm_connector *connector,
6597                                      struct drm_crtc *crtc)
6598 {
6599         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6600         uint8_t *eld = connector->eld;
6601         struct drm_device *dev = crtc->dev;
6602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6603         uint32_t eldv;
6604         uint32_t i;
6605         int len;
6606         int pipe = to_intel_crtc(crtc)->pipe;
6607         int tmp;
6608
6609         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6610         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6611         int aud_config = HSW_AUD_CFG(pipe);
6612         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6613
6614
6615         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6616
6617         /* Audio output enable */
6618         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6619         tmp = I915_READ(aud_cntrl_st2);
6620         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6621         I915_WRITE(aud_cntrl_st2, tmp);
6622
6623         /* Wait for 1 vertical blank */
6624         intel_wait_for_vblank(dev, pipe);
6625
6626         /* Set ELD valid state */
6627         tmp = I915_READ(aud_cntrl_st2);
6628         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6629         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6630         I915_WRITE(aud_cntrl_st2, tmp);
6631         tmp = I915_READ(aud_cntrl_st2);
6632         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6633
6634         /* Enable HDMI mode */
6635         tmp = I915_READ(aud_config);
6636         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6637         /* clear N_programing_enable and N_value_index */
6638         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6639         I915_WRITE(aud_config, tmp);
6640
6641         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6642
6643         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6644         intel_crtc->eld_vld = true;
6645
6646         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6647                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6648                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6649                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6650         } else
6651                 I915_WRITE(aud_config, 0);
6652
6653         if (intel_eld_uptodate(connector,
6654                                aud_cntrl_st2, eldv,
6655                                aud_cntl_st, IBX_ELD_ADDRESS,
6656                                hdmiw_hdmiedid))
6657                 return;
6658
6659         i = I915_READ(aud_cntrl_st2);
6660         i &= ~eldv;
6661         I915_WRITE(aud_cntrl_st2, i);
6662
6663         if (!eld[0])
6664                 return;
6665
6666         i = I915_READ(aud_cntl_st);
6667         i &= ~IBX_ELD_ADDRESS;
6668         I915_WRITE(aud_cntl_st, i);
6669         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6670         DRM_DEBUG_DRIVER("port num:%d\n", i);
6671
6672         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6673         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6674         for (i = 0; i < len; i++)
6675                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6676
6677         i = I915_READ(aud_cntrl_st2);
6678         i |= eldv;
6679         I915_WRITE(aud_cntrl_st2, i);
6680
6681 }
6682
6683 static void ironlake_write_eld(struct drm_connector *connector,
6684                                      struct drm_crtc *crtc)
6685 {
6686         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6687         uint8_t *eld = connector->eld;
6688         uint32_t eldv;
6689         uint32_t i;
6690         int len;
6691         int hdmiw_hdmiedid;
6692         int aud_config;
6693         int aud_cntl_st;
6694         int aud_cntrl_st2;
6695         int pipe = to_intel_crtc(crtc)->pipe;
6696
6697         if (HAS_PCH_IBX(connector->dev)) {
6698                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6699                 aud_config = IBX_AUD_CFG(pipe);
6700                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6701                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6702         } else {
6703                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6704                 aud_config = CPT_AUD_CFG(pipe);
6705                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6706                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6707         }
6708
6709         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6710
6711         i = I915_READ(aud_cntl_st);
6712         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6713         if (!i) {
6714                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6715                 /* operate blindly on all ports */
6716                 eldv = IBX_ELD_VALIDB;
6717                 eldv |= IBX_ELD_VALIDB << 4;
6718                 eldv |= IBX_ELD_VALIDB << 8;
6719         } else {
6720                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6721                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6722         }
6723
6724         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6725                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6726                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6727                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6728         } else
6729                 I915_WRITE(aud_config, 0);
6730
6731         if (intel_eld_uptodate(connector,
6732                                aud_cntrl_st2, eldv,
6733                                aud_cntl_st, IBX_ELD_ADDRESS,
6734                                hdmiw_hdmiedid))
6735                 return;
6736
6737         i = I915_READ(aud_cntrl_st2);
6738         i &= ~eldv;
6739         I915_WRITE(aud_cntrl_st2, i);
6740
6741         if (!eld[0])
6742                 return;
6743
6744         i = I915_READ(aud_cntl_st);
6745         i &= ~IBX_ELD_ADDRESS;
6746         I915_WRITE(aud_cntl_st, i);
6747
6748         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6749         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6750         for (i = 0; i < len; i++)
6751                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6752
6753         i = I915_READ(aud_cntrl_st2);
6754         i |= eldv;
6755         I915_WRITE(aud_cntrl_st2, i);
6756 }
6757
6758 void intel_write_eld(struct drm_encoder *encoder,
6759                      struct drm_display_mode *mode)
6760 {
6761         struct drm_crtc *crtc = encoder->crtc;
6762         struct drm_connector *connector;
6763         struct drm_device *dev = encoder->dev;
6764         struct drm_i915_private *dev_priv = dev->dev_private;
6765
6766         connector = drm_select_eld(encoder, mode);
6767         if (!connector)
6768                 return;
6769
6770         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6771                          connector->base.id,
6772                          drm_get_connector_name(connector),
6773                          connector->encoder->base.id,
6774                          drm_get_encoder_name(connector->encoder));
6775
6776         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6777
6778         if (dev_priv->display.write_eld)
6779                 dev_priv->display.write_eld(connector, crtc);
6780 }
6781
6782 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6783 void intel_crtc_load_lut(struct drm_crtc *crtc)
6784 {
6785         struct drm_device *dev = crtc->dev;
6786         struct drm_i915_private *dev_priv = dev->dev_private;
6787         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6788         enum pipe pipe = intel_crtc->pipe;
6789         int palreg = PALETTE(pipe);
6790         int i;
6791         bool reenable_ips = false;
6792
6793         /* The clocks have to be on to load the palette. */
6794         if (!crtc->enabled || !intel_crtc->active)
6795                 return;
6796
6797         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6798                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6799                         assert_dsi_pll_enabled(dev_priv);
6800                 else
6801                         assert_pll_enabled(dev_priv, pipe);
6802         }
6803
6804         /* use legacy palette for Ironlake */
6805         if (HAS_PCH_SPLIT(dev))
6806                 palreg = LGC_PALETTE(pipe);
6807
6808         /* Workaround : Do not read or write the pipe palette/gamma data while
6809          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6810          */
6811         if (intel_crtc->config.ips_enabled &&
6812             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6813              GAMMA_MODE_MODE_SPLIT)) {
6814                 hsw_disable_ips(intel_crtc);
6815                 reenable_ips = true;
6816         }
6817
6818         for (i = 0; i < 256; i++) {
6819                 I915_WRITE(palreg + 4 * i,
6820                            (intel_crtc->lut_r[i] << 16) |
6821                            (intel_crtc->lut_g[i] << 8) |
6822                            intel_crtc->lut_b[i]);
6823         }
6824
6825         if (reenable_ips)
6826                 hsw_enable_ips(intel_crtc);
6827 }
6828
6829 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6830 {
6831         struct drm_device *dev = crtc->dev;
6832         struct drm_i915_private *dev_priv = dev->dev_private;
6833         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6834         bool visible = base != 0;
6835         u32 cntl;
6836
6837         if (intel_crtc->cursor_visible == visible)
6838                 return;
6839
6840         cntl = I915_READ(_CURACNTR);
6841         if (visible) {
6842                 /* On these chipsets we can only modify the base whilst
6843                  * the cursor is disabled.
6844                  */
6845                 I915_WRITE(_CURABASE, base);
6846
6847                 cntl &= ~(CURSOR_FORMAT_MASK);
6848                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6849                 cntl |= CURSOR_ENABLE |
6850                         CURSOR_GAMMA_ENABLE |
6851                         CURSOR_FORMAT_ARGB;
6852         } else
6853                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6854         I915_WRITE(_CURACNTR, cntl);
6855
6856         intel_crtc->cursor_visible = visible;
6857 }
6858
6859 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6860 {
6861         struct drm_device *dev = crtc->dev;
6862         struct drm_i915_private *dev_priv = dev->dev_private;
6863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6864         int pipe = intel_crtc->pipe;
6865         bool visible = base != 0;
6866
6867         if (intel_crtc->cursor_visible != visible) {
6868                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6869                 if (base) {
6870                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6871                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6872                         cntl |= pipe << 28; /* Connect to correct pipe */
6873                 } else {
6874                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6875                         cntl |= CURSOR_MODE_DISABLE;
6876                 }
6877                 I915_WRITE(CURCNTR(pipe), cntl);
6878
6879                 intel_crtc->cursor_visible = visible;
6880         }
6881         /* and commit changes on next vblank */
6882         I915_WRITE(CURBASE(pipe), base);
6883 }
6884
6885 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6886 {
6887         struct drm_device *dev = crtc->dev;
6888         struct drm_i915_private *dev_priv = dev->dev_private;
6889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6890         int pipe = intel_crtc->pipe;
6891         bool visible = base != 0;
6892
6893         if (intel_crtc->cursor_visible != visible) {
6894                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6895                 if (base) {
6896                         cntl &= ~CURSOR_MODE;
6897                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6898                 } else {
6899                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6900                         cntl |= CURSOR_MODE_DISABLE;
6901                 }
6902                 if (IS_HASWELL(dev)) {
6903                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6904                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6905                 }
6906                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6907
6908                 intel_crtc->cursor_visible = visible;
6909         }
6910         /* and commit changes on next vblank */
6911         I915_WRITE(CURBASE_IVB(pipe), base);
6912 }
6913
6914 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6915 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6916                                      bool on)
6917 {
6918         struct drm_device *dev = crtc->dev;
6919         struct drm_i915_private *dev_priv = dev->dev_private;
6920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6921         int pipe = intel_crtc->pipe;
6922         int x = intel_crtc->cursor_x;
6923         int y = intel_crtc->cursor_y;
6924         u32 base = 0, pos = 0;
6925         bool visible;
6926
6927         if (on)
6928                 base = intel_crtc->cursor_addr;
6929
6930         if (x >= intel_crtc->config.pipe_src_w)
6931                 base = 0;
6932
6933         if (y >= intel_crtc->config.pipe_src_h)
6934                 base = 0;
6935
6936         if (x < 0) {
6937                 if (x + intel_crtc->cursor_width <= 0)
6938                         base = 0;
6939
6940                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6941                 x = -x;
6942         }
6943         pos |= x << CURSOR_X_SHIFT;
6944
6945         if (y < 0) {
6946                 if (y + intel_crtc->cursor_height <= 0)
6947                         base = 0;
6948
6949                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6950                 y = -y;
6951         }
6952         pos |= y << CURSOR_Y_SHIFT;
6953
6954         visible = base != 0;
6955         if (!visible && !intel_crtc->cursor_visible)
6956                 return;
6957
6958         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6959                 I915_WRITE(CURPOS_IVB(pipe), pos);
6960                 ivb_update_cursor(crtc, base);
6961         } else {
6962                 I915_WRITE(CURPOS(pipe), pos);
6963                 if (IS_845G(dev) || IS_I865G(dev))
6964                         i845_update_cursor(crtc, base);
6965                 else
6966                         i9xx_update_cursor(crtc, base);
6967         }
6968 }
6969
6970 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6971                                  struct drm_file *file,
6972                                  uint32_t handle,
6973                                  uint32_t width, uint32_t height)
6974 {
6975         struct drm_device *dev = crtc->dev;
6976         struct drm_i915_private *dev_priv = dev->dev_private;
6977         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6978         struct drm_i915_gem_object *obj;
6979         uint32_t addr;
6980         int ret;
6981
6982         /* if we want to turn off the cursor ignore width and height */
6983         if (!handle) {
6984                 DRM_DEBUG_KMS("cursor off\n");
6985                 addr = 0;
6986                 obj = NULL;
6987                 mutex_lock(&dev->struct_mutex);
6988                 goto finish;
6989         }
6990
6991         /* Currently we only support 64x64 cursors */
6992         if (width != 64 || height != 64) {
6993                 DRM_ERROR("we currently only support 64x64 cursors\n");
6994                 return -EINVAL;
6995         }
6996
6997         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6998         if (&obj->base == NULL)
6999                 return -ENOENT;
7000
7001         if (obj->base.size < width * height * 4) {
7002                 DRM_ERROR("buffer is to small\n");
7003                 ret = -ENOMEM;
7004                 goto fail;
7005         }
7006
7007         /* we only need to pin inside GTT if cursor is non-phy */
7008         mutex_lock(&dev->struct_mutex);
7009         if (!dev_priv->info->cursor_needs_physical) {
7010                 unsigned alignment;
7011
7012                 if (obj->tiling_mode) {
7013                         DRM_ERROR("cursor cannot be tiled\n");
7014                         ret = -EINVAL;
7015                         goto fail_locked;
7016                 }
7017
7018                 /* Note that the w/a also requires 2 PTE of padding following
7019                  * the bo. We currently fill all unused PTE with the shadow
7020                  * page and so we should always have valid PTE following the
7021                  * cursor preventing the VT-d warning.
7022                  */
7023                 alignment = 0;
7024                 if (need_vtd_wa(dev))
7025                         alignment = 64*1024;
7026
7027                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7028                 if (ret) {
7029                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7030                         goto fail_locked;
7031                 }
7032
7033                 ret = i915_gem_object_put_fence(obj);
7034                 if (ret) {
7035                         DRM_ERROR("failed to release fence for cursor");
7036                         goto fail_unpin;
7037                 }
7038
7039                 addr = i915_gem_obj_ggtt_offset(obj);
7040         } else {
7041                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7042                 ret = i915_gem_attach_phys_object(dev, obj,
7043                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7044                                                   align);
7045                 if (ret) {
7046                         DRM_ERROR("failed to attach phys object\n");
7047                         goto fail_locked;
7048                 }
7049                 addr = obj->phys_obj->handle->busaddr;
7050         }
7051
7052         if (IS_GEN2(dev))
7053                 I915_WRITE(CURSIZE, (height << 12) | width);
7054
7055  finish:
7056         if (intel_crtc->cursor_bo) {
7057                 if (dev_priv->info->cursor_needs_physical) {
7058                         if (intel_crtc->cursor_bo != obj)
7059                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7060                 } else
7061                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7062                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7063         }
7064
7065         mutex_unlock(&dev->struct_mutex);
7066
7067         intel_crtc->cursor_addr = addr;
7068         intel_crtc->cursor_bo = obj;
7069         intel_crtc->cursor_width = width;
7070         intel_crtc->cursor_height = height;
7071
7072         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7073
7074         return 0;
7075 fail_unpin:
7076         i915_gem_object_unpin_from_display_plane(obj);
7077 fail_locked:
7078         mutex_unlock(&dev->struct_mutex);
7079 fail:
7080         drm_gem_object_unreference_unlocked(&obj->base);
7081         return ret;
7082 }
7083
7084 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7085 {
7086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7087
7088         intel_crtc->cursor_x = x;
7089         intel_crtc->cursor_y = y;
7090
7091         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7092
7093         return 0;
7094 }
7095
7096 /** Sets the color ramps on behalf of RandR */
7097 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7098                                  u16 blue, int regno)
7099 {
7100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7101
7102         intel_crtc->lut_r[regno] = red >> 8;
7103         intel_crtc->lut_g[regno] = green >> 8;
7104         intel_crtc->lut_b[regno] = blue >> 8;
7105 }
7106
7107 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7108                              u16 *blue, int regno)
7109 {
7110         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7111
7112         *red = intel_crtc->lut_r[regno] << 8;
7113         *green = intel_crtc->lut_g[regno] << 8;
7114         *blue = intel_crtc->lut_b[regno] << 8;
7115 }
7116
7117 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7118                                  u16 *blue, uint32_t start, uint32_t size)
7119 {
7120         int end = (start + size > 256) ? 256 : start + size, i;
7121         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7122
7123         for (i = start; i < end; i++) {
7124                 intel_crtc->lut_r[i] = red[i] >> 8;
7125                 intel_crtc->lut_g[i] = green[i] >> 8;
7126                 intel_crtc->lut_b[i] = blue[i] >> 8;
7127         }
7128
7129         intel_crtc_load_lut(crtc);
7130 }
7131
7132 /* VESA 640x480x72Hz mode to set on the pipe */
7133 static struct drm_display_mode load_detect_mode = {
7134         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7135                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7136 };
7137
7138 static struct drm_framebuffer *
7139 intel_framebuffer_create(struct drm_device *dev,
7140                          struct drm_mode_fb_cmd2 *mode_cmd,
7141                          struct drm_i915_gem_object *obj)
7142 {
7143         struct intel_framebuffer *intel_fb;
7144         int ret;
7145
7146         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7147         if (!intel_fb) {
7148                 drm_gem_object_unreference_unlocked(&obj->base);
7149                 return ERR_PTR(-ENOMEM);
7150         }
7151
7152         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7153         if (ret) {
7154                 drm_gem_object_unreference_unlocked(&obj->base);
7155                 kfree(intel_fb);
7156                 return ERR_PTR(ret);
7157         }
7158
7159         return &intel_fb->base;
7160 }
7161
7162 static u32
7163 intel_framebuffer_pitch_for_width(int width, int bpp)
7164 {
7165         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7166         return ALIGN(pitch, 64);
7167 }
7168
7169 static u32
7170 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7171 {
7172         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7173         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7174 }
7175
7176 static struct drm_framebuffer *
7177 intel_framebuffer_create_for_mode(struct drm_device *dev,
7178                                   struct drm_display_mode *mode,
7179                                   int depth, int bpp)
7180 {
7181         struct drm_i915_gem_object *obj;
7182         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7183
7184         obj = i915_gem_alloc_object(dev,
7185                                     intel_framebuffer_size_for_mode(mode, bpp));
7186         if (obj == NULL)
7187                 return ERR_PTR(-ENOMEM);
7188
7189         mode_cmd.width = mode->hdisplay;
7190         mode_cmd.height = mode->vdisplay;
7191         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7192                                                                 bpp);
7193         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7194
7195         return intel_framebuffer_create(dev, &mode_cmd, obj);
7196 }
7197
7198 static struct drm_framebuffer *
7199 mode_fits_in_fbdev(struct drm_device *dev,
7200                    struct drm_display_mode *mode)
7201 {
7202         struct drm_i915_private *dev_priv = dev->dev_private;
7203         struct drm_i915_gem_object *obj;
7204         struct drm_framebuffer *fb;
7205
7206         if (dev_priv->fbdev == NULL)
7207                 return NULL;
7208
7209         obj = dev_priv->fbdev->ifb.obj;
7210         if (obj == NULL)
7211                 return NULL;
7212
7213         fb = &dev_priv->fbdev->ifb.base;
7214         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7215                                                                fb->bits_per_pixel))
7216                 return NULL;
7217
7218         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7219                 return NULL;
7220
7221         return fb;
7222 }
7223
7224 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7225                                 struct drm_display_mode *mode,
7226                                 struct intel_load_detect_pipe *old)
7227 {
7228         struct intel_crtc *intel_crtc;
7229         struct intel_encoder *intel_encoder =
7230                 intel_attached_encoder(connector);
7231         struct drm_crtc *possible_crtc;
7232         struct drm_encoder *encoder = &intel_encoder->base;
7233         struct drm_crtc *crtc = NULL;
7234         struct drm_device *dev = encoder->dev;
7235         struct drm_framebuffer *fb;
7236         int i = -1;
7237
7238         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7239                       connector->base.id, drm_get_connector_name(connector),
7240                       encoder->base.id, drm_get_encoder_name(encoder));
7241
7242         /*
7243          * Algorithm gets a little messy:
7244          *
7245          *   - if the connector already has an assigned crtc, use it (but make
7246          *     sure it's on first)
7247          *
7248          *   - try to find the first unused crtc that can drive this connector,
7249          *     and use that if we find one
7250          */
7251
7252         /* See if we already have a CRTC for this connector */
7253         if (encoder->crtc) {
7254                 crtc = encoder->crtc;
7255
7256                 mutex_lock(&crtc->mutex);
7257
7258                 old->dpms_mode = connector->dpms;
7259                 old->load_detect_temp = false;
7260
7261                 /* Make sure the crtc and connector are running */
7262                 if (connector->dpms != DRM_MODE_DPMS_ON)
7263                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7264
7265                 return true;
7266         }
7267
7268         /* Find an unused one (if possible) */
7269         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7270                 i++;
7271                 if (!(encoder->possible_crtcs & (1 << i)))
7272                         continue;
7273                 if (!possible_crtc->enabled) {
7274                         crtc = possible_crtc;
7275                         break;
7276                 }
7277         }
7278
7279         /*
7280          * If we didn't find an unused CRTC, don't use any.
7281          */
7282         if (!crtc) {
7283                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7284                 return false;
7285         }
7286
7287         mutex_lock(&crtc->mutex);
7288         intel_encoder->new_crtc = to_intel_crtc(crtc);
7289         to_intel_connector(connector)->new_encoder = intel_encoder;
7290
7291         intel_crtc = to_intel_crtc(crtc);
7292         old->dpms_mode = connector->dpms;
7293         old->load_detect_temp = true;
7294         old->release_fb = NULL;
7295
7296         if (!mode)
7297                 mode = &load_detect_mode;
7298
7299         /* We need a framebuffer large enough to accommodate all accesses
7300          * that the plane may generate whilst we perform load detection.
7301          * We can not rely on the fbcon either being present (we get called
7302          * during its initialisation to detect all boot displays, or it may
7303          * not even exist) or that it is large enough to satisfy the
7304          * requested mode.
7305          */
7306         fb = mode_fits_in_fbdev(dev, mode);
7307         if (fb == NULL) {
7308                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7309                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7310                 old->release_fb = fb;
7311         } else
7312                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7313         if (IS_ERR(fb)) {
7314                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7315                 mutex_unlock(&crtc->mutex);
7316                 return false;
7317         }
7318
7319         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7320                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7321                 if (old->release_fb)
7322                         old->release_fb->funcs->destroy(old->release_fb);
7323                 mutex_unlock(&crtc->mutex);
7324                 return false;
7325         }
7326
7327         /* let the connector get through one full cycle before testing */
7328         intel_wait_for_vblank(dev, intel_crtc->pipe);
7329         return true;
7330 }
7331
7332 void intel_release_load_detect_pipe(struct drm_connector *connector,
7333                                     struct intel_load_detect_pipe *old)
7334 {
7335         struct intel_encoder *intel_encoder =
7336                 intel_attached_encoder(connector);
7337         struct drm_encoder *encoder = &intel_encoder->base;
7338         struct drm_crtc *crtc = encoder->crtc;
7339
7340         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7341                       connector->base.id, drm_get_connector_name(connector),
7342                       encoder->base.id, drm_get_encoder_name(encoder));
7343
7344         if (old->load_detect_temp) {
7345                 to_intel_connector(connector)->new_encoder = NULL;
7346                 intel_encoder->new_crtc = NULL;
7347                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7348
7349                 if (old->release_fb) {
7350                         drm_framebuffer_unregister_private(old->release_fb);
7351                         drm_framebuffer_unreference(old->release_fb);
7352                 }
7353
7354                 mutex_unlock(&crtc->mutex);
7355                 return;
7356         }
7357
7358         /* Switch crtc and encoder back off if necessary */
7359         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7360                 connector->funcs->dpms(connector, old->dpms_mode);
7361
7362         mutex_unlock(&crtc->mutex);
7363 }
7364
7365 static int i9xx_pll_refclk(struct drm_device *dev,
7366                            const struct intel_crtc_config *pipe_config)
7367 {
7368         struct drm_i915_private *dev_priv = dev->dev_private;
7369         u32 dpll = pipe_config->dpll_hw_state.dpll;
7370
7371         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7372                 return dev_priv->vbt.lvds_ssc_freq * 1000;
7373         else if (HAS_PCH_SPLIT(dev))
7374                 return 120000;
7375         else if (!IS_GEN2(dev))
7376                 return 96000;
7377         else
7378                 return 48000;
7379 }
7380
7381 /* Returns the clock of the currently programmed mode of the given pipe. */
7382 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7383                                 struct intel_crtc_config *pipe_config)
7384 {
7385         struct drm_device *dev = crtc->base.dev;
7386         struct drm_i915_private *dev_priv = dev->dev_private;
7387         int pipe = pipe_config->cpu_transcoder;
7388         u32 dpll = pipe_config->dpll_hw_state.dpll;
7389         u32 fp;
7390         intel_clock_t clock;
7391         int refclk = i9xx_pll_refclk(dev, pipe_config);
7392
7393         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7394                 fp = pipe_config->dpll_hw_state.fp0;
7395         else
7396                 fp = pipe_config->dpll_hw_state.fp1;
7397
7398         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7399         if (IS_PINEVIEW(dev)) {
7400                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7401                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7402         } else {
7403                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7404                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7405         }
7406
7407         if (!IS_GEN2(dev)) {
7408                 if (IS_PINEVIEW(dev))
7409                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7410                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7411                 else
7412                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7413                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7414
7415                 switch (dpll & DPLL_MODE_MASK) {
7416                 case DPLLB_MODE_DAC_SERIAL:
7417                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7418                                 5 : 10;
7419                         break;
7420                 case DPLLB_MODE_LVDS:
7421                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7422                                 7 : 14;
7423                         break;
7424                 default:
7425                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7426                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7427                         return;
7428                 }
7429
7430                 if (IS_PINEVIEW(dev))
7431                         pineview_clock(refclk, &clock);
7432                 else
7433                         i9xx_clock(refclk, &clock);
7434         } else {
7435                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7436
7437                 if (is_lvds) {
7438                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7439                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7440                         clock.p2 = 14;
7441                 } else {
7442                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7443                                 clock.p1 = 2;
7444                         else {
7445                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7446                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7447                         }
7448                         if (dpll & PLL_P2_DIVIDE_BY_4)
7449                                 clock.p2 = 4;
7450                         else
7451                                 clock.p2 = 2;
7452                 }
7453
7454                 i9xx_clock(refclk, &clock);
7455         }
7456
7457         /*
7458          * This value includes pixel_multiplier. We will use
7459          * port_clock to compute adjusted_mode.clock in the
7460          * encoder's get_config() function.
7461          */
7462         pipe_config->port_clock = clock.dot;
7463 }
7464
7465 int intel_dotclock_calculate(int link_freq,
7466                              const struct intel_link_m_n *m_n)
7467 {
7468         /*
7469          * The calculation for the data clock is:
7470          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7471          * But we want to avoid losing precison if possible, so:
7472          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7473          *
7474          * and the link clock is simpler:
7475          * link_clock = (m * link_clock) / n
7476          */
7477
7478         if (!m_n->link_n)
7479                 return 0;
7480
7481         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7482 }
7483
7484 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7485                                    struct intel_crtc_config *pipe_config)
7486 {
7487         struct drm_device *dev = crtc->base.dev;
7488
7489         /* read out port_clock from the DPLL */
7490         i9xx_crtc_clock_get(crtc, pipe_config);
7491
7492         /*
7493          * This value does not include pixel_multiplier.
7494          * We will check that port_clock and adjusted_mode.clock
7495          * agree once we know their relationship in the encoder's
7496          * get_config() function.
7497          */
7498         pipe_config->adjusted_mode.clock =
7499                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7500                                          &pipe_config->fdi_m_n);
7501 }
7502
7503 /** Returns the currently programmed mode of the given pipe. */
7504 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7505                                              struct drm_crtc *crtc)
7506 {
7507         struct drm_i915_private *dev_priv = dev->dev_private;
7508         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7509         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7510         struct drm_display_mode *mode;
7511         struct intel_crtc_config pipe_config;
7512         int htot = I915_READ(HTOTAL(cpu_transcoder));
7513         int hsync = I915_READ(HSYNC(cpu_transcoder));
7514         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7515         int vsync = I915_READ(VSYNC(cpu_transcoder));
7516         enum pipe pipe = intel_crtc->pipe;
7517
7518         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7519         if (!mode)
7520                 return NULL;
7521
7522         /*
7523          * Construct a pipe_config sufficient for getting the clock info
7524          * back out of crtc_clock_get.
7525          *
7526          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7527          * to use a real value here instead.
7528          */
7529         pipe_config.cpu_transcoder = (enum transcoder) pipe;
7530         pipe_config.pixel_multiplier = 1;
7531         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7532         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7533         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7534         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7535
7536         mode->clock = pipe_config.adjusted_mode.clock;
7537         mode->hdisplay = (htot & 0xffff) + 1;
7538         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7539         mode->hsync_start = (hsync & 0xffff) + 1;
7540         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7541         mode->vdisplay = (vtot & 0xffff) + 1;
7542         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7543         mode->vsync_start = (vsync & 0xffff) + 1;
7544         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7545
7546         drm_mode_set_name(mode);
7547
7548         return mode;
7549 }
7550
7551 static void intel_increase_pllclock(struct drm_crtc *crtc)
7552 {
7553         struct drm_device *dev = crtc->dev;
7554         drm_i915_private_t *dev_priv = dev->dev_private;
7555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7556         int pipe = intel_crtc->pipe;
7557         int dpll_reg = DPLL(pipe);
7558         int dpll;
7559
7560         if (HAS_PCH_SPLIT(dev))
7561                 return;
7562
7563         if (!dev_priv->lvds_downclock_avail)
7564                 return;
7565
7566         dpll = I915_READ(dpll_reg);
7567         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7568                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7569
7570                 assert_panel_unlocked(dev_priv, pipe);
7571
7572                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7573                 I915_WRITE(dpll_reg, dpll);
7574                 intel_wait_for_vblank(dev, pipe);
7575
7576                 dpll = I915_READ(dpll_reg);
7577                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7578                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7579         }
7580 }
7581
7582 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7583 {
7584         struct drm_device *dev = crtc->dev;
7585         drm_i915_private_t *dev_priv = dev->dev_private;
7586         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7587
7588         if (HAS_PCH_SPLIT(dev))
7589                 return;
7590
7591         if (!dev_priv->lvds_downclock_avail)
7592                 return;
7593
7594         /*
7595          * Since this is called by a timer, we should never get here in
7596          * the manual case.
7597          */
7598         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7599                 int pipe = intel_crtc->pipe;
7600                 int dpll_reg = DPLL(pipe);
7601                 int dpll;
7602
7603                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7604
7605                 assert_panel_unlocked(dev_priv, pipe);
7606
7607                 dpll = I915_READ(dpll_reg);
7608                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7609                 I915_WRITE(dpll_reg, dpll);
7610                 intel_wait_for_vblank(dev, pipe);
7611                 dpll = I915_READ(dpll_reg);
7612                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7613                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7614         }
7615
7616 }
7617
7618 void intel_mark_busy(struct drm_device *dev)
7619 {
7620         struct drm_i915_private *dev_priv = dev->dev_private;
7621
7622         hsw_package_c8_gpu_busy(dev_priv);
7623         i915_update_gfx_val(dev_priv);
7624 }
7625
7626 void intel_mark_idle(struct drm_device *dev)
7627 {
7628         struct drm_i915_private *dev_priv = dev->dev_private;
7629         struct drm_crtc *crtc;
7630
7631         hsw_package_c8_gpu_idle(dev_priv);
7632
7633         if (!i915_powersave)
7634                 return;
7635
7636         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7637                 if (!crtc->fb)
7638                         continue;
7639
7640                 intel_decrease_pllclock(crtc);
7641         }
7642 }
7643
7644 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7645                         struct intel_ring_buffer *ring)
7646 {
7647         struct drm_device *dev = obj->base.dev;
7648         struct drm_crtc *crtc;
7649
7650         if (!i915_powersave)
7651                 return;
7652
7653         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7654                 if (!crtc->fb)
7655                         continue;
7656
7657                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7658                         continue;
7659
7660                 intel_increase_pllclock(crtc);
7661                 if (ring && intel_fbc_enabled(dev))
7662                         ring->fbc_dirty = true;
7663         }
7664 }
7665
7666 static void intel_crtc_destroy(struct drm_crtc *crtc)
7667 {
7668         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7669         struct drm_device *dev = crtc->dev;
7670         struct intel_unpin_work *work;
7671         unsigned long flags;
7672
7673         spin_lock_irqsave(&dev->event_lock, flags);
7674         work = intel_crtc->unpin_work;
7675         intel_crtc->unpin_work = NULL;
7676         spin_unlock_irqrestore(&dev->event_lock, flags);
7677
7678         if (work) {
7679                 cancel_work_sync(&work->work);
7680                 kfree(work);
7681         }
7682
7683         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7684
7685         drm_crtc_cleanup(crtc);
7686
7687         kfree(intel_crtc);
7688 }
7689
7690 static void intel_unpin_work_fn(struct work_struct *__work)
7691 {
7692         struct intel_unpin_work *work =
7693                 container_of(__work, struct intel_unpin_work, work);
7694         struct drm_device *dev = work->crtc->dev;
7695
7696         mutex_lock(&dev->struct_mutex);
7697         intel_unpin_fb_obj(work->old_fb_obj);
7698         drm_gem_object_unreference(&work->pending_flip_obj->base);
7699         drm_gem_object_unreference(&work->old_fb_obj->base);
7700
7701         intel_update_fbc(dev);
7702         mutex_unlock(&dev->struct_mutex);
7703
7704         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7705         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7706
7707         kfree(work);
7708 }
7709
7710 static void do_intel_finish_page_flip(struct drm_device *dev,
7711                                       struct drm_crtc *crtc)
7712 {
7713         drm_i915_private_t *dev_priv = dev->dev_private;
7714         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7715         struct intel_unpin_work *work;
7716         unsigned long flags;
7717
7718         /* Ignore early vblank irqs */
7719         if (intel_crtc == NULL)
7720                 return;
7721
7722         spin_lock_irqsave(&dev->event_lock, flags);
7723         work = intel_crtc->unpin_work;
7724
7725         /* Ensure we don't miss a work->pending update ... */
7726         smp_rmb();
7727
7728         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7729                 spin_unlock_irqrestore(&dev->event_lock, flags);
7730                 return;
7731         }
7732
7733         /* and that the unpin work is consistent wrt ->pending. */
7734         smp_rmb();
7735
7736         intel_crtc->unpin_work = NULL;
7737
7738         if (work->event)
7739                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7740
7741         drm_vblank_put(dev, intel_crtc->pipe);
7742
7743         spin_unlock_irqrestore(&dev->event_lock, flags);
7744
7745         wake_up_all(&dev_priv->pending_flip_queue);
7746
7747         queue_work(dev_priv->wq, &work->work);
7748
7749         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7750 }
7751
7752 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7753 {
7754         drm_i915_private_t *dev_priv = dev->dev_private;
7755         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7756
7757         do_intel_finish_page_flip(dev, crtc);
7758 }
7759
7760 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7761 {
7762         drm_i915_private_t *dev_priv = dev->dev_private;
7763         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7764
7765         do_intel_finish_page_flip(dev, crtc);
7766 }
7767
7768 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7769 {
7770         drm_i915_private_t *dev_priv = dev->dev_private;
7771         struct intel_crtc *intel_crtc =
7772                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7773         unsigned long flags;
7774
7775         /* NB: An MMIO update of the plane base pointer will also
7776          * generate a page-flip completion irq, i.e. every modeset
7777          * is also accompanied by a spurious intel_prepare_page_flip().
7778          */
7779         spin_lock_irqsave(&dev->event_lock, flags);
7780         if (intel_crtc->unpin_work)
7781                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7782         spin_unlock_irqrestore(&dev->event_lock, flags);
7783 }
7784
7785 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7786 {
7787         /* Ensure that the work item is consistent when activating it ... */
7788         smp_wmb();
7789         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7790         /* and that it is marked active as soon as the irq could fire. */
7791         smp_wmb();
7792 }
7793
7794 static int intel_gen2_queue_flip(struct drm_device *dev,
7795                                  struct drm_crtc *crtc,
7796                                  struct drm_framebuffer *fb,
7797                                  struct drm_i915_gem_object *obj,
7798                                  uint32_t flags)
7799 {
7800         struct drm_i915_private *dev_priv = dev->dev_private;
7801         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7802         u32 flip_mask;
7803         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7804         int ret;
7805
7806         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7807         if (ret)
7808                 goto err;
7809
7810         ret = intel_ring_begin(ring, 6);
7811         if (ret)
7812                 goto err_unpin;
7813
7814         /* Can't queue multiple flips, so wait for the previous
7815          * one to finish before executing the next.
7816          */
7817         if (intel_crtc->plane)
7818                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7819         else
7820                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7821         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7822         intel_ring_emit(ring, MI_NOOP);
7823         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7824                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7825         intel_ring_emit(ring, fb->pitches[0]);
7826         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7827         intel_ring_emit(ring, 0); /* aux display base address, unused */
7828
7829         intel_mark_page_flip_active(intel_crtc);
7830         __intel_ring_advance(ring);
7831         return 0;
7832
7833 err_unpin:
7834         intel_unpin_fb_obj(obj);
7835 err:
7836         return ret;
7837 }
7838
7839 static int intel_gen3_queue_flip(struct drm_device *dev,
7840                                  struct drm_crtc *crtc,
7841                                  struct drm_framebuffer *fb,
7842                                  struct drm_i915_gem_object *obj,
7843                                  uint32_t flags)
7844 {
7845         struct drm_i915_private *dev_priv = dev->dev_private;
7846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7847         u32 flip_mask;
7848         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7849         int ret;
7850
7851         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7852         if (ret)
7853                 goto err;
7854
7855         ret = intel_ring_begin(ring, 6);
7856         if (ret)
7857                 goto err_unpin;
7858
7859         if (intel_crtc->plane)
7860                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7861         else
7862                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7863         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7864         intel_ring_emit(ring, MI_NOOP);
7865         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7866                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7867         intel_ring_emit(ring, fb->pitches[0]);
7868         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7869         intel_ring_emit(ring, MI_NOOP);
7870
7871         intel_mark_page_flip_active(intel_crtc);
7872         __intel_ring_advance(ring);
7873         return 0;
7874
7875 err_unpin:
7876         intel_unpin_fb_obj(obj);
7877 err:
7878         return ret;
7879 }
7880
7881 static int intel_gen4_queue_flip(struct drm_device *dev,
7882                                  struct drm_crtc *crtc,
7883                                  struct drm_framebuffer *fb,
7884                                  struct drm_i915_gem_object *obj,
7885                                  uint32_t flags)
7886 {
7887         struct drm_i915_private *dev_priv = dev->dev_private;
7888         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7889         uint32_t pf, pipesrc;
7890         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7891         int ret;
7892
7893         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7894         if (ret)
7895                 goto err;
7896
7897         ret = intel_ring_begin(ring, 4);
7898         if (ret)
7899                 goto err_unpin;
7900
7901         /* i965+ uses the linear or tiled offsets from the
7902          * Display Registers (which do not change across a page-flip)
7903          * so we need only reprogram the base address.
7904          */
7905         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7906                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7907         intel_ring_emit(ring, fb->pitches[0]);
7908         intel_ring_emit(ring,
7909                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7910                         obj->tiling_mode);
7911
7912         /* XXX Enabling the panel-fitter across page-flip is so far
7913          * untested on non-native modes, so ignore it for now.
7914          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7915          */
7916         pf = 0;
7917         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7918         intel_ring_emit(ring, pf | pipesrc);
7919
7920         intel_mark_page_flip_active(intel_crtc);
7921         __intel_ring_advance(ring);
7922         return 0;
7923
7924 err_unpin:
7925         intel_unpin_fb_obj(obj);
7926 err:
7927         return ret;
7928 }
7929
7930 static int intel_gen6_queue_flip(struct drm_device *dev,
7931                                  struct drm_crtc *crtc,
7932                                  struct drm_framebuffer *fb,
7933                                  struct drm_i915_gem_object *obj,
7934                                  uint32_t flags)
7935 {
7936         struct drm_i915_private *dev_priv = dev->dev_private;
7937         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7938         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7939         uint32_t pf, pipesrc;
7940         int ret;
7941
7942         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7943         if (ret)
7944                 goto err;
7945
7946         ret = intel_ring_begin(ring, 4);
7947         if (ret)
7948                 goto err_unpin;
7949
7950         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7951                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7952         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7953         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7954
7955         /* Contrary to the suggestions in the documentation,
7956          * "Enable Panel Fitter" does not seem to be required when page
7957          * flipping with a non-native mode, and worse causes a normal
7958          * modeset to fail.
7959          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7960          */
7961         pf = 0;
7962         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7963         intel_ring_emit(ring, pf | pipesrc);
7964
7965         intel_mark_page_flip_active(intel_crtc);
7966         __intel_ring_advance(ring);
7967         return 0;
7968
7969 err_unpin:
7970         intel_unpin_fb_obj(obj);
7971 err:
7972         return ret;
7973 }
7974
7975 static int intel_gen7_queue_flip(struct drm_device *dev,
7976                                  struct drm_crtc *crtc,
7977                                  struct drm_framebuffer *fb,
7978                                  struct drm_i915_gem_object *obj,
7979                                  uint32_t flags)
7980 {
7981         struct drm_i915_private *dev_priv = dev->dev_private;
7982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7983         struct intel_ring_buffer *ring;
7984         uint32_t plane_bit = 0;
7985         int len, ret;
7986
7987         ring = obj->ring;
7988         if (ring == NULL || ring->id != RCS)
7989                 ring = &dev_priv->ring[BCS];
7990
7991         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7992         if (ret)
7993                 goto err;
7994
7995         switch(intel_crtc->plane) {
7996         case PLANE_A:
7997                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7998                 break;
7999         case PLANE_B:
8000                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8001                 break;
8002         case PLANE_C:
8003                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8004                 break;
8005         default:
8006                 WARN_ONCE(1, "unknown plane in flip command\n");
8007                 ret = -ENODEV;
8008                 goto err_unpin;
8009         }
8010
8011         len = 4;
8012         if (ring->id == RCS)
8013                 len += 6;
8014
8015         ret = intel_ring_begin(ring, len);
8016         if (ret)
8017                 goto err_unpin;
8018
8019         /* Unmask the flip-done completion message. Note that the bspec says that
8020          * we should do this for both the BCS and RCS, and that we must not unmask
8021          * more than one flip event at any time (or ensure that one flip message
8022          * can be sent by waiting for flip-done prior to queueing new flips).
8023          * Experimentation says that BCS works despite DERRMR masking all
8024          * flip-done completion events and that unmasking all planes at once
8025          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8026          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8027          */
8028         if (ring->id == RCS) {
8029                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8030                 intel_ring_emit(ring, DERRMR);
8031                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8032                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8033                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8034                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8035                 intel_ring_emit(ring, DERRMR);
8036                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8037         }
8038
8039         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8040         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8041         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8042         intel_ring_emit(ring, (MI_NOOP));
8043
8044         intel_mark_page_flip_active(intel_crtc);
8045         __intel_ring_advance(ring);
8046         return 0;
8047
8048 err_unpin:
8049         intel_unpin_fb_obj(obj);
8050 err:
8051         return ret;
8052 }
8053
8054 static int intel_default_queue_flip(struct drm_device *dev,
8055                                     struct drm_crtc *crtc,
8056                                     struct drm_framebuffer *fb,
8057                                     struct drm_i915_gem_object *obj,
8058                                     uint32_t flags)
8059 {
8060         return -ENODEV;
8061 }
8062
8063 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8064                                 struct drm_framebuffer *fb,
8065                                 struct drm_pending_vblank_event *event,
8066                                 uint32_t page_flip_flags)
8067 {
8068         struct drm_device *dev = crtc->dev;
8069         struct drm_i915_private *dev_priv = dev->dev_private;
8070         struct drm_framebuffer *old_fb = crtc->fb;
8071         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8072         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8073         struct intel_unpin_work *work;
8074         unsigned long flags;
8075         int ret;
8076
8077         /* Can't change pixel format via MI display flips. */
8078         if (fb->pixel_format != crtc->fb->pixel_format)
8079                 return -EINVAL;
8080
8081         /*
8082          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8083          * Note that pitch changes could also affect these register.
8084          */
8085         if (INTEL_INFO(dev)->gen > 3 &&
8086             (fb->offsets[0] != crtc->fb->offsets[0] ||
8087              fb->pitches[0] != crtc->fb->pitches[0]))
8088                 return -EINVAL;
8089
8090         work = kzalloc(sizeof *work, GFP_KERNEL);
8091         if (work == NULL)
8092                 return -ENOMEM;
8093
8094         work->event = event;
8095         work->crtc = crtc;
8096         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8097         INIT_WORK(&work->work, intel_unpin_work_fn);
8098
8099         ret = drm_vblank_get(dev, intel_crtc->pipe);
8100         if (ret)
8101                 goto free_work;
8102
8103         /* We borrow the event spin lock for protecting unpin_work */
8104         spin_lock_irqsave(&dev->event_lock, flags);
8105         if (intel_crtc->unpin_work) {
8106                 spin_unlock_irqrestore(&dev->event_lock, flags);
8107                 kfree(work);
8108                 drm_vblank_put(dev, intel_crtc->pipe);
8109
8110                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8111                 return -EBUSY;
8112         }
8113         intel_crtc->unpin_work = work;
8114         spin_unlock_irqrestore(&dev->event_lock, flags);
8115
8116         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8117                 flush_workqueue(dev_priv->wq);
8118
8119         ret = i915_mutex_lock_interruptible(dev);
8120         if (ret)
8121                 goto cleanup;
8122
8123         /* Reference the objects for the scheduled work. */
8124         drm_gem_object_reference(&work->old_fb_obj->base);
8125         drm_gem_object_reference(&obj->base);
8126
8127         crtc->fb = fb;
8128
8129         work->pending_flip_obj = obj;
8130
8131         work->enable_stall_check = true;
8132
8133         atomic_inc(&intel_crtc->unpin_work_count);
8134         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8135
8136         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8137         if (ret)
8138                 goto cleanup_pending;
8139
8140         intel_disable_fbc(dev);
8141         intel_mark_fb_busy(obj, NULL);
8142         mutex_unlock(&dev->struct_mutex);
8143
8144         trace_i915_flip_request(intel_crtc->plane, obj);
8145
8146         return 0;
8147
8148 cleanup_pending:
8149         atomic_dec(&intel_crtc->unpin_work_count);
8150         crtc->fb = old_fb;
8151         drm_gem_object_unreference(&work->old_fb_obj->base);
8152         drm_gem_object_unreference(&obj->base);
8153         mutex_unlock(&dev->struct_mutex);
8154
8155 cleanup:
8156         spin_lock_irqsave(&dev->event_lock, flags);
8157         intel_crtc->unpin_work = NULL;
8158         spin_unlock_irqrestore(&dev->event_lock, flags);
8159
8160         drm_vblank_put(dev, intel_crtc->pipe);
8161 free_work:
8162         kfree(work);
8163
8164         return ret;
8165 }
8166
8167 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8168         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8169         .load_lut = intel_crtc_load_lut,
8170 };
8171
8172 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8173                                   struct drm_crtc *crtc)
8174 {
8175         struct drm_device *dev;
8176         struct drm_crtc *tmp;
8177         int crtc_mask = 1;
8178
8179         WARN(!crtc, "checking null crtc?\n");
8180
8181         dev = crtc->dev;
8182
8183         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8184                 if (tmp == crtc)
8185                         break;
8186                 crtc_mask <<= 1;
8187         }
8188
8189         if (encoder->possible_crtcs & crtc_mask)
8190                 return true;
8191         return false;
8192 }
8193
8194 /**
8195  * intel_modeset_update_staged_output_state
8196  *
8197  * Updates the staged output configuration state, e.g. after we've read out the
8198  * current hw state.
8199  */
8200 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8201 {
8202         struct intel_encoder *encoder;
8203         struct intel_connector *connector;
8204
8205         list_for_each_entry(connector, &dev->mode_config.connector_list,
8206                             base.head) {
8207                 connector->new_encoder =
8208                         to_intel_encoder(connector->base.encoder);
8209         }
8210
8211         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8212                             base.head) {
8213                 encoder->new_crtc =
8214                         to_intel_crtc(encoder->base.crtc);
8215         }
8216 }
8217
8218 /**
8219  * intel_modeset_commit_output_state
8220  *
8221  * This function copies the stage display pipe configuration to the real one.
8222  */
8223 static void intel_modeset_commit_output_state(struct drm_device *dev)
8224 {
8225         struct intel_encoder *encoder;
8226         struct intel_connector *connector;
8227
8228         list_for_each_entry(connector, &dev->mode_config.connector_list,
8229                             base.head) {
8230                 connector->base.encoder = &connector->new_encoder->base;
8231         }
8232
8233         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8234                             base.head) {
8235                 encoder->base.crtc = &encoder->new_crtc->base;
8236         }
8237 }
8238
8239 static void
8240 connected_sink_compute_bpp(struct intel_connector * connector,
8241                            struct intel_crtc_config *pipe_config)
8242 {
8243         int bpp = pipe_config->pipe_bpp;
8244
8245         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8246                 connector->base.base.id,
8247                 drm_get_connector_name(&connector->base));
8248
8249         /* Don't use an invalid EDID bpc value */
8250         if (connector->base.display_info.bpc &&
8251             connector->base.display_info.bpc * 3 < bpp) {
8252                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8253                               bpp, connector->base.display_info.bpc*3);
8254                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8255         }
8256
8257         /* Clamp bpp to 8 on screens without EDID 1.4 */
8258         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8259                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8260                               bpp);
8261                 pipe_config->pipe_bpp = 24;
8262         }
8263 }
8264
8265 static int
8266 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8267                           struct drm_framebuffer *fb,
8268                           struct intel_crtc_config *pipe_config)
8269 {
8270         struct drm_device *dev = crtc->base.dev;
8271         struct intel_connector *connector;
8272         int bpp;
8273
8274         switch (fb->pixel_format) {
8275         case DRM_FORMAT_C8:
8276                 bpp = 8*3; /* since we go through a colormap */
8277                 break;
8278         case DRM_FORMAT_XRGB1555:
8279         case DRM_FORMAT_ARGB1555:
8280                 /* checked in intel_framebuffer_init already */
8281                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8282                         return -EINVAL;
8283         case DRM_FORMAT_RGB565:
8284                 bpp = 6*3; /* min is 18bpp */
8285                 break;
8286         case DRM_FORMAT_XBGR8888:
8287         case DRM_FORMAT_ABGR8888:
8288                 /* checked in intel_framebuffer_init already */
8289                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8290                         return -EINVAL;
8291         case DRM_FORMAT_XRGB8888:
8292         case DRM_FORMAT_ARGB8888:
8293                 bpp = 8*3;
8294                 break;
8295         case DRM_FORMAT_XRGB2101010:
8296         case DRM_FORMAT_ARGB2101010:
8297         case DRM_FORMAT_XBGR2101010:
8298         case DRM_FORMAT_ABGR2101010:
8299                 /* checked in intel_framebuffer_init already */
8300                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8301                         return -EINVAL;
8302                 bpp = 10*3;
8303                 break;
8304         /* TODO: gen4+ supports 16 bpc floating point, too. */
8305         default:
8306                 DRM_DEBUG_KMS("unsupported depth\n");
8307                 return -EINVAL;
8308         }
8309
8310         pipe_config->pipe_bpp = bpp;
8311
8312         /* Clamp display bpp to EDID value */
8313         list_for_each_entry(connector, &dev->mode_config.connector_list,
8314                             base.head) {
8315                 if (!connector->new_encoder ||
8316                     connector->new_encoder->new_crtc != crtc)
8317                         continue;
8318
8319                 connected_sink_compute_bpp(connector, pipe_config);
8320         }
8321
8322         return bpp;
8323 }
8324
8325 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8326                                    struct intel_crtc_config *pipe_config,
8327                                    const char *context)
8328 {
8329         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8330                       context, pipe_name(crtc->pipe));
8331
8332         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8333         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8334                       pipe_config->pipe_bpp, pipe_config->dither);
8335         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8336                       pipe_config->has_pch_encoder,
8337                       pipe_config->fdi_lanes,
8338                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8339                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8340                       pipe_config->fdi_m_n.tu);
8341         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8342                       pipe_config->has_dp_encoder,
8343                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8344                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8345                       pipe_config->dp_m_n.tu);
8346         DRM_DEBUG_KMS("requested mode:\n");
8347         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8348         DRM_DEBUG_KMS("adjusted mode:\n");
8349         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8350         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8351         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8352                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8353         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8354                       pipe_config->gmch_pfit.control,
8355                       pipe_config->gmch_pfit.pgm_ratios,
8356                       pipe_config->gmch_pfit.lvds_border_bits);
8357         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8358                       pipe_config->pch_pfit.pos,
8359                       pipe_config->pch_pfit.size);
8360         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8361 }
8362
8363 static bool check_encoder_cloning(struct drm_crtc *crtc)
8364 {
8365         int num_encoders = 0;
8366         bool uncloneable_encoders = false;
8367         struct intel_encoder *encoder;
8368
8369         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8370                             base.head) {
8371                 if (&encoder->new_crtc->base != crtc)
8372                         continue;
8373
8374                 num_encoders++;
8375                 if (!encoder->cloneable)
8376                         uncloneable_encoders = true;
8377         }
8378
8379         return !(num_encoders > 1 && uncloneable_encoders);
8380 }
8381
8382 static struct intel_crtc_config *
8383 intel_modeset_pipe_config(struct drm_crtc *crtc,
8384                           struct drm_framebuffer *fb,
8385                           struct drm_display_mode *mode)
8386 {
8387         struct drm_device *dev = crtc->dev;
8388         struct intel_encoder *encoder;
8389         struct intel_crtc_config *pipe_config;
8390         int plane_bpp, ret = -EINVAL;
8391         bool retry = true;
8392
8393         if (!check_encoder_cloning(crtc)) {
8394                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8395                 return ERR_PTR(-EINVAL);
8396         }
8397
8398         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8399         if (!pipe_config)
8400                 return ERR_PTR(-ENOMEM);
8401
8402         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8403         drm_mode_copy(&pipe_config->requested_mode, mode);
8404
8405         pipe_config->pipe_src_w = mode->hdisplay;
8406         pipe_config->pipe_src_h = mode->vdisplay;
8407
8408         pipe_config->cpu_transcoder =
8409                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8410         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8411
8412         /*
8413          * Sanitize sync polarity flags based on requested ones. If neither
8414          * positive or negative polarity is requested, treat this as meaning
8415          * negative polarity.
8416          */
8417         if (!(pipe_config->adjusted_mode.flags &
8418               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8419                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8420
8421         if (!(pipe_config->adjusted_mode.flags &
8422               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8423                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8424
8425         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8426          * plane pixel format and any sink constraints into account. Returns the
8427          * source plane bpp so that dithering can be selected on mismatches
8428          * after encoders and crtc also have had their say. */
8429         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8430                                               fb, pipe_config);
8431         if (plane_bpp < 0)
8432                 goto fail;
8433
8434 encoder_retry:
8435         /* Ensure the port clock defaults are reset when retrying. */
8436         pipe_config->port_clock = 0;
8437         pipe_config->pixel_multiplier = 1;
8438
8439         /* Fill in default crtc timings, allow encoders to overwrite them. */
8440         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8441
8442         /* Pass our mode to the connectors and the CRTC to give them a chance to
8443          * adjust it according to limitations or connector properties, and also
8444          * a chance to reject the mode entirely.
8445          */
8446         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8447                             base.head) {
8448
8449                 if (&encoder->new_crtc->base != crtc)
8450                         continue;
8451
8452                 if (!(encoder->compute_config(encoder, pipe_config))) {
8453                         DRM_DEBUG_KMS("Encoder config failure\n");
8454                         goto fail;
8455                 }
8456         }
8457
8458         /* Set default port clock if not overwritten by the encoder. Needs to be
8459          * done afterwards in case the encoder adjusts the mode. */
8460         if (!pipe_config->port_clock)
8461                 pipe_config->port_clock = pipe_config->adjusted_mode.clock *
8462                         pipe_config->pixel_multiplier;
8463
8464         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8465         if (ret < 0) {
8466                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8467                 goto fail;
8468         }
8469
8470         if (ret == RETRY) {
8471                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8472                         ret = -EINVAL;
8473                         goto fail;
8474                 }
8475
8476                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8477                 retry = false;
8478                 goto encoder_retry;
8479         }
8480
8481         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8482         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8483                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8484
8485         return pipe_config;
8486 fail:
8487         kfree(pipe_config);
8488         return ERR_PTR(ret);
8489 }
8490
8491 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8492  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8493 static void
8494 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8495                              unsigned *prepare_pipes, unsigned *disable_pipes)
8496 {
8497         struct intel_crtc *intel_crtc;
8498         struct drm_device *dev = crtc->dev;
8499         struct intel_encoder *encoder;
8500         struct intel_connector *connector;
8501         struct drm_crtc *tmp_crtc;
8502
8503         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8504
8505         /* Check which crtcs have changed outputs connected to them, these need
8506          * to be part of the prepare_pipes mask. We don't (yet) support global
8507          * modeset across multiple crtcs, so modeset_pipes will only have one
8508          * bit set at most. */
8509         list_for_each_entry(connector, &dev->mode_config.connector_list,
8510                             base.head) {
8511                 if (connector->base.encoder == &connector->new_encoder->base)
8512                         continue;
8513
8514                 if (connector->base.encoder) {
8515                         tmp_crtc = connector->base.encoder->crtc;
8516
8517                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8518                 }
8519
8520                 if (connector->new_encoder)
8521                         *prepare_pipes |=
8522                                 1 << connector->new_encoder->new_crtc->pipe;
8523         }
8524
8525         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8526                             base.head) {
8527                 if (encoder->base.crtc == &encoder->new_crtc->base)
8528                         continue;
8529
8530                 if (encoder->base.crtc) {
8531                         tmp_crtc = encoder->base.crtc;
8532
8533                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8534                 }
8535
8536                 if (encoder->new_crtc)
8537                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8538         }
8539
8540         /* Check for any pipes that will be fully disabled ... */
8541         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8542                             base.head) {
8543                 bool used = false;
8544
8545                 /* Don't try to disable disabled crtcs. */
8546                 if (!intel_crtc->base.enabled)
8547                         continue;
8548
8549                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8550                                     base.head) {
8551                         if (encoder->new_crtc == intel_crtc)
8552                                 used = true;
8553                 }
8554
8555                 if (!used)
8556                         *disable_pipes |= 1 << intel_crtc->pipe;
8557         }
8558
8559
8560         /* set_mode is also used to update properties on life display pipes. */
8561         intel_crtc = to_intel_crtc(crtc);
8562         if (crtc->enabled)
8563                 *prepare_pipes |= 1 << intel_crtc->pipe;
8564
8565         /*
8566          * For simplicity do a full modeset on any pipe where the output routing
8567          * changed. We could be more clever, but that would require us to be
8568          * more careful with calling the relevant encoder->mode_set functions.
8569          */
8570         if (*prepare_pipes)
8571                 *modeset_pipes = *prepare_pipes;
8572
8573         /* ... and mask these out. */
8574         *modeset_pipes &= ~(*disable_pipes);
8575         *prepare_pipes &= ~(*disable_pipes);
8576
8577         /*
8578          * HACK: We don't (yet) fully support global modesets. intel_set_config
8579          * obies this rule, but the modeset restore mode of
8580          * intel_modeset_setup_hw_state does not.
8581          */
8582         *modeset_pipes &= 1 << intel_crtc->pipe;
8583         *prepare_pipes &= 1 << intel_crtc->pipe;
8584
8585         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8586                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8587 }
8588
8589 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8590 {
8591         struct drm_encoder *encoder;
8592         struct drm_device *dev = crtc->dev;
8593
8594         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8595                 if (encoder->crtc == crtc)
8596                         return true;
8597
8598         return false;
8599 }
8600
8601 static void
8602 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8603 {
8604         struct intel_encoder *intel_encoder;
8605         struct intel_crtc *intel_crtc;
8606         struct drm_connector *connector;
8607
8608         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8609                             base.head) {
8610                 if (!intel_encoder->base.crtc)
8611                         continue;
8612
8613                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8614
8615                 if (prepare_pipes & (1 << intel_crtc->pipe))
8616                         intel_encoder->connectors_active = false;
8617         }
8618
8619         intel_modeset_commit_output_state(dev);
8620
8621         /* Update computed state. */
8622         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8623                             base.head) {
8624                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8625         }
8626
8627         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8628                 if (!connector->encoder || !connector->encoder->crtc)
8629                         continue;
8630
8631                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8632
8633                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8634                         struct drm_property *dpms_property =
8635                                 dev->mode_config.dpms_property;
8636
8637                         connector->dpms = DRM_MODE_DPMS_ON;
8638                         drm_object_property_set_value(&connector->base,
8639                                                          dpms_property,
8640                                                          DRM_MODE_DPMS_ON);
8641
8642                         intel_encoder = to_intel_encoder(connector->encoder);
8643                         intel_encoder->connectors_active = true;
8644                 }
8645         }
8646
8647 }
8648
8649 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8650 {
8651         int diff;
8652
8653         if (clock1 == clock2)
8654                 return true;
8655
8656         if (!clock1 || !clock2)
8657                 return false;
8658
8659         diff = abs(clock1 - clock2);
8660
8661         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8662                 return true;
8663
8664         return false;
8665 }
8666
8667 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8668         list_for_each_entry((intel_crtc), \
8669                             &(dev)->mode_config.crtc_list, \
8670                             base.head) \
8671                 if (mask & (1 <<(intel_crtc)->pipe))
8672
8673 static bool
8674 intel_pipe_config_compare(struct drm_device *dev,
8675                           struct intel_crtc_config *current_config,
8676                           struct intel_crtc_config *pipe_config)
8677 {
8678 #define PIPE_CONF_CHECK_X(name) \
8679         if (current_config->name != pipe_config->name) { \
8680                 DRM_ERROR("mismatch in " #name " " \
8681                           "(expected 0x%08x, found 0x%08x)\n", \
8682                           current_config->name, \
8683                           pipe_config->name); \
8684                 return false; \
8685         }
8686
8687 #define PIPE_CONF_CHECK_I(name) \
8688         if (current_config->name != pipe_config->name) { \
8689                 DRM_ERROR("mismatch in " #name " " \
8690                           "(expected %i, found %i)\n", \
8691                           current_config->name, \
8692                           pipe_config->name); \
8693                 return false; \
8694         }
8695
8696 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8697         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8698                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8699                           "(expected %i, found %i)\n", \
8700                           current_config->name & (mask), \
8701                           pipe_config->name & (mask)); \
8702                 return false; \
8703         }
8704
8705 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8706         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8707                 DRM_ERROR("mismatch in " #name " " \
8708                           "(expected %i, found %i)\n", \
8709                           current_config->name, \
8710                           pipe_config->name); \
8711                 return false; \
8712         }
8713
8714 #define PIPE_CONF_QUIRK(quirk)  \
8715         ((current_config->quirks | pipe_config->quirks) & (quirk))
8716
8717         PIPE_CONF_CHECK_I(cpu_transcoder);
8718
8719         PIPE_CONF_CHECK_I(has_pch_encoder);
8720         PIPE_CONF_CHECK_I(fdi_lanes);
8721         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8722         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8723         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8724         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8725         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8726
8727         PIPE_CONF_CHECK_I(has_dp_encoder);
8728         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8729         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8730         PIPE_CONF_CHECK_I(dp_m_n.link_m);
8731         PIPE_CONF_CHECK_I(dp_m_n.link_n);
8732         PIPE_CONF_CHECK_I(dp_m_n.tu);
8733
8734         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8735         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8736         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8737         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8738         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8739         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8740
8741         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8742         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8743         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8744         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8745         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8746         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8747
8748         PIPE_CONF_CHECK_I(pixel_multiplier);
8749
8750         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8751                               DRM_MODE_FLAG_INTERLACE);
8752
8753         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8754                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8755                                       DRM_MODE_FLAG_PHSYNC);
8756                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8757                                       DRM_MODE_FLAG_NHSYNC);
8758                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8759                                       DRM_MODE_FLAG_PVSYNC);
8760                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8761                                       DRM_MODE_FLAG_NVSYNC);
8762         }
8763
8764         PIPE_CONF_CHECK_I(pipe_src_w);
8765         PIPE_CONF_CHECK_I(pipe_src_h);
8766
8767         PIPE_CONF_CHECK_I(gmch_pfit.control);
8768         /* pfit ratios are autocomputed by the hw on gen4+ */
8769         if (INTEL_INFO(dev)->gen < 4)
8770                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8771         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8772         PIPE_CONF_CHECK_I(pch_pfit.pos);
8773         PIPE_CONF_CHECK_I(pch_pfit.size);
8774
8775         PIPE_CONF_CHECK_I(ips_enabled);
8776
8777         PIPE_CONF_CHECK_I(shared_dpll);
8778         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8779         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8780         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8781         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8782
8783         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8784                 PIPE_CONF_CHECK_I(pipe_bpp);
8785
8786         if (!IS_HASWELL(dev)) {
8787                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock);
8788                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8789         }
8790
8791 #undef PIPE_CONF_CHECK_X
8792 #undef PIPE_CONF_CHECK_I
8793 #undef PIPE_CONF_CHECK_FLAGS
8794 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8795 #undef PIPE_CONF_QUIRK
8796
8797         return true;
8798 }
8799
8800 static void
8801 check_connector_state(struct drm_device *dev)
8802 {
8803         struct intel_connector *connector;
8804
8805         list_for_each_entry(connector, &dev->mode_config.connector_list,
8806                             base.head) {
8807                 /* This also checks the encoder/connector hw state with the
8808                  * ->get_hw_state callbacks. */
8809                 intel_connector_check_state(connector);
8810
8811                 WARN(&connector->new_encoder->base != connector->base.encoder,
8812                      "connector's staged encoder doesn't match current encoder\n");
8813         }
8814 }
8815
8816 static void
8817 check_encoder_state(struct drm_device *dev)
8818 {
8819         struct intel_encoder *encoder;
8820         struct intel_connector *connector;
8821
8822         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8823                             base.head) {
8824                 bool enabled = false;
8825                 bool active = false;
8826                 enum pipe pipe, tracked_pipe;
8827
8828                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8829                               encoder->base.base.id,
8830                               drm_get_encoder_name(&encoder->base));
8831
8832                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8833                      "encoder's stage crtc doesn't match current crtc\n");
8834                 WARN(encoder->connectors_active && !encoder->base.crtc,
8835                      "encoder's active_connectors set, but no crtc\n");
8836
8837                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8838                                     base.head) {
8839                         if (connector->base.encoder != &encoder->base)
8840                                 continue;
8841                         enabled = true;
8842                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8843                                 active = true;
8844                 }
8845                 WARN(!!encoder->base.crtc != enabled,
8846                      "encoder's enabled state mismatch "
8847                      "(expected %i, found %i)\n",
8848                      !!encoder->base.crtc, enabled);
8849                 WARN(active && !encoder->base.crtc,
8850                      "active encoder with no crtc\n");
8851
8852                 WARN(encoder->connectors_active != active,
8853                      "encoder's computed active state doesn't match tracked active state "
8854                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8855
8856                 active = encoder->get_hw_state(encoder, &pipe);
8857                 WARN(active != encoder->connectors_active,
8858                      "encoder's hw state doesn't match sw tracking "
8859                      "(expected %i, found %i)\n",
8860                      encoder->connectors_active, active);
8861
8862                 if (!encoder->base.crtc)
8863                         continue;
8864
8865                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8866                 WARN(active && pipe != tracked_pipe,
8867                      "active encoder's pipe doesn't match"
8868                      "(expected %i, found %i)\n",
8869                      tracked_pipe, pipe);
8870
8871         }
8872 }
8873
8874 static void
8875 check_crtc_state(struct drm_device *dev)
8876 {
8877         drm_i915_private_t *dev_priv = dev->dev_private;
8878         struct intel_crtc *crtc;
8879         struct intel_encoder *encoder;
8880         struct intel_crtc_config pipe_config;
8881
8882         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8883                             base.head) {
8884                 bool enabled = false;
8885                 bool active = false;
8886
8887                 memset(&pipe_config, 0, sizeof(pipe_config));
8888
8889                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8890                               crtc->base.base.id);
8891
8892                 WARN(crtc->active && !crtc->base.enabled,
8893                      "active crtc, but not enabled in sw tracking\n");
8894
8895                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8896                                     base.head) {
8897                         if (encoder->base.crtc != &crtc->base)
8898                                 continue;
8899                         enabled = true;
8900                         if (encoder->connectors_active)
8901                                 active = true;
8902                 }
8903
8904                 WARN(active != crtc->active,
8905                      "crtc's computed active state doesn't match tracked active state "
8906                      "(expected %i, found %i)\n", active, crtc->active);
8907                 WARN(enabled != crtc->base.enabled,
8908                      "crtc's computed enabled state doesn't match tracked enabled state "
8909                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8910
8911                 active = dev_priv->display.get_pipe_config(crtc,
8912                                                            &pipe_config);
8913
8914                 /* hw state is inconsistent with the pipe A quirk */
8915                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8916                         active = crtc->active;
8917
8918                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8919                                     base.head) {
8920                         enum pipe pipe;
8921                         if (encoder->base.crtc != &crtc->base)
8922                                 continue;
8923                         if (encoder->get_config &&
8924                             encoder->get_hw_state(encoder, &pipe))
8925                                 encoder->get_config(encoder, &pipe_config);
8926                 }
8927
8928                 WARN(crtc->active != active,
8929                      "crtc active state doesn't match with hw state "
8930                      "(expected %i, found %i)\n", crtc->active, active);
8931
8932                 if (active &&
8933                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8934                         WARN(1, "pipe state doesn't match!\n");
8935                         intel_dump_pipe_config(crtc, &pipe_config,
8936                                                "[hw state]");
8937                         intel_dump_pipe_config(crtc, &crtc->config,
8938                                                "[sw state]");
8939                 }
8940         }
8941 }
8942
8943 static void
8944 check_shared_dpll_state(struct drm_device *dev)
8945 {
8946         drm_i915_private_t *dev_priv = dev->dev_private;
8947         struct intel_crtc *crtc;
8948         struct intel_dpll_hw_state dpll_hw_state;
8949         int i;
8950
8951         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8952                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8953                 int enabled_crtcs = 0, active_crtcs = 0;
8954                 bool active;
8955
8956                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8957
8958                 DRM_DEBUG_KMS("%s\n", pll->name);
8959
8960                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8961
8962                 WARN(pll->active > pll->refcount,
8963                      "more active pll users than references: %i vs %i\n",
8964                      pll->active, pll->refcount);
8965                 WARN(pll->active && !pll->on,
8966                      "pll in active use but not on in sw tracking\n");
8967                 WARN(pll->on && !pll->active,
8968                      "pll in on but not on in use in sw tracking\n");
8969                 WARN(pll->on != active,
8970                      "pll on state mismatch (expected %i, found %i)\n",
8971                      pll->on, active);
8972
8973                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8974                                     base.head) {
8975                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8976                                 enabled_crtcs++;
8977                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8978                                 active_crtcs++;
8979                 }
8980                 WARN(pll->active != active_crtcs,
8981                      "pll active crtcs mismatch (expected %i, found %i)\n",
8982                      pll->active, active_crtcs);
8983                 WARN(pll->refcount != enabled_crtcs,
8984                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8985                      pll->refcount, enabled_crtcs);
8986
8987                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8988                                        sizeof(dpll_hw_state)),
8989                      "pll hw state mismatch\n");
8990         }
8991 }
8992
8993 void
8994 intel_modeset_check_state(struct drm_device *dev)
8995 {
8996         check_connector_state(dev);
8997         check_encoder_state(dev);
8998         check_crtc_state(dev);
8999         check_shared_dpll_state(dev);
9000 }
9001
9002 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9003                                      int dotclock)
9004 {
9005         /*
9006          * FDI already provided one idea for the dotclock.
9007          * Yell if the encoder disagrees.
9008          */
9009         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.clock, dotclock),
9010              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9011              pipe_config->adjusted_mode.clock, dotclock);
9012 }
9013
9014 static int __intel_set_mode(struct drm_crtc *crtc,
9015                             struct drm_display_mode *mode,
9016                             int x, int y, struct drm_framebuffer *fb)
9017 {
9018         struct drm_device *dev = crtc->dev;
9019         drm_i915_private_t *dev_priv = dev->dev_private;
9020         struct drm_display_mode *saved_mode, *saved_hwmode;
9021         struct intel_crtc_config *pipe_config = NULL;
9022         struct intel_crtc *intel_crtc;
9023         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9024         int ret = 0;
9025
9026         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
9027         if (!saved_mode)
9028                 return -ENOMEM;
9029         saved_hwmode = saved_mode + 1;
9030
9031         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9032                                      &prepare_pipes, &disable_pipes);
9033
9034         *saved_hwmode = crtc->hwmode;
9035         *saved_mode = crtc->mode;
9036
9037         /* Hack: Because we don't (yet) support global modeset on multiple
9038          * crtcs, we don't keep track of the new mode for more than one crtc.
9039          * Hence simply check whether any bit is set in modeset_pipes in all the
9040          * pieces of code that are not yet converted to deal with mutliple crtcs
9041          * changing their mode at the same time. */
9042         if (modeset_pipes) {
9043                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9044                 if (IS_ERR(pipe_config)) {
9045                         ret = PTR_ERR(pipe_config);
9046                         pipe_config = NULL;
9047
9048                         goto out;
9049                 }
9050                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9051                                        "[modeset]");
9052         }
9053
9054         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9055                 intel_crtc_disable(&intel_crtc->base);
9056
9057         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9058                 if (intel_crtc->base.enabled)
9059                         dev_priv->display.crtc_disable(&intel_crtc->base);
9060         }
9061
9062         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9063          * to set it here already despite that we pass it down the callchain.
9064          */
9065         if (modeset_pipes) {
9066                 crtc->mode = *mode;
9067                 /* mode_set/enable/disable functions rely on a correct pipe
9068                  * config. */
9069                 to_intel_crtc(crtc)->config = *pipe_config;
9070         }
9071
9072         /* Only after disabling all output pipelines that will be changed can we
9073          * update the the output configuration. */
9074         intel_modeset_update_state(dev, prepare_pipes);
9075
9076         if (dev_priv->display.modeset_global_resources)
9077                 dev_priv->display.modeset_global_resources(dev);
9078
9079         /* Set up the DPLL and any encoders state that needs to adjust or depend
9080          * on the DPLL.
9081          */
9082         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9083                 ret = intel_crtc_mode_set(&intel_crtc->base,
9084                                           x, y, fb);
9085                 if (ret)
9086                         goto done;
9087         }
9088
9089         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9090         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9091                 dev_priv->display.crtc_enable(&intel_crtc->base);
9092
9093         if (modeset_pipes) {
9094                 /* Store real post-adjustment hardware mode. */
9095                 crtc->hwmode = pipe_config->adjusted_mode;
9096
9097                 /* Calculate and store various constants which
9098                  * are later needed by vblank and swap-completion
9099                  * timestamping. They are derived from true hwmode.
9100                  */
9101                 drm_calc_timestamping_constants(crtc);
9102         }
9103
9104         /* FIXME: add subpixel order */
9105 done:
9106         if (ret && crtc->enabled) {
9107                 crtc->hwmode = *saved_hwmode;
9108                 crtc->mode = *saved_mode;
9109         }
9110
9111 out:
9112         kfree(pipe_config);
9113         kfree(saved_mode);
9114         return ret;
9115 }
9116
9117 static int intel_set_mode(struct drm_crtc *crtc,
9118                           struct drm_display_mode *mode,
9119                           int x, int y, struct drm_framebuffer *fb)
9120 {
9121         int ret;
9122
9123         ret = __intel_set_mode(crtc, mode, x, y, fb);
9124
9125         if (ret == 0)
9126                 intel_modeset_check_state(crtc->dev);
9127
9128         return ret;
9129 }
9130
9131 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9132 {
9133         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9134 }
9135
9136 #undef for_each_intel_crtc_masked
9137
9138 static void intel_set_config_free(struct intel_set_config *config)
9139 {
9140         if (!config)
9141                 return;
9142
9143         kfree(config->save_connector_encoders);
9144         kfree(config->save_encoder_crtcs);
9145         kfree(config);
9146 }
9147
9148 static int intel_set_config_save_state(struct drm_device *dev,
9149                                        struct intel_set_config *config)
9150 {
9151         struct drm_encoder *encoder;
9152         struct drm_connector *connector;
9153         int count;
9154
9155         config->save_encoder_crtcs =
9156                 kcalloc(dev->mode_config.num_encoder,
9157                         sizeof(struct drm_crtc *), GFP_KERNEL);
9158         if (!config->save_encoder_crtcs)
9159                 return -ENOMEM;
9160
9161         config->save_connector_encoders =
9162                 kcalloc(dev->mode_config.num_connector,
9163                         sizeof(struct drm_encoder *), GFP_KERNEL);
9164         if (!config->save_connector_encoders)
9165                 return -ENOMEM;
9166
9167         /* Copy data. Note that driver private data is not affected.
9168          * Should anything bad happen only the expected state is
9169          * restored, not the drivers personal bookkeeping.
9170          */
9171         count = 0;
9172         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9173                 config->save_encoder_crtcs[count++] = encoder->crtc;
9174         }
9175
9176         count = 0;
9177         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9178                 config->save_connector_encoders[count++] = connector->encoder;
9179         }
9180
9181         return 0;
9182 }
9183
9184 static void intel_set_config_restore_state(struct drm_device *dev,
9185                                            struct intel_set_config *config)
9186 {
9187         struct intel_encoder *encoder;
9188         struct intel_connector *connector;
9189         int count;
9190
9191         count = 0;
9192         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9193                 encoder->new_crtc =
9194                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9195         }
9196
9197         count = 0;
9198         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9199                 connector->new_encoder =
9200                         to_intel_encoder(config->save_connector_encoders[count++]);
9201         }
9202 }
9203
9204 static bool
9205 is_crtc_connector_off(struct drm_mode_set *set)
9206 {
9207         int i;
9208
9209         if (set->num_connectors == 0)
9210                 return false;
9211
9212         if (WARN_ON(set->connectors == NULL))
9213                 return false;
9214
9215         for (i = 0; i < set->num_connectors; i++)
9216                 if (set->connectors[i]->encoder &&
9217                     set->connectors[i]->encoder->crtc == set->crtc &&
9218                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9219                         return true;
9220
9221         return false;
9222 }
9223
9224 static void
9225 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9226                                       struct intel_set_config *config)
9227 {
9228
9229         /* We should be able to check here if the fb has the same properties
9230          * and then just flip_or_move it */
9231         if (is_crtc_connector_off(set)) {
9232                 config->mode_changed = true;
9233         } else if (set->crtc->fb != set->fb) {
9234                 /* If we have no fb then treat it as a full mode set */
9235                 if (set->crtc->fb == NULL) {
9236                         struct intel_crtc *intel_crtc =
9237                                 to_intel_crtc(set->crtc);
9238
9239                         if (intel_crtc->active && i915_fastboot) {
9240                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9241                                 config->fb_changed = true;
9242                         } else {
9243                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9244                                 config->mode_changed = true;
9245                         }
9246                 } else if (set->fb == NULL) {
9247                         config->mode_changed = true;
9248                 } else if (set->fb->pixel_format !=
9249                            set->crtc->fb->pixel_format) {
9250                         config->mode_changed = true;
9251                 } else {
9252                         config->fb_changed = true;
9253                 }
9254         }
9255
9256         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9257                 config->fb_changed = true;
9258
9259         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9260                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9261                 drm_mode_debug_printmodeline(&set->crtc->mode);
9262                 drm_mode_debug_printmodeline(set->mode);
9263                 config->mode_changed = true;
9264         }
9265
9266         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9267                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9268 }
9269
9270 static int
9271 intel_modeset_stage_output_state(struct drm_device *dev,
9272                                  struct drm_mode_set *set,
9273                                  struct intel_set_config *config)
9274 {
9275         struct drm_crtc *new_crtc;
9276         struct intel_connector *connector;
9277         struct intel_encoder *encoder;
9278         int ro;
9279
9280         /* The upper layers ensure that we either disable a crtc or have a list
9281          * of connectors. For paranoia, double-check this. */
9282         WARN_ON(!set->fb && (set->num_connectors != 0));
9283         WARN_ON(set->fb && (set->num_connectors == 0));
9284
9285         list_for_each_entry(connector, &dev->mode_config.connector_list,
9286                             base.head) {
9287                 /* Otherwise traverse passed in connector list and get encoders
9288                  * for them. */
9289                 for (ro = 0; ro < set->num_connectors; ro++) {
9290                         if (set->connectors[ro] == &connector->base) {
9291                                 connector->new_encoder = connector->encoder;
9292                                 break;
9293                         }
9294                 }
9295
9296                 /* If we disable the crtc, disable all its connectors. Also, if
9297                  * the connector is on the changing crtc but not on the new
9298                  * connector list, disable it. */
9299                 if ((!set->fb || ro == set->num_connectors) &&
9300                     connector->base.encoder &&
9301                     connector->base.encoder->crtc == set->crtc) {
9302                         connector->new_encoder = NULL;
9303
9304                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9305                                 connector->base.base.id,
9306                                 drm_get_connector_name(&connector->base));
9307                 }
9308
9309
9310                 if (&connector->new_encoder->base != connector->base.encoder) {
9311                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9312                         config->mode_changed = true;
9313                 }
9314         }
9315         /* connector->new_encoder is now updated for all connectors. */
9316
9317         /* Update crtc of enabled connectors. */
9318         list_for_each_entry(connector, &dev->mode_config.connector_list,
9319                             base.head) {
9320                 if (!connector->new_encoder)
9321                         continue;
9322
9323                 new_crtc = connector->new_encoder->base.crtc;
9324
9325                 for (ro = 0; ro < set->num_connectors; ro++) {
9326                         if (set->connectors[ro] == &connector->base)
9327                                 new_crtc = set->crtc;
9328                 }
9329
9330                 /* Make sure the new CRTC will work with the encoder */
9331                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9332                                            new_crtc)) {
9333                         return -EINVAL;
9334                 }
9335                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9336
9337                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9338                         connector->base.base.id,
9339                         drm_get_connector_name(&connector->base),
9340                         new_crtc->base.id);
9341         }
9342
9343         /* Check for any encoders that needs to be disabled. */
9344         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9345                             base.head) {
9346                 list_for_each_entry(connector,
9347                                     &dev->mode_config.connector_list,
9348                                     base.head) {
9349                         if (connector->new_encoder == encoder) {
9350                                 WARN_ON(!connector->new_encoder->new_crtc);
9351
9352                                 goto next_encoder;
9353                         }
9354                 }
9355                 encoder->new_crtc = NULL;
9356 next_encoder:
9357                 /* Only now check for crtc changes so we don't miss encoders
9358                  * that will be disabled. */
9359                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9360                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9361                         config->mode_changed = true;
9362                 }
9363         }
9364         /* Now we've also updated encoder->new_crtc for all encoders. */
9365
9366         return 0;
9367 }
9368
9369 static int intel_crtc_set_config(struct drm_mode_set *set)
9370 {
9371         struct drm_device *dev;
9372         struct drm_mode_set save_set;
9373         struct intel_set_config *config;
9374         int ret;
9375
9376         BUG_ON(!set);
9377         BUG_ON(!set->crtc);
9378         BUG_ON(!set->crtc->helper_private);
9379
9380         /* Enforce sane interface api - has been abused by the fb helper. */
9381         BUG_ON(!set->mode && set->fb);
9382         BUG_ON(set->fb && set->num_connectors == 0);
9383
9384         if (set->fb) {
9385                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9386                                 set->crtc->base.id, set->fb->base.id,
9387                                 (int)set->num_connectors, set->x, set->y);
9388         } else {
9389                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9390         }
9391
9392         dev = set->crtc->dev;
9393
9394         ret = -ENOMEM;
9395         config = kzalloc(sizeof(*config), GFP_KERNEL);
9396         if (!config)
9397                 goto out_config;
9398
9399         ret = intel_set_config_save_state(dev, config);
9400         if (ret)
9401                 goto out_config;
9402
9403         save_set.crtc = set->crtc;
9404         save_set.mode = &set->crtc->mode;
9405         save_set.x = set->crtc->x;
9406         save_set.y = set->crtc->y;
9407         save_set.fb = set->crtc->fb;
9408
9409         /* Compute whether we need a full modeset, only an fb base update or no
9410          * change at all. In the future we might also check whether only the
9411          * mode changed, e.g. for LVDS where we only change the panel fitter in
9412          * such cases. */
9413         intel_set_config_compute_mode_changes(set, config);
9414
9415         ret = intel_modeset_stage_output_state(dev, set, config);
9416         if (ret)
9417                 goto fail;
9418
9419         if (config->mode_changed) {
9420                 ret = intel_set_mode(set->crtc, set->mode,
9421                                      set->x, set->y, set->fb);
9422         } else if (config->fb_changed) {
9423                 intel_crtc_wait_for_pending_flips(set->crtc);
9424
9425                 ret = intel_pipe_set_base(set->crtc,
9426                                           set->x, set->y, set->fb);
9427         }
9428
9429         if (ret) {
9430                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9431                               set->crtc->base.id, ret);
9432 fail:
9433                 intel_set_config_restore_state(dev, config);
9434
9435                 /* Try to restore the config */
9436                 if (config->mode_changed &&
9437                     intel_set_mode(save_set.crtc, save_set.mode,
9438                                    save_set.x, save_set.y, save_set.fb))
9439                         DRM_ERROR("failed to restore config after modeset failure\n");
9440         }
9441
9442 out_config:
9443         intel_set_config_free(config);
9444         return ret;
9445 }
9446
9447 static const struct drm_crtc_funcs intel_crtc_funcs = {
9448         .cursor_set = intel_crtc_cursor_set,
9449         .cursor_move = intel_crtc_cursor_move,
9450         .gamma_set = intel_crtc_gamma_set,
9451         .set_config = intel_crtc_set_config,
9452         .destroy = intel_crtc_destroy,
9453         .page_flip = intel_crtc_page_flip,
9454 };
9455
9456 static void intel_cpu_pll_init(struct drm_device *dev)
9457 {
9458         if (HAS_DDI(dev))
9459                 intel_ddi_pll_init(dev);
9460 }
9461
9462 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9463                                       struct intel_shared_dpll *pll,
9464                                       struct intel_dpll_hw_state *hw_state)
9465 {
9466         uint32_t val;
9467
9468         val = I915_READ(PCH_DPLL(pll->id));
9469         hw_state->dpll = val;
9470         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9471         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9472
9473         return val & DPLL_VCO_ENABLE;
9474 }
9475
9476 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9477                                   struct intel_shared_dpll *pll)
9478 {
9479         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9480         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9481 }
9482
9483 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9484                                 struct intel_shared_dpll *pll)
9485 {
9486         /* PCH refclock must be enabled first */
9487         assert_pch_refclk_enabled(dev_priv);
9488
9489         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9490
9491         /* Wait for the clocks to stabilize. */
9492         POSTING_READ(PCH_DPLL(pll->id));
9493         udelay(150);
9494
9495         /* The pixel multiplier can only be updated once the
9496          * DPLL is enabled and the clocks are stable.
9497          *
9498          * So write it again.
9499          */
9500         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9501         POSTING_READ(PCH_DPLL(pll->id));
9502         udelay(200);
9503 }
9504
9505 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9506                                  struct intel_shared_dpll *pll)
9507 {
9508         struct drm_device *dev = dev_priv->dev;
9509         struct intel_crtc *crtc;
9510
9511         /* Make sure no transcoder isn't still depending on us. */
9512         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9513                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9514                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9515         }
9516
9517         I915_WRITE(PCH_DPLL(pll->id), 0);
9518         POSTING_READ(PCH_DPLL(pll->id));
9519         udelay(200);
9520 }
9521
9522 static char *ibx_pch_dpll_names[] = {
9523         "PCH DPLL A",
9524         "PCH DPLL B",
9525 };
9526
9527 static void ibx_pch_dpll_init(struct drm_device *dev)
9528 {
9529         struct drm_i915_private *dev_priv = dev->dev_private;
9530         int i;
9531
9532         dev_priv->num_shared_dpll = 2;
9533
9534         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9535                 dev_priv->shared_dplls[i].id = i;
9536                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9537                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9538                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9539                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9540                 dev_priv->shared_dplls[i].get_hw_state =
9541                         ibx_pch_dpll_get_hw_state;
9542         }
9543 }
9544
9545 static void intel_shared_dpll_init(struct drm_device *dev)
9546 {
9547         struct drm_i915_private *dev_priv = dev->dev_private;
9548
9549         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9550                 ibx_pch_dpll_init(dev);
9551         else
9552                 dev_priv->num_shared_dpll = 0;
9553
9554         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9555         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9556                       dev_priv->num_shared_dpll);
9557 }
9558
9559 static void intel_crtc_init(struct drm_device *dev, int pipe)
9560 {
9561         drm_i915_private_t *dev_priv = dev->dev_private;
9562         struct intel_crtc *intel_crtc;
9563         int i;
9564
9565         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9566         if (intel_crtc == NULL)
9567                 return;
9568
9569         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9570
9571         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9572         for (i = 0; i < 256; i++) {
9573                 intel_crtc->lut_r[i] = i;
9574                 intel_crtc->lut_g[i] = i;
9575                 intel_crtc->lut_b[i] = i;
9576         }
9577
9578         /* Swap pipes & planes for FBC on pre-965 */
9579         intel_crtc->pipe = pipe;
9580         intel_crtc->plane = pipe;
9581         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9582                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9583                 intel_crtc->plane = !pipe;
9584         }
9585
9586         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9587                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9588         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9589         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9590
9591         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9592 }
9593
9594 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9595                                 struct drm_file *file)
9596 {
9597         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9598         struct drm_mode_object *drmmode_obj;
9599         struct intel_crtc *crtc;
9600
9601         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9602                 return -ENODEV;
9603
9604         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9605                         DRM_MODE_OBJECT_CRTC);
9606
9607         if (!drmmode_obj) {
9608                 DRM_ERROR("no such CRTC id\n");
9609                 return -EINVAL;
9610         }
9611
9612         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9613         pipe_from_crtc_id->pipe = crtc->pipe;
9614
9615         return 0;
9616 }
9617
9618 static int intel_encoder_clones(struct intel_encoder *encoder)
9619 {
9620         struct drm_device *dev = encoder->base.dev;
9621         struct intel_encoder *source_encoder;
9622         int index_mask = 0;
9623         int entry = 0;
9624
9625         list_for_each_entry(source_encoder,
9626                             &dev->mode_config.encoder_list, base.head) {
9627
9628                 if (encoder == source_encoder)
9629                         index_mask |= (1 << entry);
9630
9631                 /* Intel hw has only one MUX where enocoders could be cloned. */
9632                 if (encoder->cloneable && source_encoder->cloneable)
9633                         index_mask |= (1 << entry);
9634
9635                 entry++;
9636         }
9637
9638         return index_mask;
9639 }
9640
9641 static bool has_edp_a(struct drm_device *dev)
9642 {
9643         struct drm_i915_private *dev_priv = dev->dev_private;
9644
9645         if (!IS_MOBILE(dev))
9646                 return false;
9647
9648         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9649                 return false;
9650
9651         if (IS_GEN5(dev) &&
9652             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9653                 return false;
9654
9655         return true;
9656 }
9657
9658 static void intel_setup_outputs(struct drm_device *dev)
9659 {
9660         struct drm_i915_private *dev_priv = dev->dev_private;
9661         struct intel_encoder *encoder;
9662         bool dpd_is_edp = false;
9663
9664         intel_lvds_init(dev);
9665
9666         if (!IS_ULT(dev))
9667                 intel_crt_init(dev);
9668
9669         if (HAS_DDI(dev)) {
9670                 int found;
9671
9672                 /* Haswell uses DDI functions to detect digital outputs */
9673                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9674                 /* DDI A only supports eDP */
9675                 if (found)
9676                         intel_ddi_init(dev, PORT_A);
9677
9678                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9679                  * register */
9680                 found = I915_READ(SFUSE_STRAP);
9681
9682                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9683                         intel_ddi_init(dev, PORT_B);
9684                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9685                         intel_ddi_init(dev, PORT_C);
9686                 if (found & SFUSE_STRAP_DDID_DETECTED)
9687                         intel_ddi_init(dev, PORT_D);
9688         } else if (HAS_PCH_SPLIT(dev)) {
9689                 int found;
9690                 dpd_is_edp = intel_dpd_is_edp(dev);
9691
9692                 if (has_edp_a(dev))
9693                         intel_dp_init(dev, DP_A, PORT_A);
9694
9695                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9696                         /* PCH SDVOB multiplex with HDMIB */
9697                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9698                         if (!found)
9699                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9700                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9701                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9702                 }
9703
9704                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9705                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9706
9707                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9708                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9709
9710                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9711                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9712
9713                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9714                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9715         } else if (IS_VALLEYVIEW(dev)) {
9716                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9717                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9718                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9719                                         PORT_C);
9720                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9721                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9722                                               PORT_C);
9723                 }
9724
9725                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9726                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9727                                         PORT_B);
9728                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9729                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9730                 }
9731
9732                 intel_dsi_init(dev);
9733         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9734                 bool found = false;
9735
9736                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9737                         DRM_DEBUG_KMS("probing SDVOB\n");
9738                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9739                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9740                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9741                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9742                         }
9743
9744                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9745                                 intel_dp_init(dev, DP_B, PORT_B);
9746                 }
9747
9748                 /* Before G4X SDVOC doesn't have its own detect register */
9749
9750                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9751                         DRM_DEBUG_KMS("probing SDVOC\n");
9752                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9753                 }
9754
9755                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9756
9757                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9758                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9759                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9760                         }
9761                         if (SUPPORTS_INTEGRATED_DP(dev))
9762                                 intel_dp_init(dev, DP_C, PORT_C);
9763                 }
9764
9765                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9766                     (I915_READ(DP_D) & DP_DETECTED))
9767                         intel_dp_init(dev, DP_D, PORT_D);
9768         } else if (IS_GEN2(dev))
9769                 intel_dvo_init(dev);
9770
9771         if (SUPPORTS_TV(dev))
9772                 intel_tv_init(dev);
9773
9774         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9775                 encoder->base.possible_crtcs = encoder->crtc_mask;
9776                 encoder->base.possible_clones =
9777                         intel_encoder_clones(encoder);
9778         }
9779
9780         intel_init_pch_refclk(dev);
9781
9782         drm_helper_move_panel_connectors_to_head(dev);
9783 }
9784
9785 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9786 {
9787         drm_framebuffer_cleanup(&fb->base);
9788         drm_gem_object_unreference_unlocked(&fb->obj->base);
9789 }
9790
9791 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9792 {
9793         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9794
9795         intel_framebuffer_fini(intel_fb);
9796         kfree(intel_fb);
9797 }
9798
9799 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9800                                                 struct drm_file *file,
9801                                                 unsigned int *handle)
9802 {
9803         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9804         struct drm_i915_gem_object *obj = intel_fb->obj;
9805
9806         return drm_gem_handle_create(file, &obj->base, handle);
9807 }
9808
9809 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9810         .destroy = intel_user_framebuffer_destroy,
9811         .create_handle = intel_user_framebuffer_create_handle,
9812 };
9813
9814 int intel_framebuffer_init(struct drm_device *dev,
9815                            struct intel_framebuffer *intel_fb,
9816                            struct drm_mode_fb_cmd2 *mode_cmd,
9817                            struct drm_i915_gem_object *obj)
9818 {
9819         int pitch_limit;
9820         int ret;
9821
9822         if (obj->tiling_mode == I915_TILING_Y) {
9823                 DRM_DEBUG("hardware does not support tiling Y\n");
9824                 return -EINVAL;
9825         }
9826
9827         if (mode_cmd->pitches[0] & 63) {
9828                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9829                           mode_cmd->pitches[0]);
9830                 return -EINVAL;
9831         }
9832
9833         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9834                 pitch_limit = 32*1024;
9835         } else if (INTEL_INFO(dev)->gen >= 4) {
9836                 if (obj->tiling_mode)
9837                         pitch_limit = 16*1024;
9838                 else
9839                         pitch_limit = 32*1024;
9840         } else if (INTEL_INFO(dev)->gen >= 3) {
9841                 if (obj->tiling_mode)
9842                         pitch_limit = 8*1024;
9843                 else
9844                         pitch_limit = 16*1024;
9845         } else
9846                 /* XXX DSPC is limited to 4k tiled */
9847                 pitch_limit = 8*1024;
9848
9849         if (mode_cmd->pitches[0] > pitch_limit) {
9850                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9851                           obj->tiling_mode ? "tiled" : "linear",
9852                           mode_cmd->pitches[0], pitch_limit);
9853                 return -EINVAL;
9854         }
9855
9856         if (obj->tiling_mode != I915_TILING_NONE &&
9857             mode_cmd->pitches[0] != obj->stride) {
9858                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9859                           mode_cmd->pitches[0], obj->stride);
9860                 return -EINVAL;
9861         }
9862
9863         /* Reject formats not supported by any plane early. */
9864         switch (mode_cmd->pixel_format) {
9865         case DRM_FORMAT_C8:
9866         case DRM_FORMAT_RGB565:
9867         case DRM_FORMAT_XRGB8888:
9868         case DRM_FORMAT_ARGB8888:
9869                 break;
9870         case DRM_FORMAT_XRGB1555:
9871         case DRM_FORMAT_ARGB1555:
9872                 if (INTEL_INFO(dev)->gen > 3) {
9873                         DRM_DEBUG("unsupported pixel format: %s\n",
9874                                   drm_get_format_name(mode_cmd->pixel_format));
9875                         return -EINVAL;
9876                 }
9877                 break;
9878         case DRM_FORMAT_XBGR8888:
9879         case DRM_FORMAT_ABGR8888:
9880         case DRM_FORMAT_XRGB2101010:
9881         case DRM_FORMAT_ARGB2101010:
9882         case DRM_FORMAT_XBGR2101010:
9883         case DRM_FORMAT_ABGR2101010:
9884                 if (INTEL_INFO(dev)->gen < 4) {
9885                         DRM_DEBUG("unsupported pixel format: %s\n",
9886                                   drm_get_format_name(mode_cmd->pixel_format));
9887                         return -EINVAL;
9888                 }
9889                 break;
9890         case DRM_FORMAT_YUYV:
9891         case DRM_FORMAT_UYVY:
9892         case DRM_FORMAT_YVYU:
9893         case DRM_FORMAT_VYUY:
9894                 if (INTEL_INFO(dev)->gen < 5) {
9895                         DRM_DEBUG("unsupported pixel format: %s\n",
9896                                   drm_get_format_name(mode_cmd->pixel_format));
9897                         return -EINVAL;
9898                 }
9899                 break;
9900         default:
9901                 DRM_DEBUG("unsupported pixel format: %s\n",
9902                           drm_get_format_name(mode_cmd->pixel_format));
9903                 return -EINVAL;
9904         }
9905
9906         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9907         if (mode_cmd->offsets[0] != 0)
9908                 return -EINVAL;
9909
9910         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9911         intel_fb->obj = obj;
9912
9913         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9914         if (ret) {
9915                 DRM_ERROR("framebuffer init failed %d\n", ret);
9916                 return ret;
9917         }
9918
9919         return 0;
9920 }
9921
9922 static struct drm_framebuffer *
9923 intel_user_framebuffer_create(struct drm_device *dev,
9924                               struct drm_file *filp,
9925                               struct drm_mode_fb_cmd2 *mode_cmd)
9926 {
9927         struct drm_i915_gem_object *obj;
9928
9929         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9930                                                 mode_cmd->handles[0]));
9931         if (&obj->base == NULL)
9932                 return ERR_PTR(-ENOENT);
9933
9934         return intel_framebuffer_create(dev, mode_cmd, obj);
9935 }
9936
9937 static const struct drm_mode_config_funcs intel_mode_funcs = {
9938         .fb_create = intel_user_framebuffer_create,
9939         .output_poll_changed = intel_fb_output_poll_changed,
9940 };
9941
9942 /* Set up chip specific display functions */
9943 static void intel_init_display(struct drm_device *dev)
9944 {
9945         struct drm_i915_private *dev_priv = dev->dev_private;
9946
9947         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9948                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9949         else if (IS_VALLEYVIEW(dev))
9950                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9951         else if (IS_PINEVIEW(dev))
9952                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9953         else
9954                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9955
9956         if (HAS_DDI(dev)) {
9957                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9958                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9959                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9960                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9961                 dev_priv->display.off = haswell_crtc_off;
9962                 dev_priv->display.update_plane = ironlake_update_plane;
9963         } else if (HAS_PCH_SPLIT(dev)) {
9964                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9965                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9966                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9967                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9968                 dev_priv->display.off = ironlake_crtc_off;
9969                 dev_priv->display.update_plane = ironlake_update_plane;
9970         } else if (IS_VALLEYVIEW(dev)) {
9971                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9972                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9973                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9974                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9975                 dev_priv->display.off = i9xx_crtc_off;
9976                 dev_priv->display.update_plane = i9xx_update_plane;
9977         } else {
9978                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9979                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9980                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9981                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9982                 dev_priv->display.off = i9xx_crtc_off;
9983                 dev_priv->display.update_plane = i9xx_update_plane;
9984         }
9985
9986         /* Returns the core display clock speed */
9987         if (IS_VALLEYVIEW(dev))
9988                 dev_priv->display.get_display_clock_speed =
9989                         valleyview_get_display_clock_speed;
9990         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9991                 dev_priv->display.get_display_clock_speed =
9992                         i945_get_display_clock_speed;
9993         else if (IS_I915G(dev))
9994                 dev_priv->display.get_display_clock_speed =
9995                         i915_get_display_clock_speed;
9996         else if (IS_I945GM(dev) || IS_845G(dev))
9997                 dev_priv->display.get_display_clock_speed =
9998                         i9xx_misc_get_display_clock_speed;
9999         else if (IS_PINEVIEW(dev))
10000                 dev_priv->display.get_display_clock_speed =
10001                         pnv_get_display_clock_speed;
10002         else if (IS_I915GM(dev))
10003                 dev_priv->display.get_display_clock_speed =
10004                         i915gm_get_display_clock_speed;
10005         else if (IS_I865G(dev))
10006                 dev_priv->display.get_display_clock_speed =
10007                         i865_get_display_clock_speed;
10008         else if (IS_I85X(dev))
10009                 dev_priv->display.get_display_clock_speed =
10010                         i855_get_display_clock_speed;
10011         else /* 852, 830 */
10012                 dev_priv->display.get_display_clock_speed =
10013                         i830_get_display_clock_speed;
10014
10015         if (HAS_PCH_SPLIT(dev)) {
10016                 if (IS_GEN5(dev)) {
10017                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10018                         dev_priv->display.write_eld = ironlake_write_eld;
10019                 } else if (IS_GEN6(dev)) {
10020                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10021                         dev_priv->display.write_eld = ironlake_write_eld;
10022                 } else if (IS_IVYBRIDGE(dev)) {
10023                         /* FIXME: detect B0+ stepping and use auto training */
10024                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10025                         dev_priv->display.write_eld = ironlake_write_eld;
10026                         dev_priv->display.modeset_global_resources =
10027                                 ivb_modeset_global_resources;
10028                 } else if (IS_HASWELL(dev)) {
10029                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10030                         dev_priv->display.write_eld = haswell_write_eld;
10031                         dev_priv->display.modeset_global_resources =
10032                                 haswell_modeset_global_resources;
10033                 }
10034         } else if (IS_G4X(dev)) {
10035                 dev_priv->display.write_eld = g4x_write_eld;
10036         }
10037
10038         /* Default just returns -ENODEV to indicate unsupported */
10039         dev_priv->display.queue_flip = intel_default_queue_flip;
10040
10041         switch (INTEL_INFO(dev)->gen) {
10042         case 2:
10043                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10044                 break;
10045
10046         case 3:
10047                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10048                 break;
10049
10050         case 4:
10051         case 5:
10052                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10053                 break;
10054
10055         case 6:
10056                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10057                 break;
10058         case 7:
10059                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10060                 break;
10061         }
10062 }
10063
10064 /*
10065  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10066  * resume, or other times.  This quirk makes sure that's the case for
10067  * affected systems.
10068  */
10069 static void quirk_pipea_force(struct drm_device *dev)
10070 {
10071         struct drm_i915_private *dev_priv = dev->dev_private;
10072
10073         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10074         DRM_INFO("applying pipe a force quirk\n");
10075 }
10076
10077 /*
10078  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10079  */
10080 static void quirk_ssc_force_disable(struct drm_device *dev)
10081 {
10082         struct drm_i915_private *dev_priv = dev->dev_private;
10083         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10084         DRM_INFO("applying lvds SSC disable quirk\n");
10085 }
10086
10087 /*
10088  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10089  * brightness value
10090  */
10091 static void quirk_invert_brightness(struct drm_device *dev)
10092 {
10093         struct drm_i915_private *dev_priv = dev->dev_private;
10094         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10095         DRM_INFO("applying inverted panel brightness quirk\n");
10096 }
10097
10098 /*
10099  * Some machines (Dell XPS13) suffer broken backlight controls if
10100  * BLM_PCH_PWM_ENABLE is set.
10101  */
10102 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10103 {
10104         struct drm_i915_private *dev_priv = dev->dev_private;
10105         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10106         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10107 }
10108
10109 struct intel_quirk {
10110         int device;
10111         int subsystem_vendor;
10112         int subsystem_device;
10113         void (*hook)(struct drm_device *dev);
10114 };
10115
10116 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10117 struct intel_dmi_quirk {
10118         void (*hook)(struct drm_device *dev);
10119         const struct dmi_system_id (*dmi_id_list)[];
10120 };
10121
10122 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10123 {
10124         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10125         return 1;
10126 }
10127
10128 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10129         {
10130                 .dmi_id_list = &(const struct dmi_system_id[]) {
10131                         {
10132                                 .callback = intel_dmi_reverse_brightness,
10133                                 .ident = "NCR Corporation",
10134                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10135                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10136                                 },
10137                         },
10138                         { }  /* terminating entry */
10139                 },
10140                 .hook = quirk_invert_brightness,
10141         },
10142 };
10143
10144 static struct intel_quirk intel_quirks[] = {
10145         /* HP Mini needs pipe A force quirk (LP: #322104) */
10146         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10147
10148         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10149         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10150
10151         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10152         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10153
10154         /* 830/845 need to leave pipe A & dpll A up */
10155         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10156         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10157
10158         /* Lenovo U160 cannot use SSC on LVDS */
10159         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10160
10161         /* Sony Vaio Y cannot use SSC on LVDS */
10162         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10163
10164         /* Acer Aspire 5734Z must invert backlight brightness */
10165         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
10166
10167         /* Acer/eMachines G725 */
10168         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
10169
10170         /* Acer/eMachines e725 */
10171         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
10172
10173         /* Acer/Packard Bell NCL20 */
10174         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
10175
10176         /* Acer Aspire 4736Z */
10177         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
10178
10179         /* Dell XPS13 HD Sandy Bridge */
10180         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10181         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10182         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10183 };
10184
10185 static void intel_init_quirks(struct drm_device *dev)
10186 {
10187         struct pci_dev *d = dev->pdev;
10188         int i;
10189
10190         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10191                 struct intel_quirk *q = &intel_quirks[i];
10192
10193                 if (d->device == q->device &&
10194                     (d->subsystem_vendor == q->subsystem_vendor ||
10195                      q->subsystem_vendor == PCI_ANY_ID) &&
10196                     (d->subsystem_device == q->subsystem_device ||
10197                      q->subsystem_device == PCI_ANY_ID))
10198                         q->hook(dev);
10199         }
10200         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10201                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10202                         intel_dmi_quirks[i].hook(dev);
10203         }
10204 }
10205
10206 /* Disable the VGA plane that we never use */
10207 static void i915_disable_vga(struct drm_device *dev)
10208 {
10209         struct drm_i915_private *dev_priv = dev->dev_private;
10210         u8 sr1;
10211         u32 vga_reg = i915_vgacntrl_reg(dev);
10212
10213         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10214         outb(SR01, VGA_SR_INDEX);
10215         sr1 = inb(VGA_SR_DATA);
10216         outb(sr1 | 1<<5, VGA_SR_DATA);
10217
10218         /* Disable VGA memory on Intel HD */
10219         if (HAS_PCH_SPLIT(dev)) {
10220                 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10221                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10222                                                    VGA_RSRC_NORMAL_IO |
10223                                                    VGA_RSRC_NORMAL_MEM);
10224         }
10225
10226         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10227         udelay(300);
10228
10229         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10230         POSTING_READ(vga_reg);
10231 }
10232
10233 static void i915_enable_vga(struct drm_device *dev)
10234 {
10235         /* Enable VGA memory on Intel HD */
10236         if (HAS_PCH_SPLIT(dev)) {
10237                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10238                 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10239                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10240                                                    VGA_RSRC_LEGACY_MEM |
10241                                                    VGA_RSRC_NORMAL_IO |
10242                                                    VGA_RSRC_NORMAL_MEM);
10243                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10244         }
10245 }
10246
10247 void intel_modeset_init_hw(struct drm_device *dev)
10248 {
10249         intel_init_power_well(dev);
10250
10251         intel_prepare_ddi(dev);
10252
10253         intel_init_clock_gating(dev);
10254
10255         mutex_lock(&dev->struct_mutex);
10256         intel_enable_gt_powersave(dev);
10257         mutex_unlock(&dev->struct_mutex);
10258 }
10259
10260 void intel_modeset_suspend_hw(struct drm_device *dev)
10261 {
10262         intel_suspend_hw(dev);
10263 }
10264
10265 void intel_modeset_init(struct drm_device *dev)
10266 {
10267         struct drm_i915_private *dev_priv = dev->dev_private;
10268         int i, j, ret;
10269
10270         drm_mode_config_init(dev);
10271
10272         dev->mode_config.min_width = 0;
10273         dev->mode_config.min_height = 0;
10274
10275         dev->mode_config.preferred_depth = 24;
10276         dev->mode_config.prefer_shadow = 1;
10277
10278         dev->mode_config.funcs = &intel_mode_funcs;
10279
10280         intel_init_quirks(dev);
10281
10282         intel_init_pm(dev);
10283
10284         if (INTEL_INFO(dev)->num_pipes == 0)
10285                 return;
10286
10287         intel_init_display(dev);
10288
10289         if (IS_GEN2(dev)) {
10290                 dev->mode_config.max_width = 2048;
10291                 dev->mode_config.max_height = 2048;
10292         } else if (IS_GEN3(dev)) {
10293                 dev->mode_config.max_width = 4096;
10294                 dev->mode_config.max_height = 4096;
10295         } else {
10296                 dev->mode_config.max_width = 8192;
10297                 dev->mode_config.max_height = 8192;
10298         }
10299         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10300
10301         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10302                       INTEL_INFO(dev)->num_pipes,
10303                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10304
10305         for_each_pipe(i) {
10306                 intel_crtc_init(dev, i);
10307                 for (j = 0; j < dev_priv->num_plane; j++) {
10308                         ret = intel_plane_init(dev, i, j);
10309                         if (ret)
10310                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10311                                               pipe_name(i), sprite_name(i, j), ret);
10312                 }
10313         }
10314
10315         intel_cpu_pll_init(dev);
10316         intel_shared_dpll_init(dev);
10317
10318         /* Just disable it once at startup */
10319         i915_disable_vga(dev);
10320         intel_setup_outputs(dev);
10321
10322         /* Just in case the BIOS is doing something questionable. */
10323         intel_disable_fbc(dev);
10324 }
10325
10326 static void
10327 intel_connector_break_all_links(struct intel_connector *connector)
10328 {
10329         connector->base.dpms = DRM_MODE_DPMS_OFF;
10330         connector->base.encoder = NULL;
10331         connector->encoder->connectors_active = false;
10332         connector->encoder->base.crtc = NULL;
10333 }
10334
10335 static void intel_enable_pipe_a(struct drm_device *dev)
10336 {
10337         struct intel_connector *connector;
10338         struct drm_connector *crt = NULL;
10339         struct intel_load_detect_pipe load_detect_temp;
10340
10341         /* We can't just switch on the pipe A, we need to set things up with a
10342          * proper mode and output configuration. As a gross hack, enable pipe A
10343          * by enabling the load detect pipe once. */
10344         list_for_each_entry(connector,
10345                             &dev->mode_config.connector_list,
10346                             base.head) {
10347                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10348                         crt = &connector->base;
10349                         break;
10350                 }
10351         }
10352
10353         if (!crt)
10354                 return;
10355
10356         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10357                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10358
10359
10360 }
10361
10362 static bool
10363 intel_check_plane_mapping(struct intel_crtc *crtc)
10364 {
10365         struct drm_device *dev = crtc->base.dev;
10366         struct drm_i915_private *dev_priv = dev->dev_private;
10367         u32 reg, val;
10368
10369         if (INTEL_INFO(dev)->num_pipes == 1)
10370                 return true;
10371
10372         reg = DSPCNTR(!crtc->plane);
10373         val = I915_READ(reg);
10374
10375         if ((val & DISPLAY_PLANE_ENABLE) &&
10376             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10377                 return false;
10378
10379         return true;
10380 }
10381
10382 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10383 {
10384         struct drm_device *dev = crtc->base.dev;
10385         struct drm_i915_private *dev_priv = dev->dev_private;
10386         u32 reg;
10387
10388         /* Clear any frame start delays used for debugging left by the BIOS */
10389         reg = PIPECONF(crtc->config.cpu_transcoder);
10390         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10391
10392         /* We need to sanitize the plane -> pipe mapping first because this will
10393          * disable the crtc (and hence change the state) if it is wrong. Note
10394          * that gen4+ has a fixed plane -> pipe mapping.  */
10395         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10396                 struct intel_connector *connector;
10397                 bool plane;
10398
10399                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10400                               crtc->base.base.id);
10401
10402                 /* Pipe has the wrong plane attached and the plane is active.
10403                  * Temporarily change the plane mapping and disable everything
10404                  * ...  */
10405                 plane = crtc->plane;
10406                 crtc->plane = !plane;
10407                 dev_priv->display.crtc_disable(&crtc->base);
10408                 crtc->plane = plane;
10409
10410                 /* ... and break all links. */
10411                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10412                                     base.head) {
10413                         if (connector->encoder->base.crtc != &crtc->base)
10414                                 continue;
10415
10416                         intel_connector_break_all_links(connector);
10417                 }
10418
10419                 WARN_ON(crtc->active);
10420                 crtc->base.enabled = false;
10421         }
10422
10423         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10424             crtc->pipe == PIPE_A && !crtc->active) {
10425                 /* BIOS forgot to enable pipe A, this mostly happens after
10426                  * resume. Force-enable the pipe to fix this, the update_dpms
10427                  * call below we restore the pipe to the right state, but leave
10428                  * the required bits on. */
10429                 intel_enable_pipe_a(dev);
10430         }
10431
10432         /* Adjust the state of the output pipe according to whether we
10433          * have active connectors/encoders. */
10434         intel_crtc_update_dpms(&crtc->base);
10435
10436         if (crtc->active != crtc->base.enabled) {
10437                 struct intel_encoder *encoder;
10438
10439                 /* This can happen either due to bugs in the get_hw_state
10440                  * functions or because the pipe is force-enabled due to the
10441                  * pipe A quirk. */
10442                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10443                               crtc->base.base.id,
10444                               crtc->base.enabled ? "enabled" : "disabled",
10445                               crtc->active ? "enabled" : "disabled");
10446
10447                 crtc->base.enabled = crtc->active;
10448
10449                 /* Because we only establish the connector -> encoder ->
10450                  * crtc links if something is active, this means the
10451                  * crtc is now deactivated. Break the links. connector
10452                  * -> encoder links are only establish when things are
10453                  *  actually up, hence no need to break them. */
10454                 WARN_ON(crtc->active);
10455
10456                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10457                         WARN_ON(encoder->connectors_active);
10458                         encoder->base.crtc = NULL;
10459                 }
10460         }
10461 }
10462
10463 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10464 {
10465         struct intel_connector *connector;
10466         struct drm_device *dev = encoder->base.dev;
10467
10468         /* We need to check both for a crtc link (meaning that the
10469          * encoder is active and trying to read from a pipe) and the
10470          * pipe itself being active. */
10471         bool has_active_crtc = encoder->base.crtc &&
10472                 to_intel_crtc(encoder->base.crtc)->active;
10473
10474         if (encoder->connectors_active && !has_active_crtc) {
10475                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10476                               encoder->base.base.id,
10477                               drm_get_encoder_name(&encoder->base));
10478
10479                 /* Connector is active, but has no active pipe. This is
10480                  * fallout from our resume register restoring. Disable
10481                  * the encoder manually again. */
10482                 if (encoder->base.crtc) {
10483                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10484                                       encoder->base.base.id,
10485                                       drm_get_encoder_name(&encoder->base));
10486                         encoder->disable(encoder);
10487                 }
10488
10489                 /* Inconsistent output/port/pipe state happens presumably due to
10490                  * a bug in one of the get_hw_state functions. Or someplace else
10491                  * in our code, like the register restore mess on resume. Clamp
10492                  * things to off as a safer default. */
10493                 list_for_each_entry(connector,
10494                                     &dev->mode_config.connector_list,
10495                                     base.head) {
10496                         if (connector->encoder != encoder)
10497                                 continue;
10498
10499                         intel_connector_break_all_links(connector);
10500                 }
10501         }
10502         /* Enabled encoders without active connectors will be fixed in
10503          * the crtc fixup. */
10504 }
10505
10506 void i915_redisable_vga(struct drm_device *dev)
10507 {
10508         struct drm_i915_private *dev_priv = dev->dev_private;
10509         u32 vga_reg = i915_vgacntrl_reg(dev);
10510
10511         /* This function can be called both from intel_modeset_setup_hw_state or
10512          * at a very early point in our resume sequence, where the power well
10513          * structures are not yet restored. Since this function is at a very
10514          * paranoid "someone might have enabled VGA while we were not looking"
10515          * level, just check if the power well is enabled instead of trying to
10516          * follow the "don't touch the power well if we don't need it" policy
10517          * the rest of the driver uses. */
10518         if (HAS_POWER_WELL(dev) &&
10519             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10520                 return;
10521
10522         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10523                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10524                 i915_disable_vga(dev);
10525         }
10526 }
10527
10528 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10529 {
10530         struct drm_i915_private *dev_priv = dev->dev_private;
10531         enum pipe pipe;
10532         struct intel_crtc *crtc;
10533         struct intel_encoder *encoder;
10534         struct intel_connector *connector;
10535         int i;
10536
10537         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10538                             base.head) {
10539                 memset(&crtc->config, 0, sizeof(crtc->config));
10540
10541                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10542                                                                  &crtc->config);
10543
10544                 crtc->base.enabled = crtc->active;
10545
10546                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10547                               crtc->base.base.id,
10548                               crtc->active ? "enabled" : "disabled");
10549         }
10550
10551         /* FIXME: Smash this into the new shared dpll infrastructure. */
10552         if (HAS_DDI(dev))
10553                 intel_ddi_setup_hw_pll_state(dev);
10554
10555         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10556                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10557
10558                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10559                 pll->active = 0;
10560                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10561                                     base.head) {
10562                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10563                                 pll->active++;
10564                 }
10565                 pll->refcount = pll->active;
10566
10567                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10568                               pll->name, pll->refcount, pll->on);
10569         }
10570
10571         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10572                             base.head) {
10573                 pipe = 0;
10574
10575                 if (encoder->get_hw_state(encoder, &pipe)) {
10576                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10577                         encoder->base.crtc = &crtc->base;
10578                         if (encoder->get_config)
10579                                 encoder->get_config(encoder, &crtc->config);
10580                 } else {
10581                         encoder->base.crtc = NULL;
10582                 }
10583
10584                 encoder->connectors_active = false;
10585                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10586                               encoder->base.base.id,
10587                               drm_get_encoder_name(&encoder->base),
10588                               encoder->base.crtc ? "enabled" : "disabled",
10589                               pipe);
10590         }
10591
10592         list_for_each_entry(connector, &dev->mode_config.connector_list,
10593                             base.head) {
10594                 if (connector->get_hw_state(connector)) {
10595                         connector->base.dpms = DRM_MODE_DPMS_ON;
10596                         connector->encoder->connectors_active = true;
10597                         connector->base.encoder = &connector->encoder->base;
10598                 } else {
10599                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10600                         connector->base.encoder = NULL;
10601                 }
10602                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10603                               connector->base.base.id,
10604                               drm_get_connector_name(&connector->base),
10605                               connector->base.encoder ? "enabled" : "disabled");
10606         }
10607 }
10608
10609 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10610  * and i915 state tracking structures. */
10611 void intel_modeset_setup_hw_state(struct drm_device *dev,
10612                                   bool force_restore)
10613 {
10614         struct drm_i915_private *dev_priv = dev->dev_private;
10615         enum pipe pipe;
10616         struct drm_plane *plane;
10617         struct intel_crtc *crtc;
10618         struct intel_encoder *encoder;
10619         int i;
10620
10621         intel_modeset_readout_hw_state(dev);
10622
10623         /*
10624          * Now that we have the config, copy it to each CRTC struct
10625          * Note that this could go away if we move to using crtc_config
10626          * checking everywhere.
10627          */
10628         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10629                             base.head) {
10630                 if (crtc->active && i915_fastboot) {
10631                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10632
10633                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10634                                       crtc->base.base.id);
10635                         drm_mode_debug_printmodeline(&crtc->base.mode);
10636                 }
10637         }
10638
10639         /* HW state is read out, now we need to sanitize this mess. */
10640         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10641                             base.head) {
10642                 intel_sanitize_encoder(encoder);
10643         }
10644
10645         for_each_pipe(pipe) {
10646                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10647                 intel_sanitize_crtc(crtc);
10648                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10649         }
10650
10651         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10652                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10653
10654                 if (!pll->on || pll->active)
10655                         continue;
10656
10657                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10658
10659                 pll->disable(dev_priv, pll);
10660                 pll->on = false;
10661         }
10662
10663         if (force_restore) {
10664                 /*
10665                  * We need to use raw interfaces for restoring state to avoid
10666                  * checking (bogus) intermediate states.
10667                  */
10668                 for_each_pipe(pipe) {
10669                         struct drm_crtc *crtc =
10670                                 dev_priv->pipe_to_crtc_mapping[pipe];
10671
10672                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10673                                          crtc->fb);
10674                 }
10675                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10676                         intel_plane_restore(plane);
10677
10678                 i915_redisable_vga(dev);
10679         } else {
10680                 intel_modeset_update_staged_output_state(dev);
10681         }
10682
10683         intel_modeset_check_state(dev);
10684
10685         drm_mode_config_reset(dev);
10686 }
10687
10688 void intel_modeset_gem_init(struct drm_device *dev)
10689 {
10690         intel_modeset_init_hw(dev);
10691
10692         intel_setup_overlay(dev);
10693
10694         intel_modeset_setup_hw_state(dev, false);
10695 }
10696
10697 void intel_modeset_cleanup(struct drm_device *dev)
10698 {
10699         struct drm_i915_private *dev_priv = dev->dev_private;
10700         struct drm_crtc *crtc;
10701
10702         /*
10703          * Interrupts and polling as the first thing to avoid creating havoc.
10704          * Too much stuff here (turning of rps, connectors, ...) would
10705          * experience fancy races otherwise.
10706          */
10707         drm_irq_uninstall(dev);
10708         cancel_work_sync(&dev_priv->hotplug_work);
10709         /*
10710          * Due to the hpd irq storm handling the hotplug work can re-arm the
10711          * poll handlers. Hence disable polling after hpd handling is shut down.
10712          */
10713         drm_kms_helper_poll_fini(dev);
10714
10715         mutex_lock(&dev->struct_mutex);
10716
10717         intel_unregister_dsm_handler();
10718
10719         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10720                 /* Skip inactive CRTCs */
10721                 if (!crtc->fb)
10722                         continue;
10723
10724                 intel_increase_pllclock(crtc);
10725         }
10726
10727         intel_disable_fbc(dev);
10728
10729         i915_enable_vga(dev);
10730
10731         intel_disable_gt_powersave(dev);
10732
10733         ironlake_teardown_rc6(dev);
10734
10735         mutex_unlock(&dev->struct_mutex);
10736
10737         /* flush any delayed tasks or pending work */
10738         flush_scheduled_work();
10739
10740         /* destroy backlight, if any, before the connectors */
10741         intel_panel_destroy_backlight(dev);
10742
10743         drm_mode_config_cleanup(dev);
10744
10745         intel_cleanup_overlay(dev);
10746 }
10747
10748 /*
10749  * Return which encoder is currently attached for connector.
10750  */
10751 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10752 {
10753         return &intel_attached_encoder(connector)->base;
10754 }
10755
10756 void intel_connector_attach_encoder(struct intel_connector *connector,
10757                                     struct intel_encoder *encoder)
10758 {
10759         connector->encoder = encoder;
10760         drm_mode_connector_attach_encoder(&connector->base,
10761                                           &encoder->base);
10762 }
10763
10764 /*
10765  * set vga decode state - true == enable VGA decode
10766  */
10767 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10768 {
10769         struct drm_i915_private *dev_priv = dev->dev_private;
10770         u16 gmch_ctrl;
10771
10772         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10773         if (state)
10774                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10775         else
10776                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10777         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10778         return 0;
10779 }
10780
10781 struct intel_display_error_state {
10782
10783         u32 power_well_driver;
10784
10785         int num_transcoders;
10786
10787         struct intel_cursor_error_state {
10788                 u32 control;
10789                 u32 position;
10790                 u32 base;
10791                 u32 size;
10792         } cursor[I915_MAX_PIPES];
10793
10794         struct intel_pipe_error_state {
10795                 u32 source;
10796         } pipe[I915_MAX_PIPES];
10797
10798         struct intel_plane_error_state {
10799                 u32 control;
10800                 u32 stride;
10801                 u32 size;
10802                 u32 pos;
10803                 u32 addr;
10804                 u32 surface;
10805                 u32 tile_offset;
10806         } plane[I915_MAX_PIPES];
10807
10808         struct intel_transcoder_error_state {
10809                 enum transcoder cpu_transcoder;
10810
10811                 u32 conf;
10812
10813                 u32 htotal;
10814                 u32 hblank;
10815                 u32 hsync;
10816                 u32 vtotal;
10817                 u32 vblank;
10818                 u32 vsync;
10819         } transcoder[4];
10820 };
10821
10822 struct intel_display_error_state *
10823 intel_display_capture_error_state(struct drm_device *dev)
10824 {
10825         drm_i915_private_t *dev_priv = dev->dev_private;
10826         struct intel_display_error_state *error;
10827         int transcoders[] = {
10828                 TRANSCODER_A,
10829                 TRANSCODER_B,
10830                 TRANSCODER_C,
10831                 TRANSCODER_EDP,
10832         };
10833         int i;
10834
10835         if (INTEL_INFO(dev)->num_pipes == 0)
10836                 return NULL;
10837
10838         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10839         if (error == NULL)
10840                 return NULL;
10841
10842         if (HAS_POWER_WELL(dev))
10843                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10844
10845         for_each_pipe(i) {
10846                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10847                         error->cursor[i].control = I915_READ(CURCNTR(i));
10848                         error->cursor[i].position = I915_READ(CURPOS(i));
10849                         error->cursor[i].base = I915_READ(CURBASE(i));
10850                 } else {
10851                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10852                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10853                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10854                 }
10855
10856                 error->plane[i].control = I915_READ(DSPCNTR(i));
10857                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10858                 if (INTEL_INFO(dev)->gen <= 3) {
10859                         error->plane[i].size = I915_READ(DSPSIZE(i));
10860                         error->plane[i].pos = I915_READ(DSPPOS(i));
10861                 }
10862                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10863                         error->plane[i].addr = I915_READ(DSPADDR(i));
10864                 if (INTEL_INFO(dev)->gen >= 4) {
10865                         error->plane[i].surface = I915_READ(DSPSURF(i));
10866                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10867                 }
10868
10869                 error->pipe[i].source = I915_READ(PIPESRC(i));
10870         }
10871
10872         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10873         if (HAS_DDI(dev_priv->dev))
10874                 error->num_transcoders++; /* Account for eDP. */
10875
10876         for (i = 0; i < error->num_transcoders; i++) {
10877                 enum transcoder cpu_transcoder = transcoders[i];
10878
10879                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10880
10881                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10882                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10883                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10884                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10885                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10886                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10887                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10888         }
10889
10890         /* In the code above we read the registers without checking if the power
10891          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10892          * prevent the next I915_WRITE from detecting it and printing an error
10893          * message. */
10894         intel_uncore_clear_errors(dev);
10895
10896         return error;
10897 }
10898
10899 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10900
10901 void
10902 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10903                                 struct drm_device *dev,
10904                                 struct intel_display_error_state *error)
10905 {
10906         int i;
10907
10908         if (!error)
10909                 return;
10910
10911         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10912         if (HAS_POWER_WELL(dev))
10913                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10914                            error->power_well_driver);
10915         for_each_pipe(i) {
10916                 err_printf(m, "Pipe [%d]:\n", i);
10917                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10918
10919                 err_printf(m, "Plane [%d]:\n", i);
10920                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10921                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10922                 if (INTEL_INFO(dev)->gen <= 3) {
10923                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10924                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10925                 }
10926                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10927                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10928                 if (INTEL_INFO(dev)->gen >= 4) {
10929                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10930                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10931                 }
10932
10933                 err_printf(m, "Cursor [%d]:\n", i);
10934                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10935                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10936                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10937         }
10938
10939         for (i = 0; i < error->num_transcoders; i++) {
10940                 err_printf(m, "  CPU transcoder: %c\n",
10941                            transcoder_name(error->transcoder[i].cpu_transcoder));
10942                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
10943                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
10944                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
10945                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
10946                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
10947                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
10948                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
10949         }
10950 }