2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
53 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
66 typedef struct intel_limit intel_limit_t;
68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_pch_rawclk(struct drm_device *dev)
75 struct drm_i915_private *dev_priv = dev->dev_private;
77 WARN_ON(!HAS_PCH_SPLIT(dev));
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
82 static inline u32 /* units of 100MHz */
83 intel_fdi_link_freq(struct drm_device *dev)
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
92 static const intel_limit_t intel_limits_i8xx_dac = {
93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
105 static const intel_limit_t intel_limits_i8xx_dvo = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 2, .max = 33 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 4, .p2_fast = 4 },
118 static const intel_limit_t intel_limits_i8xx_lvds = {
119 .dot = { .min = 25000, .max = 350000 },
120 .vco = { .min = 930000, .max = 1400000 },
121 .n = { .min = 3, .max = 16 },
122 .m = { .min = 96, .max = 140 },
123 .m1 = { .min = 18, .max = 26 },
124 .m2 = { .min = 6, .max = 16 },
125 .p = { .min = 4, .max = 128 },
126 .p1 = { .min = 1, .max = 6 },
127 .p2 = { .dot_limit = 165000,
128 .p2_slow = 14, .p2_fast = 7 },
131 static const intel_limit_t intel_limits_i9xx_sdvo = {
132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
138 .p = { .min = 5, .max = 80 },
139 .p1 = { .min = 1, .max = 8 },
140 .p2 = { .dot_limit = 200000,
141 .p2_slow = 10, .p2_fast = 5 },
144 static const intel_limit_t intel_limits_i9xx_lvds = {
145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 8, .max = 18 },
150 .m2 = { .min = 3, .max = 7 },
151 .p = { .min = 7, .max = 98 },
152 .p1 = { .min = 1, .max = 8 },
153 .p2 = { .dot_limit = 112000,
154 .p2_slow = 14, .p2_fast = 7 },
158 static const intel_limit_t intel_limits_g4x_sdvo = {
159 .dot = { .min = 25000, .max = 270000 },
160 .vco = { .min = 1750000, .max = 3500000},
161 .n = { .min = 1, .max = 4 },
162 .m = { .min = 104, .max = 138 },
163 .m1 = { .min = 17, .max = 23 },
164 .m2 = { .min = 5, .max = 11 },
165 .p = { .min = 10, .max = 30 },
166 .p1 = { .min = 1, .max = 3},
167 .p2 = { .dot_limit = 270000,
173 static const intel_limit_t intel_limits_g4x_hdmi = {
174 .dot = { .min = 22000, .max = 400000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 16, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 5, .max = 80 },
181 .p1 = { .min = 1, .max = 8},
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 10, .p2_fast = 5 },
186 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
187 .dot = { .min = 20000, .max = 115000 },
188 .vco = { .min = 1750000, .max = 3500000 },
189 .n = { .min = 1, .max = 3 },
190 .m = { .min = 104, .max = 138 },
191 .m1 = { .min = 17, .max = 23 },
192 .m2 = { .min = 5, .max = 11 },
193 .p = { .min = 28, .max = 112 },
194 .p1 = { .min = 2, .max = 8 },
195 .p2 = { .dot_limit = 0,
196 .p2_slow = 14, .p2_fast = 14
200 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
201 .dot = { .min = 80000, .max = 224000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 14, .max = 42 },
208 .p1 = { .min = 2, .max = 6 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 7, .p2_fast = 7
214 static const intel_limit_t intel_limits_pineview_sdvo = {
215 .dot = { .min = 20000, .max = 400000},
216 .vco = { .min = 1700000, .max = 3500000 },
217 /* Pineview's Ncounter is a ring counter */
218 .n = { .min = 3, .max = 6 },
219 .m = { .min = 2, .max = 256 },
220 /* Pineview only has one combined m divider, which we treat as m2. */
221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 5, .max = 80 },
224 .p1 = { .min = 1, .max = 8 },
225 .p2 = { .dot_limit = 200000,
226 .p2_slow = 10, .p2_fast = 5 },
229 static const intel_limit_t intel_limits_pineview_lvds = {
230 .dot = { .min = 20000, .max = 400000 },
231 .vco = { .min = 1700000, .max = 3500000 },
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 .m1 = { .min = 0, .max = 0 },
235 .m2 = { .min = 0, .max = 254 },
236 .p = { .min = 7, .max = 112 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 112000,
239 .p2_slow = 14, .p2_fast = 14 },
242 /* Ironlake / Sandybridge
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
247 static const intel_limit_t intel_limits_ironlake_dac = {
248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 5 },
251 .m = { .min = 79, .max = 127 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 5, .max = 80 },
255 .p1 = { .min = 1, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 10, .p2_fast = 5 },
260 static const intel_limit_t intel_limits_ironlake_single_lvds = {
261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 118 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 28, .max = 112 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 14, .p2_fast = 14 },
273 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 3 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 14, .max = 56 },
281 .p1 = { .min = 2, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 7, .p2_fast = 7 },
286 /* LVDS 100mhz refclk limits. */
287 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 2 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
300 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 126 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 42 },
308 .p1 = { .min = 2, .max = 6 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
313 static const intel_limit_t intel_limits_vlv_dac = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 22, .max = 450 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
321 .p1 = { .min = 1, .max = 3 },
322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
326 static const intel_limit_t intel_limits_vlv_hdmi = {
327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 60, .max = 300 }, /* guess */
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 2, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
339 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
342 struct drm_device *dev = crtc->dev;
343 const intel_limit_t *limit;
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
346 if (intel_is_dual_link_lvds(dev)) {
347 if (refclk == 100000)
348 limit = &intel_limits_ironlake_dual_lvds_100m;
350 limit = &intel_limits_ironlake_dual_lvds;
352 if (refclk == 100000)
353 limit = &intel_limits_ironlake_single_lvds_100m;
355 limit = &intel_limits_ironlake_single_lvds;
358 limit = &intel_limits_ironlake_dac;
363 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
365 struct drm_device *dev = crtc->dev;
366 const intel_limit_t *limit;
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
369 if (intel_is_dual_link_lvds(dev))
370 limit = &intel_limits_g4x_dual_channel_lvds;
372 limit = &intel_limits_g4x_single_channel_lvds;
373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
375 limit = &intel_limits_g4x_hdmi;
376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
377 limit = &intel_limits_g4x_sdvo;
378 } else /* The option is for other outputs */
379 limit = &intel_limits_i9xx_sdvo;
384 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
389 if (HAS_PCH_SPLIT(dev))
390 limit = intel_ironlake_limit(crtc, refclk);
391 else if (IS_G4X(dev)) {
392 limit = intel_g4x_limit(crtc);
393 } else if (IS_PINEVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
395 limit = &intel_limits_pineview_lvds;
397 limit = &intel_limits_pineview_sdvo;
398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
402 limit = &intel_limits_vlv_hdmi;
403 } else if (!IS_GEN2(dev)) {
404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
405 limit = &intel_limits_i9xx_lvds;
407 limit = &intel_limits_i9xx_sdvo;
409 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
410 limit = &intel_limits_i8xx_lvds;
411 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
412 limit = &intel_limits_i8xx_dvo;
414 limit = &intel_limits_i8xx_dac;
419 /* m1 is reserved as 0 in Pineview, n is a ring counter */
420 static void pineview_clock(int refclk, intel_clock_t *clock)
422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
428 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
433 static void i9xx_clock(int refclk, intel_clock_t *clock)
435 clock->m = i9xx_dpll_compute_m(clock);
436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
442 * Returns whether any output on the specified pipe is of the specified type
444 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
446 struct drm_device *dev = crtc->dev;
447 struct intel_encoder *encoder;
449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
456 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
462 static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
467 INTELPllInvalid("p1 out of range\n");
468 if (clock->p < limit->p.min || limit->p.max < clock->p)
469 INTELPllInvalid("p out of range\n");
470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
471 INTELPllInvalid("m2 out of range\n");
472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
473 INTELPllInvalid("m1 out of range\n");
474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
475 INTELPllInvalid("m1 <= m2\n");
476 if (clock->m < limit->m.min || limit->m.max < clock->m)
477 INTELPllInvalid("m out of range\n");
478 if (clock->n < limit->n.min || limit->n.max < clock->n)
479 INTELPllInvalid("n out of range\n");
480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
481 INTELPllInvalid("vco out of range\n");
482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
486 INTELPllInvalid("dot out of range\n");
492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
496 struct drm_device *dev = crtc->dev;
500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
506 if (intel_is_dual_link_lvds(dev))
507 clock.p2 = limit->p2.p2_fast;
509 clock.p2 = limit->p2.p2_slow;
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
514 clock.p2 = limit->p2.p2_fast;
517 memset(best_clock, 0, sizeof(*best_clock));
519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
523 if (clock.m2 >= clock.m1)
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
536 clock.p != match_clock->p)
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
549 return (err != target);
553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
557 struct drm_device *dev = crtc->dev;
561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
567 if (intel_is_dual_link_lvds(dev))
568 clock.p2 = limit->p2.p2_fast;
570 clock.p2 = limit->p2.p2_slow;
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
575 clock.p2 = limit->p2.p2_fast;
578 memset(best_clock, 0, sizeof(*best_clock));
580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
590 pineview_clock(refclk, &clock);
591 if (!intel_PLL_is_valid(dev, limit,
595 clock.p != match_clock->p)
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
608 return (err != target);
612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
616 struct drm_device *dev = crtc->dev;
620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
625 if (intel_is_dual_link_lvds(dev))
626 clock.p2 = limit->p2.p2_fast;
628 clock.p2 = limit->p2.p2_slow;
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
633 clock.p2 = limit->p2.p2_fast;
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
638 /* based on hardware requirement, prefer smaller n to precision */
639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
640 /* based on hardware requirement, prefere larger m1,m2 */
641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
649 i9xx_clock(refclk, &clock);
650 if (!intel_PLL_is_valid(dev, limit,
654 this_err = abs(clock.dot - target);
655 if (this_err < err_most) {
669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
675 u32 updrate, minupdate, p;
676 unsigned long bestppm, ppm, absppm;
680 dotclk = target * 1000;
683 fastclk = dotclk / (2*100);
686 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
687 bestm1 = bestm2 = bestp1 = bestp2 = 0;
689 /* based on hardware requirement, prefer smaller n to precision */
690 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
691 updrate = refclk / n;
692 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
693 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
697 /* based on hardware requirement, prefer bigger m1,m2 values */
698 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
699 m2 = (((2*(fastclk * p * n / m1 )) +
700 refclk) / (2*refclk));
703 if (vco >= limit->vco.min && vco < limit->vco.max) {
704 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
705 absppm = (ppm > 0) ? ppm : (-ppm);
706 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
710 if (absppm < bestppm - 10) {
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
736 bool intel_crtc_active(struct drm_crtc *crtc)
738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
740 /* Be paranoid as we can arrive here with only partial
741 * state retrieved from the hardware during setup.
743 * We can ditch the adjusted_mode.clock check as soon
744 * as Haswell has gained clock readout/fastboot support.
746 * We can ditch the crtc->fb check as soon as we can
747 * properly reconstruct framebuffers.
749 return intel_crtc->active && crtc->fb &&
750 intel_crtc->config.adjusted_mode.clock;
753 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
756 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
759 return intel_crtc->config.cpu_transcoder;
762 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 u32 frame, frame_reg = PIPEFRAME(pipe);
767 frame = I915_READ(frame_reg);
769 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
770 DRM_DEBUG_KMS("vblank wait timed out\n");
774 * intel_wait_for_vblank - wait for vblank on a given pipe
776 * @pipe: pipe to wait for
778 * Wait for vblank to occur on a given pipe. Needed for various bits of
781 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 int pipestat_reg = PIPESTAT(pipe);
786 if (INTEL_INFO(dev)->gen >= 5) {
787 ironlake_wait_for_vblank(dev, pipe);
791 /* Clear existing vblank status. Note this will clear any other
792 * sticky status fields as well.
794 * This races with i915_driver_irq_handler() with the result
795 * that either function could miss a vblank event. Here it is not
796 * fatal, as we will either wait upon the next vblank interrupt or
797 * timeout. Generally speaking intel_wait_for_vblank() is only
798 * called during modeset at which time the GPU should be idle and
799 * should *not* be performing page flips and thus not waiting on
801 * Currently, the result of us stealing a vblank from the irq
802 * handler is that a single frame will be skipped during swapbuffers.
804 I915_WRITE(pipestat_reg,
805 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
807 /* Wait for vblank interrupt bit to set */
808 if (wait_for(I915_READ(pipestat_reg) &
809 PIPE_VBLANK_INTERRUPT_STATUS,
811 DRM_DEBUG_KMS("vblank wait timed out\n");
815 * intel_wait_for_pipe_off - wait for pipe to turn off
817 * @pipe: pipe to wait for
819 * After disabling a pipe, we can't wait for vblank in the usual way,
820 * spinning on the vblank interrupt status bit, since we won't actually
821 * see an interrupt when the pipe is disabled.
824 * wait for the pipe register state bit to turn off
827 * wait for the display line value to settle (it usually
828 * ends up stopping at the start of the next frame).
831 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
833 struct drm_i915_private *dev_priv = dev->dev_private;
834 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
837 if (INTEL_INFO(dev)->gen >= 4) {
838 int reg = PIPECONF(cpu_transcoder);
840 /* Wait for the Pipe State to go off */
841 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
843 WARN(1, "pipe_off wait timed out\n");
845 u32 last_line, line_mask;
846 int reg = PIPEDSL(pipe);
847 unsigned long timeout = jiffies + msecs_to_jiffies(100);
850 line_mask = DSL_LINEMASK_GEN2;
852 line_mask = DSL_LINEMASK_GEN3;
854 /* Wait for the display line to settle */
856 last_line = I915_READ(reg) & line_mask;
858 } while (((I915_READ(reg) & line_mask) != last_line) &&
859 time_after(timeout, jiffies));
860 if (time_after(jiffies, timeout))
861 WARN(1, "pipe_off wait timed out\n");
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
870 * Returns true if @port is connected, false otherwise.
872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
877 if (HAS_PCH_IBX(dev_priv->dev)) {
880 bit = SDE_PORTB_HOTPLUG;
883 bit = SDE_PORTC_HOTPLUG;
886 bit = SDE_PORTD_HOTPLUG;
894 bit = SDE_PORTB_HOTPLUG_CPT;
897 bit = SDE_PORTC_HOTPLUG_CPT;
900 bit = SDE_PORTD_HOTPLUG_CPT;
907 return I915_READ(SDEISR) & bit;
910 static const char *state_string(bool enabled)
912 return enabled ? "on" : "off";
915 /* Only for pre-ILK configs */
916 void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
931 /* XXX: the dsi pll is shared between MIPI DSI ports */
932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
949 struct intel_shared_dpll *
950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
954 if (crtc->config.shared_dpll < 0)
957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
966 struct intel_dpll_hw_state hw_state;
968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
974 "asserting DPLL %s with no DPLL\n", state_string(state)))
977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
978 WARN(cur_state != state,
979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
995 val = I915_READ(reg);
996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037 if (HAS_DDI(dev_priv->dev))
1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1063 int pp_reg, lvds_reg;
1065 enum pipe panel_pipe = PIPE_A;
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1072 pp_reg = PP_CONTROL;
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1092 struct drm_device *dev = dev_priv->dev;
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
1133 pipe_name(pipe), state_string(state), state_string(cur_state));
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1157 struct drm_device *dev = dev_priv->dev;
1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1172 /* Need to check both planes against the pipe */
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1187 struct drm_device *dev = dev_priv->dev;
1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1201 val = I915_READ(reg);
1202 WARN((val & SPRITE_ENABLE),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
1207 val = I915_READ(reg);
1208 WARN((val & DVS_ENABLE),
1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210 plane_name(pipe), pipe_name(pipe));
1214 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1237 reg = PCH_TRANSCONF(pipe);
1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
1248 if ((val & DP_PORT_EN) == 0)
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1266 if ((val & SDVO_ENABLE) == 0)
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1282 if ((val & LVDS_PORT_EN) == 0)
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311 enum pipe pipe, int reg, u32 port_sel)
1313 u32 val = I915_READ(reg);
1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316 reg, pipe_name(pipe));
1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
1320 "IBX PCH dp port still using transcoder B\n");
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1326 u32 val = I915_READ(reg);
1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329 reg, pipe_name(pipe));
1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332 && (val & SDVO_PIPE_B_SELECT),
1333 "IBX PCH hdmi port still using transcoder B\n");
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1347 val = I915_READ(reg);
1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
1353 val = I915_READ(reg);
1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1363 static void vlv_enable_pll(struct intel_crtc *crtc)
1365 struct drm_device *dev = crtc->base.dev;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 int reg = DPLL(crtc->pipe);
1368 u32 dpll = crtc->config.dpll_hw_state.dpll;
1370 assert_pipe_disabled(dev_priv, crtc->pipe);
1372 /* No really, not for ILK+ */
1373 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1375 /* PLL is protected by panel, make sure we can write it */
1376 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1377 assert_panel_unlocked(dev_priv, crtc->pipe);
1379 I915_WRITE(reg, dpll);
1383 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1384 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1386 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1387 POSTING_READ(DPLL_MD(crtc->pipe));
1389 /* We do this three times for luck */
1390 I915_WRITE(reg, dpll);
1392 udelay(150); /* wait for warmup */
1393 I915_WRITE(reg, dpll);
1395 udelay(150); /* wait for warmup */
1396 I915_WRITE(reg, dpll);
1398 udelay(150); /* wait for warmup */
1401 static void i9xx_enable_pll(struct intel_crtc *crtc)
1403 struct drm_device *dev = crtc->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 int reg = DPLL(crtc->pipe);
1406 u32 dpll = crtc->config.dpll_hw_state.dpll;
1408 assert_pipe_disabled(dev_priv, crtc->pipe);
1410 /* No really, not for ILK+ */
1411 BUG_ON(dev_priv->info->gen >= 5);
1413 /* PLL is protected by panel, make sure we can write it */
1414 if (IS_MOBILE(dev) && !IS_I830(dev))
1415 assert_panel_unlocked(dev_priv, crtc->pipe);
1417 I915_WRITE(reg, dpll);
1419 /* Wait for the clocks to stabilize. */
1423 if (INTEL_INFO(dev)->gen >= 4) {
1424 I915_WRITE(DPLL_MD(crtc->pipe),
1425 crtc->config.dpll_hw_state.dpll_md);
1427 /* The pixel multiplier can only be updated once the
1428 * DPLL is enabled and the clocks are stable.
1430 * So write it again.
1432 I915_WRITE(reg, dpll);
1435 /* We do this three times for luck */
1436 I915_WRITE(reg, dpll);
1438 udelay(150); /* wait for warmup */
1439 I915_WRITE(reg, dpll);
1441 udelay(150); /* wait for warmup */
1442 I915_WRITE(reg, dpll);
1444 udelay(150); /* wait for warmup */
1448 * i9xx_disable_pll - disable a PLL
1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to disable
1452 * Disable the PLL for @pipe, making sure the pipe is off first.
1454 * Note! This is for pre-ILK only.
1456 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1458 /* Don't disable pipe A or pipe A PLLs if needed */
1459 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1462 /* Make sure the pipe isn't still relying on us */
1463 assert_pipe_disabled(dev_priv, pipe);
1465 I915_WRITE(DPLL(pipe), 0);
1466 POSTING_READ(DPLL(pipe));
1469 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1474 port_mask = DPLL_PORTB_READY_MASK;
1476 port_mask = DPLL_PORTC_READY_MASK;
1478 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1479 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1480 'B' + port, I915_READ(DPLL(0)));
1484 * ironlake_enable_shared_dpll - enable PCH PLL
1485 * @dev_priv: i915 private structure
1486 * @pipe: pipe PLL to enable
1488 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1489 * drives the transcoder clock.
1491 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1493 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1494 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1496 /* PCH PLLs only available on ILK, SNB and IVB */
1497 BUG_ON(dev_priv->info->gen < 5);
1498 if (WARN_ON(pll == NULL))
1501 if (WARN_ON(pll->refcount == 0))
1504 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1505 pll->name, pll->active, pll->on,
1506 crtc->base.base.id);
1508 if (pll->active++) {
1510 assert_shared_dpll_enabled(dev_priv, pll);
1515 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1516 pll->enable(dev_priv, pll);
1520 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1522 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1523 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1525 /* PCH only available on ILK+ */
1526 BUG_ON(dev_priv->info->gen < 5);
1527 if (WARN_ON(pll == NULL))
1530 if (WARN_ON(pll->refcount == 0))
1533 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1534 pll->name, pll->active, pll->on,
1535 crtc->base.base.id);
1537 if (WARN_ON(pll->active == 0)) {
1538 assert_shared_dpll_disabled(dev_priv, pll);
1542 assert_shared_dpll_enabled(dev_priv, pll);
1547 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1548 pll->disable(dev_priv, pll);
1552 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1555 struct drm_device *dev = dev_priv->dev;
1556 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1558 uint32_t reg, val, pipeconf_val;
1560 /* PCH only available on ILK+ */
1561 BUG_ON(dev_priv->info->gen < 5);
1563 /* Make sure PCH DPLL is enabled */
1564 assert_shared_dpll_enabled(dev_priv,
1565 intel_crtc_to_shared_dpll(intel_crtc));
1567 /* FDI must be feeding us bits for PCH ports */
1568 assert_fdi_tx_enabled(dev_priv, pipe);
1569 assert_fdi_rx_enabled(dev_priv, pipe);
1571 if (HAS_PCH_CPT(dev)) {
1572 /* Workaround: Set the timing override bit before enabling the
1573 * pch transcoder. */
1574 reg = TRANS_CHICKEN2(pipe);
1575 val = I915_READ(reg);
1576 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1577 I915_WRITE(reg, val);
1580 reg = PCH_TRANSCONF(pipe);
1581 val = I915_READ(reg);
1582 pipeconf_val = I915_READ(PIPECONF(pipe));
1584 if (HAS_PCH_IBX(dev_priv->dev)) {
1586 * make the BPC in transcoder be consistent with
1587 * that in pipeconf reg.
1589 val &= ~PIPECONF_BPC_MASK;
1590 val |= pipeconf_val & PIPECONF_BPC_MASK;
1593 val &= ~TRANS_INTERLACE_MASK;
1594 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1595 if (HAS_PCH_IBX(dev_priv->dev) &&
1596 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1597 val |= TRANS_LEGACY_INTERLACED_ILK;
1599 val |= TRANS_INTERLACED;
1601 val |= TRANS_PROGRESSIVE;
1603 I915_WRITE(reg, val | TRANS_ENABLE);
1604 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1605 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1608 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1609 enum transcoder cpu_transcoder)
1611 u32 val, pipeconf_val;
1613 /* PCH only available on ILK+ */
1614 BUG_ON(dev_priv->info->gen < 5);
1616 /* FDI must be feeding us bits for PCH ports */
1617 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1618 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1620 /* Workaround: set timing override bit. */
1621 val = I915_READ(_TRANSA_CHICKEN2);
1622 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1623 I915_WRITE(_TRANSA_CHICKEN2, val);
1626 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1628 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1629 PIPECONF_INTERLACED_ILK)
1630 val |= TRANS_INTERLACED;
1632 val |= TRANS_PROGRESSIVE;
1634 I915_WRITE(LPT_TRANSCONF, val);
1635 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1636 DRM_ERROR("Failed to enable PCH transcoder\n");
1639 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1642 struct drm_device *dev = dev_priv->dev;
1645 /* FDI relies on the transcoder */
1646 assert_fdi_tx_disabled(dev_priv, pipe);
1647 assert_fdi_rx_disabled(dev_priv, pipe);
1649 /* Ports must be off as well */
1650 assert_pch_ports_disabled(dev_priv, pipe);
1652 reg = PCH_TRANSCONF(pipe);
1653 val = I915_READ(reg);
1654 val &= ~TRANS_ENABLE;
1655 I915_WRITE(reg, val);
1656 /* wait for PCH transcoder off, transcoder state */
1657 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1658 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1660 if (!HAS_PCH_IBX(dev)) {
1661 /* Workaround: Clear the timing override chicken bit again. */
1662 reg = TRANS_CHICKEN2(pipe);
1663 val = I915_READ(reg);
1664 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1665 I915_WRITE(reg, val);
1669 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1673 val = I915_READ(LPT_TRANSCONF);
1674 val &= ~TRANS_ENABLE;
1675 I915_WRITE(LPT_TRANSCONF, val);
1676 /* wait for PCH transcoder off, transcoder state */
1677 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1678 DRM_ERROR("Failed to disable PCH transcoder\n");
1680 /* Workaround: clear timing override bit. */
1681 val = I915_READ(_TRANSA_CHICKEN2);
1682 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1683 I915_WRITE(_TRANSA_CHICKEN2, val);
1687 * intel_enable_pipe - enable a pipe, asserting requirements
1688 * @dev_priv: i915 private structure
1689 * @pipe: pipe to enable
1690 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1692 * Enable @pipe, making sure that various hardware specific requirements
1693 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1695 * @pipe should be %PIPE_A or %PIPE_B.
1697 * Will wait until the pipe is actually running (i.e. first vblank) before
1700 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1701 bool pch_port, bool dsi)
1703 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1705 enum pipe pch_transcoder;
1709 assert_planes_disabled(dev_priv, pipe);
1710 assert_cursor_disabled(dev_priv, pipe);
1711 assert_sprites_disabled(dev_priv, pipe);
1713 if (HAS_PCH_LPT(dev_priv->dev))
1714 pch_transcoder = TRANSCODER_A;
1716 pch_transcoder = pipe;
1719 * A pipe without a PLL won't actually be able to drive bits from
1720 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1723 if (!HAS_PCH_SPLIT(dev_priv->dev))
1725 assert_dsi_pll_enabled(dev_priv);
1727 assert_pll_enabled(dev_priv, pipe);
1730 /* if driving the PCH, we need FDI enabled */
1731 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1732 assert_fdi_tx_pll_enabled(dev_priv,
1733 (enum pipe) cpu_transcoder);
1735 /* FIXME: assert CPU port conditions for SNB+ */
1738 reg = PIPECONF(cpu_transcoder);
1739 val = I915_READ(reg);
1740 if (val & PIPECONF_ENABLE)
1743 I915_WRITE(reg, val | PIPECONF_ENABLE);
1744 intel_wait_for_vblank(dev_priv->dev, pipe);
1748 * intel_disable_pipe - disable a pipe, asserting requirements
1749 * @dev_priv: i915 private structure
1750 * @pipe: pipe to disable
1752 * Disable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1755 * @pipe should be %PIPE_A or %PIPE_B.
1757 * Will wait until the pipe has shut down before returning.
1759 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1768 * Make sure planes won't keep trying to pump pixels to us,
1769 * or we might hang the display.
1771 assert_planes_disabled(dev_priv, pipe);
1772 assert_cursor_disabled(dev_priv, pipe);
1773 assert_sprites_disabled(dev_priv, pipe);
1775 /* Don't disable pipe A or pipe A PLLs if needed */
1776 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1779 reg = PIPECONF(cpu_transcoder);
1780 val = I915_READ(reg);
1781 if ((val & PIPECONF_ENABLE) == 0)
1784 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1785 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1789 * Plane regs are double buffered, going from enabled->disabled needs a
1790 * trigger in order to latch. The display address reg provides this.
1792 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1795 if (dev_priv->info->gen >= 4)
1796 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1798 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1802 * intel_enable_plane - enable a display plane on a given pipe
1803 * @dev_priv: i915 private structure
1804 * @plane: plane to enable
1805 * @pipe: pipe being fed
1807 * Enable @plane on @pipe, making sure that @pipe is running first.
1809 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1810 enum plane plane, enum pipe pipe)
1815 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1816 assert_pipe_enabled(dev_priv, pipe);
1818 reg = DSPCNTR(plane);
1819 val = I915_READ(reg);
1820 if (val & DISPLAY_PLANE_ENABLE)
1823 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1824 intel_flush_display_plane(dev_priv, plane);
1825 intel_wait_for_vblank(dev_priv->dev, pipe);
1829 * intel_disable_plane - disable a display plane
1830 * @dev_priv: i915 private structure
1831 * @plane: plane to disable
1832 * @pipe: pipe consuming the data
1834 * Disable @plane; should be an independent operation.
1836 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1837 enum plane plane, enum pipe pipe)
1842 reg = DSPCNTR(plane);
1843 val = I915_READ(reg);
1844 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1847 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1848 intel_flush_display_plane(dev_priv, plane);
1849 intel_wait_for_vblank(dev_priv->dev, pipe);
1852 static bool need_vtd_wa(struct drm_device *dev)
1854 #ifdef CONFIG_INTEL_IOMMU
1855 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1862 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1863 struct drm_i915_gem_object *obj,
1864 struct intel_ring_buffer *pipelined)
1866 struct drm_i915_private *dev_priv = dev->dev_private;
1870 switch (obj->tiling_mode) {
1871 case I915_TILING_NONE:
1872 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1873 alignment = 128 * 1024;
1874 else if (INTEL_INFO(dev)->gen >= 4)
1875 alignment = 4 * 1024;
1877 alignment = 64 * 1024;
1880 /* pin() will align the object as required by fence */
1884 /* Despite that we check this in framebuffer_init userspace can
1885 * screw us over and change the tiling after the fact. Only
1886 * pinned buffers can't change their tiling. */
1887 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1893 /* Note that the w/a also requires 64 PTE of padding following the
1894 * bo. We currently fill all unused PTE with the shadow page and so
1895 * we should always have valid PTE following the scanout preventing
1898 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1899 alignment = 256 * 1024;
1901 dev_priv->mm.interruptible = false;
1902 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1904 goto err_interruptible;
1906 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1907 * fence, whereas 965+ only requires a fence if using
1908 * framebuffer compression. For simplicity, we always install
1909 * a fence as the cost is not that onerous.
1911 ret = i915_gem_object_get_fence(obj);
1915 i915_gem_object_pin_fence(obj);
1917 dev_priv->mm.interruptible = true;
1921 i915_gem_object_unpin_from_display_plane(obj);
1923 dev_priv->mm.interruptible = true;
1927 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1929 i915_gem_object_unpin_fence(obj);
1930 i915_gem_object_unpin_from_display_plane(obj);
1933 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1934 * is assumed to be a power-of-two. */
1935 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1936 unsigned int tiling_mode,
1940 if (tiling_mode != I915_TILING_NONE) {
1941 unsigned int tile_rows, tiles;
1946 tiles = *x / (512/cpp);
1949 return tile_rows * pitch * 8 + tiles * 4096;
1951 unsigned int offset;
1953 offset = *y * pitch + *x * cpp;
1955 *x = (offset & 4095) / cpp;
1956 return offset & -4096;
1960 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1963 struct drm_device *dev = crtc->dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966 struct intel_framebuffer *intel_fb;
1967 struct drm_i915_gem_object *obj;
1968 int plane = intel_crtc->plane;
1969 unsigned long linear_offset;
1978 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1982 intel_fb = to_intel_framebuffer(fb);
1983 obj = intel_fb->obj;
1985 reg = DSPCNTR(plane);
1986 dspcntr = I915_READ(reg);
1987 /* Mask out pixel format bits in case we change it */
1988 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1989 switch (fb->pixel_format) {
1991 dspcntr |= DISPPLANE_8BPP;
1993 case DRM_FORMAT_XRGB1555:
1994 case DRM_FORMAT_ARGB1555:
1995 dspcntr |= DISPPLANE_BGRX555;
1997 case DRM_FORMAT_RGB565:
1998 dspcntr |= DISPPLANE_BGRX565;
2000 case DRM_FORMAT_XRGB8888:
2001 case DRM_FORMAT_ARGB8888:
2002 dspcntr |= DISPPLANE_BGRX888;
2004 case DRM_FORMAT_XBGR8888:
2005 case DRM_FORMAT_ABGR8888:
2006 dspcntr |= DISPPLANE_RGBX888;
2008 case DRM_FORMAT_XRGB2101010:
2009 case DRM_FORMAT_ARGB2101010:
2010 dspcntr |= DISPPLANE_BGRX101010;
2012 case DRM_FORMAT_XBGR2101010:
2013 case DRM_FORMAT_ABGR2101010:
2014 dspcntr |= DISPPLANE_RGBX101010;
2020 if (INTEL_INFO(dev)->gen >= 4) {
2021 if (obj->tiling_mode != I915_TILING_NONE)
2022 dspcntr |= DISPPLANE_TILED;
2024 dspcntr &= ~DISPPLANE_TILED;
2028 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2030 I915_WRITE(reg, dspcntr);
2032 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2034 if (INTEL_INFO(dev)->gen >= 4) {
2035 intel_crtc->dspaddr_offset =
2036 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2037 fb->bits_per_pixel / 8,
2039 linear_offset -= intel_crtc->dspaddr_offset;
2041 intel_crtc->dspaddr_offset = linear_offset;
2044 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2045 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2047 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2048 if (INTEL_INFO(dev)->gen >= 4) {
2049 I915_MODIFY_DISPBASE(DSPSURF(plane),
2050 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2051 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2052 I915_WRITE(DSPLINOFF(plane), linear_offset);
2054 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2060 static int ironlake_update_plane(struct drm_crtc *crtc,
2061 struct drm_framebuffer *fb, int x, int y)
2063 struct drm_device *dev = crtc->dev;
2064 struct drm_i915_private *dev_priv = dev->dev_private;
2065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2066 struct intel_framebuffer *intel_fb;
2067 struct drm_i915_gem_object *obj;
2068 int plane = intel_crtc->plane;
2069 unsigned long linear_offset;
2079 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2083 intel_fb = to_intel_framebuffer(fb);
2084 obj = intel_fb->obj;
2086 reg = DSPCNTR(plane);
2087 dspcntr = I915_READ(reg);
2088 /* Mask out pixel format bits in case we change it */
2089 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2090 switch (fb->pixel_format) {
2092 dspcntr |= DISPPLANE_8BPP;
2094 case DRM_FORMAT_RGB565:
2095 dspcntr |= DISPPLANE_BGRX565;
2097 case DRM_FORMAT_XRGB8888:
2098 case DRM_FORMAT_ARGB8888:
2099 dspcntr |= DISPPLANE_BGRX888;
2101 case DRM_FORMAT_XBGR8888:
2102 case DRM_FORMAT_ABGR8888:
2103 dspcntr |= DISPPLANE_RGBX888;
2105 case DRM_FORMAT_XRGB2101010:
2106 case DRM_FORMAT_ARGB2101010:
2107 dspcntr |= DISPPLANE_BGRX101010;
2109 case DRM_FORMAT_XBGR2101010:
2110 case DRM_FORMAT_ABGR2101010:
2111 dspcntr |= DISPPLANE_RGBX101010;
2117 if (obj->tiling_mode != I915_TILING_NONE)
2118 dspcntr |= DISPPLANE_TILED;
2120 dspcntr &= ~DISPPLANE_TILED;
2122 if (IS_HASWELL(dev))
2123 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2125 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2127 I915_WRITE(reg, dspcntr);
2129 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2130 intel_crtc->dspaddr_offset =
2131 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2132 fb->bits_per_pixel / 8,
2134 linear_offset -= intel_crtc->dspaddr_offset;
2136 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2139 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2140 I915_MODIFY_DISPBASE(DSPSURF(plane),
2141 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2142 if (IS_HASWELL(dev)) {
2143 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2145 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2146 I915_WRITE(DSPLINOFF(plane), linear_offset);
2153 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2155 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2156 int x, int y, enum mode_set_atomic state)
2158 struct drm_device *dev = crtc->dev;
2159 struct drm_i915_private *dev_priv = dev->dev_private;
2161 if (dev_priv->display.disable_fbc)
2162 dev_priv->display.disable_fbc(dev);
2163 intel_increase_pllclock(crtc);
2165 return dev_priv->display.update_plane(crtc, fb, x, y);
2168 void intel_display_handle_reset(struct drm_device *dev)
2170 struct drm_i915_private *dev_priv = dev->dev_private;
2171 struct drm_crtc *crtc;
2174 * Flips in the rings have been nuked by the reset,
2175 * so complete all pending flips so that user space
2176 * will get its events and not get stuck.
2178 * Also update the base address of all primary
2179 * planes to the the last fb to make sure we're
2180 * showing the correct fb after a reset.
2182 * Need to make two loops over the crtcs so that we
2183 * don't try to grab a crtc mutex before the
2184 * pending_flip_queue really got woken up.
2187 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2189 enum plane plane = intel_crtc->plane;
2191 intel_prepare_page_flip(dev, plane);
2192 intel_finish_page_flip_plane(dev, plane);
2195 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2198 mutex_lock(&crtc->mutex);
2199 if (intel_crtc->active)
2200 dev_priv->display.update_plane(crtc, crtc->fb,
2202 mutex_unlock(&crtc->mutex);
2207 intel_finish_fb(struct drm_framebuffer *old_fb)
2209 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2210 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2211 bool was_interruptible = dev_priv->mm.interruptible;
2214 /* Big Hammer, we also need to ensure that any pending
2215 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2216 * current scanout is retired before unpinning the old
2219 * This should only fail upon a hung GPU, in which case we
2220 * can safely continue.
2222 dev_priv->mm.interruptible = false;
2223 ret = i915_gem_object_finish_gpu(obj);
2224 dev_priv->mm.interruptible = was_interruptible;
2229 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2231 struct drm_device *dev = crtc->dev;
2232 struct drm_i915_master_private *master_priv;
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2235 if (!dev->primary->master)
2238 master_priv = dev->primary->master->driver_priv;
2239 if (!master_priv->sarea_priv)
2242 switch (intel_crtc->pipe) {
2244 master_priv->sarea_priv->pipeA_x = x;
2245 master_priv->sarea_priv->pipeA_y = y;
2248 master_priv->sarea_priv->pipeB_x = x;
2249 master_priv->sarea_priv->pipeB_y = y;
2257 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2258 struct drm_framebuffer *fb)
2260 struct drm_device *dev = crtc->dev;
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2263 struct drm_framebuffer *old_fb;
2268 DRM_ERROR("No FB bound\n");
2272 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2273 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2274 plane_name(intel_crtc->plane),
2275 INTEL_INFO(dev)->num_pipes);
2279 mutex_lock(&dev->struct_mutex);
2280 ret = intel_pin_and_fence_fb_obj(dev,
2281 to_intel_framebuffer(fb)->obj,
2284 mutex_unlock(&dev->struct_mutex);
2285 DRM_ERROR("pin & fence failed\n");
2289 /* Update pipe size and adjust fitter if needed */
2290 if (i915_fastboot) {
2291 I915_WRITE(PIPESRC(intel_crtc->pipe),
2292 ((crtc->mode.hdisplay - 1) << 16) |
2293 (crtc->mode.vdisplay - 1));
2294 if (!intel_crtc->config.pch_pfit.size &&
2295 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2296 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2297 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2298 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2299 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2303 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2305 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2306 mutex_unlock(&dev->struct_mutex);
2307 DRM_ERROR("failed to update base address\n");
2317 if (intel_crtc->active && old_fb != fb)
2318 intel_wait_for_vblank(dev, intel_crtc->pipe);
2319 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2322 intel_update_fbc(dev);
2323 intel_edp_psr_update(dev);
2324 mutex_unlock(&dev->struct_mutex);
2326 intel_crtc_update_sarea_pos(crtc, x, y);
2331 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
2342 if (IS_IVYBRIDGE(dev)) {
2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2349 I915_WRITE(reg, temp);
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2362 /* wait one idle pattern time */
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
2372 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2374 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2377 static void ivb_modeset_global_resources(struct drm_device *dev)
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *pipe_B_crtc =
2381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382 struct intel_crtc *pipe_C_crtc =
2383 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2387 * When everything is off disable fdi C so that we could enable fdi B
2388 * with all lanes. Note that we don't care about enabled pipes without
2389 * an enabled pch encoder.
2391 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392 !pipe_has_enabled_pch(pipe_C_crtc)) {
2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2396 temp = I915_READ(SOUTH_CHICKEN1);
2397 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399 I915_WRITE(SOUTH_CHICKEN1, temp);
2403 /* The FDI link training functions for ILK/Ibexpeak. */
2404 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
2410 int plane = intel_crtc->plane;
2411 u32 reg, temp, tries;
2413 /* FDI needs bits from pipe & plane first */
2414 assert_pipe_enabled(dev_priv, pipe);
2415 assert_plane_enabled(dev_priv, plane);
2417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2419 reg = FDI_RX_IMR(pipe);
2420 temp = I915_READ(reg);
2421 temp &= ~FDI_RX_SYMBOL_LOCK;
2422 temp &= ~FDI_RX_BIT_LOCK;
2423 I915_WRITE(reg, temp);
2427 /* enable CPU FDI TX and PCH FDI RX */
2428 reg = FDI_TX_CTL(pipe);
2429 temp = I915_READ(reg);
2430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
2434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
2440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2445 /* Ironlake workaround, enable clock pointer after FDI enable*/
2446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448 FDI_RX_PHASE_SYNC_POINTER_EN);
2450 reg = FDI_RX_IIR(pipe);
2451 for (tries = 0; tries < 5; tries++) {
2452 temp = I915_READ(reg);
2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2455 if ((temp & FDI_RX_BIT_LOCK)) {
2456 DRM_DEBUG_KMS("FDI train 1 done.\n");
2457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2462 DRM_ERROR("FDI train 1 fail!\n");
2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
2469 I915_WRITE(reg, temp);
2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2;
2475 I915_WRITE(reg, temp);
2480 reg = FDI_RX_IIR(pipe);
2481 for (tries = 0; tries < 5; tries++) {
2482 temp = I915_READ(reg);
2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2485 if (temp & FDI_RX_SYMBOL_LOCK) {
2486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2487 DRM_DEBUG_KMS("FDI train 2 done.\n");
2492 DRM_ERROR("FDI train 2 fail!\n");
2494 DRM_DEBUG_KMS("FDI train done\n");
2498 static const int snb_b_fdi_train_param[] = {
2499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2505 /* The FDI link training functions for SNB/Cougarpoint. */
2506 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2508 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 int pipe = intel_crtc->pipe;
2512 u32 reg, temp, i, retry;
2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
2520 I915_WRITE(reg, temp);
2525 /* enable CPU FDI TX and PCH FDI RX */
2526 reg = FDI_TX_CTL(pipe);
2527 temp = I915_READ(reg);
2528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_1;
2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2537 I915_WRITE(FDI_RX_MISC(pipe),
2538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2554 for (i = 0; i < 4; i++) {
2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
2557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558 temp |= snb_b_fdi_train_param[i];
2559 I915_WRITE(reg, temp);
2564 for (retry = 0; retry < 5; retry++) {
2565 reg = FDI_RX_IIR(pipe);
2566 temp = I915_READ(reg);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568 if (temp & FDI_RX_BIT_LOCK) {
2569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570 DRM_DEBUG_KMS("FDI train 1 done.\n");
2579 DRM_ERROR("FDI train 1 fail!\n");
2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_2;
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2591 I915_WRITE(reg, temp);
2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_2;
2602 I915_WRITE(reg, temp);
2607 for (i = 0; i < 4; i++) {
2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
2612 I915_WRITE(reg, temp);
2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_SYMBOL_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623 DRM_DEBUG_KMS("FDI train 2 done.\n");
2632 DRM_ERROR("FDI train 2 fail!\n");
2634 DRM_DEBUG_KMS("FDI train done.\n");
2637 /* Manual link training for Ivy Bridge A0 parts */
2638 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 int pipe = intel_crtc->pipe;
2644 u32 reg, temp, i, j;
2646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2648 reg = FDI_RX_IMR(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_RX_SYMBOL_LOCK;
2651 temp &= ~FDI_RX_BIT_LOCK;
2652 I915_WRITE(reg, temp);
2657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658 I915_READ(FDI_RX_IIR(pipe)));
2660 /* Try each vswing and preemphasis setting twice before moving on */
2661 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2662 /* disable first in case we need to retry */
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666 temp &= ~FDI_TX_ENABLE;
2667 I915_WRITE(reg, temp);
2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp &= ~FDI_RX_ENABLE;
2674 I915_WRITE(reg, temp);
2676 /* enable CPU FDI TX and PCH FDI RX */
2677 reg = FDI_TX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2681 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2683 temp |= snb_b_fdi_train_param[j/2];
2684 temp |= FDI_COMPOSITE_SYNC;
2685 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2687 I915_WRITE(FDI_RX_MISC(pipe),
2688 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2690 reg = FDI_RX_CTL(pipe);
2691 temp = I915_READ(reg);
2692 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2693 temp |= FDI_COMPOSITE_SYNC;
2694 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2697 udelay(1); /* should be 0.5us */
2699 for (i = 0; i < 4; i++) {
2700 reg = FDI_RX_IIR(pipe);
2701 temp = I915_READ(reg);
2702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2704 if (temp & FDI_RX_BIT_LOCK ||
2705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2711 udelay(1); /* should be 0.5us */
2714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2722 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2723 I915_WRITE(reg, temp);
2725 reg = FDI_RX_CTL(pipe);
2726 temp = I915_READ(reg);
2727 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2728 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2729 I915_WRITE(reg, temp);
2732 udelay(2); /* should be 1.5us */
2734 for (i = 0; i < 4; i++) {
2735 reg = FDI_RX_IIR(pipe);
2736 temp = I915_READ(reg);
2737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2739 if (temp & FDI_RX_SYMBOL_LOCK ||
2740 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2741 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2746 udelay(2); /* should be 1.5us */
2749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2753 DRM_DEBUG_KMS("FDI train done.\n");
2756 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2758 struct drm_device *dev = intel_crtc->base.dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 int pipe = intel_crtc->pipe;
2764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2768 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2769 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2770 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2775 /* Switch from Rawclk to PCDclk */
2776 temp = I915_READ(reg);
2777 I915_WRITE(reg, temp | FDI_PCDCLK);
2782 /* Enable CPU FDI TX PLL, always on for Ironlake */
2783 reg = FDI_TX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2786 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2793 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2795 struct drm_device *dev = intel_crtc->base.dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 int pipe = intel_crtc->pipe;
2800 /* Switch from PCDclk to Rawclk */
2801 reg = FDI_RX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2805 /* Disable CPU FDI TX PLL */
2806 reg = FDI_TX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2813 reg = FDI_RX_CTL(pipe);
2814 temp = I915_READ(reg);
2815 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2817 /* Wait for the clocks to turn off. */
2822 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2824 struct drm_device *dev = crtc->dev;
2825 struct drm_i915_private *dev_priv = dev->dev_private;
2826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2827 int pipe = intel_crtc->pipe;
2830 /* disable CPU FDI tx and PCH FDI rx */
2831 reg = FDI_TX_CTL(pipe);
2832 temp = I915_READ(reg);
2833 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 temp &= ~(0x7 << 16);
2839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2840 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2845 /* Ironlake workaround, disable clock pointer after downing FDI */
2846 if (HAS_PCH_IBX(dev)) {
2847 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2850 /* still set train pattern 1 */
2851 reg = FDI_TX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 temp &= ~FDI_LINK_TRAIN_NONE;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1;
2855 I915_WRITE(reg, temp);
2857 reg = FDI_RX_CTL(pipe);
2858 temp = I915_READ(reg);
2859 if (HAS_PCH_CPT(dev)) {
2860 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2861 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2863 temp &= ~FDI_LINK_TRAIN_NONE;
2864 temp |= FDI_LINK_TRAIN_PATTERN_1;
2866 /* BPC in FDI rx is consistent with that in PIPECONF */
2867 temp &= ~(0x07 << 16);
2868 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2869 I915_WRITE(reg, temp);
2875 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880 unsigned long flags;
2883 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2884 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2887 spin_lock_irqsave(&dev->event_lock, flags);
2888 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2889 spin_unlock_irqrestore(&dev->event_lock, flags);
2894 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2896 struct drm_device *dev = crtc->dev;
2897 struct drm_i915_private *dev_priv = dev->dev_private;
2899 if (crtc->fb == NULL)
2902 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2904 wait_event(dev_priv->pending_flip_queue,
2905 !intel_crtc_has_pending_flip(crtc));
2907 mutex_lock(&dev->struct_mutex);
2908 intel_finish_fb(crtc->fb);
2909 mutex_unlock(&dev->struct_mutex);
2912 /* Program iCLKIP clock to the desired frequency */
2913 static void lpt_program_iclkip(struct drm_crtc *crtc)
2915 struct drm_device *dev = crtc->dev;
2916 struct drm_i915_private *dev_priv = dev->dev_private;
2917 int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
2918 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2921 mutex_lock(&dev_priv->dpio_lock);
2923 /* It is necessary to ungate the pixclk gate prior to programming
2924 * the divisors, and gate it back when it is done.
2926 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2928 /* Disable SSCCTL */
2929 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2930 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2934 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2935 if (clock == 20000) {
2940 /* The iCLK virtual clock root frequency is in MHz,
2941 * but the adjusted_mode->clock in in KHz. To get the divisors,
2942 * it is necessary to divide one by another, so we
2943 * convert the virtual clock precision to KHz here for higher
2946 u32 iclk_virtual_root_freq = 172800 * 1000;
2947 u32 iclk_pi_range = 64;
2948 u32 desired_divisor, msb_divisor_value, pi_value;
2950 desired_divisor = (iclk_virtual_root_freq / clock);
2951 msb_divisor_value = desired_divisor / iclk_pi_range;
2952 pi_value = desired_divisor % iclk_pi_range;
2955 divsel = msb_divisor_value - 2;
2956 phaseinc = pi_value;
2959 /* This should not happen with any sane values */
2960 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2961 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2962 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2963 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2965 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2972 /* Program SSCDIVINTPHASE6 */
2973 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2974 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2975 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2976 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2977 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2978 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2979 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2980 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2982 /* Program SSCAUXDIV */
2983 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2984 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2985 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2986 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2988 /* Enable modulator and associated divider */
2989 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2990 temp &= ~SBI_SSCCTL_DISABLE;
2991 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2993 /* Wait for initialization time */
2996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2998 mutex_unlock(&dev_priv->dpio_lock);
3001 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3002 enum pipe pch_transcoder)
3004 struct drm_device *dev = crtc->base.dev;
3005 struct drm_i915_private *dev_priv = dev->dev_private;
3006 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3008 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3009 I915_READ(HTOTAL(cpu_transcoder)));
3010 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3011 I915_READ(HBLANK(cpu_transcoder)));
3012 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3013 I915_READ(HSYNC(cpu_transcoder)));
3015 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3016 I915_READ(VTOTAL(cpu_transcoder)));
3017 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3018 I915_READ(VBLANK(cpu_transcoder)));
3019 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3020 I915_READ(VSYNC(cpu_transcoder)));
3021 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3022 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3026 * Enable PCH resources required for PCH ports:
3028 * - FDI training & RX/TX
3029 * - update transcoder timings
3030 * - DP transcoding bits
3033 static void ironlake_pch_enable(struct drm_crtc *crtc)
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038 int pipe = intel_crtc->pipe;
3041 assert_pch_transcoder_disabled(dev_priv, pipe);
3043 /* Write the TU size bits before fdi link training, so that error
3044 * detection works. */
3045 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3046 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3048 /* For PCH output, training FDI link */
3049 dev_priv->display.fdi_link_train(crtc);
3051 /* We need to program the right clock selection before writing the pixel
3052 * mutliplier into the DPLL. */
3053 if (HAS_PCH_CPT(dev)) {
3056 temp = I915_READ(PCH_DPLL_SEL);
3057 temp |= TRANS_DPLL_ENABLE(pipe);
3058 sel = TRANS_DPLLB_SEL(pipe);
3059 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3063 I915_WRITE(PCH_DPLL_SEL, temp);
3066 /* XXX: pch pll's can be enabled any time before we enable the PCH
3067 * transcoder, and we actually should do this to not upset any PCH
3068 * transcoder that already use the clock when we share it.
3070 * Note that enable_shared_dpll tries to do the right thing, but
3071 * get_shared_dpll unconditionally resets the pll - we need that to have
3072 * the right LVDS enable sequence. */
3073 ironlake_enable_shared_dpll(intel_crtc);
3075 /* set transcoder timing, panel must allow it */
3076 assert_panel_unlocked(dev_priv, pipe);
3077 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3079 intel_fdi_normal_train(crtc);
3081 /* For PCH DP, enable TRANS_DP_CTL */
3082 if (HAS_PCH_CPT(dev) &&
3083 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3084 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3085 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3086 reg = TRANS_DP_CTL(pipe);
3087 temp = I915_READ(reg);
3088 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3089 TRANS_DP_SYNC_MASK |
3091 temp |= (TRANS_DP_OUTPUT_ENABLE |
3092 TRANS_DP_ENH_FRAMING);
3093 temp |= bpc << 9; /* same format but at 11:9 */
3095 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3096 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3097 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3098 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3100 switch (intel_trans_dp_port_sel(crtc)) {
3102 temp |= TRANS_DP_PORT_SEL_B;
3105 temp |= TRANS_DP_PORT_SEL_C;
3108 temp |= TRANS_DP_PORT_SEL_D;
3114 I915_WRITE(reg, temp);
3117 ironlake_enable_pch_transcoder(dev_priv, pipe);
3120 static void lpt_pch_enable(struct drm_crtc *crtc)
3122 struct drm_device *dev = crtc->dev;
3123 struct drm_i915_private *dev_priv = dev->dev_private;
3124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3125 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3127 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3129 lpt_program_iclkip(crtc);
3131 /* Set transcoder timing. */
3132 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3134 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3137 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3139 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3144 if (pll->refcount == 0) {
3145 WARN(1, "bad %s refcount\n", pll->name);
3149 if (--pll->refcount == 0) {
3151 WARN_ON(pll->active);
3154 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3157 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3160 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3161 enum intel_dpll_id i;
3164 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3165 crtc->base.base.id, pll->name);
3166 intel_put_shared_dpll(crtc);
3169 if (HAS_PCH_IBX(dev_priv->dev)) {
3170 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3171 i = (enum intel_dpll_id) crtc->pipe;
3172 pll = &dev_priv->shared_dplls[i];
3174 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3175 crtc->base.base.id, pll->name);
3180 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3181 pll = &dev_priv->shared_dplls[i];
3183 /* Only want to check enabled timings first */
3184 if (pll->refcount == 0)
3187 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3188 sizeof(pll->hw_state)) == 0) {
3189 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3191 pll->name, pll->refcount, pll->active);
3197 /* Ok no matching timings, maybe there's a free one? */
3198 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3199 pll = &dev_priv->shared_dplls[i];
3200 if (pll->refcount == 0) {
3201 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3202 crtc->base.base.id, pll->name);
3210 crtc->config.shared_dpll = i;
3211 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3212 pipe_name(crtc->pipe));
3214 if (pll->active == 0) {
3215 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3216 sizeof(pll->hw_state));
3218 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3220 assert_shared_dpll_disabled(dev_priv, pll);
3222 pll->mode_set(dev_priv, pll);
3229 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3231 struct drm_i915_private *dev_priv = dev->dev_private;
3232 int dslreg = PIPEDSL(pipe);
3235 temp = I915_READ(dslreg);
3237 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3238 if (wait_for(I915_READ(dslreg) != temp, 5))
3239 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3243 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3245 struct drm_device *dev = crtc->base.dev;
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 int pipe = crtc->pipe;
3249 if (crtc->config.pch_pfit.size) {
3250 /* Force use of hard-coded filter coefficients
3251 * as some pre-programmed values are broken,
3254 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3255 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3256 PF_PIPE_SEL_IVB(pipe));
3258 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3259 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3260 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3264 static void intel_enable_planes(struct drm_crtc *crtc)
3266 struct drm_device *dev = crtc->dev;
3267 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3268 struct intel_plane *intel_plane;
3270 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3271 if (intel_plane->pipe == pipe)
3272 intel_plane_restore(&intel_plane->base);
3275 static void intel_disable_planes(struct drm_crtc *crtc)
3277 struct drm_device *dev = crtc->dev;
3278 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3279 struct intel_plane *intel_plane;
3281 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3282 if (intel_plane->pipe == pipe)
3283 intel_plane_disable(&intel_plane->base);
3286 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3288 struct drm_device *dev = crtc->dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3291 struct intel_encoder *encoder;
3292 int pipe = intel_crtc->pipe;
3293 int plane = intel_crtc->plane;
3295 WARN_ON(!crtc->enabled);
3297 if (intel_crtc->active)
3300 intel_crtc->active = true;
3302 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3303 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3305 for_each_encoder_on_crtc(dev, crtc, encoder)
3306 if (encoder->pre_enable)
3307 encoder->pre_enable(encoder);
3309 if (intel_crtc->config.has_pch_encoder) {
3310 /* Note: FDI PLL enabling _must_ be done before we enable the
3311 * cpu pipes, hence this is separate from all the other fdi/pch
3313 ironlake_fdi_pll_enable(intel_crtc);
3315 assert_fdi_tx_disabled(dev_priv, pipe);
3316 assert_fdi_rx_disabled(dev_priv, pipe);
3319 ironlake_pfit_enable(intel_crtc);
3322 * On ILK+ LUT must be loaded before the pipe is running but with
3325 intel_crtc_load_lut(crtc);
3327 intel_update_watermarks(crtc);
3328 intel_enable_pipe(dev_priv, pipe,
3329 intel_crtc->config.has_pch_encoder, false);
3330 intel_enable_plane(dev_priv, plane, pipe);
3331 intel_enable_planes(crtc);
3332 intel_crtc_update_cursor(crtc, true);
3334 if (intel_crtc->config.has_pch_encoder)
3335 ironlake_pch_enable(crtc);
3337 mutex_lock(&dev->struct_mutex);
3338 intel_update_fbc(dev);
3339 mutex_unlock(&dev->struct_mutex);
3341 for_each_encoder_on_crtc(dev, crtc, encoder)
3342 encoder->enable(encoder);
3344 if (HAS_PCH_CPT(dev))
3345 cpt_verify_modeset(dev, intel_crtc->pipe);
3348 * There seems to be a race in PCH platform hw (at least on some
3349 * outputs) where an enabled pipe still completes any pageflip right
3350 * away (as if the pipe is off) instead of waiting for vblank. As soon
3351 * as the first vblank happend, everything works as expected. Hence just
3352 * wait for one vblank before returning to avoid strange things
3355 intel_wait_for_vblank(dev, intel_crtc->pipe);
3358 /* IPS only exists on ULT machines and is tied to pipe A. */
3359 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3361 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3364 static void hsw_enable_ips(struct intel_crtc *crtc)
3366 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3368 if (!crtc->config.ips_enabled)
3371 /* We can only enable IPS after we enable a plane and wait for a vblank.
3372 * We guarantee that the plane is enabled by calling intel_enable_ips
3373 * only after intel_enable_plane. And intel_enable_plane already waits
3374 * for a vblank, so all we need to do here is to enable the IPS bit. */
3375 assert_plane_enabled(dev_priv, crtc->plane);
3376 I915_WRITE(IPS_CTL, IPS_ENABLE);
3379 static void hsw_disable_ips(struct intel_crtc *crtc)
3381 struct drm_device *dev = crtc->base.dev;
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3384 if (!crtc->config.ips_enabled)
3387 assert_plane_enabled(dev_priv, crtc->plane);
3388 I915_WRITE(IPS_CTL, 0);
3389 POSTING_READ(IPS_CTL);
3391 /* We need to wait for a vblank before we can disable the plane. */
3392 intel_wait_for_vblank(dev, crtc->pipe);
3395 static void haswell_crtc_enable(struct drm_crtc *crtc)
3397 struct drm_device *dev = crtc->dev;
3398 struct drm_i915_private *dev_priv = dev->dev_private;
3399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3400 struct intel_encoder *encoder;
3401 int pipe = intel_crtc->pipe;
3402 int plane = intel_crtc->plane;
3404 WARN_ON(!crtc->enabled);
3406 if (intel_crtc->active)
3409 intel_crtc->active = true;
3411 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3412 if (intel_crtc->config.has_pch_encoder)
3413 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3415 if (intel_crtc->config.has_pch_encoder)
3416 dev_priv->display.fdi_link_train(crtc);
3418 for_each_encoder_on_crtc(dev, crtc, encoder)
3419 if (encoder->pre_enable)
3420 encoder->pre_enable(encoder);
3422 intel_ddi_enable_pipe_clock(intel_crtc);
3424 ironlake_pfit_enable(intel_crtc);
3427 * On ILK+ LUT must be loaded before the pipe is running but with
3430 intel_crtc_load_lut(crtc);
3432 intel_ddi_set_pipe_settings(crtc);
3433 intel_ddi_enable_transcoder_func(crtc);
3435 intel_update_watermarks(crtc);
3436 intel_enable_pipe(dev_priv, pipe,
3437 intel_crtc->config.has_pch_encoder, false);
3438 intel_enable_plane(dev_priv, plane, pipe);
3439 intel_enable_planes(crtc);
3440 intel_crtc_update_cursor(crtc, true);
3442 hsw_enable_ips(intel_crtc);
3444 if (intel_crtc->config.has_pch_encoder)
3445 lpt_pch_enable(crtc);
3447 mutex_lock(&dev->struct_mutex);
3448 intel_update_fbc(dev);
3449 mutex_unlock(&dev->struct_mutex);
3451 for_each_encoder_on_crtc(dev, crtc, encoder) {
3452 encoder->enable(encoder);
3453 intel_opregion_notify_encoder(encoder, true);
3457 * There seems to be a race in PCH platform hw (at least on some
3458 * outputs) where an enabled pipe still completes any pageflip right
3459 * away (as if the pipe is off) instead of waiting for vblank. As soon
3460 * as the first vblank happend, everything works as expected. Hence just
3461 * wait for one vblank before returning to avoid strange things
3464 intel_wait_for_vblank(dev, intel_crtc->pipe);
3467 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3469 struct drm_device *dev = crtc->base.dev;
3470 struct drm_i915_private *dev_priv = dev->dev_private;
3471 int pipe = crtc->pipe;
3473 /* To avoid upsetting the power well on haswell only disable the pfit if
3474 * it's in use. The hw state code will make sure we get this right. */
3475 if (crtc->config.pch_pfit.size) {
3476 I915_WRITE(PF_CTL(pipe), 0);
3477 I915_WRITE(PF_WIN_POS(pipe), 0);
3478 I915_WRITE(PF_WIN_SZ(pipe), 0);
3482 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3484 struct drm_device *dev = crtc->dev;
3485 struct drm_i915_private *dev_priv = dev->dev_private;
3486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3487 struct intel_encoder *encoder;
3488 int pipe = intel_crtc->pipe;
3489 int plane = intel_crtc->plane;
3493 if (!intel_crtc->active)
3496 for_each_encoder_on_crtc(dev, crtc, encoder)
3497 encoder->disable(encoder);
3499 intel_crtc_wait_for_pending_flips(crtc);
3500 drm_vblank_off(dev, pipe);
3502 if (dev_priv->fbc.plane == plane)
3503 intel_disable_fbc(dev);
3505 intel_crtc_update_cursor(crtc, false);
3506 intel_disable_planes(crtc);
3507 intel_disable_plane(dev_priv, plane, pipe);
3509 if (intel_crtc->config.has_pch_encoder)
3510 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3512 intel_disable_pipe(dev_priv, pipe);
3514 ironlake_pfit_disable(intel_crtc);
3516 for_each_encoder_on_crtc(dev, crtc, encoder)
3517 if (encoder->post_disable)
3518 encoder->post_disable(encoder);
3520 if (intel_crtc->config.has_pch_encoder) {
3521 ironlake_fdi_disable(crtc);
3523 ironlake_disable_pch_transcoder(dev_priv, pipe);
3524 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3526 if (HAS_PCH_CPT(dev)) {
3527 /* disable TRANS_DP_CTL */
3528 reg = TRANS_DP_CTL(pipe);
3529 temp = I915_READ(reg);
3530 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3531 TRANS_DP_PORT_SEL_MASK);
3532 temp |= TRANS_DP_PORT_SEL_NONE;
3533 I915_WRITE(reg, temp);
3535 /* disable DPLL_SEL */
3536 temp = I915_READ(PCH_DPLL_SEL);
3537 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3538 I915_WRITE(PCH_DPLL_SEL, temp);
3541 /* disable PCH DPLL */
3542 intel_disable_shared_dpll(intel_crtc);
3544 ironlake_fdi_pll_disable(intel_crtc);
3547 intel_crtc->active = false;
3548 intel_update_watermarks(crtc);
3550 mutex_lock(&dev->struct_mutex);
3551 intel_update_fbc(dev);
3552 mutex_unlock(&dev->struct_mutex);
3555 static void haswell_crtc_disable(struct drm_crtc *crtc)
3557 struct drm_device *dev = crtc->dev;
3558 struct drm_i915_private *dev_priv = dev->dev_private;
3559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3560 struct intel_encoder *encoder;
3561 int pipe = intel_crtc->pipe;
3562 int plane = intel_crtc->plane;
3563 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3565 if (!intel_crtc->active)
3568 for_each_encoder_on_crtc(dev, crtc, encoder) {
3569 intel_opregion_notify_encoder(encoder, false);
3570 encoder->disable(encoder);
3573 intel_crtc_wait_for_pending_flips(crtc);
3574 drm_vblank_off(dev, pipe);
3576 /* FBC must be disabled before disabling the plane on HSW. */
3577 if (dev_priv->fbc.plane == plane)
3578 intel_disable_fbc(dev);
3580 hsw_disable_ips(intel_crtc);
3582 intel_crtc_update_cursor(crtc, false);
3583 intel_disable_planes(crtc);
3584 intel_disable_plane(dev_priv, plane, pipe);
3586 if (intel_crtc->config.has_pch_encoder)
3587 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3588 intel_disable_pipe(dev_priv, pipe);
3590 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3592 ironlake_pfit_disable(intel_crtc);
3594 intel_ddi_disable_pipe_clock(intel_crtc);
3596 for_each_encoder_on_crtc(dev, crtc, encoder)
3597 if (encoder->post_disable)
3598 encoder->post_disable(encoder);
3600 if (intel_crtc->config.has_pch_encoder) {
3601 lpt_disable_pch_transcoder(dev_priv);
3602 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3603 intel_ddi_fdi_disable(crtc);
3606 intel_crtc->active = false;
3607 intel_update_watermarks(crtc);
3609 mutex_lock(&dev->struct_mutex);
3610 intel_update_fbc(dev);
3611 mutex_unlock(&dev->struct_mutex);
3614 static void ironlake_crtc_off(struct drm_crtc *crtc)
3616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617 intel_put_shared_dpll(intel_crtc);
3620 static void haswell_crtc_off(struct drm_crtc *crtc)
3622 intel_ddi_put_crtc_pll(crtc);
3625 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3627 if (!enable && intel_crtc->overlay) {
3628 struct drm_device *dev = intel_crtc->base.dev;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3631 mutex_lock(&dev->struct_mutex);
3632 dev_priv->mm.interruptible = false;
3633 (void) intel_overlay_switch_off(intel_crtc->overlay);
3634 dev_priv->mm.interruptible = true;
3635 mutex_unlock(&dev->struct_mutex);
3638 /* Let userspace switch the overlay on again. In most cases userspace
3639 * has to recompute where to put it anyway.
3644 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3645 * cursor plane briefly if not already running after enabling the display
3647 * This workaround avoids occasional blank screens when self refresh is
3651 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3653 u32 cntl = I915_READ(CURCNTR(pipe));
3655 if ((cntl & CURSOR_MODE) == 0) {
3656 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3658 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3659 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3660 intel_wait_for_vblank(dev_priv->dev, pipe);
3661 I915_WRITE(CURCNTR(pipe), cntl);
3662 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3663 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3667 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3669 struct drm_device *dev = crtc->base.dev;
3670 struct drm_i915_private *dev_priv = dev->dev_private;
3671 struct intel_crtc_config *pipe_config = &crtc->config;
3673 if (!crtc->config.gmch_pfit.control)
3677 * The panel fitter should only be adjusted whilst the pipe is disabled,
3678 * according to register description and PRM.
3680 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3681 assert_pipe_disabled(dev_priv, crtc->pipe);
3683 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3684 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3686 /* Border color in case we don't scale up to the full screen. Black by
3687 * default, change to something else for debugging. */
3688 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3691 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3693 struct drm_device *dev = crtc->dev;
3694 struct drm_i915_private *dev_priv = dev->dev_private;
3695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3696 struct intel_encoder *encoder;
3697 int pipe = intel_crtc->pipe;
3698 int plane = intel_crtc->plane;
3701 WARN_ON(!crtc->enabled);
3703 if (intel_crtc->active)
3706 intel_crtc->active = true;
3708 for_each_encoder_on_crtc(dev, crtc, encoder)
3709 if (encoder->pre_pll_enable)
3710 encoder->pre_pll_enable(encoder);
3712 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3715 vlv_enable_pll(intel_crtc);
3717 for_each_encoder_on_crtc(dev, crtc, encoder)
3718 if (encoder->pre_enable)
3719 encoder->pre_enable(encoder);
3721 i9xx_pfit_enable(intel_crtc);
3723 intel_crtc_load_lut(crtc);
3725 intel_update_watermarks(crtc);
3726 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3727 intel_enable_plane(dev_priv, plane, pipe);
3728 intel_enable_planes(crtc);
3729 intel_crtc_update_cursor(crtc, true);
3731 intel_update_fbc(dev);
3733 for_each_encoder_on_crtc(dev, crtc, encoder)
3734 encoder->enable(encoder);
3737 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3739 struct drm_device *dev = crtc->dev;
3740 struct drm_i915_private *dev_priv = dev->dev_private;
3741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3742 struct intel_encoder *encoder;
3743 int pipe = intel_crtc->pipe;
3744 int plane = intel_crtc->plane;
3746 WARN_ON(!crtc->enabled);
3748 if (intel_crtc->active)
3751 intel_crtc->active = true;
3753 for_each_encoder_on_crtc(dev, crtc, encoder)
3754 if (encoder->pre_enable)
3755 encoder->pre_enable(encoder);
3757 i9xx_enable_pll(intel_crtc);
3759 i9xx_pfit_enable(intel_crtc);
3761 intel_crtc_load_lut(crtc);
3763 intel_update_watermarks(crtc);
3764 intel_enable_pipe(dev_priv, pipe, false, false);
3765 intel_enable_plane(dev_priv, plane, pipe);
3766 intel_enable_planes(crtc);
3767 /* The fixup needs to happen before cursor is enabled */
3769 g4x_fixup_plane(dev_priv, pipe);
3770 intel_crtc_update_cursor(crtc, true);
3772 /* Give the overlay scaler a chance to enable if it's on this pipe */
3773 intel_crtc_dpms_overlay(intel_crtc, true);
3775 intel_update_fbc(dev);
3777 for_each_encoder_on_crtc(dev, crtc, encoder)
3778 encoder->enable(encoder);
3781 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3783 struct drm_device *dev = crtc->base.dev;
3784 struct drm_i915_private *dev_priv = dev->dev_private;
3786 if (!crtc->config.gmch_pfit.control)
3789 assert_pipe_disabled(dev_priv, crtc->pipe);
3791 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3792 I915_READ(PFIT_CONTROL));
3793 I915_WRITE(PFIT_CONTROL, 0);
3796 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3798 struct drm_device *dev = crtc->dev;
3799 struct drm_i915_private *dev_priv = dev->dev_private;
3800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3801 struct intel_encoder *encoder;
3802 int pipe = intel_crtc->pipe;
3803 int plane = intel_crtc->plane;
3805 if (!intel_crtc->active)
3808 for_each_encoder_on_crtc(dev, crtc, encoder)
3809 encoder->disable(encoder);
3811 /* Give the overlay scaler a chance to disable if it's on this pipe */
3812 intel_crtc_wait_for_pending_flips(crtc);
3813 drm_vblank_off(dev, pipe);
3815 if (dev_priv->fbc.plane == plane)
3816 intel_disable_fbc(dev);
3818 intel_crtc_dpms_overlay(intel_crtc, false);
3819 intel_crtc_update_cursor(crtc, false);
3820 intel_disable_planes(crtc);
3821 intel_disable_plane(dev_priv, plane, pipe);
3823 intel_disable_pipe(dev_priv, pipe);
3825 i9xx_pfit_disable(intel_crtc);
3827 for_each_encoder_on_crtc(dev, crtc, encoder)
3828 if (encoder->post_disable)
3829 encoder->post_disable(encoder);
3831 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3832 i9xx_disable_pll(dev_priv, pipe);
3834 intel_crtc->active = false;
3835 intel_update_watermarks(crtc);
3837 intel_update_fbc(dev);
3840 static void i9xx_crtc_off(struct drm_crtc *crtc)
3844 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3847 struct drm_device *dev = crtc->dev;
3848 struct drm_i915_master_private *master_priv;
3849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3850 int pipe = intel_crtc->pipe;
3852 if (!dev->primary->master)
3855 master_priv = dev->primary->master->driver_priv;
3856 if (!master_priv->sarea_priv)
3861 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3862 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3865 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3866 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3869 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3875 * Sets the power management mode of the pipe and plane.
3877 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3879 struct drm_device *dev = crtc->dev;
3880 struct drm_i915_private *dev_priv = dev->dev_private;
3881 struct intel_encoder *intel_encoder;
3882 bool enable = false;
3884 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3885 enable |= intel_encoder->connectors_active;
3888 dev_priv->display.crtc_enable(crtc);
3890 dev_priv->display.crtc_disable(crtc);
3892 intel_crtc_update_sarea(crtc, enable);
3895 static void intel_crtc_disable(struct drm_crtc *crtc)
3897 struct drm_device *dev = crtc->dev;
3898 struct drm_connector *connector;
3899 struct drm_i915_private *dev_priv = dev->dev_private;
3900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3902 /* crtc should still be enabled when we disable it. */
3903 WARN_ON(!crtc->enabled);
3905 dev_priv->display.crtc_disable(crtc);
3906 intel_crtc->eld_vld = false;
3907 intel_crtc_update_sarea(crtc, false);
3908 dev_priv->display.off(crtc);
3910 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3911 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
3912 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3915 mutex_lock(&dev->struct_mutex);
3916 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3917 mutex_unlock(&dev->struct_mutex);
3921 /* Update computed state. */
3922 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3923 if (!connector->encoder || !connector->encoder->crtc)
3926 if (connector->encoder->crtc != crtc)
3929 connector->dpms = DRM_MODE_DPMS_OFF;
3930 to_intel_encoder(connector->encoder)->connectors_active = false;
3934 void intel_encoder_destroy(struct drm_encoder *encoder)
3936 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3938 drm_encoder_cleanup(encoder);
3939 kfree(intel_encoder);
3942 /* Simple dpms helper for encoders with just one connector, no cloning and only
3943 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3944 * state of the entire output pipe. */
3945 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3947 if (mode == DRM_MODE_DPMS_ON) {
3948 encoder->connectors_active = true;
3950 intel_crtc_update_dpms(encoder->base.crtc);
3952 encoder->connectors_active = false;
3954 intel_crtc_update_dpms(encoder->base.crtc);
3958 /* Cross check the actual hw state with our own modeset state tracking (and it's
3959 * internal consistency). */
3960 static void intel_connector_check_state(struct intel_connector *connector)
3962 if (connector->get_hw_state(connector)) {
3963 struct intel_encoder *encoder = connector->encoder;
3964 struct drm_crtc *crtc;
3965 bool encoder_enabled;
3968 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3969 connector->base.base.id,
3970 drm_get_connector_name(&connector->base));
3972 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3973 "wrong connector dpms state\n");
3974 WARN(connector->base.encoder != &encoder->base,
3975 "active connector not linked to encoder\n");
3976 WARN(!encoder->connectors_active,
3977 "encoder->connectors_active not set\n");
3979 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3980 WARN(!encoder_enabled, "encoder not enabled\n");
3981 if (WARN_ON(!encoder->base.crtc))
3984 crtc = encoder->base.crtc;
3986 WARN(!crtc->enabled, "crtc not enabled\n");
3987 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3988 WARN(pipe != to_intel_crtc(crtc)->pipe,
3989 "encoder active on the wrong pipe\n");
3993 /* Even simpler default implementation, if there's really no special case to
3995 void intel_connector_dpms(struct drm_connector *connector, int mode)
3997 struct intel_encoder *encoder = intel_attached_encoder(connector);
3999 /* All the simple cases only support two dpms states. */
4000 if (mode != DRM_MODE_DPMS_ON)
4001 mode = DRM_MODE_DPMS_OFF;
4003 if (mode == connector->dpms)
4006 connector->dpms = mode;
4008 /* Only need to change hw state when actually enabled */
4009 if (encoder->base.crtc)
4010 intel_encoder_dpms(encoder, mode);
4012 WARN_ON(encoder->connectors_active != false);
4014 intel_modeset_check_state(connector->dev);
4017 /* Simple connector->get_hw_state implementation for encoders that support only
4018 * one connector and no cloning and hence the encoder state determines the state
4019 * of the connector. */
4020 bool intel_connector_get_hw_state(struct intel_connector *connector)
4023 struct intel_encoder *encoder = connector->encoder;
4025 return encoder->get_hw_state(encoder, &pipe);
4028 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4029 struct intel_crtc_config *pipe_config)
4031 struct drm_i915_private *dev_priv = dev->dev_private;
4032 struct intel_crtc *pipe_B_crtc =
4033 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4035 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4036 pipe_name(pipe), pipe_config->fdi_lanes);
4037 if (pipe_config->fdi_lanes > 4) {
4038 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4039 pipe_name(pipe), pipe_config->fdi_lanes);
4043 if (IS_HASWELL(dev)) {
4044 if (pipe_config->fdi_lanes > 2) {
4045 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4046 pipe_config->fdi_lanes);
4053 if (INTEL_INFO(dev)->num_pipes == 2)
4056 /* Ivybridge 3 pipe is really complicated */
4061 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4062 pipe_config->fdi_lanes > 2) {
4063 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4064 pipe_name(pipe), pipe_config->fdi_lanes);
4069 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4070 pipe_B_crtc->config.fdi_lanes <= 2) {
4071 if (pipe_config->fdi_lanes > 2) {
4072 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4073 pipe_name(pipe), pipe_config->fdi_lanes);
4077 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4087 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4088 struct intel_crtc_config *pipe_config)
4090 struct drm_device *dev = intel_crtc->base.dev;
4091 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4092 int lane, link_bw, fdi_dotclock;
4093 bool setup_ok, needs_recompute = false;
4096 /* FDI is a binary signal running at ~2.7GHz, encoding
4097 * each output octet as 10 bits. The actual frequency
4098 * is stored as a divider into a 100MHz clock, and the
4099 * mode pixel clock is stored in units of 1KHz.
4100 * Hence the bw of each lane in terms of the mode signal
4103 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4105 fdi_dotclock = adjusted_mode->clock;
4107 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4108 pipe_config->pipe_bpp);
4110 pipe_config->fdi_lanes = lane;
4112 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4113 link_bw, &pipe_config->fdi_m_n);
4115 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4116 intel_crtc->pipe, pipe_config);
4117 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4118 pipe_config->pipe_bpp -= 2*3;
4119 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4120 pipe_config->pipe_bpp);
4121 needs_recompute = true;
4122 pipe_config->bw_constrained = true;
4127 if (needs_recompute)
4130 return setup_ok ? 0 : -EINVAL;
4133 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4134 struct intel_crtc_config *pipe_config)
4136 pipe_config->ips_enabled = i915_enable_ips &&
4137 hsw_crtc_supports_ips(crtc) &&
4138 pipe_config->pipe_bpp <= 24;
4141 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4142 struct intel_crtc_config *pipe_config)
4144 struct drm_device *dev = crtc->base.dev;
4145 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4147 /* FIXME should check pixel clock limits on all platforms */
4148 if (INTEL_INFO(dev)->gen < 4) {
4149 struct drm_i915_private *dev_priv = dev->dev_private;
4151 dev_priv->display.get_display_clock_speed(dev);
4154 * Enable pixel doubling when the dot clock
4155 * is > 90% of the (display) core speed.
4157 * GDG double wide on either pipe,
4158 * otherwise pipe A only.
4160 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4161 adjusted_mode->clock > clock_limit * 9 / 10) {
4163 pipe_config->double_wide = true;
4166 if (adjusted_mode->clock > clock_limit * 9 / 10)
4171 * Pipe horizontal size must be even in:
4173 * - LVDS dual channel mode
4174 * - Double wide pipe
4176 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4177 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4178 pipe_config->pipe_src_w &= ~1;
4180 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4181 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4183 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4184 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4187 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4188 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4189 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4190 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4192 pipe_config->pipe_bpp = 8*3;
4196 hsw_compute_ips_config(crtc, pipe_config);
4198 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4199 * clock survives for now. */
4200 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4201 pipe_config->shared_dpll = crtc->config.shared_dpll;
4203 if (pipe_config->has_pch_encoder)
4204 return ironlake_fdi_compute_config(crtc, pipe_config);
4209 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4211 return 400000; /* FIXME */
4214 static int i945_get_display_clock_speed(struct drm_device *dev)
4219 static int i915_get_display_clock_speed(struct drm_device *dev)
4224 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4229 static int pnv_get_display_clock_speed(struct drm_device *dev)
4233 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4235 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4236 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4238 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4240 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4242 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4245 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4246 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4248 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4253 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4257 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4259 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4262 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4263 case GC_DISPLAY_CLOCK_333_MHZ:
4266 case GC_DISPLAY_CLOCK_190_200_MHZ:
4272 static int i865_get_display_clock_speed(struct drm_device *dev)
4277 static int i855_get_display_clock_speed(struct drm_device *dev)
4280 /* Assume that the hardware is in the high speed state. This
4281 * should be the default.
4283 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4284 case GC_CLOCK_133_200:
4285 case GC_CLOCK_100_200:
4287 case GC_CLOCK_166_250:
4289 case GC_CLOCK_100_133:
4293 /* Shouldn't happen */
4297 static int i830_get_display_clock_speed(struct drm_device *dev)
4303 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4305 while (*num > DATA_LINK_M_N_MASK ||
4306 *den > DATA_LINK_M_N_MASK) {
4312 static void compute_m_n(unsigned int m, unsigned int n,
4313 uint32_t *ret_m, uint32_t *ret_n)
4315 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4316 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4317 intel_reduce_m_n_ratio(ret_m, ret_n);
4321 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4322 int pixel_clock, int link_clock,
4323 struct intel_link_m_n *m_n)
4327 compute_m_n(bits_per_pixel * pixel_clock,
4328 link_clock * nlanes * 8,
4329 &m_n->gmch_m, &m_n->gmch_n);
4331 compute_m_n(pixel_clock, link_clock,
4332 &m_n->link_m, &m_n->link_n);
4335 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4337 if (i915_panel_use_ssc >= 0)
4338 return i915_panel_use_ssc != 0;
4339 return dev_priv->vbt.lvds_use_ssc
4340 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4343 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4345 struct drm_device *dev = crtc->dev;
4346 struct drm_i915_private *dev_priv = dev->dev_private;
4349 if (IS_VALLEYVIEW(dev)) {
4351 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4352 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4353 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4354 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4356 } else if (!IS_GEN2(dev)) {
4365 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4367 return (1 << dpll->n) << 16 | dpll->m2;
4370 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4372 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4375 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4376 intel_clock_t *reduced_clock)
4378 struct drm_device *dev = crtc->base.dev;
4379 struct drm_i915_private *dev_priv = dev->dev_private;
4380 int pipe = crtc->pipe;
4383 if (IS_PINEVIEW(dev)) {
4384 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4386 fp2 = pnv_dpll_compute_fp(reduced_clock);
4388 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4390 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4393 I915_WRITE(FP0(pipe), fp);
4394 crtc->config.dpll_hw_state.fp0 = fp;
4396 crtc->lowfreq_avail = false;
4397 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4398 reduced_clock && i915_powersave) {
4399 I915_WRITE(FP1(pipe), fp2);
4400 crtc->config.dpll_hw_state.fp1 = fp2;
4401 crtc->lowfreq_avail = true;
4403 I915_WRITE(FP1(pipe), fp);
4404 crtc->config.dpll_hw_state.fp1 = fp;
4408 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4414 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4415 * and set it to a reasonable value instead.
4417 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4418 reg_val &= 0xffffff00;
4419 reg_val |= 0x00000030;
4420 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4422 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4423 reg_val &= 0x8cffffff;
4424 reg_val = 0x8c000000;
4425 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4427 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4428 reg_val &= 0xffffff00;
4429 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4431 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4432 reg_val &= 0x00ffffff;
4433 reg_val |= 0xb0000000;
4434 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4437 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4438 struct intel_link_m_n *m_n)
4440 struct drm_device *dev = crtc->base.dev;
4441 struct drm_i915_private *dev_priv = dev->dev_private;
4442 int pipe = crtc->pipe;
4444 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4445 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4446 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4447 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4450 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4451 struct intel_link_m_n *m_n)
4453 struct drm_device *dev = crtc->base.dev;
4454 struct drm_i915_private *dev_priv = dev->dev_private;
4455 int pipe = crtc->pipe;
4456 enum transcoder transcoder = crtc->config.cpu_transcoder;
4458 if (INTEL_INFO(dev)->gen >= 5) {
4459 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4460 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4461 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4462 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4464 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4465 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4466 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4467 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4471 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4473 if (crtc->config.has_pch_encoder)
4474 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4476 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4479 static void vlv_update_pll(struct intel_crtc *crtc)
4481 struct drm_device *dev = crtc->base.dev;
4482 struct drm_i915_private *dev_priv = dev->dev_private;
4483 int pipe = crtc->pipe;
4485 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4486 u32 coreclk, reg_val, dpll_md;
4488 mutex_lock(&dev_priv->dpio_lock);
4490 bestn = crtc->config.dpll.n;
4491 bestm1 = crtc->config.dpll.m1;
4492 bestm2 = crtc->config.dpll.m2;
4493 bestp1 = crtc->config.dpll.p1;
4494 bestp2 = crtc->config.dpll.p2;
4496 /* See eDP HDMI DPIO driver vbios notes doc */
4498 /* PLL B needs special handling */
4500 vlv_pllb_recal_opamp(dev_priv, pipe);
4502 /* Set up Tx target for periodic Rcomp update */
4503 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4505 /* Disable target IRef on PLL */
4506 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4507 reg_val &= 0x00ffffff;
4508 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4510 /* Disable fast lock */
4511 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4513 /* Set idtafcrecal before PLL is enabled */
4514 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4515 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4516 mdiv |= ((bestn << DPIO_N_SHIFT));
4517 mdiv |= (1 << DPIO_K_SHIFT);
4520 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4521 * but we don't support that).
4522 * Note: don't use the DAC post divider as it seems unstable.
4524 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4525 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4527 mdiv |= DPIO_ENABLE_CALIBRATION;
4528 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4530 /* Set HBR and RBR LPF coefficients */
4531 if (crtc->config.port_clock == 162000 ||
4532 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4533 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4534 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4537 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4540 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4541 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4542 /* Use SSC source */
4544 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4547 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4549 } else { /* HDMI or VGA */
4550 /* Use bend source */
4552 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4555 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4559 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4560 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4561 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4562 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4563 coreclk |= 0x01000000;
4564 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4566 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4568 /* Enable DPIO clock input */
4569 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4570 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4572 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4574 dpll |= DPLL_VCO_ENABLE;
4575 crtc->config.dpll_hw_state.dpll = dpll;
4577 dpll_md = (crtc->config.pixel_multiplier - 1)
4578 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4579 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4581 if (crtc->config.has_dp_encoder)
4582 intel_dp_set_m_n(crtc);
4584 mutex_unlock(&dev_priv->dpio_lock);
4587 static void i9xx_update_pll(struct intel_crtc *crtc,
4588 intel_clock_t *reduced_clock,
4591 struct drm_device *dev = crtc->base.dev;
4592 struct drm_i915_private *dev_priv = dev->dev_private;
4595 struct dpll *clock = &crtc->config.dpll;
4597 i9xx_update_pll_dividers(crtc, reduced_clock);
4599 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4600 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4602 dpll = DPLL_VGA_MODE_DIS;
4604 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4605 dpll |= DPLLB_MODE_LVDS;
4607 dpll |= DPLLB_MODE_DAC_SERIAL;
4609 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4610 dpll |= (crtc->config.pixel_multiplier - 1)
4611 << SDVO_MULTIPLIER_SHIFT_HIRES;
4615 dpll |= DPLL_SDVO_HIGH_SPEED;
4617 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4618 dpll |= DPLL_SDVO_HIGH_SPEED;
4620 /* compute bitmask from p1 value */
4621 if (IS_PINEVIEW(dev))
4622 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4624 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4625 if (IS_G4X(dev) && reduced_clock)
4626 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4628 switch (clock->p2) {
4630 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4633 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4636 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4639 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4642 if (INTEL_INFO(dev)->gen >= 4)
4643 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4645 if (crtc->config.sdvo_tv_clock)
4646 dpll |= PLL_REF_INPUT_TVCLKINBC;
4647 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4648 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4649 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4651 dpll |= PLL_REF_INPUT_DREFCLK;
4653 dpll |= DPLL_VCO_ENABLE;
4654 crtc->config.dpll_hw_state.dpll = dpll;
4656 if (INTEL_INFO(dev)->gen >= 4) {
4657 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4658 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4659 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4662 if (crtc->config.has_dp_encoder)
4663 intel_dp_set_m_n(crtc);
4666 static void i8xx_update_pll(struct intel_crtc *crtc,
4667 intel_clock_t *reduced_clock,
4670 struct drm_device *dev = crtc->base.dev;
4671 struct drm_i915_private *dev_priv = dev->dev_private;
4673 struct dpll *clock = &crtc->config.dpll;
4675 i9xx_update_pll_dividers(crtc, reduced_clock);
4677 dpll = DPLL_VGA_MODE_DIS;
4679 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4680 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4683 dpll |= PLL_P1_DIVIDE_BY_TWO;
4685 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4687 dpll |= PLL_P2_DIVIDE_BY_4;
4690 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4691 dpll |= DPLL_DVO_2X_MODE;
4693 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4694 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4695 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4697 dpll |= PLL_REF_INPUT_DREFCLK;
4699 dpll |= DPLL_VCO_ENABLE;
4700 crtc->config.dpll_hw_state.dpll = dpll;
4703 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4705 struct drm_device *dev = intel_crtc->base.dev;
4706 struct drm_i915_private *dev_priv = dev->dev_private;
4707 enum pipe pipe = intel_crtc->pipe;
4708 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4709 struct drm_display_mode *adjusted_mode =
4710 &intel_crtc->config.adjusted_mode;
4711 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4713 /* We need to be careful not to changed the adjusted mode, for otherwise
4714 * the hw state checker will get angry at the mismatch. */
4715 crtc_vtotal = adjusted_mode->crtc_vtotal;
4716 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4718 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4719 /* the chip adds 2 halflines automatically */
4721 crtc_vblank_end -= 1;
4722 vsyncshift = adjusted_mode->crtc_hsync_start
4723 - adjusted_mode->crtc_htotal / 2;
4728 if (INTEL_INFO(dev)->gen > 3)
4729 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4731 I915_WRITE(HTOTAL(cpu_transcoder),
4732 (adjusted_mode->crtc_hdisplay - 1) |
4733 ((adjusted_mode->crtc_htotal - 1) << 16));
4734 I915_WRITE(HBLANK(cpu_transcoder),
4735 (adjusted_mode->crtc_hblank_start - 1) |
4736 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4737 I915_WRITE(HSYNC(cpu_transcoder),
4738 (adjusted_mode->crtc_hsync_start - 1) |
4739 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4741 I915_WRITE(VTOTAL(cpu_transcoder),
4742 (adjusted_mode->crtc_vdisplay - 1) |
4743 ((crtc_vtotal - 1) << 16));
4744 I915_WRITE(VBLANK(cpu_transcoder),
4745 (adjusted_mode->crtc_vblank_start - 1) |
4746 ((crtc_vblank_end - 1) << 16));
4747 I915_WRITE(VSYNC(cpu_transcoder),
4748 (adjusted_mode->crtc_vsync_start - 1) |
4749 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4751 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4752 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4753 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4755 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4756 (pipe == PIPE_B || pipe == PIPE_C))
4757 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4759 /* pipesrc controls the size that is scaled from, which should
4760 * always be the user's requested size.
4762 I915_WRITE(PIPESRC(pipe),
4763 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4764 (intel_crtc->config.pipe_src_h - 1));
4767 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4768 struct intel_crtc_config *pipe_config)
4770 struct drm_device *dev = crtc->base.dev;
4771 struct drm_i915_private *dev_priv = dev->dev_private;
4772 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4775 tmp = I915_READ(HTOTAL(cpu_transcoder));
4776 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4777 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4778 tmp = I915_READ(HBLANK(cpu_transcoder));
4779 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4780 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4781 tmp = I915_READ(HSYNC(cpu_transcoder));
4782 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4783 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4785 tmp = I915_READ(VTOTAL(cpu_transcoder));
4786 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4787 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4788 tmp = I915_READ(VBLANK(cpu_transcoder));
4789 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4790 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4791 tmp = I915_READ(VSYNC(cpu_transcoder));
4792 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4793 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4795 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4796 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4797 pipe_config->adjusted_mode.crtc_vtotal += 1;
4798 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4801 tmp = I915_READ(PIPESRC(crtc->pipe));
4802 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4803 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4805 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4806 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
4809 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4810 struct intel_crtc_config *pipe_config)
4812 struct drm_crtc *crtc = &intel_crtc->base;
4814 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4815 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4816 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4817 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4819 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4820 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4821 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4822 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4824 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4826 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4827 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4830 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4832 struct drm_device *dev = intel_crtc->base.dev;
4833 struct drm_i915_private *dev_priv = dev->dev_private;
4838 if (intel_crtc->config.double_wide)
4839 pipeconf |= PIPECONF_DOUBLE_WIDE;
4841 /* only g4x and later have fancy bpc/dither controls */
4842 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4843 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4844 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4845 pipeconf |= PIPECONF_DITHER_EN |
4846 PIPECONF_DITHER_TYPE_SP;
4848 switch (intel_crtc->config.pipe_bpp) {
4850 pipeconf |= PIPECONF_6BPC;
4853 pipeconf |= PIPECONF_8BPC;
4856 pipeconf |= PIPECONF_10BPC;
4859 /* Case prevented by intel_choose_pipe_bpp_dither. */
4864 if (HAS_PIPE_CXSR(dev)) {
4865 if (intel_crtc->lowfreq_avail) {
4866 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4867 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4869 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4873 if (!IS_GEN2(dev) &&
4874 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4875 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4877 pipeconf |= PIPECONF_PROGRESSIVE;
4879 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4880 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4882 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4883 POSTING_READ(PIPECONF(intel_crtc->pipe));
4886 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4888 struct drm_framebuffer *fb)
4890 struct drm_device *dev = crtc->dev;
4891 struct drm_i915_private *dev_priv = dev->dev_private;
4892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4893 int pipe = intel_crtc->pipe;
4894 int plane = intel_crtc->plane;
4895 int refclk, num_connectors = 0;
4896 intel_clock_t clock, reduced_clock;
4898 bool ok, has_reduced_clock = false;
4899 bool is_lvds = false, is_dsi = false;
4900 struct intel_encoder *encoder;
4901 const intel_limit_t *limit;
4904 for_each_encoder_on_crtc(dev, crtc, encoder) {
4905 switch (encoder->type) {
4906 case INTEL_OUTPUT_LVDS:
4909 case INTEL_OUTPUT_DSI:
4917 refclk = i9xx_get_refclk(crtc, num_connectors);
4919 if (!is_dsi && !intel_crtc->config.clock_set) {
4921 * Returns a set of divisors for the desired target clock with
4922 * the given refclk, or FALSE. The returned values represent
4923 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4926 limit = intel_limit(crtc, refclk);
4927 ok = dev_priv->display.find_dpll(limit, crtc,
4928 intel_crtc->config.port_clock,
4929 refclk, NULL, &clock);
4930 if (!ok && !intel_crtc->config.clock_set) {
4931 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4936 /* Ensure that the cursor is valid for the new mode before changing... */
4937 intel_crtc_update_cursor(crtc, true);
4939 if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
4941 * Ensure we match the reduced clock's P to the target clock.
4942 * If the clocks don't match, we can't switch the display clock
4943 * by using the FP0/FP1. In such case we will disable the LVDS
4944 * downclock feature.
4946 limit = intel_limit(crtc, refclk);
4948 dev_priv->display.find_dpll(limit, crtc,
4949 dev_priv->lvds_downclock,
4953 /* Compat-code for transition, will disappear. */
4954 if (!intel_crtc->config.clock_set) {
4955 intel_crtc->config.dpll.n = clock.n;
4956 intel_crtc->config.dpll.m1 = clock.m1;
4957 intel_crtc->config.dpll.m2 = clock.m2;
4958 intel_crtc->config.dpll.p1 = clock.p1;
4959 intel_crtc->config.dpll.p2 = clock.p2;
4963 i8xx_update_pll(intel_crtc,
4964 has_reduced_clock ? &reduced_clock : NULL,
4966 } else if (IS_VALLEYVIEW(dev)) {
4968 vlv_update_pll(intel_crtc);
4970 i9xx_update_pll(intel_crtc,
4971 has_reduced_clock ? &reduced_clock : NULL,
4975 /* Set up the display plane register */
4976 dspcntr = DISPPLANE_GAMMA_ENABLE;
4978 if (!IS_VALLEYVIEW(dev)) {
4980 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4982 dspcntr |= DISPPLANE_SEL_PIPE_B;
4985 intel_set_pipe_timings(intel_crtc);
4987 /* pipesrc and dspsize control the size that is scaled from,
4988 * which should always be the user's requested size.
4990 I915_WRITE(DSPSIZE(plane),
4991 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4992 (intel_crtc->config.pipe_src_w - 1));
4993 I915_WRITE(DSPPOS(plane), 0);
4995 i9xx_set_pipeconf(intel_crtc);
4997 I915_WRITE(DSPCNTR(plane), dspcntr);
4998 POSTING_READ(DSPCNTR(plane));
5000 ret = intel_pipe_set_base(crtc, x, y, fb);
5005 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5006 struct intel_crtc_config *pipe_config)
5008 struct drm_device *dev = crtc->base.dev;
5009 struct drm_i915_private *dev_priv = dev->dev_private;
5012 tmp = I915_READ(PFIT_CONTROL);
5013 if (!(tmp & PFIT_ENABLE))
5016 /* Check whether the pfit is attached to our pipe. */
5017 if (INTEL_INFO(dev)->gen < 4) {
5018 if (crtc->pipe != PIPE_B)
5021 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5025 pipe_config->gmch_pfit.control = tmp;
5026 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5027 if (INTEL_INFO(dev)->gen < 5)
5028 pipe_config->gmch_pfit.lvds_border_bits =
5029 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5032 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5033 struct intel_crtc_config *pipe_config)
5035 struct drm_device *dev = crtc->base.dev;
5036 struct drm_i915_private *dev_priv = dev->dev_private;
5039 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5040 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5042 tmp = I915_READ(PIPECONF(crtc->pipe));
5043 if (!(tmp & PIPECONF_ENABLE))
5046 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5047 switch (tmp & PIPECONF_BPC_MASK) {
5049 pipe_config->pipe_bpp = 18;
5052 pipe_config->pipe_bpp = 24;
5054 case PIPECONF_10BPC:
5055 pipe_config->pipe_bpp = 30;
5062 if (INTEL_INFO(dev)->gen < 4)
5063 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5065 intel_get_pipe_timings(crtc, pipe_config);
5067 i9xx_get_pfit_config(crtc, pipe_config);
5069 if (INTEL_INFO(dev)->gen >= 4) {
5070 tmp = I915_READ(DPLL_MD(crtc->pipe));
5071 pipe_config->pixel_multiplier =
5072 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5073 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5074 pipe_config->dpll_hw_state.dpll_md = tmp;
5075 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5076 tmp = I915_READ(DPLL(crtc->pipe));
5077 pipe_config->pixel_multiplier =
5078 ((tmp & SDVO_MULTIPLIER_MASK)
5079 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5081 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5082 * port and will be fixed up in the encoder->get_config
5084 pipe_config->pixel_multiplier = 1;
5086 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5087 if (!IS_VALLEYVIEW(dev)) {
5088 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5089 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5091 /* Mask out read-only status bits. */
5092 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5093 DPLL_PORTC_READY_MASK |
5094 DPLL_PORTB_READY_MASK);
5097 i9xx_crtc_clock_get(crtc, pipe_config);
5102 static void ironlake_init_pch_refclk(struct drm_device *dev)
5104 struct drm_i915_private *dev_priv = dev->dev_private;
5105 struct drm_mode_config *mode_config = &dev->mode_config;
5106 struct intel_encoder *encoder;
5108 bool has_lvds = false;
5109 bool has_cpu_edp = false;
5110 bool has_panel = false;
5111 bool has_ck505 = false;
5112 bool can_ssc = false;
5114 /* We need to take the global config into account */
5115 list_for_each_entry(encoder, &mode_config->encoder_list,
5117 switch (encoder->type) {
5118 case INTEL_OUTPUT_LVDS:
5122 case INTEL_OUTPUT_EDP:
5124 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5130 if (HAS_PCH_IBX(dev)) {
5131 has_ck505 = dev_priv->vbt.display_clock_mode;
5132 can_ssc = has_ck505;
5138 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5139 has_panel, has_lvds, has_ck505);
5141 /* Ironlake: try to setup display ref clock before DPLL
5142 * enabling. This is only under driver's control after
5143 * PCH B stepping, previous chipset stepping should be
5144 * ignoring this setting.
5146 val = I915_READ(PCH_DREF_CONTROL);
5148 /* As we must carefully and slowly disable/enable each source in turn,
5149 * compute the final state we want first and check if we need to
5150 * make any changes at all.
5153 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5155 final |= DREF_NONSPREAD_CK505_ENABLE;
5157 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5159 final &= ~DREF_SSC_SOURCE_MASK;
5160 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5161 final &= ~DREF_SSC1_ENABLE;
5164 final |= DREF_SSC_SOURCE_ENABLE;
5166 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5167 final |= DREF_SSC1_ENABLE;
5170 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5171 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5173 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5175 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5177 final |= DREF_SSC_SOURCE_DISABLE;
5178 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5184 /* Always enable nonspread source */
5185 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5188 val |= DREF_NONSPREAD_CK505_ENABLE;
5190 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5193 val &= ~DREF_SSC_SOURCE_MASK;
5194 val |= DREF_SSC_SOURCE_ENABLE;
5196 /* SSC must be turned on before enabling the CPU output */
5197 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5198 DRM_DEBUG_KMS("Using SSC on panel\n");
5199 val |= DREF_SSC1_ENABLE;
5201 val &= ~DREF_SSC1_ENABLE;
5203 /* Get SSC going before enabling the outputs */
5204 I915_WRITE(PCH_DREF_CONTROL, val);
5205 POSTING_READ(PCH_DREF_CONTROL);
5208 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5210 /* Enable CPU source on CPU attached eDP */
5212 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5213 DRM_DEBUG_KMS("Using SSC on eDP\n");
5214 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5217 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5219 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5221 I915_WRITE(PCH_DREF_CONTROL, val);
5222 POSTING_READ(PCH_DREF_CONTROL);
5225 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5227 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5229 /* Turn off CPU output */
5230 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5232 I915_WRITE(PCH_DREF_CONTROL, val);
5233 POSTING_READ(PCH_DREF_CONTROL);
5236 /* Turn off the SSC source */
5237 val &= ~DREF_SSC_SOURCE_MASK;
5238 val |= DREF_SSC_SOURCE_DISABLE;
5241 val &= ~DREF_SSC1_ENABLE;
5243 I915_WRITE(PCH_DREF_CONTROL, val);
5244 POSTING_READ(PCH_DREF_CONTROL);
5248 BUG_ON(val != final);
5251 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5255 tmp = I915_READ(SOUTH_CHICKEN2);
5256 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5257 I915_WRITE(SOUTH_CHICKEN2, tmp);
5259 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5260 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5261 DRM_ERROR("FDI mPHY reset assert timeout\n");
5263 tmp = I915_READ(SOUTH_CHICKEN2);
5264 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5265 I915_WRITE(SOUTH_CHICKEN2, tmp);
5267 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5268 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5269 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5272 /* WaMPhyProgramming:hsw */
5273 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5277 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5278 tmp &= ~(0xFF << 24);
5279 tmp |= (0x12 << 24);
5280 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5282 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5284 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5286 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5288 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5290 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5291 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5292 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5294 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5295 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5296 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5298 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5301 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5303 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5306 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5308 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5311 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5313 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5316 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5318 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5319 tmp &= ~(0xFF << 16);
5320 tmp |= (0x1C << 16);
5321 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5323 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5324 tmp &= ~(0xFF << 16);
5325 tmp |= (0x1C << 16);
5326 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5328 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5330 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5332 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5334 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5336 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5337 tmp &= ~(0xF << 28);
5339 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5341 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5342 tmp &= ~(0xF << 28);
5344 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5347 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5348 * Programming" based on the parameters passed:
5349 * - Sequence to enable CLKOUT_DP
5350 * - Sequence to enable CLKOUT_DP without spread
5351 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5353 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5356 struct drm_i915_private *dev_priv = dev->dev_private;
5359 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5361 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5362 with_fdi, "LP PCH doesn't have FDI\n"))
5365 mutex_lock(&dev_priv->dpio_lock);
5367 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5368 tmp &= ~SBI_SSCCTL_DISABLE;
5369 tmp |= SBI_SSCCTL_PATHALT;
5370 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5375 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5376 tmp &= ~SBI_SSCCTL_PATHALT;
5377 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5380 lpt_reset_fdi_mphy(dev_priv);
5381 lpt_program_fdi_mphy(dev_priv);
5385 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5386 SBI_GEN0 : SBI_DBUFF0;
5387 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5388 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5389 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5391 mutex_unlock(&dev_priv->dpio_lock);
5394 /* Sequence to disable CLKOUT_DP */
5395 static void lpt_disable_clkout_dp(struct drm_device *dev)
5397 struct drm_i915_private *dev_priv = dev->dev_private;
5400 mutex_lock(&dev_priv->dpio_lock);
5402 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5403 SBI_GEN0 : SBI_DBUFF0;
5404 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5405 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5406 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5408 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5409 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5410 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5411 tmp |= SBI_SSCCTL_PATHALT;
5412 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5415 tmp |= SBI_SSCCTL_DISABLE;
5416 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5419 mutex_unlock(&dev_priv->dpio_lock);
5422 static void lpt_init_pch_refclk(struct drm_device *dev)
5424 struct drm_mode_config *mode_config = &dev->mode_config;
5425 struct intel_encoder *encoder;
5426 bool has_vga = false;
5428 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5429 switch (encoder->type) {
5430 case INTEL_OUTPUT_ANALOG:
5437 lpt_enable_clkout_dp(dev, true, true);
5439 lpt_disable_clkout_dp(dev);
5443 * Initialize reference clocks when the driver loads
5445 void intel_init_pch_refclk(struct drm_device *dev)
5447 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5448 ironlake_init_pch_refclk(dev);
5449 else if (HAS_PCH_LPT(dev))
5450 lpt_init_pch_refclk(dev);
5453 static int ironlake_get_refclk(struct drm_crtc *crtc)
5455 struct drm_device *dev = crtc->dev;
5456 struct drm_i915_private *dev_priv = dev->dev_private;
5457 struct intel_encoder *encoder;
5458 int num_connectors = 0;
5459 bool is_lvds = false;
5461 for_each_encoder_on_crtc(dev, crtc, encoder) {
5462 switch (encoder->type) {
5463 case INTEL_OUTPUT_LVDS:
5470 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5471 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5472 dev_priv->vbt.lvds_ssc_freq);
5473 return dev_priv->vbt.lvds_ssc_freq * 1000;
5479 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5481 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5483 int pipe = intel_crtc->pipe;
5488 switch (intel_crtc->config.pipe_bpp) {
5490 val |= PIPECONF_6BPC;
5493 val |= PIPECONF_8BPC;
5496 val |= PIPECONF_10BPC;
5499 val |= PIPECONF_12BPC;
5502 /* Case prevented by intel_choose_pipe_bpp_dither. */
5506 if (intel_crtc->config.dither)
5507 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5509 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5510 val |= PIPECONF_INTERLACED_ILK;
5512 val |= PIPECONF_PROGRESSIVE;
5514 if (intel_crtc->config.limited_color_range)
5515 val |= PIPECONF_COLOR_RANGE_SELECT;
5517 I915_WRITE(PIPECONF(pipe), val);
5518 POSTING_READ(PIPECONF(pipe));
5522 * Set up the pipe CSC unit.
5524 * Currently only full range RGB to limited range RGB conversion
5525 * is supported, but eventually this should handle various
5526 * RGB<->YCbCr scenarios as well.
5528 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5530 struct drm_device *dev = crtc->dev;
5531 struct drm_i915_private *dev_priv = dev->dev_private;
5532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5533 int pipe = intel_crtc->pipe;
5534 uint16_t coeff = 0x7800; /* 1.0 */
5537 * TODO: Check what kind of values actually come out of the pipe
5538 * with these coeff/postoff values and adjust to get the best
5539 * accuracy. Perhaps we even need to take the bpc value into
5543 if (intel_crtc->config.limited_color_range)
5544 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5547 * GY/GU and RY/RU should be the other way around according
5548 * to BSpec, but reality doesn't agree. Just set them up in
5549 * a way that results in the correct picture.
5551 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5552 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5554 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5555 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5557 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5558 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5560 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5561 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5562 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5564 if (INTEL_INFO(dev)->gen > 6) {
5565 uint16_t postoff = 0;
5567 if (intel_crtc->config.limited_color_range)
5568 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5570 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5571 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5572 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5574 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5576 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5578 if (intel_crtc->config.limited_color_range)
5579 mode |= CSC_BLACK_SCREEN_OFFSET;
5581 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5585 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5587 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5589 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5594 if (intel_crtc->config.dither)
5595 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5597 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5598 val |= PIPECONF_INTERLACED_ILK;
5600 val |= PIPECONF_PROGRESSIVE;
5602 I915_WRITE(PIPECONF(cpu_transcoder), val);
5603 POSTING_READ(PIPECONF(cpu_transcoder));
5605 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5606 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5609 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5610 intel_clock_t *clock,
5611 bool *has_reduced_clock,
5612 intel_clock_t *reduced_clock)
5614 struct drm_device *dev = crtc->dev;
5615 struct drm_i915_private *dev_priv = dev->dev_private;
5616 struct intel_encoder *intel_encoder;
5618 const intel_limit_t *limit;
5619 bool ret, is_lvds = false;
5621 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5622 switch (intel_encoder->type) {
5623 case INTEL_OUTPUT_LVDS:
5629 refclk = ironlake_get_refclk(crtc);
5632 * Returns a set of divisors for the desired target clock with the given
5633 * refclk, or FALSE. The returned values represent the clock equation:
5634 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5636 limit = intel_limit(crtc, refclk);
5637 ret = dev_priv->display.find_dpll(limit, crtc,
5638 to_intel_crtc(crtc)->config.port_clock,
5639 refclk, NULL, clock);
5643 if (is_lvds && dev_priv->lvds_downclock_avail) {
5645 * Ensure we match the reduced clock's P to the target clock.
5646 * If the clocks don't match, we can't switch the display clock
5647 * by using the FP0/FP1. In such case we will disable the LVDS
5648 * downclock feature.
5650 *has_reduced_clock =
5651 dev_priv->display.find_dpll(limit, crtc,
5652 dev_priv->lvds_downclock,
5660 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5662 struct drm_i915_private *dev_priv = dev->dev_private;
5665 temp = I915_READ(SOUTH_CHICKEN1);
5666 if (temp & FDI_BC_BIFURCATION_SELECT)
5669 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5670 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5672 temp |= FDI_BC_BIFURCATION_SELECT;
5673 DRM_DEBUG_KMS("enabling fdi C rx\n");
5674 I915_WRITE(SOUTH_CHICKEN1, temp);
5675 POSTING_READ(SOUTH_CHICKEN1);
5678 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5680 struct drm_device *dev = intel_crtc->base.dev;
5681 struct drm_i915_private *dev_priv = dev->dev_private;
5683 switch (intel_crtc->pipe) {
5687 if (intel_crtc->config.fdi_lanes > 2)
5688 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5690 cpt_enable_fdi_bc_bifurcation(dev);
5694 cpt_enable_fdi_bc_bifurcation(dev);
5702 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5705 * Account for spread spectrum to avoid
5706 * oversubscribing the link. Max center spread
5707 * is 2.5%; use 5% for safety's sake.
5709 u32 bps = target_clock * bpp * 21 / 20;
5710 return bps / (link_bw * 8) + 1;
5713 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5715 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5718 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5720 intel_clock_t *reduced_clock, u32 *fp2)
5722 struct drm_crtc *crtc = &intel_crtc->base;
5723 struct drm_device *dev = crtc->dev;
5724 struct drm_i915_private *dev_priv = dev->dev_private;
5725 struct intel_encoder *intel_encoder;
5727 int factor, num_connectors = 0;
5728 bool is_lvds = false, is_sdvo = false;
5730 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5731 switch (intel_encoder->type) {
5732 case INTEL_OUTPUT_LVDS:
5735 case INTEL_OUTPUT_SDVO:
5736 case INTEL_OUTPUT_HDMI:
5744 /* Enable autotuning of the PLL clock (if permissible) */
5747 if ((intel_panel_use_ssc(dev_priv) &&
5748 dev_priv->vbt.lvds_ssc_freq == 100) ||
5749 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5751 } else if (intel_crtc->config.sdvo_tv_clock)
5754 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5757 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5763 dpll |= DPLLB_MODE_LVDS;
5765 dpll |= DPLLB_MODE_DAC_SERIAL;
5767 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5768 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5771 dpll |= DPLL_SDVO_HIGH_SPEED;
5772 if (intel_crtc->config.has_dp_encoder)
5773 dpll |= DPLL_SDVO_HIGH_SPEED;
5775 /* compute bitmask from p1 value */
5776 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5778 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5780 switch (intel_crtc->config.dpll.p2) {
5782 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5785 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5788 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5791 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5795 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5796 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5798 dpll |= PLL_REF_INPUT_DREFCLK;
5800 return dpll | DPLL_VCO_ENABLE;
5803 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5805 struct drm_framebuffer *fb)
5807 struct drm_device *dev = crtc->dev;
5808 struct drm_i915_private *dev_priv = dev->dev_private;
5809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5810 int pipe = intel_crtc->pipe;
5811 int plane = intel_crtc->plane;
5812 int num_connectors = 0;
5813 intel_clock_t clock, reduced_clock;
5814 u32 dpll = 0, fp = 0, fp2 = 0;
5815 bool ok, has_reduced_clock = false;
5816 bool is_lvds = false;
5817 struct intel_encoder *encoder;
5818 struct intel_shared_dpll *pll;
5821 for_each_encoder_on_crtc(dev, crtc, encoder) {
5822 switch (encoder->type) {
5823 case INTEL_OUTPUT_LVDS:
5831 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5832 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5834 ok = ironlake_compute_clocks(crtc, &clock,
5835 &has_reduced_clock, &reduced_clock);
5836 if (!ok && !intel_crtc->config.clock_set) {
5837 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5840 /* Compat-code for transition, will disappear. */
5841 if (!intel_crtc->config.clock_set) {
5842 intel_crtc->config.dpll.n = clock.n;
5843 intel_crtc->config.dpll.m1 = clock.m1;
5844 intel_crtc->config.dpll.m2 = clock.m2;
5845 intel_crtc->config.dpll.p1 = clock.p1;
5846 intel_crtc->config.dpll.p2 = clock.p2;
5849 /* Ensure that the cursor is valid for the new mode before changing... */
5850 intel_crtc_update_cursor(crtc, true);
5852 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5853 if (intel_crtc->config.has_pch_encoder) {
5854 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5855 if (has_reduced_clock)
5856 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5858 dpll = ironlake_compute_dpll(intel_crtc,
5859 &fp, &reduced_clock,
5860 has_reduced_clock ? &fp2 : NULL);
5862 intel_crtc->config.dpll_hw_state.dpll = dpll;
5863 intel_crtc->config.dpll_hw_state.fp0 = fp;
5864 if (has_reduced_clock)
5865 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5867 intel_crtc->config.dpll_hw_state.fp1 = fp;
5869 pll = intel_get_shared_dpll(intel_crtc);
5871 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5876 intel_put_shared_dpll(intel_crtc);
5878 if (intel_crtc->config.has_dp_encoder)
5879 intel_dp_set_m_n(intel_crtc);
5881 if (is_lvds && has_reduced_clock && i915_powersave)
5882 intel_crtc->lowfreq_avail = true;
5884 intel_crtc->lowfreq_avail = false;
5886 if (intel_crtc->config.has_pch_encoder) {
5887 pll = intel_crtc_to_shared_dpll(intel_crtc);
5891 intel_set_pipe_timings(intel_crtc);
5893 if (intel_crtc->config.has_pch_encoder) {
5894 intel_cpu_transcoder_set_m_n(intel_crtc,
5895 &intel_crtc->config.fdi_m_n);
5898 if (IS_IVYBRIDGE(dev))
5899 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5901 ironlake_set_pipeconf(crtc);
5903 /* Set up the display plane register */
5904 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5905 POSTING_READ(DSPCNTR(plane));
5907 ret = intel_pipe_set_base(crtc, x, y, fb);
5912 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5913 struct intel_link_m_n *m_n)
5915 struct drm_device *dev = crtc->base.dev;
5916 struct drm_i915_private *dev_priv = dev->dev_private;
5917 enum pipe pipe = crtc->pipe;
5919 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5920 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5921 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5923 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5924 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
5925 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5928 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5929 enum transcoder transcoder,
5930 struct intel_link_m_n *m_n)
5932 struct drm_device *dev = crtc->base.dev;
5933 struct drm_i915_private *dev_priv = dev->dev_private;
5934 enum pipe pipe = crtc->pipe;
5936 if (INTEL_INFO(dev)->gen >= 5) {
5937 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
5938 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
5939 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5941 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5942 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5943 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5945 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
5946 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
5947 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
5949 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
5950 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
5951 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5955 void intel_dp_get_m_n(struct intel_crtc *crtc,
5956 struct intel_crtc_config *pipe_config)
5958 if (crtc->config.has_pch_encoder)
5959 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5961 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5962 &pipe_config->dp_m_n);
5965 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5966 struct intel_crtc_config *pipe_config)
5968 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5969 &pipe_config->fdi_m_n);
5972 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5973 struct intel_crtc_config *pipe_config)
5975 struct drm_device *dev = crtc->base.dev;
5976 struct drm_i915_private *dev_priv = dev->dev_private;
5979 tmp = I915_READ(PF_CTL(crtc->pipe));
5981 if (tmp & PF_ENABLE) {
5982 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5983 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5985 /* We currently do not free assignements of panel fitters on
5986 * ivb/hsw (since we don't use the higher upscaling modes which
5987 * differentiates them) so just WARN about this case for now. */
5989 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5990 PF_PIPE_SEL_IVB(crtc->pipe));
5995 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5996 struct intel_crtc_config *pipe_config)
5998 struct drm_device *dev = crtc->base.dev;
5999 struct drm_i915_private *dev_priv = dev->dev_private;
6002 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6003 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6005 tmp = I915_READ(PIPECONF(crtc->pipe));
6006 if (!(tmp & PIPECONF_ENABLE))
6009 switch (tmp & PIPECONF_BPC_MASK) {
6011 pipe_config->pipe_bpp = 18;
6014 pipe_config->pipe_bpp = 24;
6016 case PIPECONF_10BPC:
6017 pipe_config->pipe_bpp = 30;
6019 case PIPECONF_12BPC:
6020 pipe_config->pipe_bpp = 36;
6026 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6027 struct intel_shared_dpll *pll;
6029 pipe_config->has_pch_encoder = true;
6031 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6032 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6033 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6035 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6037 if (HAS_PCH_IBX(dev_priv->dev)) {
6038 pipe_config->shared_dpll =
6039 (enum intel_dpll_id) crtc->pipe;
6041 tmp = I915_READ(PCH_DPLL_SEL);
6042 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6043 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6045 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6048 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6050 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6051 &pipe_config->dpll_hw_state));
6053 tmp = pipe_config->dpll_hw_state.dpll;
6054 pipe_config->pixel_multiplier =
6055 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6056 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6058 ironlake_pch_clock_get(crtc, pipe_config);
6060 pipe_config->pixel_multiplier = 1;
6063 intel_get_pipe_timings(crtc, pipe_config);
6065 ironlake_get_pfit_config(crtc, pipe_config);
6070 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6072 struct drm_device *dev = dev_priv->dev;
6073 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6074 struct intel_crtc *crtc;
6075 unsigned long irqflags;
6078 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6079 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6080 pipe_name(crtc->pipe));
6082 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6083 WARN(plls->spll_refcount, "SPLL enabled\n");
6084 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6085 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6086 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6087 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6088 "CPU PWM1 enabled\n");
6089 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6090 "CPU PWM2 enabled\n");
6091 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6092 "PCH PWM1 enabled\n");
6093 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6094 "Utility pin enabled\n");
6095 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6097 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6098 val = I915_READ(DEIMR);
6099 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6100 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6101 val = I915_READ(SDEIMR);
6102 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6103 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6104 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6108 * This function implements pieces of two sequences from BSpec:
6109 * - Sequence for display software to disable LCPLL
6110 * - Sequence for display software to allow package C8+
6111 * The steps implemented here are just the steps that actually touch the LCPLL
6112 * register. Callers should take care of disabling all the display engine
6113 * functions, doing the mode unset, fixing interrupts, etc.
6115 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6116 bool switch_to_fclk, bool allow_power_down)
6120 assert_can_disable_lcpll(dev_priv);
6122 val = I915_READ(LCPLL_CTL);
6124 if (switch_to_fclk) {
6125 val |= LCPLL_CD_SOURCE_FCLK;
6126 I915_WRITE(LCPLL_CTL, val);
6128 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6129 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6130 DRM_ERROR("Switching to FCLK failed\n");
6132 val = I915_READ(LCPLL_CTL);
6135 val |= LCPLL_PLL_DISABLE;
6136 I915_WRITE(LCPLL_CTL, val);
6137 POSTING_READ(LCPLL_CTL);
6139 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6140 DRM_ERROR("LCPLL still locked\n");
6142 val = I915_READ(D_COMP);
6143 val |= D_COMP_COMP_DISABLE;
6144 mutex_lock(&dev_priv->rps.hw_lock);
6145 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6146 DRM_ERROR("Failed to disable D_COMP\n");
6147 mutex_unlock(&dev_priv->rps.hw_lock);
6148 POSTING_READ(D_COMP);
6151 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6152 DRM_ERROR("D_COMP RCOMP still in progress\n");
6154 if (allow_power_down) {
6155 val = I915_READ(LCPLL_CTL);
6156 val |= LCPLL_POWER_DOWN_ALLOW;
6157 I915_WRITE(LCPLL_CTL, val);
6158 POSTING_READ(LCPLL_CTL);
6163 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6166 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6170 val = I915_READ(LCPLL_CTL);
6172 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6173 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6176 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6177 * we'll hang the machine! */
6178 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6180 if (val & LCPLL_POWER_DOWN_ALLOW) {
6181 val &= ~LCPLL_POWER_DOWN_ALLOW;
6182 I915_WRITE(LCPLL_CTL, val);
6183 POSTING_READ(LCPLL_CTL);
6186 val = I915_READ(D_COMP);
6187 val |= D_COMP_COMP_FORCE;
6188 val &= ~D_COMP_COMP_DISABLE;
6189 mutex_lock(&dev_priv->rps.hw_lock);
6190 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6191 DRM_ERROR("Failed to enable D_COMP\n");
6192 mutex_unlock(&dev_priv->rps.hw_lock);
6193 POSTING_READ(D_COMP);
6195 val = I915_READ(LCPLL_CTL);
6196 val &= ~LCPLL_PLL_DISABLE;
6197 I915_WRITE(LCPLL_CTL, val);
6199 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6200 DRM_ERROR("LCPLL not locked yet\n");
6202 if (val & LCPLL_CD_SOURCE_FCLK) {
6203 val = I915_READ(LCPLL_CTL);
6204 val &= ~LCPLL_CD_SOURCE_FCLK;
6205 I915_WRITE(LCPLL_CTL, val);
6207 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6208 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6209 DRM_ERROR("Switching back to LCPLL failed\n");
6212 dev_priv->uncore.funcs.force_wake_put(dev_priv);
6215 void hsw_enable_pc8_work(struct work_struct *__work)
6217 struct drm_i915_private *dev_priv =
6218 container_of(to_delayed_work(__work), struct drm_i915_private,
6220 struct drm_device *dev = dev_priv->dev;
6223 if (dev_priv->pc8.enabled)
6226 DRM_DEBUG_KMS("Enabling package C8+\n");
6228 dev_priv->pc8.enabled = true;
6230 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6231 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6232 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6233 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6236 lpt_disable_clkout_dp(dev);
6237 hsw_pc8_disable_interrupts(dev);
6238 hsw_disable_lcpll(dev_priv, true, true);
6241 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6243 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6244 WARN(dev_priv->pc8.disable_count < 1,
6245 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6247 dev_priv->pc8.disable_count--;
6248 if (dev_priv->pc8.disable_count != 0)
6251 schedule_delayed_work(&dev_priv->pc8.enable_work,
6252 msecs_to_jiffies(i915_pc8_timeout));
6255 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6257 struct drm_device *dev = dev_priv->dev;
6260 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6261 WARN(dev_priv->pc8.disable_count < 0,
6262 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6264 dev_priv->pc8.disable_count++;
6265 if (dev_priv->pc8.disable_count != 1)
6268 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6269 if (!dev_priv->pc8.enabled)
6272 DRM_DEBUG_KMS("Disabling package C8+\n");
6274 hsw_restore_lcpll(dev_priv);
6275 hsw_pc8_restore_interrupts(dev);
6276 lpt_init_pch_refclk(dev);
6278 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6279 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6280 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6281 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6284 intel_prepare_ddi(dev);
6285 i915_gem_init_swizzling(dev);
6286 mutex_lock(&dev_priv->rps.hw_lock);
6287 gen6_update_ring_freq(dev);
6288 mutex_unlock(&dev_priv->rps.hw_lock);
6289 dev_priv->pc8.enabled = false;
6292 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6294 mutex_lock(&dev_priv->pc8.lock);
6295 __hsw_enable_package_c8(dev_priv);
6296 mutex_unlock(&dev_priv->pc8.lock);
6299 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6301 mutex_lock(&dev_priv->pc8.lock);
6302 __hsw_disable_package_c8(dev_priv);
6303 mutex_unlock(&dev_priv->pc8.lock);
6306 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6308 struct drm_device *dev = dev_priv->dev;
6309 struct intel_crtc *crtc;
6312 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6313 if (crtc->base.enabled)
6316 /* This case is still possible since we have the i915.disable_power_well
6317 * parameter and also the KVMr or something else might be requesting the
6319 val = I915_READ(HSW_PWR_WELL_DRIVER);
6321 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6328 /* Since we're called from modeset_global_resources there's no way to
6329 * symmetrically increase and decrease the refcount, so we use
6330 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6333 static void hsw_update_package_c8(struct drm_device *dev)
6335 struct drm_i915_private *dev_priv = dev->dev_private;
6338 if (!i915_enable_pc8)
6341 mutex_lock(&dev_priv->pc8.lock);
6343 allow = hsw_can_enable_package_c8(dev_priv);
6345 if (allow == dev_priv->pc8.requirements_met)
6348 dev_priv->pc8.requirements_met = allow;
6351 __hsw_enable_package_c8(dev_priv);
6353 __hsw_disable_package_c8(dev_priv);
6356 mutex_unlock(&dev_priv->pc8.lock);
6359 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6361 if (!dev_priv->pc8.gpu_idle) {
6362 dev_priv->pc8.gpu_idle = true;
6363 hsw_enable_package_c8(dev_priv);
6367 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6369 if (dev_priv->pc8.gpu_idle) {
6370 dev_priv->pc8.gpu_idle = false;
6371 hsw_disable_package_c8(dev_priv);
6375 static void haswell_modeset_global_resources(struct drm_device *dev)
6377 bool enable = false;
6378 struct intel_crtc *crtc;
6380 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6381 if (!crtc->base.enabled)
6384 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6385 crtc->config.cpu_transcoder != TRANSCODER_EDP)
6389 intel_set_power_well(dev, enable);
6391 hsw_update_package_c8(dev);
6394 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6396 struct drm_framebuffer *fb)
6398 struct drm_device *dev = crtc->dev;
6399 struct drm_i915_private *dev_priv = dev->dev_private;
6400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6401 int plane = intel_crtc->plane;
6404 if (!intel_ddi_pll_mode_set(crtc))
6407 /* Ensure that the cursor is valid for the new mode before changing... */
6408 intel_crtc_update_cursor(crtc, true);
6410 if (intel_crtc->config.has_dp_encoder)
6411 intel_dp_set_m_n(intel_crtc);
6413 intel_crtc->lowfreq_avail = false;
6415 intel_set_pipe_timings(intel_crtc);
6417 if (intel_crtc->config.has_pch_encoder) {
6418 intel_cpu_transcoder_set_m_n(intel_crtc,
6419 &intel_crtc->config.fdi_m_n);
6422 haswell_set_pipeconf(crtc);
6424 intel_set_pipe_csc(crtc);
6426 /* Set up the display plane register */
6427 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6428 POSTING_READ(DSPCNTR(plane));
6430 ret = intel_pipe_set_base(crtc, x, y, fb);
6435 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6436 struct intel_crtc_config *pipe_config)
6438 struct drm_device *dev = crtc->base.dev;
6439 struct drm_i915_private *dev_priv = dev->dev_private;
6440 enum intel_display_power_domain pfit_domain;
6443 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6444 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6446 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6447 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6448 enum pipe trans_edp_pipe;
6449 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6451 WARN(1, "unknown pipe linked to edp transcoder\n");
6452 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6453 case TRANS_DDI_EDP_INPUT_A_ON:
6454 trans_edp_pipe = PIPE_A;
6456 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6457 trans_edp_pipe = PIPE_B;
6459 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6460 trans_edp_pipe = PIPE_C;
6464 if (trans_edp_pipe == crtc->pipe)
6465 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6468 if (!intel_display_power_enabled(dev,
6469 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6472 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6473 if (!(tmp & PIPECONF_ENABLE))
6477 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6478 * DDI E. So just check whether this pipe is wired to DDI E and whether
6479 * the PCH transcoder is on.
6481 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6482 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6483 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6484 pipe_config->has_pch_encoder = true;
6486 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6487 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6488 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6490 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6493 intel_get_pipe_timings(crtc, pipe_config);
6495 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6496 if (intel_display_power_enabled(dev, pfit_domain))
6497 ironlake_get_pfit_config(crtc, pipe_config);
6499 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6500 (I915_READ(IPS_CTL) & IPS_ENABLE);
6502 pipe_config->pixel_multiplier = 1;
6507 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6509 struct drm_framebuffer *fb)
6511 struct drm_device *dev = crtc->dev;
6512 struct drm_i915_private *dev_priv = dev->dev_private;
6513 struct intel_encoder *encoder;
6514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6515 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6516 int pipe = intel_crtc->pipe;
6519 drm_vblank_pre_modeset(dev, pipe);
6521 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6523 drm_vblank_post_modeset(dev, pipe);
6528 for_each_encoder_on_crtc(dev, crtc, encoder) {
6529 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6530 encoder->base.base.id,
6531 drm_get_encoder_name(&encoder->base),
6532 mode->base.id, mode->name);
6533 encoder->mode_set(encoder);
6539 static bool intel_eld_uptodate(struct drm_connector *connector,
6540 int reg_eldv, uint32_t bits_eldv,
6541 int reg_elda, uint32_t bits_elda,
6544 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6545 uint8_t *eld = connector->eld;
6548 i = I915_READ(reg_eldv);
6557 i = I915_READ(reg_elda);
6559 I915_WRITE(reg_elda, i);
6561 for (i = 0; i < eld[2]; i++)
6562 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6568 static void g4x_write_eld(struct drm_connector *connector,
6569 struct drm_crtc *crtc)
6571 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6572 uint8_t *eld = connector->eld;
6577 i = I915_READ(G4X_AUD_VID_DID);
6579 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6580 eldv = G4X_ELDV_DEVCL_DEVBLC;
6582 eldv = G4X_ELDV_DEVCTG;
6584 if (intel_eld_uptodate(connector,
6585 G4X_AUD_CNTL_ST, eldv,
6586 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6587 G4X_HDMIW_HDMIEDID))
6590 i = I915_READ(G4X_AUD_CNTL_ST);
6591 i &= ~(eldv | G4X_ELD_ADDR);
6592 len = (i >> 9) & 0x1f; /* ELD buffer size */
6593 I915_WRITE(G4X_AUD_CNTL_ST, i);
6598 len = min_t(uint8_t, eld[2], len);
6599 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6600 for (i = 0; i < len; i++)
6601 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6603 i = I915_READ(G4X_AUD_CNTL_ST);
6605 I915_WRITE(G4X_AUD_CNTL_ST, i);
6608 static void haswell_write_eld(struct drm_connector *connector,
6609 struct drm_crtc *crtc)
6611 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6612 uint8_t *eld = connector->eld;
6613 struct drm_device *dev = crtc->dev;
6614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6618 int pipe = to_intel_crtc(crtc)->pipe;
6621 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6622 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6623 int aud_config = HSW_AUD_CFG(pipe);
6624 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6627 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6629 /* Audio output enable */
6630 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6631 tmp = I915_READ(aud_cntrl_st2);
6632 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6633 I915_WRITE(aud_cntrl_st2, tmp);
6635 /* Wait for 1 vertical blank */
6636 intel_wait_for_vblank(dev, pipe);
6638 /* Set ELD valid state */
6639 tmp = I915_READ(aud_cntrl_st2);
6640 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6641 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6642 I915_WRITE(aud_cntrl_st2, tmp);
6643 tmp = I915_READ(aud_cntrl_st2);
6644 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6646 /* Enable HDMI mode */
6647 tmp = I915_READ(aud_config);
6648 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6649 /* clear N_programing_enable and N_value_index */
6650 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6651 I915_WRITE(aud_config, tmp);
6653 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6655 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6656 intel_crtc->eld_vld = true;
6658 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6659 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6660 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6661 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6663 I915_WRITE(aud_config, 0);
6665 if (intel_eld_uptodate(connector,
6666 aud_cntrl_st2, eldv,
6667 aud_cntl_st, IBX_ELD_ADDRESS,
6671 i = I915_READ(aud_cntrl_st2);
6673 I915_WRITE(aud_cntrl_st2, i);
6678 i = I915_READ(aud_cntl_st);
6679 i &= ~IBX_ELD_ADDRESS;
6680 I915_WRITE(aud_cntl_st, i);
6681 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6682 DRM_DEBUG_DRIVER("port num:%d\n", i);
6684 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6685 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6686 for (i = 0; i < len; i++)
6687 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6689 i = I915_READ(aud_cntrl_st2);
6691 I915_WRITE(aud_cntrl_st2, i);
6695 static void ironlake_write_eld(struct drm_connector *connector,
6696 struct drm_crtc *crtc)
6698 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6699 uint8_t *eld = connector->eld;
6707 int pipe = to_intel_crtc(crtc)->pipe;
6709 if (HAS_PCH_IBX(connector->dev)) {
6710 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6711 aud_config = IBX_AUD_CFG(pipe);
6712 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6713 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6715 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6716 aud_config = CPT_AUD_CFG(pipe);
6717 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6718 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6721 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6723 i = I915_READ(aud_cntl_st);
6724 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6726 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6727 /* operate blindly on all ports */
6728 eldv = IBX_ELD_VALIDB;
6729 eldv |= IBX_ELD_VALIDB << 4;
6730 eldv |= IBX_ELD_VALIDB << 8;
6732 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6733 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6736 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6737 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6738 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6739 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6741 I915_WRITE(aud_config, 0);
6743 if (intel_eld_uptodate(connector,
6744 aud_cntrl_st2, eldv,
6745 aud_cntl_st, IBX_ELD_ADDRESS,
6749 i = I915_READ(aud_cntrl_st2);
6751 I915_WRITE(aud_cntrl_st2, i);
6756 i = I915_READ(aud_cntl_st);
6757 i &= ~IBX_ELD_ADDRESS;
6758 I915_WRITE(aud_cntl_st, i);
6760 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6761 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6762 for (i = 0; i < len; i++)
6763 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6765 i = I915_READ(aud_cntrl_st2);
6767 I915_WRITE(aud_cntrl_st2, i);
6770 void intel_write_eld(struct drm_encoder *encoder,
6771 struct drm_display_mode *mode)
6773 struct drm_crtc *crtc = encoder->crtc;
6774 struct drm_connector *connector;
6775 struct drm_device *dev = encoder->dev;
6776 struct drm_i915_private *dev_priv = dev->dev_private;
6778 connector = drm_select_eld(encoder, mode);
6782 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6784 drm_get_connector_name(connector),
6785 connector->encoder->base.id,
6786 drm_get_encoder_name(connector->encoder));
6788 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6790 if (dev_priv->display.write_eld)
6791 dev_priv->display.write_eld(connector, crtc);
6794 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6795 void intel_crtc_load_lut(struct drm_crtc *crtc)
6797 struct drm_device *dev = crtc->dev;
6798 struct drm_i915_private *dev_priv = dev->dev_private;
6799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6800 enum pipe pipe = intel_crtc->pipe;
6801 int palreg = PALETTE(pipe);
6803 bool reenable_ips = false;
6805 /* The clocks have to be on to load the palette. */
6806 if (!crtc->enabled || !intel_crtc->active)
6809 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6810 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6811 assert_dsi_pll_enabled(dev_priv);
6813 assert_pll_enabled(dev_priv, pipe);
6816 /* use legacy palette for Ironlake */
6817 if (HAS_PCH_SPLIT(dev))
6818 palreg = LGC_PALETTE(pipe);
6820 /* Workaround : Do not read or write the pipe palette/gamma data while
6821 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6823 if (intel_crtc->config.ips_enabled &&
6824 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6825 GAMMA_MODE_MODE_SPLIT)) {
6826 hsw_disable_ips(intel_crtc);
6827 reenable_ips = true;
6830 for (i = 0; i < 256; i++) {
6831 I915_WRITE(palreg + 4 * i,
6832 (intel_crtc->lut_r[i] << 16) |
6833 (intel_crtc->lut_g[i] << 8) |
6834 intel_crtc->lut_b[i]);
6838 hsw_enable_ips(intel_crtc);
6841 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6843 struct drm_device *dev = crtc->dev;
6844 struct drm_i915_private *dev_priv = dev->dev_private;
6845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6846 bool visible = base != 0;
6849 if (intel_crtc->cursor_visible == visible)
6852 cntl = I915_READ(_CURACNTR);
6854 /* On these chipsets we can only modify the base whilst
6855 * the cursor is disabled.
6857 I915_WRITE(_CURABASE, base);
6859 cntl &= ~(CURSOR_FORMAT_MASK);
6860 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6861 cntl |= CURSOR_ENABLE |
6862 CURSOR_GAMMA_ENABLE |
6865 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6866 I915_WRITE(_CURACNTR, cntl);
6868 intel_crtc->cursor_visible = visible;
6871 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6873 struct drm_device *dev = crtc->dev;
6874 struct drm_i915_private *dev_priv = dev->dev_private;
6875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6876 int pipe = intel_crtc->pipe;
6877 bool visible = base != 0;
6879 if (intel_crtc->cursor_visible != visible) {
6880 uint32_t cntl = I915_READ(CURCNTR(pipe));
6882 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6883 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6884 cntl |= pipe << 28; /* Connect to correct pipe */
6886 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6887 cntl |= CURSOR_MODE_DISABLE;
6889 I915_WRITE(CURCNTR(pipe), cntl);
6891 intel_crtc->cursor_visible = visible;
6893 /* and commit changes on next vblank */
6894 I915_WRITE(CURBASE(pipe), base);
6897 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6899 struct drm_device *dev = crtc->dev;
6900 struct drm_i915_private *dev_priv = dev->dev_private;
6901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6902 int pipe = intel_crtc->pipe;
6903 bool visible = base != 0;
6905 if (intel_crtc->cursor_visible != visible) {
6906 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6908 cntl &= ~CURSOR_MODE;
6909 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6911 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6912 cntl |= CURSOR_MODE_DISABLE;
6914 if (IS_HASWELL(dev)) {
6915 cntl |= CURSOR_PIPE_CSC_ENABLE;
6916 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6918 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6920 intel_crtc->cursor_visible = visible;
6922 /* and commit changes on next vblank */
6923 I915_WRITE(CURBASE_IVB(pipe), base);
6926 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6927 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6930 struct drm_device *dev = crtc->dev;
6931 struct drm_i915_private *dev_priv = dev->dev_private;
6932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6933 int pipe = intel_crtc->pipe;
6934 int x = intel_crtc->cursor_x;
6935 int y = intel_crtc->cursor_y;
6936 u32 base = 0, pos = 0;
6940 base = intel_crtc->cursor_addr;
6942 if (x >= intel_crtc->config.pipe_src_w)
6945 if (y >= intel_crtc->config.pipe_src_h)
6949 if (x + intel_crtc->cursor_width <= 0)
6952 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6955 pos |= x << CURSOR_X_SHIFT;
6958 if (y + intel_crtc->cursor_height <= 0)
6961 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6964 pos |= y << CURSOR_Y_SHIFT;
6966 visible = base != 0;
6967 if (!visible && !intel_crtc->cursor_visible)
6970 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6971 I915_WRITE(CURPOS_IVB(pipe), pos);
6972 ivb_update_cursor(crtc, base);
6974 I915_WRITE(CURPOS(pipe), pos);
6975 if (IS_845G(dev) || IS_I865G(dev))
6976 i845_update_cursor(crtc, base);
6978 i9xx_update_cursor(crtc, base);
6982 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6983 struct drm_file *file,
6985 uint32_t width, uint32_t height)
6987 struct drm_device *dev = crtc->dev;
6988 struct drm_i915_private *dev_priv = dev->dev_private;
6989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6990 struct drm_i915_gem_object *obj;
6994 /* if we want to turn off the cursor ignore width and height */
6996 DRM_DEBUG_KMS("cursor off\n");
6999 mutex_lock(&dev->struct_mutex);
7003 /* Currently we only support 64x64 cursors */
7004 if (width != 64 || height != 64) {
7005 DRM_ERROR("we currently only support 64x64 cursors\n");
7009 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7010 if (&obj->base == NULL)
7013 if (obj->base.size < width * height * 4) {
7014 DRM_ERROR("buffer is to small\n");
7019 /* we only need to pin inside GTT if cursor is non-phy */
7020 mutex_lock(&dev->struct_mutex);
7021 if (!dev_priv->info->cursor_needs_physical) {
7024 if (obj->tiling_mode) {
7025 DRM_ERROR("cursor cannot be tiled\n");
7030 /* Note that the w/a also requires 2 PTE of padding following
7031 * the bo. We currently fill all unused PTE with the shadow
7032 * page and so we should always have valid PTE following the
7033 * cursor preventing the VT-d warning.
7036 if (need_vtd_wa(dev))
7037 alignment = 64*1024;
7039 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7041 DRM_ERROR("failed to move cursor bo into the GTT\n");
7045 ret = i915_gem_object_put_fence(obj);
7047 DRM_ERROR("failed to release fence for cursor");
7051 addr = i915_gem_obj_ggtt_offset(obj);
7053 int align = IS_I830(dev) ? 16 * 1024 : 256;
7054 ret = i915_gem_attach_phys_object(dev, obj,
7055 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7058 DRM_ERROR("failed to attach phys object\n");
7061 addr = obj->phys_obj->handle->busaddr;
7065 I915_WRITE(CURSIZE, (height << 12) | width);
7068 if (intel_crtc->cursor_bo) {
7069 if (dev_priv->info->cursor_needs_physical) {
7070 if (intel_crtc->cursor_bo != obj)
7071 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7073 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7074 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7077 mutex_unlock(&dev->struct_mutex);
7079 intel_crtc->cursor_addr = addr;
7080 intel_crtc->cursor_bo = obj;
7081 intel_crtc->cursor_width = width;
7082 intel_crtc->cursor_height = height;
7084 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7088 i915_gem_object_unpin_from_display_plane(obj);
7090 mutex_unlock(&dev->struct_mutex);
7092 drm_gem_object_unreference_unlocked(&obj->base);
7096 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7100 intel_crtc->cursor_x = x;
7101 intel_crtc->cursor_y = y;
7103 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7108 /** Sets the color ramps on behalf of RandR */
7109 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7110 u16 blue, int regno)
7112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7114 intel_crtc->lut_r[regno] = red >> 8;
7115 intel_crtc->lut_g[regno] = green >> 8;
7116 intel_crtc->lut_b[regno] = blue >> 8;
7119 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7120 u16 *blue, int regno)
7122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7124 *red = intel_crtc->lut_r[regno] << 8;
7125 *green = intel_crtc->lut_g[regno] << 8;
7126 *blue = intel_crtc->lut_b[regno] << 8;
7129 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7130 u16 *blue, uint32_t start, uint32_t size)
7132 int end = (start + size > 256) ? 256 : start + size, i;
7133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7135 for (i = start; i < end; i++) {
7136 intel_crtc->lut_r[i] = red[i] >> 8;
7137 intel_crtc->lut_g[i] = green[i] >> 8;
7138 intel_crtc->lut_b[i] = blue[i] >> 8;
7141 intel_crtc_load_lut(crtc);
7144 /* VESA 640x480x72Hz mode to set on the pipe */
7145 static struct drm_display_mode load_detect_mode = {
7146 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7147 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7150 static struct drm_framebuffer *
7151 intel_framebuffer_create(struct drm_device *dev,
7152 struct drm_mode_fb_cmd2 *mode_cmd,
7153 struct drm_i915_gem_object *obj)
7155 struct intel_framebuffer *intel_fb;
7158 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7160 drm_gem_object_unreference_unlocked(&obj->base);
7161 return ERR_PTR(-ENOMEM);
7164 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7166 drm_gem_object_unreference_unlocked(&obj->base);
7168 return ERR_PTR(ret);
7171 return &intel_fb->base;
7175 intel_framebuffer_pitch_for_width(int width, int bpp)
7177 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7178 return ALIGN(pitch, 64);
7182 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7184 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7185 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7188 static struct drm_framebuffer *
7189 intel_framebuffer_create_for_mode(struct drm_device *dev,
7190 struct drm_display_mode *mode,
7193 struct drm_i915_gem_object *obj;
7194 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7196 obj = i915_gem_alloc_object(dev,
7197 intel_framebuffer_size_for_mode(mode, bpp));
7199 return ERR_PTR(-ENOMEM);
7201 mode_cmd.width = mode->hdisplay;
7202 mode_cmd.height = mode->vdisplay;
7203 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7205 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7207 return intel_framebuffer_create(dev, &mode_cmd, obj);
7210 static struct drm_framebuffer *
7211 mode_fits_in_fbdev(struct drm_device *dev,
7212 struct drm_display_mode *mode)
7214 struct drm_i915_private *dev_priv = dev->dev_private;
7215 struct drm_i915_gem_object *obj;
7216 struct drm_framebuffer *fb;
7218 if (dev_priv->fbdev == NULL)
7221 obj = dev_priv->fbdev->ifb.obj;
7225 fb = &dev_priv->fbdev->ifb.base;
7226 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7227 fb->bits_per_pixel))
7230 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7236 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7237 struct drm_display_mode *mode,
7238 struct intel_load_detect_pipe *old)
7240 struct intel_crtc *intel_crtc;
7241 struct intel_encoder *intel_encoder =
7242 intel_attached_encoder(connector);
7243 struct drm_crtc *possible_crtc;
7244 struct drm_encoder *encoder = &intel_encoder->base;
7245 struct drm_crtc *crtc = NULL;
7246 struct drm_device *dev = encoder->dev;
7247 struct drm_framebuffer *fb;
7250 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7251 connector->base.id, drm_get_connector_name(connector),
7252 encoder->base.id, drm_get_encoder_name(encoder));
7255 * Algorithm gets a little messy:
7257 * - if the connector already has an assigned crtc, use it (but make
7258 * sure it's on first)
7260 * - try to find the first unused crtc that can drive this connector,
7261 * and use that if we find one
7264 /* See if we already have a CRTC for this connector */
7265 if (encoder->crtc) {
7266 crtc = encoder->crtc;
7268 mutex_lock(&crtc->mutex);
7270 old->dpms_mode = connector->dpms;
7271 old->load_detect_temp = false;
7273 /* Make sure the crtc and connector are running */
7274 if (connector->dpms != DRM_MODE_DPMS_ON)
7275 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7280 /* Find an unused one (if possible) */
7281 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7283 if (!(encoder->possible_crtcs & (1 << i)))
7285 if (!possible_crtc->enabled) {
7286 crtc = possible_crtc;
7292 * If we didn't find an unused CRTC, don't use any.
7295 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7299 mutex_lock(&crtc->mutex);
7300 intel_encoder->new_crtc = to_intel_crtc(crtc);
7301 to_intel_connector(connector)->new_encoder = intel_encoder;
7303 intel_crtc = to_intel_crtc(crtc);
7304 old->dpms_mode = connector->dpms;
7305 old->load_detect_temp = true;
7306 old->release_fb = NULL;
7309 mode = &load_detect_mode;
7311 /* We need a framebuffer large enough to accommodate all accesses
7312 * that the plane may generate whilst we perform load detection.
7313 * We can not rely on the fbcon either being present (we get called
7314 * during its initialisation to detect all boot displays, or it may
7315 * not even exist) or that it is large enough to satisfy the
7318 fb = mode_fits_in_fbdev(dev, mode);
7320 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7321 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7322 old->release_fb = fb;
7324 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7326 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7327 mutex_unlock(&crtc->mutex);
7331 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7332 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7333 if (old->release_fb)
7334 old->release_fb->funcs->destroy(old->release_fb);
7335 mutex_unlock(&crtc->mutex);
7339 /* let the connector get through one full cycle before testing */
7340 intel_wait_for_vblank(dev, intel_crtc->pipe);
7344 void intel_release_load_detect_pipe(struct drm_connector *connector,
7345 struct intel_load_detect_pipe *old)
7347 struct intel_encoder *intel_encoder =
7348 intel_attached_encoder(connector);
7349 struct drm_encoder *encoder = &intel_encoder->base;
7350 struct drm_crtc *crtc = encoder->crtc;
7352 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7353 connector->base.id, drm_get_connector_name(connector),
7354 encoder->base.id, drm_get_encoder_name(encoder));
7356 if (old->load_detect_temp) {
7357 to_intel_connector(connector)->new_encoder = NULL;
7358 intel_encoder->new_crtc = NULL;
7359 intel_set_mode(crtc, NULL, 0, 0, NULL);
7361 if (old->release_fb) {
7362 drm_framebuffer_unregister_private(old->release_fb);
7363 drm_framebuffer_unreference(old->release_fb);
7366 mutex_unlock(&crtc->mutex);
7370 /* Switch crtc and encoder back off if necessary */
7371 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7372 connector->funcs->dpms(connector, old->dpms_mode);
7374 mutex_unlock(&crtc->mutex);
7377 static int i9xx_pll_refclk(struct drm_device *dev,
7378 const struct intel_crtc_config *pipe_config)
7380 struct drm_i915_private *dev_priv = dev->dev_private;
7381 u32 dpll = pipe_config->dpll_hw_state.dpll;
7383 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7384 return dev_priv->vbt.lvds_ssc_freq * 1000;
7385 else if (HAS_PCH_SPLIT(dev))
7387 else if (!IS_GEN2(dev))
7393 /* Returns the clock of the currently programmed mode of the given pipe. */
7394 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7395 struct intel_crtc_config *pipe_config)
7397 struct drm_device *dev = crtc->base.dev;
7398 struct drm_i915_private *dev_priv = dev->dev_private;
7399 int pipe = pipe_config->cpu_transcoder;
7400 u32 dpll = pipe_config->dpll_hw_state.dpll;
7402 intel_clock_t clock;
7403 int refclk = i9xx_pll_refclk(dev, pipe_config);
7405 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7406 fp = pipe_config->dpll_hw_state.fp0;
7408 fp = pipe_config->dpll_hw_state.fp1;
7410 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7411 if (IS_PINEVIEW(dev)) {
7412 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7413 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7415 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7416 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7419 if (!IS_GEN2(dev)) {
7420 if (IS_PINEVIEW(dev))
7421 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7422 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7424 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7425 DPLL_FPA01_P1_POST_DIV_SHIFT);
7427 switch (dpll & DPLL_MODE_MASK) {
7428 case DPLLB_MODE_DAC_SERIAL:
7429 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7432 case DPLLB_MODE_LVDS:
7433 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7437 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7438 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7442 if (IS_PINEVIEW(dev))
7443 pineview_clock(refclk, &clock);
7445 i9xx_clock(refclk, &clock);
7447 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7450 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7451 DPLL_FPA01_P1_POST_DIV_SHIFT);
7454 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7457 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7458 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7460 if (dpll & PLL_P2_DIVIDE_BY_4)
7466 i9xx_clock(refclk, &clock);
7470 * This value includes pixel_multiplier. We will use
7471 * port_clock to compute adjusted_mode.clock in the
7472 * encoder's get_config() function.
7474 pipe_config->port_clock = clock.dot;
7477 int intel_dotclock_calculate(int link_freq,
7478 const struct intel_link_m_n *m_n)
7481 * The calculation for the data clock is:
7482 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7483 * But we want to avoid losing precison if possible, so:
7484 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7486 * and the link clock is simpler:
7487 * link_clock = (m * link_clock) / n
7493 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7496 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7497 struct intel_crtc_config *pipe_config)
7499 struct drm_device *dev = crtc->base.dev;
7501 /* read out port_clock from the DPLL */
7502 i9xx_crtc_clock_get(crtc, pipe_config);
7505 * This value does not include pixel_multiplier.
7506 * We will check that port_clock and adjusted_mode.clock
7507 * agree once we know their relationship in the encoder's
7508 * get_config() function.
7510 pipe_config->adjusted_mode.clock =
7511 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7512 &pipe_config->fdi_m_n);
7515 /** Returns the currently programmed mode of the given pipe. */
7516 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7517 struct drm_crtc *crtc)
7519 struct drm_i915_private *dev_priv = dev->dev_private;
7520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7521 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7522 struct drm_display_mode *mode;
7523 struct intel_crtc_config pipe_config;
7524 int htot = I915_READ(HTOTAL(cpu_transcoder));
7525 int hsync = I915_READ(HSYNC(cpu_transcoder));
7526 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7527 int vsync = I915_READ(VSYNC(cpu_transcoder));
7528 enum pipe pipe = intel_crtc->pipe;
7530 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7535 * Construct a pipe_config sufficient for getting the clock info
7536 * back out of crtc_clock_get.
7538 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7539 * to use a real value here instead.
7541 pipe_config.cpu_transcoder = (enum transcoder) pipe;
7542 pipe_config.pixel_multiplier = 1;
7543 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7544 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7545 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7546 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7548 mode->clock = pipe_config.adjusted_mode.clock;
7549 mode->hdisplay = (htot & 0xffff) + 1;
7550 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7551 mode->hsync_start = (hsync & 0xffff) + 1;
7552 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7553 mode->vdisplay = (vtot & 0xffff) + 1;
7554 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7555 mode->vsync_start = (vsync & 0xffff) + 1;
7556 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7558 drm_mode_set_name(mode);
7563 static void intel_increase_pllclock(struct drm_crtc *crtc)
7565 struct drm_device *dev = crtc->dev;
7566 drm_i915_private_t *dev_priv = dev->dev_private;
7567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7568 int pipe = intel_crtc->pipe;
7569 int dpll_reg = DPLL(pipe);
7572 if (HAS_PCH_SPLIT(dev))
7575 if (!dev_priv->lvds_downclock_avail)
7578 dpll = I915_READ(dpll_reg);
7579 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7580 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7582 assert_panel_unlocked(dev_priv, pipe);
7584 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7585 I915_WRITE(dpll_reg, dpll);
7586 intel_wait_for_vblank(dev, pipe);
7588 dpll = I915_READ(dpll_reg);
7589 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7590 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7594 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7596 struct drm_device *dev = crtc->dev;
7597 drm_i915_private_t *dev_priv = dev->dev_private;
7598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7600 if (HAS_PCH_SPLIT(dev))
7603 if (!dev_priv->lvds_downclock_avail)
7607 * Since this is called by a timer, we should never get here in
7610 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7611 int pipe = intel_crtc->pipe;
7612 int dpll_reg = DPLL(pipe);
7615 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7617 assert_panel_unlocked(dev_priv, pipe);
7619 dpll = I915_READ(dpll_reg);
7620 dpll |= DISPLAY_RATE_SELECT_FPA1;
7621 I915_WRITE(dpll_reg, dpll);
7622 intel_wait_for_vblank(dev, pipe);
7623 dpll = I915_READ(dpll_reg);
7624 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7625 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7630 void intel_mark_busy(struct drm_device *dev)
7632 struct drm_i915_private *dev_priv = dev->dev_private;
7634 hsw_package_c8_gpu_busy(dev_priv);
7635 i915_update_gfx_val(dev_priv);
7638 void intel_mark_idle(struct drm_device *dev)
7640 struct drm_i915_private *dev_priv = dev->dev_private;
7641 struct drm_crtc *crtc;
7643 hsw_package_c8_gpu_idle(dev_priv);
7645 if (!i915_powersave)
7648 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7652 intel_decrease_pllclock(crtc);
7656 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7657 struct intel_ring_buffer *ring)
7659 struct drm_device *dev = obj->base.dev;
7660 struct drm_crtc *crtc;
7662 if (!i915_powersave)
7665 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7669 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7672 intel_increase_pllclock(crtc);
7673 if (ring && intel_fbc_enabled(dev))
7674 ring->fbc_dirty = true;
7678 static void intel_crtc_destroy(struct drm_crtc *crtc)
7680 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7681 struct drm_device *dev = crtc->dev;
7682 struct intel_unpin_work *work;
7683 unsigned long flags;
7685 spin_lock_irqsave(&dev->event_lock, flags);
7686 work = intel_crtc->unpin_work;
7687 intel_crtc->unpin_work = NULL;
7688 spin_unlock_irqrestore(&dev->event_lock, flags);
7691 cancel_work_sync(&work->work);
7695 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7697 drm_crtc_cleanup(crtc);
7702 static void intel_unpin_work_fn(struct work_struct *__work)
7704 struct intel_unpin_work *work =
7705 container_of(__work, struct intel_unpin_work, work);
7706 struct drm_device *dev = work->crtc->dev;
7708 mutex_lock(&dev->struct_mutex);
7709 intel_unpin_fb_obj(work->old_fb_obj);
7710 drm_gem_object_unreference(&work->pending_flip_obj->base);
7711 drm_gem_object_unreference(&work->old_fb_obj->base);
7713 intel_update_fbc(dev);
7714 mutex_unlock(&dev->struct_mutex);
7716 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7717 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7722 static void do_intel_finish_page_flip(struct drm_device *dev,
7723 struct drm_crtc *crtc)
7725 drm_i915_private_t *dev_priv = dev->dev_private;
7726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7727 struct intel_unpin_work *work;
7728 unsigned long flags;
7730 /* Ignore early vblank irqs */
7731 if (intel_crtc == NULL)
7734 spin_lock_irqsave(&dev->event_lock, flags);
7735 work = intel_crtc->unpin_work;
7737 /* Ensure we don't miss a work->pending update ... */
7740 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7741 spin_unlock_irqrestore(&dev->event_lock, flags);
7745 /* and that the unpin work is consistent wrt ->pending. */
7748 intel_crtc->unpin_work = NULL;
7751 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7753 drm_vblank_put(dev, intel_crtc->pipe);
7755 spin_unlock_irqrestore(&dev->event_lock, flags);
7757 wake_up_all(&dev_priv->pending_flip_queue);
7759 queue_work(dev_priv->wq, &work->work);
7761 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7764 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7766 drm_i915_private_t *dev_priv = dev->dev_private;
7767 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7769 do_intel_finish_page_flip(dev, crtc);
7772 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7774 drm_i915_private_t *dev_priv = dev->dev_private;
7775 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7777 do_intel_finish_page_flip(dev, crtc);
7780 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7782 drm_i915_private_t *dev_priv = dev->dev_private;
7783 struct intel_crtc *intel_crtc =
7784 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7785 unsigned long flags;
7787 /* NB: An MMIO update of the plane base pointer will also
7788 * generate a page-flip completion irq, i.e. every modeset
7789 * is also accompanied by a spurious intel_prepare_page_flip().
7791 spin_lock_irqsave(&dev->event_lock, flags);
7792 if (intel_crtc->unpin_work)
7793 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7794 spin_unlock_irqrestore(&dev->event_lock, flags);
7797 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7799 /* Ensure that the work item is consistent when activating it ... */
7801 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7802 /* and that it is marked active as soon as the irq could fire. */
7806 static int intel_gen2_queue_flip(struct drm_device *dev,
7807 struct drm_crtc *crtc,
7808 struct drm_framebuffer *fb,
7809 struct drm_i915_gem_object *obj,
7812 struct drm_i915_private *dev_priv = dev->dev_private;
7813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7815 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7818 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7822 ret = intel_ring_begin(ring, 6);
7826 /* Can't queue multiple flips, so wait for the previous
7827 * one to finish before executing the next.
7829 if (intel_crtc->plane)
7830 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7832 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7833 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7834 intel_ring_emit(ring, MI_NOOP);
7835 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7836 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7837 intel_ring_emit(ring, fb->pitches[0]);
7838 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7839 intel_ring_emit(ring, 0); /* aux display base address, unused */
7841 intel_mark_page_flip_active(intel_crtc);
7842 __intel_ring_advance(ring);
7846 intel_unpin_fb_obj(obj);
7851 static int intel_gen3_queue_flip(struct drm_device *dev,
7852 struct drm_crtc *crtc,
7853 struct drm_framebuffer *fb,
7854 struct drm_i915_gem_object *obj,
7857 struct drm_i915_private *dev_priv = dev->dev_private;
7858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7860 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7863 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7867 ret = intel_ring_begin(ring, 6);
7871 if (intel_crtc->plane)
7872 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7874 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7875 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7876 intel_ring_emit(ring, MI_NOOP);
7877 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7878 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7879 intel_ring_emit(ring, fb->pitches[0]);
7880 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7881 intel_ring_emit(ring, MI_NOOP);
7883 intel_mark_page_flip_active(intel_crtc);
7884 __intel_ring_advance(ring);
7888 intel_unpin_fb_obj(obj);
7893 static int intel_gen4_queue_flip(struct drm_device *dev,
7894 struct drm_crtc *crtc,
7895 struct drm_framebuffer *fb,
7896 struct drm_i915_gem_object *obj,
7899 struct drm_i915_private *dev_priv = dev->dev_private;
7900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7901 uint32_t pf, pipesrc;
7902 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7905 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7909 ret = intel_ring_begin(ring, 4);
7913 /* i965+ uses the linear or tiled offsets from the
7914 * Display Registers (which do not change across a page-flip)
7915 * so we need only reprogram the base address.
7917 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7918 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7919 intel_ring_emit(ring, fb->pitches[0]);
7920 intel_ring_emit(ring,
7921 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7924 /* XXX Enabling the panel-fitter across page-flip is so far
7925 * untested on non-native modes, so ignore it for now.
7926 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7929 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7930 intel_ring_emit(ring, pf | pipesrc);
7932 intel_mark_page_flip_active(intel_crtc);
7933 __intel_ring_advance(ring);
7937 intel_unpin_fb_obj(obj);
7942 static int intel_gen6_queue_flip(struct drm_device *dev,
7943 struct drm_crtc *crtc,
7944 struct drm_framebuffer *fb,
7945 struct drm_i915_gem_object *obj,
7948 struct drm_i915_private *dev_priv = dev->dev_private;
7949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7950 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7951 uint32_t pf, pipesrc;
7954 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7958 ret = intel_ring_begin(ring, 4);
7962 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7963 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7964 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7965 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7967 /* Contrary to the suggestions in the documentation,
7968 * "Enable Panel Fitter" does not seem to be required when page
7969 * flipping with a non-native mode, and worse causes a normal
7971 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7974 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7975 intel_ring_emit(ring, pf | pipesrc);
7977 intel_mark_page_flip_active(intel_crtc);
7978 __intel_ring_advance(ring);
7982 intel_unpin_fb_obj(obj);
7987 static int intel_gen7_queue_flip(struct drm_device *dev,
7988 struct drm_crtc *crtc,
7989 struct drm_framebuffer *fb,
7990 struct drm_i915_gem_object *obj,
7993 struct drm_i915_private *dev_priv = dev->dev_private;
7994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7995 struct intel_ring_buffer *ring;
7996 uint32_t plane_bit = 0;
8000 if (ring == NULL || ring->id != RCS)
8001 ring = &dev_priv->ring[BCS];
8003 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8007 switch(intel_crtc->plane) {
8009 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8012 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8015 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8018 WARN_ONCE(1, "unknown plane in flip command\n");
8024 if (ring->id == RCS)
8027 ret = intel_ring_begin(ring, len);
8031 /* Unmask the flip-done completion message. Note that the bspec says that
8032 * we should do this for both the BCS and RCS, and that we must not unmask
8033 * more than one flip event at any time (or ensure that one flip message
8034 * can be sent by waiting for flip-done prior to queueing new flips).
8035 * Experimentation says that BCS works despite DERRMR masking all
8036 * flip-done completion events and that unmasking all planes at once
8037 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8038 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8040 if (ring->id == RCS) {
8041 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8042 intel_ring_emit(ring, DERRMR);
8043 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8044 DERRMR_PIPEB_PRI_FLIP_DONE |
8045 DERRMR_PIPEC_PRI_FLIP_DONE));
8046 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8047 intel_ring_emit(ring, DERRMR);
8048 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8051 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8052 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8053 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8054 intel_ring_emit(ring, (MI_NOOP));
8056 intel_mark_page_flip_active(intel_crtc);
8057 __intel_ring_advance(ring);
8061 intel_unpin_fb_obj(obj);
8066 static int intel_default_queue_flip(struct drm_device *dev,
8067 struct drm_crtc *crtc,
8068 struct drm_framebuffer *fb,
8069 struct drm_i915_gem_object *obj,
8075 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8076 struct drm_framebuffer *fb,
8077 struct drm_pending_vblank_event *event,
8078 uint32_t page_flip_flags)
8080 struct drm_device *dev = crtc->dev;
8081 struct drm_i915_private *dev_priv = dev->dev_private;
8082 struct drm_framebuffer *old_fb = crtc->fb;
8083 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8085 struct intel_unpin_work *work;
8086 unsigned long flags;
8089 /* Can't change pixel format via MI display flips. */
8090 if (fb->pixel_format != crtc->fb->pixel_format)
8094 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8095 * Note that pitch changes could also affect these register.
8097 if (INTEL_INFO(dev)->gen > 3 &&
8098 (fb->offsets[0] != crtc->fb->offsets[0] ||
8099 fb->pitches[0] != crtc->fb->pitches[0]))
8102 work = kzalloc(sizeof *work, GFP_KERNEL);
8106 work->event = event;
8108 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8109 INIT_WORK(&work->work, intel_unpin_work_fn);
8111 ret = drm_vblank_get(dev, intel_crtc->pipe);
8115 /* We borrow the event spin lock for protecting unpin_work */
8116 spin_lock_irqsave(&dev->event_lock, flags);
8117 if (intel_crtc->unpin_work) {
8118 spin_unlock_irqrestore(&dev->event_lock, flags);
8120 drm_vblank_put(dev, intel_crtc->pipe);
8122 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8125 intel_crtc->unpin_work = work;
8126 spin_unlock_irqrestore(&dev->event_lock, flags);
8128 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8129 flush_workqueue(dev_priv->wq);
8131 ret = i915_mutex_lock_interruptible(dev);
8135 /* Reference the objects for the scheduled work. */
8136 drm_gem_object_reference(&work->old_fb_obj->base);
8137 drm_gem_object_reference(&obj->base);
8141 work->pending_flip_obj = obj;
8143 work->enable_stall_check = true;
8145 atomic_inc(&intel_crtc->unpin_work_count);
8146 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8148 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8150 goto cleanup_pending;
8152 intel_disable_fbc(dev);
8153 intel_mark_fb_busy(obj, NULL);
8154 mutex_unlock(&dev->struct_mutex);
8156 trace_i915_flip_request(intel_crtc->plane, obj);
8161 atomic_dec(&intel_crtc->unpin_work_count);
8163 drm_gem_object_unreference(&work->old_fb_obj->base);
8164 drm_gem_object_unreference(&obj->base);
8165 mutex_unlock(&dev->struct_mutex);
8168 spin_lock_irqsave(&dev->event_lock, flags);
8169 intel_crtc->unpin_work = NULL;
8170 spin_unlock_irqrestore(&dev->event_lock, flags);
8172 drm_vblank_put(dev, intel_crtc->pipe);
8179 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8180 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8181 .load_lut = intel_crtc_load_lut,
8184 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8185 struct drm_crtc *crtc)
8187 struct drm_device *dev;
8188 struct drm_crtc *tmp;
8191 WARN(!crtc, "checking null crtc?\n");
8195 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8201 if (encoder->possible_crtcs & crtc_mask)
8207 * intel_modeset_update_staged_output_state
8209 * Updates the staged output configuration state, e.g. after we've read out the
8212 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8214 struct intel_encoder *encoder;
8215 struct intel_connector *connector;
8217 list_for_each_entry(connector, &dev->mode_config.connector_list,
8219 connector->new_encoder =
8220 to_intel_encoder(connector->base.encoder);
8223 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8226 to_intel_crtc(encoder->base.crtc);
8231 * intel_modeset_commit_output_state
8233 * This function copies the stage display pipe configuration to the real one.
8235 static void intel_modeset_commit_output_state(struct drm_device *dev)
8237 struct intel_encoder *encoder;
8238 struct intel_connector *connector;
8240 list_for_each_entry(connector, &dev->mode_config.connector_list,
8242 connector->base.encoder = &connector->new_encoder->base;
8245 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8247 encoder->base.crtc = &encoder->new_crtc->base;
8252 connected_sink_compute_bpp(struct intel_connector * connector,
8253 struct intel_crtc_config *pipe_config)
8255 int bpp = pipe_config->pipe_bpp;
8257 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8258 connector->base.base.id,
8259 drm_get_connector_name(&connector->base));
8261 /* Don't use an invalid EDID bpc value */
8262 if (connector->base.display_info.bpc &&
8263 connector->base.display_info.bpc * 3 < bpp) {
8264 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8265 bpp, connector->base.display_info.bpc*3);
8266 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8269 /* Clamp bpp to 8 on screens without EDID 1.4 */
8270 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8271 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8273 pipe_config->pipe_bpp = 24;
8278 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8279 struct drm_framebuffer *fb,
8280 struct intel_crtc_config *pipe_config)
8282 struct drm_device *dev = crtc->base.dev;
8283 struct intel_connector *connector;
8286 switch (fb->pixel_format) {
8288 bpp = 8*3; /* since we go through a colormap */
8290 case DRM_FORMAT_XRGB1555:
8291 case DRM_FORMAT_ARGB1555:
8292 /* checked in intel_framebuffer_init already */
8293 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8295 case DRM_FORMAT_RGB565:
8296 bpp = 6*3; /* min is 18bpp */
8298 case DRM_FORMAT_XBGR8888:
8299 case DRM_FORMAT_ABGR8888:
8300 /* checked in intel_framebuffer_init already */
8301 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8303 case DRM_FORMAT_XRGB8888:
8304 case DRM_FORMAT_ARGB8888:
8307 case DRM_FORMAT_XRGB2101010:
8308 case DRM_FORMAT_ARGB2101010:
8309 case DRM_FORMAT_XBGR2101010:
8310 case DRM_FORMAT_ABGR2101010:
8311 /* checked in intel_framebuffer_init already */
8312 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8316 /* TODO: gen4+ supports 16 bpc floating point, too. */
8318 DRM_DEBUG_KMS("unsupported depth\n");
8322 pipe_config->pipe_bpp = bpp;
8324 /* Clamp display bpp to EDID value */
8325 list_for_each_entry(connector, &dev->mode_config.connector_list,
8327 if (!connector->new_encoder ||
8328 connector->new_encoder->new_crtc != crtc)
8331 connected_sink_compute_bpp(connector, pipe_config);
8337 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8339 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8340 "type: 0x%x flags: 0x%x\n",
8342 mode->crtc_hdisplay, mode->crtc_hsync_start,
8343 mode->crtc_hsync_end, mode->crtc_htotal,
8344 mode->crtc_vdisplay, mode->crtc_vsync_start,
8345 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8348 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8349 struct intel_crtc_config *pipe_config,
8350 const char *context)
8352 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8353 context, pipe_name(crtc->pipe));
8355 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8356 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8357 pipe_config->pipe_bpp, pipe_config->dither);
8358 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8359 pipe_config->has_pch_encoder,
8360 pipe_config->fdi_lanes,
8361 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8362 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8363 pipe_config->fdi_m_n.tu);
8364 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8365 pipe_config->has_dp_encoder,
8366 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8367 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8368 pipe_config->dp_m_n.tu);
8369 DRM_DEBUG_KMS("requested mode:\n");
8370 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8371 DRM_DEBUG_KMS("adjusted mode:\n");
8372 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8373 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8374 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8375 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8376 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8377 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8378 pipe_config->gmch_pfit.control,
8379 pipe_config->gmch_pfit.pgm_ratios,
8380 pipe_config->gmch_pfit.lvds_border_bits);
8381 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8382 pipe_config->pch_pfit.pos,
8383 pipe_config->pch_pfit.size);
8384 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8385 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8388 static bool check_encoder_cloning(struct drm_crtc *crtc)
8390 int num_encoders = 0;
8391 bool uncloneable_encoders = false;
8392 struct intel_encoder *encoder;
8394 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8396 if (&encoder->new_crtc->base != crtc)
8400 if (!encoder->cloneable)
8401 uncloneable_encoders = true;
8404 return !(num_encoders > 1 && uncloneable_encoders);
8407 static struct intel_crtc_config *
8408 intel_modeset_pipe_config(struct drm_crtc *crtc,
8409 struct drm_framebuffer *fb,
8410 struct drm_display_mode *mode)
8412 struct drm_device *dev = crtc->dev;
8413 struct intel_encoder *encoder;
8414 struct intel_crtc_config *pipe_config;
8415 int plane_bpp, ret = -EINVAL;
8418 if (!check_encoder_cloning(crtc)) {
8419 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8420 return ERR_PTR(-EINVAL);
8423 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8425 return ERR_PTR(-ENOMEM);
8427 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8428 drm_mode_copy(&pipe_config->requested_mode, mode);
8430 pipe_config->pipe_src_w = mode->hdisplay;
8431 pipe_config->pipe_src_h = mode->vdisplay;
8433 pipe_config->cpu_transcoder =
8434 (enum transcoder) to_intel_crtc(crtc)->pipe;
8435 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8438 * Sanitize sync polarity flags based on requested ones. If neither
8439 * positive or negative polarity is requested, treat this as meaning
8440 * negative polarity.
8442 if (!(pipe_config->adjusted_mode.flags &
8443 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8444 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8446 if (!(pipe_config->adjusted_mode.flags &
8447 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8448 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8450 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8451 * plane pixel format and any sink constraints into account. Returns the
8452 * source plane bpp so that dithering can be selected on mismatches
8453 * after encoders and crtc also have had their say. */
8454 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8460 /* Ensure the port clock defaults are reset when retrying. */
8461 pipe_config->port_clock = 0;
8462 pipe_config->pixel_multiplier = 1;
8464 /* Fill in default crtc timings, allow encoders to overwrite them. */
8465 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8467 /* Pass our mode to the connectors and the CRTC to give them a chance to
8468 * adjust it according to limitations or connector properties, and also
8469 * a chance to reject the mode entirely.
8471 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8474 if (&encoder->new_crtc->base != crtc)
8477 if (!(encoder->compute_config(encoder, pipe_config))) {
8478 DRM_DEBUG_KMS("Encoder config failure\n");
8483 /* Set default port clock if not overwritten by the encoder. Needs to be
8484 * done afterwards in case the encoder adjusts the mode. */
8485 if (!pipe_config->port_clock)
8486 pipe_config->port_clock = pipe_config->adjusted_mode.clock *
8487 pipe_config->pixel_multiplier;
8489 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8491 DRM_DEBUG_KMS("CRTC fixup failed\n");
8496 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8501 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8506 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8507 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8508 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8513 return ERR_PTR(ret);
8516 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8517 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8519 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8520 unsigned *prepare_pipes, unsigned *disable_pipes)
8522 struct intel_crtc *intel_crtc;
8523 struct drm_device *dev = crtc->dev;
8524 struct intel_encoder *encoder;
8525 struct intel_connector *connector;
8526 struct drm_crtc *tmp_crtc;
8528 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8530 /* Check which crtcs have changed outputs connected to them, these need
8531 * to be part of the prepare_pipes mask. We don't (yet) support global
8532 * modeset across multiple crtcs, so modeset_pipes will only have one
8533 * bit set at most. */
8534 list_for_each_entry(connector, &dev->mode_config.connector_list,
8536 if (connector->base.encoder == &connector->new_encoder->base)
8539 if (connector->base.encoder) {
8540 tmp_crtc = connector->base.encoder->crtc;
8542 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8545 if (connector->new_encoder)
8547 1 << connector->new_encoder->new_crtc->pipe;
8550 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8552 if (encoder->base.crtc == &encoder->new_crtc->base)
8555 if (encoder->base.crtc) {
8556 tmp_crtc = encoder->base.crtc;
8558 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8561 if (encoder->new_crtc)
8562 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8565 /* Check for any pipes that will be fully disabled ... */
8566 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8570 /* Don't try to disable disabled crtcs. */
8571 if (!intel_crtc->base.enabled)
8574 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8576 if (encoder->new_crtc == intel_crtc)
8581 *disable_pipes |= 1 << intel_crtc->pipe;
8585 /* set_mode is also used to update properties on life display pipes. */
8586 intel_crtc = to_intel_crtc(crtc);
8588 *prepare_pipes |= 1 << intel_crtc->pipe;
8591 * For simplicity do a full modeset on any pipe where the output routing
8592 * changed. We could be more clever, but that would require us to be
8593 * more careful with calling the relevant encoder->mode_set functions.
8596 *modeset_pipes = *prepare_pipes;
8598 /* ... and mask these out. */
8599 *modeset_pipes &= ~(*disable_pipes);
8600 *prepare_pipes &= ~(*disable_pipes);
8603 * HACK: We don't (yet) fully support global modesets. intel_set_config
8604 * obies this rule, but the modeset restore mode of
8605 * intel_modeset_setup_hw_state does not.
8607 *modeset_pipes &= 1 << intel_crtc->pipe;
8608 *prepare_pipes &= 1 << intel_crtc->pipe;
8610 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8611 *modeset_pipes, *prepare_pipes, *disable_pipes);
8614 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8616 struct drm_encoder *encoder;
8617 struct drm_device *dev = crtc->dev;
8619 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8620 if (encoder->crtc == crtc)
8627 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8629 struct intel_encoder *intel_encoder;
8630 struct intel_crtc *intel_crtc;
8631 struct drm_connector *connector;
8633 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8635 if (!intel_encoder->base.crtc)
8638 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8640 if (prepare_pipes & (1 << intel_crtc->pipe))
8641 intel_encoder->connectors_active = false;
8644 intel_modeset_commit_output_state(dev);
8646 /* Update computed state. */
8647 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8649 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8652 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8653 if (!connector->encoder || !connector->encoder->crtc)
8656 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8658 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8659 struct drm_property *dpms_property =
8660 dev->mode_config.dpms_property;
8662 connector->dpms = DRM_MODE_DPMS_ON;
8663 drm_object_property_set_value(&connector->base,
8667 intel_encoder = to_intel_encoder(connector->encoder);
8668 intel_encoder->connectors_active = true;
8674 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8678 if (clock1 == clock2)
8681 if (!clock1 || !clock2)
8684 diff = abs(clock1 - clock2);
8686 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8692 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8693 list_for_each_entry((intel_crtc), \
8694 &(dev)->mode_config.crtc_list, \
8696 if (mask & (1 <<(intel_crtc)->pipe))
8699 intel_pipe_config_compare(struct drm_device *dev,
8700 struct intel_crtc_config *current_config,
8701 struct intel_crtc_config *pipe_config)
8703 #define PIPE_CONF_CHECK_X(name) \
8704 if (current_config->name != pipe_config->name) { \
8705 DRM_ERROR("mismatch in " #name " " \
8706 "(expected 0x%08x, found 0x%08x)\n", \
8707 current_config->name, \
8708 pipe_config->name); \
8712 #define PIPE_CONF_CHECK_I(name) \
8713 if (current_config->name != pipe_config->name) { \
8714 DRM_ERROR("mismatch in " #name " " \
8715 "(expected %i, found %i)\n", \
8716 current_config->name, \
8717 pipe_config->name); \
8721 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8722 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8723 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8724 "(expected %i, found %i)\n", \
8725 current_config->name & (mask), \
8726 pipe_config->name & (mask)); \
8730 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8731 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8732 DRM_ERROR("mismatch in " #name " " \
8733 "(expected %i, found %i)\n", \
8734 current_config->name, \
8735 pipe_config->name); \
8739 #define PIPE_CONF_QUIRK(quirk) \
8740 ((current_config->quirks | pipe_config->quirks) & (quirk))
8742 PIPE_CONF_CHECK_I(cpu_transcoder);
8744 PIPE_CONF_CHECK_I(has_pch_encoder);
8745 PIPE_CONF_CHECK_I(fdi_lanes);
8746 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8747 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8748 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8749 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8750 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8752 PIPE_CONF_CHECK_I(has_dp_encoder);
8753 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8754 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8755 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8756 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8757 PIPE_CONF_CHECK_I(dp_m_n.tu);
8759 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8760 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8761 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8762 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8763 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8764 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8766 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8767 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8768 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8769 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8770 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8771 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8773 PIPE_CONF_CHECK_I(pixel_multiplier);
8775 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8776 DRM_MODE_FLAG_INTERLACE);
8778 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8779 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8780 DRM_MODE_FLAG_PHSYNC);
8781 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8782 DRM_MODE_FLAG_NHSYNC);
8783 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8784 DRM_MODE_FLAG_PVSYNC);
8785 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8786 DRM_MODE_FLAG_NVSYNC);
8789 PIPE_CONF_CHECK_I(pipe_src_w);
8790 PIPE_CONF_CHECK_I(pipe_src_h);
8792 PIPE_CONF_CHECK_I(gmch_pfit.control);
8793 /* pfit ratios are autocomputed by the hw on gen4+ */
8794 if (INTEL_INFO(dev)->gen < 4)
8795 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8796 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8797 PIPE_CONF_CHECK_I(pch_pfit.pos);
8798 PIPE_CONF_CHECK_I(pch_pfit.size);
8800 PIPE_CONF_CHECK_I(ips_enabled);
8802 PIPE_CONF_CHECK_I(double_wide);
8804 PIPE_CONF_CHECK_I(shared_dpll);
8805 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8806 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8807 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8808 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8810 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8811 PIPE_CONF_CHECK_I(pipe_bpp);
8813 if (!IS_HASWELL(dev)) {
8814 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock);
8815 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8818 #undef PIPE_CONF_CHECK_X
8819 #undef PIPE_CONF_CHECK_I
8820 #undef PIPE_CONF_CHECK_FLAGS
8821 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8822 #undef PIPE_CONF_QUIRK
8828 check_connector_state(struct drm_device *dev)
8830 struct intel_connector *connector;
8832 list_for_each_entry(connector, &dev->mode_config.connector_list,
8834 /* This also checks the encoder/connector hw state with the
8835 * ->get_hw_state callbacks. */
8836 intel_connector_check_state(connector);
8838 WARN(&connector->new_encoder->base != connector->base.encoder,
8839 "connector's staged encoder doesn't match current encoder\n");
8844 check_encoder_state(struct drm_device *dev)
8846 struct intel_encoder *encoder;
8847 struct intel_connector *connector;
8849 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8851 bool enabled = false;
8852 bool active = false;
8853 enum pipe pipe, tracked_pipe;
8855 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8856 encoder->base.base.id,
8857 drm_get_encoder_name(&encoder->base));
8859 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8860 "encoder's stage crtc doesn't match current crtc\n");
8861 WARN(encoder->connectors_active && !encoder->base.crtc,
8862 "encoder's active_connectors set, but no crtc\n");
8864 list_for_each_entry(connector, &dev->mode_config.connector_list,
8866 if (connector->base.encoder != &encoder->base)
8869 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8872 WARN(!!encoder->base.crtc != enabled,
8873 "encoder's enabled state mismatch "
8874 "(expected %i, found %i)\n",
8875 !!encoder->base.crtc, enabled);
8876 WARN(active && !encoder->base.crtc,
8877 "active encoder with no crtc\n");
8879 WARN(encoder->connectors_active != active,
8880 "encoder's computed active state doesn't match tracked active state "
8881 "(expected %i, found %i)\n", active, encoder->connectors_active);
8883 active = encoder->get_hw_state(encoder, &pipe);
8884 WARN(active != encoder->connectors_active,
8885 "encoder's hw state doesn't match sw tracking "
8886 "(expected %i, found %i)\n",
8887 encoder->connectors_active, active);
8889 if (!encoder->base.crtc)
8892 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8893 WARN(active && pipe != tracked_pipe,
8894 "active encoder's pipe doesn't match"
8895 "(expected %i, found %i)\n",
8896 tracked_pipe, pipe);
8902 check_crtc_state(struct drm_device *dev)
8904 drm_i915_private_t *dev_priv = dev->dev_private;
8905 struct intel_crtc *crtc;
8906 struct intel_encoder *encoder;
8907 struct intel_crtc_config pipe_config;
8909 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8911 bool enabled = false;
8912 bool active = false;
8914 memset(&pipe_config, 0, sizeof(pipe_config));
8916 DRM_DEBUG_KMS("[CRTC:%d]\n",
8917 crtc->base.base.id);
8919 WARN(crtc->active && !crtc->base.enabled,
8920 "active crtc, but not enabled in sw tracking\n");
8922 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8924 if (encoder->base.crtc != &crtc->base)
8927 if (encoder->connectors_active)
8931 WARN(active != crtc->active,
8932 "crtc's computed active state doesn't match tracked active state "
8933 "(expected %i, found %i)\n", active, crtc->active);
8934 WARN(enabled != crtc->base.enabled,
8935 "crtc's computed enabled state doesn't match tracked enabled state "
8936 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8938 active = dev_priv->display.get_pipe_config(crtc,
8941 /* hw state is inconsistent with the pipe A quirk */
8942 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8943 active = crtc->active;
8945 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8948 if (encoder->base.crtc != &crtc->base)
8950 if (encoder->get_config &&
8951 encoder->get_hw_state(encoder, &pipe))
8952 encoder->get_config(encoder, &pipe_config);
8955 WARN(crtc->active != active,
8956 "crtc active state doesn't match with hw state "
8957 "(expected %i, found %i)\n", crtc->active, active);
8960 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8961 WARN(1, "pipe state doesn't match!\n");
8962 intel_dump_pipe_config(crtc, &pipe_config,
8964 intel_dump_pipe_config(crtc, &crtc->config,
8971 check_shared_dpll_state(struct drm_device *dev)
8973 drm_i915_private_t *dev_priv = dev->dev_private;
8974 struct intel_crtc *crtc;
8975 struct intel_dpll_hw_state dpll_hw_state;
8978 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8979 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8980 int enabled_crtcs = 0, active_crtcs = 0;
8983 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8985 DRM_DEBUG_KMS("%s\n", pll->name);
8987 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8989 WARN(pll->active > pll->refcount,
8990 "more active pll users than references: %i vs %i\n",
8991 pll->active, pll->refcount);
8992 WARN(pll->active && !pll->on,
8993 "pll in active use but not on in sw tracking\n");
8994 WARN(pll->on && !pll->active,
8995 "pll in on but not on in use in sw tracking\n");
8996 WARN(pll->on != active,
8997 "pll on state mismatch (expected %i, found %i)\n",
9000 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9002 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9004 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9007 WARN(pll->active != active_crtcs,
9008 "pll active crtcs mismatch (expected %i, found %i)\n",
9009 pll->active, active_crtcs);
9010 WARN(pll->refcount != enabled_crtcs,
9011 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9012 pll->refcount, enabled_crtcs);
9014 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9015 sizeof(dpll_hw_state)),
9016 "pll hw state mismatch\n");
9021 intel_modeset_check_state(struct drm_device *dev)
9023 check_connector_state(dev);
9024 check_encoder_state(dev);
9025 check_crtc_state(dev);
9026 check_shared_dpll_state(dev);
9029 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9033 * FDI already provided one idea for the dotclock.
9034 * Yell if the encoder disagrees.
9036 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.clock, dotclock),
9037 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9038 pipe_config->adjusted_mode.clock, dotclock);
9041 static int __intel_set_mode(struct drm_crtc *crtc,
9042 struct drm_display_mode *mode,
9043 int x, int y, struct drm_framebuffer *fb)
9045 struct drm_device *dev = crtc->dev;
9046 drm_i915_private_t *dev_priv = dev->dev_private;
9047 struct drm_display_mode *saved_mode, *saved_hwmode;
9048 struct intel_crtc_config *pipe_config = NULL;
9049 struct intel_crtc *intel_crtc;
9050 unsigned disable_pipes, prepare_pipes, modeset_pipes;
9053 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
9056 saved_hwmode = saved_mode + 1;
9058 intel_modeset_affected_pipes(crtc, &modeset_pipes,
9059 &prepare_pipes, &disable_pipes);
9061 *saved_hwmode = crtc->hwmode;
9062 *saved_mode = crtc->mode;
9064 /* Hack: Because we don't (yet) support global modeset on multiple
9065 * crtcs, we don't keep track of the new mode for more than one crtc.
9066 * Hence simply check whether any bit is set in modeset_pipes in all the
9067 * pieces of code that are not yet converted to deal with mutliple crtcs
9068 * changing their mode at the same time. */
9069 if (modeset_pipes) {
9070 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9071 if (IS_ERR(pipe_config)) {
9072 ret = PTR_ERR(pipe_config);
9077 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9081 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9082 intel_crtc_disable(&intel_crtc->base);
9084 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9085 if (intel_crtc->base.enabled)
9086 dev_priv->display.crtc_disable(&intel_crtc->base);
9089 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9090 * to set it here already despite that we pass it down the callchain.
9092 if (modeset_pipes) {
9094 /* mode_set/enable/disable functions rely on a correct pipe
9096 to_intel_crtc(crtc)->config = *pipe_config;
9099 /* Only after disabling all output pipelines that will be changed can we
9100 * update the the output configuration. */
9101 intel_modeset_update_state(dev, prepare_pipes);
9103 if (dev_priv->display.modeset_global_resources)
9104 dev_priv->display.modeset_global_resources(dev);
9106 /* Set up the DPLL and any encoders state that needs to adjust or depend
9109 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9110 ret = intel_crtc_mode_set(&intel_crtc->base,
9116 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9117 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9118 dev_priv->display.crtc_enable(&intel_crtc->base);
9120 if (modeset_pipes) {
9121 /* Store real post-adjustment hardware mode. */
9122 crtc->hwmode = pipe_config->adjusted_mode;
9124 /* Calculate and store various constants which
9125 * are later needed by vblank and swap-completion
9126 * timestamping. They are derived from true hwmode.
9128 drm_calc_timestamping_constants(crtc);
9131 /* FIXME: add subpixel order */
9133 if (ret && crtc->enabled) {
9134 crtc->hwmode = *saved_hwmode;
9135 crtc->mode = *saved_mode;
9144 static int intel_set_mode(struct drm_crtc *crtc,
9145 struct drm_display_mode *mode,
9146 int x, int y, struct drm_framebuffer *fb)
9150 ret = __intel_set_mode(crtc, mode, x, y, fb);
9153 intel_modeset_check_state(crtc->dev);
9158 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9160 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9163 #undef for_each_intel_crtc_masked
9165 static void intel_set_config_free(struct intel_set_config *config)
9170 kfree(config->save_connector_encoders);
9171 kfree(config->save_encoder_crtcs);
9175 static int intel_set_config_save_state(struct drm_device *dev,
9176 struct intel_set_config *config)
9178 struct drm_encoder *encoder;
9179 struct drm_connector *connector;
9182 config->save_encoder_crtcs =
9183 kcalloc(dev->mode_config.num_encoder,
9184 sizeof(struct drm_crtc *), GFP_KERNEL);
9185 if (!config->save_encoder_crtcs)
9188 config->save_connector_encoders =
9189 kcalloc(dev->mode_config.num_connector,
9190 sizeof(struct drm_encoder *), GFP_KERNEL);
9191 if (!config->save_connector_encoders)
9194 /* Copy data. Note that driver private data is not affected.
9195 * Should anything bad happen only the expected state is
9196 * restored, not the drivers personal bookkeeping.
9199 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9200 config->save_encoder_crtcs[count++] = encoder->crtc;
9204 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9205 config->save_connector_encoders[count++] = connector->encoder;
9211 static void intel_set_config_restore_state(struct drm_device *dev,
9212 struct intel_set_config *config)
9214 struct intel_encoder *encoder;
9215 struct intel_connector *connector;
9219 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9221 to_intel_crtc(config->save_encoder_crtcs[count++]);
9225 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9226 connector->new_encoder =
9227 to_intel_encoder(config->save_connector_encoders[count++]);
9232 is_crtc_connector_off(struct drm_mode_set *set)
9236 if (set->num_connectors == 0)
9239 if (WARN_ON(set->connectors == NULL))
9242 for (i = 0; i < set->num_connectors; i++)
9243 if (set->connectors[i]->encoder &&
9244 set->connectors[i]->encoder->crtc == set->crtc &&
9245 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9252 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9253 struct intel_set_config *config)
9256 /* We should be able to check here if the fb has the same properties
9257 * and then just flip_or_move it */
9258 if (is_crtc_connector_off(set)) {
9259 config->mode_changed = true;
9260 } else if (set->crtc->fb != set->fb) {
9261 /* If we have no fb then treat it as a full mode set */
9262 if (set->crtc->fb == NULL) {
9263 struct intel_crtc *intel_crtc =
9264 to_intel_crtc(set->crtc);
9266 if (intel_crtc->active && i915_fastboot) {
9267 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9268 config->fb_changed = true;
9270 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9271 config->mode_changed = true;
9273 } else if (set->fb == NULL) {
9274 config->mode_changed = true;
9275 } else if (set->fb->pixel_format !=
9276 set->crtc->fb->pixel_format) {
9277 config->mode_changed = true;
9279 config->fb_changed = true;
9283 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9284 config->fb_changed = true;
9286 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9287 DRM_DEBUG_KMS("modes are different, full mode set\n");
9288 drm_mode_debug_printmodeline(&set->crtc->mode);
9289 drm_mode_debug_printmodeline(set->mode);
9290 config->mode_changed = true;
9293 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9294 set->crtc->base.id, config->mode_changed, config->fb_changed);
9298 intel_modeset_stage_output_state(struct drm_device *dev,
9299 struct drm_mode_set *set,
9300 struct intel_set_config *config)
9302 struct drm_crtc *new_crtc;
9303 struct intel_connector *connector;
9304 struct intel_encoder *encoder;
9307 /* The upper layers ensure that we either disable a crtc or have a list
9308 * of connectors. For paranoia, double-check this. */
9309 WARN_ON(!set->fb && (set->num_connectors != 0));
9310 WARN_ON(set->fb && (set->num_connectors == 0));
9312 list_for_each_entry(connector, &dev->mode_config.connector_list,
9314 /* Otherwise traverse passed in connector list and get encoders
9316 for (ro = 0; ro < set->num_connectors; ro++) {
9317 if (set->connectors[ro] == &connector->base) {
9318 connector->new_encoder = connector->encoder;
9323 /* If we disable the crtc, disable all its connectors. Also, if
9324 * the connector is on the changing crtc but not on the new
9325 * connector list, disable it. */
9326 if ((!set->fb || ro == set->num_connectors) &&
9327 connector->base.encoder &&
9328 connector->base.encoder->crtc == set->crtc) {
9329 connector->new_encoder = NULL;
9331 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9332 connector->base.base.id,
9333 drm_get_connector_name(&connector->base));
9337 if (&connector->new_encoder->base != connector->base.encoder) {
9338 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9339 config->mode_changed = true;
9342 /* connector->new_encoder is now updated for all connectors. */
9344 /* Update crtc of enabled connectors. */
9345 list_for_each_entry(connector, &dev->mode_config.connector_list,
9347 if (!connector->new_encoder)
9350 new_crtc = connector->new_encoder->base.crtc;
9352 for (ro = 0; ro < set->num_connectors; ro++) {
9353 if (set->connectors[ro] == &connector->base)
9354 new_crtc = set->crtc;
9357 /* Make sure the new CRTC will work with the encoder */
9358 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9362 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9364 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9365 connector->base.base.id,
9366 drm_get_connector_name(&connector->base),
9370 /* Check for any encoders that needs to be disabled. */
9371 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9373 list_for_each_entry(connector,
9374 &dev->mode_config.connector_list,
9376 if (connector->new_encoder == encoder) {
9377 WARN_ON(!connector->new_encoder->new_crtc);
9382 encoder->new_crtc = NULL;
9384 /* Only now check for crtc changes so we don't miss encoders
9385 * that will be disabled. */
9386 if (&encoder->new_crtc->base != encoder->base.crtc) {
9387 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9388 config->mode_changed = true;
9391 /* Now we've also updated encoder->new_crtc for all encoders. */
9396 static int intel_crtc_set_config(struct drm_mode_set *set)
9398 struct drm_device *dev;
9399 struct drm_mode_set save_set;
9400 struct intel_set_config *config;
9405 BUG_ON(!set->crtc->helper_private);
9407 /* Enforce sane interface api - has been abused by the fb helper. */
9408 BUG_ON(!set->mode && set->fb);
9409 BUG_ON(set->fb && set->num_connectors == 0);
9412 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9413 set->crtc->base.id, set->fb->base.id,
9414 (int)set->num_connectors, set->x, set->y);
9416 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9419 dev = set->crtc->dev;
9422 config = kzalloc(sizeof(*config), GFP_KERNEL);
9426 ret = intel_set_config_save_state(dev, config);
9430 save_set.crtc = set->crtc;
9431 save_set.mode = &set->crtc->mode;
9432 save_set.x = set->crtc->x;
9433 save_set.y = set->crtc->y;
9434 save_set.fb = set->crtc->fb;
9436 /* Compute whether we need a full modeset, only an fb base update or no
9437 * change at all. In the future we might also check whether only the
9438 * mode changed, e.g. for LVDS where we only change the panel fitter in
9440 intel_set_config_compute_mode_changes(set, config);
9442 ret = intel_modeset_stage_output_state(dev, set, config);
9446 if (config->mode_changed) {
9447 ret = intel_set_mode(set->crtc, set->mode,
9448 set->x, set->y, set->fb);
9449 } else if (config->fb_changed) {
9450 intel_crtc_wait_for_pending_flips(set->crtc);
9452 ret = intel_pipe_set_base(set->crtc,
9453 set->x, set->y, set->fb);
9457 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9458 set->crtc->base.id, ret);
9460 intel_set_config_restore_state(dev, config);
9462 /* Try to restore the config */
9463 if (config->mode_changed &&
9464 intel_set_mode(save_set.crtc, save_set.mode,
9465 save_set.x, save_set.y, save_set.fb))
9466 DRM_ERROR("failed to restore config after modeset failure\n");
9470 intel_set_config_free(config);
9474 static const struct drm_crtc_funcs intel_crtc_funcs = {
9475 .cursor_set = intel_crtc_cursor_set,
9476 .cursor_move = intel_crtc_cursor_move,
9477 .gamma_set = intel_crtc_gamma_set,
9478 .set_config = intel_crtc_set_config,
9479 .destroy = intel_crtc_destroy,
9480 .page_flip = intel_crtc_page_flip,
9483 static void intel_cpu_pll_init(struct drm_device *dev)
9486 intel_ddi_pll_init(dev);
9489 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9490 struct intel_shared_dpll *pll,
9491 struct intel_dpll_hw_state *hw_state)
9495 val = I915_READ(PCH_DPLL(pll->id));
9496 hw_state->dpll = val;
9497 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9498 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9500 return val & DPLL_VCO_ENABLE;
9503 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9504 struct intel_shared_dpll *pll)
9506 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9507 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9510 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9511 struct intel_shared_dpll *pll)
9513 /* PCH refclock must be enabled first */
9514 assert_pch_refclk_enabled(dev_priv);
9516 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9518 /* Wait for the clocks to stabilize. */
9519 POSTING_READ(PCH_DPLL(pll->id));
9522 /* The pixel multiplier can only be updated once the
9523 * DPLL is enabled and the clocks are stable.
9525 * So write it again.
9527 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9528 POSTING_READ(PCH_DPLL(pll->id));
9532 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9533 struct intel_shared_dpll *pll)
9535 struct drm_device *dev = dev_priv->dev;
9536 struct intel_crtc *crtc;
9538 /* Make sure no transcoder isn't still depending on us. */
9539 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9540 if (intel_crtc_to_shared_dpll(crtc) == pll)
9541 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9544 I915_WRITE(PCH_DPLL(pll->id), 0);
9545 POSTING_READ(PCH_DPLL(pll->id));
9549 static char *ibx_pch_dpll_names[] = {
9554 static void ibx_pch_dpll_init(struct drm_device *dev)
9556 struct drm_i915_private *dev_priv = dev->dev_private;
9559 dev_priv->num_shared_dpll = 2;
9561 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9562 dev_priv->shared_dplls[i].id = i;
9563 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9564 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9565 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9566 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9567 dev_priv->shared_dplls[i].get_hw_state =
9568 ibx_pch_dpll_get_hw_state;
9572 static void intel_shared_dpll_init(struct drm_device *dev)
9574 struct drm_i915_private *dev_priv = dev->dev_private;
9576 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9577 ibx_pch_dpll_init(dev);
9579 dev_priv->num_shared_dpll = 0;
9581 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9582 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9583 dev_priv->num_shared_dpll);
9586 static void intel_crtc_init(struct drm_device *dev, int pipe)
9588 drm_i915_private_t *dev_priv = dev->dev_private;
9589 struct intel_crtc *intel_crtc;
9592 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9593 if (intel_crtc == NULL)
9596 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9598 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9599 for (i = 0; i < 256; i++) {
9600 intel_crtc->lut_r[i] = i;
9601 intel_crtc->lut_g[i] = i;
9602 intel_crtc->lut_b[i] = i;
9605 /* Swap pipes & planes for FBC on pre-965 */
9606 intel_crtc->pipe = pipe;
9607 intel_crtc->plane = pipe;
9608 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9609 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9610 intel_crtc->plane = !pipe;
9613 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9614 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9615 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9616 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9618 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9621 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9622 struct drm_file *file)
9624 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9625 struct drm_mode_object *drmmode_obj;
9626 struct intel_crtc *crtc;
9628 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9631 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9632 DRM_MODE_OBJECT_CRTC);
9635 DRM_ERROR("no such CRTC id\n");
9639 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9640 pipe_from_crtc_id->pipe = crtc->pipe;
9645 static int intel_encoder_clones(struct intel_encoder *encoder)
9647 struct drm_device *dev = encoder->base.dev;
9648 struct intel_encoder *source_encoder;
9652 list_for_each_entry(source_encoder,
9653 &dev->mode_config.encoder_list, base.head) {
9655 if (encoder == source_encoder)
9656 index_mask |= (1 << entry);
9658 /* Intel hw has only one MUX where enocoders could be cloned. */
9659 if (encoder->cloneable && source_encoder->cloneable)
9660 index_mask |= (1 << entry);
9668 static bool has_edp_a(struct drm_device *dev)
9670 struct drm_i915_private *dev_priv = dev->dev_private;
9672 if (!IS_MOBILE(dev))
9675 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9679 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9685 static void intel_setup_outputs(struct drm_device *dev)
9687 struct drm_i915_private *dev_priv = dev->dev_private;
9688 struct intel_encoder *encoder;
9689 bool dpd_is_edp = false;
9691 intel_lvds_init(dev);
9694 intel_crt_init(dev);
9699 /* Haswell uses DDI functions to detect digital outputs */
9700 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9701 /* DDI A only supports eDP */
9703 intel_ddi_init(dev, PORT_A);
9705 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9707 found = I915_READ(SFUSE_STRAP);
9709 if (found & SFUSE_STRAP_DDIB_DETECTED)
9710 intel_ddi_init(dev, PORT_B);
9711 if (found & SFUSE_STRAP_DDIC_DETECTED)
9712 intel_ddi_init(dev, PORT_C);
9713 if (found & SFUSE_STRAP_DDID_DETECTED)
9714 intel_ddi_init(dev, PORT_D);
9715 } else if (HAS_PCH_SPLIT(dev)) {
9717 dpd_is_edp = intel_dpd_is_edp(dev);
9720 intel_dp_init(dev, DP_A, PORT_A);
9722 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9723 /* PCH SDVOB multiplex with HDMIB */
9724 found = intel_sdvo_init(dev, PCH_SDVOB, true);
9726 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9727 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9728 intel_dp_init(dev, PCH_DP_B, PORT_B);
9731 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9732 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9734 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9735 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9737 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9738 intel_dp_init(dev, PCH_DP_C, PORT_C);
9740 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9741 intel_dp_init(dev, PCH_DP_D, PORT_D);
9742 } else if (IS_VALLEYVIEW(dev)) {
9743 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9744 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9745 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9747 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9748 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9752 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9753 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9755 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9756 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9759 intel_dsi_init(dev);
9760 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9763 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9764 DRM_DEBUG_KMS("probing SDVOB\n");
9765 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9766 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9767 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9768 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9771 if (!found && SUPPORTS_INTEGRATED_DP(dev))
9772 intel_dp_init(dev, DP_B, PORT_B);
9775 /* Before G4X SDVOC doesn't have its own detect register */
9777 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9778 DRM_DEBUG_KMS("probing SDVOC\n");
9779 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9782 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9784 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9785 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9786 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9788 if (SUPPORTS_INTEGRATED_DP(dev))
9789 intel_dp_init(dev, DP_C, PORT_C);
9792 if (SUPPORTS_INTEGRATED_DP(dev) &&
9793 (I915_READ(DP_D) & DP_DETECTED))
9794 intel_dp_init(dev, DP_D, PORT_D);
9795 } else if (IS_GEN2(dev))
9796 intel_dvo_init(dev);
9798 if (SUPPORTS_TV(dev))
9801 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9802 encoder->base.possible_crtcs = encoder->crtc_mask;
9803 encoder->base.possible_clones =
9804 intel_encoder_clones(encoder);
9807 intel_init_pch_refclk(dev);
9809 drm_helper_move_panel_connectors_to_head(dev);
9812 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9814 drm_framebuffer_cleanup(&fb->base);
9815 drm_gem_object_unreference_unlocked(&fb->obj->base);
9818 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9820 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9822 intel_framebuffer_fini(intel_fb);
9826 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9827 struct drm_file *file,
9828 unsigned int *handle)
9830 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9831 struct drm_i915_gem_object *obj = intel_fb->obj;
9833 return drm_gem_handle_create(file, &obj->base, handle);
9836 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9837 .destroy = intel_user_framebuffer_destroy,
9838 .create_handle = intel_user_framebuffer_create_handle,
9841 int intel_framebuffer_init(struct drm_device *dev,
9842 struct intel_framebuffer *intel_fb,
9843 struct drm_mode_fb_cmd2 *mode_cmd,
9844 struct drm_i915_gem_object *obj)
9849 if (obj->tiling_mode == I915_TILING_Y) {
9850 DRM_DEBUG("hardware does not support tiling Y\n");
9854 if (mode_cmd->pitches[0] & 63) {
9855 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9856 mode_cmd->pitches[0]);
9860 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9861 pitch_limit = 32*1024;
9862 } else if (INTEL_INFO(dev)->gen >= 4) {
9863 if (obj->tiling_mode)
9864 pitch_limit = 16*1024;
9866 pitch_limit = 32*1024;
9867 } else if (INTEL_INFO(dev)->gen >= 3) {
9868 if (obj->tiling_mode)
9869 pitch_limit = 8*1024;
9871 pitch_limit = 16*1024;
9873 /* XXX DSPC is limited to 4k tiled */
9874 pitch_limit = 8*1024;
9876 if (mode_cmd->pitches[0] > pitch_limit) {
9877 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9878 obj->tiling_mode ? "tiled" : "linear",
9879 mode_cmd->pitches[0], pitch_limit);
9883 if (obj->tiling_mode != I915_TILING_NONE &&
9884 mode_cmd->pitches[0] != obj->stride) {
9885 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9886 mode_cmd->pitches[0], obj->stride);
9890 /* Reject formats not supported by any plane early. */
9891 switch (mode_cmd->pixel_format) {
9893 case DRM_FORMAT_RGB565:
9894 case DRM_FORMAT_XRGB8888:
9895 case DRM_FORMAT_ARGB8888:
9897 case DRM_FORMAT_XRGB1555:
9898 case DRM_FORMAT_ARGB1555:
9899 if (INTEL_INFO(dev)->gen > 3) {
9900 DRM_DEBUG("unsupported pixel format: %s\n",
9901 drm_get_format_name(mode_cmd->pixel_format));
9905 case DRM_FORMAT_XBGR8888:
9906 case DRM_FORMAT_ABGR8888:
9907 case DRM_FORMAT_XRGB2101010:
9908 case DRM_FORMAT_ARGB2101010:
9909 case DRM_FORMAT_XBGR2101010:
9910 case DRM_FORMAT_ABGR2101010:
9911 if (INTEL_INFO(dev)->gen < 4) {
9912 DRM_DEBUG("unsupported pixel format: %s\n",
9913 drm_get_format_name(mode_cmd->pixel_format));
9917 case DRM_FORMAT_YUYV:
9918 case DRM_FORMAT_UYVY:
9919 case DRM_FORMAT_YVYU:
9920 case DRM_FORMAT_VYUY:
9921 if (INTEL_INFO(dev)->gen < 5) {
9922 DRM_DEBUG("unsupported pixel format: %s\n",
9923 drm_get_format_name(mode_cmd->pixel_format));
9928 DRM_DEBUG("unsupported pixel format: %s\n",
9929 drm_get_format_name(mode_cmd->pixel_format));
9933 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9934 if (mode_cmd->offsets[0] != 0)
9937 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9938 intel_fb->obj = obj;
9940 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9942 DRM_ERROR("framebuffer init failed %d\n", ret);
9949 static struct drm_framebuffer *
9950 intel_user_framebuffer_create(struct drm_device *dev,
9951 struct drm_file *filp,
9952 struct drm_mode_fb_cmd2 *mode_cmd)
9954 struct drm_i915_gem_object *obj;
9956 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9957 mode_cmd->handles[0]));
9958 if (&obj->base == NULL)
9959 return ERR_PTR(-ENOENT);
9961 return intel_framebuffer_create(dev, mode_cmd, obj);
9964 static const struct drm_mode_config_funcs intel_mode_funcs = {
9965 .fb_create = intel_user_framebuffer_create,
9966 .output_poll_changed = intel_fb_output_poll_changed,
9969 /* Set up chip specific display functions */
9970 static void intel_init_display(struct drm_device *dev)
9972 struct drm_i915_private *dev_priv = dev->dev_private;
9974 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9975 dev_priv->display.find_dpll = g4x_find_best_dpll;
9976 else if (IS_VALLEYVIEW(dev))
9977 dev_priv->display.find_dpll = vlv_find_best_dpll;
9978 else if (IS_PINEVIEW(dev))
9979 dev_priv->display.find_dpll = pnv_find_best_dpll;
9981 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9984 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9985 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9986 dev_priv->display.crtc_enable = haswell_crtc_enable;
9987 dev_priv->display.crtc_disable = haswell_crtc_disable;
9988 dev_priv->display.off = haswell_crtc_off;
9989 dev_priv->display.update_plane = ironlake_update_plane;
9990 } else if (HAS_PCH_SPLIT(dev)) {
9991 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9992 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9993 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9994 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9995 dev_priv->display.off = ironlake_crtc_off;
9996 dev_priv->display.update_plane = ironlake_update_plane;
9997 } else if (IS_VALLEYVIEW(dev)) {
9998 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9999 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10000 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10001 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10002 dev_priv->display.off = i9xx_crtc_off;
10003 dev_priv->display.update_plane = i9xx_update_plane;
10005 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10006 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10007 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10008 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10009 dev_priv->display.off = i9xx_crtc_off;
10010 dev_priv->display.update_plane = i9xx_update_plane;
10013 /* Returns the core display clock speed */
10014 if (IS_VALLEYVIEW(dev))
10015 dev_priv->display.get_display_clock_speed =
10016 valleyview_get_display_clock_speed;
10017 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10018 dev_priv->display.get_display_clock_speed =
10019 i945_get_display_clock_speed;
10020 else if (IS_I915G(dev))
10021 dev_priv->display.get_display_clock_speed =
10022 i915_get_display_clock_speed;
10023 else if (IS_I945GM(dev) || IS_845G(dev))
10024 dev_priv->display.get_display_clock_speed =
10025 i9xx_misc_get_display_clock_speed;
10026 else if (IS_PINEVIEW(dev))
10027 dev_priv->display.get_display_clock_speed =
10028 pnv_get_display_clock_speed;
10029 else if (IS_I915GM(dev))
10030 dev_priv->display.get_display_clock_speed =
10031 i915gm_get_display_clock_speed;
10032 else if (IS_I865G(dev))
10033 dev_priv->display.get_display_clock_speed =
10034 i865_get_display_clock_speed;
10035 else if (IS_I85X(dev))
10036 dev_priv->display.get_display_clock_speed =
10037 i855_get_display_clock_speed;
10038 else /* 852, 830 */
10039 dev_priv->display.get_display_clock_speed =
10040 i830_get_display_clock_speed;
10042 if (HAS_PCH_SPLIT(dev)) {
10043 if (IS_GEN5(dev)) {
10044 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10045 dev_priv->display.write_eld = ironlake_write_eld;
10046 } else if (IS_GEN6(dev)) {
10047 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10048 dev_priv->display.write_eld = ironlake_write_eld;
10049 } else if (IS_IVYBRIDGE(dev)) {
10050 /* FIXME: detect B0+ stepping and use auto training */
10051 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10052 dev_priv->display.write_eld = ironlake_write_eld;
10053 dev_priv->display.modeset_global_resources =
10054 ivb_modeset_global_resources;
10055 } else if (IS_HASWELL(dev)) {
10056 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10057 dev_priv->display.write_eld = haswell_write_eld;
10058 dev_priv->display.modeset_global_resources =
10059 haswell_modeset_global_resources;
10061 } else if (IS_G4X(dev)) {
10062 dev_priv->display.write_eld = g4x_write_eld;
10065 /* Default just returns -ENODEV to indicate unsupported */
10066 dev_priv->display.queue_flip = intel_default_queue_flip;
10068 switch (INTEL_INFO(dev)->gen) {
10070 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10074 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10079 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10083 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10086 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10092 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10093 * resume, or other times. This quirk makes sure that's the case for
10094 * affected systems.
10096 static void quirk_pipea_force(struct drm_device *dev)
10098 struct drm_i915_private *dev_priv = dev->dev_private;
10100 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10101 DRM_INFO("applying pipe a force quirk\n");
10105 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10107 static void quirk_ssc_force_disable(struct drm_device *dev)
10109 struct drm_i915_private *dev_priv = dev->dev_private;
10110 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10111 DRM_INFO("applying lvds SSC disable quirk\n");
10115 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10118 static void quirk_invert_brightness(struct drm_device *dev)
10120 struct drm_i915_private *dev_priv = dev->dev_private;
10121 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10122 DRM_INFO("applying inverted panel brightness quirk\n");
10126 * Some machines (Dell XPS13) suffer broken backlight controls if
10127 * BLM_PCH_PWM_ENABLE is set.
10129 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10131 struct drm_i915_private *dev_priv = dev->dev_private;
10132 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10133 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10136 struct intel_quirk {
10138 int subsystem_vendor;
10139 int subsystem_device;
10140 void (*hook)(struct drm_device *dev);
10143 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10144 struct intel_dmi_quirk {
10145 void (*hook)(struct drm_device *dev);
10146 const struct dmi_system_id (*dmi_id_list)[];
10149 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10151 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10155 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10157 .dmi_id_list = &(const struct dmi_system_id[]) {
10159 .callback = intel_dmi_reverse_brightness,
10160 .ident = "NCR Corporation",
10161 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10162 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10165 { } /* terminating entry */
10167 .hook = quirk_invert_brightness,
10171 static struct intel_quirk intel_quirks[] = {
10172 /* HP Mini needs pipe A force quirk (LP: #322104) */
10173 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10175 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10176 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10178 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10179 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10181 /* 830/845 need to leave pipe A & dpll A up */
10182 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10183 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10185 /* Lenovo U160 cannot use SSC on LVDS */
10186 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10188 /* Sony Vaio Y cannot use SSC on LVDS */
10189 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10192 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10193 * seem to use inverted backlight PWM.
10195 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10197 /* Dell XPS13 HD Sandy Bridge */
10198 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10199 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10200 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10203 static void intel_init_quirks(struct drm_device *dev)
10205 struct pci_dev *d = dev->pdev;
10208 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10209 struct intel_quirk *q = &intel_quirks[i];
10211 if (d->device == q->device &&
10212 (d->subsystem_vendor == q->subsystem_vendor ||
10213 q->subsystem_vendor == PCI_ANY_ID) &&
10214 (d->subsystem_device == q->subsystem_device ||
10215 q->subsystem_device == PCI_ANY_ID))
10218 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10219 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10220 intel_dmi_quirks[i].hook(dev);
10224 /* Disable the VGA plane that we never use */
10225 static void i915_disable_vga(struct drm_device *dev)
10227 struct drm_i915_private *dev_priv = dev->dev_private;
10229 u32 vga_reg = i915_vgacntrl_reg(dev);
10231 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10232 outb(SR01, VGA_SR_INDEX);
10233 sr1 = inb(VGA_SR_DATA);
10234 outb(sr1 | 1<<5, VGA_SR_DATA);
10236 /* Disable VGA memory on Intel HD */
10237 if (HAS_PCH_SPLIT(dev)) {
10238 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10239 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10240 VGA_RSRC_NORMAL_IO |
10241 VGA_RSRC_NORMAL_MEM);
10244 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10247 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10248 POSTING_READ(vga_reg);
10251 static void i915_enable_vga(struct drm_device *dev)
10253 /* Enable VGA memory on Intel HD */
10254 if (HAS_PCH_SPLIT(dev)) {
10255 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10256 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10257 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10258 VGA_RSRC_LEGACY_MEM |
10259 VGA_RSRC_NORMAL_IO |
10260 VGA_RSRC_NORMAL_MEM);
10261 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10265 void intel_modeset_init_hw(struct drm_device *dev)
10267 intel_prepare_ddi(dev);
10269 intel_init_clock_gating(dev);
10271 mutex_lock(&dev->struct_mutex);
10272 intel_enable_gt_powersave(dev);
10273 mutex_unlock(&dev->struct_mutex);
10276 void intel_modeset_suspend_hw(struct drm_device *dev)
10278 intel_suspend_hw(dev);
10281 void intel_modeset_init(struct drm_device *dev)
10283 struct drm_i915_private *dev_priv = dev->dev_private;
10286 drm_mode_config_init(dev);
10288 dev->mode_config.min_width = 0;
10289 dev->mode_config.min_height = 0;
10291 dev->mode_config.preferred_depth = 24;
10292 dev->mode_config.prefer_shadow = 1;
10294 dev->mode_config.funcs = &intel_mode_funcs;
10296 intel_init_quirks(dev);
10298 intel_init_pm(dev);
10300 if (INTEL_INFO(dev)->num_pipes == 0)
10303 intel_init_display(dev);
10305 if (IS_GEN2(dev)) {
10306 dev->mode_config.max_width = 2048;
10307 dev->mode_config.max_height = 2048;
10308 } else if (IS_GEN3(dev)) {
10309 dev->mode_config.max_width = 4096;
10310 dev->mode_config.max_height = 4096;
10312 dev->mode_config.max_width = 8192;
10313 dev->mode_config.max_height = 8192;
10315 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10317 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10318 INTEL_INFO(dev)->num_pipes,
10319 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10322 intel_crtc_init(dev, i);
10323 for (j = 0; j < dev_priv->num_plane; j++) {
10324 ret = intel_plane_init(dev, i, j);
10326 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10327 pipe_name(i), sprite_name(i, j), ret);
10331 intel_cpu_pll_init(dev);
10332 intel_shared_dpll_init(dev);
10334 /* Just disable it once at startup */
10335 i915_disable_vga(dev);
10336 intel_setup_outputs(dev);
10338 /* Just in case the BIOS is doing something questionable. */
10339 intel_disable_fbc(dev);
10343 intel_connector_break_all_links(struct intel_connector *connector)
10345 connector->base.dpms = DRM_MODE_DPMS_OFF;
10346 connector->base.encoder = NULL;
10347 connector->encoder->connectors_active = false;
10348 connector->encoder->base.crtc = NULL;
10351 static void intel_enable_pipe_a(struct drm_device *dev)
10353 struct intel_connector *connector;
10354 struct drm_connector *crt = NULL;
10355 struct intel_load_detect_pipe load_detect_temp;
10357 /* We can't just switch on the pipe A, we need to set things up with a
10358 * proper mode and output configuration. As a gross hack, enable pipe A
10359 * by enabling the load detect pipe once. */
10360 list_for_each_entry(connector,
10361 &dev->mode_config.connector_list,
10363 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10364 crt = &connector->base;
10372 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10373 intel_release_load_detect_pipe(crt, &load_detect_temp);
10379 intel_check_plane_mapping(struct intel_crtc *crtc)
10381 struct drm_device *dev = crtc->base.dev;
10382 struct drm_i915_private *dev_priv = dev->dev_private;
10385 if (INTEL_INFO(dev)->num_pipes == 1)
10388 reg = DSPCNTR(!crtc->plane);
10389 val = I915_READ(reg);
10391 if ((val & DISPLAY_PLANE_ENABLE) &&
10392 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10398 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10400 struct drm_device *dev = crtc->base.dev;
10401 struct drm_i915_private *dev_priv = dev->dev_private;
10404 /* Clear any frame start delays used for debugging left by the BIOS */
10405 reg = PIPECONF(crtc->config.cpu_transcoder);
10406 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10408 /* We need to sanitize the plane -> pipe mapping first because this will
10409 * disable the crtc (and hence change the state) if it is wrong. Note
10410 * that gen4+ has a fixed plane -> pipe mapping. */
10411 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10412 struct intel_connector *connector;
10415 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10416 crtc->base.base.id);
10418 /* Pipe has the wrong plane attached and the plane is active.
10419 * Temporarily change the plane mapping and disable everything
10421 plane = crtc->plane;
10422 crtc->plane = !plane;
10423 dev_priv->display.crtc_disable(&crtc->base);
10424 crtc->plane = plane;
10426 /* ... and break all links. */
10427 list_for_each_entry(connector, &dev->mode_config.connector_list,
10429 if (connector->encoder->base.crtc != &crtc->base)
10432 intel_connector_break_all_links(connector);
10435 WARN_ON(crtc->active);
10436 crtc->base.enabled = false;
10439 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10440 crtc->pipe == PIPE_A && !crtc->active) {
10441 /* BIOS forgot to enable pipe A, this mostly happens after
10442 * resume. Force-enable the pipe to fix this, the update_dpms
10443 * call below we restore the pipe to the right state, but leave
10444 * the required bits on. */
10445 intel_enable_pipe_a(dev);
10448 /* Adjust the state of the output pipe according to whether we
10449 * have active connectors/encoders. */
10450 intel_crtc_update_dpms(&crtc->base);
10452 if (crtc->active != crtc->base.enabled) {
10453 struct intel_encoder *encoder;
10455 /* This can happen either due to bugs in the get_hw_state
10456 * functions or because the pipe is force-enabled due to the
10458 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10459 crtc->base.base.id,
10460 crtc->base.enabled ? "enabled" : "disabled",
10461 crtc->active ? "enabled" : "disabled");
10463 crtc->base.enabled = crtc->active;
10465 /* Because we only establish the connector -> encoder ->
10466 * crtc links if something is active, this means the
10467 * crtc is now deactivated. Break the links. connector
10468 * -> encoder links are only establish when things are
10469 * actually up, hence no need to break them. */
10470 WARN_ON(crtc->active);
10472 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10473 WARN_ON(encoder->connectors_active);
10474 encoder->base.crtc = NULL;
10479 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10481 struct intel_connector *connector;
10482 struct drm_device *dev = encoder->base.dev;
10484 /* We need to check both for a crtc link (meaning that the
10485 * encoder is active and trying to read from a pipe) and the
10486 * pipe itself being active. */
10487 bool has_active_crtc = encoder->base.crtc &&
10488 to_intel_crtc(encoder->base.crtc)->active;
10490 if (encoder->connectors_active && !has_active_crtc) {
10491 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10492 encoder->base.base.id,
10493 drm_get_encoder_name(&encoder->base));
10495 /* Connector is active, but has no active pipe. This is
10496 * fallout from our resume register restoring. Disable
10497 * the encoder manually again. */
10498 if (encoder->base.crtc) {
10499 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10500 encoder->base.base.id,
10501 drm_get_encoder_name(&encoder->base));
10502 encoder->disable(encoder);
10505 /* Inconsistent output/port/pipe state happens presumably due to
10506 * a bug in one of the get_hw_state functions. Or someplace else
10507 * in our code, like the register restore mess on resume. Clamp
10508 * things to off as a safer default. */
10509 list_for_each_entry(connector,
10510 &dev->mode_config.connector_list,
10512 if (connector->encoder != encoder)
10515 intel_connector_break_all_links(connector);
10518 /* Enabled encoders without active connectors will be fixed in
10519 * the crtc fixup. */
10522 void i915_redisable_vga(struct drm_device *dev)
10524 struct drm_i915_private *dev_priv = dev->dev_private;
10525 u32 vga_reg = i915_vgacntrl_reg(dev);
10527 /* This function can be called both from intel_modeset_setup_hw_state or
10528 * at a very early point in our resume sequence, where the power well
10529 * structures are not yet restored. Since this function is at a very
10530 * paranoid "someone might have enabled VGA while we were not looking"
10531 * level, just check if the power well is enabled instead of trying to
10532 * follow the "don't touch the power well if we don't need it" policy
10533 * the rest of the driver uses. */
10534 if (HAS_POWER_WELL(dev) &&
10535 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10538 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10539 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10540 i915_disable_vga(dev);
10544 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10546 struct drm_i915_private *dev_priv = dev->dev_private;
10548 struct intel_crtc *crtc;
10549 struct intel_encoder *encoder;
10550 struct intel_connector *connector;
10553 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10555 memset(&crtc->config, 0, sizeof(crtc->config));
10557 crtc->active = dev_priv->display.get_pipe_config(crtc,
10560 crtc->base.enabled = crtc->active;
10562 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10563 crtc->base.base.id,
10564 crtc->active ? "enabled" : "disabled");
10567 /* FIXME: Smash this into the new shared dpll infrastructure. */
10569 intel_ddi_setup_hw_pll_state(dev);
10571 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10572 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10574 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10576 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10578 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10581 pll->refcount = pll->active;
10583 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10584 pll->name, pll->refcount, pll->on);
10587 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10591 if (encoder->get_hw_state(encoder, &pipe)) {
10592 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10593 encoder->base.crtc = &crtc->base;
10594 if (encoder->get_config)
10595 encoder->get_config(encoder, &crtc->config);
10597 encoder->base.crtc = NULL;
10600 encoder->connectors_active = false;
10601 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10602 encoder->base.base.id,
10603 drm_get_encoder_name(&encoder->base),
10604 encoder->base.crtc ? "enabled" : "disabled",
10608 list_for_each_entry(connector, &dev->mode_config.connector_list,
10610 if (connector->get_hw_state(connector)) {
10611 connector->base.dpms = DRM_MODE_DPMS_ON;
10612 connector->encoder->connectors_active = true;
10613 connector->base.encoder = &connector->encoder->base;
10615 connector->base.dpms = DRM_MODE_DPMS_OFF;
10616 connector->base.encoder = NULL;
10618 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10619 connector->base.base.id,
10620 drm_get_connector_name(&connector->base),
10621 connector->base.encoder ? "enabled" : "disabled");
10625 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10626 * and i915 state tracking structures. */
10627 void intel_modeset_setup_hw_state(struct drm_device *dev,
10628 bool force_restore)
10630 struct drm_i915_private *dev_priv = dev->dev_private;
10632 struct drm_plane *plane;
10633 struct intel_crtc *crtc;
10634 struct intel_encoder *encoder;
10637 intel_modeset_readout_hw_state(dev);
10640 * Now that we have the config, copy it to each CRTC struct
10641 * Note that this could go away if we move to using crtc_config
10642 * checking everywhere.
10644 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10646 if (crtc->active && i915_fastboot) {
10647 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10649 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10650 crtc->base.base.id);
10651 drm_mode_debug_printmodeline(&crtc->base.mode);
10655 /* HW state is read out, now we need to sanitize this mess. */
10656 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10658 intel_sanitize_encoder(encoder);
10661 for_each_pipe(pipe) {
10662 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10663 intel_sanitize_crtc(crtc);
10664 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10667 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10668 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10670 if (!pll->on || pll->active)
10673 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10675 pll->disable(dev_priv, pll);
10679 if (force_restore) {
10681 * We need to use raw interfaces for restoring state to avoid
10682 * checking (bogus) intermediate states.
10684 for_each_pipe(pipe) {
10685 struct drm_crtc *crtc =
10686 dev_priv->pipe_to_crtc_mapping[pipe];
10688 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10691 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10692 intel_plane_restore(plane);
10694 i915_redisable_vga(dev);
10696 intel_modeset_update_staged_output_state(dev);
10699 intel_modeset_check_state(dev);
10701 drm_mode_config_reset(dev);
10704 void intel_modeset_gem_init(struct drm_device *dev)
10706 intel_modeset_init_hw(dev);
10708 intel_setup_overlay(dev);
10710 intel_modeset_setup_hw_state(dev, false);
10713 void intel_modeset_cleanup(struct drm_device *dev)
10715 struct drm_i915_private *dev_priv = dev->dev_private;
10716 struct drm_crtc *crtc;
10719 * Interrupts and polling as the first thing to avoid creating havoc.
10720 * Too much stuff here (turning of rps, connectors, ...) would
10721 * experience fancy races otherwise.
10723 drm_irq_uninstall(dev);
10724 cancel_work_sync(&dev_priv->hotplug_work);
10726 * Due to the hpd irq storm handling the hotplug work can re-arm the
10727 * poll handlers. Hence disable polling after hpd handling is shut down.
10729 drm_kms_helper_poll_fini(dev);
10731 mutex_lock(&dev->struct_mutex);
10733 intel_unregister_dsm_handler();
10735 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10736 /* Skip inactive CRTCs */
10740 intel_increase_pllclock(crtc);
10743 intel_disable_fbc(dev);
10745 i915_enable_vga(dev);
10747 intel_disable_gt_powersave(dev);
10749 ironlake_teardown_rc6(dev);
10751 mutex_unlock(&dev->struct_mutex);
10753 /* flush any delayed tasks or pending work */
10754 flush_scheduled_work();
10756 /* destroy backlight, if any, before the connectors */
10757 intel_panel_destroy_backlight(dev);
10759 drm_mode_config_cleanup(dev);
10761 intel_cleanup_overlay(dev);
10765 * Return which encoder is currently attached for connector.
10767 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10769 return &intel_attached_encoder(connector)->base;
10772 void intel_connector_attach_encoder(struct intel_connector *connector,
10773 struct intel_encoder *encoder)
10775 connector->encoder = encoder;
10776 drm_mode_connector_attach_encoder(&connector->base,
10781 * set vga decode state - true == enable VGA decode
10783 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10785 struct drm_i915_private *dev_priv = dev->dev_private;
10788 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10790 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10792 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10793 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10797 struct intel_display_error_state {
10799 u32 power_well_driver;
10801 int num_transcoders;
10803 struct intel_cursor_error_state {
10808 } cursor[I915_MAX_PIPES];
10810 struct intel_pipe_error_state {
10812 } pipe[I915_MAX_PIPES];
10814 struct intel_plane_error_state {
10822 } plane[I915_MAX_PIPES];
10824 struct intel_transcoder_error_state {
10825 enum transcoder cpu_transcoder;
10838 struct intel_display_error_state *
10839 intel_display_capture_error_state(struct drm_device *dev)
10841 drm_i915_private_t *dev_priv = dev->dev_private;
10842 struct intel_display_error_state *error;
10843 int transcoders[] = {
10851 if (INTEL_INFO(dev)->num_pipes == 0)
10854 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10858 if (HAS_POWER_WELL(dev))
10859 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10862 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10863 error->cursor[i].control = I915_READ(CURCNTR(i));
10864 error->cursor[i].position = I915_READ(CURPOS(i));
10865 error->cursor[i].base = I915_READ(CURBASE(i));
10867 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10868 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10869 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10872 error->plane[i].control = I915_READ(DSPCNTR(i));
10873 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10874 if (INTEL_INFO(dev)->gen <= 3) {
10875 error->plane[i].size = I915_READ(DSPSIZE(i));
10876 error->plane[i].pos = I915_READ(DSPPOS(i));
10878 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10879 error->plane[i].addr = I915_READ(DSPADDR(i));
10880 if (INTEL_INFO(dev)->gen >= 4) {
10881 error->plane[i].surface = I915_READ(DSPSURF(i));
10882 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10885 error->pipe[i].source = I915_READ(PIPESRC(i));
10888 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10889 if (HAS_DDI(dev_priv->dev))
10890 error->num_transcoders++; /* Account for eDP. */
10892 for (i = 0; i < error->num_transcoders; i++) {
10893 enum transcoder cpu_transcoder = transcoders[i];
10895 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10897 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10898 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10899 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10900 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10901 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10902 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10903 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10906 /* In the code above we read the registers without checking if the power
10907 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10908 * prevent the next I915_WRITE from detecting it and printing an error
10910 intel_uncore_clear_errors(dev);
10915 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10918 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10919 struct drm_device *dev,
10920 struct intel_display_error_state *error)
10927 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10928 if (HAS_POWER_WELL(dev))
10929 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10930 error->power_well_driver);
10932 err_printf(m, "Pipe [%d]:\n", i);
10933 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10935 err_printf(m, "Plane [%d]:\n", i);
10936 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10937 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
10938 if (INTEL_INFO(dev)->gen <= 3) {
10939 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10940 err_printf(m, " POS: %08x\n", error->plane[i].pos);
10942 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10943 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
10944 if (INTEL_INFO(dev)->gen >= 4) {
10945 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10946 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
10949 err_printf(m, "Cursor [%d]:\n", i);
10950 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10951 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10952 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
10955 for (i = 0; i < error->num_transcoders; i++) {
10956 err_printf(m, " CPU transcoder: %c\n",
10957 transcoder_name(error->transcoder[i].cpu_transcoder));
10958 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10959 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10960 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10961 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10962 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10963 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10964 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);