2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll[] = {
57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
62 static const struct dp_link_dpll pch_dpll[] = {
64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
69 static const struct dp_link_dpll vlv_dpll[] = {
71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates[] = { 162000, 270000, 540000 };
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
107 static bool is_edp(struct intel_dp *intel_dp)
109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
118 return intel_dig_port->base.base.dev;
121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
126 static void intel_dp_link_down(struct intel_dp *intel_dp);
127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
130 static void vlv_steal_power_sequencer(struct drm_device *dev,
132 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
135 intel_dp_max_link_bw(struct intel_dp *intel_dp)
137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
147 max_link_bw = DP_LINK_BW_1_62;
153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
156 u8 source_max, sink_max;
158 source_max = intel_dig_port->max_lanes;
159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
161 return min(source_max, sink_max);
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
170 * 270000 * 1 * 8 / 10 == 216000
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
182 intel_dp_link_required(int pixel_clock, int bpp)
184 return (pixel_clock * bpp + 9) / 10;
188 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
190 return (max_link_clock * max_lanes * 8) / 10;
194 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
196 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
197 struct intel_encoder *encoder = &intel_dig_port->base;
198 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
199 int max_dotclk = dev_priv->max_dotclk_freq;
202 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
204 if (type != DP_DS_PORT_TYPE_VGA)
207 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
208 intel_dp->downstream_ports);
210 if (ds_max_dotclk != 0)
211 max_dotclk = min(max_dotclk, ds_max_dotclk);
217 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
219 if (intel_dp->num_sink_rates) {
220 *sink_rates = intel_dp->sink_rates;
221 return intel_dp->num_sink_rates;
224 *sink_rates = default_rates;
226 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
230 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
232 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
233 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
236 if (IS_BROXTON(dev_priv)) {
237 *source_rates = bxt_rates;
238 size = ARRAY_SIZE(bxt_rates);
239 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
240 *source_rates = skl_rates;
241 size = ARRAY_SIZE(skl_rates);
243 *source_rates = default_rates;
244 size = ARRAY_SIZE(default_rates);
247 /* This depends on the fact that 5.4 is last value in the array */
248 if (!intel_dp_source_supports_hbr2(intel_dp))
254 static int intersect_rates(const int *source_rates, int source_len,
255 const int *sink_rates, int sink_len,
258 int i = 0, j = 0, k = 0;
260 while (i < source_len && j < sink_len) {
261 if (source_rates[i] == sink_rates[j]) {
262 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
264 common_rates[k] = source_rates[i];
268 } else if (source_rates[i] < sink_rates[j]) {
277 static int intel_dp_common_rates(struct intel_dp *intel_dp,
280 const int *source_rates, *sink_rates;
281 int source_len, sink_len;
283 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
284 source_len = intel_dp_source_rates(intel_dp, &source_rates);
286 return intersect_rates(source_rates, source_len,
287 sink_rates, sink_len,
291 static enum drm_mode_status
292 intel_dp_mode_valid(struct drm_connector *connector,
293 struct drm_display_mode *mode)
295 struct intel_dp *intel_dp = intel_attached_dp(connector);
296 struct intel_connector *intel_connector = to_intel_connector(connector);
297 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
298 int target_clock = mode->clock;
299 int max_rate, mode_rate, max_lanes, max_link_clock;
302 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
304 if (is_edp(intel_dp) && fixed_mode) {
305 if (mode->hdisplay > fixed_mode->hdisplay)
308 if (mode->vdisplay > fixed_mode->vdisplay)
311 target_clock = fixed_mode->clock;
314 max_link_clock = intel_dp_max_link_rate(intel_dp);
315 max_lanes = intel_dp_max_lane_count(intel_dp);
317 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
318 mode_rate = intel_dp_link_required(target_clock, 18);
320 if (mode_rate > max_rate || target_clock > max_dotclk)
321 return MODE_CLOCK_HIGH;
323 if (mode->clock < 10000)
324 return MODE_CLOCK_LOW;
326 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
327 return MODE_H_ILLEGAL;
332 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
339 for (i = 0; i < src_bytes; i++)
340 v |= ((uint32_t) src[i]) << ((3-i) * 8);
344 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
349 for (i = 0; i < dst_bytes; i++)
350 dst[i] = src >> ((3-i) * 8);
354 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
355 struct intel_dp *intel_dp);
357 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
358 struct intel_dp *intel_dp);
360 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
362 static void pps_lock(struct intel_dp *intel_dp)
364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
365 struct intel_encoder *encoder = &intel_dig_port->base;
366 struct drm_device *dev = encoder->base.dev;
367 struct drm_i915_private *dev_priv = to_i915(dev);
368 enum intel_display_power_domain power_domain;
371 * See vlv_power_sequencer_reset() why we need
372 * a power domain reference here.
374 power_domain = intel_display_port_aux_power_domain(encoder);
375 intel_display_power_get(dev_priv, power_domain);
377 mutex_lock(&dev_priv->pps_mutex);
380 static void pps_unlock(struct intel_dp *intel_dp)
382 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
383 struct intel_encoder *encoder = &intel_dig_port->base;
384 struct drm_device *dev = encoder->base.dev;
385 struct drm_i915_private *dev_priv = to_i915(dev);
386 enum intel_display_power_domain power_domain;
388 mutex_unlock(&dev_priv->pps_mutex);
390 power_domain = intel_display_port_aux_power_domain(encoder);
391 intel_display_power_put(dev_priv, power_domain);
395 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
397 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
398 struct drm_device *dev = intel_dig_port->base.base.dev;
399 struct drm_i915_private *dev_priv = to_i915(dev);
400 enum pipe pipe = intel_dp->pps_pipe;
401 bool pll_enabled, release_cl_override = false;
402 enum dpio_phy phy = DPIO_PHY(pipe);
403 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
406 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
407 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
408 pipe_name(pipe), port_name(intel_dig_port->port)))
411 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
412 pipe_name(pipe), port_name(intel_dig_port->port));
414 /* Preserve the BIOS-computed detected bit. This is
415 * supposed to be read-only.
417 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
418 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
419 DP |= DP_PORT_WIDTH(1);
420 DP |= DP_LINK_TRAIN_PAT_1;
422 if (IS_CHERRYVIEW(dev_priv))
423 DP |= DP_PIPE_SELECT_CHV(pipe);
424 else if (pipe == PIPE_B)
425 DP |= DP_PIPEB_SELECT;
427 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
430 * The DPLL for the pipe must be enabled for this to work.
431 * So enable temporarily it if it's not already enabled.
434 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
435 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
437 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev_priv) ?
438 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
439 DRM_ERROR("Failed to force on pll for pipe %c!\n",
446 * Similar magic as in intel_dp_enable_port().
447 * We _must_ do this port enable + disable trick
448 * to make this power seqeuencer lock onto the port.
449 * Otherwise even VDD force bit won't work.
451 I915_WRITE(intel_dp->output_reg, DP);
452 POSTING_READ(intel_dp->output_reg);
454 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
455 POSTING_READ(intel_dp->output_reg);
457 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
458 POSTING_READ(intel_dp->output_reg);
461 vlv_force_pll_off(dev, pipe);
463 if (release_cl_override)
464 chv_phy_powergate_ch(dev_priv, phy, ch, false);
469 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
471 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
472 struct drm_device *dev = intel_dig_port->base.base.dev;
473 struct drm_i915_private *dev_priv = to_i915(dev);
474 struct intel_encoder *encoder;
475 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
478 lockdep_assert_held(&dev_priv->pps_mutex);
480 /* We should never land here with regular DP ports */
481 WARN_ON(!is_edp(intel_dp));
483 if (intel_dp->pps_pipe != INVALID_PIPE)
484 return intel_dp->pps_pipe;
487 * We don't have power sequencer currently.
488 * Pick one that's not used by other ports.
490 for_each_intel_encoder(dev, encoder) {
491 struct intel_dp *tmp;
493 if (encoder->type != INTEL_OUTPUT_EDP)
496 tmp = enc_to_intel_dp(&encoder->base);
498 if (tmp->pps_pipe != INVALID_PIPE)
499 pipes &= ~(1 << tmp->pps_pipe);
503 * Didn't find one. This should not happen since there
504 * are two power sequencers and up to two eDP ports.
506 if (WARN_ON(pipes == 0))
509 pipe = ffs(pipes) - 1;
511 vlv_steal_power_sequencer(dev, pipe);
512 intel_dp->pps_pipe = pipe;
514 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
515 pipe_name(intel_dp->pps_pipe),
516 port_name(intel_dig_port->port));
518 /* init power sequencer on this pipe and port */
519 intel_dp_init_panel_power_sequencer(dev, intel_dp);
520 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
523 * Even vdd force doesn't work until we've made
524 * the power sequencer lock in on the port.
526 vlv_power_sequencer_kick(intel_dp);
528 return intel_dp->pps_pipe;
532 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
534 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
535 struct drm_device *dev = intel_dig_port->base.base.dev;
536 struct drm_i915_private *dev_priv = to_i915(dev);
538 lockdep_assert_held(&dev_priv->pps_mutex);
540 /* We should never land here with regular DP ports */
541 WARN_ON(!is_edp(intel_dp));
544 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
545 * mapping needs to be retrieved from VBT, for now just hard-code to
546 * use instance #0 always.
548 if (!intel_dp->pps_reset)
551 intel_dp->pps_reset = false;
554 * Only the HW needs to be reprogrammed, the SW state is fixed and
555 * has been setup during connector init.
557 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
562 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
565 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
568 return I915_READ(PP_STATUS(pipe)) & PP_ON;
571 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
574 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
577 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
584 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
586 vlv_pipe_check pipe_check)
590 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
591 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
592 PANEL_PORT_SELECT_MASK;
594 if (port_sel != PANEL_PORT_SELECT_VLV(port))
597 if (!pipe_check(dev_priv, pipe))
607 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
610 struct drm_device *dev = intel_dig_port->base.base.dev;
611 struct drm_i915_private *dev_priv = to_i915(dev);
612 enum port port = intel_dig_port->port;
614 lockdep_assert_held(&dev_priv->pps_mutex);
616 /* try to find a pipe with this port selected */
617 /* first pick one where the panel is on */
618 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
620 /* didn't find one? pick one where vdd is on */
621 if (intel_dp->pps_pipe == INVALID_PIPE)
622 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
623 vlv_pipe_has_vdd_on);
624 /* didn't find one? pick one with just the correct port */
625 if (intel_dp->pps_pipe == INVALID_PIPE)
626 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
629 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
630 if (intel_dp->pps_pipe == INVALID_PIPE) {
631 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
636 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
637 port_name(port), pipe_name(intel_dp->pps_pipe));
639 intel_dp_init_panel_power_sequencer(dev, intel_dp);
640 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
643 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
645 struct drm_device *dev = &dev_priv->drm;
646 struct intel_encoder *encoder;
648 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
649 !IS_BROXTON(dev_priv)))
653 * We can't grab pps_mutex here due to deadlock with power_domain
654 * mutex when power_domain functions are called while holding pps_mutex.
655 * That also means that in order to use pps_pipe the code needs to
656 * hold both a power domain reference and pps_mutex, and the power domain
657 * reference get/put must be done while _not_ holding pps_mutex.
658 * pps_{lock,unlock}() do these steps in the correct order, so one
659 * should use them always.
662 for_each_intel_encoder(dev, encoder) {
663 struct intel_dp *intel_dp;
665 if (encoder->type != INTEL_OUTPUT_EDP)
668 intel_dp = enc_to_intel_dp(&encoder->base);
669 if (IS_BROXTON(dev_priv))
670 intel_dp->pps_reset = true;
672 intel_dp->pps_pipe = INVALID_PIPE;
676 struct pps_registers {
684 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
685 struct intel_dp *intel_dp,
686 struct pps_registers *regs)
690 memset(regs, 0, sizeof(*regs));
692 if (IS_BROXTON(dev_priv))
693 pps_idx = bxt_power_sequencer_idx(intel_dp);
694 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
695 pps_idx = vlv_power_sequencer_pipe(intel_dp);
697 regs->pp_ctrl = PP_CONTROL(pps_idx);
698 regs->pp_stat = PP_STATUS(pps_idx);
699 regs->pp_on = PP_ON_DELAYS(pps_idx);
700 regs->pp_off = PP_OFF_DELAYS(pps_idx);
701 if (!IS_BROXTON(dev_priv))
702 regs->pp_div = PP_DIVISOR(pps_idx);
706 _pp_ctrl_reg(struct intel_dp *intel_dp)
708 struct pps_registers regs;
710 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
717 _pp_stat_reg(struct intel_dp *intel_dp)
719 struct pps_registers regs;
721 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
727 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
728 This function only applicable when panel PM state is not to be tracked */
729 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
732 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
734 struct drm_device *dev = intel_dp_to_dev(intel_dp);
735 struct drm_i915_private *dev_priv = to_i915(dev);
737 if (!is_edp(intel_dp) || code != SYS_RESTART)
742 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
743 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
744 i915_reg_t pp_ctrl_reg, pp_div_reg;
747 pp_ctrl_reg = PP_CONTROL(pipe);
748 pp_div_reg = PP_DIVISOR(pipe);
749 pp_div = I915_READ(pp_div_reg);
750 pp_div &= PP_REFERENCE_DIVIDER_MASK;
752 /* 0x1F write to PP_DIV_REG sets max cycle delay */
753 I915_WRITE(pp_div_reg, pp_div | 0x1F);
754 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
755 msleep(intel_dp->panel_power_cycle_delay);
758 pps_unlock(intel_dp);
763 static bool edp_have_panel_power(struct intel_dp *intel_dp)
765 struct drm_device *dev = intel_dp_to_dev(intel_dp);
766 struct drm_i915_private *dev_priv = to_i915(dev);
768 lockdep_assert_held(&dev_priv->pps_mutex);
770 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
771 intel_dp->pps_pipe == INVALID_PIPE)
774 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
777 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
779 struct drm_device *dev = intel_dp_to_dev(intel_dp);
780 struct drm_i915_private *dev_priv = to_i915(dev);
782 lockdep_assert_held(&dev_priv->pps_mutex);
784 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
785 intel_dp->pps_pipe == INVALID_PIPE)
788 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
792 intel_dp_check_edp(struct intel_dp *intel_dp)
794 struct drm_device *dev = intel_dp_to_dev(intel_dp);
795 struct drm_i915_private *dev_priv = to_i915(dev);
797 if (!is_edp(intel_dp))
800 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
801 WARN(1, "eDP powered off while attempting aux channel communication.\n");
802 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
803 I915_READ(_pp_stat_reg(intel_dp)),
804 I915_READ(_pp_ctrl_reg(intel_dp)));
809 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
811 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
812 struct drm_device *dev = intel_dig_port->base.base.dev;
813 struct drm_i915_private *dev_priv = to_i915(dev);
814 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
818 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
820 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
821 msecs_to_jiffies_timeout(10));
823 done = wait_for(C, 10) == 0;
825 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
832 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
834 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
835 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
841 * The clock divider is based off the hrawclk, and would like to run at
842 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
844 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
847 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
849 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
850 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
856 * The clock divider is based off the cdclk or PCH rawclk, and would
857 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
858 * divide by 2000 and use that
860 if (intel_dig_port->port == PORT_A)
861 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
863 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
866 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
868 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
869 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
871 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
872 /* Workaround for non-ULT HSW */
880 return ilk_get_aux_clock_divider(intel_dp, index);
883 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
886 * SKL doesn't need us to program the AUX clock divider (Hardware will
887 * derive the clock from CDCLK automatically). We still implement the
888 * get_aux_clock_divider vfunc to plug-in into the existing code.
890 return index ? 0 : 1;
893 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
896 uint32_t aux_clock_divider)
898 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
899 struct drm_i915_private *dev_priv =
900 to_i915(intel_dig_port->base.base.dev);
901 uint32_t precharge, timeout;
903 if (IS_GEN6(dev_priv))
908 if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
909 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
911 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
913 return DP_AUX_CH_CTL_SEND_BUSY |
915 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
916 DP_AUX_CH_CTL_TIME_OUT_ERROR |
918 DP_AUX_CH_CTL_RECEIVE_ERROR |
919 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
920 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
921 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
924 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
929 return DP_AUX_CH_CTL_SEND_BUSY |
931 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
932 DP_AUX_CH_CTL_TIME_OUT_ERROR |
933 DP_AUX_CH_CTL_TIME_OUT_1600us |
934 DP_AUX_CH_CTL_RECEIVE_ERROR |
935 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
936 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
937 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
941 intel_dp_aux_ch(struct intel_dp *intel_dp,
942 const uint8_t *send, int send_bytes,
943 uint8_t *recv, int recv_size)
945 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
946 struct drm_device *dev = intel_dig_port->base.base.dev;
947 struct drm_i915_private *dev_priv = to_i915(dev);
948 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
949 uint32_t aux_clock_divider;
950 int i, ret, recv_bytes;
953 bool has_aux_irq = HAS_AUX_IRQ(dev);
959 * We will be called with VDD already enabled for dpcd/edid/oui reads.
960 * In such cases we want to leave VDD enabled and it's up to upper layers
961 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
964 vdd = edp_panel_vdd_on(intel_dp);
966 /* dp aux is extremely sensitive to irq latency, hence request the
967 * lowest possible wakeup latency and so prevent the cpu from going into
970 pm_qos_update_request(&dev_priv->pm_qos, 0);
972 intel_dp_check_edp(intel_dp);
974 /* Try to wait for any previous AUX channel activity */
975 for (try = 0; try < 3; try++) {
976 status = I915_READ_NOTRACE(ch_ctl);
977 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
983 static u32 last_status = -1;
984 const u32 status = I915_READ(ch_ctl);
986 if (status != last_status) {
987 WARN(1, "dp_aux_ch not started status 0x%08x\n",
989 last_status = status;
996 /* Only 5 data registers! */
997 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1002 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1003 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1008 /* Must try at least 3 times according to DP spec */
1009 for (try = 0; try < 5; try++) {
1010 /* Load the send data into the aux channel data registers */
1011 for (i = 0; i < send_bytes; i += 4)
1012 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1013 intel_dp_pack_aux(send + i,
1016 /* Send the command and wait for it to complete */
1017 I915_WRITE(ch_ctl, send_ctl);
1019 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1021 /* Clear done status and any errors */
1024 DP_AUX_CH_CTL_DONE |
1025 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1026 DP_AUX_CH_CTL_RECEIVE_ERROR);
1028 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1031 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1032 * 400us delay required for errors and timeouts
1033 * Timeout errors from the HW already meet this
1034 * requirement so skip to next iteration
1036 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1037 usleep_range(400, 500);
1040 if (status & DP_AUX_CH_CTL_DONE)
1045 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1046 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1052 /* Check for timeout or receive error.
1053 * Timeouts occur when the sink is not connected
1055 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1056 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1061 /* Timeouts occur when the device isn't connected, so they're
1062 * "normal" -- don't fill the kernel log with these */
1063 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1064 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1069 /* Unload any bytes sent back from the other side */
1070 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1071 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1074 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1075 * We have no idea of what happened so we return -EBUSY so
1076 * drm layer takes care for the necessary retries.
1078 if (recv_bytes == 0 || recv_bytes > 20) {
1079 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1082 * FIXME: This patch was created on top of a series that
1083 * organize the retries at drm level. There EBUSY should
1084 * also take care for 1ms wait before retrying.
1085 * That aux retries re-org is still needed and after that is
1086 * merged we remove this sleep from here.
1088 usleep_range(1000, 1500);
1093 if (recv_bytes > recv_size)
1094 recv_bytes = recv_size;
1096 for (i = 0; i < recv_bytes; i += 4)
1097 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1098 recv + i, recv_bytes - i);
1102 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1105 edp_panel_vdd_off(intel_dp, false);
1107 pps_unlock(intel_dp);
1112 #define BARE_ADDRESS_SIZE 3
1113 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1115 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1117 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1118 uint8_t txbuf[20], rxbuf[20];
1119 size_t txsize, rxsize;
1122 txbuf[0] = (msg->request << 4) |
1123 ((msg->address >> 16) & 0xf);
1124 txbuf[1] = (msg->address >> 8) & 0xff;
1125 txbuf[2] = msg->address & 0xff;
1126 txbuf[3] = msg->size - 1;
1128 switch (msg->request & ~DP_AUX_I2C_MOT) {
1129 case DP_AUX_NATIVE_WRITE:
1130 case DP_AUX_I2C_WRITE:
1131 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1132 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1133 rxsize = 2; /* 0 or 1 data bytes */
1135 if (WARN_ON(txsize > 20))
1138 WARN_ON(!msg->buffer != !msg->size);
1141 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1143 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1145 msg->reply = rxbuf[0] >> 4;
1148 /* Number of bytes written in a short write. */
1149 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1151 /* Return payload size. */
1157 case DP_AUX_NATIVE_READ:
1158 case DP_AUX_I2C_READ:
1159 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1160 rxsize = msg->size + 1;
1162 if (WARN_ON(rxsize > 20))
1165 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1167 msg->reply = rxbuf[0] >> 4;
1169 * Assume happy day, and copy the data. The caller is
1170 * expected to check msg->reply before touching it.
1172 * Return payload size.
1175 memcpy(msg->buffer, rxbuf + 1, ret);
1187 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1190 const struct ddi_vbt_port_info *info =
1191 &dev_priv->vbt.ddi_port_info[port];
1194 if (!info->alternate_aux_channel) {
1195 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1196 port_name(port), port_name(port));
1200 switch (info->alternate_aux_channel) {
1214 MISSING_CASE(info->alternate_aux_channel);
1219 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1220 port_name(aux_port), port_name(port));
1225 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1232 return DP_AUX_CH_CTL(port);
1235 return DP_AUX_CH_CTL(PORT_B);
1239 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1240 enum port port, int index)
1246 return DP_AUX_CH_DATA(port, index);
1249 return DP_AUX_CH_DATA(PORT_B, index);
1253 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1258 return DP_AUX_CH_CTL(port);
1262 return PCH_DP_AUX_CH_CTL(port);
1265 return DP_AUX_CH_CTL(PORT_A);
1269 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1270 enum port port, int index)
1274 return DP_AUX_CH_DATA(port, index);
1278 return PCH_DP_AUX_CH_DATA(port, index);
1281 return DP_AUX_CH_DATA(PORT_A, index);
1285 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1293 return DP_AUX_CH_CTL(port);
1296 return DP_AUX_CH_CTL(PORT_A);
1300 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1301 enum port port, int index)
1308 return DP_AUX_CH_DATA(port, index);
1311 return DP_AUX_CH_DATA(PORT_A, index);
1315 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1318 if (INTEL_INFO(dev_priv)->gen >= 9)
1319 return skl_aux_ctl_reg(dev_priv, port);
1320 else if (HAS_PCH_SPLIT(dev_priv))
1321 return ilk_aux_ctl_reg(dev_priv, port);
1323 return g4x_aux_ctl_reg(dev_priv, port);
1326 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1327 enum port port, int index)
1329 if (INTEL_INFO(dev_priv)->gen >= 9)
1330 return skl_aux_data_reg(dev_priv, port, index);
1331 else if (HAS_PCH_SPLIT(dev_priv))
1332 return ilk_aux_data_reg(dev_priv, port, index);
1334 return g4x_aux_data_reg(dev_priv, port, index);
1337 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1339 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1340 enum port port = intel_aux_port(dev_priv,
1341 dp_to_dig_port(intel_dp)->port);
1344 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1345 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1346 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1350 intel_dp_aux_fini(struct intel_dp *intel_dp)
1352 kfree(intel_dp->aux.name);
1356 intel_dp_aux_init(struct intel_dp *intel_dp)
1358 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1359 enum port port = intel_dig_port->port;
1361 intel_aux_reg_init(intel_dp);
1362 drm_dp_aux_init(&intel_dp->aux);
1364 /* Failure to allocate our preferred name is not critical */
1365 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1366 intel_dp->aux.transfer = intel_dp_aux_transfer;
1369 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1371 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1372 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1374 if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1375 IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
1382 intel_dp_set_clock(struct intel_encoder *encoder,
1383 struct intel_crtc_state *pipe_config)
1385 struct drm_device *dev = encoder->base.dev;
1386 struct drm_i915_private *dev_priv = to_i915(dev);
1387 const struct dp_link_dpll *divisor = NULL;
1390 if (IS_G4X(dev_priv)) {
1391 divisor = gen4_dpll;
1392 count = ARRAY_SIZE(gen4_dpll);
1393 } else if (HAS_PCH_SPLIT(dev_priv)) {
1395 count = ARRAY_SIZE(pch_dpll);
1396 } else if (IS_CHERRYVIEW(dev_priv)) {
1398 count = ARRAY_SIZE(chv_dpll);
1399 } else if (IS_VALLEYVIEW(dev_priv)) {
1401 count = ARRAY_SIZE(vlv_dpll);
1404 if (divisor && count) {
1405 for (i = 0; i < count; i++) {
1406 if (pipe_config->port_clock == divisor[i].clock) {
1407 pipe_config->dpll = divisor[i].dpll;
1408 pipe_config->clock_set = true;
1415 static void snprintf_int_array(char *str, size_t len,
1416 const int *array, int nelem)
1422 for (i = 0; i < nelem; i++) {
1423 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1431 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1433 const int *source_rates, *sink_rates;
1434 int source_len, sink_len, common_len;
1435 int common_rates[DP_MAX_SUPPORTED_RATES];
1436 char str[128]; /* FIXME: too big for stack? */
1438 if ((drm_debug & DRM_UT_KMS) == 0)
1441 source_len = intel_dp_source_rates(intel_dp, &source_rates);
1442 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1443 DRM_DEBUG_KMS("source rates: %s\n", str);
1445 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1446 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1447 DRM_DEBUG_KMS("sink rates: %s\n", str);
1449 common_len = intel_dp_common_rates(intel_dp, common_rates);
1450 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1451 DRM_DEBUG_KMS("common rates: %s\n", str);
1455 __intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc)
1457 u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI :
1460 return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) ==
1464 bool intel_dp_read_desc(struct intel_dp *intel_dp)
1466 struct intel_dp_desc *desc = &intel_dp->desc;
1467 bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] &
1471 if (!__intel_dp_read_desc(intel_dp, desc))
1474 dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id));
1475 DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n",
1476 drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink",
1477 (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)",
1478 dev_id_len, desc->device_id,
1479 desc->hw_rev >> 4, desc->hw_rev & 0xf,
1480 desc->sw_major_rev, desc->sw_minor_rev);
1485 static int rate_to_index(int find, const int *rates)
1489 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1490 if (find == rates[i])
1497 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1499 int rates[DP_MAX_SUPPORTED_RATES] = {};
1502 len = intel_dp_common_rates(intel_dp, rates);
1503 if (WARN_ON(len <= 0))
1506 return rates[len - 1];
1509 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1511 return rate_to_index(rate, intel_dp->sink_rates);
1514 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1515 uint8_t *link_bw, uint8_t *rate_select)
1517 if (intel_dp->num_sink_rates) {
1520 intel_dp_rate_select(intel_dp, port_clock);
1522 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1527 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1528 struct intel_crtc_state *pipe_config)
1532 bpp = pipe_config->pipe_bpp;
1533 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1536 bpp = min(bpp, 3*bpc);
1542 intel_dp_compute_config(struct intel_encoder *encoder,
1543 struct intel_crtc_state *pipe_config,
1544 struct drm_connector_state *conn_state)
1546 struct drm_device *dev = encoder->base.dev;
1547 struct drm_i915_private *dev_priv = to_i915(dev);
1548 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1549 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1550 enum port port = dp_to_dig_port(intel_dp)->port;
1551 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1552 struct intel_connector *intel_connector = intel_dp->attached_connector;
1553 int lane_count, clock;
1554 int min_lane_count = 1;
1555 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1556 /* Conveniently, the link BW constants become indices with a shift...*/
1560 int link_avail, link_clock;
1561 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1563 uint8_t link_bw, rate_select;
1565 common_len = intel_dp_common_rates(intel_dp, common_rates);
1567 /* No common link rates between source and sink */
1568 WARN_ON(common_len <= 0);
1570 max_clock = common_len - 1;
1572 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1573 pipe_config->has_pch_encoder = true;
1575 pipe_config->has_drrs = false;
1576 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1578 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1579 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1582 if (INTEL_INFO(dev)->gen >= 9) {
1584 ret = skl_update_scaler_crtc(pipe_config);
1589 if (HAS_GMCH_DISPLAY(dev_priv))
1590 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1591 intel_connector->panel.fitting_mode);
1593 intel_pch_panel_fitting(intel_crtc, pipe_config,
1594 intel_connector->panel.fitting_mode);
1597 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1600 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1601 "max bw %d pixel clock %iKHz\n",
1602 max_lane_count, common_rates[max_clock],
1603 adjusted_mode->crtc_clock);
1605 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1606 * bpc in between. */
1607 bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1608 if (is_edp(intel_dp)) {
1610 /* Get bpp from vbt only for panels that dont have bpp in edid */
1611 if (intel_connector->base.display_info.bpc == 0 &&
1612 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1613 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1614 dev_priv->vbt.edp.bpp);
1615 bpp = dev_priv->vbt.edp.bpp;
1619 * Use the maximum clock and number of lanes the eDP panel
1620 * advertizes being capable of. The panels are generally
1621 * designed to support only a single clock and lane
1622 * configuration, and typically these values correspond to the
1623 * native resolution of the panel.
1625 min_lane_count = max_lane_count;
1626 min_clock = max_clock;
1629 for (; bpp >= 6*3; bpp -= 2*3) {
1630 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1633 for (clock = min_clock; clock <= max_clock; clock++) {
1634 for (lane_count = min_lane_count;
1635 lane_count <= max_lane_count;
1638 link_clock = common_rates[clock];
1639 link_avail = intel_dp_max_data_rate(link_clock,
1642 if (mode_rate <= link_avail) {
1652 if (intel_dp->color_range_auto) {
1655 * CEA-861-E - 5.1 Default Encoding Parameters
1656 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1658 pipe_config->limited_color_range =
1659 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1661 pipe_config->limited_color_range =
1662 intel_dp->limited_color_range;
1665 pipe_config->lane_count = lane_count;
1667 pipe_config->pipe_bpp = bpp;
1668 pipe_config->port_clock = common_rates[clock];
1670 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1671 &link_bw, &rate_select);
1673 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1674 link_bw, rate_select, pipe_config->lane_count,
1675 pipe_config->port_clock, bpp);
1676 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1677 mode_rate, link_avail);
1679 intel_link_compute_m_n(bpp, lane_count,
1680 adjusted_mode->crtc_clock,
1681 pipe_config->port_clock,
1682 &pipe_config->dp_m_n);
1684 if (intel_connector->panel.downclock_mode != NULL &&
1685 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1686 pipe_config->has_drrs = true;
1687 intel_link_compute_m_n(bpp, lane_count,
1688 intel_connector->panel.downclock_mode->clock,
1689 pipe_config->port_clock,
1690 &pipe_config->dp_m2_n2);
1694 * DPLL0 VCO may need to be adjusted to get the correct
1695 * clock for eDP. This will affect cdclk as well.
1697 if (is_edp(intel_dp) &&
1698 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1701 switch (pipe_config->port_clock / 2) {
1711 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1714 if (!HAS_DDI(dev_priv))
1715 intel_dp_set_clock(encoder, pipe_config);
1720 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1721 int link_rate, uint8_t lane_count,
1724 intel_dp->link_rate = link_rate;
1725 intel_dp->lane_count = lane_count;
1726 intel_dp->link_mst = link_mst;
1729 static void intel_dp_prepare(struct intel_encoder *encoder,
1730 struct intel_crtc_state *pipe_config)
1732 struct drm_device *dev = encoder->base.dev;
1733 struct drm_i915_private *dev_priv = to_i915(dev);
1734 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1735 enum port port = dp_to_dig_port(intel_dp)->port;
1736 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1737 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1739 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1740 pipe_config->lane_count,
1741 intel_crtc_has_type(pipe_config,
1742 INTEL_OUTPUT_DP_MST));
1745 * There are four kinds of DP registers:
1752 * IBX PCH and CPU are the same for almost everything,
1753 * except that the CPU DP PLL is configured in this
1756 * CPT PCH is quite different, having many bits moved
1757 * to the TRANS_DP_CTL register instead. That
1758 * configuration happens (oddly) in ironlake_pch_enable
1761 /* Preserve the BIOS-computed detected bit. This is
1762 * supposed to be read-only.
1764 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1766 /* Handle DP bits in common between all three register formats */
1767 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1768 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1770 /* Split out the IBX/CPU vs CPT settings */
1772 if (IS_GEN7(dev_priv) && port == PORT_A) {
1773 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1774 intel_dp->DP |= DP_SYNC_HS_HIGH;
1775 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1776 intel_dp->DP |= DP_SYNC_VS_HIGH;
1777 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1779 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1780 intel_dp->DP |= DP_ENHANCED_FRAMING;
1782 intel_dp->DP |= crtc->pipe << 29;
1783 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1786 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1788 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1789 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1790 trans_dp |= TRANS_DP_ENH_FRAMING;
1792 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1793 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1795 if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
1796 !IS_CHERRYVIEW(dev_priv) &&
1797 pipe_config->limited_color_range)
1798 intel_dp->DP |= DP_COLOR_RANGE_16_235;
1800 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1801 intel_dp->DP |= DP_SYNC_HS_HIGH;
1802 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1803 intel_dp->DP |= DP_SYNC_VS_HIGH;
1804 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1806 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1807 intel_dp->DP |= DP_ENHANCED_FRAMING;
1809 if (IS_CHERRYVIEW(dev_priv))
1810 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1811 else if (crtc->pipe == PIPE_B)
1812 intel_dp->DP |= DP_PIPEB_SELECT;
1816 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1817 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1819 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1820 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1822 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1823 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1825 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1826 struct intel_dp *intel_dp);
1828 static void wait_panel_status(struct intel_dp *intel_dp,
1832 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1833 struct drm_i915_private *dev_priv = to_i915(dev);
1834 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1836 lockdep_assert_held(&dev_priv->pps_mutex);
1838 intel_pps_verify_state(dev_priv, intel_dp);
1840 pp_stat_reg = _pp_stat_reg(intel_dp);
1841 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1843 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1845 I915_READ(pp_stat_reg),
1846 I915_READ(pp_ctrl_reg));
1848 if (intel_wait_for_register(dev_priv,
1849 pp_stat_reg, mask, value,
1851 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1852 I915_READ(pp_stat_reg),
1853 I915_READ(pp_ctrl_reg));
1855 DRM_DEBUG_KMS("Wait complete\n");
1858 static void wait_panel_on(struct intel_dp *intel_dp)
1860 DRM_DEBUG_KMS("Wait for panel power on\n");
1861 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1864 static void wait_panel_off(struct intel_dp *intel_dp)
1866 DRM_DEBUG_KMS("Wait for panel power off time\n");
1867 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1870 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1872 ktime_t panel_power_on_time;
1873 s64 panel_power_off_duration;
1875 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1877 /* take the difference of currrent time and panel power off time
1878 * and then make panel wait for t11_t12 if needed. */
1879 panel_power_on_time = ktime_get_boottime();
1880 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1882 /* When we disable the VDD override bit last we have to do the manual
1884 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1885 wait_remaining_ms_from_jiffies(jiffies,
1886 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1888 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1891 static void wait_backlight_on(struct intel_dp *intel_dp)
1893 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1894 intel_dp->backlight_on_delay);
1897 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1899 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1900 intel_dp->backlight_off_delay);
1903 /* Read the current pp_control value, unlocking the register if it
1907 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1909 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1910 struct drm_i915_private *dev_priv = to_i915(dev);
1913 lockdep_assert_held(&dev_priv->pps_mutex);
1915 control = I915_READ(_pp_ctrl_reg(intel_dp));
1916 if (WARN_ON(!HAS_DDI(dev_priv) &&
1917 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
1918 control &= ~PANEL_UNLOCK_MASK;
1919 control |= PANEL_UNLOCK_REGS;
1925 * Must be paired with edp_panel_vdd_off().
1926 * Must hold pps_mutex around the whole on/off sequence.
1927 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1929 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1931 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1932 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1933 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1934 struct drm_i915_private *dev_priv = to_i915(dev);
1935 enum intel_display_power_domain power_domain;
1937 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1938 bool need_to_disable = !intel_dp->want_panel_vdd;
1940 lockdep_assert_held(&dev_priv->pps_mutex);
1942 if (!is_edp(intel_dp))
1945 cancel_delayed_work(&intel_dp->panel_vdd_work);
1946 intel_dp->want_panel_vdd = true;
1948 if (edp_have_panel_vdd(intel_dp))
1949 return need_to_disable;
1951 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1952 intel_display_power_get(dev_priv, power_domain);
1954 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1955 port_name(intel_dig_port->port));
1957 if (!edp_have_panel_power(intel_dp))
1958 wait_panel_power_cycle(intel_dp);
1960 pp = ironlake_get_pp_control(intel_dp);
1961 pp |= EDP_FORCE_VDD;
1963 pp_stat_reg = _pp_stat_reg(intel_dp);
1964 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1966 I915_WRITE(pp_ctrl_reg, pp);
1967 POSTING_READ(pp_ctrl_reg);
1968 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1969 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1971 * If the panel wasn't on, delay before accessing aux channel
1973 if (!edp_have_panel_power(intel_dp)) {
1974 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1975 port_name(intel_dig_port->port));
1976 msleep(intel_dp->panel_power_up_delay);
1979 return need_to_disable;
1983 * Must be paired with intel_edp_panel_vdd_off() or
1984 * intel_edp_panel_off().
1985 * Nested calls to these functions are not allowed since
1986 * we drop the lock. Caller must use some higher level
1987 * locking to prevent nested calls from other threads.
1989 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1993 if (!is_edp(intel_dp))
1997 vdd = edp_panel_vdd_on(intel_dp);
1998 pps_unlock(intel_dp);
2000 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2001 port_name(dp_to_dig_port(intel_dp)->port));
2004 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2006 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2007 struct drm_i915_private *dev_priv = to_i915(dev);
2008 struct intel_digital_port *intel_dig_port =
2009 dp_to_dig_port(intel_dp);
2010 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2011 enum intel_display_power_domain power_domain;
2013 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2015 lockdep_assert_held(&dev_priv->pps_mutex);
2017 WARN_ON(intel_dp->want_panel_vdd);
2019 if (!edp_have_panel_vdd(intel_dp))
2022 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2023 port_name(intel_dig_port->port));
2025 pp = ironlake_get_pp_control(intel_dp);
2026 pp &= ~EDP_FORCE_VDD;
2028 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2029 pp_stat_reg = _pp_stat_reg(intel_dp);
2031 I915_WRITE(pp_ctrl_reg, pp);
2032 POSTING_READ(pp_ctrl_reg);
2034 /* Make sure sequencer is idle before allowing subsequent activity */
2035 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2036 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2038 if ((pp & PANEL_POWER_ON) == 0)
2039 intel_dp->panel_power_off_time = ktime_get_boottime();
2041 power_domain = intel_display_port_aux_power_domain(intel_encoder);
2042 intel_display_power_put(dev_priv, power_domain);
2045 static void edp_panel_vdd_work(struct work_struct *__work)
2047 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2048 struct intel_dp, panel_vdd_work);
2051 if (!intel_dp->want_panel_vdd)
2052 edp_panel_vdd_off_sync(intel_dp);
2053 pps_unlock(intel_dp);
2056 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2058 unsigned long delay;
2061 * Queue the timer to fire a long time from now (relative to the power
2062 * down delay) to keep the panel power up across a sequence of
2065 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2066 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2070 * Must be paired with edp_panel_vdd_on().
2071 * Must hold pps_mutex around the whole on/off sequence.
2072 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2074 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2076 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2078 lockdep_assert_held(&dev_priv->pps_mutex);
2080 if (!is_edp(intel_dp))
2083 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2084 port_name(dp_to_dig_port(intel_dp)->port));
2086 intel_dp->want_panel_vdd = false;
2089 edp_panel_vdd_off_sync(intel_dp);
2091 edp_panel_vdd_schedule_off(intel_dp);
2094 static void edp_panel_on(struct intel_dp *intel_dp)
2096 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2097 struct drm_i915_private *dev_priv = to_i915(dev);
2099 i915_reg_t pp_ctrl_reg;
2101 lockdep_assert_held(&dev_priv->pps_mutex);
2103 if (!is_edp(intel_dp))
2106 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2107 port_name(dp_to_dig_port(intel_dp)->port));
2109 if (WARN(edp_have_panel_power(intel_dp),
2110 "eDP port %c panel power already on\n",
2111 port_name(dp_to_dig_port(intel_dp)->port)))
2114 wait_panel_power_cycle(intel_dp);
2116 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2117 pp = ironlake_get_pp_control(intel_dp);
2118 if (IS_GEN5(dev_priv)) {
2119 /* ILK workaround: disable reset around power sequence */
2120 pp &= ~PANEL_POWER_RESET;
2121 I915_WRITE(pp_ctrl_reg, pp);
2122 POSTING_READ(pp_ctrl_reg);
2125 pp |= PANEL_POWER_ON;
2126 if (!IS_GEN5(dev_priv))
2127 pp |= PANEL_POWER_RESET;
2129 I915_WRITE(pp_ctrl_reg, pp);
2130 POSTING_READ(pp_ctrl_reg);
2132 wait_panel_on(intel_dp);
2133 intel_dp->last_power_on = jiffies;
2135 if (IS_GEN5(dev_priv)) {
2136 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2137 I915_WRITE(pp_ctrl_reg, pp);
2138 POSTING_READ(pp_ctrl_reg);
2142 void intel_edp_panel_on(struct intel_dp *intel_dp)
2144 if (!is_edp(intel_dp))
2148 edp_panel_on(intel_dp);
2149 pps_unlock(intel_dp);
2153 static void edp_panel_off(struct intel_dp *intel_dp)
2155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2156 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2157 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2158 struct drm_i915_private *dev_priv = to_i915(dev);
2159 enum intel_display_power_domain power_domain;
2161 i915_reg_t pp_ctrl_reg;
2163 lockdep_assert_held(&dev_priv->pps_mutex);
2165 if (!is_edp(intel_dp))
2168 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2169 port_name(dp_to_dig_port(intel_dp)->port));
2171 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2172 port_name(dp_to_dig_port(intel_dp)->port));
2174 pp = ironlake_get_pp_control(intel_dp);
2175 /* We need to switch off panel power _and_ force vdd, for otherwise some
2176 * panels get very unhappy and cease to work. */
2177 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2180 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2182 intel_dp->want_panel_vdd = false;
2184 I915_WRITE(pp_ctrl_reg, pp);
2185 POSTING_READ(pp_ctrl_reg);
2187 intel_dp->panel_power_off_time = ktime_get_boottime();
2188 wait_panel_off(intel_dp);
2190 /* We got a reference when we enabled the VDD. */
2191 power_domain = intel_display_port_aux_power_domain(intel_encoder);
2192 intel_display_power_put(dev_priv, power_domain);
2195 void intel_edp_panel_off(struct intel_dp *intel_dp)
2197 if (!is_edp(intel_dp))
2201 edp_panel_off(intel_dp);
2202 pps_unlock(intel_dp);
2205 /* Enable backlight in the panel power control. */
2206 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2208 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2209 struct drm_device *dev = intel_dig_port->base.base.dev;
2210 struct drm_i915_private *dev_priv = to_i915(dev);
2212 i915_reg_t pp_ctrl_reg;
2215 * If we enable the backlight right away following a panel power
2216 * on, we may see slight flicker as the panel syncs with the eDP
2217 * link. So delay a bit to make sure the image is solid before
2218 * allowing it to appear.
2220 wait_backlight_on(intel_dp);
2224 pp = ironlake_get_pp_control(intel_dp);
2225 pp |= EDP_BLC_ENABLE;
2227 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2229 I915_WRITE(pp_ctrl_reg, pp);
2230 POSTING_READ(pp_ctrl_reg);
2232 pps_unlock(intel_dp);
2235 /* Enable backlight PWM and backlight PP control. */
2236 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2238 if (!is_edp(intel_dp))
2241 DRM_DEBUG_KMS("\n");
2243 intel_panel_enable_backlight(intel_dp->attached_connector);
2244 _intel_edp_backlight_on(intel_dp);
2247 /* Disable backlight in the panel power control. */
2248 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2250 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2251 struct drm_i915_private *dev_priv = to_i915(dev);
2253 i915_reg_t pp_ctrl_reg;
2255 if (!is_edp(intel_dp))
2260 pp = ironlake_get_pp_control(intel_dp);
2261 pp &= ~EDP_BLC_ENABLE;
2263 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2265 I915_WRITE(pp_ctrl_reg, pp);
2266 POSTING_READ(pp_ctrl_reg);
2268 pps_unlock(intel_dp);
2270 intel_dp->last_backlight_off = jiffies;
2271 edp_wait_backlight_off(intel_dp);
2274 /* Disable backlight PP control and backlight PWM. */
2275 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2277 if (!is_edp(intel_dp))
2280 DRM_DEBUG_KMS("\n");
2282 _intel_edp_backlight_off(intel_dp);
2283 intel_panel_disable_backlight(intel_dp->attached_connector);
2287 * Hook for controlling the panel power control backlight through the bl_power
2288 * sysfs attribute. Take care to handle multiple calls.
2290 static void intel_edp_backlight_power(struct intel_connector *connector,
2293 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2297 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2298 pps_unlock(intel_dp);
2300 if (is_enabled == enable)
2303 DRM_DEBUG_KMS("panel power control backlight %s\n",
2304 enable ? "enable" : "disable");
2307 _intel_edp_backlight_on(intel_dp);
2309 _intel_edp_backlight_off(intel_dp);
2312 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2314 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2315 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2316 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2318 I915_STATE_WARN(cur_state != state,
2319 "DP port %c state assertion failure (expected %s, current %s)\n",
2320 port_name(dig_port->port),
2321 onoff(state), onoff(cur_state));
2323 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2325 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2327 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2329 I915_STATE_WARN(cur_state != state,
2330 "eDP PLL state assertion failure (expected %s, current %s)\n",
2331 onoff(state), onoff(cur_state));
2333 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2334 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2336 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2337 struct intel_crtc_state *pipe_config)
2339 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2340 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2342 assert_pipe_disabled(dev_priv, crtc->pipe);
2343 assert_dp_port_disabled(intel_dp);
2344 assert_edp_pll_disabled(dev_priv);
2346 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2347 pipe_config->port_clock);
2349 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2351 if (pipe_config->port_clock == 162000)
2352 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2354 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2356 I915_WRITE(DP_A, intel_dp->DP);
2361 * [DevILK] Work around required when enabling DP PLL
2362 * while a pipe is enabled going to FDI:
2363 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2364 * 2. Program DP PLL enable
2366 if (IS_GEN5(dev_priv))
2367 intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe);
2369 intel_dp->DP |= DP_PLL_ENABLE;
2371 I915_WRITE(DP_A, intel_dp->DP);
2376 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2378 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2379 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2380 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2382 assert_pipe_disabled(dev_priv, crtc->pipe);
2383 assert_dp_port_disabled(intel_dp);
2384 assert_edp_pll_enabled(dev_priv);
2386 DRM_DEBUG_KMS("disabling eDP PLL\n");
2388 intel_dp->DP &= ~DP_PLL_ENABLE;
2390 I915_WRITE(DP_A, intel_dp->DP);
2395 /* If the sink supports it, try to set the power state appropriately */
2396 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2400 /* Should have a valid DPCD by this point */
2401 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2404 if (mode != DRM_MODE_DPMS_ON) {
2405 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2409 * When turning on, we need to retry for 1ms to give the sink
2412 for (i = 0; i < 3; i++) {
2413 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2422 DRM_DEBUG_KMS("failed to %s sink power state\n",
2423 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2426 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2429 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2430 enum port port = dp_to_dig_port(intel_dp)->port;
2431 struct drm_device *dev = encoder->base.dev;
2432 struct drm_i915_private *dev_priv = to_i915(dev);
2433 enum intel_display_power_domain power_domain;
2437 power_domain = intel_display_port_power_domain(encoder);
2438 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2443 tmp = I915_READ(intel_dp->output_reg);
2445 if (!(tmp & DP_PORT_EN))
2448 if (IS_GEN7(dev_priv) && port == PORT_A) {
2449 *pipe = PORT_TO_PIPE_CPT(tmp);
2450 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2453 for_each_pipe(dev_priv, p) {
2454 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2455 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2463 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2464 i915_mmio_reg_offset(intel_dp->output_reg));
2465 } else if (IS_CHERRYVIEW(dev_priv)) {
2466 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2468 *pipe = PORT_TO_PIPE(tmp);
2474 intel_display_power_put(dev_priv, power_domain);
2479 static void intel_dp_get_config(struct intel_encoder *encoder,
2480 struct intel_crtc_state *pipe_config)
2482 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2484 struct drm_device *dev = encoder->base.dev;
2485 struct drm_i915_private *dev_priv = to_i915(dev);
2486 enum port port = dp_to_dig_port(intel_dp)->port;
2487 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2489 tmp = I915_READ(intel_dp->output_reg);
2491 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2493 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2494 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2496 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2497 flags |= DRM_MODE_FLAG_PHSYNC;
2499 flags |= DRM_MODE_FLAG_NHSYNC;
2501 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2502 flags |= DRM_MODE_FLAG_PVSYNC;
2504 flags |= DRM_MODE_FLAG_NVSYNC;
2506 if (tmp & DP_SYNC_HS_HIGH)
2507 flags |= DRM_MODE_FLAG_PHSYNC;
2509 flags |= DRM_MODE_FLAG_NHSYNC;
2511 if (tmp & DP_SYNC_VS_HIGH)
2512 flags |= DRM_MODE_FLAG_PVSYNC;
2514 flags |= DRM_MODE_FLAG_NVSYNC;
2517 pipe_config->base.adjusted_mode.flags |= flags;
2519 if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
2520 !IS_CHERRYVIEW(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2521 pipe_config->limited_color_range = true;
2523 pipe_config->lane_count =
2524 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2526 intel_dp_get_m_n(crtc, pipe_config);
2528 if (port == PORT_A) {
2529 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2530 pipe_config->port_clock = 162000;
2532 pipe_config->port_clock = 270000;
2535 pipe_config->base.adjusted_mode.crtc_clock =
2536 intel_dotclock_calculate(pipe_config->port_clock,
2537 &pipe_config->dp_m_n);
2539 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2540 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2542 * This is a big fat ugly hack.
2544 * Some machines in UEFI boot mode provide us a VBT that has 18
2545 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2546 * unknown we fail to light up. Yet the same BIOS boots up with
2547 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2548 * max, not what it tells us to use.
2550 * Note: This will still be broken if the eDP panel is not lit
2551 * up by the BIOS, and thus we can't get the mode at module
2554 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2555 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2556 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2560 static void intel_disable_dp(struct intel_encoder *encoder,
2561 struct intel_crtc_state *old_crtc_state,
2562 struct drm_connector_state *old_conn_state)
2564 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2565 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2567 if (old_crtc_state->has_audio)
2568 intel_audio_codec_disable(encoder);
2570 if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2571 intel_psr_disable(intel_dp);
2573 /* Make sure the panel is off before trying to change the mode. But also
2574 * ensure that we have vdd while we switch off the panel. */
2575 intel_edp_panel_vdd_on(intel_dp);
2576 intel_edp_backlight_off(intel_dp);
2577 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2578 intel_edp_panel_off(intel_dp);
2580 /* disable the port before the pipe on g4x */
2581 if (INTEL_GEN(dev_priv) < 5)
2582 intel_dp_link_down(intel_dp);
2585 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2586 struct intel_crtc_state *old_crtc_state,
2587 struct drm_connector_state *old_conn_state)
2589 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2590 enum port port = dp_to_dig_port(intel_dp)->port;
2592 intel_dp_link_down(intel_dp);
2594 /* Only ilk+ has port A */
2596 ironlake_edp_pll_off(intel_dp);
2599 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2600 struct intel_crtc_state *old_crtc_state,
2601 struct drm_connector_state *old_conn_state)
2603 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2605 intel_dp_link_down(intel_dp);
2608 static void chv_post_disable_dp(struct intel_encoder *encoder,
2609 struct intel_crtc_state *old_crtc_state,
2610 struct drm_connector_state *old_conn_state)
2612 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2613 struct drm_device *dev = encoder->base.dev;
2614 struct drm_i915_private *dev_priv = to_i915(dev);
2616 intel_dp_link_down(intel_dp);
2618 mutex_lock(&dev_priv->sb_lock);
2620 /* Assert data lane reset */
2621 chv_data_lane_soft_reset(encoder, true);
2623 mutex_unlock(&dev_priv->sb_lock);
2627 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2629 uint8_t dp_train_pat)
2631 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2632 struct drm_device *dev = intel_dig_port->base.base.dev;
2633 struct drm_i915_private *dev_priv = to_i915(dev);
2634 enum port port = intel_dig_port->port;
2636 if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2637 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2638 dp_train_pat & DP_TRAINING_PATTERN_MASK);
2640 if (HAS_DDI(dev_priv)) {
2641 uint32_t temp = I915_READ(DP_TP_CTL(port));
2643 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2644 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2646 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2648 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2649 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2650 case DP_TRAINING_PATTERN_DISABLE:
2651 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2654 case DP_TRAINING_PATTERN_1:
2655 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2657 case DP_TRAINING_PATTERN_2:
2658 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2660 case DP_TRAINING_PATTERN_3:
2661 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2664 I915_WRITE(DP_TP_CTL(port), temp);
2666 } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2667 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2668 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2670 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2671 case DP_TRAINING_PATTERN_DISABLE:
2672 *DP |= DP_LINK_TRAIN_OFF_CPT;
2674 case DP_TRAINING_PATTERN_1:
2675 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2677 case DP_TRAINING_PATTERN_2:
2678 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2680 case DP_TRAINING_PATTERN_3:
2681 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2682 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2687 if (IS_CHERRYVIEW(dev_priv))
2688 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2690 *DP &= ~DP_LINK_TRAIN_MASK;
2692 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2693 case DP_TRAINING_PATTERN_DISABLE:
2694 *DP |= DP_LINK_TRAIN_OFF;
2696 case DP_TRAINING_PATTERN_1:
2697 *DP |= DP_LINK_TRAIN_PAT_1;
2699 case DP_TRAINING_PATTERN_2:
2700 *DP |= DP_LINK_TRAIN_PAT_2;
2702 case DP_TRAINING_PATTERN_3:
2703 if (IS_CHERRYVIEW(dev_priv)) {
2704 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2706 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2707 *DP |= DP_LINK_TRAIN_PAT_2;
2714 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2715 struct intel_crtc_state *old_crtc_state)
2717 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2718 struct drm_i915_private *dev_priv = to_i915(dev);
2720 /* enable with pattern 1 (as per spec) */
2722 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2725 * Magic for VLV/CHV. We _must_ first set up the register
2726 * without actually enabling the port, and then do another
2727 * write to enable the port. Otherwise link training will
2728 * fail when the power sequencer is freshly used for this port.
2730 intel_dp->DP |= DP_PORT_EN;
2731 if (old_crtc_state->has_audio)
2732 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2734 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2735 POSTING_READ(intel_dp->output_reg);
2738 static void intel_enable_dp(struct intel_encoder *encoder,
2739 struct intel_crtc_state *pipe_config)
2741 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2742 struct drm_device *dev = encoder->base.dev;
2743 struct drm_i915_private *dev_priv = to_i915(dev);
2744 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2745 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2746 enum pipe pipe = crtc->pipe;
2748 if (WARN_ON(dp_reg & DP_PORT_EN))
2753 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2754 vlv_init_panel_power_sequencer(intel_dp);
2756 intel_dp_enable_port(intel_dp, pipe_config);
2758 edp_panel_vdd_on(intel_dp);
2759 edp_panel_on(intel_dp);
2760 edp_panel_vdd_off(intel_dp, true);
2762 pps_unlock(intel_dp);
2764 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2765 unsigned int lane_mask = 0x0;
2767 if (IS_CHERRYVIEW(dev_priv))
2768 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2770 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2774 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2775 intel_dp_start_link_train(intel_dp);
2776 intel_dp_stop_link_train(intel_dp);
2778 if (pipe_config->has_audio) {
2779 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2781 intel_audio_codec_enable(encoder);
2785 static void g4x_enable_dp(struct intel_encoder *encoder,
2786 struct intel_crtc_state *pipe_config,
2787 struct drm_connector_state *conn_state)
2789 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2791 intel_enable_dp(encoder, pipe_config);
2792 intel_edp_backlight_on(intel_dp);
2795 static void vlv_enable_dp(struct intel_encoder *encoder,
2796 struct intel_crtc_state *pipe_config,
2797 struct drm_connector_state *conn_state)
2799 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2801 intel_edp_backlight_on(intel_dp);
2802 intel_psr_enable(intel_dp);
2805 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2806 struct intel_crtc_state *pipe_config,
2807 struct drm_connector_state *conn_state)
2809 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2810 enum port port = dp_to_dig_port(intel_dp)->port;
2812 intel_dp_prepare(encoder, pipe_config);
2814 /* Only ilk+ has port A */
2816 ironlake_edp_pll_on(intel_dp, pipe_config);
2819 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2821 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2822 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2823 enum pipe pipe = intel_dp->pps_pipe;
2824 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2826 edp_panel_vdd_off_sync(intel_dp);
2829 * VLV seems to get confused when multiple power seqeuencers
2830 * have the same port selected (even if only one has power/vdd
2831 * enabled). The failure manifests as vlv_wait_port_ready() failing
2832 * CHV on the other hand doesn't seem to mind having the same port
2833 * selected in multiple power seqeuencers, but let's clear the
2834 * port select always when logically disconnecting a power sequencer
2837 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2838 pipe_name(pipe), port_name(intel_dig_port->port));
2839 I915_WRITE(pp_on_reg, 0);
2840 POSTING_READ(pp_on_reg);
2842 intel_dp->pps_pipe = INVALID_PIPE;
2845 static void vlv_steal_power_sequencer(struct drm_device *dev,
2848 struct drm_i915_private *dev_priv = to_i915(dev);
2849 struct intel_encoder *encoder;
2851 lockdep_assert_held(&dev_priv->pps_mutex);
2853 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2856 for_each_intel_encoder(dev, encoder) {
2857 struct intel_dp *intel_dp;
2860 if (encoder->type != INTEL_OUTPUT_EDP)
2863 intel_dp = enc_to_intel_dp(&encoder->base);
2864 port = dp_to_dig_port(intel_dp)->port;
2866 if (intel_dp->pps_pipe != pipe)
2869 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2870 pipe_name(pipe), port_name(port));
2872 WARN(encoder->base.crtc,
2873 "stealing pipe %c power sequencer from active eDP port %c\n",
2874 pipe_name(pipe), port_name(port));
2876 /* make sure vdd is off before we steal it */
2877 vlv_detach_power_sequencer(intel_dp);
2881 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2883 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2884 struct intel_encoder *encoder = &intel_dig_port->base;
2885 struct drm_device *dev = encoder->base.dev;
2886 struct drm_i915_private *dev_priv = to_i915(dev);
2887 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2889 lockdep_assert_held(&dev_priv->pps_mutex);
2891 if (!is_edp(intel_dp))
2894 if (intel_dp->pps_pipe == crtc->pipe)
2898 * If another power sequencer was being used on this
2899 * port previously make sure to turn off vdd there while
2900 * we still have control of it.
2902 if (intel_dp->pps_pipe != INVALID_PIPE)
2903 vlv_detach_power_sequencer(intel_dp);
2906 * We may be stealing the power
2907 * sequencer from another port.
2909 vlv_steal_power_sequencer(dev, crtc->pipe);
2911 /* now it's all ours */
2912 intel_dp->pps_pipe = crtc->pipe;
2914 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2915 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2917 /* init power sequencer on this pipe and port */
2918 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2919 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2922 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
2923 struct intel_crtc_state *pipe_config,
2924 struct drm_connector_state *conn_state)
2926 vlv_phy_pre_encoder_enable(encoder);
2928 intel_enable_dp(encoder, pipe_config);
2931 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
2932 struct intel_crtc_state *pipe_config,
2933 struct drm_connector_state *conn_state)
2935 intel_dp_prepare(encoder, pipe_config);
2937 vlv_phy_pre_pll_enable(encoder);
2940 static void chv_pre_enable_dp(struct intel_encoder *encoder,
2941 struct intel_crtc_state *pipe_config,
2942 struct drm_connector_state *conn_state)
2944 chv_phy_pre_encoder_enable(encoder);
2946 intel_enable_dp(encoder, pipe_config);
2948 /* Second common lane will stay alive on its own now */
2949 chv_phy_release_cl2_override(encoder);
2952 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
2953 struct intel_crtc_state *pipe_config,
2954 struct drm_connector_state *conn_state)
2956 intel_dp_prepare(encoder, pipe_config);
2958 chv_phy_pre_pll_enable(encoder);
2961 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
2962 struct intel_crtc_state *pipe_config,
2963 struct drm_connector_state *conn_state)
2965 chv_phy_post_pll_disable(encoder);
2969 * Fetch AUX CH registers 0x202 - 0x207 which contain
2970 * link status information
2973 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2975 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2976 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2979 /* These are source-specific values. */
2981 intel_dp_voltage_max(struct intel_dp *intel_dp)
2983 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2984 struct drm_i915_private *dev_priv = to_i915(dev);
2985 enum port port = dp_to_dig_port(intel_dp)->port;
2987 if (IS_BROXTON(dev_priv))
2988 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2989 else if (INTEL_INFO(dev)->gen >= 9) {
2990 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
2991 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2992 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2993 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2994 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2995 else if (IS_GEN7(dev_priv) && port == PORT_A)
2996 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2997 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2998 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3000 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3004 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3006 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3007 enum port port = dp_to_dig_port(intel_dp)->port;
3009 if (INTEL_GEN(dev_priv) >= 9) {
3010 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3011 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3012 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3014 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3015 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3016 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3017 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3018 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3020 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3022 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3023 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3024 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3025 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3026 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3027 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3028 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3029 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3030 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3032 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3034 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3035 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3036 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3037 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3038 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3039 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3040 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3041 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3042 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3044 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3046 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3047 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3048 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3049 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3051 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3052 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3054 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3057 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3058 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3059 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3060 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3061 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3062 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3063 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3064 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3066 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3071 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3073 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3074 unsigned long demph_reg_value, preemph_reg_value,
3075 uniqtranscale_reg_value;
3076 uint8_t train_set = intel_dp->train_set[0];
3078 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3079 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3080 preemph_reg_value = 0x0004000;
3081 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3082 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3083 demph_reg_value = 0x2B405555;
3084 uniqtranscale_reg_value = 0x552AB83A;
3086 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3087 demph_reg_value = 0x2B404040;
3088 uniqtranscale_reg_value = 0x5548B83A;
3090 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3091 demph_reg_value = 0x2B245555;
3092 uniqtranscale_reg_value = 0x5560B83A;
3094 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3095 demph_reg_value = 0x2B405555;
3096 uniqtranscale_reg_value = 0x5598DA3A;
3102 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3103 preemph_reg_value = 0x0002000;
3104 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3105 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3106 demph_reg_value = 0x2B404040;
3107 uniqtranscale_reg_value = 0x5552B83A;
3109 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3110 demph_reg_value = 0x2B404848;
3111 uniqtranscale_reg_value = 0x5580B83A;
3113 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3114 demph_reg_value = 0x2B404040;
3115 uniqtranscale_reg_value = 0x55ADDA3A;
3121 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3122 preemph_reg_value = 0x0000000;
3123 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3124 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3125 demph_reg_value = 0x2B305555;
3126 uniqtranscale_reg_value = 0x5570B83A;
3128 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3129 demph_reg_value = 0x2B2B4040;
3130 uniqtranscale_reg_value = 0x55ADDA3A;
3136 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3137 preemph_reg_value = 0x0006000;
3138 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3139 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3140 demph_reg_value = 0x1B405555;
3141 uniqtranscale_reg_value = 0x55ADDA3A;
3151 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3152 uniqtranscale_reg_value, 0);
3157 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3159 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3160 u32 deemph_reg_value, margin_reg_value;
3161 bool uniq_trans_scale = false;
3162 uint8_t train_set = intel_dp->train_set[0];
3164 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3165 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3166 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3167 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3168 deemph_reg_value = 128;
3169 margin_reg_value = 52;
3171 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3172 deemph_reg_value = 128;
3173 margin_reg_value = 77;
3175 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3176 deemph_reg_value = 128;
3177 margin_reg_value = 102;
3179 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3180 deemph_reg_value = 128;
3181 margin_reg_value = 154;
3182 uniq_trans_scale = true;
3188 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3189 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3191 deemph_reg_value = 85;
3192 margin_reg_value = 78;
3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3195 deemph_reg_value = 85;
3196 margin_reg_value = 116;
3198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3199 deemph_reg_value = 85;
3200 margin_reg_value = 154;
3206 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3207 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3209 deemph_reg_value = 64;
3210 margin_reg_value = 104;
3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3213 deemph_reg_value = 64;
3214 margin_reg_value = 154;
3220 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3221 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3223 deemph_reg_value = 43;
3224 margin_reg_value = 154;
3234 chv_set_phy_signal_level(encoder, deemph_reg_value,
3235 margin_reg_value, uniq_trans_scale);
3241 gen4_signal_levels(uint8_t train_set)
3243 uint32_t signal_levels = 0;
3245 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3248 signal_levels |= DP_VOLTAGE_0_4;
3250 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3251 signal_levels |= DP_VOLTAGE_0_6;
3253 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3254 signal_levels |= DP_VOLTAGE_0_8;
3256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3257 signal_levels |= DP_VOLTAGE_1_2;
3260 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3261 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3263 signal_levels |= DP_PRE_EMPHASIS_0;
3265 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3266 signal_levels |= DP_PRE_EMPHASIS_3_5;
3268 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3269 signal_levels |= DP_PRE_EMPHASIS_6;
3271 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3272 signal_levels |= DP_PRE_EMPHASIS_9_5;
3275 return signal_levels;
3278 /* Gen6's DP voltage swing and pre-emphasis control */
3280 gen6_edp_signal_levels(uint8_t train_set)
3282 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3283 DP_TRAIN_PRE_EMPHASIS_MASK);
3284 switch (signal_levels) {
3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3287 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3288 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3289 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3291 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3292 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3294 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3295 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3296 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3297 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3298 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3300 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3301 "0x%x\n", signal_levels);
3302 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3306 /* Gen7's DP voltage swing and pre-emphasis control */
3308 gen7_edp_signal_levels(uint8_t train_set)
3310 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3311 DP_TRAIN_PRE_EMPHASIS_MASK);
3312 switch (signal_levels) {
3313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3314 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3315 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3316 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3317 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3318 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3321 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3322 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3323 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3326 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3327 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3328 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3331 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3332 "0x%x\n", signal_levels);
3333 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3338 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3340 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3341 enum port port = intel_dig_port->port;
3342 struct drm_device *dev = intel_dig_port->base.base.dev;
3343 struct drm_i915_private *dev_priv = to_i915(dev);
3344 uint32_t signal_levels, mask = 0;
3345 uint8_t train_set = intel_dp->train_set[0];
3347 if (HAS_DDI(dev_priv)) {
3348 signal_levels = ddi_signal_levels(intel_dp);
3350 if (IS_BROXTON(dev_priv))
3353 mask = DDI_BUF_EMP_MASK;
3354 } else if (IS_CHERRYVIEW(dev_priv)) {
3355 signal_levels = chv_signal_levels(intel_dp);
3356 } else if (IS_VALLEYVIEW(dev_priv)) {
3357 signal_levels = vlv_signal_levels(intel_dp);
3358 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3359 signal_levels = gen7_edp_signal_levels(train_set);
3360 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3361 } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3362 signal_levels = gen6_edp_signal_levels(train_set);
3363 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3365 signal_levels = gen4_signal_levels(train_set);
3366 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3370 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3372 DRM_DEBUG_KMS("Using vswing level %d\n",
3373 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3374 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3375 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3376 DP_TRAIN_PRE_EMPHASIS_SHIFT);
3378 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3380 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3381 POSTING_READ(intel_dp->output_reg);
3385 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3386 uint8_t dp_train_pat)
3388 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3389 struct drm_i915_private *dev_priv =
3390 to_i915(intel_dig_port->base.base.dev);
3392 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3394 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3395 POSTING_READ(intel_dp->output_reg);
3398 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3400 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3401 struct drm_device *dev = intel_dig_port->base.base.dev;
3402 struct drm_i915_private *dev_priv = to_i915(dev);
3403 enum port port = intel_dig_port->port;
3406 if (!HAS_DDI(dev_priv))
3409 val = I915_READ(DP_TP_CTL(port));
3410 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3411 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3412 I915_WRITE(DP_TP_CTL(port), val);
3415 * On PORT_A we can have only eDP in SST mode. There the only reason
3416 * we need to set idle transmission mode is to work around a HW issue
3417 * where we enable the pipe while not in idle link-training mode.
3418 * In this case there is requirement to wait for a minimum number of
3419 * idle patterns to be sent.
3424 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3425 DP_TP_STATUS_IDLE_DONE,
3426 DP_TP_STATUS_IDLE_DONE,
3428 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3432 intel_dp_link_down(struct intel_dp *intel_dp)
3434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3435 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3436 enum port port = intel_dig_port->port;
3437 struct drm_device *dev = intel_dig_port->base.base.dev;
3438 struct drm_i915_private *dev_priv = to_i915(dev);
3439 uint32_t DP = intel_dp->DP;
3441 if (WARN_ON(HAS_DDI(dev_priv)))
3444 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3447 DRM_DEBUG_KMS("\n");
3449 if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3450 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3451 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3452 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3454 if (IS_CHERRYVIEW(dev_priv))
3455 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3457 DP &= ~DP_LINK_TRAIN_MASK;
3458 DP |= DP_LINK_TRAIN_PAT_IDLE;
3460 I915_WRITE(intel_dp->output_reg, DP);
3461 POSTING_READ(intel_dp->output_reg);
3463 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3464 I915_WRITE(intel_dp->output_reg, DP);
3465 POSTING_READ(intel_dp->output_reg);
3468 * HW workaround for IBX, we need to move the port
3469 * to transcoder A after disabling it to allow the
3470 * matching HDMI port to be enabled on transcoder A.
3472 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3474 * We get CPU/PCH FIFO underruns on the other pipe when
3475 * doing the workaround. Sweep them under the rug.
3477 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3478 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3480 /* always enable with pattern 1 (as per spec) */
3481 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3482 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3483 I915_WRITE(intel_dp->output_reg, DP);
3484 POSTING_READ(intel_dp->output_reg);
3487 I915_WRITE(intel_dp->output_reg, DP);
3488 POSTING_READ(intel_dp->output_reg);
3490 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
3491 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3492 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3495 msleep(intel_dp->panel_power_down_delay);
3501 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3503 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3504 sizeof(intel_dp->dpcd)) < 0)
3505 return false; /* aux transfer failed */
3507 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3509 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3513 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3515 struct drm_i915_private *dev_priv =
3516 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3518 /* this function is meant to be called only once */
3519 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3521 if (!intel_dp_read_dpcd(intel_dp))
3524 intel_dp_read_desc(intel_dp);
3526 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3527 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3528 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3530 /* Check if the panel supports PSR */
3531 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3533 sizeof(intel_dp->psr_dpcd));
3534 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3535 dev_priv->psr.sink_support = true;
3536 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3539 if (INTEL_GEN(dev_priv) >= 9 &&
3540 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3541 uint8_t frame_sync_cap;
3543 dev_priv->psr.sink_support = true;
3544 drm_dp_dpcd_read(&intel_dp->aux,
3545 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3546 &frame_sync_cap, 1);
3547 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3548 /* PSR2 needs frame sync as well */
3549 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3550 DRM_DEBUG_KMS("PSR2 %s on sink",
3551 dev_priv->psr.psr2_support ? "supported" : "not supported");
3554 /* Read the eDP Display control capabilities registers */
3555 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3556 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3557 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3558 sizeof(intel_dp->edp_dpcd))
3559 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3560 intel_dp->edp_dpcd);
3562 /* Intermediate frequency support */
3563 if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3564 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3567 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3568 sink_rates, sizeof(sink_rates));
3570 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3571 int val = le16_to_cpu(sink_rates[i]);
3576 /* Value read is in kHz while drm clock is saved in deca-kHz */
3577 intel_dp->sink_rates[i] = (val * 200) / 10;
3579 intel_dp->num_sink_rates = i;
3587 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3589 if (!intel_dp_read_dpcd(intel_dp))
3592 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3593 &intel_dp->sink_count, 1) < 0)
3597 * Sink count can change between short pulse hpd hence
3598 * a member variable in intel_dp will track any changes
3599 * between short pulse interrupts.
3601 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3604 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3605 * a dongle is present but no display. Unless we require to know
3606 * if a dongle is present or not, we don't need to update
3607 * downstream port information. So, an early return here saves
3608 * time from performing other operations which are not required.
3610 if (!is_edp(intel_dp) && !intel_dp->sink_count)
3613 if (!drm_dp_is_branch(intel_dp->dpcd))
3614 return true; /* native DP sink */
3616 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3617 return true; /* no per-port downstream info */
3619 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3620 intel_dp->downstream_ports,
3621 DP_MAX_DOWNSTREAM_PORTS) < 0)
3622 return false; /* downstream port status fetch failed */
3628 intel_dp_can_mst(struct intel_dp *intel_dp)
3632 if (!i915.enable_dp_mst)
3635 if (!intel_dp->can_mst)
3638 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3641 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3644 return buf[0] & DP_MST_CAP;
3648 intel_dp_configure_mst(struct intel_dp *intel_dp)
3650 if (!i915.enable_dp_mst)
3653 if (!intel_dp->can_mst)
3656 intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3658 if (intel_dp->is_mst)
3659 DRM_DEBUG_KMS("Sink is MST capable\n");
3661 DRM_DEBUG_KMS("Sink is not MST capable\n");
3663 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3667 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3669 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3670 struct drm_device *dev = dig_port->base.base.dev;
3671 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3677 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3678 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3683 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3684 buf & ~DP_TEST_SINK_START) < 0) {
3685 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3691 intel_wait_for_vblank(dev, intel_crtc->pipe);
3693 if (drm_dp_dpcd_readb(&intel_dp->aux,
3694 DP_TEST_SINK_MISC, &buf) < 0) {
3698 count = buf & DP_TEST_COUNT_MASK;
3699 } while (--attempts && count);
3701 if (attempts == 0) {
3702 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3707 hsw_enable_ips(intel_crtc);
3711 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3713 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3714 struct drm_device *dev = dig_port->base.base.dev;
3715 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3719 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3722 if (!(buf & DP_TEST_CRC_SUPPORTED))
3725 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3728 if (buf & DP_TEST_SINK_START) {
3729 ret = intel_dp_sink_crc_stop(intel_dp);
3734 hsw_disable_ips(intel_crtc);
3736 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3737 buf | DP_TEST_SINK_START) < 0) {
3738 hsw_enable_ips(intel_crtc);
3742 intel_wait_for_vblank(dev, intel_crtc->pipe);
3746 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3748 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3749 struct drm_device *dev = dig_port->base.base.dev;
3750 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3755 ret = intel_dp_sink_crc_start(intel_dp);
3760 intel_wait_for_vblank(dev, intel_crtc->pipe);
3762 if (drm_dp_dpcd_readb(&intel_dp->aux,
3763 DP_TEST_SINK_MISC, &buf) < 0) {
3767 count = buf & DP_TEST_COUNT_MASK;
3769 } while (--attempts && count == 0);
3771 if (attempts == 0) {
3772 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3777 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3783 intel_dp_sink_crc_stop(intel_dp);
3788 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3790 return drm_dp_dpcd_read(&intel_dp->aux,
3791 DP_DEVICE_SERVICE_IRQ_VECTOR,
3792 sink_irq_vector, 1) == 1;
3796 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3800 ret = drm_dp_dpcd_read(&intel_dp->aux,
3802 sink_irq_vector, 14);
3809 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3811 uint8_t test_result = DP_TEST_ACK;
3815 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3817 uint8_t test_result = DP_TEST_NAK;
3821 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
3823 uint8_t test_result = DP_TEST_NAK;
3824 struct intel_connector *intel_connector = intel_dp->attached_connector;
3825 struct drm_connector *connector = &intel_connector->base;
3827 if (intel_connector->detect_edid == NULL ||
3828 connector->edid_corrupt ||
3829 intel_dp->aux.i2c_defer_count > 6) {
3830 /* Check EDID read for NACKs, DEFERs and corruption
3831 * (DP CTS 1.2 Core r1.1)
3832 * 4.2.2.4 : Failed EDID read, I2C_NAK
3833 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3834 * 4.2.2.6 : EDID corruption detected
3835 * Use failsafe mode for all cases
3837 if (intel_dp->aux.i2c_nack_count > 0 ||
3838 intel_dp->aux.i2c_defer_count > 0)
3839 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3840 intel_dp->aux.i2c_nack_count,
3841 intel_dp->aux.i2c_defer_count);
3842 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3844 struct edid *block = intel_connector->detect_edid;
3846 /* We have to write the checksum
3847 * of the last block read
3849 block += intel_connector->detect_edid->extensions;
3851 if (!drm_dp_dpcd_write(&intel_dp->aux,
3852 DP_TEST_EDID_CHECKSUM,
3855 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3857 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3858 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3861 /* Set test active flag here so userspace doesn't interrupt things */
3862 intel_dp->compliance_test_active = 1;
3867 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3869 uint8_t test_result = DP_TEST_NAK;
3873 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3875 uint8_t response = DP_TEST_NAK;
3879 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3881 DRM_DEBUG_KMS("Could not read test request from sink\n");
3886 case DP_TEST_LINK_TRAINING:
3887 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3888 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3889 response = intel_dp_autotest_link_training(intel_dp);
3891 case DP_TEST_LINK_VIDEO_PATTERN:
3892 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3893 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3894 response = intel_dp_autotest_video_pattern(intel_dp);
3896 case DP_TEST_LINK_EDID_READ:
3897 DRM_DEBUG_KMS("EDID test requested\n");
3898 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3899 response = intel_dp_autotest_edid(intel_dp);
3901 case DP_TEST_LINK_PHY_TEST_PATTERN:
3902 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3903 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3904 response = intel_dp_autotest_phy_pattern(intel_dp);
3907 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3912 status = drm_dp_dpcd_write(&intel_dp->aux,
3916 DRM_DEBUG_KMS("Could not write test response to sink\n");
3920 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3924 if (intel_dp->is_mst) {
3929 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3933 /* check link status - esi[10] = 0x200c */
3934 if (intel_dp->active_mst_links &&
3935 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3936 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3937 intel_dp_start_link_train(intel_dp);
3938 intel_dp_stop_link_train(intel_dp);
3941 DRM_DEBUG_KMS("got esi %3ph\n", esi);
3942 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3945 for (retry = 0; retry < 3; retry++) {
3947 wret = drm_dp_dpcd_write(&intel_dp->aux,
3948 DP_SINK_COUNT_ESI+1,
3955 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3957 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
3965 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3966 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3967 intel_dp->is_mst = false;
3968 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3969 /* send a hotplug event */
3970 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3977 intel_dp_retrain_link(struct intel_dp *intel_dp)
3979 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3980 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3981 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
3983 /* Suppress underruns caused by re-training */
3984 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3985 if (crtc->config->has_pch_encoder)
3986 intel_set_pch_fifo_underrun_reporting(dev_priv,
3987 intel_crtc_pch_transcoder(crtc), false);
3989 intel_dp_start_link_train(intel_dp);
3990 intel_dp_stop_link_train(intel_dp);
3992 /* Keep underrun reporting disabled until things are stable */
3993 intel_wait_for_vblank(&dev_priv->drm, crtc->pipe);
3995 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
3996 if (crtc->config->has_pch_encoder)
3997 intel_set_pch_fifo_underrun_reporting(dev_priv,
3998 intel_crtc_pch_transcoder(crtc), true);
4002 intel_dp_check_link_status(struct intel_dp *intel_dp)
4004 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4005 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4006 u8 link_status[DP_LINK_STATUS_SIZE];
4008 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4010 if (!intel_dp_get_link_status(intel_dp, link_status)) {
4011 DRM_ERROR("Failed to get link status\n");
4015 if (!intel_encoder->base.crtc)
4018 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4021 /* FIXME: we need to synchronize this sort of stuff with hardware
4023 if (WARN_ON_ONCE(!intel_dp->lane_count))
4026 /* if link training is requested we should perform it always */
4027 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4028 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4029 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4030 intel_encoder->base.name);
4032 intel_dp_retrain_link(intel_dp);
4037 * According to DP spec
4040 * 2. Configure link according to Receiver Capabilities
4041 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4042 * 4. Check link status on receipt of hot-plug interrupt
4044 * intel_dp_short_pulse - handles short pulse interrupts
4045 * when full detection is not required.
4046 * Returns %true if short pulse is handled and full detection
4047 * is NOT required and %false otherwise.
4050 intel_dp_short_pulse(struct intel_dp *intel_dp)
4052 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4053 u8 sink_irq_vector = 0;
4054 u8 old_sink_count = intel_dp->sink_count;
4058 * Clearing compliance test variables to allow capturing
4059 * of values for next automated test request.
4061 intel_dp->compliance_test_active = 0;
4062 intel_dp->compliance_test_type = 0;
4063 intel_dp->compliance_test_data = 0;
4066 * Now read the DPCD to see if it's actually running
4067 * If the current value of sink count doesn't match with
4068 * the value that was stored earlier or dpcd read failed
4069 * we need to do full detection
4071 ret = intel_dp_get_dpcd(intel_dp);
4073 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4074 /* No need to proceed if we are going to do full detect */
4078 /* Try to read the source of the interrupt */
4079 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4080 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4081 sink_irq_vector != 0) {
4082 /* Clear interrupt source */
4083 drm_dp_dpcd_writeb(&intel_dp->aux,
4084 DP_DEVICE_SERVICE_IRQ_VECTOR,
4087 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4088 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4089 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4090 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4093 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4094 intel_dp_check_link_status(intel_dp);
4095 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4100 /* XXX this is probably wrong for multiple downstream ports */
4101 static enum drm_connector_status
4102 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4104 uint8_t *dpcd = intel_dp->dpcd;
4107 if (!intel_dp_get_dpcd(intel_dp))
4108 return connector_status_disconnected;
4110 if (is_edp(intel_dp))
4111 return connector_status_connected;
4113 /* if there's no downstream port, we're done */
4114 if (!drm_dp_is_branch(dpcd))
4115 return connector_status_connected;
4117 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4118 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4119 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4121 return intel_dp->sink_count ?
4122 connector_status_connected : connector_status_disconnected;
4125 if (intel_dp_can_mst(intel_dp))
4126 return connector_status_connected;
4128 /* If no HPD, poke DDC gently */
4129 if (drm_probe_ddc(&intel_dp->aux.ddc))
4130 return connector_status_connected;
4132 /* Well we tried, say unknown for unreliable port types */
4133 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4134 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4135 if (type == DP_DS_PORT_TYPE_VGA ||
4136 type == DP_DS_PORT_TYPE_NON_EDID)
4137 return connector_status_unknown;
4139 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4140 DP_DWN_STRM_PORT_TYPE_MASK;
4141 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4142 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4143 return connector_status_unknown;
4146 /* Anything else is out of spec, warn and ignore */
4147 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4148 return connector_status_disconnected;
4151 static enum drm_connector_status
4152 edp_detect(struct intel_dp *intel_dp)
4154 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4155 enum drm_connector_status status;
4157 status = intel_panel_detect(dev);
4158 if (status == connector_status_unknown)
4159 status = connector_status_connected;
4164 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4165 struct intel_digital_port *port)
4169 switch (port->port) {
4173 bit = SDE_PORTB_HOTPLUG;
4176 bit = SDE_PORTC_HOTPLUG;
4179 bit = SDE_PORTD_HOTPLUG;
4182 MISSING_CASE(port->port);
4186 return I915_READ(SDEISR) & bit;
4189 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4190 struct intel_digital_port *port)
4194 switch (port->port) {
4198 bit = SDE_PORTB_HOTPLUG_CPT;
4201 bit = SDE_PORTC_HOTPLUG_CPT;
4204 bit = SDE_PORTD_HOTPLUG_CPT;
4207 bit = SDE_PORTE_HOTPLUG_SPT;
4210 MISSING_CASE(port->port);
4214 return I915_READ(SDEISR) & bit;
4217 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4218 struct intel_digital_port *port)
4222 switch (port->port) {
4224 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4227 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4230 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4233 MISSING_CASE(port->port);
4237 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4240 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4241 struct intel_digital_port *port)
4245 switch (port->port) {
4247 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4250 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4253 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4256 MISSING_CASE(port->port);
4260 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4263 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4264 struct intel_digital_port *intel_dig_port)
4266 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4270 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4273 bit = BXT_DE_PORT_HP_DDIA;
4276 bit = BXT_DE_PORT_HP_DDIB;
4279 bit = BXT_DE_PORT_HP_DDIC;
4286 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4290 * intel_digital_port_connected - is the specified port connected?
4291 * @dev_priv: i915 private structure
4292 * @port: the port to test
4294 * Return %true if @port is connected, %false otherwise.
4296 static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4297 struct intel_digital_port *port)
4299 if (HAS_PCH_IBX(dev_priv))
4300 return ibx_digital_port_connected(dev_priv, port);
4301 else if (HAS_PCH_SPLIT(dev_priv))
4302 return cpt_digital_port_connected(dev_priv, port);
4303 else if (IS_BROXTON(dev_priv))
4304 return bxt_digital_port_connected(dev_priv, port);
4305 else if (IS_GM45(dev_priv))
4306 return gm45_digital_port_connected(dev_priv, port);
4308 return g4x_digital_port_connected(dev_priv, port);
4311 static struct edid *
4312 intel_dp_get_edid(struct intel_dp *intel_dp)
4314 struct intel_connector *intel_connector = intel_dp->attached_connector;
4316 /* use cached edid if we have one */
4317 if (intel_connector->edid) {
4319 if (IS_ERR(intel_connector->edid))
4322 return drm_edid_duplicate(intel_connector->edid);
4324 return drm_get_edid(&intel_connector->base,
4325 &intel_dp->aux.ddc);
4329 intel_dp_set_edid(struct intel_dp *intel_dp)
4331 struct intel_connector *intel_connector = intel_dp->attached_connector;
4334 intel_dp_unset_edid(intel_dp);
4335 edid = intel_dp_get_edid(intel_dp);
4336 intel_connector->detect_edid = edid;
4338 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4339 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4341 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4345 intel_dp_unset_edid(struct intel_dp *intel_dp)
4347 struct intel_connector *intel_connector = intel_dp->attached_connector;
4349 kfree(intel_connector->detect_edid);
4350 intel_connector->detect_edid = NULL;
4352 intel_dp->has_audio = false;
4355 static enum drm_connector_status
4356 intel_dp_long_pulse(struct intel_connector *intel_connector)
4358 struct drm_connector *connector = &intel_connector->base;
4359 struct intel_dp *intel_dp = intel_attached_dp(connector);
4360 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4361 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4362 struct drm_device *dev = connector->dev;
4363 enum drm_connector_status status;
4364 enum intel_display_power_domain power_domain;
4365 u8 sink_irq_vector = 0;
4367 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4368 intel_display_power_get(to_i915(dev), power_domain);
4370 /* Can't disconnect eDP, but you can close the lid... */
4371 if (is_edp(intel_dp))
4372 status = edp_detect(intel_dp);
4373 else if (intel_digital_port_connected(to_i915(dev),
4374 dp_to_dig_port(intel_dp)))
4375 status = intel_dp_detect_dpcd(intel_dp);
4377 status = connector_status_disconnected;
4379 if (status == connector_status_disconnected) {
4380 intel_dp->compliance_test_active = 0;
4381 intel_dp->compliance_test_type = 0;
4382 intel_dp->compliance_test_data = 0;
4384 if (intel_dp->is_mst) {
4385 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4387 intel_dp->mst_mgr.mst_state);
4388 intel_dp->is_mst = false;
4389 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4396 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4397 intel_encoder->type = INTEL_OUTPUT_DP;
4399 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4400 yesno(intel_dp_source_supports_hbr2(intel_dp)),
4401 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4403 intel_dp_print_rates(intel_dp);
4405 intel_dp_read_desc(intel_dp);
4407 intel_dp_configure_mst(intel_dp);
4409 if (intel_dp->is_mst) {
4411 * If we are in MST mode then this connector
4412 * won't appear connected or have anything
4415 status = connector_status_disconnected;
4417 } else if (connector->status == connector_status_connected) {
4419 * If display was connected already and is still connected
4420 * check links status, there has been known issues of
4421 * link loss triggerring long pulse!!!!
4423 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4424 intel_dp_check_link_status(intel_dp);
4425 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4430 * Clearing NACK and defer counts to get their exact values
4431 * while reading EDID which are required by Compliance tests
4432 * 4.2.2.4 and 4.2.2.5
4434 intel_dp->aux.i2c_nack_count = 0;
4435 intel_dp->aux.i2c_defer_count = 0;
4437 intel_dp_set_edid(intel_dp);
4438 if (is_edp(intel_dp) || intel_connector->detect_edid)
4439 status = connector_status_connected;
4440 intel_dp->detect_done = true;
4442 /* Try to read the source of the interrupt */
4443 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4444 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4445 sink_irq_vector != 0) {
4446 /* Clear interrupt source */
4447 drm_dp_dpcd_writeb(&intel_dp->aux,
4448 DP_DEVICE_SERVICE_IRQ_VECTOR,
4451 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4452 intel_dp_handle_test_request(intel_dp);
4453 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4454 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4458 if (status != connector_status_connected && !intel_dp->is_mst)
4459 intel_dp_unset_edid(intel_dp);
4461 intel_display_power_put(to_i915(dev), power_domain);
4465 static enum drm_connector_status
4466 intel_dp_detect(struct drm_connector *connector, bool force)
4468 struct intel_dp *intel_dp = intel_attached_dp(connector);
4469 enum drm_connector_status status = connector->status;
4471 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4472 connector->base.id, connector->name);
4474 /* If full detect is not performed yet, do a full detect */
4475 if (!intel_dp->detect_done)
4476 status = intel_dp_long_pulse(intel_dp->attached_connector);
4478 intel_dp->detect_done = false;
4484 intel_dp_force(struct drm_connector *connector)
4486 struct intel_dp *intel_dp = intel_attached_dp(connector);
4487 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4488 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4489 enum intel_display_power_domain power_domain;
4491 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4492 connector->base.id, connector->name);
4493 intel_dp_unset_edid(intel_dp);
4495 if (connector->status != connector_status_connected)
4498 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4499 intel_display_power_get(dev_priv, power_domain);
4501 intel_dp_set_edid(intel_dp);
4503 intel_display_power_put(dev_priv, power_domain);
4505 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4506 intel_encoder->type = INTEL_OUTPUT_DP;
4509 static int intel_dp_get_modes(struct drm_connector *connector)
4511 struct intel_connector *intel_connector = to_intel_connector(connector);
4514 edid = intel_connector->detect_edid;
4516 int ret = intel_connector_update_modes(connector, edid);
4521 /* if eDP has no EDID, fall back to fixed mode */
4522 if (is_edp(intel_attached_dp(connector)) &&
4523 intel_connector->panel.fixed_mode) {
4524 struct drm_display_mode *mode;
4526 mode = drm_mode_duplicate(connector->dev,
4527 intel_connector->panel.fixed_mode);
4529 drm_mode_probed_add(connector, mode);
4538 intel_dp_detect_audio(struct drm_connector *connector)
4540 bool has_audio = false;
4543 edid = to_intel_connector(connector)->detect_edid;
4545 has_audio = drm_detect_monitor_audio(edid);
4551 intel_dp_set_property(struct drm_connector *connector,
4552 struct drm_property *property,
4555 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4556 struct intel_connector *intel_connector = to_intel_connector(connector);
4557 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4558 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4561 ret = drm_object_property_set_value(&connector->base, property, val);
4565 if (property == dev_priv->force_audio_property) {
4569 if (i == intel_dp->force_audio)
4572 intel_dp->force_audio = i;
4574 if (i == HDMI_AUDIO_AUTO)
4575 has_audio = intel_dp_detect_audio(connector);
4577 has_audio = (i == HDMI_AUDIO_ON);
4579 if (has_audio == intel_dp->has_audio)
4582 intel_dp->has_audio = has_audio;
4586 if (property == dev_priv->broadcast_rgb_property) {
4587 bool old_auto = intel_dp->color_range_auto;
4588 bool old_range = intel_dp->limited_color_range;
4591 case INTEL_BROADCAST_RGB_AUTO:
4592 intel_dp->color_range_auto = true;
4594 case INTEL_BROADCAST_RGB_FULL:
4595 intel_dp->color_range_auto = false;
4596 intel_dp->limited_color_range = false;
4598 case INTEL_BROADCAST_RGB_LIMITED:
4599 intel_dp->color_range_auto = false;
4600 intel_dp->limited_color_range = true;
4606 if (old_auto == intel_dp->color_range_auto &&
4607 old_range == intel_dp->limited_color_range)
4613 if (is_edp(intel_dp) &&
4614 property == connector->dev->mode_config.scaling_mode_property) {
4615 if (val == DRM_MODE_SCALE_NONE) {
4616 DRM_DEBUG_KMS("no scaling not supported\n");
4619 if (HAS_GMCH_DISPLAY(dev_priv) &&
4620 val == DRM_MODE_SCALE_CENTER) {
4621 DRM_DEBUG_KMS("centering not supported\n");
4625 if (intel_connector->panel.fitting_mode == val) {
4626 /* the eDP scaling property is not changed */
4629 intel_connector->panel.fitting_mode = val;
4637 if (intel_encoder->base.crtc)
4638 intel_crtc_restore_mode(intel_encoder->base.crtc);
4644 intel_dp_connector_register(struct drm_connector *connector)
4646 struct intel_dp *intel_dp = intel_attached_dp(connector);
4649 ret = intel_connector_register(connector);
4653 i915_debugfs_connector_add(connector);
4655 DRM_DEBUG_KMS("registering %s bus for %s\n",
4656 intel_dp->aux.name, connector->kdev->kobj.name);
4658 intel_dp->aux.dev = connector->kdev;
4659 return drm_dp_aux_register(&intel_dp->aux);
4663 intel_dp_connector_unregister(struct drm_connector *connector)
4665 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4666 intel_connector_unregister(connector);
4670 intel_dp_connector_destroy(struct drm_connector *connector)
4672 struct intel_connector *intel_connector = to_intel_connector(connector);
4674 kfree(intel_connector->detect_edid);
4676 if (!IS_ERR_OR_NULL(intel_connector->edid))
4677 kfree(intel_connector->edid);
4679 /* Can't call is_edp() since the encoder may have been destroyed
4681 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4682 intel_panel_fini(&intel_connector->panel);
4684 drm_connector_cleanup(connector);
4688 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4690 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4691 struct intel_dp *intel_dp = &intel_dig_port->dp;
4693 intel_dp_mst_encoder_cleanup(intel_dig_port);
4694 if (is_edp(intel_dp)) {
4695 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4697 * vdd might still be enabled do to the delayed vdd off.
4698 * Make sure vdd is actually turned off here.
4701 edp_panel_vdd_off_sync(intel_dp);
4702 pps_unlock(intel_dp);
4704 if (intel_dp->edp_notifier.notifier_call) {
4705 unregister_reboot_notifier(&intel_dp->edp_notifier);
4706 intel_dp->edp_notifier.notifier_call = NULL;
4710 intel_dp_aux_fini(intel_dp);
4712 drm_encoder_cleanup(encoder);
4713 kfree(intel_dig_port);
4716 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4718 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4720 if (!is_edp(intel_dp))
4724 * vdd might still be enabled do to the delayed vdd off.
4725 * Make sure vdd is actually turned off here.
4727 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4729 edp_panel_vdd_off_sync(intel_dp);
4730 pps_unlock(intel_dp);
4733 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4735 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4736 struct drm_device *dev = intel_dig_port->base.base.dev;
4737 struct drm_i915_private *dev_priv = to_i915(dev);
4738 enum intel_display_power_domain power_domain;
4740 lockdep_assert_held(&dev_priv->pps_mutex);
4742 if (!edp_have_panel_vdd(intel_dp))
4746 * The VDD bit needs a power domain reference, so if the bit is
4747 * already enabled when we boot or resume, grab this reference and
4748 * schedule a vdd off, so we don't hold on to the reference
4751 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4752 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4753 intel_display_power_get(dev_priv, power_domain);
4755 edp_panel_vdd_schedule_off(intel_dp);
4758 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4760 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4761 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4762 struct intel_lspcon *lspcon = &intel_dig_port->lspcon;
4763 struct intel_dp *intel_dp = &intel_dig_port->dp;
4765 if (!HAS_DDI(dev_priv))
4766 intel_dp->DP = I915_READ(intel_dp->output_reg);
4768 if (IS_GEN9(dev_priv) && lspcon->active)
4769 lspcon_resume(lspcon);
4771 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4776 /* Reinit the power sequencer, in case BIOS did something with it. */
4777 intel_dp_pps_init(encoder->dev, intel_dp);
4778 intel_edp_panel_vdd_sanitize(intel_dp);
4780 pps_unlock(intel_dp);
4783 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4784 .dpms = drm_atomic_helper_connector_dpms,
4785 .detect = intel_dp_detect,
4786 .force = intel_dp_force,
4787 .fill_modes = drm_helper_probe_single_connector_modes,
4788 .set_property = intel_dp_set_property,
4789 .atomic_get_property = intel_connector_atomic_get_property,
4790 .late_register = intel_dp_connector_register,
4791 .early_unregister = intel_dp_connector_unregister,
4792 .destroy = intel_dp_connector_destroy,
4793 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4794 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4797 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4798 .get_modes = intel_dp_get_modes,
4799 .mode_valid = intel_dp_mode_valid,
4802 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4803 .reset = intel_dp_encoder_reset,
4804 .destroy = intel_dp_encoder_destroy,
4808 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4810 struct intel_dp *intel_dp = &intel_dig_port->dp;
4811 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4812 struct drm_device *dev = intel_dig_port->base.base.dev;
4813 struct drm_i915_private *dev_priv = to_i915(dev);
4814 enum intel_display_power_domain power_domain;
4815 enum irqreturn ret = IRQ_NONE;
4817 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4818 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4819 intel_dig_port->base.type = INTEL_OUTPUT_DP;
4821 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4823 * vdd off can generate a long pulse on eDP which
4824 * would require vdd on to handle it, and thus we
4825 * would end up in an endless cycle of
4826 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4828 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4829 port_name(intel_dig_port->port));
4833 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4834 port_name(intel_dig_port->port),
4835 long_hpd ? "long" : "short");
4838 intel_dp->detect_done = false;
4842 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4843 intel_display_power_get(dev_priv, power_domain);
4845 if (intel_dp->is_mst) {
4846 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4848 * If we were in MST mode, and device is not
4849 * there, get out of MST mode
4851 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4852 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4853 intel_dp->is_mst = false;
4854 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4856 intel_dp->detect_done = false;
4861 if (!intel_dp->is_mst) {
4862 if (!intel_dp_short_pulse(intel_dp)) {
4863 intel_dp->detect_done = false;
4871 intel_display_power_put(dev_priv, power_domain);
4876 /* check the VBT to see whether the eDP is on another port */
4877 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4879 struct drm_i915_private *dev_priv = to_i915(dev);
4882 * eDP not supported on g4x. so bail out early just
4883 * for a bit extra safety in case the VBT is bonkers.
4885 if (INTEL_INFO(dev)->gen < 5)
4891 return intel_bios_is_port_edp(dev_priv, port);
4895 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4897 struct intel_connector *intel_connector = to_intel_connector(connector);
4899 intel_attach_force_audio_property(connector);
4900 intel_attach_broadcast_rgb_property(connector);
4901 intel_dp->color_range_auto = true;
4903 if (is_edp(intel_dp)) {
4904 drm_mode_create_scaling_mode_property(connector->dev);
4905 drm_object_attach_property(
4907 connector->dev->mode_config.scaling_mode_property,
4908 DRM_MODE_SCALE_ASPECT);
4909 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4913 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4915 intel_dp->panel_power_off_time = ktime_get_boottime();
4916 intel_dp->last_power_on = jiffies;
4917 intel_dp->last_backlight_off = jiffies;
4921 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
4922 struct intel_dp *intel_dp, struct edp_power_seq *seq)
4924 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
4925 struct pps_registers regs;
4927 intel_pps_get_registers(dev_priv, intel_dp, ®s);
4929 /* Workaround: Need to write PP_CONTROL with the unlock key as
4930 * the very first thing. */
4931 pp_ctl = ironlake_get_pp_control(intel_dp);
4933 pp_on = I915_READ(regs.pp_on);
4934 pp_off = I915_READ(regs.pp_off);
4935 if (!IS_BROXTON(dev_priv)) {
4936 I915_WRITE(regs.pp_ctrl, pp_ctl);
4937 pp_div = I915_READ(regs.pp_div);
4940 /* Pull timing values out of registers */
4941 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4942 PANEL_POWER_UP_DELAY_SHIFT;
4944 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4945 PANEL_LIGHT_ON_DELAY_SHIFT;
4947 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4948 PANEL_LIGHT_OFF_DELAY_SHIFT;
4950 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4951 PANEL_POWER_DOWN_DELAY_SHIFT;
4953 if (IS_BROXTON(dev_priv)) {
4954 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4955 BXT_POWER_CYCLE_DELAY_SHIFT;
4957 seq->t11_t12 = (tmp - 1) * 1000;
4961 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4962 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4967 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
4969 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4971 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
4975 intel_pps_verify_state(struct drm_i915_private *dev_priv,
4976 struct intel_dp *intel_dp)
4978 struct edp_power_seq hw;
4979 struct edp_power_seq *sw = &intel_dp->pps_delays;
4981 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
4983 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
4984 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
4985 DRM_ERROR("PPS state mismatch\n");
4986 intel_pps_dump_state("sw", sw);
4987 intel_pps_dump_state("hw", &hw);
4992 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4993 struct intel_dp *intel_dp)
4995 struct drm_i915_private *dev_priv = to_i915(dev);
4996 struct edp_power_seq cur, vbt, spec,
4997 *final = &intel_dp->pps_delays;
4999 lockdep_assert_held(&dev_priv->pps_mutex);
5001 /* already initialized? */
5002 if (final->t11_t12 != 0)
5005 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5007 intel_pps_dump_state("cur", &cur);
5009 vbt = dev_priv->vbt.edp.pps;
5011 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5012 * our hw here, which are all in 100usec. */
5013 spec.t1_t3 = 210 * 10;
5014 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5015 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5016 spec.t10 = 500 * 10;
5017 /* This one is special and actually in units of 100ms, but zero
5018 * based in the hw (so we need to add 100 ms). But the sw vbt
5019 * table multiplies it with 1000 to make it in units of 100usec,
5021 spec.t11_t12 = (510 + 100) * 10;
5023 intel_pps_dump_state("vbt", &vbt);
5025 /* Use the max of the register settings and vbt. If both are
5026 * unset, fall back to the spec limits. */
5027 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5029 max(cur.field, vbt.field))
5030 assign_final(t1_t3);
5034 assign_final(t11_t12);
5037 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5038 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5039 intel_dp->backlight_on_delay = get_delay(t8);
5040 intel_dp->backlight_off_delay = get_delay(t9);
5041 intel_dp->panel_power_down_delay = get_delay(t10);
5042 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5045 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5046 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5047 intel_dp->panel_power_cycle_delay);
5049 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5050 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5053 * We override the HW backlight delays to 1 because we do manual waits
5054 * on them. For T8, even BSpec recommends doing it. For T9, if we
5055 * don't do this, we'll end up waiting for the backlight off delay
5056 * twice: once when we do the manual sleep, and once when we disable
5057 * the panel and wait for the PP_STATUS bit to become zero.
5064 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5065 struct intel_dp *intel_dp)
5067 struct drm_i915_private *dev_priv = to_i915(dev);
5068 u32 pp_on, pp_off, pp_div, port_sel = 0;
5069 int div = dev_priv->rawclk_freq / 1000;
5070 struct pps_registers regs;
5071 enum port port = dp_to_dig_port(intel_dp)->port;
5072 const struct edp_power_seq *seq = &intel_dp->pps_delays;
5074 lockdep_assert_held(&dev_priv->pps_mutex);
5076 intel_pps_get_registers(dev_priv, intel_dp, ®s);
5078 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5079 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5080 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5081 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5082 /* Compute the divisor for the pp clock, simply match the Bspec
5084 if (IS_BROXTON(dev_priv)) {
5085 pp_div = I915_READ(regs.pp_ctrl);
5086 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5087 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5088 << BXT_POWER_CYCLE_DELAY_SHIFT);
5090 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5091 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5092 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5095 /* Haswell doesn't have any port selection bits for the panel
5096 * power sequencer any more. */
5097 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5098 port_sel = PANEL_PORT_SELECT_VLV(port);
5099 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5101 port_sel = PANEL_PORT_SELECT_DPA;
5103 port_sel = PANEL_PORT_SELECT_DPD;
5108 I915_WRITE(regs.pp_on, pp_on);
5109 I915_WRITE(regs.pp_off, pp_off);
5110 if (IS_BROXTON(dev_priv))
5111 I915_WRITE(regs.pp_ctrl, pp_div);
5113 I915_WRITE(regs.pp_div, pp_div);
5115 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5116 I915_READ(regs.pp_on),
5117 I915_READ(regs.pp_off),
5118 IS_BROXTON(dev_priv) ?
5119 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5120 I915_READ(regs.pp_div));
5123 static void intel_dp_pps_init(struct drm_device *dev,
5124 struct intel_dp *intel_dp)
5126 struct drm_i915_private *dev_priv = to_i915(dev);
5128 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5129 vlv_initial_power_sequencer_setup(intel_dp);
5131 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5132 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5137 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5138 * @dev_priv: i915 device
5139 * @crtc_state: a pointer to the active intel_crtc_state
5140 * @refresh_rate: RR to be programmed
5142 * This function gets called when refresh rate (RR) has to be changed from
5143 * one frequency to another. Switches can be between high and low RR
5144 * supported by the panel or to any other RR based on media playback (in
5145 * this case, RR value needs to be passed from user space).
5147 * The caller of this function needs to take a lock on dev_priv->drrs.
5149 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5150 struct intel_crtc_state *crtc_state,
5153 struct intel_encoder *encoder;
5154 struct intel_digital_port *dig_port = NULL;
5155 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5157 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5159 if (refresh_rate <= 0) {
5160 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5164 if (intel_dp == NULL) {
5165 DRM_DEBUG_KMS("DRRS not supported.\n");
5170 * FIXME: This needs proper synchronization with psr state for some
5171 * platforms that cannot have PSR and DRRS enabled at the same time.
5174 dig_port = dp_to_dig_port(intel_dp);
5175 encoder = &dig_port->base;
5176 intel_crtc = to_intel_crtc(encoder->base.crtc);
5179 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5183 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5184 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5188 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5190 index = DRRS_LOW_RR;
5192 if (index == dev_priv->drrs.refresh_rate_type) {
5194 "DRRS requested for previously set RR...ignoring\n");
5198 if (!crtc_state->base.active) {
5199 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5203 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5206 intel_dp_set_m_n(intel_crtc, M1_N1);
5209 intel_dp_set_m_n(intel_crtc, M2_N2);
5213 DRM_ERROR("Unsupported refreshrate type\n");
5215 } else if (INTEL_GEN(dev_priv) > 6) {
5216 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5219 val = I915_READ(reg);
5220 if (index > DRRS_HIGH_RR) {
5221 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5222 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5224 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5226 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5227 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5229 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5231 I915_WRITE(reg, val);
5234 dev_priv->drrs.refresh_rate_type = index;
5236 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5240 * intel_edp_drrs_enable - init drrs struct if supported
5241 * @intel_dp: DP struct
5242 * @crtc_state: A pointer to the active crtc state.
5244 * Initializes frontbuffer_bits and drrs.dp
5246 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5247 struct intel_crtc_state *crtc_state)
5249 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5250 struct drm_i915_private *dev_priv = to_i915(dev);
5252 if (!crtc_state->has_drrs) {
5253 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5257 mutex_lock(&dev_priv->drrs.mutex);
5258 if (WARN_ON(dev_priv->drrs.dp)) {
5259 DRM_ERROR("DRRS already enabled\n");
5263 dev_priv->drrs.busy_frontbuffer_bits = 0;
5265 dev_priv->drrs.dp = intel_dp;
5268 mutex_unlock(&dev_priv->drrs.mutex);
5272 * intel_edp_drrs_disable - Disable DRRS
5273 * @intel_dp: DP struct
5274 * @old_crtc_state: Pointer to old crtc_state.
5277 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5278 struct intel_crtc_state *old_crtc_state)
5280 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5281 struct drm_i915_private *dev_priv = to_i915(dev);
5283 if (!old_crtc_state->has_drrs)
5286 mutex_lock(&dev_priv->drrs.mutex);
5287 if (!dev_priv->drrs.dp) {
5288 mutex_unlock(&dev_priv->drrs.mutex);
5292 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5293 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5294 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5296 dev_priv->drrs.dp = NULL;
5297 mutex_unlock(&dev_priv->drrs.mutex);
5299 cancel_delayed_work_sync(&dev_priv->drrs.work);
5302 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5304 struct drm_i915_private *dev_priv =
5305 container_of(work, typeof(*dev_priv), drrs.work.work);
5306 struct intel_dp *intel_dp;
5308 mutex_lock(&dev_priv->drrs.mutex);
5310 intel_dp = dev_priv->drrs.dp;
5316 * The delayed work can race with an invalidate hence we need to
5320 if (dev_priv->drrs.busy_frontbuffer_bits)
5323 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5324 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5326 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5327 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5331 mutex_unlock(&dev_priv->drrs.mutex);
5335 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5336 * @dev_priv: i915 device
5337 * @frontbuffer_bits: frontbuffer plane tracking bits
5339 * This function gets called everytime rendering on the given planes start.
5340 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5342 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5344 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5345 unsigned int frontbuffer_bits)
5347 struct drm_crtc *crtc;
5350 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5353 cancel_delayed_work(&dev_priv->drrs.work);
5355 mutex_lock(&dev_priv->drrs.mutex);
5356 if (!dev_priv->drrs.dp) {
5357 mutex_unlock(&dev_priv->drrs.mutex);
5361 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5362 pipe = to_intel_crtc(crtc)->pipe;
5364 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5365 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5367 /* invalidate means busy screen hence upclock */
5368 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5369 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5370 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5372 mutex_unlock(&dev_priv->drrs.mutex);
5376 * intel_edp_drrs_flush - Restart Idleness DRRS
5377 * @dev_priv: i915 device
5378 * @frontbuffer_bits: frontbuffer plane tracking bits
5380 * This function gets called every time rendering on the given planes has
5381 * completed or flip on a crtc is completed. So DRRS should be upclocked
5382 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5383 * if no other planes are dirty.
5385 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5387 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5388 unsigned int frontbuffer_bits)
5390 struct drm_crtc *crtc;
5393 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5396 cancel_delayed_work(&dev_priv->drrs.work);
5398 mutex_lock(&dev_priv->drrs.mutex);
5399 if (!dev_priv->drrs.dp) {
5400 mutex_unlock(&dev_priv->drrs.mutex);
5404 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5405 pipe = to_intel_crtc(crtc)->pipe;
5407 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5408 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5410 /* flush means busy screen hence upclock */
5411 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5412 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5413 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5416 * flush also means no more activity hence schedule downclock, if all
5417 * other fbs are quiescent too
5419 if (!dev_priv->drrs.busy_frontbuffer_bits)
5420 schedule_delayed_work(&dev_priv->drrs.work,
5421 msecs_to_jiffies(1000));
5422 mutex_unlock(&dev_priv->drrs.mutex);
5426 * DOC: Display Refresh Rate Switching (DRRS)
5428 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5429 * which enables swtching between low and high refresh rates,
5430 * dynamically, based on the usage scenario. This feature is applicable
5431 * for internal panels.
5433 * Indication that the panel supports DRRS is given by the panel EDID, which
5434 * would list multiple refresh rates for one resolution.
5436 * DRRS is of 2 types - static and seamless.
5437 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5438 * (may appear as a blink on screen) and is used in dock-undock scenario.
5439 * Seamless DRRS involves changing RR without any visual effect to the user
5440 * and can be used during normal system usage. This is done by programming
5441 * certain registers.
5443 * Support for static/seamless DRRS may be indicated in the VBT based on
5444 * inputs from the panel spec.
5446 * DRRS saves power by switching to low RR based on usage scenarios.
5448 * The implementation is based on frontbuffer tracking implementation. When
5449 * there is a disturbance on the screen triggered by user activity or a periodic
5450 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5451 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5454 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5455 * and intel_edp_drrs_flush() are called.
5457 * DRRS can be further extended to support other internal panels and also
5458 * the scenario of video playback wherein RR is set based on the rate
5459 * requested by userspace.
5463 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5464 * @intel_connector: eDP connector
5465 * @fixed_mode: preferred mode of panel
5467 * This function is called only once at driver load to initialize basic
5471 * Downclock mode if panel supports it, else return NULL.
5472 * DRRS support is determined by the presence of downclock mode (apart
5473 * from VBT setting).
5475 static struct drm_display_mode *
5476 intel_dp_drrs_init(struct intel_connector *intel_connector,
5477 struct drm_display_mode *fixed_mode)
5479 struct drm_connector *connector = &intel_connector->base;
5480 struct drm_device *dev = connector->dev;
5481 struct drm_i915_private *dev_priv = to_i915(dev);
5482 struct drm_display_mode *downclock_mode = NULL;
5484 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5485 mutex_init(&dev_priv->drrs.mutex);
5487 if (INTEL_INFO(dev)->gen <= 6) {
5488 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5492 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5493 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5497 downclock_mode = intel_find_panel_downclock
5498 (dev, fixed_mode, connector);
5500 if (!downclock_mode) {
5501 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5505 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5507 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5508 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5509 return downclock_mode;
5512 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5513 struct intel_connector *intel_connector)
5515 struct drm_connector *connector = &intel_connector->base;
5516 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5517 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5518 struct drm_device *dev = intel_encoder->base.dev;
5519 struct drm_i915_private *dev_priv = to_i915(dev);
5520 struct drm_display_mode *fixed_mode = NULL;
5521 struct drm_display_mode *downclock_mode = NULL;
5523 struct drm_display_mode *scan;
5525 enum pipe pipe = INVALID_PIPE;
5527 if (!is_edp(intel_dp))
5531 * On IBX/CPT we may get here with LVDS already registered. Since the
5532 * driver uses the only internal power sequencer available for both
5533 * eDP and LVDS bail out early in this case to prevent interfering
5534 * with an already powered-on LVDS power sequencer.
5536 if (intel_get_lvds_encoder(dev)) {
5537 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5538 DRM_INFO("LVDS was detected, not registering eDP\n");
5545 intel_dp_init_panel_power_timestamps(intel_dp);
5546 intel_dp_pps_init(dev, intel_dp);
5547 intel_edp_panel_vdd_sanitize(intel_dp);
5549 pps_unlock(intel_dp);
5551 /* Cache DPCD and EDID for edp. */
5552 has_dpcd = intel_edp_init_dpcd(intel_dp);
5555 /* if this fails, presume the device is a ghost */
5556 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5560 mutex_lock(&dev->mode_config.mutex);
5561 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5563 if (drm_add_edid_modes(connector, edid)) {
5564 drm_mode_connector_update_edid_property(connector,
5566 drm_edid_to_eld(connector, edid);
5569 edid = ERR_PTR(-EINVAL);
5572 edid = ERR_PTR(-ENOENT);
5574 intel_connector->edid = edid;
5576 /* prefer fixed mode from EDID if available */
5577 list_for_each_entry(scan, &connector->probed_modes, head) {
5578 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5579 fixed_mode = drm_mode_duplicate(dev, scan);
5580 downclock_mode = intel_dp_drrs_init(
5581 intel_connector, fixed_mode);
5586 /* fallback to VBT if available for eDP */
5587 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5588 fixed_mode = drm_mode_duplicate(dev,
5589 dev_priv->vbt.lfp_lvds_vbt_mode);
5591 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5592 connector->display_info.width_mm = fixed_mode->width_mm;
5593 connector->display_info.height_mm = fixed_mode->height_mm;
5596 mutex_unlock(&dev->mode_config.mutex);
5598 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5599 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5600 register_reboot_notifier(&intel_dp->edp_notifier);
5603 * Figure out the current pipe for the initial backlight setup.
5604 * If the current pipe isn't valid, try the PPS pipe, and if that
5605 * fails just assume pipe A.
5607 if (IS_CHERRYVIEW(dev_priv))
5608 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5610 pipe = PORT_TO_PIPE(intel_dp->DP);
5612 if (pipe != PIPE_A && pipe != PIPE_B)
5613 pipe = intel_dp->pps_pipe;
5615 if (pipe != PIPE_A && pipe != PIPE_B)
5618 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5622 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5623 intel_connector->panel.backlight.power = intel_edp_backlight_power;
5624 intel_panel_setup_backlight(connector, pipe);
5629 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5631 * vdd might still be enabled do to the delayed vdd off.
5632 * Make sure vdd is actually turned off here.
5635 edp_panel_vdd_off_sync(intel_dp);
5636 pps_unlock(intel_dp);
5642 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5643 struct intel_connector *intel_connector)
5645 struct drm_connector *connector = &intel_connector->base;
5646 struct intel_dp *intel_dp = &intel_dig_port->dp;
5647 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5648 struct drm_device *dev = intel_encoder->base.dev;
5649 struct drm_i915_private *dev_priv = to_i915(dev);
5650 enum port port = intel_dig_port->port;
5653 if (WARN(intel_dig_port->max_lanes < 1,
5654 "Not enough lanes (%d) for DP on port %c\n",
5655 intel_dig_port->max_lanes, port_name(port)))
5658 intel_dp->pps_pipe = INVALID_PIPE;
5660 /* intel_dp vfuncs */
5661 if (INTEL_INFO(dev)->gen >= 9)
5662 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5663 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5664 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5665 else if (HAS_PCH_SPLIT(dev_priv))
5666 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5668 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5670 if (INTEL_INFO(dev)->gen >= 9)
5671 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5673 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5675 if (HAS_DDI(dev_priv))
5676 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5678 /* Preserve the current hw state. */
5679 intel_dp->DP = I915_READ(intel_dp->output_reg);
5680 intel_dp->attached_connector = intel_connector;
5682 if (intel_dp_is_edp(dev, port))
5683 type = DRM_MODE_CONNECTOR_eDP;
5685 type = DRM_MODE_CONNECTOR_DisplayPort;
5688 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5689 * for DP the encoder type can be set by the caller to
5690 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5692 if (type == DRM_MODE_CONNECTOR_eDP)
5693 intel_encoder->type = INTEL_OUTPUT_EDP;
5695 /* eDP only on port B and/or C on vlv/chv */
5696 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
5697 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5700 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5701 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5704 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5705 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5707 connector->interlace_allowed = true;
5708 connector->doublescan_allowed = 0;
5710 intel_dp_aux_init(intel_dp);
5712 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5713 edp_panel_vdd_work);
5715 intel_connector_attach_encoder(intel_connector, intel_encoder);
5717 if (HAS_DDI(dev_priv))
5718 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5720 intel_connector->get_hw_state = intel_connector_get_hw_state;
5722 /* Set up the hotplug pin. */
5725 intel_encoder->hpd_pin = HPD_PORT_A;
5728 intel_encoder->hpd_pin = HPD_PORT_B;
5729 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
5730 intel_encoder->hpd_pin = HPD_PORT_A;
5733 intel_encoder->hpd_pin = HPD_PORT_C;
5736 intel_encoder->hpd_pin = HPD_PORT_D;
5739 intel_encoder->hpd_pin = HPD_PORT_E;
5745 /* init MST on ports that can support it */
5746 if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
5747 (port == PORT_B || port == PORT_C || port == PORT_D))
5748 intel_dp_mst_encoder_init(intel_dig_port,
5749 intel_connector->base.base.id);
5751 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5752 intel_dp_aux_fini(intel_dp);
5753 intel_dp_mst_encoder_cleanup(intel_dig_port);
5757 intel_dp_add_properties(intel_dp, connector);
5759 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5760 * 0xd. Failure to do so will result in spurious interrupts being
5761 * generated on the port when a cable is not attached.
5763 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
5764 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5765 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5771 drm_connector_cleanup(connector);
5776 bool intel_dp_init(struct drm_device *dev,
5777 i915_reg_t output_reg,
5780 struct drm_i915_private *dev_priv = to_i915(dev);
5781 struct intel_digital_port *intel_dig_port;
5782 struct intel_encoder *intel_encoder;
5783 struct drm_encoder *encoder;
5784 struct intel_connector *intel_connector;
5786 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5787 if (!intel_dig_port)
5790 intel_connector = intel_connector_alloc();
5791 if (!intel_connector)
5792 goto err_connector_alloc;
5794 intel_encoder = &intel_dig_port->base;
5795 encoder = &intel_encoder->base;
5797 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5798 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
5799 goto err_encoder_init;
5801 intel_encoder->compute_config = intel_dp_compute_config;
5802 intel_encoder->disable = intel_disable_dp;
5803 intel_encoder->get_hw_state = intel_dp_get_hw_state;
5804 intel_encoder->get_config = intel_dp_get_config;
5805 intel_encoder->suspend = intel_dp_encoder_suspend;
5806 if (IS_CHERRYVIEW(dev_priv)) {
5807 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5808 intel_encoder->pre_enable = chv_pre_enable_dp;
5809 intel_encoder->enable = vlv_enable_dp;
5810 intel_encoder->post_disable = chv_post_disable_dp;
5811 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
5812 } else if (IS_VALLEYVIEW(dev_priv)) {
5813 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5814 intel_encoder->pre_enable = vlv_pre_enable_dp;
5815 intel_encoder->enable = vlv_enable_dp;
5816 intel_encoder->post_disable = vlv_post_disable_dp;
5818 intel_encoder->pre_enable = g4x_pre_enable_dp;
5819 intel_encoder->enable = g4x_enable_dp;
5820 if (INTEL_INFO(dev)->gen >= 5)
5821 intel_encoder->post_disable = ilk_post_disable_dp;
5824 intel_dig_port->port = port;
5825 intel_dig_port->dp.output_reg = output_reg;
5826 intel_dig_port->max_lanes = 4;
5828 intel_encoder->type = INTEL_OUTPUT_DP;
5829 if (IS_CHERRYVIEW(dev_priv)) {
5831 intel_encoder->crtc_mask = 1 << 2;
5833 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5835 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5837 intel_encoder->cloneable = 0;
5838 intel_encoder->port = port;
5840 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5841 dev_priv->hotplug.irq_port[port] = intel_dig_port;
5843 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5844 goto err_init_connector;
5849 drm_encoder_cleanup(encoder);
5851 kfree(intel_connector);
5852 err_connector_alloc:
5853 kfree(intel_dig_port);
5857 void intel_dp_mst_suspend(struct drm_device *dev)
5859 struct drm_i915_private *dev_priv = to_i915(dev);
5863 for (i = 0; i < I915_MAX_PORTS; i++) {
5864 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5866 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5869 if (intel_dig_port->dp.is_mst)
5870 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5874 void intel_dp_mst_resume(struct drm_device *dev)
5876 struct drm_i915_private *dev_priv = to_i915(dev);
5879 for (i = 0; i < I915_MAX_PORTS; i++) {
5880 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5883 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5886 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5888 intel_dp_check_mst_status(&intel_dig_port->dp);