drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 struct intel_dp {
  46         struct intel_encoder base;
  47         uint32_t output_reg;
  48         uint32_t DP;
  49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  50         bool has_audio;
  51         int force_audio;
  52         uint32_t color_range;
  53         int dpms_mode;
  54         uint8_t link_bw;
  55         uint8_t lane_count;
  56         uint8_t dpcd[8];
  57         struct i2c_adapter adapter;
  58         struct i2c_algo_dp_aux_data algo;
  59         bool is_pch_edp;
  60         uint8_t train_set[4];
  61         uint8_t link_status[DP_LINK_STATUS_SIZE];
  62 };
  63
  64 /**
  65  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  66  * @intel_dp: DP struct
  67  *
  68  * If a CPU or PCH DP output is attached to an eDP panel, this function
  69  * will return true, and false otherwise.
  70  */
  71 static bool is_edp(struct intel_dp *intel_dp)
  72 {
  73         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  74 }
  75
  76 /**
  77  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  78  * @intel_dp: DP struct
  79  *
  80  * Returns true if the given DP struct corresponds to a PCH DP port attached
  81  * to an eDP panel, false otherwise.  Helpful for determining whether we
  82  * may need FDI resources for a given DP output or not.
  83  */
  84 static bool is_pch_edp(struct intel_dp *intel_dp)
  85 {
  86         return intel_dp->is_pch_edp;
  87 }
  88
  89 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  90 {
  91         return container_of(encoder, struct intel_dp, base.base);
  92 }
  93
  94 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  95 {
  96         return container_of(intel_attached_encoder(connector),
  97                             struct intel_dp, base);
  98 }
  99
 100 /**
 101  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 102  * @encoder: DRM encoder
 103  *
 104  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 105  * by intel_display.c.
 106  */
 107 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 108 {
 109         struct intel_dp *intel_dp;
 110
 111         if (!encoder)
 112                 return false;
 113
 114         intel_dp = enc_to_intel_dp(encoder);
 115
 116         return is_pch_edp(intel_dp);
 117 }
 118
 119 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 120 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 121 static void intel_dp_link_down(struct intel_dp *intel_dp);
 122
 123 void
 124 intel_edp_link_config (struct intel_encoder *intel_encoder,
 125                        int *lane_num, int *link_bw)
 126 {
 127         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 128
 129         *lane_num = intel_dp->lane_count;
 130         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 131                 *link_bw = 162000;
 132         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 133                 *link_bw = 270000;
 134 }
 135
 136 static int
 137 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 138 {
 139         int max_lane_count = 4;
 140
 141         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
 142                 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 143                 switch (max_lane_count) {
 144                 case 1: case 2: case 4:
 145                         break;
 146                 default:
 147                         max_lane_count = 4;
 148                 }
 149         }
 150         return max_lane_count;
 151 }
 152
 153 static int
 154 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 155 {
 156         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 157
 158         switch (max_link_bw) {
 159         case DP_LINK_BW_1_62:
 160         case DP_LINK_BW_2_7:
 161                 break;
 162         default:
 163                 max_link_bw = DP_LINK_BW_1_62;
 164                 break;
 165         }
 166         return max_link_bw;
 167 }
 168
 169 static int
 170 intel_dp_link_clock(uint8_t link_bw)
 171 {
 172         if (link_bw == DP_LINK_BW_2_7)
 173                 return 270000;
 174         else
 175                 return 162000;
 176 }
 177
 178 /* I think this is a fiction */
 179 static int
 180 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
 181 {
 182         struct drm_i915_private *dev_priv = dev->dev_private;
 183
 184         if (is_edp(intel_dp))
 185                 return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
 186         else
 187                 return pixel_clock * 3;
 188 }
 189
 190 static int
 191 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 192 {
 193         return (max_link_clock * max_lanes * 8) / 10;
 194 }
 195
 196 static int
 197 intel_dp_mode_valid(struct drm_connector *connector,
 198                     struct drm_display_mode *mode)
 199 {
 200         struct intel_dp *intel_dp = intel_attached_dp(connector);
 201         struct drm_device *dev = connector->dev;
 202         struct drm_i915_private *dev_priv = dev->dev_private;
 203         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 204         int max_lanes = intel_dp_max_lane_count(intel_dp);
 205
 206         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 207                 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
 208                         return MODE_PANEL;
 209
 210                 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
 211                         return MODE_PANEL;
 212         }
 213
 214         /* only refuse the mode on non eDP since we have seen some weird eDP panels
 215            which are outside spec tolerances but somehow work by magic */
 216         if (!is_edp(intel_dp) &&
 217             (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
 218              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 219                 return MODE_CLOCK_HIGH;
 220
 221         if (mode->clock < 10000)
 222                 return MODE_CLOCK_LOW;
 223
 224         return MODE_OK;
 225 }
 226
 227 static uint32_t
 228 pack_aux(uint8_t *src, int src_bytes)
 229 {
 230         int     i;
 231         uint32_t v = 0;
 232
 233         if (src_bytes > 4)
 234                 src_bytes = 4;
 235         for (i = 0; i < src_bytes; i++)
 236                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 237         return v;
 238 }
 239
 240 static void
 241 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 242 {
 243         int i;
 244         if (dst_bytes > 4)
 245                 dst_bytes = 4;
 246         for (i = 0; i < dst_bytes; i++)
 247                 dst[i] = src >> ((3-i) * 8);
 248 }
 249
 250 /* hrawclock is 1/4 the FSB frequency */
 251 static int
 252 intel_hrawclk(struct drm_device *dev)
 253 {
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255         uint32_t clkcfg;
 256
 257         clkcfg = I915_READ(CLKCFG);
 258         switch (clkcfg & CLKCFG_FSB_MASK) {
 259         case CLKCFG_FSB_400:
 260                 return 100;
 261         case CLKCFG_FSB_533:
 262                 return 133;
 263         case CLKCFG_FSB_667:
 264                 return 166;
 265         case CLKCFG_FSB_800:
 266                 return 200;
 267         case CLKCFG_FSB_1067:
 268                 return 266;
 269         case CLKCFG_FSB_1333:
 270                 return 333;
 271         /* these two are just a guess; one of them might be right */
 272         case CLKCFG_FSB_1600:
 273         case CLKCFG_FSB_1600_ALT:
 274                 return 400;
 275         default:
 276                 return 133;
 277         }
 278 }
 279
 280 static int
 281 intel_dp_aux_ch(struct intel_dp *intel_dp,
 282                 uint8_t *send, int send_bytes,
 283                 uint8_t *recv, int recv_size)
 284 {
 285         uint32_t output_reg = intel_dp->output_reg;
 286         struct drm_device *dev = intel_dp->base.base.dev;
 287         struct drm_i915_private *dev_priv = dev->dev_private;
 288         uint32_t ch_ctl = output_reg + 0x10;
 289         uint32_t ch_data = ch_ctl + 4;
 290         int i;
 291         int recv_bytes;
 292         uint32_t status;
 293         uint32_t aux_clock_divider;
 294         int try, precharge;
 295
 296         /* The clock divider is based off the hrawclk,
 297          * and would like to run at 2MHz. So, take the
 298          * hrawclk value and divide by 2 and use that
 299          *
 300          * Note that PCH attached eDP panels should use a 125MHz input
 301          * clock divider.
 302          */
 303         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 304                 if (IS_GEN6(dev))
 305                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 306                 else
 307                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 308         } else if (HAS_PCH_SPLIT(dev))
 309                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 310         else
 311                 aux_clock_divider = intel_hrawclk(dev) / 2;
 312
 313         if (IS_GEN6(dev))
 314                 precharge = 3;
 315         else
 316                 precharge = 5;
 317
 318         if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
 319                 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
 320                           I915_READ(ch_ctl));
 321                 return -EBUSY;
 322         }
 323
 324         /* Must try at least 3 times according to DP spec */
 325         for (try = 0; try < 5; try++) {
 326                 /* Load the send data into the aux channel data registers */
 327                 for (i = 0; i < send_bytes; i += 4)
 328                         I915_WRITE(ch_data + i,
 329                                    pack_aux(send + i, send_bytes - i));
 330
 331                 /* Send the command and wait for it to complete */
 332                 I915_WRITE(ch_ctl,
 333                            DP_AUX_CH_CTL_SEND_BUSY |
 334                            DP_AUX_CH_CTL_TIME_OUT_400us |
 335                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 336                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 337                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 338                            DP_AUX_CH_CTL_DONE |
 339                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 340                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 341                 for (;;) {
 342                         status = I915_READ(ch_ctl);
 343                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 344                                 break;
 345                         udelay(100);
 346                 }
 347
 348                 /* Clear done status and any errors */
 349                 I915_WRITE(ch_ctl,
 350                            status |
 351                            DP_AUX_CH_CTL_DONE |
 352                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 353                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 354                 if (status & DP_AUX_CH_CTL_DONE)
 355                         break;
 356         }
 357
 358         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 359                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 360                 return -EBUSY;
 361         }
 362
 363         /* Check for timeout or receive error.
 364          * Timeouts occur when the sink is not connected
 365          */
 366         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 367                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 368                 return -EIO;
 369         }
 370
 371         /* Timeouts occur when the device isn't connected, so they're
 372          * "normal" -- don't fill the kernel log with these */
 373         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 374                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 375                 return -ETIMEDOUT;
 376         }
 377
 378         /* Unload any bytes sent back from the other side */
 379         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 380                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 381         if (recv_bytes > recv_size)
 382                 recv_bytes = recv_size;
 383
 384         for (i = 0; i < recv_bytes; i += 4)
 385                 unpack_aux(I915_READ(ch_data + i),
 386                            recv + i, recv_bytes - i);
 387
 388         return recv_bytes;
 389 }
 390
 391 /* Write data to the aux channel in native mode */
 392 static int
 393 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 394                           uint16_t address, uint8_t *send, int send_bytes)
 395 {
 396         int ret;
 397         uint8_t msg[20];
 398         int msg_bytes;
 399         uint8_t ack;
 400
 401         if (send_bytes > 16)
 402                 return -1;
 403         msg[0] = AUX_NATIVE_WRITE << 4;
 404         msg[1] = address >> 8;
 405         msg[2] = address & 0xff;
 406         msg[3] = send_bytes - 1;
 407         memcpy(&msg[4], send, send_bytes);
 408         msg_bytes = send_bytes + 4;
 409         for (;;) {
 410                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 411                 if (ret < 0)
 412                         return ret;
 413                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 414                         break;
 415                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 416                         udelay(100);
 417                 else
 418                         return -EIO;
 419         }
 420         return send_bytes;
 421 }
 422
 423 /* Write a single byte to the aux channel in native mode */
 424 static int
 425 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 426                             uint16_t address, uint8_t byte)
 427 {
 428         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 429 }
 430
 431 /* read bytes from a native aux channel */
 432 static int
 433 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 434                          uint16_t address, uint8_t *recv, int recv_bytes)
 435 {
 436         uint8_t msg[4];
 437         int msg_bytes;
 438         uint8_t reply[20];
 439         int reply_bytes;
 440         uint8_t ack;
 441         int ret;
 442
 443         msg[0] = AUX_NATIVE_READ << 4;
 444         msg[1] = address >> 8;
 445         msg[2] = address & 0xff;
 446         msg[3] = recv_bytes - 1;
 447
 448         msg_bytes = 4;
 449         reply_bytes = recv_bytes + 1;
 450
 451         for (;;) {
 452                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 453                                       reply, reply_bytes);
 454                 if (ret == 0)
 455                         return -EPROTO;
 456                 if (ret < 0)
 457                         return ret;
 458                 ack = reply[0];
 459                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 460                         memcpy(recv, reply + 1, ret - 1);
 461                         return ret - 1;
 462                 }
 463                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 464                         udelay(100);
 465                 else
 466                         return -EIO;
 467         }
 468 }
 469
 470 static int
 471 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 472                     uint8_t write_byte, uint8_t *read_byte)
 473 {
 474         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 475         struct intel_dp *intel_dp = container_of(adapter,
 476                                                 struct intel_dp,
 477                                                 adapter);
 478         uint16_t address = algo_data->address;
 479         uint8_t msg[5];
 480         uint8_t reply[2];
 481         unsigned retry;
 482         int msg_bytes;
 483         int reply_bytes;
 484         int ret;
 485
 486         /* Set up the command byte */
 487         if (mode & MODE_I2C_READ)
 488                 msg[0] = AUX_I2C_READ << 4;
 489         else
 490                 msg[0] = AUX_I2C_WRITE << 4;
 491
 492         if (!(mode & MODE_I2C_STOP))
 493                 msg[0] |= AUX_I2C_MOT << 4;
 494
 495         msg[1] = address >> 8;
 496         msg[2] = address;
 497
 498         switch (mode) {
 499         case MODE_I2C_WRITE:
 500                 msg[3] = 0;
 501                 msg[4] = write_byte;
 502                 msg_bytes = 5;
 503                 reply_bytes = 1;
 504                 break;
 505         case MODE_I2C_READ:
 506                 msg[3] = 0;
 507                 msg_bytes = 4;
 508                 reply_bytes = 2;
 509                 break;
 510         default:
 511                 msg_bytes = 3;
 512                 reply_bytes = 1;
 513                 break;
 514         }
 515
 516         for (retry = 0; retry < 5; retry++) {
 517                 ret = intel_dp_aux_ch(intel_dp,
 518                                       msg, msg_bytes,
 519                                       reply, reply_bytes);
 520                 if (ret < 0) {
 521                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 522                         return ret;
 523                 }
 524
 525                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 526                 case AUX_NATIVE_REPLY_ACK:
 527                         /* I2C-over-AUX Reply field is only valid
 528                          * when paired with AUX ACK.
 529                          */
 530                         break;
 531                 case AUX_NATIVE_REPLY_NACK:
 532                         DRM_DEBUG_KMS("aux_ch native nack\n");
 533                         return -EREMOTEIO;
 534                 case AUX_NATIVE_REPLY_DEFER:
 535                         udelay(100);
 536                         continue;
 537                 default:
 538                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 539                                   reply[0]);
 540                         return -EREMOTEIO;
 541                 }
 542
 543                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 544                 case AUX_I2C_REPLY_ACK:
 545                         if (mode == MODE_I2C_READ) {
 546                                 *read_byte = reply[1];
 547                         }
 548                         return reply_bytes - 1;
 549                 case AUX_I2C_REPLY_NACK:
 550                         DRM_DEBUG_KMS("aux_i2c nack\n");
 551                         return -EREMOTEIO;
 552                 case AUX_I2C_REPLY_DEFER:
 553                         DRM_DEBUG_KMS("aux_i2c defer\n");
 554                         udelay(100);
 555                         break;
 556                 default:
 557                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 558                         return -EREMOTEIO;
 559                 }
 560         }
 561
 562         DRM_ERROR("too many retries, giving up\n");
 563         return -EREMOTEIO;
 564 }
 565
 566 static int
 567 intel_dp_i2c_init(struct intel_dp *intel_dp,
 568                   struct intel_connector *intel_connector, const char *name)
 569 {
 570         DRM_DEBUG_KMS("i2c_init %s\n", name);
 571         intel_dp->algo.running = false;
 572         intel_dp->algo.address = 0;
 573         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 574
 575         memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
 576         intel_dp->adapter.owner = THIS_MODULE;
 577         intel_dp->adapter.class = I2C_CLASS_DDC;
 578         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 579         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 580         intel_dp->adapter.algo_data = &intel_dp->algo;
 581         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 582
 583         return i2c_dp_aux_add_bus(&intel_dp->adapter);
 584 }
 585
 586 static bool
 587 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 588                     struct drm_display_mode *adjusted_mode)
 589 {
 590         struct drm_device *dev = encoder->dev;
 591         struct drm_i915_private *dev_priv = dev->dev_private;
 592         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 593         int lane_count, clock;
 594         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 595         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 596         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 597
 598         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 599                 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
 600                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 601                                         mode, adjusted_mode);
 602                 /*
 603                  * the mode->clock is used to calculate the Data&Link M/N
 604                  * of the pipe. For the eDP the fixed clock should be used.
 605                  */
 606                 mode->clock = dev_priv->panel_fixed_mode->clock;
 607         }
 608
 609         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 610                 for (clock = 0; clock <= max_clock; clock++) {
 611                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 612
 613                         if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
 614                                         <= link_avail) {
 615                                 intel_dp->link_bw = bws[clock];
 616                                 intel_dp->lane_count = lane_count;
 617                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 618                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 619                                                 "count %d clock %d\n",
 620                                        intel_dp->link_bw, intel_dp->lane_count,
 621                                        adjusted_mode->clock);
 622                                 return true;
 623                         }
 624                 }
 625         }
 626
 627         if (is_edp(intel_dp)) {
 628                 /* okay we failed just pick the highest */
 629                 intel_dp->lane_count = max_lane_count;
 630                 intel_dp->link_bw = bws[max_clock];
 631                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 632                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
 633                               "count %d clock %d\n",
 634                               intel_dp->link_bw, intel_dp->lane_count,
 635                               adjusted_mode->clock);
 636
 637                 return true;
 638         }
 639
 640         return false;
 641 }
 642
 643 struct intel_dp_m_n {
 644         uint32_t        tu;
 645         uint32_t        gmch_m;
 646         uint32_t        gmch_n;
 647         uint32_t        link_m;
 648         uint32_t        link_n;
 649 };
 650
 651 static void
 652 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 653 {
 654         while (*num > 0xffffff || *den > 0xffffff) {
 655                 *num >>= 1;
 656                 *den >>= 1;
 657         }
 658 }
 659
 660 static void
 661 intel_dp_compute_m_n(int bpp,
 662                      int nlanes,
 663                      int pixel_clock,
 664                      int link_clock,
 665                      struct intel_dp_m_n *m_n)
 666 {
 667         m_n->tu = 64;
 668         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 669         m_n->gmch_n = link_clock * nlanes;
 670         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 671         m_n->link_m = pixel_clock;
 672         m_n->link_n = link_clock;
 673         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 674 }
 675
 676 void
 677 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 678                  struct drm_display_mode *adjusted_mode)
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_mode_config *mode_config = &dev->mode_config;
 682         struct drm_encoder *encoder;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 685         int lane_count = 4, bpp = 24;
 686         struct intel_dp_m_n m_n;
 687         int pipe = intel_crtc->pipe;
 688
 689         /*
 690          * Find the lane count in the intel_encoder private
 691          */
 692         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 693                 struct intel_dp *intel_dp;
 694
 695                 if (encoder->crtc != crtc)
 696                         continue;
 697
 698                 intel_dp = enc_to_intel_dp(encoder);
 699                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
 700                         lane_count = intel_dp->lane_count;
 701                         break;
 702                 } else if (is_edp(intel_dp)) {
 703                         lane_count = dev_priv->edp.lanes;
 704                         bpp = dev_priv->edp.bpp;
 705                         break;
 706                 }
 707         }
 708
 709         /*
 710          * Compute the GMCH and Link ratios. The '3' here is
 711          * the number of bytes_per_pixel post-LUT, which we always
 712          * set up for 8-bits of R/G/B, or 3 bytes total.
 713          */
 714         intel_dp_compute_m_n(bpp, lane_count,
 715                              mode->clock, adjusted_mode->clock, &m_n);
 716
 717         if (HAS_PCH_SPLIT(dev)) {
 718                 I915_WRITE(TRANSDATA_M1(pipe),
 719                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 720                            m_n.gmch_m);
 721                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 722                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 723                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 724         } else {
 725                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 726                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 727                            m_n.gmch_m);
 728                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 729                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 730                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 731         }
 732 }
 733
 734 static void
 735 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 736                   struct drm_display_mode *adjusted_mode)
 737 {
 738         struct drm_device *dev = encoder->dev;
 739         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 740         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 742
 743         intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 744         intel_dp->DP |= intel_dp->color_range;
 745
 746         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 747                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 748         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 749                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 750
 751         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
 752                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 753         else
 754                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 755
 756         switch (intel_dp->lane_count) {
 757         case 1:
 758                 intel_dp->DP |= DP_PORT_WIDTH_1;
 759                 break;
 760         case 2:
 761                 intel_dp->DP |= DP_PORT_WIDTH_2;
 762                 break;
 763         case 4:
 764                 intel_dp->DP |= DP_PORT_WIDTH_4;
 765                 break;
 766         }
 767         if (intel_dp->has_audio)
 768                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 769
 770         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 771         intel_dp->link_configuration[0] = intel_dp->link_bw;
 772         intel_dp->link_configuration[1] = intel_dp->lane_count;
 773         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 774
 775         /*
 776          * Check for DPCD version > 1.1 and enhanced framing support
 777          */
 778         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 779             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 780                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 781                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 782         }
 783
 784         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 785         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 786                 intel_dp->DP |= DP_PIPEB_SELECT;
 787
 788         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 789                 /* don't miss out required setting for eDP */
 790                 intel_dp->DP |= DP_PLL_ENABLE;
 791                 if (adjusted_mode->clock < 200000)
 792                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 793                 else
 794                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 795         }
 796 }
 797
 798 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 799 {
 800         struct drm_device *dev = intel_dp->base.base.dev;
 801         struct drm_i915_private *dev_priv = dev->dev_private;
 802         u32 pp;
 803
 804         /*
 805          * If the panel wasn't on, make sure there's not a currently
 806          * active PP sequence before enabling AUX VDD.
 807          */
 808         if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
 809                 msleep(dev_priv->panel_t3);
 810
 811         pp = I915_READ(PCH_PP_CONTROL);
 812         pp |= EDP_FORCE_VDD;
 813         I915_WRITE(PCH_PP_CONTROL, pp);
 814         POSTING_READ(PCH_PP_CONTROL);
 815 }
 816
 817 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
 818 {
 819         struct drm_device *dev = intel_dp->base.base.dev;
 820         struct drm_i915_private *dev_priv = dev->dev_private;
 821         u32 pp;
 822
 823         pp = I915_READ(PCH_PP_CONTROL);
 824         pp &= ~EDP_FORCE_VDD;
 825         I915_WRITE(PCH_PP_CONTROL, pp);
 826         POSTING_READ(PCH_PP_CONTROL);
 827
 828         /* Make sure sequencer is idle before allowing subsequent activity */
 829         msleep(dev_priv->panel_t12);
 830 }
 831
 832 /* Returns true if the panel was already on when called */
 833 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
 834 {
 835         struct drm_device *dev = intel_dp->base.base.dev;
 836         struct drm_i915_private *dev_priv = dev->dev_private;
 837         u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
 838
 839         if (I915_READ(PCH_PP_STATUS) & PP_ON)
 840                 return true;
 841
 842         pp = I915_READ(PCH_PP_CONTROL);
 843
 844         /* ILK workaround: disable reset around power sequence */
 845         pp &= ~PANEL_POWER_RESET;
 846         I915_WRITE(PCH_PP_CONTROL, pp);
 847         POSTING_READ(PCH_PP_CONTROL);
 848
 849         pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
 850         I915_WRITE(PCH_PP_CONTROL, pp);
 851         POSTING_READ(PCH_PP_CONTROL);
 852
 853         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
 854                      5000))
 855                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
 856                           I915_READ(PCH_PP_STATUS));
 857
 858         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 859         I915_WRITE(PCH_PP_CONTROL, pp);
 860         POSTING_READ(PCH_PP_CONTROL);
 861
 862         return false;
 863 }
 864
 865 static void ironlake_edp_panel_off (struct drm_device *dev)
 866 {
 867         struct drm_i915_private *dev_priv = dev->dev_private;
 868         u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
 869                 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
 870
 871         pp = I915_READ(PCH_PP_CONTROL);
 872
 873         /* ILK workaround: disable reset around power sequence */
 874         pp &= ~PANEL_POWER_RESET;
 875         I915_WRITE(PCH_PP_CONTROL, pp);
 876         POSTING_READ(PCH_PP_CONTROL);
 877
 878         pp &= ~POWER_TARGET_ON;
 879         I915_WRITE(PCH_PP_CONTROL, pp);
 880         POSTING_READ(PCH_PP_CONTROL);
 881
 882         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
 883                 DRM_ERROR("panel off wait timed out: 0x%08x\n",
 884                           I915_READ(PCH_PP_STATUS));
 885
 886         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 887         I915_WRITE(PCH_PP_CONTROL, pp);
 888         POSTING_READ(PCH_PP_CONTROL);
 889 }
 890
 891 static void ironlake_edp_backlight_on (struct drm_device *dev)
 892 {
 893         struct drm_i915_private *dev_priv = dev->dev_private;
 894         u32 pp;
 895
 896         DRM_DEBUG_KMS("\n");
 897         /*
 898          * If we enable the backlight right away following a panel power
 899          * on, we may see slight flicker as the panel syncs with the eDP
 900          * link.  So delay a bit to make sure the image is solid before
 901          * allowing it to appear.
 902          */
 903         msleep(300);
 904         pp = I915_READ(PCH_PP_CONTROL);
 905         pp |= EDP_BLC_ENABLE;
 906         I915_WRITE(PCH_PP_CONTROL, pp);
 907 }
 908
 909 static void ironlake_edp_backlight_off (struct drm_device *dev)
 910 {
 911         struct drm_i915_private *dev_priv = dev->dev_private;
 912         u32 pp;
 913
 914         DRM_DEBUG_KMS("\n");
 915         pp = I915_READ(PCH_PP_CONTROL);
 916         pp &= ~EDP_BLC_ENABLE;
 917         I915_WRITE(PCH_PP_CONTROL, pp);
 918 }
 919
 920 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
 921 {
 922         struct drm_device *dev = encoder->dev;
 923         struct drm_i915_private *dev_priv = dev->dev_private;
 924         u32 dpa_ctl;
 925
 926         DRM_DEBUG_KMS("\n");
 927         dpa_ctl = I915_READ(DP_A);
 928         dpa_ctl |= DP_PLL_ENABLE;
 929         I915_WRITE(DP_A, dpa_ctl);
 930         POSTING_READ(DP_A);
 931         udelay(200);
 932 }
 933
 934 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
 935 {
 936         struct drm_device *dev = encoder->dev;
 937         struct drm_i915_private *dev_priv = dev->dev_private;
 938         u32 dpa_ctl;
 939
 940         dpa_ctl = I915_READ(DP_A);
 941         dpa_ctl &= ~DP_PLL_ENABLE;
 942         I915_WRITE(DP_A, dpa_ctl);
 943         POSTING_READ(DP_A);
 944         udelay(200);
 945 }
 946
 947 /* If the sink supports it, try to set the power state appropriately */
 948 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
 949 {
 950         int ret, i;
 951
 952         /* Should have a valid DPCD by this point */
 953         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
 954                 return;
 955
 956         if (mode != DRM_MODE_DPMS_ON) {
 957                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
 958                                                   DP_SET_POWER_D3);
 959                 if (ret != 1)
 960                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
 961         } else {
 962                 /*
 963                  * When turning on, we need to retry for 1ms to give the sink
 964                  * time to wake up.
 965                  */
 966                 for (i = 0; i < 3; i++) {
 967                         ret = intel_dp_aux_native_write_1(intel_dp,
 968                                                           DP_SET_POWER,
 969                                                           DP_SET_POWER_D0);
 970                         if (ret == 1)
 971                                 break;
 972                         msleep(1);
 973                 }
 974         }
 975 }
 976
 977 static void intel_dp_prepare(struct drm_encoder *encoder)
 978 {
 979         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 980         struct drm_device *dev = encoder->dev;
 981
 982         /* Wake up the sink first */
 983         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 984
 985         if (is_edp(intel_dp)) {
 986                 ironlake_edp_backlight_off(dev);
 987                 ironlake_edp_panel_off(dev);
 988                 if (!is_pch_edp(intel_dp))
 989                         ironlake_edp_pll_on(encoder);
 990                 else
 991                         ironlake_edp_pll_off(encoder);
 992         }
 993         intel_dp_link_down(intel_dp);
 994 }
 995
 996 static void intel_dp_commit(struct drm_encoder *encoder)
 997 {
 998         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 999         struct drm_device *dev = encoder->dev;
1000
1001         if (is_edp(intel_dp))
1002                 ironlake_edp_panel_vdd_on(intel_dp);
1003
1004         intel_dp_start_link_train(intel_dp);
1005
1006         if (is_edp(intel_dp)) {
1007                 ironlake_edp_panel_on(intel_dp);
1008                 ironlake_edp_panel_vdd_off(intel_dp);
1009         }
1010
1011         intel_dp_complete_link_train(intel_dp);
1012
1013         if (is_edp(intel_dp))
1014                 ironlake_edp_backlight_on(dev);
1015
1016         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1017 }
1018
1019 static void
1020 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1021 {
1022         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1023         struct drm_device *dev = encoder->dev;
1024         struct drm_i915_private *dev_priv = dev->dev_private;
1025         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1026
1027         if (mode != DRM_MODE_DPMS_ON) {
1028                 if (is_edp(intel_dp))
1029                         ironlake_edp_backlight_off(dev);
1030                 intel_dp_sink_dpms(intel_dp, mode);
1031                 intel_dp_link_down(intel_dp);
1032                 if (is_edp(intel_dp))
1033                         ironlake_edp_panel_off(dev);
1034                 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
1035                         ironlake_edp_pll_off(encoder);
1036         } else {
1037                 if (is_edp(intel_dp))
1038                         ironlake_edp_panel_vdd_on(intel_dp);
1039                 intel_dp_sink_dpms(intel_dp, mode);
1040                 if (!(dp_reg & DP_PORT_EN)) {
1041                         intel_dp_start_link_train(intel_dp);
1042                         if (is_edp(intel_dp)) {
1043                                 ironlake_edp_panel_on(intel_dp);
1044                                 ironlake_edp_panel_vdd_off(intel_dp);
1045                         }
1046                         intel_dp_complete_link_train(intel_dp);
1047                 }
1048                 if (is_edp(intel_dp))
1049                         ironlake_edp_backlight_on(dev);
1050         }
1051         intel_dp->dpms_mode = mode;
1052 }
1053
1054 /*
1055  * Native read with retry for link status and receiver capability reads for
1056  * cases where the sink may still be asleep.
1057  */
1058 static bool
1059 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1060                                uint8_t *recv, int recv_bytes)
1061 {
1062         int ret, i;
1063
1064         /*
1065          * Sinks are *supposed* to come up within 1ms from an off state,
1066          * but we're also supposed to retry 3 times per the spec.
1067          */
1068         for (i = 0; i < 3; i++) {
1069                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1070                                                recv_bytes);
1071                 if (ret == recv_bytes)
1072                         return true;
1073                 msleep(1);
1074         }
1075
1076         return false;
1077 }
1078
1079 /*
1080  * Fetch AUX CH registers 0x202 - 0x207 which contain
1081  * link status information
1082  */
1083 static bool
1084 intel_dp_get_link_status(struct intel_dp *intel_dp)
1085 {
1086         return intel_dp_aux_native_read_retry(intel_dp,
1087                                               DP_LANE0_1_STATUS,
1088                                               intel_dp->link_status,
1089                                               DP_LINK_STATUS_SIZE);
1090 }
1091
1092 static uint8_t
1093 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1094                      int r)
1095 {
1096         return link_status[r - DP_LANE0_1_STATUS];
1097 }
1098
1099 static uint8_t
1100 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1101                                  int lane)
1102 {
1103         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1104         int         s = ((lane & 1) ?
1105                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1106                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1107         uint8_t l = intel_dp_link_status(link_status, i);
1108
1109         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1110 }
1111
1112 static uint8_t
1113 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1114                                       int lane)
1115 {
1116         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1117         int         s = ((lane & 1) ?
1118                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1119                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1120         uint8_t l = intel_dp_link_status(link_status, i);
1121
1122         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1123 }
1124
1125
1126 #if 0
1127 static char     *voltage_names[] = {
1128         "0.4V", "0.6V", "0.8V", "1.2V"
1129 };
1130 static char     *pre_emph_names[] = {
1131         "0dB", "3.5dB", "6dB", "9.5dB"
1132 };
1133 static char     *link_train_names[] = {
1134         "pattern 1", "pattern 2", "idle", "off"
1135 };
1136 #endif
1137
1138 /*
1139  * These are source-specific values; current Intel hardware supports
1140  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1141  */
1142 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1143
1144 static uint8_t
1145 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1146 {
1147         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1148         case DP_TRAIN_VOLTAGE_SWING_400:
1149                 return DP_TRAIN_PRE_EMPHASIS_6;
1150         case DP_TRAIN_VOLTAGE_SWING_600:
1151                 return DP_TRAIN_PRE_EMPHASIS_6;
1152         case DP_TRAIN_VOLTAGE_SWING_800:
1153                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1154         case DP_TRAIN_VOLTAGE_SWING_1200:
1155         default:
1156                 return DP_TRAIN_PRE_EMPHASIS_0;
1157         }
1158 }
1159
1160 static void
1161 intel_get_adjust_train(struct intel_dp *intel_dp)
1162 {
1163         uint8_t v = 0;
1164         uint8_t p = 0;
1165         int lane;
1166
1167         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1168                 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1169                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1170
1171                 if (this_v > v)
1172                         v = this_v;
1173                 if (this_p > p)
1174                         p = this_p;
1175         }
1176
1177         if (v >= I830_DP_VOLTAGE_MAX)
1178                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1179
1180         if (p >= intel_dp_pre_emphasis_max(v))
1181                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1182
1183         for (lane = 0; lane < 4; lane++)
1184                 intel_dp->train_set[lane] = v | p;
1185 }
1186
1187 static uint32_t
1188 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1189 {
1190         uint32_t        signal_levels = 0;
1191
1192         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1193         case DP_TRAIN_VOLTAGE_SWING_400:
1194         default:
1195                 signal_levels |= DP_VOLTAGE_0_4;
1196                 break;
1197         case DP_TRAIN_VOLTAGE_SWING_600:
1198                 signal_levels |= DP_VOLTAGE_0_6;
1199                 break;
1200         case DP_TRAIN_VOLTAGE_SWING_800:
1201                 signal_levels |= DP_VOLTAGE_0_8;
1202                 break;
1203         case DP_TRAIN_VOLTAGE_SWING_1200:
1204                 signal_levels |= DP_VOLTAGE_1_2;
1205                 break;
1206         }
1207         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1208         case DP_TRAIN_PRE_EMPHASIS_0:
1209         default:
1210                 signal_levels |= DP_PRE_EMPHASIS_0;
1211                 break;
1212         case DP_TRAIN_PRE_EMPHASIS_3_5:
1213                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1214                 break;
1215         case DP_TRAIN_PRE_EMPHASIS_6:
1216                 signal_levels |= DP_PRE_EMPHASIS_6;
1217                 break;
1218         case DP_TRAIN_PRE_EMPHASIS_9_5:
1219                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1220                 break;
1221         }
1222         return signal_levels;
1223 }
1224
1225 /* Gen6's DP voltage swing and pre-emphasis control */
1226 static uint32_t
1227 intel_gen6_edp_signal_levels(uint8_t train_set)
1228 {
1229         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1230                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1231         switch (signal_levels) {
1232         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1233         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1234                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1235         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1236                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1237         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1238         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1239                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1240         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1241         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1242                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1243         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1244         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1245                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1246         default:
1247                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1248                               "0x%x\n", signal_levels);
1249                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1250         }
1251 }
1252
1253 static uint8_t
1254 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1255                       int lane)
1256 {
1257         int i = DP_LANE0_1_STATUS + (lane >> 1);
1258         int s = (lane & 1) * 4;
1259         uint8_t l = intel_dp_link_status(link_status, i);
1260
1261         return (l >> s) & 0xf;
1262 }
1263
1264 /* Check for clock recovery is done on all channels */
1265 static bool
1266 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1267 {
1268         int lane;
1269         uint8_t lane_status;
1270
1271         for (lane = 0; lane < lane_count; lane++) {
1272                 lane_status = intel_get_lane_status(link_status, lane);
1273                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 /* Check to see if channel eq is done on all channels */
1280 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1281                          DP_LANE_CHANNEL_EQ_DONE|\
1282                          DP_LANE_SYMBOL_LOCKED)
1283 static bool
1284 intel_channel_eq_ok(struct intel_dp *intel_dp)
1285 {
1286         uint8_t lane_align;
1287         uint8_t lane_status;
1288         int lane;
1289
1290         lane_align = intel_dp_link_status(intel_dp->link_status,
1291                                           DP_LANE_ALIGN_STATUS_UPDATED);
1292         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1293                 return false;
1294         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1295                 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1296                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1297                         return false;
1298         }
1299         return true;
1300 }
1301
1302 static bool
1303 intel_dp_set_link_train(struct intel_dp *intel_dp,
1304                         uint32_t dp_reg_value,
1305                         uint8_t dp_train_pat)
1306 {
1307         struct drm_device *dev = intel_dp->base.base.dev;
1308         struct drm_i915_private *dev_priv = dev->dev_private;
1309         int ret;
1310
1311         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1312         POSTING_READ(intel_dp->output_reg);
1313
1314         intel_dp_aux_native_write_1(intel_dp,
1315                                     DP_TRAINING_PATTERN_SET,
1316                                     dp_train_pat);
1317
1318         ret = intel_dp_aux_native_write(intel_dp,
1319                                         DP_TRAINING_LANE0_SET,
1320                                         intel_dp->train_set, 4);
1321         if (ret != 4)
1322                 return false;
1323
1324         return true;
1325 }
1326
1327 /* Enable corresponding port and start training pattern 1 */
1328 static void
1329 intel_dp_start_link_train(struct intel_dp *intel_dp)
1330 {
1331         struct drm_device *dev = intel_dp->base.base.dev;
1332         struct drm_i915_private *dev_priv = dev->dev_private;
1333         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1334         int i;
1335         uint8_t voltage;
1336         bool clock_recovery = false;
1337         int tries;
1338         u32 reg;
1339         uint32_t DP = intel_dp->DP;
1340
1341         /*
1342          * On CPT we have to enable the port in training pattern 1, which
1343          * will happen below in intel_dp_set_link_train.  Otherwise, enable
1344          * the port and wait for it to become active.
1345          */
1346         if (!HAS_PCH_CPT(dev)) {
1347                 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1348                 POSTING_READ(intel_dp->output_reg);
1349                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1350         }
1351
1352         /* Write the link configuration data */
1353         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1354                                   intel_dp->link_configuration,
1355                                   DP_LINK_CONFIGURATION_SIZE);
1356
1357         DP |= DP_PORT_EN;
1358         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1359                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1360         else
1361                 DP &= ~DP_LINK_TRAIN_MASK;
1362         memset(intel_dp->train_set, 0, 4);
1363         voltage = 0xff;
1364         tries = 0;
1365         clock_recovery = false;
1366         for (;;) {
1367                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1368                 uint32_t    signal_levels;
1369                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1370                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1371                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1372                 } else {
1373                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1374                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1375                 }
1376
1377                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1378                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1379                 else
1380                         reg = DP | DP_LINK_TRAIN_PAT_1;
1381
1382                 if (!intel_dp_set_link_train(intel_dp, reg,
1383                                              DP_TRAINING_PATTERN_1 |
1384                                              DP_LINK_SCRAMBLING_DISABLE))
1385                         break;
1386                 /* Set training pattern 1 */
1387
1388                 udelay(100);
1389                 if (!intel_dp_get_link_status(intel_dp))
1390                         break;
1391
1392                 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1393                         clock_recovery = true;
1394                         break;
1395                 }
1396
1397                 /* Check to see if we've tried the max voltage */
1398                 for (i = 0; i < intel_dp->lane_count; i++)
1399                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1400                                 break;
1401                 if (i == intel_dp->lane_count)
1402                         break;
1403
1404                 /* Check to see if we've tried the same voltage 5 times */
1405                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1406                         ++tries;
1407                         if (tries == 5)
1408                                 break;
1409                 } else
1410                         tries = 0;
1411                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1412
1413                 /* Compute new intel_dp->train_set as requested by target */
1414                 intel_get_adjust_train(intel_dp);
1415         }
1416
1417         intel_dp->DP = DP;
1418 }
1419
1420 static void
1421 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1422 {
1423         struct drm_device *dev = intel_dp->base.base.dev;
1424         struct drm_i915_private *dev_priv = dev->dev_private;
1425         bool channel_eq = false;
1426         int tries, cr_tries;
1427         u32 reg;
1428         uint32_t DP = intel_dp->DP;
1429
1430         /* channel equalization */
1431         tries = 0;
1432         cr_tries = 0;
1433         channel_eq = false;
1434         for (;;) {
1435                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1436                 uint32_t    signal_levels;
1437
1438                 if (cr_tries > 5) {
1439                         DRM_ERROR("failed to train DP, aborting\n");
1440                         intel_dp_link_down(intel_dp);
1441                         break;
1442                 }
1443
1444                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1445                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1446                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1447                 } else {
1448                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1449                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1450                 }
1451
1452                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1453                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1454                 else
1455                         reg = DP | DP_LINK_TRAIN_PAT_2;
1456
1457                 /* channel eq pattern */
1458                 if (!intel_dp_set_link_train(intel_dp, reg,
1459                                              DP_TRAINING_PATTERN_2 |
1460                                              DP_LINK_SCRAMBLING_DISABLE))
1461                         break;
1462
1463                 udelay(400);
1464                 if (!intel_dp_get_link_status(intel_dp))
1465                         break;
1466
1467                 /* Make sure clock is still ok */
1468                 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1469                         intel_dp_start_link_train(intel_dp);
1470                         cr_tries++;
1471                         continue;
1472                 }
1473
1474                 if (intel_channel_eq_ok(intel_dp)) {
1475                         channel_eq = true;
1476                         break;
1477                 }
1478
1479                 /* Try 5 times, then try clock recovery if that fails */
1480                 if (tries > 5) {
1481                         intel_dp_link_down(intel_dp);
1482                         intel_dp_start_link_train(intel_dp);
1483                         tries = 0;
1484                         cr_tries++;
1485                         continue;
1486                 }
1487
1488                 /* Compute new intel_dp->train_set as requested by target */
1489                 intel_get_adjust_train(intel_dp);
1490                 ++tries;
1491         }
1492
1493         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1494                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1495         else
1496                 reg = DP | DP_LINK_TRAIN_OFF;
1497
1498         I915_WRITE(intel_dp->output_reg, reg);
1499         POSTING_READ(intel_dp->output_reg);
1500         intel_dp_aux_native_write_1(intel_dp,
1501                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1502 }
1503
1504 static void
1505 intel_dp_link_down(struct intel_dp *intel_dp)
1506 {
1507         struct drm_device *dev = intel_dp->base.base.dev;
1508         struct drm_i915_private *dev_priv = dev->dev_private;
1509         uint32_t DP = intel_dp->DP;
1510
1511         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1512                 return;
1513
1514         DRM_DEBUG_KMS("\n");
1515
1516         if (is_edp(intel_dp)) {
1517                 DP &= ~DP_PLL_ENABLE;
1518                 I915_WRITE(intel_dp->output_reg, DP);
1519                 POSTING_READ(intel_dp->output_reg);
1520                 udelay(100);
1521         }
1522
1523         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1524                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1525                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1526         } else {
1527                 DP &= ~DP_LINK_TRAIN_MASK;
1528                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1529         }
1530         POSTING_READ(intel_dp->output_reg);
1531
1532         msleep(17);
1533
1534         if (is_edp(intel_dp))
1535                 DP |= DP_LINK_TRAIN_OFF;
1536
1537         if (!HAS_PCH_CPT(dev) &&
1538             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1539                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1540
1541                 /* Hardware workaround: leaving our transcoder select
1542                  * set to transcoder B while it's off will prevent the
1543                  * corresponding HDMI output on transcoder A.
1544                  *
1545                  * Combine this with another hardware workaround:
1546                  * transcoder select bit can only be cleared while the
1547                  * port is enabled.
1548                  */
1549                 DP &= ~DP_PIPEB_SELECT;
1550                 I915_WRITE(intel_dp->output_reg, DP);
1551
1552                 /* Changes to enable or select take place the vblank
1553                  * after being written.
1554                  */
1555                 if (crtc == NULL) {
1556                         /* We can arrive here never having been attached
1557                          * to a CRTC, for instance, due to inheriting
1558                          * random state from the BIOS.
1559                          *
1560                          * If the pipe is not running, play safe and
1561                          * wait for the clocks to stabilise before
1562                          * continuing.
1563                          */
1564                         POSTING_READ(intel_dp->output_reg);
1565                         msleep(50);
1566                 } else
1567                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1568         }
1569
1570         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1571         POSTING_READ(intel_dp->output_reg);
1572 }
1573
1574 static bool
1575 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1576 {
1577         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1578                                            sizeof (intel_dp->dpcd)) &&
1579             (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1580                 return true;
1581         }
1582
1583         return false;
1584 }
1585
1586 /*
1587  * According to DP spec
1588  * 5.1.2:
1589  *  1. Read DPCD
1590  *  2. Configure link according to Receiver Capabilities
1591  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1592  *  4. Check link status on receipt of hot-plug interrupt
1593  */
1594
1595 static void
1596 intel_dp_check_link_status(struct intel_dp *intel_dp)
1597 {
1598         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1599                 return;
1600
1601         if (!intel_dp->base.base.crtc)
1602                 return;
1603
1604         /* Try to read receiver status if the link appears to be up */
1605         if (!intel_dp_get_link_status(intel_dp)) {
1606                 intel_dp_link_down(intel_dp);
1607                 return;
1608         }
1609
1610         /* Now read the DPCD to see if it's actually running */
1611         if (!intel_dp_get_dpcd(intel_dp)) {
1612                 intel_dp_link_down(intel_dp);
1613                 return;
1614         }
1615
1616         if (!intel_channel_eq_ok(intel_dp)) {
1617                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1618                               drm_get_encoder_name(&intel_dp->base.base));
1619                 intel_dp_start_link_train(intel_dp);
1620                 intel_dp_complete_link_train(intel_dp);
1621         }
1622 }
1623
1624 static enum drm_connector_status
1625 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
1626 {
1627         if (intel_dp_get_dpcd(intel_dp))
1628                 return connector_status_connected;
1629         return connector_status_disconnected;
1630 }
1631
1632 static enum drm_connector_status
1633 ironlake_dp_detect(struct intel_dp *intel_dp)
1634 {
1635         enum drm_connector_status status;
1636
1637         /* Can't disconnect eDP, but you can close the lid... */
1638         if (is_edp(intel_dp)) {
1639                 status = intel_panel_detect(intel_dp->base.base.dev);
1640                 if (status == connector_status_unknown)
1641                         status = connector_status_connected;
1642                 return status;
1643         }
1644
1645         return intel_dp_detect_dpcd(intel_dp);
1646 }
1647
1648 static enum drm_connector_status
1649 g4x_dp_detect(struct intel_dp *intel_dp)
1650 {
1651         struct drm_device *dev = intel_dp->base.base.dev;
1652         struct drm_i915_private *dev_priv = dev->dev_private;
1653         uint32_t temp, bit;
1654
1655         switch (intel_dp->output_reg) {
1656         case DP_B:
1657                 bit = DPB_HOTPLUG_INT_STATUS;
1658                 break;
1659         case DP_C:
1660                 bit = DPC_HOTPLUG_INT_STATUS;
1661                 break;
1662         case DP_D:
1663                 bit = DPD_HOTPLUG_INT_STATUS;
1664                 break;
1665         default:
1666                 return connector_status_unknown;
1667         }
1668
1669         temp = I915_READ(PORT_HOTPLUG_STAT);
1670
1671         if ((temp & bit) == 0)
1672                 return connector_status_disconnected;
1673
1674         return intel_dp_detect_dpcd(intel_dp);
1675 }
1676
1677 /**
1678  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1679  *
1680  * \return true if DP port is connected.
1681  * \return false if DP port is disconnected.
1682  */
1683 static enum drm_connector_status
1684 intel_dp_detect(struct drm_connector *connector, bool force)
1685 {
1686         struct intel_dp *intel_dp = intel_attached_dp(connector);
1687         struct drm_device *dev = intel_dp->base.base.dev;
1688         enum drm_connector_status status;
1689         struct edid *edid = NULL;
1690
1691         intel_dp->has_audio = false;
1692         memset(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd));
1693
1694         if (HAS_PCH_SPLIT(dev))
1695                 status = ironlake_dp_detect(intel_dp);
1696         else
1697                 status = g4x_dp_detect(intel_dp);
1698
1699         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1700                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
1701                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
1702                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
1703
1704         if (status != connector_status_connected)
1705                 return status;
1706
1707         if (intel_dp->force_audio) {
1708                 intel_dp->has_audio = intel_dp->force_audio > 0;
1709         } else {
1710                 edid = drm_get_edid(connector, &intel_dp->adapter);
1711                 if (edid) {
1712                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
1713                         connector->display_info.raw_edid = NULL;
1714                         kfree(edid);
1715                 }
1716         }
1717
1718         return connector_status_connected;
1719 }
1720
1721 static int intel_dp_get_modes(struct drm_connector *connector)
1722 {
1723         struct intel_dp *intel_dp = intel_attached_dp(connector);
1724         struct drm_device *dev = intel_dp->base.base.dev;
1725         struct drm_i915_private *dev_priv = dev->dev_private;
1726         int ret;
1727
1728         /* We should parse the EDID data and find out if it has an audio sink
1729          */
1730
1731         ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1732         if (ret) {
1733                 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1734                         struct drm_display_mode *newmode;
1735                         list_for_each_entry(newmode, &connector->probed_modes,
1736                                             head) {
1737                                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1738                                         dev_priv->panel_fixed_mode =
1739                                                 drm_mode_duplicate(dev, newmode);
1740                                         break;
1741                                 }
1742                         }
1743                 }
1744
1745                 return ret;
1746         }
1747
1748         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1749         if (is_edp(intel_dp)) {
1750                 if (dev_priv->panel_fixed_mode != NULL) {
1751                         struct drm_display_mode *mode;
1752                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1753                         drm_mode_probed_add(connector, mode);
1754                         return 1;
1755                 }
1756         }
1757         return 0;
1758 }
1759
1760 static bool
1761 intel_dp_detect_audio(struct drm_connector *connector)
1762 {
1763         struct intel_dp *intel_dp = intel_attached_dp(connector);
1764         struct edid *edid;
1765         bool has_audio = false;
1766
1767         edid = drm_get_edid(connector, &intel_dp->adapter);
1768         if (edid) {
1769                 has_audio = drm_detect_monitor_audio(edid);
1770
1771                 connector->display_info.raw_edid = NULL;
1772                 kfree(edid);
1773         }
1774
1775         return has_audio;
1776 }
1777
1778 static int
1779 intel_dp_set_property(struct drm_connector *connector,
1780                       struct drm_property *property,
1781                       uint64_t val)
1782 {
1783         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1784         struct intel_dp *intel_dp = intel_attached_dp(connector);
1785         int ret;
1786
1787         ret = drm_connector_property_set_value(connector, property, val);
1788         if (ret)
1789                 return ret;
1790
1791         if (property == dev_priv->force_audio_property) {
1792                 int i = val;
1793                 bool has_audio;
1794
1795                 if (i == intel_dp->force_audio)
1796                         return 0;
1797
1798                 intel_dp->force_audio = i;
1799
1800                 if (i == 0)
1801                         has_audio = intel_dp_detect_audio(connector);
1802                 else
1803                         has_audio = i > 0;
1804
1805                 if (has_audio == intel_dp->has_audio)
1806                         return 0;
1807
1808                 intel_dp->has_audio = has_audio;
1809                 goto done;
1810         }
1811
1812         if (property == dev_priv->broadcast_rgb_property) {
1813                 if (val == !!intel_dp->color_range)
1814                         return 0;
1815
1816                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1817                 goto done;
1818         }
1819
1820         return -EINVAL;
1821
1822 done:
1823         if (intel_dp->base.base.crtc) {
1824                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1825                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1826                                          crtc->x, crtc->y,
1827                                          crtc->fb);
1828         }
1829
1830         return 0;
1831 }
1832
1833 static void
1834 intel_dp_destroy (struct drm_connector *connector)
1835 {
1836         drm_sysfs_connector_remove(connector);
1837         drm_connector_cleanup(connector);
1838         kfree(connector);
1839 }
1840
1841 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1842 {
1843         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1844
1845         i2c_del_adapter(&intel_dp->adapter);
1846         drm_encoder_cleanup(encoder);
1847         kfree(intel_dp);
1848 }
1849
1850 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1851         .dpms = intel_dp_dpms,
1852         .mode_fixup = intel_dp_mode_fixup,
1853         .prepare = intel_dp_prepare,
1854         .mode_set = intel_dp_mode_set,
1855         .commit = intel_dp_commit,
1856 };
1857
1858 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1859         .dpms = drm_helper_connector_dpms,
1860         .detect = intel_dp_detect,
1861         .fill_modes = drm_helper_probe_single_connector_modes,
1862         .set_property = intel_dp_set_property,
1863         .destroy = intel_dp_destroy,
1864 };
1865
1866 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1867         .get_modes = intel_dp_get_modes,
1868         .mode_valid = intel_dp_mode_valid,
1869         .best_encoder = intel_best_encoder,
1870 };
1871
1872 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1873         .destroy = intel_dp_encoder_destroy,
1874 };
1875
1876 static void
1877 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1878 {
1879         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1880
1881         intel_dp_check_link_status(intel_dp);
1882 }
1883
1884 /* Return which DP Port should be selected for Transcoder DP control */
1885 int
1886 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1887 {
1888         struct drm_device *dev = crtc->dev;
1889         struct drm_mode_config *mode_config = &dev->mode_config;
1890         struct drm_encoder *encoder;
1891
1892         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1893                 struct intel_dp *intel_dp;
1894
1895                 if (encoder->crtc != crtc)
1896                         continue;
1897
1898                 intel_dp = enc_to_intel_dp(encoder);
1899                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1900                         return intel_dp->output_reg;
1901         }
1902
1903         return -1;
1904 }
1905
1906 /* check the VBT to see whether the eDP is on DP-D port */
1907 bool intel_dpd_is_edp(struct drm_device *dev)
1908 {
1909         struct drm_i915_private *dev_priv = dev->dev_private;
1910         struct child_device_config *p_child;
1911         int i;
1912
1913         if (!dev_priv->child_dev_num)
1914                 return false;
1915
1916         for (i = 0; i < dev_priv->child_dev_num; i++) {
1917                 p_child = dev_priv->child_dev + i;
1918
1919                 if (p_child->dvo_port == PORT_IDPD &&
1920                     p_child->device_type == DEVICE_TYPE_eDP)
1921                         return true;
1922         }
1923         return false;
1924 }
1925
1926 static void
1927 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1928 {
1929         intel_attach_force_audio_property(connector);
1930         intel_attach_broadcast_rgb_property(connector);
1931 }
1932
1933 void
1934 intel_dp_init(struct drm_device *dev, int output_reg)
1935 {
1936         struct drm_i915_private *dev_priv = dev->dev_private;
1937         struct drm_connector *connector;
1938         struct intel_dp *intel_dp;
1939         struct intel_encoder *intel_encoder;
1940         struct intel_connector *intel_connector;
1941         const char *name = NULL;
1942         int type;
1943
1944         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1945         if (!intel_dp)
1946                 return;
1947
1948         intel_dp->output_reg = output_reg;
1949         intel_dp->dpms_mode = -1;
1950
1951         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1952         if (!intel_connector) {
1953                 kfree(intel_dp);
1954                 return;
1955         }
1956         intel_encoder = &intel_dp->base;
1957
1958         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1959                 if (intel_dpd_is_edp(dev))
1960                         intel_dp->is_pch_edp = true;
1961
1962         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1963                 type = DRM_MODE_CONNECTOR_eDP;
1964                 intel_encoder->type = INTEL_OUTPUT_EDP;
1965         } else {
1966                 type = DRM_MODE_CONNECTOR_DisplayPort;
1967                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1968         }
1969
1970         connector = &intel_connector->base;
1971         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1972         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1973
1974         connector->polled = DRM_CONNECTOR_POLL_HPD;
1975
1976         if (output_reg == DP_B || output_reg == PCH_DP_B)
1977                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1978         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1979                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1980         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1981                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1982
1983         if (is_edp(intel_dp))
1984                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1985
1986         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1987         connector->interlace_allowed = true;
1988         connector->doublescan_allowed = 0;
1989
1990         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1991                          DRM_MODE_ENCODER_TMDS);
1992         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1993
1994         intel_connector_attach_encoder(intel_connector, intel_encoder);
1995         drm_sysfs_connector_add(connector);
1996
1997         /* Set up the DDC bus. */
1998         switch (output_reg) {
1999                 case DP_A:
2000                         name = "DPDDC-A";
2001                         break;
2002                 case DP_B:
2003                 case PCH_DP_B:
2004                         dev_priv->hotplug_supported_mask |=
2005                                 HDMIB_HOTPLUG_INT_STATUS;
2006                         name = "DPDDC-B";
2007                         break;
2008                 case DP_C:
2009                 case PCH_DP_C:
2010                         dev_priv->hotplug_supported_mask |=
2011                                 HDMIC_HOTPLUG_INT_STATUS;
2012                         name = "DPDDC-C";
2013                         break;
2014                 case DP_D:
2015                 case PCH_DP_D:
2016                         dev_priv->hotplug_supported_mask |=
2017                                 HDMID_HOTPLUG_INT_STATUS;
2018                         name = "DPDDC-D";
2019                         break;
2020         }
2021
2022         intel_dp_i2c_init(intel_dp, intel_connector, name);
2023
2024         /* Cache some DPCD data in the eDP case */
2025         if (is_edp(intel_dp)) {
2026                 bool ret;
2027                 u32 pp_on, pp_div;
2028
2029                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2030                 pp_div = I915_READ(PCH_PP_DIVISOR);
2031
2032                 /* Get T3 & T12 values (note: VESA not bspec terminology) */
2033                 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
2034                 dev_priv->panel_t3 /= 10; /* t3 in 100us units */
2035                 dev_priv->panel_t12 = pp_div & 0xf;
2036                 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
2037
2038                 ironlake_edp_panel_vdd_on(intel_dp);
2039                 ret = intel_dp_get_dpcd(intel_dp);
2040                 ironlake_edp_panel_vdd_off(intel_dp);
2041                 if (ret) {
2042                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2043                                 dev_priv->no_aux_handshake =
2044                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2045                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2046                 } else {
2047                         /* if this fails, presume the device is a ghost */
2048                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2049                         intel_dp_encoder_destroy(&intel_dp->base.base);
2050                         intel_dp_destroy(&intel_connector->base);
2051                         return;
2052                 }
2053         }
2054
2055         intel_encoder->hot_plug = intel_dp_hot_plug;
2056
2057         if (is_edp(intel_dp)) {
2058                 /* initialize panel mode from VBT if available for eDP */
2059                 if (dev_priv->lfp_lvds_vbt_mode) {
2060                         dev_priv->panel_fixed_mode =
2061                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2062                         if (dev_priv->panel_fixed_mode) {
2063                                 dev_priv->panel_fixed_mode->type |=
2064                                         DRM_MODE_TYPE_PREFERRED;
2065                         }
2066                 }
2067         }
2068
2069         intel_dp_add_properties(intel_dp, connector);
2070
2071         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2072          * 0xd.  Failure to do so will result in spurious interrupts being
2073          * generated on the port when a cable is not attached.
2074          */
2075         if (IS_G4X(dev) && !IS_GM45(dev)) {
2076                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2077                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2078         }
2079 }