drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "drm_crtc.h"
  34 #include "drm_crtc_helper.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "drm_dp_helper.h"
  39
  40 #define DP_RECEIVER_CAP_SIZE    0xf
  41 #define DP_LINK_STATUS_SIZE     6
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 #define DP_LINK_CONFIGURATION_SIZE      9
  45
  46 struct intel_dp {
  47         struct intel_encoder base;
  48         uint32_t output_reg;
  49         uint32_t DP;
  50         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  51         bool has_audio;
  52         enum hdmi_force_audio force_audio;
  53         uint32_t color_range;
  54         int dpms_mode;
  55         uint8_t link_bw;
  56         uint8_t lane_count;
  57         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  58         struct i2c_adapter adapter;
  59         struct i2c_algo_dp_aux_data algo;
  60         bool is_pch_edp;
  61         uint8_t train_set[4];
  62         int panel_power_up_delay;
  63         int panel_power_down_delay;
  64         int panel_power_cycle_delay;
  65         int backlight_on_delay;
  66         int backlight_off_delay;
  67         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
  68         struct delayed_work panel_vdd_work;
  69         bool want_panel_vdd;
  70 };
  71
  72 /**
  73  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  74  * @intel_dp: DP struct
  75  *
  76  * If a CPU or PCH DP output is attached to an eDP panel, this function
  77  * will return true, and false otherwise.
  78  */
  79 static bool is_edp(struct intel_dp *intel_dp)
  80 {
  81         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  82 }
  83
  84 /**
  85  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  86  * @intel_dp: DP struct
  87  *
  88  * Returns true if the given DP struct corresponds to a PCH DP port attached
  89  * to an eDP panel, false otherwise.  Helpful for determining whether we
  90  * may need FDI resources for a given DP output or not.
  91  */
  92 static bool is_pch_edp(struct intel_dp *intel_dp)
  93 {
  94         return intel_dp->is_pch_edp;
  95 }
  96
  97 /**
  98  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  99  * @intel_dp: DP struct
 100  *
 101  * Returns true if the given DP struct corresponds to a CPU eDP port.
 102  */
 103 static bool is_cpu_edp(struct intel_dp *intel_dp)
 104 {
 105         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
 106 }
 107
 108 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 109 {
 110         return container_of(encoder, struct intel_dp, base.base);
 111 }
 112
 113 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 114 {
 115         return container_of(intel_attached_encoder(connector),
 116                             struct intel_dp, base);
 117 }
 118
 119 /**
 120  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 121  * @encoder: DRM encoder
 122  *
 123  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 124  * by intel_display.c.
 125  */
 126 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 127 {
 128         struct intel_dp *intel_dp;
 129
 130         if (!encoder)
 131                 return false;
 132
 133         intel_dp = enc_to_intel_dp(encoder);
 134
 135         return is_pch_edp(intel_dp);
 136 }
 137
 138 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 139 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 140 static void intel_dp_link_down(struct intel_dp *intel_dp);
 141
 142 void
 143 intel_edp_link_config(struct intel_encoder *intel_encoder,
 144                        int *lane_num, int *link_bw)
 145 {
 146         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 147
 148         *lane_num = intel_dp->lane_count;
 149         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 150                 *link_bw = 162000;
 151         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 152                 *link_bw = 270000;
 153 }
 154
 155 static int
 156 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 157 {
 158         int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 159         switch (max_lane_count) {
 160         case 1: case 2: case 4:
 161                 break;
 162         default:
 163                 max_lane_count = 4;
 164         }
 165         return max_lane_count;
 166 }
 167
 168 static int
 169 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 170 {
 171         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 172
 173         switch (max_link_bw) {
 174         case DP_LINK_BW_1_62:
 175         case DP_LINK_BW_2_7:
 176                 break;
 177         default:
 178                 max_link_bw = DP_LINK_BW_1_62;
 179                 break;
 180         }
 181         return max_link_bw;
 182 }
 183
 184 static int
 185 intel_dp_link_clock(uint8_t link_bw)
 186 {
 187         if (link_bw == DP_LINK_BW_2_7)
 188                 return 270000;
 189         else
 190                 return 162000;
 191 }
 192
 193 /*
 194  * The units on the numbers in the next two are... bizarre.  Examples will
 195  * make it clearer; this one parallels an example in the eDP spec.
 196  *
 197  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 198  *
 199  *     270000 * 1 * 8 / 10 == 216000
 200  *
 201  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 202  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 203  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 204  * 119000.  At 18bpp that's 2142000 kilobits per second.
 205  *
 206  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 207  * get the result in decakilobits instead of kilobits.
 208  */
 209
 210 static int
 211 intel_dp_link_required(int pixel_clock, int bpp)
 212 {
 213         return (pixel_clock * bpp + 9) / 10;
 214 }
 215
 216 static int
 217 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 218 {
 219         return (max_link_clock * max_lanes * 8) / 10;
 220 }
 221
 222 static bool
 223 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
 224                           struct drm_display_mode *mode,
 225                           struct drm_display_mode *adjusted_mode)
 226 {
 227         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 228         int max_lanes = intel_dp_max_lane_count(intel_dp);
 229         int max_rate, mode_rate;
 230
 231         mode_rate = intel_dp_link_required(mode->clock, 24);
 232         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 233
 234         if (mode_rate > max_rate) {
 235                 mode_rate = intel_dp_link_required(mode->clock, 18);
 236                 if (mode_rate > max_rate)
 237                         return false;
 238
 239                 if (adjusted_mode)
 240                         adjusted_mode->private_flags
 241                                 |= INTEL_MODE_DP_FORCE_6BPC;
 242
 243                 return true;
 244         }
 245
 246         return true;
 247 }
 248
 249 static int
 250 intel_dp_mode_valid(struct drm_connector *connector,
 251                     struct drm_display_mode *mode)
 252 {
 253         struct intel_dp *intel_dp = intel_attached_dp(connector);
 254
 255         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 256                 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 257                         return MODE_PANEL;
 258
 259                 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 260                         return MODE_PANEL;
 261         }
 262
 263         if (!intel_dp_adjust_dithering(intel_dp, mode, NULL))
 264                 return MODE_CLOCK_HIGH;
 265
 266         if (mode->clock < 10000)
 267                 return MODE_CLOCK_LOW;
 268
 269         return MODE_OK;
 270 }
 271
 272 static uint32_t
 273 pack_aux(uint8_t *src, int src_bytes)
 274 {
 275         int     i;
 276         uint32_t v = 0;
 277
 278         if (src_bytes > 4)
 279                 src_bytes = 4;
 280         for (i = 0; i < src_bytes; i++)
 281                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 282         return v;
 283 }
 284
 285 static void
 286 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 287 {
 288         int i;
 289         if (dst_bytes > 4)
 290                 dst_bytes = 4;
 291         for (i = 0; i < dst_bytes; i++)
 292                 dst[i] = src >> ((3-i) * 8);
 293 }
 294
 295 /* hrawclock is 1/4 the FSB frequency */
 296 static int
 297 intel_hrawclk(struct drm_device *dev)
 298 {
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         uint32_t clkcfg;
 301
 302         clkcfg = I915_READ(CLKCFG);
 303         switch (clkcfg & CLKCFG_FSB_MASK) {
 304         case CLKCFG_FSB_400:
 305                 return 100;
 306         case CLKCFG_FSB_533:
 307                 return 133;
 308         case CLKCFG_FSB_667:
 309                 return 166;
 310         case CLKCFG_FSB_800:
 311                 return 200;
 312         case CLKCFG_FSB_1067:
 313                 return 266;
 314         case CLKCFG_FSB_1333:
 315                 return 333;
 316         /* these two are just a guess; one of them might be right */
 317         case CLKCFG_FSB_1600:
 318         case CLKCFG_FSB_1600_ALT:
 319                 return 400;
 320         default:
 321                 return 133;
 322         }
 323 }
 324
 325 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 326 {
 327         struct drm_device *dev = intel_dp->base.base.dev;
 328         struct drm_i915_private *dev_priv = dev->dev_private;
 329
 330         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 331 }
 332
 333 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 334 {
 335         struct drm_device *dev = intel_dp->base.base.dev;
 336         struct drm_i915_private *dev_priv = dev->dev_private;
 337
 338         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 339 }
 340
 341 static void
 342 intel_dp_check_edp(struct intel_dp *intel_dp)
 343 {
 344         struct drm_device *dev = intel_dp->base.base.dev;
 345         struct drm_i915_private *dev_priv = dev->dev_private;
 346
 347         if (!is_edp(intel_dp))
 348                 return;
 349         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 350                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 351                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 352                               I915_READ(PCH_PP_STATUS),
 353                               I915_READ(PCH_PP_CONTROL));
 354         }
 355 }
 356
 357 static int
 358 intel_dp_aux_ch(struct intel_dp *intel_dp,
 359                 uint8_t *send, int send_bytes,
 360                 uint8_t *recv, int recv_size)
 361 {
 362         uint32_t output_reg = intel_dp->output_reg;
 363         struct drm_device *dev = intel_dp->base.base.dev;
 364         struct drm_i915_private *dev_priv = dev->dev_private;
 365         uint32_t ch_ctl = output_reg + 0x10;
 366         uint32_t ch_data = ch_ctl + 4;
 367         int i;
 368         int recv_bytes;
 369         uint32_t status;
 370         uint32_t aux_clock_divider;
 371         int try, precharge = 5;
 372
 373         intel_dp_check_edp(intel_dp);
 374         /* The clock divider is based off the hrawclk,
 375          * and would like to run at 2MHz. So, take the
 376          * hrawclk value and divide by 2 and use that
 377          *
 378          * Note that PCH attached eDP panels should use a 125MHz input
 379          * clock divider.
 380          */
 381         if (is_cpu_edp(intel_dp)) {
 382                 if (IS_GEN6(dev) || IS_GEN7(dev))
 383                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 384                 else
 385                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 386         } else if (HAS_PCH_SPLIT(dev))
 387                 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
 388         else
 389                 aux_clock_divider = intel_hrawclk(dev) / 2;
 390
 391         /* Try to wait for any previous AUX channel activity */
 392         for (try = 0; try < 3; try++) {
 393                 status = I915_READ(ch_ctl);
 394                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 395                         break;
 396                 msleep(1);
 397         }
 398
 399         if (try == 3) {
 400                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 401                      I915_READ(ch_ctl));
 402                 return -EBUSY;
 403         }
 404
 405         /* Must try at least 3 times according to DP spec */
 406         for (try = 0; try < 5; try++) {
 407                 /* Load the send data into the aux channel data registers */
 408                 for (i = 0; i < send_bytes; i += 4)
 409                         I915_WRITE(ch_data + i,
 410                                    pack_aux(send + i, send_bytes - i));
 411
 412                 /* Send the command and wait for it to complete */
 413                 I915_WRITE(ch_ctl,
 414                            DP_AUX_CH_CTL_SEND_BUSY |
 415                            DP_AUX_CH_CTL_TIME_OUT_400us |
 416                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 417                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 418                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 419                            DP_AUX_CH_CTL_DONE |
 420                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 421                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 422                 for (;;) {
 423                         status = I915_READ(ch_ctl);
 424                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 425                                 break;
 426                         udelay(100);
 427                 }
 428
 429                 /* Clear done status and any errors */
 430                 I915_WRITE(ch_ctl,
 431                            status |
 432                            DP_AUX_CH_CTL_DONE |
 433                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 434                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 435
 436                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 437                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 438                         continue;
 439                 if (status & DP_AUX_CH_CTL_DONE)
 440                         break;
 441         }
 442
 443         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 444                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 445                 return -EBUSY;
 446         }
 447
 448         /* Check for timeout or receive error.
 449          * Timeouts occur when the sink is not connected
 450          */
 451         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 452                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 453                 return -EIO;
 454         }
 455
 456         /* Timeouts occur when the device isn't connected, so they're
 457          * "normal" -- don't fill the kernel log with these */
 458         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 459                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 460                 return -ETIMEDOUT;
 461         }
 462
 463         /* Unload any bytes sent back from the other side */
 464         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 465                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 466         if (recv_bytes > recv_size)
 467                 recv_bytes = recv_size;
 468
 469         for (i = 0; i < recv_bytes; i += 4)
 470                 unpack_aux(I915_READ(ch_data + i),
 471                            recv + i, recv_bytes - i);
 472
 473         return recv_bytes;
 474 }
 475
 476 /* Write data to the aux channel in native mode */
 477 static int
 478 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 479                           uint16_t address, uint8_t *send, int send_bytes)
 480 {
 481         int ret;
 482         uint8_t msg[20];
 483         int msg_bytes;
 484         uint8_t ack;
 485
 486         intel_dp_check_edp(intel_dp);
 487         if (send_bytes > 16)
 488                 return -1;
 489         msg[0] = AUX_NATIVE_WRITE << 4;
 490         msg[1] = address >> 8;
 491         msg[2] = address & 0xff;
 492         msg[3] = send_bytes - 1;
 493         memcpy(&msg[4], send, send_bytes);
 494         msg_bytes = send_bytes + 4;
 495         for (;;) {
 496                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 497                 if (ret < 0)
 498                         return ret;
 499                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 500                         break;
 501                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 502                         udelay(100);
 503                 else
 504                         return -EIO;
 505         }
 506         return send_bytes;
 507 }
 508
 509 /* Write a single byte to the aux channel in native mode */
 510 static int
 511 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 512                             uint16_t address, uint8_t byte)
 513 {
 514         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 515 }
 516
 517 /* read bytes from a native aux channel */
 518 static int
 519 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 520                          uint16_t address, uint8_t *recv, int recv_bytes)
 521 {
 522         uint8_t msg[4];
 523         int msg_bytes;
 524         uint8_t reply[20];
 525         int reply_bytes;
 526         uint8_t ack;
 527         int ret;
 528
 529         intel_dp_check_edp(intel_dp);
 530         msg[0] = AUX_NATIVE_READ << 4;
 531         msg[1] = address >> 8;
 532         msg[2] = address & 0xff;
 533         msg[3] = recv_bytes - 1;
 534
 535         msg_bytes = 4;
 536         reply_bytes = recv_bytes + 1;
 537
 538         for (;;) {
 539                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 540                                       reply, reply_bytes);
 541                 if (ret == 0)
 542                         return -EPROTO;
 543                 if (ret < 0)
 544                         return ret;
 545                 ack = reply[0];
 546                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 547                         memcpy(recv, reply + 1, ret - 1);
 548                         return ret - 1;
 549                 }
 550                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 551                         udelay(100);
 552                 else
 553                         return -EIO;
 554         }
 555 }
 556
 557 static int
 558 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 559                     uint8_t write_byte, uint8_t *read_byte)
 560 {
 561         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 562         struct intel_dp *intel_dp = container_of(adapter,
 563                                                 struct intel_dp,
 564                                                 adapter);
 565         uint16_t address = algo_data->address;
 566         uint8_t msg[5];
 567         uint8_t reply[2];
 568         unsigned retry;
 569         int msg_bytes;
 570         int reply_bytes;
 571         int ret;
 572
 573         intel_dp_check_edp(intel_dp);
 574         /* Set up the command byte */
 575         if (mode & MODE_I2C_READ)
 576                 msg[0] = AUX_I2C_READ << 4;
 577         else
 578                 msg[0] = AUX_I2C_WRITE << 4;
 579
 580         if (!(mode & MODE_I2C_STOP))
 581                 msg[0] |= AUX_I2C_MOT << 4;
 582
 583         msg[1] = address >> 8;
 584         msg[2] = address;
 585
 586         switch (mode) {
 587         case MODE_I2C_WRITE:
 588                 msg[3] = 0;
 589                 msg[4] = write_byte;
 590                 msg_bytes = 5;
 591                 reply_bytes = 1;
 592                 break;
 593         case MODE_I2C_READ:
 594                 msg[3] = 0;
 595                 msg_bytes = 4;
 596                 reply_bytes = 2;
 597                 break;
 598         default:
 599                 msg_bytes = 3;
 600                 reply_bytes = 1;
 601                 break;
 602         }
 603
 604         for (retry = 0; retry < 5; retry++) {
 605                 ret = intel_dp_aux_ch(intel_dp,
 606                                       msg, msg_bytes,
 607                                       reply, reply_bytes);
 608                 if (ret < 0) {
 609                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 610                         return ret;
 611                 }
 612
 613                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 614                 case AUX_NATIVE_REPLY_ACK:
 615                         /* I2C-over-AUX Reply field is only valid
 616                          * when paired with AUX ACK.
 617                          */
 618                         break;
 619                 case AUX_NATIVE_REPLY_NACK:
 620                         DRM_DEBUG_KMS("aux_ch native nack\n");
 621                         return -EREMOTEIO;
 622                 case AUX_NATIVE_REPLY_DEFER:
 623                         udelay(100);
 624                         continue;
 625                 default:
 626                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 627                                   reply[0]);
 628                         return -EREMOTEIO;
 629                 }
 630
 631                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 632                 case AUX_I2C_REPLY_ACK:
 633                         if (mode == MODE_I2C_READ) {
 634                                 *read_byte = reply[1];
 635                         }
 636                         return reply_bytes - 1;
 637                 case AUX_I2C_REPLY_NACK:
 638                         DRM_DEBUG_KMS("aux_i2c nack\n");
 639                         return -EREMOTEIO;
 640                 case AUX_I2C_REPLY_DEFER:
 641                         DRM_DEBUG_KMS("aux_i2c defer\n");
 642                         udelay(100);
 643                         break;
 644                 default:
 645                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 646                         return -EREMOTEIO;
 647                 }
 648         }
 649
 650         DRM_ERROR("too many retries, giving up\n");
 651         return -EREMOTEIO;
 652 }
 653
 654 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 655 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 656
 657 static int
 658 intel_dp_i2c_init(struct intel_dp *intel_dp,
 659                   struct intel_connector *intel_connector, const char *name)
 660 {
 661         int     ret;
 662
 663         DRM_DEBUG_KMS("i2c_init %s\n", name);
 664         intel_dp->algo.running = false;
 665         intel_dp->algo.address = 0;
 666         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 667
 668         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 669         intel_dp->adapter.owner = THIS_MODULE;
 670         intel_dp->adapter.class = I2C_CLASS_DDC;
 671         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 672         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 673         intel_dp->adapter.algo_data = &intel_dp->algo;
 674         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 675
 676         ironlake_edp_panel_vdd_on(intel_dp);
 677         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 678         ironlake_edp_panel_vdd_off(intel_dp, false);
 679         return ret;
 680 }
 681
 682 static bool
 683 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 684                     struct drm_display_mode *adjusted_mode)
 685 {
 686         struct drm_device *dev = encoder->dev;
 687         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 688         int lane_count, clock;
 689         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 690         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 691         int bpp;
 692         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 693
 694         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 695                 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 696                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 697                                         mode, adjusted_mode);
 698                 /*
 699                  * the mode->clock is used to calculate the Data&Link M/N
 700                  * of the pipe. For the eDP the fixed clock should be used.
 701                  */
 702                 mode->clock = intel_dp->panel_fixed_mode->clock;
 703         }
 704
 705         if (!intel_dp_adjust_dithering(intel_dp, mode, adjusted_mode))
 706                 return false;
 707
 708         bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
 709
 710         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 711                 for (clock = 0; clock <= max_clock; clock++) {
 712                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 713
 714                         if (intel_dp_link_required(mode->clock, bpp)
 715                                         <= link_avail) {
 716                                 intel_dp->link_bw = bws[clock];
 717                                 intel_dp->lane_count = lane_count;
 718                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 719                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 720                                                 "count %d clock %d\n",
 721                                        intel_dp->link_bw, intel_dp->lane_count,
 722                                        adjusted_mode->clock);
 723                                 return true;
 724                         }
 725                 }
 726         }
 727
 728         return false;
 729 }
 730
 731 struct intel_dp_m_n {
 732         uint32_t        tu;
 733         uint32_t        gmch_m;
 734         uint32_t        gmch_n;
 735         uint32_t        link_m;
 736         uint32_t        link_n;
 737 };
 738
 739 static void
 740 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 741 {
 742         while (*num > 0xffffff || *den > 0xffffff) {
 743                 *num >>= 1;
 744                 *den >>= 1;
 745         }
 746 }
 747
 748 static void
 749 intel_dp_compute_m_n(int bpp,
 750                      int nlanes,
 751                      int pixel_clock,
 752                      int link_clock,
 753                      struct intel_dp_m_n *m_n)
 754 {
 755         m_n->tu = 64;
 756         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 757         m_n->gmch_n = link_clock * nlanes;
 758         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 759         m_n->link_m = pixel_clock;
 760         m_n->link_n = link_clock;
 761         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 762 }
 763
 764 void
 765 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 766                  struct drm_display_mode *adjusted_mode)
 767 {
 768         struct drm_device *dev = crtc->dev;
 769         struct drm_mode_config *mode_config = &dev->mode_config;
 770         struct drm_encoder *encoder;
 771         struct drm_i915_private *dev_priv = dev->dev_private;
 772         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 773         int lane_count = 4;
 774         struct intel_dp_m_n m_n;
 775         int pipe = intel_crtc->pipe;
 776
 777         /*
 778          * Find the lane count in the intel_encoder private
 779          */
 780         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 781                 struct intel_dp *intel_dp;
 782
 783                 if (encoder->crtc != crtc)
 784                         continue;
 785
 786                 intel_dp = enc_to_intel_dp(encoder);
 787                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
 788                     intel_dp->base.type == INTEL_OUTPUT_EDP)
 789                 {
 790                         lane_count = intel_dp->lane_count;
 791                         break;
 792                 }
 793         }
 794
 795         /*
 796          * Compute the GMCH and Link ratios. The '3' here is
 797          * the number of bytes_per_pixel post-LUT, which we always
 798          * set up for 8-bits of R/G/B, or 3 bytes total.
 799          */
 800         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 801                              mode->clock, adjusted_mode->clock, &m_n);
 802
 803         if (HAS_PCH_SPLIT(dev)) {
 804                 I915_WRITE(TRANSDATA_M1(pipe),
 805                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 806                            m_n.gmch_m);
 807                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 808                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 809                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 810         } else {
 811                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 812                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 813                            m_n.gmch_m);
 814                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 815                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 816                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 817         }
 818 }
 819
 820 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
 821 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
 822
 823 static void
 824 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 825                   struct drm_display_mode *adjusted_mode)
 826 {
 827         struct drm_device *dev = encoder->dev;
 828         struct drm_i915_private *dev_priv = dev->dev_private;
 829         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 830         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 832
 833         /* Turn on the eDP PLL if needed */
 834         if (is_edp(intel_dp)) {
 835                 if (!is_pch_edp(intel_dp))
 836                         ironlake_edp_pll_on(encoder);
 837                 else
 838                         ironlake_edp_pll_off(encoder);
 839         }
 840
 841         /*
 842          * There are four kinds of DP registers:
 843          *
 844          *      IBX PCH
 845          *      SNB CPU
 846          *      IVB CPU
 847          *      CPT PCH
 848          *
 849          * IBX PCH and CPU are the same for almost everything,
 850          * except that the CPU DP PLL is configured in this
 851          * register
 852          *
 853          * CPT PCH is quite different, having many bits moved
 854          * to the TRANS_DP_CTL register instead. That
 855          * configuration happens (oddly) in ironlake_pch_enable
 856          */
 857
 858         /* Preserve the BIOS-computed detected bit. This is
 859          * supposed to be read-only.
 860          */
 861         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 862         intel_dp->DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 863
 864         /* Handle DP bits in common between all three register formats */
 865
 866         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 867
 868         switch (intel_dp->lane_count) {
 869         case 1:
 870                 intel_dp->DP |= DP_PORT_WIDTH_1;
 871                 break;
 872         case 2:
 873                 intel_dp->DP |= DP_PORT_WIDTH_2;
 874                 break;
 875         case 4:
 876                 intel_dp->DP |= DP_PORT_WIDTH_4;
 877                 break;
 878         }
 879         if (intel_dp->has_audio) {
 880                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 881                                  pipe_name(intel_crtc->pipe));
 882                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 883                 intel_write_eld(encoder, adjusted_mode);
 884         }
 885         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 886         intel_dp->link_configuration[0] = intel_dp->link_bw;
 887         intel_dp->link_configuration[1] = intel_dp->lane_count;
 888         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 889         /*
 890          * Check for DPCD version > 1.1 and enhanced framing support
 891          */
 892         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 893             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 894                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 895         }
 896
 897         /* Split out the IBX/CPU vs CPT settings */
 898
 899         if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
 900                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 901                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 902                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 903                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 904                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 905
 906                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 907                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 908
 909                 intel_dp->DP |= intel_crtc->pipe << 29;
 910
 911                 /* don't miss out required setting for eDP */
 912                 intel_dp->DP |= DP_PLL_ENABLE;
 913                 if (adjusted_mode->clock < 200000)
 914                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 915                 else
 916                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 917         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 918                 intel_dp->DP |= intel_dp->color_range;
 919
 920                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 921                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 922                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 923                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 924                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 925
 926                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 927                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 928
 929                 if (intel_crtc->pipe == 1)
 930                         intel_dp->DP |= DP_PIPEB_SELECT;
 931
 932                 if (is_cpu_edp(intel_dp)) {
 933                         /* don't miss out required setting for eDP */
 934                         intel_dp->DP |= DP_PLL_ENABLE;
 935                         if (adjusted_mode->clock < 200000)
 936                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 937                         else
 938                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 939                 }
 940         } else {
 941                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 942         }
 943 }
 944
 945 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 946 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 947
 948 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 949 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 950
 951 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 952 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 953
 954 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 955                                        u32 mask,
 956                                        u32 value)
 957 {
 958         struct drm_device *dev = intel_dp->base.base.dev;
 959         struct drm_i915_private *dev_priv = dev->dev_private;
 960
 961         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 962                       mask, value,
 963                       I915_READ(PCH_PP_STATUS),
 964                       I915_READ(PCH_PP_CONTROL));
 965
 966         if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
 967                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 968                           I915_READ(PCH_PP_STATUS),
 969                           I915_READ(PCH_PP_CONTROL));
 970         }
 971 }
 972
 973 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 974 {
 975         DRM_DEBUG_KMS("Wait for panel power on\n");
 976         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 977 }
 978
 979 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 980 {
 981         DRM_DEBUG_KMS("Wait for panel power off time\n");
 982         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 983 }
 984
 985 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 986 {
 987         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 988         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 989 }
 990
 991
 992 /* Read the current pp_control value, unlocking the register if it
 993  * is locked
 994  */
 995
 996 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
 997 {
 998         u32     control = I915_READ(PCH_PP_CONTROL);
 999
1000         control &= ~PANEL_UNLOCK_MASK;
1001         control |= PANEL_UNLOCK_REGS;
1002         return control;
1003 }
1004
1005 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1006 {
1007         struct drm_device *dev = intel_dp->base.base.dev;
1008         struct drm_i915_private *dev_priv = dev->dev_private;
1009         u32 pp;
1010
1011         if (!is_edp(intel_dp))
1012                 return;
1013         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1014
1015         WARN(intel_dp->want_panel_vdd,
1016              "eDP VDD already requested on\n");
1017
1018         intel_dp->want_panel_vdd = true;
1019
1020         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1021                 DRM_DEBUG_KMS("eDP VDD already on\n");
1022                 return;
1023         }
1024
1025         if (!ironlake_edp_have_panel_power(intel_dp))
1026                 ironlake_wait_panel_power_cycle(intel_dp);
1027
1028         pp = ironlake_get_pp_control(dev_priv);
1029         pp |= EDP_FORCE_VDD;
1030         I915_WRITE(PCH_PP_CONTROL, pp);
1031         POSTING_READ(PCH_PP_CONTROL);
1032         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1033                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1034
1035         /*
1036          * If the panel wasn't on, delay before accessing aux channel
1037          */
1038         if (!ironlake_edp_have_panel_power(intel_dp)) {
1039                 DRM_DEBUG_KMS("eDP was not running\n");
1040                 msleep(intel_dp->panel_power_up_delay);
1041         }
1042 }
1043
1044 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1045 {
1046         struct drm_device *dev = intel_dp->base.base.dev;
1047         struct drm_i915_private *dev_priv = dev->dev_private;
1048         u32 pp;
1049
1050         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1051                 pp = ironlake_get_pp_control(dev_priv);
1052                 pp &= ~EDP_FORCE_VDD;
1053                 I915_WRITE(PCH_PP_CONTROL, pp);
1054                 POSTING_READ(PCH_PP_CONTROL);
1055
1056                 /* Make sure sequencer is idle before allowing subsequent activity */
1057                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1058                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1059
1060                 msleep(intel_dp->panel_power_down_delay);
1061         }
1062 }
1063
1064 static void ironlake_panel_vdd_work(struct work_struct *__work)
1065 {
1066         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1067                                                  struct intel_dp, panel_vdd_work);
1068         struct drm_device *dev = intel_dp->base.base.dev;
1069
1070         mutex_lock(&dev->mode_config.mutex);
1071         ironlake_panel_vdd_off_sync(intel_dp);
1072         mutex_unlock(&dev->mode_config.mutex);
1073 }
1074
1075 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1076 {
1077         if (!is_edp(intel_dp))
1078                 return;
1079
1080         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1081         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1082
1083         intel_dp->want_panel_vdd = false;
1084
1085         if (sync) {
1086                 ironlake_panel_vdd_off_sync(intel_dp);
1087         } else {
1088                 /*
1089                  * Queue the timer to fire a long
1090                  * time from now (relative to the power down delay)
1091                  * to keep the panel power up across a sequence of operations
1092                  */
1093                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1094                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1095         }
1096 }
1097
1098 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1099 {
1100         struct drm_device *dev = intel_dp->base.base.dev;
1101         struct drm_i915_private *dev_priv = dev->dev_private;
1102         u32 pp;
1103
1104         if (!is_edp(intel_dp))
1105                 return;
1106
1107         DRM_DEBUG_KMS("Turn eDP power on\n");
1108
1109         if (ironlake_edp_have_panel_power(intel_dp)) {
1110                 DRM_DEBUG_KMS("eDP power already on\n");
1111                 return;
1112         }
1113
1114         ironlake_wait_panel_power_cycle(intel_dp);
1115
1116         pp = ironlake_get_pp_control(dev_priv);
1117         if (IS_GEN5(dev)) {
1118                 /* ILK workaround: disable reset around power sequence */
1119                 pp &= ~PANEL_POWER_RESET;
1120                 I915_WRITE(PCH_PP_CONTROL, pp);
1121                 POSTING_READ(PCH_PP_CONTROL);
1122         }
1123
1124         pp |= POWER_TARGET_ON;
1125         if (!IS_GEN5(dev))
1126                 pp |= PANEL_POWER_RESET;
1127
1128         I915_WRITE(PCH_PP_CONTROL, pp);
1129         POSTING_READ(PCH_PP_CONTROL);
1130
1131         ironlake_wait_panel_on(intel_dp);
1132
1133         if (IS_GEN5(dev)) {
1134                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1135                 I915_WRITE(PCH_PP_CONTROL, pp);
1136                 POSTING_READ(PCH_PP_CONTROL);
1137         }
1138 }
1139
1140 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1141 {
1142         struct drm_device *dev = intel_dp->base.base.dev;
1143         struct drm_i915_private *dev_priv = dev->dev_private;
1144         u32 pp;
1145
1146         if (!is_edp(intel_dp))
1147                 return;
1148
1149         DRM_DEBUG_KMS("Turn eDP power off\n");
1150
1151         WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
1152
1153         pp = ironlake_get_pp_control(dev_priv);
1154         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1155         I915_WRITE(PCH_PP_CONTROL, pp);
1156         POSTING_READ(PCH_PP_CONTROL);
1157
1158         ironlake_wait_panel_off(intel_dp);
1159 }
1160
1161 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1162 {
1163         struct drm_device *dev = intel_dp->base.base.dev;
1164         struct drm_i915_private *dev_priv = dev->dev_private;
1165         u32 pp;
1166
1167         if (!is_edp(intel_dp))
1168                 return;
1169
1170         DRM_DEBUG_KMS("\n");
1171         /*
1172          * If we enable the backlight right away following a panel power
1173          * on, we may see slight flicker as the panel syncs with the eDP
1174          * link.  So delay a bit to make sure the image is solid before
1175          * allowing it to appear.
1176          */
1177         msleep(intel_dp->backlight_on_delay);
1178         pp = ironlake_get_pp_control(dev_priv);
1179         pp |= EDP_BLC_ENABLE;
1180         I915_WRITE(PCH_PP_CONTROL, pp);
1181         POSTING_READ(PCH_PP_CONTROL);
1182 }
1183
1184 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1185 {
1186         struct drm_device *dev = intel_dp->base.base.dev;
1187         struct drm_i915_private *dev_priv = dev->dev_private;
1188         u32 pp;
1189
1190         if (!is_edp(intel_dp))
1191                 return;
1192
1193         DRM_DEBUG_KMS("\n");
1194         pp = ironlake_get_pp_control(dev_priv);
1195         pp &= ~EDP_BLC_ENABLE;
1196         I915_WRITE(PCH_PP_CONTROL, pp);
1197         POSTING_READ(PCH_PP_CONTROL);
1198         msleep(intel_dp->backlight_off_delay);
1199 }
1200
1201 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1202 {
1203         struct drm_device *dev = encoder->dev;
1204         struct drm_i915_private *dev_priv = dev->dev_private;
1205         u32 dpa_ctl;
1206
1207         DRM_DEBUG_KMS("\n");
1208         dpa_ctl = I915_READ(DP_A);
1209         dpa_ctl |= DP_PLL_ENABLE;
1210         I915_WRITE(DP_A, dpa_ctl);
1211         POSTING_READ(DP_A);
1212         udelay(200);
1213 }
1214
1215 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1216 {
1217         struct drm_device *dev = encoder->dev;
1218         struct drm_i915_private *dev_priv = dev->dev_private;
1219         u32 dpa_ctl;
1220
1221         dpa_ctl = I915_READ(DP_A);
1222         dpa_ctl &= ~DP_PLL_ENABLE;
1223         I915_WRITE(DP_A, dpa_ctl);
1224         POSTING_READ(DP_A);
1225         udelay(200);
1226 }
1227
1228 /* If the sink supports it, try to set the power state appropriately */
1229 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1230 {
1231         int ret, i;
1232
1233         /* Should have a valid DPCD by this point */
1234         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1235                 return;
1236
1237         if (mode != DRM_MODE_DPMS_ON) {
1238                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1239                                                   DP_SET_POWER_D3);
1240                 if (ret != 1)
1241                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1242         } else {
1243                 /*
1244                  * When turning on, we need to retry for 1ms to give the sink
1245                  * time to wake up.
1246                  */
1247                 for (i = 0; i < 3; i++) {
1248                         ret = intel_dp_aux_native_write_1(intel_dp,
1249                                                           DP_SET_POWER,
1250                                                           DP_SET_POWER_D0);
1251                         if (ret == 1)
1252                                 break;
1253                         msleep(1);
1254                 }
1255         }
1256 }
1257
1258 static void intel_dp_prepare(struct drm_encoder *encoder)
1259 {
1260         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1261
1262         ironlake_edp_backlight_off(intel_dp);
1263         ironlake_edp_panel_off(intel_dp);
1264
1265         /* Wake up the sink first */
1266         ironlake_edp_panel_vdd_on(intel_dp);
1267         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1268         intel_dp_link_down(intel_dp);
1269         ironlake_edp_panel_vdd_off(intel_dp, false);
1270
1271         /* Make sure the panel is off before trying to
1272          * change the mode
1273          */
1274 }
1275
1276 static void intel_dp_commit(struct drm_encoder *encoder)
1277 {
1278         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1279         struct drm_device *dev = encoder->dev;
1280         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1281
1282         ironlake_edp_panel_vdd_on(intel_dp);
1283         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1284         intel_dp_start_link_train(intel_dp);
1285         ironlake_edp_panel_on(intel_dp);
1286         ironlake_edp_panel_vdd_off(intel_dp, true);
1287         intel_dp_complete_link_train(intel_dp);
1288         ironlake_edp_backlight_on(intel_dp);
1289
1290         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1291
1292         if (HAS_PCH_CPT(dev))
1293                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1294 }
1295
1296 static void
1297 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1298 {
1299         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1300         struct drm_device *dev = encoder->dev;
1301         struct drm_i915_private *dev_priv = dev->dev_private;
1302         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1303
1304         if (mode != DRM_MODE_DPMS_ON) {
1305                 ironlake_edp_backlight_off(intel_dp);
1306                 ironlake_edp_panel_off(intel_dp);
1307
1308                 ironlake_edp_panel_vdd_on(intel_dp);
1309                 intel_dp_sink_dpms(intel_dp, mode);
1310                 intel_dp_link_down(intel_dp);
1311                 ironlake_edp_panel_vdd_off(intel_dp, false);
1312
1313                 if (is_cpu_edp(intel_dp))
1314                         ironlake_edp_pll_off(encoder);
1315         } else {
1316                 if (is_cpu_edp(intel_dp))
1317                         ironlake_edp_pll_on(encoder);
1318
1319                 ironlake_edp_panel_vdd_on(intel_dp);
1320                 intel_dp_sink_dpms(intel_dp, mode);
1321                 if (!(dp_reg & DP_PORT_EN)) {
1322                         intel_dp_start_link_train(intel_dp);
1323                         ironlake_edp_panel_on(intel_dp);
1324                         ironlake_edp_panel_vdd_off(intel_dp, true);
1325                         intel_dp_complete_link_train(intel_dp);
1326                 } else
1327                         ironlake_edp_panel_vdd_off(intel_dp, false);
1328                 ironlake_edp_backlight_on(intel_dp);
1329         }
1330         intel_dp->dpms_mode = mode;
1331 }
1332
1333 /*
1334  * Native read with retry for link status and receiver capability reads for
1335  * cases where the sink may still be asleep.
1336  */
1337 static bool
1338 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1339                                uint8_t *recv, int recv_bytes)
1340 {
1341         int ret, i;
1342
1343         /*
1344          * Sinks are *supposed* to come up within 1ms from an off state,
1345          * but we're also supposed to retry 3 times per the spec.
1346          */
1347         for (i = 0; i < 3; i++) {
1348                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1349                                                recv_bytes);
1350                 if (ret == recv_bytes)
1351                         return true;
1352                 msleep(1);
1353         }
1354
1355         return false;
1356 }
1357
1358 /*
1359  * Fetch AUX CH registers 0x202 - 0x207 which contain
1360  * link status information
1361  */
1362 static bool
1363 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1364 {
1365         return intel_dp_aux_native_read_retry(intel_dp,
1366                                               DP_LANE0_1_STATUS,
1367                                               link_status,
1368                                               DP_LINK_STATUS_SIZE);
1369 }
1370
1371 static uint8_t
1372 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1373                      int r)
1374 {
1375         return link_status[r - DP_LANE0_1_STATUS];
1376 }
1377
1378 static uint8_t
1379 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1380                                  int lane)
1381 {
1382         int         s = ((lane & 1) ?
1383                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1384                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1385         uint8_t l = adjust_request[lane>>1];
1386
1387         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1388 }
1389
1390 static uint8_t
1391 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1392                                       int lane)
1393 {
1394         int         s = ((lane & 1) ?
1395                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1396                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1397         uint8_t l = adjust_request[lane>>1];
1398
1399         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1400 }
1401
1402
1403 #if 0
1404 static char     *voltage_names[] = {
1405         "0.4V", "0.6V", "0.8V", "1.2V"
1406 };
1407 static char     *pre_emph_names[] = {
1408         "0dB", "3.5dB", "6dB", "9.5dB"
1409 };
1410 static char     *link_train_names[] = {
1411         "pattern 1", "pattern 2", "idle", "off"
1412 };
1413 #endif
1414
1415 /*
1416  * These are source-specific values; current Intel hardware supports
1417  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1418  */
1419
1420 static uint8_t
1421 intel_dp_voltage_max(struct intel_dp *intel_dp)
1422 {
1423         struct drm_device *dev = intel_dp->base.base.dev;
1424
1425         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1426                 return DP_TRAIN_VOLTAGE_SWING_800;
1427         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1428                 return DP_TRAIN_VOLTAGE_SWING_1200;
1429         else
1430                 return DP_TRAIN_VOLTAGE_SWING_800;
1431 }
1432
1433 static uint8_t
1434 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1435 {
1436         struct drm_device *dev = intel_dp->base.base.dev;
1437
1438         if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1439                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1440                 case DP_TRAIN_VOLTAGE_SWING_400:
1441                         return DP_TRAIN_PRE_EMPHASIS_6;
1442                 case DP_TRAIN_VOLTAGE_SWING_600:
1443                 case DP_TRAIN_VOLTAGE_SWING_800:
1444                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1445                 default:
1446                         return DP_TRAIN_PRE_EMPHASIS_0;
1447                 }
1448         } else {
1449                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1450                 case DP_TRAIN_VOLTAGE_SWING_400:
1451                         return DP_TRAIN_PRE_EMPHASIS_6;
1452                 case DP_TRAIN_VOLTAGE_SWING_600:
1453                         return DP_TRAIN_PRE_EMPHASIS_6;
1454                 case DP_TRAIN_VOLTAGE_SWING_800:
1455                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1456                 case DP_TRAIN_VOLTAGE_SWING_1200:
1457                 default:
1458                         return DP_TRAIN_PRE_EMPHASIS_0;
1459                 }
1460         }
1461 }
1462
1463 static void
1464 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1465 {
1466         uint8_t v = 0;
1467         uint8_t p = 0;
1468         int lane;
1469         uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1470         uint8_t voltage_max;
1471         uint8_t preemph_max;
1472
1473         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1474                 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1475                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1476
1477                 if (this_v > v)
1478                         v = this_v;
1479                 if (this_p > p)
1480                         p = this_p;
1481         }
1482
1483         voltage_max = intel_dp_voltage_max(intel_dp);
1484         if (v >= voltage_max)
1485                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1486
1487         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1488         if (p >= preemph_max)
1489                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1490
1491         for (lane = 0; lane < 4; lane++)
1492                 intel_dp->train_set[lane] = v | p;
1493 }
1494
1495 static uint32_t
1496 intel_dp_signal_levels(uint8_t train_set)
1497 {
1498         uint32_t        signal_levels = 0;
1499
1500         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1501         case DP_TRAIN_VOLTAGE_SWING_400:
1502         default:
1503                 signal_levels |= DP_VOLTAGE_0_4;
1504                 break;
1505         case DP_TRAIN_VOLTAGE_SWING_600:
1506                 signal_levels |= DP_VOLTAGE_0_6;
1507                 break;
1508         case DP_TRAIN_VOLTAGE_SWING_800:
1509                 signal_levels |= DP_VOLTAGE_0_8;
1510                 break;
1511         case DP_TRAIN_VOLTAGE_SWING_1200:
1512                 signal_levels |= DP_VOLTAGE_1_2;
1513                 break;
1514         }
1515         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1516         case DP_TRAIN_PRE_EMPHASIS_0:
1517         default:
1518                 signal_levels |= DP_PRE_EMPHASIS_0;
1519                 break;
1520         case DP_TRAIN_PRE_EMPHASIS_3_5:
1521                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1522                 break;
1523         case DP_TRAIN_PRE_EMPHASIS_6:
1524                 signal_levels |= DP_PRE_EMPHASIS_6;
1525                 break;
1526         case DP_TRAIN_PRE_EMPHASIS_9_5:
1527                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1528                 break;
1529         }
1530         return signal_levels;
1531 }
1532
1533 /* Gen6's DP voltage swing and pre-emphasis control */
1534 static uint32_t
1535 intel_gen6_edp_signal_levels(uint8_t train_set)
1536 {
1537         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1538                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1539         switch (signal_levels) {
1540         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1541         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1542                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1543         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1544                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1545         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1546         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1547                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1548         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1549         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1550                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1551         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1552         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1553                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1554         default:
1555                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1556                               "0x%x\n", signal_levels);
1557                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1558         }
1559 }
1560
1561 /* Gen7's DP voltage swing and pre-emphasis control */
1562 static uint32_t
1563 intel_gen7_edp_signal_levels(uint8_t train_set)
1564 {
1565         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1566                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1567         switch (signal_levels) {
1568         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1569                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1570         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1571                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1572         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1573                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1574
1575         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1576                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1577         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1578                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1579
1580         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1581                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1582         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1583                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1584
1585         default:
1586                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1587                               "0x%x\n", signal_levels);
1588                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1589         }
1590 }
1591
1592 static uint8_t
1593 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1594                       int lane)
1595 {
1596         int s = (lane & 1) * 4;
1597         uint8_t l = link_status[lane>>1];
1598
1599         return (l >> s) & 0xf;
1600 }
1601
1602 /* Check for clock recovery is done on all channels */
1603 static bool
1604 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1605 {
1606         int lane;
1607         uint8_t lane_status;
1608
1609         for (lane = 0; lane < lane_count; lane++) {
1610                 lane_status = intel_get_lane_status(link_status, lane);
1611                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1612                         return false;
1613         }
1614         return true;
1615 }
1616
1617 /* Check to see if channel eq is done on all channels */
1618 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1619                          DP_LANE_CHANNEL_EQ_DONE|\
1620                          DP_LANE_SYMBOL_LOCKED)
1621 static bool
1622 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1623 {
1624         uint8_t lane_align;
1625         uint8_t lane_status;
1626         int lane;
1627
1628         lane_align = intel_dp_link_status(link_status,
1629                                           DP_LANE_ALIGN_STATUS_UPDATED);
1630         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1631                 return false;
1632         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1633                 lane_status = intel_get_lane_status(link_status, lane);
1634                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1635                         return false;
1636         }
1637         return true;
1638 }
1639
1640 static bool
1641 intel_dp_set_link_train(struct intel_dp *intel_dp,
1642                         uint32_t dp_reg_value,
1643                         uint8_t dp_train_pat)
1644 {
1645         struct drm_device *dev = intel_dp->base.base.dev;
1646         struct drm_i915_private *dev_priv = dev->dev_private;
1647         int ret;
1648
1649         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1650         POSTING_READ(intel_dp->output_reg);
1651
1652         intel_dp_aux_native_write_1(intel_dp,
1653                                     DP_TRAINING_PATTERN_SET,
1654                                     dp_train_pat);
1655
1656         ret = intel_dp_aux_native_write(intel_dp,
1657                                         DP_TRAINING_LANE0_SET,
1658                                         intel_dp->train_set,
1659                                         intel_dp->lane_count);
1660         if (ret != intel_dp->lane_count)
1661                 return false;
1662
1663         return true;
1664 }
1665
1666 /* Enable corresponding port and start training pattern 1 */
1667 static void
1668 intel_dp_start_link_train(struct intel_dp *intel_dp)
1669 {
1670         struct drm_device *dev = intel_dp->base.base.dev;
1671         struct drm_i915_private *dev_priv = dev->dev_private;
1672         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1673         int i;
1674         uint8_t voltage;
1675         bool clock_recovery = false;
1676         int voltage_tries, loop_tries;
1677         u32 reg;
1678         uint32_t DP = intel_dp->DP;
1679
1680         /*
1681          * On CPT we have to enable the port in training pattern 1, which
1682          * will happen below in intel_dp_set_link_train.  Otherwise, enable
1683          * the port and wait for it to become active.
1684          */
1685         if (!HAS_PCH_CPT(dev)) {
1686                 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1687                 POSTING_READ(intel_dp->output_reg);
1688                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1689         }
1690
1691         /* Write the link configuration data */
1692         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1693                                   intel_dp->link_configuration,
1694                                   DP_LINK_CONFIGURATION_SIZE);
1695
1696         DP |= DP_PORT_EN;
1697
1698         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1699                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1700         else
1701                 DP &= ~DP_LINK_TRAIN_MASK;
1702         memset(intel_dp->train_set, 0, 4);
1703         voltage = 0xff;
1704         voltage_tries = 0;
1705         loop_tries = 0;
1706         clock_recovery = false;
1707         for (;;) {
1708                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1709                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1710                 uint32_t    signal_levels;
1711
1712
1713                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1714                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1715                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1716                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1717                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1718                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1719                 } else {
1720                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1721                         DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1722                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1723                 }
1724
1725                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1726                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1727                 else
1728                         reg = DP | DP_LINK_TRAIN_PAT_1;
1729
1730                 if (!intel_dp_set_link_train(intel_dp, reg,
1731                                              DP_TRAINING_PATTERN_1 |
1732                                              DP_LINK_SCRAMBLING_DISABLE))
1733                         break;
1734                 /* Set training pattern 1 */
1735
1736                 udelay(100);
1737                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1738                         DRM_ERROR("failed to get link status\n");
1739                         break;
1740                 }
1741
1742                 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1743                         DRM_DEBUG_KMS("clock recovery OK\n");
1744                         clock_recovery = true;
1745                         break;
1746                 }
1747
1748                 /* Check to see if we've tried the max voltage */
1749                 for (i = 0; i < intel_dp->lane_count; i++)
1750                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1751                                 break;
1752                 if (i == intel_dp->lane_count) {
1753                         ++loop_tries;
1754                         if (loop_tries == 5) {
1755                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1756                                 break;
1757                         }
1758                         memset(intel_dp->train_set, 0, 4);
1759                         voltage_tries = 0;
1760                         continue;
1761                 }
1762
1763                 /* Check to see if we've tried the same voltage 5 times */
1764                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1765                         ++voltage_tries;
1766                         if (voltage_tries == 5) {
1767                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1768                                 break;
1769                         }
1770                 } else
1771                         voltage_tries = 0;
1772                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1773
1774                 /* Compute new intel_dp->train_set as requested by target */
1775                 intel_get_adjust_train(intel_dp, link_status);
1776         }
1777
1778         intel_dp->DP = DP;
1779 }
1780
1781 static void
1782 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1783 {
1784         struct drm_device *dev = intel_dp->base.base.dev;
1785         struct drm_i915_private *dev_priv = dev->dev_private;
1786         bool channel_eq = false;
1787         int tries, cr_tries;
1788         u32 reg;
1789         uint32_t DP = intel_dp->DP;
1790
1791         /* channel equalization */
1792         tries = 0;
1793         cr_tries = 0;
1794         channel_eq = false;
1795         for (;;) {
1796                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1797                 uint32_t    signal_levels;
1798                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1799
1800                 if (cr_tries > 5) {
1801                         DRM_ERROR("failed to train DP, aborting\n");
1802                         intel_dp_link_down(intel_dp);
1803                         break;
1804                 }
1805
1806                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1807                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1808                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1809                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1810                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1811                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1812                 } else {
1813                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1814                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1815                 }
1816
1817                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1818                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1819                 else
1820                         reg = DP | DP_LINK_TRAIN_PAT_2;
1821
1822                 /* channel eq pattern */
1823                 if (!intel_dp_set_link_train(intel_dp, reg,
1824                                              DP_TRAINING_PATTERN_2 |
1825                                              DP_LINK_SCRAMBLING_DISABLE))
1826                         break;
1827
1828                 udelay(400);
1829                 if (!intel_dp_get_link_status(intel_dp, link_status))
1830                         break;
1831
1832                 /* Make sure clock is still ok */
1833                 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1834                         intel_dp_start_link_train(intel_dp);
1835                         cr_tries++;
1836                         continue;
1837                 }
1838
1839                 if (intel_channel_eq_ok(intel_dp, link_status)) {
1840                         channel_eq = true;
1841                         break;
1842                 }
1843
1844                 /* Try 5 times, then try clock recovery if that fails */
1845                 if (tries > 5) {
1846                         intel_dp_link_down(intel_dp);
1847                         intel_dp_start_link_train(intel_dp);
1848                         tries = 0;
1849                         cr_tries++;
1850                         continue;
1851                 }
1852
1853                 /* Compute new intel_dp->train_set as requested by target */
1854                 intel_get_adjust_train(intel_dp, link_status);
1855                 ++tries;
1856         }
1857
1858         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1859                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1860         else
1861                 reg = DP | DP_LINK_TRAIN_OFF;
1862
1863         I915_WRITE(intel_dp->output_reg, reg);
1864         POSTING_READ(intel_dp->output_reg);
1865         intel_dp_aux_native_write_1(intel_dp,
1866                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1867 }
1868
1869 static void
1870 intel_dp_link_down(struct intel_dp *intel_dp)
1871 {
1872         struct drm_device *dev = intel_dp->base.base.dev;
1873         struct drm_i915_private *dev_priv = dev->dev_private;
1874         uint32_t DP = intel_dp->DP;
1875
1876         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1877                 return;
1878
1879         DRM_DEBUG_KMS("\n");
1880
1881         if (is_edp(intel_dp)) {
1882                 DP &= ~DP_PLL_ENABLE;
1883                 I915_WRITE(intel_dp->output_reg, DP);
1884                 POSTING_READ(intel_dp->output_reg);
1885                 udelay(100);
1886         }
1887
1888         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1889                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1890                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1891         } else {
1892                 DP &= ~DP_LINK_TRAIN_MASK;
1893                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1894         }
1895         POSTING_READ(intel_dp->output_reg);
1896
1897         msleep(17);
1898
1899         if (is_edp(intel_dp)) {
1900                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1901                         DP |= DP_LINK_TRAIN_OFF_CPT;
1902                 else
1903                         DP |= DP_LINK_TRAIN_OFF;
1904         }
1905
1906         if (!HAS_PCH_CPT(dev) &&
1907             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1908                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1909
1910                 /* Hardware workaround: leaving our transcoder select
1911                  * set to transcoder B while it's off will prevent the
1912                  * corresponding HDMI output on transcoder A.
1913                  *
1914                  * Combine this with another hardware workaround:
1915                  * transcoder select bit can only be cleared while the
1916                  * port is enabled.
1917                  */
1918                 DP &= ~DP_PIPEB_SELECT;
1919                 I915_WRITE(intel_dp->output_reg, DP);
1920
1921                 /* Changes to enable or select take place the vblank
1922                  * after being written.
1923                  */
1924                 if (crtc == NULL) {
1925                         /* We can arrive here never having been attached
1926                          * to a CRTC, for instance, due to inheriting
1927                          * random state from the BIOS.
1928                          *
1929                          * If the pipe is not running, play safe and
1930                          * wait for the clocks to stabilise before
1931                          * continuing.
1932                          */
1933                         POSTING_READ(intel_dp->output_reg);
1934                         msleep(50);
1935                 } else
1936                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1937         }
1938
1939         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
1940         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1941         POSTING_READ(intel_dp->output_reg);
1942         msleep(intel_dp->panel_power_down_delay);
1943 }
1944
1945 static bool
1946 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1947 {
1948         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1949                                            sizeof(intel_dp->dpcd)) &&
1950             (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1951                 return true;
1952         }
1953
1954         return false;
1955 }
1956
1957 static bool
1958 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1959 {
1960         int ret;
1961
1962         ret = intel_dp_aux_native_read_retry(intel_dp,
1963                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
1964                                              sink_irq_vector, 1);
1965         if (!ret)
1966                 return false;
1967
1968         return true;
1969 }
1970
1971 static void
1972 intel_dp_handle_test_request(struct intel_dp *intel_dp)
1973 {
1974         /* NAK by default */
1975         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1976 }
1977
1978 /*
1979  * According to DP spec
1980  * 5.1.2:
1981  *  1. Read DPCD
1982  *  2. Configure link according to Receiver Capabilities
1983  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1984  *  4. Check link status on receipt of hot-plug interrupt
1985  */
1986
1987 static void
1988 intel_dp_check_link_status(struct intel_dp *intel_dp)
1989 {
1990         u8 sink_irq_vector;
1991         u8 link_status[DP_LINK_STATUS_SIZE];
1992
1993         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1994                 return;
1995
1996         if (!intel_dp->base.base.crtc)
1997                 return;
1998
1999         /* Try to read receiver status if the link appears to be up */
2000         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2001                 intel_dp_link_down(intel_dp);
2002                 return;
2003         }
2004
2005         /* Now read the DPCD to see if it's actually running */
2006         if (!intel_dp_get_dpcd(intel_dp)) {
2007                 intel_dp_link_down(intel_dp);
2008                 return;
2009         }
2010
2011         /* Try to read the source of the interrupt */
2012         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2013             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2014                 /* Clear interrupt source */
2015                 intel_dp_aux_native_write_1(intel_dp,
2016                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2017                                             sink_irq_vector);
2018
2019                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2020                         intel_dp_handle_test_request(intel_dp);
2021                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2022                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2023         }
2024
2025         if (!intel_channel_eq_ok(intel_dp, link_status)) {
2026                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2027                               drm_get_encoder_name(&intel_dp->base.base));
2028                 intel_dp_start_link_train(intel_dp);
2029                 intel_dp_complete_link_train(intel_dp);
2030         }
2031 }
2032
2033 static enum drm_connector_status
2034 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2035 {
2036         if (intel_dp_get_dpcd(intel_dp))
2037                 return connector_status_connected;
2038         return connector_status_disconnected;
2039 }
2040
2041 static enum drm_connector_status
2042 ironlake_dp_detect(struct intel_dp *intel_dp)
2043 {
2044         enum drm_connector_status status;
2045
2046         /* Can't disconnect eDP, but you can close the lid... */
2047         if (is_edp(intel_dp)) {
2048                 status = intel_panel_detect(intel_dp->base.base.dev);
2049                 if (status == connector_status_unknown)
2050                         status = connector_status_connected;
2051                 return status;
2052         }
2053
2054         return intel_dp_detect_dpcd(intel_dp);
2055 }
2056
2057 static enum drm_connector_status
2058 g4x_dp_detect(struct intel_dp *intel_dp)
2059 {
2060         struct drm_device *dev = intel_dp->base.base.dev;
2061         struct drm_i915_private *dev_priv = dev->dev_private;
2062         uint32_t temp, bit;
2063
2064         switch (intel_dp->output_reg) {
2065         case DP_B:
2066                 bit = DPB_HOTPLUG_INT_STATUS;
2067                 break;
2068         case DP_C:
2069                 bit = DPC_HOTPLUG_INT_STATUS;
2070                 break;
2071         case DP_D:
2072                 bit = DPD_HOTPLUG_INT_STATUS;
2073                 break;
2074         default:
2075                 return connector_status_unknown;
2076         }
2077
2078         temp = I915_READ(PORT_HOTPLUG_STAT);
2079
2080         if ((temp & bit) == 0)
2081                 return connector_status_disconnected;
2082
2083         return intel_dp_detect_dpcd(intel_dp);
2084 }
2085
2086 static struct edid *
2087 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2088 {
2089         struct intel_dp *intel_dp = intel_attached_dp(connector);
2090         struct edid     *edid;
2091
2092         ironlake_edp_panel_vdd_on(intel_dp);
2093         edid = drm_get_edid(connector, adapter);
2094         ironlake_edp_panel_vdd_off(intel_dp, false);
2095         return edid;
2096 }
2097
2098 static int
2099 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2100 {
2101         struct intel_dp *intel_dp = intel_attached_dp(connector);
2102         int     ret;
2103
2104         ironlake_edp_panel_vdd_on(intel_dp);
2105         ret = intel_ddc_get_modes(connector, adapter);
2106         ironlake_edp_panel_vdd_off(intel_dp, false);
2107         return ret;
2108 }
2109
2110
2111 /**
2112  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2113  *
2114  * \return true if DP port is connected.
2115  * \return false if DP port is disconnected.
2116  */
2117 static enum drm_connector_status
2118 intel_dp_detect(struct drm_connector *connector, bool force)
2119 {
2120         struct intel_dp *intel_dp = intel_attached_dp(connector);
2121         struct drm_device *dev = intel_dp->base.base.dev;
2122         enum drm_connector_status status;
2123         struct edid *edid = NULL;
2124
2125         intel_dp->has_audio = false;
2126
2127         if (HAS_PCH_SPLIT(dev))
2128                 status = ironlake_dp_detect(intel_dp);
2129         else
2130                 status = g4x_dp_detect(intel_dp);
2131
2132         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2133                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2134                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2135                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
2136
2137         if (status != connector_status_connected)
2138                 return status;
2139
2140         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2141                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2142         } else {
2143                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2144                 if (edid) {
2145                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2146                         connector->display_info.raw_edid = NULL;
2147                         kfree(edid);
2148                 }
2149         }
2150
2151         return connector_status_connected;
2152 }
2153
2154 static int intel_dp_get_modes(struct drm_connector *connector)
2155 {
2156         struct intel_dp *intel_dp = intel_attached_dp(connector);
2157         struct drm_device *dev = intel_dp->base.base.dev;
2158         struct drm_i915_private *dev_priv = dev->dev_private;
2159         int ret;
2160
2161         /* We should parse the EDID data and find out if it has an audio sink
2162          */
2163
2164         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2165         if (ret) {
2166                 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2167                         struct drm_display_mode *newmode;
2168                         list_for_each_entry(newmode, &connector->probed_modes,
2169                                             head) {
2170                                 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2171                                         intel_dp->panel_fixed_mode =
2172                                                 drm_mode_duplicate(dev, newmode);
2173                                         break;
2174                                 }
2175                         }
2176                 }
2177                 return ret;
2178         }
2179
2180         /* if eDP has no EDID, try to use fixed panel mode from VBT */
2181         if (is_edp(intel_dp)) {
2182                 /* initialize panel mode from VBT if available for eDP */
2183                 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2184                         intel_dp->panel_fixed_mode =
2185                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2186                         if (intel_dp->panel_fixed_mode) {
2187                                 intel_dp->panel_fixed_mode->type |=
2188                                         DRM_MODE_TYPE_PREFERRED;
2189                         }
2190                 }
2191                 if (intel_dp->panel_fixed_mode) {
2192                         struct drm_display_mode *mode;
2193                         mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2194                         drm_mode_probed_add(connector, mode);
2195                         return 1;
2196                 }
2197         }
2198         return 0;
2199 }
2200
2201 static bool
2202 intel_dp_detect_audio(struct drm_connector *connector)
2203 {
2204         struct intel_dp *intel_dp = intel_attached_dp(connector);
2205         struct edid *edid;
2206         bool has_audio = false;
2207
2208         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2209         if (edid) {
2210                 has_audio = drm_detect_monitor_audio(edid);
2211
2212                 connector->display_info.raw_edid = NULL;
2213                 kfree(edid);
2214         }
2215
2216         return has_audio;
2217 }
2218
2219 static int
2220 intel_dp_set_property(struct drm_connector *connector,
2221                       struct drm_property *property,
2222                       uint64_t val)
2223 {
2224         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2225         struct intel_dp *intel_dp = intel_attached_dp(connector);
2226         int ret;
2227
2228         ret = drm_connector_property_set_value(connector, property, val);
2229         if (ret)
2230                 return ret;
2231
2232         if (property == dev_priv->force_audio_property) {
2233                 int i = val;
2234                 bool has_audio;
2235
2236                 if (i == intel_dp->force_audio)
2237                         return 0;
2238
2239                 intel_dp->force_audio = i;
2240
2241                 if (i == HDMI_AUDIO_AUTO)
2242                         has_audio = intel_dp_detect_audio(connector);
2243                 else
2244                         has_audio = (i == HDMI_AUDIO_ON);
2245
2246                 if (has_audio == intel_dp->has_audio)
2247                         return 0;
2248
2249                 intel_dp->has_audio = has_audio;
2250                 goto done;
2251         }
2252
2253         if (property == dev_priv->broadcast_rgb_property) {
2254                 if (val == !!intel_dp->color_range)
2255                         return 0;
2256
2257                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2258                 goto done;
2259         }
2260
2261         return -EINVAL;
2262
2263 done:
2264         if (intel_dp->base.base.crtc) {
2265                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2266                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2267                                          crtc->x, crtc->y,
2268                                          crtc->fb);
2269         }
2270
2271         return 0;
2272 }
2273
2274 static void
2275 intel_dp_destroy(struct drm_connector *connector)
2276 {
2277         struct drm_device *dev = connector->dev;
2278
2279         if (intel_dpd_is_edp(dev))
2280                 intel_panel_destroy_backlight(dev);
2281
2282         drm_sysfs_connector_remove(connector);
2283         drm_connector_cleanup(connector);
2284         kfree(connector);
2285 }
2286
2287 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2288 {
2289         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2290
2291         i2c_del_adapter(&intel_dp->adapter);
2292         drm_encoder_cleanup(encoder);
2293         if (is_edp(intel_dp)) {
2294                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2295                 ironlake_panel_vdd_off_sync(intel_dp);
2296         }
2297         kfree(intel_dp);
2298 }
2299
2300 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2301         .dpms = intel_dp_dpms,
2302         .mode_fixup = intel_dp_mode_fixup,
2303         .prepare = intel_dp_prepare,
2304         .mode_set = intel_dp_mode_set,
2305         .commit = intel_dp_commit,
2306 };
2307
2308 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2309         .dpms = drm_helper_connector_dpms,
2310         .detect = intel_dp_detect,
2311         .fill_modes = drm_helper_probe_single_connector_modes,
2312         .set_property = intel_dp_set_property,
2313         .destroy = intel_dp_destroy,
2314 };
2315
2316 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2317         .get_modes = intel_dp_get_modes,
2318         .mode_valid = intel_dp_mode_valid,
2319         .best_encoder = intel_best_encoder,
2320 };
2321
2322 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2323         .destroy = intel_dp_encoder_destroy,
2324 };
2325
2326 static void
2327 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2328 {
2329         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2330
2331         intel_dp_check_link_status(intel_dp);
2332 }
2333
2334 /* Return which DP Port should be selected for Transcoder DP control */
2335 int
2336 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2337 {
2338         struct drm_device *dev = crtc->dev;
2339         struct drm_mode_config *mode_config = &dev->mode_config;
2340         struct drm_encoder *encoder;
2341
2342         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2343                 struct intel_dp *intel_dp;
2344
2345                 if (encoder->crtc != crtc)
2346                         continue;
2347
2348                 intel_dp = enc_to_intel_dp(encoder);
2349                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2350                     intel_dp->base.type == INTEL_OUTPUT_EDP)
2351                         return intel_dp->output_reg;
2352         }
2353
2354         return -1;
2355 }
2356
2357 /* check the VBT to see whether the eDP is on DP-D port */
2358 bool intel_dpd_is_edp(struct drm_device *dev)
2359 {
2360         struct drm_i915_private *dev_priv = dev->dev_private;
2361         struct child_device_config *p_child;
2362         int i;
2363
2364         if (!dev_priv->child_dev_num)
2365                 return false;
2366
2367         for (i = 0; i < dev_priv->child_dev_num; i++) {
2368                 p_child = dev_priv->child_dev + i;
2369
2370                 if (p_child->dvo_port == PORT_IDPD &&
2371                     p_child->device_type == DEVICE_TYPE_eDP)
2372                         return true;
2373         }
2374         return false;
2375 }
2376
2377 static void
2378 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2379 {
2380         intel_attach_force_audio_property(connector);
2381         intel_attach_broadcast_rgb_property(connector);
2382 }
2383
2384 void
2385 intel_dp_init(struct drm_device *dev, int output_reg)
2386 {
2387         struct drm_i915_private *dev_priv = dev->dev_private;
2388         struct drm_connector *connector;
2389         struct intel_dp *intel_dp;
2390         struct intel_encoder *intel_encoder;
2391         struct intel_connector *intel_connector;
2392         const char *name = NULL;
2393         int type;
2394
2395         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2396         if (!intel_dp)
2397                 return;
2398
2399         intel_dp->output_reg = output_reg;
2400         intel_dp->dpms_mode = -1;
2401
2402         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2403         if (!intel_connector) {
2404                 kfree(intel_dp);
2405                 return;
2406         }
2407         intel_encoder = &intel_dp->base;
2408
2409         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2410                 if (intel_dpd_is_edp(dev))
2411                         intel_dp->is_pch_edp = true;
2412
2413         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2414                 type = DRM_MODE_CONNECTOR_eDP;
2415                 intel_encoder->type = INTEL_OUTPUT_EDP;
2416         } else {
2417                 type = DRM_MODE_CONNECTOR_DisplayPort;
2418                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2419         }
2420
2421         connector = &intel_connector->base;
2422         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2423         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2424
2425         connector->polled = DRM_CONNECTOR_POLL_HPD;
2426
2427         if (output_reg == DP_B || output_reg == PCH_DP_B)
2428                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2429         else if (output_reg == DP_C || output_reg == PCH_DP_C)
2430                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2431         else if (output_reg == DP_D || output_reg == PCH_DP_D)
2432                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2433
2434         if (is_edp(intel_dp)) {
2435                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2436                 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2437                                   ironlake_panel_vdd_work);
2438         }
2439
2440         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2441         connector->interlace_allowed = true;
2442         connector->doublescan_allowed = 0;
2443
2444         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2445                          DRM_MODE_ENCODER_TMDS);
2446         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2447
2448         intel_connector_attach_encoder(intel_connector, intel_encoder);
2449         drm_sysfs_connector_add(connector);
2450
2451         /* Set up the DDC bus. */
2452         switch (output_reg) {
2453                 case DP_A:
2454                         name = "DPDDC-A";
2455                         break;
2456                 case DP_B:
2457                 case PCH_DP_B:
2458                         dev_priv->hotplug_supported_mask |=
2459                                 HDMIB_HOTPLUG_INT_STATUS;
2460                         name = "DPDDC-B";
2461                         break;
2462                 case DP_C:
2463                 case PCH_DP_C:
2464                         dev_priv->hotplug_supported_mask |=
2465                                 HDMIC_HOTPLUG_INT_STATUS;
2466                         name = "DPDDC-C";
2467                         break;
2468                 case DP_D:
2469                 case PCH_DP_D:
2470                         dev_priv->hotplug_supported_mask |=
2471                                 HDMID_HOTPLUG_INT_STATUS;
2472                         name = "DPDDC-D";
2473                         break;
2474         }
2475
2476         /* Cache some DPCD data in the eDP case */
2477         if (is_edp(intel_dp)) {
2478                 bool ret;
2479                 struct edp_power_seq    cur, vbt;
2480                 u32 pp_on, pp_off, pp_div;
2481
2482                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2483                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2484                 pp_div = I915_READ(PCH_PP_DIVISOR);
2485
2486                 /* Pull timing values out of registers */
2487                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2488                         PANEL_POWER_UP_DELAY_SHIFT;
2489
2490                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2491                         PANEL_LIGHT_ON_DELAY_SHIFT;
2492
2493                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2494                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2495
2496                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2497                         PANEL_POWER_DOWN_DELAY_SHIFT;
2498
2499                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2500                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2501
2502                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2503                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2504
2505                 vbt = dev_priv->edp.pps;
2506
2507                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2508                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2509
2510 #define get_delay(field)        ((max(cur.field, vbt.field) + 9) / 10)
2511
2512                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2513                 intel_dp->backlight_on_delay = get_delay(t8);
2514                 intel_dp->backlight_off_delay = get_delay(t9);
2515                 intel_dp->panel_power_down_delay = get_delay(t10);
2516                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2517
2518                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2519                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2520                               intel_dp->panel_power_cycle_delay);
2521
2522                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2523                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2524
2525                 ironlake_edp_panel_vdd_on(intel_dp);
2526                 ret = intel_dp_get_dpcd(intel_dp);
2527                 ironlake_edp_panel_vdd_off(intel_dp, false);
2528
2529                 if (ret) {
2530                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2531                                 dev_priv->no_aux_handshake =
2532                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2533                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2534                 } else {
2535                         /* if this fails, presume the device is a ghost */
2536                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2537                         intel_dp_encoder_destroy(&intel_dp->base.base);
2538                         intel_dp_destroy(&intel_connector->base);
2539                         return;
2540                 }
2541         }
2542
2543         intel_dp_i2c_init(intel_dp, intel_connector, name);
2544
2545         intel_encoder->hot_plug = intel_dp_hot_plug;
2546
2547         if (is_edp(intel_dp)) {
2548                 dev_priv->int_edp_connector = connector;
2549                 intel_panel_setup_backlight(dev);
2550         }
2551
2552         intel_dp_add_properties(intel_dp, connector);
2553
2554         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2555          * 0xd.  Failure to do so will result in spurious interrupts being
2556          * generated on the port when a cable is not attached.
2557          */
2558         if (IS_G4X(dev) && !IS_GM45(dev)) {
2559                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2560                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2561         }
2562 }