drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "drm_crtc.h"
  34 #include "drm_crtc_helper.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "drm_dp_helper.h"
  39
  40 #define DP_RECEIVER_CAP_SIZE    0xf
  41 #define DP_LINK_STATUS_SIZE     6
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 #define DP_LINK_CONFIGURATION_SIZE      9
  45
  46 struct intel_dp {
  47         struct intel_encoder base;
  48         uint32_t output_reg;
  49         uint32_t DP;
  50         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  51         bool has_audio;
  52         enum hdmi_force_audio force_audio;
  53         uint32_t color_range;
  54         int dpms_mode;
  55         uint8_t link_bw;
  56         uint8_t lane_count;
  57         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  58         struct i2c_adapter adapter;
  59         struct i2c_algo_dp_aux_data algo;
  60         bool is_pch_edp;
  61         uint8_t train_set[4];
  62         int panel_power_up_delay;
  63         int panel_power_down_delay;
  64         int panel_power_cycle_delay;
  65         int backlight_on_delay;
  66         int backlight_off_delay;
  67         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
  68         struct delayed_work panel_vdd_work;
  69         bool want_panel_vdd;
  70 };
  71
  72 /**
  73  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  74  * @intel_dp: DP struct
  75  *
  76  * If a CPU or PCH DP output is attached to an eDP panel, this function
  77  * will return true, and false otherwise.
  78  */
  79 static bool is_edp(struct intel_dp *intel_dp)
  80 {
  81         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  82 }
  83
  84 /**
  85  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  86  * @intel_dp: DP struct
  87  *
  88  * Returns true if the given DP struct corresponds to a PCH DP port attached
  89  * to an eDP panel, false otherwise.  Helpful for determining whether we
  90  * may need FDI resources for a given DP output or not.
  91  */
  92 static bool is_pch_edp(struct intel_dp *intel_dp)
  93 {
  94         return intel_dp->is_pch_edp;
  95 }
  96
  97 /**
  98  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  99  * @intel_dp: DP struct
 100  *
 101  * Returns true if the given DP struct corresponds to a CPU eDP port.
 102  */
 103 static bool is_cpu_edp(struct intel_dp *intel_dp)
 104 {
 105         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
 106 }
 107
 108 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 109 {
 110         return container_of(encoder, struct intel_dp, base.base);
 111 }
 112
 113 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 114 {
 115         return container_of(intel_attached_encoder(connector),
 116                             struct intel_dp, base);
 117 }
 118
 119 /**
 120  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 121  * @encoder: DRM encoder
 122  *
 123  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 124  * by intel_display.c.
 125  */
 126 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 127 {
 128         struct intel_dp *intel_dp;
 129
 130         if (!encoder)
 131                 return false;
 132
 133         intel_dp = enc_to_intel_dp(encoder);
 134
 135         return is_pch_edp(intel_dp);
 136 }
 137
 138 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 139 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 140 static void intel_dp_link_down(struct intel_dp *intel_dp);
 141
 142 void
 143 intel_edp_link_config(struct intel_encoder *intel_encoder,
 144                        int *lane_num, int *link_bw)
 145 {
 146         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 147
 148         *lane_num = intel_dp->lane_count;
 149         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 150                 *link_bw = 162000;
 151         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 152                 *link_bw = 270000;
 153 }
 154
 155 static int
 156 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 157 {
 158         int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 159         switch (max_lane_count) {
 160         case 1: case 2: case 4:
 161                 break;
 162         default:
 163                 max_lane_count = 4;
 164         }
 165         return max_lane_count;
 166 }
 167
 168 static int
 169 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 170 {
 171         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 172
 173         switch (max_link_bw) {
 174         case DP_LINK_BW_1_62:
 175         case DP_LINK_BW_2_7:
 176                 break;
 177         default:
 178                 max_link_bw = DP_LINK_BW_1_62;
 179                 break;
 180         }
 181         return max_link_bw;
 182 }
 183
 184 static int
 185 intel_dp_link_clock(uint8_t link_bw)
 186 {
 187         if (link_bw == DP_LINK_BW_2_7)
 188                 return 270000;
 189         else
 190                 return 162000;
 191 }
 192
 193 /*
 194  * The units on the numbers in the next two are... bizarre.  Examples will
 195  * make it clearer; this one parallels an example in the eDP spec.
 196  *
 197  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 198  *
 199  *     270000 * 1 * 8 / 10 == 216000
 200  *
 201  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 202  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 203  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 204  * 119000.  At 18bpp that's 2142000 kilobits per second.
 205  *
 206  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 207  * get the result in decakilobits instead of kilobits.
 208  */
 209
 210 static int
 211 intel_dp_link_required(int pixel_clock, int bpp)
 212 {
 213         return (pixel_clock * bpp + 9) / 10;
 214 }
 215
 216 static int
 217 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 218 {
 219         return (max_link_clock * max_lanes * 8) / 10;
 220 }
 221
 222 static bool
 223 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
 224                           struct drm_display_mode *mode,
 225                           struct drm_display_mode *adjusted_mode)
 226 {
 227         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 228         int max_lanes = intel_dp_max_lane_count(intel_dp);
 229         int max_rate, mode_rate;
 230
 231         mode_rate = intel_dp_link_required(mode->clock, 24);
 232         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 233
 234         if (mode_rate > max_rate) {
 235                 mode_rate = intel_dp_link_required(mode->clock, 18);
 236                 if (mode_rate > max_rate)
 237                         return false;
 238
 239                 if (adjusted_mode)
 240                         adjusted_mode->private_flags
 241                                 |= INTEL_MODE_DP_FORCE_6BPC;
 242
 243                 return true;
 244         }
 245
 246         return true;
 247 }
 248
 249 static int
 250 intel_dp_mode_valid(struct drm_connector *connector,
 251                     struct drm_display_mode *mode)
 252 {
 253         struct intel_dp *intel_dp = intel_attached_dp(connector);
 254
 255         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 256                 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 257                         return MODE_PANEL;
 258
 259                 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 260                         return MODE_PANEL;
 261         }
 262
 263         if (!intel_dp_adjust_dithering(intel_dp, mode, NULL))
 264                 return MODE_CLOCK_HIGH;
 265
 266         if (mode->clock < 10000)
 267                 return MODE_CLOCK_LOW;
 268
 269         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 270                 return MODE_H_ILLEGAL;
 271
 272         return MODE_OK;
 273 }
 274
 275 static uint32_t
 276 pack_aux(uint8_t *src, int src_bytes)
 277 {
 278         int     i;
 279         uint32_t v = 0;
 280
 281         if (src_bytes > 4)
 282                 src_bytes = 4;
 283         for (i = 0; i < src_bytes; i++)
 284                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 285         return v;
 286 }
 287
 288 static void
 289 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 290 {
 291         int i;
 292         if (dst_bytes > 4)
 293                 dst_bytes = 4;
 294         for (i = 0; i < dst_bytes; i++)
 295                 dst[i] = src >> ((3-i) * 8);
 296 }
 297
 298 /* hrawclock is 1/4 the FSB frequency */
 299 static int
 300 intel_hrawclk(struct drm_device *dev)
 301 {
 302         struct drm_i915_private *dev_priv = dev->dev_private;
 303         uint32_t clkcfg;
 304
 305         clkcfg = I915_READ(CLKCFG);
 306         switch (clkcfg & CLKCFG_FSB_MASK) {
 307         case CLKCFG_FSB_400:
 308                 return 100;
 309         case CLKCFG_FSB_533:
 310                 return 133;
 311         case CLKCFG_FSB_667:
 312                 return 166;
 313         case CLKCFG_FSB_800:
 314                 return 200;
 315         case CLKCFG_FSB_1067:
 316                 return 266;
 317         case CLKCFG_FSB_1333:
 318                 return 333;
 319         /* these two are just a guess; one of them might be right */
 320         case CLKCFG_FSB_1600:
 321         case CLKCFG_FSB_1600_ALT:
 322                 return 400;
 323         default:
 324                 return 133;
 325         }
 326 }
 327
 328 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 329 {
 330         struct drm_device *dev = intel_dp->base.base.dev;
 331         struct drm_i915_private *dev_priv = dev->dev_private;
 332
 333         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 334 }
 335
 336 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 337 {
 338         struct drm_device *dev = intel_dp->base.base.dev;
 339         struct drm_i915_private *dev_priv = dev->dev_private;
 340
 341         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 342 }
 343
 344 static void
 345 intel_dp_check_edp(struct intel_dp *intel_dp)
 346 {
 347         struct drm_device *dev = intel_dp->base.base.dev;
 348         struct drm_i915_private *dev_priv = dev->dev_private;
 349
 350         if (!is_edp(intel_dp))
 351                 return;
 352         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 353                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 354                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 355                               I915_READ(PCH_PP_STATUS),
 356                               I915_READ(PCH_PP_CONTROL));
 357         }
 358 }
 359
 360 static int
 361 intel_dp_aux_ch(struct intel_dp *intel_dp,
 362                 uint8_t *send, int send_bytes,
 363                 uint8_t *recv, int recv_size)
 364 {
 365         uint32_t output_reg = intel_dp->output_reg;
 366         struct drm_device *dev = intel_dp->base.base.dev;
 367         struct drm_i915_private *dev_priv = dev->dev_private;
 368         uint32_t ch_ctl = output_reg + 0x10;
 369         uint32_t ch_data = ch_ctl + 4;
 370         int i;
 371         int recv_bytes;
 372         uint32_t status;
 373         uint32_t aux_clock_divider;
 374         int try, precharge;
 375
 376         intel_dp_check_edp(intel_dp);
 377         /* The clock divider is based off the hrawclk,
 378          * and would like to run at 2MHz. So, take the
 379          * hrawclk value and divide by 2 and use that
 380          *
 381          * Note that PCH attached eDP panels should use a 125MHz input
 382          * clock divider.
 383          */
 384         if (is_cpu_edp(intel_dp)) {
 385                 if (IS_GEN6(dev) || IS_GEN7(dev))
 386                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 387                 else
 388                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 389         } else if (HAS_PCH_SPLIT(dev))
 390                 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
 391         else
 392                 aux_clock_divider = intel_hrawclk(dev) / 2;
 393
 394         if (IS_GEN6(dev))
 395                 precharge = 3;
 396         else
 397                 precharge = 5;
 398
 399         /* Try to wait for any previous AUX channel activity */
 400         for (try = 0; try < 3; try++) {
 401                 status = I915_READ(ch_ctl);
 402                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 403                         break;
 404                 msleep(1);
 405         }
 406
 407         if (try == 3) {
 408                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 409                      I915_READ(ch_ctl));
 410                 return -EBUSY;
 411         }
 412
 413         /* Must try at least 3 times according to DP spec */
 414         for (try = 0; try < 5; try++) {
 415                 /* Load the send data into the aux channel data registers */
 416                 for (i = 0; i < send_bytes; i += 4)
 417                         I915_WRITE(ch_data + i,
 418                                    pack_aux(send + i, send_bytes - i));
 419
 420                 /* Send the command and wait for it to complete */
 421                 I915_WRITE(ch_ctl,
 422                            DP_AUX_CH_CTL_SEND_BUSY |
 423                            DP_AUX_CH_CTL_TIME_OUT_400us |
 424                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 425                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 426                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 427                            DP_AUX_CH_CTL_DONE |
 428                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 429                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 430                 for (;;) {
 431                         status = I915_READ(ch_ctl);
 432                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 433                                 break;
 434                         udelay(100);
 435                 }
 436
 437                 /* Clear done status and any errors */
 438                 I915_WRITE(ch_ctl,
 439                            status |
 440                            DP_AUX_CH_CTL_DONE |
 441                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 442                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 443
 444                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 445                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 446                         continue;
 447                 if (status & DP_AUX_CH_CTL_DONE)
 448                         break;
 449         }
 450
 451         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 452                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 453                 return -EBUSY;
 454         }
 455
 456         /* Check for timeout or receive error.
 457          * Timeouts occur when the sink is not connected
 458          */
 459         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 460                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 461                 return -EIO;
 462         }
 463
 464         /* Timeouts occur when the device isn't connected, so they're
 465          * "normal" -- don't fill the kernel log with these */
 466         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 467                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 468                 return -ETIMEDOUT;
 469         }
 470
 471         /* Unload any bytes sent back from the other side */
 472         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 473                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 474         if (recv_bytes > recv_size)
 475                 recv_bytes = recv_size;
 476
 477         for (i = 0; i < recv_bytes; i += 4)
 478                 unpack_aux(I915_READ(ch_data + i),
 479                            recv + i, recv_bytes - i);
 480
 481         return recv_bytes;
 482 }
 483
 484 /* Write data to the aux channel in native mode */
 485 static int
 486 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 487                           uint16_t address, uint8_t *send, int send_bytes)
 488 {
 489         int ret;
 490         uint8_t msg[20];
 491         int msg_bytes;
 492         uint8_t ack;
 493
 494         intel_dp_check_edp(intel_dp);
 495         if (send_bytes > 16)
 496                 return -1;
 497         msg[0] = AUX_NATIVE_WRITE << 4;
 498         msg[1] = address >> 8;
 499         msg[2] = address & 0xff;
 500         msg[3] = send_bytes - 1;
 501         memcpy(&msg[4], send, send_bytes);
 502         msg_bytes = send_bytes + 4;
 503         for (;;) {
 504                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 505                 if (ret < 0)
 506                         return ret;
 507                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 508                         break;
 509                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 510                         udelay(100);
 511                 else
 512                         return -EIO;
 513         }
 514         return send_bytes;
 515 }
 516
 517 /* Write a single byte to the aux channel in native mode */
 518 static int
 519 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 520                             uint16_t address, uint8_t byte)
 521 {
 522         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 523 }
 524
 525 /* read bytes from a native aux channel */
 526 static int
 527 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 528                          uint16_t address, uint8_t *recv, int recv_bytes)
 529 {
 530         uint8_t msg[4];
 531         int msg_bytes;
 532         uint8_t reply[20];
 533         int reply_bytes;
 534         uint8_t ack;
 535         int ret;
 536
 537         intel_dp_check_edp(intel_dp);
 538         msg[0] = AUX_NATIVE_READ << 4;
 539         msg[1] = address >> 8;
 540         msg[2] = address & 0xff;
 541         msg[3] = recv_bytes - 1;
 542
 543         msg_bytes = 4;
 544         reply_bytes = recv_bytes + 1;
 545
 546         for (;;) {
 547                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 548                                       reply, reply_bytes);
 549                 if (ret == 0)
 550                         return -EPROTO;
 551                 if (ret < 0)
 552                         return ret;
 553                 ack = reply[0];
 554                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 555                         memcpy(recv, reply + 1, ret - 1);
 556                         return ret - 1;
 557                 }
 558                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 559                         udelay(100);
 560                 else
 561                         return -EIO;
 562         }
 563 }
 564
 565 static int
 566 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 567                     uint8_t write_byte, uint8_t *read_byte)
 568 {
 569         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 570         struct intel_dp *intel_dp = container_of(adapter,
 571                                                 struct intel_dp,
 572                                                 adapter);
 573         uint16_t address = algo_data->address;
 574         uint8_t msg[5];
 575         uint8_t reply[2];
 576         unsigned retry;
 577         int msg_bytes;
 578         int reply_bytes;
 579         int ret;
 580
 581         intel_dp_check_edp(intel_dp);
 582         /* Set up the command byte */
 583         if (mode & MODE_I2C_READ)
 584                 msg[0] = AUX_I2C_READ << 4;
 585         else
 586                 msg[0] = AUX_I2C_WRITE << 4;
 587
 588         if (!(mode & MODE_I2C_STOP))
 589                 msg[0] |= AUX_I2C_MOT << 4;
 590
 591         msg[1] = address >> 8;
 592         msg[2] = address;
 593
 594         switch (mode) {
 595         case MODE_I2C_WRITE:
 596                 msg[3] = 0;
 597                 msg[4] = write_byte;
 598                 msg_bytes = 5;
 599                 reply_bytes = 1;
 600                 break;
 601         case MODE_I2C_READ:
 602                 msg[3] = 0;
 603                 msg_bytes = 4;
 604                 reply_bytes = 2;
 605                 break;
 606         default:
 607                 msg_bytes = 3;
 608                 reply_bytes = 1;
 609                 break;
 610         }
 611
 612         for (retry = 0; retry < 5; retry++) {
 613                 ret = intel_dp_aux_ch(intel_dp,
 614                                       msg, msg_bytes,
 615                                       reply, reply_bytes);
 616                 if (ret < 0) {
 617                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 618                         return ret;
 619                 }
 620
 621                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 622                 case AUX_NATIVE_REPLY_ACK:
 623                         /* I2C-over-AUX Reply field is only valid
 624                          * when paired with AUX ACK.
 625                          */
 626                         break;
 627                 case AUX_NATIVE_REPLY_NACK:
 628                         DRM_DEBUG_KMS("aux_ch native nack\n");
 629                         return -EREMOTEIO;
 630                 case AUX_NATIVE_REPLY_DEFER:
 631                         udelay(100);
 632                         continue;
 633                 default:
 634                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 635                                   reply[0]);
 636                         return -EREMOTEIO;
 637                 }
 638
 639                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 640                 case AUX_I2C_REPLY_ACK:
 641                         if (mode == MODE_I2C_READ) {
 642                                 *read_byte = reply[1];
 643                         }
 644                         return reply_bytes - 1;
 645                 case AUX_I2C_REPLY_NACK:
 646                         DRM_DEBUG_KMS("aux_i2c nack\n");
 647                         return -EREMOTEIO;
 648                 case AUX_I2C_REPLY_DEFER:
 649                         DRM_DEBUG_KMS("aux_i2c defer\n");
 650                         udelay(100);
 651                         break;
 652                 default:
 653                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 654                         return -EREMOTEIO;
 655                 }
 656         }
 657
 658         DRM_ERROR("too many retries, giving up\n");
 659         return -EREMOTEIO;
 660 }
 661
 662 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 663 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 664
 665 static int
 666 intel_dp_i2c_init(struct intel_dp *intel_dp,
 667                   struct intel_connector *intel_connector, const char *name)
 668 {
 669         int     ret;
 670
 671         DRM_DEBUG_KMS("i2c_init %s\n", name);
 672         intel_dp->algo.running = false;
 673         intel_dp->algo.address = 0;
 674         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 675
 676         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 677         intel_dp->adapter.owner = THIS_MODULE;
 678         intel_dp->adapter.class = I2C_CLASS_DDC;
 679         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 680         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 681         intel_dp->adapter.algo_data = &intel_dp->algo;
 682         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 683
 684         ironlake_edp_panel_vdd_on(intel_dp);
 685         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 686         ironlake_edp_panel_vdd_off(intel_dp, false);
 687         return ret;
 688 }
 689
 690 static bool
 691 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 692                     struct drm_display_mode *adjusted_mode)
 693 {
 694         struct drm_device *dev = encoder->dev;
 695         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 696         int lane_count, clock;
 697         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 698         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 699         int bpp, mode_rate;
 700         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 701
 702         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 703                 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 704                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 705                                         mode, adjusted_mode);
 706                 /*
 707                  * the mode->clock is used to calculate the Data&Link M/N
 708                  * of the pipe. For the eDP the fixed clock should be used.
 709                  */
 710                 mode->clock = intel_dp->panel_fixed_mode->clock;
 711         }
 712
 713         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 714                 return false;
 715
 716         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 717                       "max bw %02x pixel clock %iKHz\n",
 718                       max_lane_count, bws[max_clock], mode->clock);
 719
 720         if (!intel_dp_adjust_dithering(intel_dp, mode, adjusted_mode))
 721                 return false;
 722
 723         bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
 724         mode_rate = intel_dp_link_required(mode->clock, bpp);
 725
 726         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 727                 for (clock = 0; clock <= max_clock; clock++) {
 728                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 729
 730                         if (mode_rate <= link_avail) {
 731                                 intel_dp->link_bw = bws[clock];
 732                                 intel_dp->lane_count = lane_count;
 733                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 734                                 DRM_DEBUG_KMS("DP link bw %02x lane "
 735                                                 "count %d clock %d bpp %d\n",
 736                                        intel_dp->link_bw, intel_dp->lane_count,
 737                                        adjusted_mode->clock, bpp);
 738                                 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 739                                               mode_rate, link_avail);
 740                                 return true;
 741                         }
 742                 }
 743         }
 744
 745         return false;
 746 }
 747
 748 struct intel_dp_m_n {
 749         uint32_t        tu;
 750         uint32_t        gmch_m;
 751         uint32_t        gmch_n;
 752         uint32_t        link_m;
 753         uint32_t        link_n;
 754 };
 755
 756 static void
 757 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 758 {
 759         while (*num > 0xffffff || *den > 0xffffff) {
 760                 *num >>= 1;
 761                 *den >>= 1;
 762         }
 763 }
 764
 765 static void
 766 intel_dp_compute_m_n(int bpp,
 767                      int nlanes,
 768                      int pixel_clock,
 769                      int link_clock,
 770                      struct intel_dp_m_n *m_n)
 771 {
 772         m_n->tu = 64;
 773         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 774         m_n->gmch_n = link_clock * nlanes;
 775         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 776         m_n->link_m = pixel_clock;
 777         m_n->link_n = link_clock;
 778         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 779 }
 780
 781 void
 782 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 783                  struct drm_display_mode *adjusted_mode)
 784 {
 785         struct drm_device *dev = crtc->dev;
 786         struct drm_mode_config *mode_config = &dev->mode_config;
 787         struct drm_encoder *encoder;
 788         struct drm_i915_private *dev_priv = dev->dev_private;
 789         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 790         int lane_count = 4;
 791         struct intel_dp_m_n m_n;
 792         int pipe = intel_crtc->pipe;
 793
 794         /*
 795          * Find the lane count in the intel_encoder private
 796          */
 797         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 798                 struct intel_dp *intel_dp;
 799
 800                 if (encoder->crtc != crtc)
 801                         continue;
 802
 803                 intel_dp = enc_to_intel_dp(encoder);
 804                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
 805                     intel_dp->base.type == INTEL_OUTPUT_EDP)
 806                 {
 807                         lane_count = intel_dp->lane_count;
 808                         break;
 809                 }
 810         }
 811
 812         /*
 813          * Compute the GMCH and Link ratios. The '3' here is
 814          * the number of bytes_per_pixel post-LUT, which we always
 815          * set up for 8-bits of R/G/B, or 3 bytes total.
 816          */
 817         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 818                              mode->clock, adjusted_mode->clock, &m_n);
 819
 820         if (HAS_PCH_SPLIT(dev)) {
 821                 I915_WRITE(TRANSDATA_M1(pipe),
 822                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 823                            m_n.gmch_m);
 824                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 825                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 826                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 827         } else {
 828                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 829                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 830                            m_n.gmch_m);
 831                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 832                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 833                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 834         }
 835 }
 836
 837 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
 838 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
 839
 840 static void
 841 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 842                   struct drm_display_mode *adjusted_mode)
 843 {
 844         struct drm_device *dev = encoder->dev;
 845         struct drm_i915_private *dev_priv = dev->dev_private;
 846         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 847         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 849
 850         /* Turn on the eDP PLL if needed */
 851         if (is_edp(intel_dp)) {
 852                 if (!is_pch_edp(intel_dp))
 853                         ironlake_edp_pll_on(encoder);
 854                 else
 855                         ironlake_edp_pll_off(encoder);
 856         }
 857
 858         /*
 859          * There are four kinds of DP registers:
 860          *
 861          *      IBX PCH
 862          *      SNB CPU
 863          *      IVB CPU
 864          *      CPT PCH
 865          *
 866          * IBX PCH and CPU are the same for almost everything,
 867          * except that the CPU DP PLL is configured in this
 868          * register
 869          *
 870          * CPT PCH is quite different, having many bits moved
 871          * to the TRANS_DP_CTL register instead. That
 872          * configuration happens (oddly) in ironlake_pch_enable
 873          */
 874
 875         /* Preserve the BIOS-computed detected bit. This is
 876          * supposed to be read-only.
 877          */
 878         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 879         intel_dp->DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 880
 881         /* Handle DP bits in common between all three register formats */
 882
 883         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 884
 885         switch (intel_dp->lane_count) {
 886         case 1:
 887                 intel_dp->DP |= DP_PORT_WIDTH_1;
 888                 break;
 889         case 2:
 890                 intel_dp->DP |= DP_PORT_WIDTH_2;
 891                 break;
 892         case 4:
 893                 intel_dp->DP |= DP_PORT_WIDTH_4;
 894                 break;
 895         }
 896         if (intel_dp->has_audio) {
 897                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 898                                  pipe_name(intel_crtc->pipe));
 899                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 900                 intel_write_eld(encoder, adjusted_mode);
 901         }
 902         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 903         intel_dp->link_configuration[0] = intel_dp->link_bw;
 904         intel_dp->link_configuration[1] = intel_dp->lane_count;
 905         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 906         /*
 907          * Check for DPCD version > 1.1 and enhanced framing support
 908          */
 909         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 910             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 911                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 912         }
 913
 914         /* Split out the IBX/CPU vs CPT settings */
 915
 916         if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
 917                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 918                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 919                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 920                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 921                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 922
 923                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 924                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 925
 926                 intel_dp->DP |= intel_crtc->pipe << 29;
 927
 928                 /* don't miss out required setting for eDP */
 929                 intel_dp->DP |= DP_PLL_ENABLE;
 930                 if (adjusted_mode->clock < 200000)
 931                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 932                 else
 933                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 934         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 935                 intel_dp->DP |= intel_dp->color_range;
 936
 937                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 938                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 939                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 940                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 941                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 942
 943                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 944                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 945
 946                 if (intel_crtc->pipe == 1)
 947                         intel_dp->DP |= DP_PIPEB_SELECT;
 948
 949                 if (is_cpu_edp(intel_dp)) {
 950                         /* don't miss out required setting for eDP */
 951                         intel_dp->DP |= DP_PLL_ENABLE;
 952                         if (adjusted_mode->clock < 200000)
 953                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 954                         else
 955                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 956                 }
 957         } else {
 958                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 959         }
 960 }
 961
 962 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 963 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 964
 965 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 966 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 967
 968 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 969 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 970
 971 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 972                                        u32 mask,
 973                                        u32 value)
 974 {
 975         struct drm_device *dev = intel_dp->base.base.dev;
 976         struct drm_i915_private *dev_priv = dev->dev_private;
 977
 978         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 979                       mask, value,
 980                       I915_READ(PCH_PP_STATUS),
 981                       I915_READ(PCH_PP_CONTROL));
 982
 983         if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
 984                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 985                           I915_READ(PCH_PP_STATUS),
 986                           I915_READ(PCH_PP_CONTROL));
 987         }
 988 }
 989
 990 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 991 {
 992         DRM_DEBUG_KMS("Wait for panel power on\n");
 993         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 994 }
 995
 996 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 997 {
 998         DRM_DEBUG_KMS("Wait for panel power off time\n");
 999         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1000 }
1001
1002 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1003 {
1004         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1005         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1006 }
1007
1008
1009 /* Read the current pp_control value, unlocking the register if it
1010  * is locked
1011  */
1012
1013 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1014 {
1015         u32     control = I915_READ(PCH_PP_CONTROL);
1016
1017         control &= ~PANEL_UNLOCK_MASK;
1018         control |= PANEL_UNLOCK_REGS;
1019         return control;
1020 }
1021
1022 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1023 {
1024         struct drm_device *dev = intel_dp->base.base.dev;
1025         struct drm_i915_private *dev_priv = dev->dev_private;
1026         u32 pp;
1027
1028         if (!is_edp(intel_dp))
1029                 return;
1030         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1031
1032         WARN(intel_dp->want_panel_vdd,
1033              "eDP VDD already requested on\n");
1034
1035         intel_dp->want_panel_vdd = true;
1036
1037         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1038                 DRM_DEBUG_KMS("eDP VDD already on\n");
1039                 return;
1040         }
1041
1042         if (!ironlake_edp_have_panel_power(intel_dp))
1043                 ironlake_wait_panel_power_cycle(intel_dp);
1044
1045         pp = ironlake_get_pp_control(dev_priv);
1046         pp |= EDP_FORCE_VDD;
1047         I915_WRITE(PCH_PP_CONTROL, pp);
1048         POSTING_READ(PCH_PP_CONTROL);
1049         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1050                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1051
1052         /*
1053          * If the panel wasn't on, delay before accessing aux channel
1054          */
1055         if (!ironlake_edp_have_panel_power(intel_dp)) {
1056                 DRM_DEBUG_KMS("eDP was not running\n");
1057                 msleep(intel_dp->panel_power_up_delay);
1058         }
1059 }
1060
1061 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1062 {
1063         struct drm_device *dev = intel_dp->base.base.dev;
1064         struct drm_i915_private *dev_priv = dev->dev_private;
1065         u32 pp;
1066
1067         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1068                 pp = ironlake_get_pp_control(dev_priv);
1069                 pp &= ~EDP_FORCE_VDD;
1070                 I915_WRITE(PCH_PP_CONTROL, pp);
1071                 POSTING_READ(PCH_PP_CONTROL);
1072
1073                 /* Make sure sequencer is idle before allowing subsequent activity */
1074                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1075                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1076
1077                 msleep(intel_dp->panel_power_down_delay);
1078         }
1079 }
1080
1081 static void ironlake_panel_vdd_work(struct work_struct *__work)
1082 {
1083         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1084                                                  struct intel_dp, panel_vdd_work);
1085         struct drm_device *dev = intel_dp->base.base.dev;
1086
1087         mutex_lock(&dev->mode_config.mutex);
1088         ironlake_panel_vdd_off_sync(intel_dp);
1089         mutex_unlock(&dev->mode_config.mutex);
1090 }
1091
1092 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1093 {
1094         if (!is_edp(intel_dp))
1095                 return;
1096
1097         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1098         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1099
1100         intel_dp->want_panel_vdd = false;
1101
1102         if (sync) {
1103                 ironlake_panel_vdd_off_sync(intel_dp);
1104         } else {
1105                 /*
1106                  * Queue the timer to fire a long
1107                  * time from now (relative to the power down delay)
1108                  * to keep the panel power up across a sequence of operations
1109                  */
1110                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1111                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1112         }
1113 }
1114
1115 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1116 {
1117         struct drm_device *dev = intel_dp->base.base.dev;
1118         struct drm_i915_private *dev_priv = dev->dev_private;
1119         u32 pp;
1120
1121         if (!is_edp(intel_dp))
1122                 return;
1123
1124         DRM_DEBUG_KMS("Turn eDP power on\n");
1125
1126         if (ironlake_edp_have_panel_power(intel_dp)) {
1127                 DRM_DEBUG_KMS("eDP power already on\n");
1128                 return;
1129         }
1130
1131         ironlake_wait_panel_power_cycle(intel_dp);
1132
1133         pp = ironlake_get_pp_control(dev_priv);
1134         if (IS_GEN5(dev)) {
1135                 /* ILK workaround: disable reset around power sequence */
1136                 pp &= ~PANEL_POWER_RESET;
1137                 I915_WRITE(PCH_PP_CONTROL, pp);
1138                 POSTING_READ(PCH_PP_CONTROL);
1139         }
1140
1141         pp |= POWER_TARGET_ON;
1142         if (!IS_GEN5(dev))
1143                 pp |= PANEL_POWER_RESET;
1144
1145         I915_WRITE(PCH_PP_CONTROL, pp);
1146         POSTING_READ(PCH_PP_CONTROL);
1147
1148         ironlake_wait_panel_on(intel_dp);
1149
1150         if (IS_GEN5(dev)) {
1151                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1152                 I915_WRITE(PCH_PP_CONTROL, pp);
1153                 POSTING_READ(PCH_PP_CONTROL);
1154         }
1155 }
1156
1157 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1158 {
1159         struct drm_device *dev = intel_dp->base.base.dev;
1160         struct drm_i915_private *dev_priv = dev->dev_private;
1161         u32 pp;
1162
1163         if (!is_edp(intel_dp))
1164                 return;
1165
1166         DRM_DEBUG_KMS("Turn eDP power off\n");
1167
1168         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1169
1170         pp = ironlake_get_pp_control(dev_priv);
1171         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1172         I915_WRITE(PCH_PP_CONTROL, pp);
1173         POSTING_READ(PCH_PP_CONTROL);
1174
1175         ironlake_wait_panel_off(intel_dp);
1176 }
1177
1178 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1179 {
1180         struct drm_device *dev = intel_dp->base.base.dev;
1181         struct drm_i915_private *dev_priv = dev->dev_private;
1182         u32 pp;
1183
1184         if (!is_edp(intel_dp))
1185                 return;
1186
1187         DRM_DEBUG_KMS("\n");
1188         /*
1189          * If we enable the backlight right away following a panel power
1190          * on, we may see slight flicker as the panel syncs with the eDP
1191          * link.  So delay a bit to make sure the image is solid before
1192          * allowing it to appear.
1193          */
1194         msleep(intel_dp->backlight_on_delay);
1195         pp = ironlake_get_pp_control(dev_priv);
1196         pp |= EDP_BLC_ENABLE;
1197         I915_WRITE(PCH_PP_CONTROL, pp);
1198         POSTING_READ(PCH_PP_CONTROL);
1199 }
1200
1201 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1202 {
1203         struct drm_device *dev = intel_dp->base.base.dev;
1204         struct drm_i915_private *dev_priv = dev->dev_private;
1205         u32 pp;
1206
1207         if (!is_edp(intel_dp))
1208                 return;
1209
1210         DRM_DEBUG_KMS("\n");
1211         pp = ironlake_get_pp_control(dev_priv);
1212         pp &= ~EDP_BLC_ENABLE;
1213         I915_WRITE(PCH_PP_CONTROL, pp);
1214         POSTING_READ(PCH_PP_CONTROL);
1215         msleep(intel_dp->backlight_off_delay);
1216 }
1217
1218 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1219 {
1220         struct drm_device *dev = encoder->dev;
1221         struct drm_i915_private *dev_priv = dev->dev_private;
1222         u32 dpa_ctl;
1223
1224         DRM_DEBUG_KMS("\n");
1225         dpa_ctl = I915_READ(DP_A);
1226         dpa_ctl |= DP_PLL_ENABLE;
1227         I915_WRITE(DP_A, dpa_ctl);
1228         POSTING_READ(DP_A);
1229         udelay(200);
1230 }
1231
1232 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1233 {
1234         struct drm_device *dev = encoder->dev;
1235         struct drm_i915_private *dev_priv = dev->dev_private;
1236         u32 dpa_ctl;
1237
1238         dpa_ctl = I915_READ(DP_A);
1239         dpa_ctl &= ~DP_PLL_ENABLE;
1240         I915_WRITE(DP_A, dpa_ctl);
1241         POSTING_READ(DP_A);
1242         udelay(200);
1243 }
1244
1245 /* If the sink supports it, try to set the power state appropriately */
1246 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1247 {
1248         int ret, i;
1249
1250         /* Should have a valid DPCD by this point */
1251         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1252                 return;
1253
1254         if (mode != DRM_MODE_DPMS_ON) {
1255                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1256                                                   DP_SET_POWER_D3);
1257                 if (ret != 1)
1258                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1259         } else {
1260                 /*
1261                  * When turning on, we need to retry for 1ms to give the sink
1262                  * time to wake up.
1263                  */
1264                 for (i = 0; i < 3; i++) {
1265                         ret = intel_dp_aux_native_write_1(intel_dp,
1266                                                           DP_SET_POWER,
1267                                                           DP_SET_POWER_D0);
1268                         if (ret == 1)
1269                                 break;
1270                         msleep(1);
1271                 }
1272         }
1273 }
1274
1275 static void intel_dp_prepare(struct drm_encoder *encoder)
1276 {
1277         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1278
1279
1280         /* Make sure the panel is off before trying to change the mode. But also
1281          * ensure that we have vdd while we switch off the panel. */
1282         ironlake_edp_panel_vdd_on(intel_dp);
1283         ironlake_edp_backlight_off(intel_dp);
1284         ironlake_edp_panel_off(intel_dp);
1285
1286         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1287         intel_dp_link_down(intel_dp);
1288         ironlake_edp_panel_vdd_off(intel_dp, false);
1289 }
1290
1291 static void intel_dp_commit(struct drm_encoder *encoder)
1292 {
1293         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1294         struct drm_device *dev = encoder->dev;
1295         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1296
1297         ironlake_edp_panel_vdd_on(intel_dp);
1298         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1299         intel_dp_start_link_train(intel_dp);
1300         ironlake_edp_panel_on(intel_dp);
1301         ironlake_edp_panel_vdd_off(intel_dp, true);
1302         intel_dp_complete_link_train(intel_dp);
1303         ironlake_edp_backlight_on(intel_dp);
1304
1305         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1306
1307         if (HAS_PCH_CPT(dev))
1308                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1309 }
1310
1311 static void
1312 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1313 {
1314         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1315         struct drm_device *dev = encoder->dev;
1316         struct drm_i915_private *dev_priv = dev->dev_private;
1317         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1318
1319         if (mode != DRM_MODE_DPMS_ON) {
1320                 /* Switching the panel off requires vdd. */
1321                 ironlake_edp_panel_vdd_on(intel_dp);
1322                 ironlake_edp_backlight_off(intel_dp);
1323                 ironlake_edp_panel_off(intel_dp);
1324
1325                 intel_dp_sink_dpms(intel_dp, mode);
1326                 intel_dp_link_down(intel_dp);
1327                 ironlake_edp_panel_vdd_off(intel_dp, false);
1328
1329                 if (is_cpu_edp(intel_dp))
1330                         ironlake_edp_pll_off(encoder);
1331         } else {
1332                 if (is_cpu_edp(intel_dp))
1333                         ironlake_edp_pll_on(encoder);
1334
1335                 ironlake_edp_panel_vdd_on(intel_dp);
1336                 intel_dp_sink_dpms(intel_dp, mode);
1337                 if (!(dp_reg & DP_PORT_EN)) {
1338                         intel_dp_start_link_train(intel_dp);
1339                         ironlake_edp_panel_on(intel_dp);
1340                         ironlake_edp_panel_vdd_off(intel_dp, true);
1341                         intel_dp_complete_link_train(intel_dp);
1342                 } else
1343                         ironlake_edp_panel_vdd_off(intel_dp, false);
1344                 ironlake_edp_backlight_on(intel_dp);
1345         }
1346         intel_dp->dpms_mode = mode;
1347 }
1348
1349 /*
1350  * Native read with retry for link status and receiver capability reads for
1351  * cases where the sink may still be asleep.
1352  */
1353 static bool
1354 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1355                                uint8_t *recv, int recv_bytes)
1356 {
1357         int ret, i;
1358
1359         /*
1360          * Sinks are *supposed* to come up within 1ms from an off state,
1361          * but we're also supposed to retry 3 times per the spec.
1362          */
1363         for (i = 0; i < 3; i++) {
1364                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1365                                                recv_bytes);
1366                 if (ret == recv_bytes)
1367                         return true;
1368                 msleep(1);
1369         }
1370
1371         return false;
1372 }
1373
1374 /*
1375  * Fetch AUX CH registers 0x202 - 0x207 which contain
1376  * link status information
1377  */
1378 static bool
1379 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1380 {
1381         return intel_dp_aux_native_read_retry(intel_dp,
1382                                               DP_LANE0_1_STATUS,
1383                                               link_status,
1384                                               DP_LINK_STATUS_SIZE);
1385 }
1386
1387 static uint8_t
1388 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1389                      int r)
1390 {
1391         return link_status[r - DP_LANE0_1_STATUS];
1392 }
1393
1394 static uint8_t
1395 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1396                                  int lane)
1397 {
1398         int         s = ((lane & 1) ?
1399                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1400                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1401         uint8_t l = adjust_request[lane>>1];
1402
1403         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1404 }
1405
1406 static uint8_t
1407 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1408                                       int lane)
1409 {
1410         int         s = ((lane & 1) ?
1411                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1412                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1413         uint8_t l = adjust_request[lane>>1];
1414
1415         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1416 }
1417
1418
1419 #if 0
1420 static char     *voltage_names[] = {
1421         "0.4V", "0.6V", "0.8V", "1.2V"
1422 };
1423 static char     *pre_emph_names[] = {
1424         "0dB", "3.5dB", "6dB", "9.5dB"
1425 };
1426 static char     *link_train_names[] = {
1427         "pattern 1", "pattern 2", "idle", "off"
1428 };
1429 #endif
1430
1431 /*
1432  * These are source-specific values; current Intel hardware supports
1433  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1434  */
1435
1436 static uint8_t
1437 intel_dp_voltage_max(struct intel_dp *intel_dp)
1438 {
1439         struct drm_device *dev = intel_dp->base.base.dev;
1440
1441         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1442                 return DP_TRAIN_VOLTAGE_SWING_800;
1443         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1444                 return DP_TRAIN_VOLTAGE_SWING_1200;
1445         else
1446                 return DP_TRAIN_VOLTAGE_SWING_800;
1447 }
1448
1449 static uint8_t
1450 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1451 {
1452         struct drm_device *dev = intel_dp->base.base.dev;
1453
1454         if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1455                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1456                 case DP_TRAIN_VOLTAGE_SWING_400:
1457                         return DP_TRAIN_PRE_EMPHASIS_6;
1458                 case DP_TRAIN_VOLTAGE_SWING_600:
1459                 case DP_TRAIN_VOLTAGE_SWING_800:
1460                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1461                 default:
1462                         return DP_TRAIN_PRE_EMPHASIS_0;
1463                 }
1464         } else {
1465                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1466                 case DP_TRAIN_VOLTAGE_SWING_400:
1467                         return DP_TRAIN_PRE_EMPHASIS_6;
1468                 case DP_TRAIN_VOLTAGE_SWING_600:
1469                         return DP_TRAIN_PRE_EMPHASIS_6;
1470                 case DP_TRAIN_VOLTAGE_SWING_800:
1471                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1472                 case DP_TRAIN_VOLTAGE_SWING_1200:
1473                 default:
1474                         return DP_TRAIN_PRE_EMPHASIS_0;
1475                 }
1476         }
1477 }
1478
1479 static void
1480 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1481 {
1482         uint8_t v = 0;
1483         uint8_t p = 0;
1484         int lane;
1485         uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1486         uint8_t voltage_max;
1487         uint8_t preemph_max;
1488
1489         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1490                 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1491                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1492
1493                 if (this_v > v)
1494                         v = this_v;
1495                 if (this_p > p)
1496                         p = this_p;
1497         }
1498
1499         voltage_max = intel_dp_voltage_max(intel_dp);
1500         if (v >= voltage_max)
1501                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1502
1503         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1504         if (p >= preemph_max)
1505                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1506
1507         for (lane = 0; lane < 4; lane++)
1508                 intel_dp->train_set[lane] = v | p;
1509 }
1510
1511 static uint32_t
1512 intel_dp_signal_levels(uint8_t train_set)
1513 {
1514         uint32_t        signal_levels = 0;
1515
1516         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1517         case DP_TRAIN_VOLTAGE_SWING_400:
1518         default:
1519                 signal_levels |= DP_VOLTAGE_0_4;
1520                 break;
1521         case DP_TRAIN_VOLTAGE_SWING_600:
1522                 signal_levels |= DP_VOLTAGE_0_6;
1523                 break;
1524         case DP_TRAIN_VOLTAGE_SWING_800:
1525                 signal_levels |= DP_VOLTAGE_0_8;
1526                 break;
1527         case DP_TRAIN_VOLTAGE_SWING_1200:
1528                 signal_levels |= DP_VOLTAGE_1_2;
1529                 break;
1530         }
1531         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1532         case DP_TRAIN_PRE_EMPHASIS_0:
1533         default:
1534                 signal_levels |= DP_PRE_EMPHASIS_0;
1535                 break;
1536         case DP_TRAIN_PRE_EMPHASIS_3_5:
1537                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1538                 break;
1539         case DP_TRAIN_PRE_EMPHASIS_6:
1540                 signal_levels |= DP_PRE_EMPHASIS_6;
1541                 break;
1542         case DP_TRAIN_PRE_EMPHASIS_9_5:
1543                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1544                 break;
1545         }
1546         return signal_levels;
1547 }
1548
1549 /* Gen6's DP voltage swing and pre-emphasis control */
1550 static uint32_t
1551 intel_gen6_edp_signal_levels(uint8_t train_set)
1552 {
1553         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1554                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1555         switch (signal_levels) {
1556         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1557         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1558                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1559         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1560                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1561         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1562         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1563                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1564         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1565         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1566                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1567         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1568         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1569                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1570         default:
1571                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1572                               "0x%x\n", signal_levels);
1573                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1574         }
1575 }
1576
1577 /* Gen7's DP voltage swing and pre-emphasis control */
1578 static uint32_t
1579 intel_gen7_edp_signal_levels(uint8_t train_set)
1580 {
1581         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1582                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1583         switch (signal_levels) {
1584         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1585                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1586         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1587                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1588         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1589                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1590
1591         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1592                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1593         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1594                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1595
1596         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1597                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1598         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1599                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1600
1601         default:
1602                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1603                               "0x%x\n", signal_levels);
1604                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1605         }
1606 }
1607
1608 static uint8_t
1609 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1610                       int lane)
1611 {
1612         int s = (lane & 1) * 4;
1613         uint8_t l = link_status[lane>>1];
1614
1615         return (l >> s) & 0xf;
1616 }
1617
1618 /* Check for clock recovery is done on all channels */
1619 static bool
1620 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1621 {
1622         int lane;
1623         uint8_t lane_status;
1624
1625         for (lane = 0; lane < lane_count; lane++) {
1626                 lane_status = intel_get_lane_status(link_status, lane);
1627                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1628                         return false;
1629         }
1630         return true;
1631 }
1632
1633 /* Check to see if channel eq is done on all channels */
1634 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1635                          DP_LANE_CHANNEL_EQ_DONE|\
1636                          DP_LANE_SYMBOL_LOCKED)
1637 static bool
1638 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1639 {
1640         uint8_t lane_align;
1641         uint8_t lane_status;
1642         int lane;
1643
1644         lane_align = intel_dp_link_status(link_status,
1645                                           DP_LANE_ALIGN_STATUS_UPDATED);
1646         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1647                 return false;
1648         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1649                 lane_status = intel_get_lane_status(link_status, lane);
1650                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1651                         return false;
1652         }
1653         return true;
1654 }
1655
1656 static bool
1657 intel_dp_set_link_train(struct intel_dp *intel_dp,
1658                         uint32_t dp_reg_value,
1659                         uint8_t dp_train_pat)
1660 {
1661         struct drm_device *dev = intel_dp->base.base.dev;
1662         struct drm_i915_private *dev_priv = dev->dev_private;
1663         int ret;
1664
1665         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1666         POSTING_READ(intel_dp->output_reg);
1667
1668         intel_dp_aux_native_write_1(intel_dp,
1669                                     DP_TRAINING_PATTERN_SET,
1670                                     dp_train_pat);
1671
1672         ret = intel_dp_aux_native_write(intel_dp,
1673                                         DP_TRAINING_LANE0_SET,
1674                                         intel_dp->train_set,
1675                                         intel_dp->lane_count);
1676         if (ret != intel_dp->lane_count)
1677                 return false;
1678
1679         return true;
1680 }
1681
1682 /* Enable corresponding port and start training pattern 1 */
1683 static void
1684 intel_dp_start_link_train(struct intel_dp *intel_dp)
1685 {
1686         struct drm_device *dev = intel_dp->base.base.dev;
1687         struct drm_i915_private *dev_priv = dev->dev_private;
1688         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1689         int i;
1690         uint8_t voltage;
1691         bool clock_recovery = false;
1692         int voltage_tries, loop_tries;
1693         u32 reg;
1694         uint32_t DP = intel_dp->DP;
1695
1696         /*
1697          * On CPT we have to enable the port in training pattern 1, which
1698          * will happen below in intel_dp_set_link_train.  Otherwise, enable
1699          * the port and wait for it to become active.
1700          */
1701         if (!HAS_PCH_CPT(dev)) {
1702                 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1703                 POSTING_READ(intel_dp->output_reg);
1704                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1705         }
1706
1707         /* Write the link configuration data */
1708         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1709                                   intel_dp->link_configuration,
1710                                   DP_LINK_CONFIGURATION_SIZE);
1711
1712         DP |= DP_PORT_EN;
1713
1714         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1715                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1716         else
1717                 DP &= ~DP_LINK_TRAIN_MASK;
1718         memset(intel_dp->train_set, 0, 4);
1719         voltage = 0xff;
1720         voltage_tries = 0;
1721         loop_tries = 0;
1722         clock_recovery = false;
1723         for (;;) {
1724                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1725                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1726                 uint32_t    signal_levels;
1727
1728
1729                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1730                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1731                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1732                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1733                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1734                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1735                 } else {
1736                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1737                         DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1738                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1739                 }
1740
1741                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1742                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1743                 else
1744                         reg = DP | DP_LINK_TRAIN_PAT_1;
1745
1746                 if (!intel_dp_set_link_train(intel_dp, reg,
1747                                              DP_TRAINING_PATTERN_1 |
1748                                              DP_LINK_SCRAMBLING_DISABLE))
1749                         break;
1750                 /* Set training pattern 1 */
1751
1752                 udelay(100);
1753                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1754                         DRM_ERROR("failed to get link status\n");
1755                         break;
1756                 }
1757
1758                 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1759                         DRM_DEBUG_KMS("clock recovery OK\n");
1760                         clock_recovery = true;
1761                         break;
1762                 }
1763
1764                 /* Check to see if we've tried the max voltage */
1765                 for (i = 0; i < intel_dp->lane_count; i++)
1766                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1767                                 break;
1768                 if (i == intel_dp->lane_count) {
1769                         ++loop_tries;
1770                         if (loop_tries == 5) {
1771                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1772                                 break;
1773                         }
1774                         memset(intel_dp->train_set, 0, 4);
1775                         voltage_tries = 0;
1776                         continue;
1777                 }
1778
1779                 /* Check to see if we've tried the same voltage 5 times */
1780                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1781                         ++voltage_tries;
1782                         if (voltage_tries == 5) {
1783                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1784                                 break;
1785                         }
1786                 } else
1787                         voltage_tries = 0;
1788                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1789
1790                 /* Compute new intel_dp->train_set as requested by target */
1791                 intel_get_adjust_train(intel_dp, link_status);
1792         }
1793
1794         intel_dp->DP = DP;
1795 }
1796
1797 static void
1798 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1799 {
1800         struct drm_device *dev = intel_dp->base.base.dev;
1801         struct drm_i915_private *dev_priv = dev->dev_private;
1802         bool channel_eq = false;
1803         int tries, cr_tries;
1804         u32 reg;
1805         uint32_t DP = intel_dp->DP;
1806
1807         /* channel equalization */
1808         tries = 0;
1809         cr_tries = 0;
1810         channel_eq = false;
1811         for (;;) {
1812                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1813                 uint32_t    signal_levels;
1814                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1815
1816                 if (cr_tries > 5) {
1817                         DRM_ERROR("failed to train DP, aborting\n");
1818                         intel_dp_link_down(intel_dp);
1819                         break;
1820                 }
1821
1822                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1823                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1824                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1825                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1826                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1827                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1828                 } else {
1829                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1830                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1831                 }
1832
1833                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1834                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1835                 else
1836                         reg = DP | DP_LINK_TRAIN_PAT_2;
1837
1838                 /* channel eq pattern */
1839                 if (!intel_dp_set_link_train(intel_dp, reg,
1840                                              DP_TRAINING_PATTERN_2 |
1841                                              DP_LINK_SCRAMBLING_DISABLE))
1842                         break;
1843
1844                 udelay(400);
1845                 if (!intel_dp_get_link_status(intel_dp, link_status))
1846                         break;
1847
1848                 /* Make sure clock is still ok */
1849                 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1850                         intel_dp_start_link_train(intel_dp);
1851                         cr_tries++;
1852                         continue;
1853                 }
1854
1855                 if (intel_channel_eq_ok(intel_dp, link_status)) {
1856                         channel_eq = true;
1857                         break;
1858                 }
1859
1860                 /* Try 5 times, then try clock recovery if that fails */
1861                 if (tries > 5) {
1862                         intel_dp_link_down(intel_dp);
1863                         intel_dp_start_link_train(intel_dp);
1864                         tries = 0;
1865                         cr_tries++;
1866                         continue;
1867                 }
1868
1869                 /* Compute new intel_dp->train_set as requested by target */
1870                 intel_get_adjust_train(intel_dp, link_status);
1871                 ++tries;
1872         }
1873
1874         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1875                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1876         else
1877                 reg = DP | DP_LINK_TRAIN_OFF;
1878
1879         I915_WRITE(intel_dp->output_reg, reg);
1880         POSTING_READ(intel_dp->output_reg);
1881         intel_dp_aux_native_write_1(intel_dp,
1882                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1883 }
1884
1885 static void
1886 intel_dp_link_down(struct intel_dp *intel_dp)
1887 {
1888         struct drm_device *dev = intel_dp->base.base.dev;
1889         struct drm_i915_private *dev_priv = dev->dev_private;
1890         uint32_t DP = intel_dp->DP;
1891
1892         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1893                 return;
1894
1895         DRM_DEBUG_KMS("\n");
1896
1897         if (is_edp(intel_dp)) {
1898                 DP &= ~DP_PLL_ENABLE;
1899                 I915_WRITE(intel_dp->output_reg, DP);
1900                 POSTING_READ(intel_dp->output_reg);
1901                 udelay(100);
1902         }
1903
1904         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1905                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1906                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1907         } else {
1908                 DP &= ~DP_LINK_TRAIN_MASK;
1909                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1910         }
1911         POSTING_READ(intel_dp->output_reg);
1912
1913         msleep(17);
1914
1915         if (is_edp(intel_dp)) {
1916                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1917                         DP |= DP_LINK_TRAIN_OFF_CPT;
1918                 else
1919                         DP |= DP_LINK_TRAIN_OFF;
1920         }
1921
1922         if (!HAS_PCH_CPT(dev) &&
1923             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1924                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1925
1926                 /* Hardware workaround: leaving our transcoder select
1927                  * set to transcoder B while it's off will prevent the
1928                  * corresponding HDMI output on transcoder A.
1929                  *
1930                  * Combine this with another hardware workaround:
1931                  * transcoder select bit can only be cleared while the
1932                  * port is enabled.
1933                  */
1934                 DP &= ~DP_PIPEB_SELECT;
1935                 I915_WRITE(intel_dp->output_reg, DP);
1936
1937                 /* Changes to enable or select take place the vblank
1938                  * after being written.
1939                  */
1940                 if (crtc == NULL) {
1941                         /* We can arrive here never having been attached
1942                          * to a CRTC, for instance, due to inheriting
1943                          * random state from the BIOS.
1944                          *
1945                          * If the pipe is not running, play safe and
1946                          * wait for the clocks to stabilise before
1947                          * continuing.
1948                          */
1949                         POSTING_READ(intel_dp->output_reg);
1950                         msleep(50);
1951                 } else
1952                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1953         }
1954
1955         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
1956         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1957         POSTING_READ(intel_dp->output_reg);
1958         msleep(intel_dp->panel_power_down_delay);
1959 }
1960
1961 static bool
1962 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1963 {
1964         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1965                                            sizeof(intel_dp->dpcd)) &&
1966             (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1967                 return true;
1968         }
1969
1970         return false;
1971 }
1972
1973 static void
1974 intel_dp_probe_oui(struct intel_dp *intel_dp)
1975 {
1976         u8 buf[3];
1977
1978         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
1979                 return;
1980
1981         ironlake_edp_panel_vdd_on(intel_dp);
1982
1983         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
1984                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
1985                               buf[0], buf[1], buf[2]);
1986
1987         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
1988                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
1989                               buf[0], buf[1], buf[2]);
1990
1991         ironlake_edp_panel_vdd_off(intel_dp, false);
1992 }
1993
1994 static bool
1995 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1996 {
1997         int ret;
1998
1999         ret = intel_dp_aux_native_read_retry(intel_dp,
2000                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2001                                              sink_irq_vector, 1);
2002         if (!ret)
2003                 return false;
2004
2005         return true;
2006 }
2007
2008 static void
2009 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2010 {
2011         /* NAK by default */
2012         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2013 }
2014
2015 /*
2016  * According to DP spec
2017  * 5.1.2:
2018  *  1. Read DPCD
2019  *  2. Configure link according to Receiver Capabilities
2020  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2021  *  4. Check link status on receipt of hot-plug interrupt
2022  */
2023
2024 static void
2025 intel_dp_check_link_status(struct intel_dp *intel_dp)
2026 {
2027         u8 sink_irq_vector;
2028         u8 link_status[DP_LINK_STATUS_SIZE];
2029
2030         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
2031                 return;
2032
2033         if (!intel_dp->base.base.crtc)
2034                 return;
2035
2036         /* Try to read receiver status if the link appears to be up */
2037         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2038                 intel_dp_link_down(intel_dp);
2039                 return;
2040         }
2041
2042         /* Now read the DPCD to see if it's actually running */
2043         if (!intel_dp_get_dpcd(intel_dp)) {
2044                 intel_dp_link_down(intel_dp);
2045                 return;
2046         }
2047
2048         /* Try to read the source of the interrupt */
2049         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2050             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2051                 /* Clear interrupt source */
2052                 intel_dp_aux_native_write_1(intel_dp,
2053                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2054                                             sink_irq_vector);
2055
2056                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2057                         intel_dp_handle_test_request(intel_dp);
2058                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2059                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2060         }
2061
2062         if (!intel_channel_eq_ok(intel_dp, link_status)) {
2063                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2064                               drm_get_encoder_name(&intel_dp->base.base));
2065                 intel_dp_start_link_train(intel_dp);
2066                 intel_dp_complete_link_train(intel_dp);
2067         }
2068 }
2069
2070 static enum drm_connector_status
2071 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2072 {
2073         if (intel_dp_get_dpcd(intel_dp))
2074                 return connector_status_connected;
2075         return connector_status_disconnected;
2076 }
2077
2078 static enum drm_connector_status
2079 ironlake_dp_detect(struct intel_dp *intel_dp)
2080 {
2081         enum drm_connector_status status;
2082
2083         /* Can't disconnect eDP, but you can close the lid... */
2084         if (is_edp(intel_dp)) {
2085                 status = intel_panel_detect(intel_dp->base.base.dev);
2086                 if (status == connector_status_unknown)
2087                         status = connector_status_connected;
2088                 return status;
2089         }
2090
2091         return intel_dp_detect_dpcd(intel_dp);
2092 }
2093
2094 static enum drm_connector_status
2095 g4x_dp_detect(struct intel_dp *intel_dp)
2096 {
2097         struct drm_device *dev = intel_dp->base.base.dev;
2098         struct drm_i915_private *dev_priv = dev->dev_private;
2099         uint32_t temp, bit;
2100
2101         switch (intel_dp->output_reg) {
2102         case DP_B:
2103                 bit = DPB_HOTPLUG_INT_STATUS;
2104                 break;
2105         case DP_C:
2106                 bit = DPC_HOTPLUG_INT_STATUS;
2107                 break;
2108         case DP_D:
2109                 bit = DPD_HOTPLUG_INT_STATUS;
2110                 break;
2111         default:
2112                 return connector_status_unknown;
2113         }
2114
2115         temp = I915_READ(PORT_HOTPLUG_STAT);
2116
2117         if ((temp & bit) == 0)
2118                 return connector_status_disconnected;
2119
2120         return intel_dp_detect_dpcd(intel_dp);
2121 }
2122
2123 static struct edid *
2124 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2125 {
2126         struct intel_dp *intel_dp = intel_attached_dp(connector);
2127         struct edid     *edid;
2128
2129         ironlake_edp_panel_vdd_on(intel_dp);
2130         edid = drm_get_edid(connector, adapter);
2131         ironlake_edp_panel_vdd_off(intel_dp, false);
2132         return edid;
2133 }
2134
2135 static int
2136 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2137 {
2138         struct intel_dp *intel_dp = intel_attached_dp(connector);
2139         int     ret;
2140
2141         ironlake_edp_panel_vdd_on(intel_dp);
2142         ret = intel_ddc_get_modes(connector, adapter);
2143         ironlake_edp_panel_vdd_off(intel_dp, false);
2144         return ret;
2145 }
2146
2147
2148 /**
2149  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2150  *
2151  * \return true if DP port is connected.
2152  * \return false if DP port is disconnected.
2153  */
2154 static enum drm_connector_status
2155 intel_dp_detect(struct drm_connector *connector, bool force)
2156 {
2157         struct intel_dp *intel_dp = intel_attached_dp(connector);
2158         struct drm_device *dev = intel_dp->base.base.dev;
2159         enum drm_connector_status status;
2160         struct edid *edid = NULL;
2161
2162         intel_dp->has_audio = false;
2163
2164         if (HAS_PCH_SPLIT(dev))
2165                 status = ironlake_dp_detect(intel_dp);
2166         else
2167                 status = g4x_dp_detect(intel_dp);
2168
2169         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2170                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2171                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2172                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
2173
2174         if (status != connector_status_connected)
2175                 return status;
2176
2177         intel_dp_probe_oui(intel_dp);
2178
2179         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2180                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2181         } else {
2182                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2183                 if (edid) {
2184                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2185                         connector->display_info.raw_edid = NULL;
2186                         kfree(edid);
2187                 }
2188         }
2189
2190         return connector_status_connected;
2191 }
2192
2193 static int intel_dp_get_modes(struct drm_connector *connector)
2194 {
2195         struct intel_dp *intel_dp = intel_attached_dp(connector);
2196         struct drm_device *dev = intel_dp->base.base.dev;
2197         struct drm_i915_private *dev_priv = dev->dev_private;
2198         int ret;
2199
2200         /* We should parse the EDID data and find out if it has an audio sink
2201          */
2202
2203         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2204         if (ret) {
2205                 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2206                         struct drm_display_mode *newmode;
2207                         list_for_each_entry(newmode, &connector->probed_modes,
2208                                             head) {
2209                                 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2210                                         intel_dp->panel_fixed_mode =
2211                                                 drm_mode_duplicate(dev, newmode);
2212                                         break;
2213                                 }
2214                         }
2215                 }
2216                 return ret;
2217         }
2218
2219         /* if eDP has no EDID, try to use fixed panel mode from VBT */
2220         if (is_edp(intel_dp)) {
2221                 /* initialize panel mode from VBT if available for eDP */
2222                 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2223                         intel_dp->panel_fixed_mode =
2224                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2225                         if (intel_dp->panel_fixed_mode) {
2226                                 intel_dp->panel_fixed_mode->type |=
2227                                         DRM_MODE_TYPE_PREFERRED;
2228                         }
2229                 }
2230                 if (intel_dp->panel_fixed_mode) {
2231                         struct drm_display_mode *mode;
2232                         mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2233                         drm_mode_probed_add(connector, mode);
2234                         return 1;
2235                 }
2236         }
2237         return 0;
2238 }
2239
2240 static bool
2241 intel_dp_detect_audio(struct drm_connector *connector)
2242 {
2243         struct intel_dp *intel_dp = intel_attached_dp(connector);
2244         struct edid *edid;
2245         bool has_audio = false;
2246
2247         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2248         if (edid) {
2249                 has_audio = drm_detect_monitor_audio(edid);
2250
2251                 connector->display_info.raw_edid = NULL;
2252                 kfree(edid);
2253         }
2254
2255         return has_audio;
2256 }
2257
2258 static int
2259 intel_dp_set_property(struct drm_connector *connector,
2260                       struct drm_property *property,
2261                       uint64_t val)
2262 {
2263         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2264         struct intel_dp *intel_dp = intel_attached_dp(connector);
2265         int ret;
2266
2267         ret = drm_connector_property_set_value(connector, property, val);
2268         if (ret)
2269                 return ret;
2270
2271         if (property == dev_priv->force_audio_property) {
2272                 int i = val;
2273                 bool has_audio;
2274
2275                 if (i == intel_dp->force_audio)
2276                         return 0;
2277
2278                 intel_dp->force_audio = i;
2279
2280                 if (i == HDMI_AUDIO_AUTO)
2281                         has_audio = intel_dp_detect_audio(connector);
2282                 else
2283                         has_audio = (i == HDMI_AUDIO_ON);
2284
2285                 if (has_audio == intel_dp->has_audio)
2286                         return 0;
2287
2288                 intel_dp->has_audio = has_audio;
2289                 goto done;
2290         }
2291
2292         if (property == dev_priv->broadcast_rgb_property) {
2293                 if (val == !!intel_dp->color_range)
2294                         return 0;
2295
2296                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2297                 goto done;
2298         }
2299
2300         return -EINVAL;
2301
2302 done:
2303         if (intel_dp->base.base.crtc) {
2304                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2305                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2306                                          crtc->x, crtc->y,
2307                                          crtc->fb);
2308         }
2309
2310         return 0;
2311 }
2312
2313 static void
2314 intel_dp_destroy(struct drm_connector *connector)
2315 {
2316         struct drm_device *dev = connector->dev;
2317
2318         if (intel_dpd_is_edp(dev))
2319                 intel_panel_destroy_backlight(dev);
2320
2321         drm_sysfs_connector_remove(connector);
2322         drm_connector_cleanup(connector);
2323         kfree(connector);
2324 }
2325
2326 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2327 {
2328         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2329
2330         i2c_del_adapter(&intel_dp->adapter);
2331         drm_encoder_cleanup(encoder);
2332         if (is_edp(intel_dp)) {
2333                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2334                 ironlake_panel_vdd_off_sync(intel_dp);
2335         }
2336         kfree(intel_dp);
2337 }
2338
2339 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2340         .dpms = intel_dp_dpms,
2341         .mode_fixup = intel_dp_mode_fixup,
2342         .prepare = intel_dp_prepare,
2343         .mode_set = intel_dp_mode_set,
2344         .commit = intel_dp_commit,
2345 };
2346
2347 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2348         .dpms = drm_helper_connector_dpms,
2349         .detect = intel_dp_detect,
2350         .fill_modes = drm_helper_probe_single_connector_modes,
2351         .set_property = intel_dp_set_property,
2352         .destroy = intel_dp_destroy,
2353 };
2354
2355 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2356         .get_modes = intel_dp_get_modes,
2357         .mode_valid = intel_dp_mode_valid,
2358         .best_encoder = intel_best_encoder,
2359 };
2360
2361 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2362         .destroy = intel_dp_encoder_destroy,
2363 };
2364
2365 static void
2366 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2367 {
2368         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2369
2370         intel_dp_check_link_status(intel_dp);
2371 }
2372
2373 /* Return which DP Port should be selected for Transcoder DP control */
2374 int
2375 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2376 {
2377         struct drm_device *dev = crtc->dev;
2378         struct drm_mode_config *mode_config = &dev->mode_config;
2379         struct drm_encoder *encoder;
2380
2381         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2382                 struct intel_dp *intel_dp;
2383
2384                 if (encoder->crtc != crtc)
2385                         continue;
2386
2387                 intel_dp = enc_to_intel_dp(encoder);
2388                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2389                     intel_dp->base.type == INTEL_OUTPUT_EDP)
2390                         return intel_dp->output_reg;
2391         }
2392
2393         return -1;
2394 }
2395
2396 /* check the VBT to see whether the eDP is on DP-D port */
2397 bool intel_dpd_is_edp(struct drm_device *dev)
2398 {
2399         struct drm_i915_private *dev_priv = dev->dev_private;
2400         struct child_device_config *p_child;
2401         int i;
2402
2403         if (!dev_priv->child_dev_num)
2404                 return false;
2405
2406         for (i = 0; i < dev_priv->child_dev_num; i++) {
2407                 p_child = dev_priv->child_dev + i;
2408
2409                 if (p_child->dvo_port == PORT_IDPD &&
2410                     p_child->device_type == DEVICE_TYPE_eDP)
2411                         return true;
2412         }
2413         return false;
2414 }
2415
2416 static void
2417 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2418 {
2419         intel_attach_force_audio_property(connector);
2420         intel_attach_broadcast_rgb_property(connector);
2421 }
2422
2423 void
2424 intel_dp_init(struct drm_device *dev, int output_reg)
2425 {
2426         struct drm_i915_private *dev_priv = dev->dev_private;
2427         struct drm_connector *connector;
2428         struct intel_dp *intel_dp;
2429         struct intel_encoder *intel_encoder;
2430         struct intel_connector *intel_connector;
2431         const char *name = NULL;
2432         int type;
2433
2434         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2435         if (!intel_dp)
2436                 return;
2437
2438         intel_dp->output_reg = output_reg;
2439         intel_dp->dpms_mode = -1;
2440
2441         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2442         if (!intel_connector) {
2443                 kfree(intel_dp);
2444                 return;
2445         }
2446         intel_encoder = &intel_dp->base;
2447
2448         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2449                 if (intel_dpd_is_edp(dev))
2450                         intel_dp->is_pch_edp = true;
2451
2452         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2453                 type = DRM_MODE_CONNECTOR_eDP;
2454                 intel_encoder->type = INTEL_OUTPUT_EDP;
2455         } else {
2456                 type = DRM_MODE_CONNECTOR_DisplayPort;
2457                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2458         }
2459
2460         connector = &intel_connector->base;
2461         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2462         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2463
2464         connector->polled = DRM_CONNECTOR_POLL_HPD;
2465
2466         if (output_reg == DP_B || output_reg == PCH_DP_B)
2467                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2468         else if (output_reg == DP_C || output_reg == PCH_DP_C)
2469                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2470         else if (output_reg == DP_D || output_reg == PCH_DP_D)
2471                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2472
2473         if (is_edp(intel_dp)) {
2474                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2475                 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2476                                   ironlake_panel_vdd_work);
2477         }
2478
2479         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2480
2481         connector->interlace_allowed = true;
2482         connector->doublescan_allowed = 0;
2483
2484         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2485                          DRM_MODE_ENCODER_TMDS);
2486         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2487
2488         intel_connector_attach_encoder(intel_connector, intel_encoder);
2489         drm_sysfs_connector_add(connector);
2490
2491         /* Set up the DDC bus. */
2492         switch (output_reg) {
2493                 case DP_A:
2494                         name = "DPDDC-A";
2495                         break;
2496                 case DP_B:
2497                 case PCH_DP_B:
2498                         dev_priv->hotplug_supported_mask |=
2499                                 HDMIB_HOTPLUG_INT_STATUS;
2500                         name = "DPDDC-B";
2501                         break;
2502                 case DP_C:
2503                 case PCH_DP_C:
2504                         dev_priv->hotplug_supported_mask |=
2505                                 HDMIC_HOTPLUG_INT_STATUS;
2506                         name = "DPDDC-C";
2507                         break;
2508                 case DP_D:
2509                 case PCH_DP_D:
2510                         dev_priv->hotplug_supported_mask |=
2511                                 HDMID_HOTPLUG_INT_STATUS;
2512                         name = "DPDDC-D";
2513                         break;
2514         }
2515
2516         /* Cache some DPCD data in the eDP case */
2517         if (is_edp(intel_dp)) {
2518                 bool ret;
2519                 struct edp_power_seq    cur, vbt;
2520                 u32 pp_on, pp_off, pp_div;
2521
2522                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2523                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2524                 pp_div = I915_READ(PCH_PP_DIVISOR);
2525
2526                 if (!pp_on || !pp_off || !pp_div) {
2527                         DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2528                         intel_dp_encoder_destroy(&intel_dp->base.base);
2529                         intel_dp_destroy(&intel_connector->base);
2530                         return;
2531                 }
2532
2533                 /* Pull timing values out of registers */
2534                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2535                         PANEL_POWER_UP_DELAY_SHIFT;
2536
2537                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2538                         PANEL_LIGHT_ON_DELAY_SHIFT;
2539
2540                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2541                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2542
2543                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2544                         PANEL_POWER_DOWN_DELAY_SHIFT;
2545
2546                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2547                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2548
2549                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2550                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2551
2552                 vbt = dev_priv->edp.pps;
2553
2554                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2555                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2556
2557 #define get_delay(field)        ((max(cur.field, vbt.field) + 9) / 10)
2558
2559                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2560                 intel_dp->backlight_on_delay = get_delay(t8);
2561                 intel_dp->backlight_off_delay = get_delay(t9);
2562                 intel_dp->panel_power_down_delay = get_delay(t10);
2563                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2564
2565                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2566                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2567                               intel_dp->panel_power_cycle_delay);
2568
2569                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2570                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2571
2572                 ironlake_edp_panel_vdd_on(intel_dp);
2573                 ret = intel_dp_get_dpcd(intel_dp);
2574                 ironlake_edp_panel_vdd_off(intel_dp, false);
2575
2576                 if (ret) {
2577                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2578                                 dev_priv->no_aux_handshake =
2579                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2580                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2581                 } else {
2582                         /* if this fails, presume the device is a ghost */
2583                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2584                         intel_dp_encoder_destroy(&intel_dp->base.base);
2585                         intel_dp_destroy(&intel_connector->base);
2586                         return;
2587                 }
2588         }
2589
2590         intel_dp_i2c_init(intel_dp, intel_connector, name);
2591
2592         intel_encoder->hot_plug = intel_dp_hot_plug;
2593
2594         if (is_edp(intel_dp)) {
2595                 dev_priv->int_edp_connector = connector;
2596                 intel_panel_setup_backlight(dev);
2597         }
2598
2599         intel_dp_add_properties(intel_dp, connector);
2600
2601         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2602          * 0xd.  Failure to do so will result in spurious interrupts being
2603          * generated on the port when a cable is not attached.
2604          */
2605         if (IS_G4X(dev) && !IS_GM45(dev)) {
2606                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2607                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2608         }
2609 }