2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll[] = {
57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
62 static const struct dp_link_dpll pch_dpll[] = {
64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
69 static const struct dp_link_dpll vlv_dpll[] = {
71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates[] = { 162000, 270000, 540000 };
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
107 static bool is_edp(struct intel_dp *intel_dp)
109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
118 return intel_dig_port->base.base.dev;
121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
126 static void intel_dp_link_down(struct intel_dp *intel_dp);
127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
130 static void vlv_steal_power_sequencer(struct drm_device *dev,
132 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
135 intel_dp_max_link_bw(struct intel_dp *intel_dp)
137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
147 max_link_bw = DP_LINK_BW_1_62;
153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
156 u8 source_max, sink_max;
158 source_max = intel_dig_port->max_lanes;
159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
161 return min(source_max, sink_max);
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
170 * 270000 * 1 * 8 / 10 == 216000
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
182 intel_dp_link_required(int pixel_clock, int bpp)
184 return (pixel_clock * bpp + 9) / 10;
188 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
190 return (max_link_clock * max_lanes * 8) / 10;
193 static enum drm_mode_status
194 intel_dp_mode_valid(struct drm_connector *connector,
195 struct drm_display_mode *mode)
197 struct intel_dp *intel_dp = intel_attached_dp(connector);
198 struct intel_connector *intel_connector = to_intel_connector(connector);
199 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
200 int target_clock = mode->clock;
201 int max_rate, mode_rate, max_lanes, max_link_clock;
202 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
204 if (is_edp(intel_dp) && fixed_mode) {
205 if (mode->hdisplay > fixed_mode->hdisplay)
208 if (mode->vdisplay > fixed_mode->vdisplay)
211 target_clock = fixed_mode->clock;
214 max_link_clock = intel_dp_max_link_rate(intel_dp);
215 max_lanes = intel_dp_max_lane_count(intel_dp);
217 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
218 mode_rate = intel_dp_link_required(target_clock, 18);
220 if (mode_rate > max_rate || target_clock > max_dotclk)
221 return MODE_CLOCK_HIGH;
223 if (mode->clock < 10000)
224 return MODE_CLOCK_LOW;
226 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
227 return MODE_H_ILLEGAL;
232 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
239 for (i = 0; i < src_bytes; i++)
240 v |= ((uint32_t) src[i]) << ((3-i) * 8);
244 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
249 for (i = 0; i < dst_bytes; i++)
250 dst[i] = src >> ((3-i) * 8);
254 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
255 struct intel_dp *intel_dp);
257 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
258 struct intel_dp *intel_dp);
260 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
262 static void pps_lock(struct intel_dp *intel_dp)
264 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
265 struct intel_encoder *encoder = &intel_dig_port->base;
266 struct drm_device *dev = encoder->base.dev;
267 struct drm_i915_private *dev_priv = to_i915(dev);
268 enum intel_display_power_domain power_domain;
271 * See vlv_power_sequencer_reset() why we need
272 * a power domain reference here.
274 power_domain = intel_display_port_aux_power_domain(encoder);
275 intel_display_power_get(dev_priv, power_domain);
277 mutex_lock(&dev_priv->pps_mutex);
280 static void pps_unlock(struct intel_dp *intel_dp)
282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
283 struct intel_encoder *encoder = &intel_dig_port->base;
284 struct drm_device *dev = encoder->base.dev;
285 struct drm_i915_private *dev_priv = to_i915(dev);
286 enum intel_display_power_domain power_domain;
288 mutex_unlock(&dev_priv->pps_mutex);
290 power_domain = intel_display_port_aux_power_domain(encoder);
291 intel_display_power_put(dev_priv, power_domain);
295 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
297 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
298 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = to_i915(dev);
300 enum pipe pipe = intel_dp->pps_pipe;
301 bool pll_enabled, release_cl_override = false;
302 enum dpio_phy phy = DPIO_PHY(pipe);
303 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
306 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
307 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
308 pipe_name(pipe), port_name(intel_dig_port->port)))
311 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
312 pipe_name(pipe), port_name(intel_dig_port->port));
314 /* Preserve the BIOS-computed detected bit. This is
315 * supposed to be read-only.
317 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
318 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
319 DP |= DP_PORT_WIDTH(1);
320 DP |= DP_LINK_TRAIN_PAT_1;
322 if (IS_CHERRYVIEW(dev))
323 DP |= DP_PIPE_SELECT_CHV(pipe);
324 else if (pipe == PIPE_B)
325 DP |= DP_PIPEB_SELECT;
327 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
330 * The DPLL for the pipe must be enabled for this to work.
331 * So enable temporarily it if it's not already enabled.
334 release_cl_override = IS_CHERRYVIEW(dev) &&
335 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
337 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
338 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
339 DRM_ERROR("Failed to force on pll for pipe %c!\n",
346 * Similar magic as in intel_dp_enable_port().
347 * We _must_ do this port enable + disable trick
348 * to make this power seqeuencer lock onto the port.
349 * Otherwise even VDD force bit won't work.
351 I915_WRITE(intel_dp->output_reg, DP);
352 POSTING_READ(intel_dp->output_reg);
354 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
355 POSTING_READ(intel_dp->output_reg);
357 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
358 POSTING_READ(intel_dp->output_reg);
361 vlv_force_pll_off(dev, pipe);
363 if (release_cl_override)
364 chv_phy_powergate_ch(dev_priv, phy, ch, false);
369 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
371 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
372 struct drm_device *dev = intel_dig_port->base.base.dev;
373 struct drm_i915_private *dev_priv = to_i915(dev);
374 struct intel_encoder *encoder;
375 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
378 lockdep_assert_held(&dev_priv->pps_mutex);
380 /* We should never land here with regular DP ports */
381 WARN_ON(!is_edp(intel_dp));
383 if (intel_dp->pps_pipe != INVALID_PIPE)
384 return intel_dp->pps_pipe;
387 * We don't have power sequencer currently.
388 * Pick one that's not used by other ports.
390 for_each_intel_encoder(dev, encoder) {
391 struct intel_dp *tmp;
393 if (encoder->type != INTEL_OUTPUT_EDP)
396 tmp = enc_to_intel_dp(&encoder->base);
398 if (tmp->pps_pipe != INVALID_PIPE)
399 pipes &= ~(1 << tmp->pps_pipe);
403 * Didn't find one. This should not happen since there
404 * are two power sequencers and up to two eDP ports.
406 if (WARN_ON(pipes == 0))
409 pipe = ffs(pipes) - 1;
411 vlv_steal_power_sequencer(dev, pipe);
412 intel_dp->pps_pipe = pipe;
414 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
415 pipe_name(intel_dp->pps_pipe),
416 port_name(intel_dig_port->port));
418 /* init power sequencer on this pipe and port */
419 intel_dp_init_panel_power_sequencer(dev, intel_dp);
420 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
423 * Even vdd force doesn't work until we've made
424 * the power sequencer lock in on the port.
426 vlv_power_sequencer_kick(intel_dp);
428 return intel_dp->pps_pipe;
432 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
435 struct drm_device *dev = intel_dig_port->base.base.dev;
436 struct drm_i915_private *dev_priv = to_i915(dev);
438 lockdep_assert_held(&dev_priv->pps_mutex);
440 /* We should never land here with regular DP ports */
441 WARN_ON(!is_edp(intel_dp));
444 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
445 * mapping needs to be retrieved from VBT, for now just hard-code to
446 * use instance #0 always.
448 if (!intel_dp->pps_reset)
451 intel_dp->pps_reset = false;
454 * Only the HW needs to be reprogrammed, the SW state is fixed and
455 * has been setup during connector init.
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
462 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
465 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
468 return I915_READ(PP_STATUS(pipe)) & PP_ON;
471 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
474 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
477 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
484 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
486 vlv_pipe_check pipe_check)
490 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
491 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
492 PANEL_PORT_SELECT_MASK;
494 if (port_sel != PANEL_PORT_SELECT_VLV(port))
497 if (!pipe_check(dev_priv, pipe))
507 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
509 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
510 struct drm_device *dev = intel_dig_port->base.base.dev;
511 struct drm_i915_private *dev_priv = to_i915(dev);
512 enum port port = intel_dig_port->port;
514 lockdep_assert_held(&dev_priv->pps_mutex);
516 /* try to find a pipe with this port selected */
517 /* first pick one where the panel is on */
518 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
520 /* didn't find one? pick one where vdd is on */
521 if (intel_dp->pps_pipe == INVALID_PIPE)
522 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
523 vlv_pipe_has_vdd_on);
524 /* didn't find one? pick one with just the correct port */
525 if (intel_dp->pps_pipe == INVALID_PIPE)
526 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
529 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
530 if (intel_dp->pps_pipe == INVALID_PIPE) {
531 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
536 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
537 port_name(port), pipe_name(intel_dp->pps_pipe));
539 intel_dp_init_panel_power_sequencer(dev, intel_dp);
540 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
543 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
545 struct drm_device *dev = &dev_priv->drm;
546 struct intel_encoder *encoder;
548 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
553 * We can't grab pps_mutex here due to deadlock with power_domain
554 * mutex when power_domain functions are called while holding pps_mutex.
555 * That also means that in order to use pps_pipe the code needs to
556 * hold both a power domain reference and pps_mutex, and the power domain
557 * reference get/put must be done while _not_ holding pps_mutex.
558 * pps_{lock,unlock}() do these steps in the correct order, so one
559 * should use them always.
562 for_each_intel_encoder(dev, encoder) {
563 struct intel_dp *intel_dp;
565 if (encoder->type != INTEL_OUTPUT_EDP)
568 intel_dp = enc_to_intel_dp(&encoder->base);
570 intel_dp->pps_reset = true;
572 intel_dp->pps_pipe = INVALID_PIPE;
576 struct pps_registers {
584 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
585 struct intel_dp *intel_dp,
586 struct pps_registers *regs)
590 memset(regs, 0, sizeof(*regs));
592 if (IS_BROXTON(dev_priv))
593 pps_idx = bxt_power_sequencer_idx(intel_dp);
594 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
595 pps_idx = vlv_power_sequencer_pipe(intel_dp);
597 regs->pp_ctrl = PP_CONTROL(pps_idx);
598 regs->pp_stat = PP_STATUS(pps_idx);
599 regs->pp_on = PP_ON_DELAYS(pps_idx);
600 regs->pp_off = PP_OFF_DELAYS(pps_idx);
601 if (!IS_BROXTON(dev_priv))
602 regs->pp_div = PP_DIVISOR(pps_idx);
606 _pp_ctrl_reg(struct intel_dp *intel_dp)
608 struct pps_registers regs;
610 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
617 _pp_stat_reg(struct intel_dp *intel_dp)
619 struct pps_registers regs;
621 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
627 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
628 This function only applicable when panel PM state is not to be tracked */
629 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
632 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
634 struct drm_device *dev = intel_dp_to_dev(intel_dp);
635 struct drm_i915_private *dev_priv = to_i915(dev);
637 if (!is_edp(intel_dp) || code != SYS_RESTART)
642 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
643 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
644 i915_reg_t pp_ctrl_reg, pp_div_reg;
647 pp_ctrl_reg = PP_CONTROL(pipe);
648 pp_div_reg = PP_DIVISOR(pipe);
649 pp_div = I915_READ(pp_div_reg);
650 pp_div &= PP_REFERENCE_DIVIDER_MASK;
652 /* 0x1F write to PP_DIV_REG sets max cycle delay */
653 I915_WRITE(pp_div_reg, pp_div | 0x1F);
654 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
655 msleep(intel_dp->panel_power_cycle_delay);
658 pps_unlock(intel_dp);
663 static bool edp_have_panel_power(struct intel_dp *intel_dp)
665 struct drm_device *dev = intel_dp_to_dev(intel_dp);
666 struct drm_i915_private *dev_priv = to_i915(dev);
668 lockdep_assert_held(&dev_priv->pps_mutex);
670 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
671 intel_dp->pps_pipe == INVALID_PIPE)
674 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
677 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
679 struct drm_device *dev = intel_dp_to_dev(intel_dp);
680 struct drm_i915_private *dev_priv = to_i915(dev);
682 lockdep_assert_held(&dev_priv->pps_mutex);
684 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
685 intel_dp->pps_pipe == INVALID_PIPE)
688 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
692 intel_dp_check_edp(struct intel_dp *intel_dp)
694 struct drm_device *dev = intel_dp_to_dev(intel_dp);
695 struct drm_i915_private *dev_priv = to_i915(dev);
697 if (!is_edp(intel_dp))
700 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
701 WARN(1, "eDP powered off while attempting aux channel communication.\n");
702 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
703 I915_READ(_pp_stat_reg(intel_dp)),
704 I915_READ(_pp_ctrl_reg(intel_dp)));
709 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
711 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
712 struct drm_device *dev = intel_dig_port->base.base.dev;
713 struct drm_i915_private *dev_priv = to_i915(dev);
714 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
718 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
720 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
721 msecs_to_jiffies_timeout(10));
723 done = wait_for(C, 10) == 0;
725 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
732 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
734 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
735 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
741 * The clock divider is based off the hrawclk, and would like to run at
742 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
744 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
747 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
749 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
750 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
756 * The clock divider is based off the cdclk or PCH rawclk, and would
757 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
758 * divide by 2000 and use that
760 if (intel_dig_port->port == PORT_A)
761 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
763 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
766 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
768 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
769 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
771 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
772 /* Workaround for non-ULT HSW */
780 return ilk_get_aux_clock_divider(intel_dp, index);
783 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
786 * SKL doesn't need us to program the AUX clock divider (Hardware will
787 * derive the clock from CDCLK automatically). We still implement the
788 * get_aux_clock_divider vfunc to plug-in into the existing code.
790 return index ? 0 : 1;
793 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
796 uint32_t aux_clock_divider)
798 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
799 struct drm_device *dev = intel_dig_port->base.base.dev;
800 uint32_t precharge, timeout;
807 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
808 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
810 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
812 return DP_AUX_CH_CTL_SEND_BUSY |
814 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
815 DP_AUX_CH_CTL_TIME_OUT_ERROR |
817 DP_AUX_CH_CTL_RECEIVE_ERROR |
818 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
819 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
820 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
823 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
828 return DP_AUX_CH_CTL_SEND_BUSY |
830 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
831 DP_AUX_CH_CTL_TIME_OUT_ERROR |
832 DP_AUX_CH_CTL_TIME_OUT_1600us |
833 DP_AUX_CH_CTL_RECEIVE_ERROR |
834 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
835 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
836 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
840 intel_dp_aux_ch(struct intel_dp *intel_dp,
841 const uint8_t *send, int send_bytes,
842 uint8_t *recv, int recv_size)
844 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
845 struct drm_device *dev = intel_dig_port->base.base.dev;
846 struct drm_i915_private *dev_priv = to_i915(dev);
847 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
848 uint32_t aux_clock_divider;
849 int i, ret, recv_bytes;
852 bool has_aux_irq = HAS_AUX_IRQ(dev);
858 * We will be called with VDD already enabled for dpcd/edid/oui reads.
859 * In such cases we want to leave VDD enabled and it's up to upper layers
860 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
863 vdd = edp_panel_vdd_on(intel_dp);
865 /* dp aux is extremely sensitive to irq latency, hence request the
866 * lowest possible wakeup latency and so prevent the cpu from going into
869 pm_qos_update_request(&dev_priv->pm_qos, 0);
871 intel_dp_check_edp(intel_dp);
873 /* Try to wait for any previous AUX channel activity */
874 for (try = 0; try < 3; try++) {
875 status = I915_READ_NOTRACE(ch_ctl);
876 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
882 static u32 last_status = -1;
883 const u32 status = I915_READ(ch_ctl);
885 if (status != last_status) {
886 WARN(1, "dp_aux_ch not started status 0x%08x\n",
888 last_status = status;
895 /* Only 5 data registers! */
896 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
901 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
902 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
907 /* Must try at least 3 times according to DP spec */
908 for (try = 0; try < 5; try++) {
909 /* Load the send data into the aux channel data registers */
910 for (i = 0; i < send_bytes; i += 4)
911 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
912 intel_dp_pack_aux(send + i,
915 /* Send the command and wait for it to complete */
916 I915_WRITE(ch_ctl, send_ctl);
918 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
920 /* Clear done status and any errors */
924 DP_AUX_CH_CTL_TIME_OUT_ERROR |
925 DP_AUX_CH_CTL_RECEIVE_ERROR);
927 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
930 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
931 * 400us delay required for errors and timeouts
932 * Timeout errors from the HW already meet this
933 * requirement so skip to next iteration
935 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
936 usleep_range(400, 500);
939 if (status & DP_AUX_CH_CTL_DONE)
944 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
945 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
951 /* Check for timeout or receive error.
952 * Timeouts occur when the sink is not connected
954 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
955 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
960 /* Timeouts occur when the device isn't connected, so they're
961 * "normal" -- don't fill the kernel log with these */
962 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
963 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
968 /* Unload any bytes sent back from the other side */
969 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
970 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
973 * By BSpec: "Message sizes of 0 or >20 are not allowed."
974 * We have no idea of what happened so we return -EBUSY so
975 * drm layer takes care for the necessary retries.
977 if (recv_bytes == 0 || recv_bytes > 20) {
978 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
981 * FIXME: This patch was created on top of a series that
982 * organize the retries at drm level. There EBUSY should
983 * also take care for 1ms wait before retrying.
984 * That aux retries re-org is still needed and after that is
985 * merged we remove this sleep from here.
987 usleep_range(1000, 1500);
992 if (recv_bytes > recv_size)
993 recv_bytes = recv_size;
995 for (i = 0; i < recv_bytes; i += 4)
996 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
997 recv + i, recv_bytes - i);
1001 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1004 edp_panel_vdd_off(intel_dp, false);
1006 pps_unlock(intel_dp);
1011 #define BARE_ADDRESS_SIZE 3
1012 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1014 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1016 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1017 uint8_t txbuf[20], rxbuf[20];
1018 size_t txsize, rxsize;
1021 txbuf[0] = (msg->request << 4) |
1022 ((msg->address >> 16) & 0xf);
1023 txbuf[1] = (msg->address >> 8) & 0xff;
1024 txbuf[2] = msg->address & 0xff;
1025 txbuf[3] = msg->size - 1;
1027 switch (msg->request & ~DP_AUX_I2C_MOT) {
1028 case DP_AUX_NATIVE_WRITE:
1029 case DP_AUX_I2C_WRITE:
1030 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1031 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1032 rxsize = 2; /* 0 or 1 data bytes */
1034 if (WARN_ON(txsize > 20))
1037 WARN_ON(!msg->buffer != !msg->size);
1040 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1042 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1044 msg->reply = rxbuf[0] >> 4;
1047 /* Number of bytes written in a short write. */
1048 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1050 /* Return payload size. */
1056 case DP_AUX_NATIVE_READ:
1057 case DP_AUX_I2C_READ:
1058 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1059 rxsize = msg->size + 1;
1061 if (WARN_ON(rxsize > 20))
1064 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1066 msg->reply = rxbuf[0] >> 4;
1068 * Assume happy day, and copy the data. The caller is
1069 * expected to check msg->reply before touching it.
1071 * Return payload size.
1074 memcpy(msg->buffer, rxbuf + 1, ret);
1086 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1093 return DP_AUX_CH_CTL(port);
1096 return DP_AUX_CH_CTL(PORT_B);
1100 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1101 enum port port, int index)
1107 return DP_AUX_CH_DATA(port, index);
1110 return DP_AUX_CH_DATA(PORT_B, index);
1114 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1119 return DP_AUX_CH_CTL(port);
1123 return PCH_DP_AUX_CH_CTL(port);
1126 return DP_AUX_CH_CTL(PORT_A);
1130 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1131 enum port port, int index)
1135 return DP_AUX_CH_DATA(port, index);
1139 return PCH_DP_AUX_CH_DATA(port, index);
1142 return DP_AUX_CH_DATA(PORT_A, index);
1147 * On SKL we don't have Aux for port E so we rely
1148 * on VBT to set a proper alternate aux channel.
1150 static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1152 const struct ddi_vbt_port_info *info =
1153 &dev_priv->vbt.ddi_port_info[PORT_E];
1155 switch (info->alternate_aux_channel) {
1165 MISSING_CASE(info->alternate_aux_channel);
1170 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1174 port = skl_porte_aux_port(dev_priv);
1181 return DP_AUX_CH_CTL(port);
1184 return DP_AUX_CH_CTL(PORT_A);
1188 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1189 enum port port, int index)
1192 port = skl_porte_aux_port(dev_priv);
1199 return DP_AUX_CH_DATA(port, index);
1202 return DP_AUX_CH_DATA(PORT_A, index);
1206 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1209 if (INTEL_INFO(dev_priv)->gen >= 9)
1210 return skl_aux_ctl_reg(dev_priv, port);
1211 else if (HAS_PCH_SPLIT(dev_priv))
1212 return ilk_aux_ctl_reg(dev_priv, port);
1214 return g4x_aux_ctl_reg(dev_priv, port);
1217 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1218 enum port port, int index)
1220 if (INTEL_INFO(dev_priv)->gen >= 9)
1221 return skl_aux_data_reg(dev_priv, port, index);
1222 else if (HAS_PCH_SPLIT(dev_priv))
1223 return ilk_aux_data_reg(dev_priv, port, index);
1225 return g4x_aux_data_reg(dev_priv, port, index);
1228 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1230 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1231 enum port port = dp_to_dig_port(intel_dp)->port;
1234 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1235 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1236 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1240 intel_dp_aux_fini(struct intel_dp *intel_dp)
1242 kfree(intel_dp->aux.name);
1246 intel_dp_aux_init(struct intel_dp *intel_dp)
1248 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1249 enum port port = intel_dig_port->port;
1251 intel_aux_reg_init(intel_dp);
1252 drm_dp_aux_init(&intel_dp->aux);
1254 /* Failure to allocate our preferred name is not critical */
1255 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1256 intel_dp->aux.transfer = intel_dp_aux_transfer;
1260 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1262 if (intel_dp->num_sink_rates) {
1263 *sink_rates = intel_dp->sink_rates;
1264 return intel_dp->num_sink_rates;
1267 *sink_rates = default_rates;
1269 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1272 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1274 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1275 struct drm_device *dev = dig_port->base.base.dev;
1277 /* WaDisableHBR2:skl */
1278 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
1281 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1282 (INTEL_INFO(dev)->gen >= 9))
1289 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
1291 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1292 struct drm_device *dev = dig_port->base.base.dev;
1295 if (IS_BROXTON(dev)) {
1296 *source_rates = bxt_rates;
1297 size = ARRAY_SIZE(bxt_rates);
1298 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1299 *source_rates = skl_rates;
1300 size = ARRAY_SIZE(skl_rates);
1302 *source_rates = default_rates;
1303 size = ARRAY_SIZE(default_rates);
1306 /* This depends on the fact that 5.4 is last value in the array */
1307 if (!intel_dp_source_supports_hbr2(intel_dp))
1314 intel_dp_set_clock(struct intel_encoder *encoder,
1315 struct intel_crtc_state *pipe_config)
1317 struct drm_device *dev = encoder->base.dev;
1318 const struct dp_link_dpll *divisor = NULL;
1322 divisor = gen4_dpll;
1323 count = ARRAY_SIZE(gen4_dpll);
1324 } else if (HAS_PCH_SPLIT(dev)) {
1326 count = ARRAY_SIZE(pch_dpll);
1327 } else if (IS_CHERRYVIEW(dev)) {
1329 count = ARRAY_SIZE(chv_dpll);
1330 } else if (IS_VALLEYVIEW(dev)) {
1332 count = ARRAY_SIZE(vlv_dpll);
1335 if (divisor && count) {
1336 for (i = 0; i < count; i++) {
1337 if (pipe_config->port_clock == divisor[i].clock) {
1338 pipe_config->dpll = divisor[i].dpll;
1339 pipe_config->clock_set = true;
1346 static int intersect_rates(const int *source_rates, int source_len,
1347 const int *sink_rates, int sink_len,
1350 int i = 0, j = 0, k = 0;
1352 while (i < source_len && j < sink_len) {
1353 if (source_rates[i] == sink_rates[j]) {
1354 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1356 common_rates[k] = source_rates[i];
1360 } else if (source_rates[i] < sink_rates[j]) {
1369 static int intel_dp_common_rates(struct intel_dp *intel_dp,
1372 const int *source_rates, *sink_rates;
1373 int source_len, sink_len;
1375 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1376 source_len = intel_dp_source_rates(intel_dp, &source_rates);
1378 return intersect_rates(source_rates, source_len,
1379 sink_rates, sink_len,
1383 static void snprintf_int_array(char *str, size_t len,
1384 const int *array, int nelem)
1390 for (i = 0; i < nelem; i++) {
1391 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1399 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1401 const int *source_rates, *sink_rates;
1402 int source_len, sink_len, common_len;
1403 int common_rates[DP_MAX_SUPPORTED_RATES];
1404 char str[128]; /* FIXME: too big for stack? */
1406 if ((drm_debug & DRM_UT_KMS) == 0)
1409 source_len = intel_dp_source_rates(intel_dp, &source_rates);
1410 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1411 DRM_DEBUG_KMS("source rates: %s\n", str);
1413 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1414 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1415 DRM_DEBUG_KMS("sink rates: %s\n", str);
1417 common_len = intel_dp_common_rates(intel_dp, common_rates);
1418 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1419 DRM_DEBUG_KMS("common rates: %s\n", str);
1422 static int rate_to_index(int find, const int *rates)
1426 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1427 if (find == rates[i])
1434 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1436 int rates[DP_MAX_SUPPORTED_RATES] = {};
1439 len = intel_dp_common_rates(intel_dp, rates);
1440 if (WARN_ON(len <= 0))
1443 return rates[len - 1];
1446 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1448 return rate_to_index(rate, intel_dp->sink_rates);
1451 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1452 uint8_t *link_bw, uint8_t *rate_select)
1454 if (intel_dp->num_sink_rates) {
1457 intel_dp_rate_select(intel_dp, port_clock);
1459 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1465 intel_dp_compute_config(struct intel_encoder *encoder,
1466 struct intel_crtc_state *pipe_config,
1467 struct drm_connector_state *conn_state)
1469 struct drm_device *dev = encoder->base.dev;
1470 struct drm_i915_private *dev_priv = to_i915(dev);
1471 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1472 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1473 enum port port = dp_to_dig_port(intel_dp)->port;
1474 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1475 struct intel_connector *intel_connector = intel_dp->attached_connector;
1476 int lane_count, clock;
1477 int min_lane_count = 1;
1478 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1479 /* Conveniently, the link BW constants become indices with a shift...*/
1483 int link_avail, link_clock;
1484 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1486 uint8_t link_bw, rate_select;
1488 common_len = intel_dp_common_rates(intel_dp, common_rates);
1490 /* No common link rates between source and sink */
1491 WARN_ON(common_len <= 0);
1493 max_clock = common_len - 1;
1495 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1496 pipe_config->has_pch_encoder = true;
1498 pipe_config->has_drrs = false;
1499 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1501 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1502 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1505 if (INTEL_INFO(dev)->gen >= 9) {
1507 ret = skl_update_scaler_crtc(pipe_config);
1512 if (HAS_GMCH_DISPLAY(dev))
1513 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1514 intel_connector->panel.fitting_mode);
1516 intel_pch_panel_fitting(intel_crtc, pipe_config,
1517 intel_connector->panel.fitting_mode);
1520 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1523 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1524 "max bw %d pixel clock %iKHz\n",
1525 max_lane_count, common_rates[max_clock],
1526 adjusted_mode->crtc_clock);
1528 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1529 * bpc in between. */
1530 bpp = pipe_config->pipe_bpp;
1531 if (is_edp(intel_dp)) {
1533 /* Get bpp from vbt only for panels that dont have bpp in edid */
1534 if (intel_connector->base.display_info.bpc == 0 &&
1535 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1536 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1537 dev_priv->vbt.edp.bpp);
1538 bpp = dev_priv->vbt.edp.bpp;
1542 * Use the maximum clock and number of lanes the eDP panel
1543 * advertizes being capable of. The panels are generally
1544 * designed to support only a single clock and lane
1545 * configuration, and typically these values correspond to the
1546 * native resolution of the panel.
1548 min_lane_count = max_lane_count;
1549 min_clock = max_clock;
1552 for (; bpp >= 6*3; bpp -= 2*3) {
1553 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1556 for (clock = min_clock; clock <= max_clock; clock++) {
1557 for (lane_count = min_lane_count;
1558 lane_count <= max_lane_count;
1561 link_clock = common_rates[clock];
1562 link_avail = intel_dp_max_data_rate(link_clock,
1565 if (mode_rate <= link_avail) {
1575 if (intel_dp->color_range_auto) {
1578 * CEA-861-E - 5.1 Default Encoding Parameters
1579 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1581 pipe_config->limited_color_range =
1582 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1584 pipe_config->limited_color_range =
1585 intel_dp->limited_color_range;
1588 pipe_config->lane_count = lane_count;
1590 pipe_config->pipe_bpp = bpp;
1591 pipe_config->port_clock = common_rates[clock];
1593 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1594 &link_bw, &rate_select);
1596 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1597 link_bw, rate_select, pipe_config->lane_count,
1598 pipe_config->port_clock, bpp);
1599 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1600 mode_rate, link_avail);
1602 intel_link_compute_m_n(bpp, lane_count,
1603 adjusted_mode->crtc_clock,
1604 pipe_config->port_clock,
1605 &pipe_config->dp_m_n);
1607 if (intel_connector->panel.downclock_mode != NULL &&
1608 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1609 pipe_config->has_drrs = true;
1610 intel_link_compute_m_n(bpp, lane_count,
1611 intel_connector->panel.downclock_mode->clock,
1612 pipe_config->port_clock,
1613 &pipe_config->dp_m2_n2);
1617 * DPLL0 VCO may need to be adjusted to get the correct
1618 * clock for eDP. This will affect cdclk as well.
1620 if (is_edp(intel_dp) &&
1621 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1624 switch (pipe_config->port_clock / 2) {
1634 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1638 intel_dp_set_clock(encoder, pipe_config);
1643 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1644 int link_rate, uint8_t lane_count,
1647 intel_dp->link_rate = link_rate;
1648 intel_dp->lane_count = lane_count;
1649 intel_dp->link_mst = link_mst;
1652 static void intel_dp_prepare(struct intel_encoder *encoder,
1653 struct intel_crtc_state *pipe_config)
1655 struct drm_device *dev = encoder->base.dev;
1656 struct drm_i915_private *dev_priv = to_i915(dev);
1657 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1658 enum port port = dp_to_dig_port(intel_dp)->port;
1659 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1660 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1662 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1663 pipe_config->lane_count,
1664 intel_crtc_has_type(pipe_config,
1665 INTEL_OUTPUT_DP_MST));
1668 * There are four kinds of DP registers:
1675 * IBX PCH and CPU are the same for almost everything,
1676 * except that the CPU DP PLL is configured in this
1679 * CPT PCH is quite different, having many bits moved
1680 * to the TRANS_DP_CTL register instead. That
1681 * configuration happens (oddly) in ironlake_pch_enable
1684 /* Preserve the BIOS-computed detected bit. This is
1685 * supposed to be read-only.
1687 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1689 /* Handle DP bits in common between all three register formats */
1690 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1691 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1693 /* Split out the IBX/CPU vs CPT settings */
1695 if (IS_GEN7(dev) && port == PORT_A) {
1696 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1697 intel_dp->DP |= DP_SYNC_HS_HIGH;
1698 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1699 intel_dp->DP |= DP_SYNC_VS_HIGH;
1700 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1702 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1703 intel_dp->DP |= DP_ENHANCED_FRAMING;
1705 intel_dp->DP |= crtc->pipe << 29;
1706 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1709 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1711 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1712 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1713 trans_dp |= TRANS_DP_ENH_FRAMING;
1715 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1716 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1718 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1719 !IS_CHERRYVIEW(dev) && pipe_config->limited_color_range)
1720 intel_dp->DP |= DP_COLOR_RANGE_16_235;
1722 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1723 intel_dp->DP |= DP_SYNC_HS_HIGH;
1724 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1725 intel_dp->DP |= DP_SYNC_VS_HIGH;
1726 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1728 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1729 intel_dp->DP |= DP_ENHANCED_FRAMING;
1731 if (IS_CHERRYVIEW(dev))
1732 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1733 else if (crtc->pipe == PIPE_B)
1734 intel_dp->DP |= DP_PIPEB_SELECT;
1738 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1739 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1741 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1742 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1744 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1745 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1747 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1748 struct intel_dp *intel_dp);
1750 static void wait_panel_status(struct intel_dp *intel_dp,
1754 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1755 struct drm_i915_private *dev_priv = to_i915(dev);
1756 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1758 lockdep_assert_held(&dev_priv->pps_mutex);
1760 intel_pps_verify_state(dev_priv, intel_dp);
1762 pp_stat_reg = _pp_stat_reg(intel_dp);
1763 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1765 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1767 I915_READ(pp_stat_reg),
1768 I915_READ(pp_ctrl_reg));
1770 if (intel_wait_for_register(dev_priv,
1771 pp_stat_reg, mask, value,
1773 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1774 I915_READ(pp_stat_reg),
1775 I915_READ(pp_ctrl_reg));
1777 DRM_DEBUG_KMS("Wait complete\n");
1780 static void wait_panel_on(struct intel_dp *intel_dp)
1782 DRM_DEBUG_KMS("Wait for panel power on\n");
1783 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1786 static void wait_panel_off(struct intel_dp *intel_dp)
1788 DRM_DEBUG_KMS("Wait for panel power off time\n");
1789 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1792 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1794 ktime_t panel_power_on_time;
1795 s64 panel_power_off_duration;
1797 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1799 /* take the difference of currrent time and panel power off time
1800 * and then make panel wait for t11_t12 if needed. */
1801 panel_power_on_time = ktime_get_boottime();
1802 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1804 /* When we disable the VDD override bit last we have to do the manual
1806 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1807 wait_remaining_ms_from_jiffies(jiffies,
1808 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1810 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1813 static void wait_backlight_on(struct intel_dp *intel_dp)
1815 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1816 intel_dp->backlight_on_delay);
1819 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1821 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1822 intel_dp->backlight_off_delay);
1825 /* Read the current pp_control value, unlocking the register if it
1829 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1831 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1832 struct drm_i915_private *dev_priv = to_i915(dev);
1835 lockdep_assert_held(&dev_priv->pps_mutex);
1837 control = I915_READ(_pp_ctrl_reg(intel_dp));
1838 if (WARN_ON(!HAS_DDI(dev_priv) &&
1839 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
1840 control &= ~PANEL_UNLOCK_MASK;
1841 control |= PANEL_UNLOCK_REGS;
1847 * Must be paired with edp_panel_vdd_off().
1848 * Must hold pps_mutex around the whole on/off sequence.
1849 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1851 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1853 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1854 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1855 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1856 struct drm_i915_private *dev_priv = to_i915(dev);
1857 enum intel_display_power_domain power_domain;
1859 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1860 bool need_to_disable = !intel_dp->want_panel_vdd;
1862 lockdep_assert_held(&dev_priv->pps_mutex);
1864 if (!is_edp(intel_dp))
1867 cancel_delayed_work(&intel_dp->panel_vdd_work);
1868 intel_dp->want_panel_vdd = true;
1870 if (edp_have_panel_vdd(intel_dp))
1871 return need_to_disable;
1873 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1874 intel_display_power_get(dev_priv, power_domain);
1876 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1877 port_name(intel_dig_port->port));
1879 if (!edp_have_panel_power(intel_dp))
1880 wait_panel_power_cycle(intel_dp);
1882 pp = ironlake_get_pp_control(intel_dp);
1883 pp |= EDP_FORCE_VDD;
1885 pp_stat_reg = _pp_stat_reg(intel_dp);
1886 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1888 I915_WRITE(pp_ctrl_reg, pp);
1889 POSTING_READ(pp_ctrl_reg);
1890 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1891 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1893 * If the panel wasn't on, delay before accessing aux channel
1895 if (!edp_have_panel_power(intel_dp)) {
1896 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1897 port_name(intel_dig_port->port));
1898 msleep(intel_dp->panel_power_up_delay);
1901 return need_to_disable;
1905 * Must be paired with intel_edp_panel_vdd_off() or
1906 * intel_edp_panel_off().
1907 * Nested calls to these functions are not allowed since
1908 * we drop the lock. Caller must use some higher level
1909 * locking to prevent nested calls from other threads.
1911 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1915 if (!is_edp(intel_dp))
1919 vdd = edp_panel_vdd_on(intel_dp);
1920 pps_unlock(intel_dp);
1922 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1923 port_name(dp_to_dig_port(intel_dp)->port));
1926 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1928 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1929 struct drm_i915_private *dev_priv = to_i915(dev);
1930 struct intel_digital_port *intel_dig_port =
1931 dp_to_dig_port(intel_dp);
1932 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1933 enum intel_display_power_domain power_domain;
1935 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1937 lockdep_assert_held(&dev_priv->pps_mutex);
1939 WARN_ON(intel_dp->want_panel_vdd);
1941 if (!edp_have_panel_vdd(intel_dp))
1944 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1945 port_name(intel_dig_port->port));
1947 pp = ironlake_get_pp_control(intel_dp);
1948 pp &= ~EDP_FORCE_VDD;
1950 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1951 pp_stat_reg = _pp_stat_reg(intel_dp);
1953 I915_WRITE(pp_ctrl_reg, pp);
1954 POSTING_READ(pp_ctrl_reg);
1956 /* Make sure sequencer is idle before allowing subsequent activity */
1957 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1958 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1960 if ((pp & PANEL_POWER_ON) == 0)
1961 intel_dp->panel_power_off_time = ktime_get_boottime();
1963 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1964 intel_display_power_put(dev_priv, power_domain);
1967 static void edp_panel_vdd_work(struct work_struct *__work)
1969 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1970 struct intel_dp, panel_vdd_work);
1973 if (!intel_dp->want_panel_vdd)
1974 edp_panel_vdd_off_sync(intel_dp);
1975 pps_unlock(intel_dp);
1978 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1980 unsigned long delay;
1983 * Queue the timer to fire a long time from now (relative to the power
1984 * down delay) to keep the panel power up across a sequence of
1987 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1988 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1992 * Must be paired with edp_panel_vdd_on().
1993 * Must hold pps_mutex around the whole on/off sequence.
1994 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1996 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1998 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2000 lockdep_assert_held(&dev_priv->pps_mutex);
2002 if (!is_edp(intel_dp))
2005 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2006 port_name(dp_to_dig_port(intel_dp)->port));
2008 intel_dp->want_panel_vdd = false;
2011 edp_panel_vdd_off_sync(intel_dp);
2013 edp_panel_vdd_schedule_off(intel_dp);
2016 static void edp_panel_on(struct intel_dp *intel_dp)
2018 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2019 struct drm_i915_private *dev_priv = to_i915(dev);
2021 i915_reg_t pp_ctrl_reg;
2023 lockdep_assert_held(&dev_priv->pps_mutex);
2025 if (!is_edp(intel_dp))
2028 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2029 port_name(dp_to_dig_port(intel_dp)->port));
2031 if (WARN(edp_have_panel_power(intel_dp),
2032 "eDP port %c panel power already on\n",
2033 port_name(dp_to_dig_port(intel_dp)->port)))
2036 wait_panel_power_cycle(intel_dp);
2038 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2039 pp = ironlake_get_pp_control(intel_dp);
2041 /* ILK workaround: disable reset around power sequence */
2042 pp &= ~PANEL_POWER_RESET;
2043 I915_WRITE(pp_ctrl_reg, pp);
2044 POSTING_READ(pp_ctrl_reg);
2047 pp |= PANEL_POWER_ON;
2049 pp |= PANEL_POWER_RESET;
2051 I915_WRITE(pp_ctrl_reg, pp);
2052 POSTING_READ(pp_ctrl_reg);
2054 wait_panel_on(intel_dp);
2055 intel_dp->last_power_on = jiffies;
2058 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2059 I915_WRITE(pp_ctrl_reg, pp);
2060 POSTING_READ(pp_ctrl_reg);
2064 void intel_edp_panel_on(struct intel_dp *intel_dp)
2066 if (!is_edp(intel_dp))
2070 edp_panel_on(intel_dp);
2071 pps_unlock(intel_dp);
2075 static void edp_panel_off(struct intel_dp *intel_dp)
2077 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2078 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2079 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2080 struct drm_i915_private *dev_priv = to_i915(dev);
2081 enum intel_display_power_domain power_domain;
2083 i915_reg_t pp_ctrl_reg;
2085 lockdep_assert_held(&dev_priv->pps_mutex);
2087 if (!is_edp(intel_dp))
2090 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2091 port_name(dp_to_dig_port(intel_dp)->port));
2093 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2094 port_name(dp_to_dig_port(intel_dp)->port));
2096 pp = ironlake_get_pp_control(intel_dp);
2097 /* We need to switch off panel power _and_ force vdd, for otherwise some
2098 * panels get very unhappy and cease to work. */
2099 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2102 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2104 intel_dp->want_panel_vdd = false;
2106 I915_WRITE(pp_ctrl_reg, pp);
2107 POSTING_READ(pp_ctrl_reg);
2109 intel_dp->panel_power_off_time = ktime_get_boottime();
2110 wait_panel_off(intel_dp);
2112 /* We got a reference when we enabled the VDD. */
2113 power_domain = intel_display_port_aux_power_domain(intel_encoder);
2114 intel_display_power_put(dev_priv, power_domain);
2117 void intel_edp_panel_off(struct intel_dp *intel_dp)
2119 if (!is_edp(intel_dp))
2123 edp_panel_off(intel_dp);
2124 pps_unlock(intel_dp);
2127 /* Enable backlight in the panel power control. */
2128 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2130 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2131 struct drm_device *dev = intel_dig_port->base.base.dev;
2132 struct drm_i915_private *dev_priv = to_i915(dev);
2134 i915_reg_t pp_ctrl_reg;
2137 * If we enable the backlight right away following a panel power
2138 * on, we may see slight flicker as the panel syncs with the eDP
2139 * link. So delay a bit to make sure the image is solid before
2140 * allowing it to appear.
2142 wait_backlight_on(intel_dp);
2146 pp = ironlake_get_pp_control(intel_dp);
2147 pp |= EDP_BLC_ENABLE;
2149 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2151 I915_WRITE(pp_ctrl_reg, pp);
2152 POSTING_READ(pp_ctrl_reg);
2154 pps_unlock(intel_dp);
2157 /* Enable backlight PWM and backlight PP control. */
2158 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2160 if (!is_edp(intel_dp))
2163 DRM_DEBUG_KMS("\n");
2165 intel_panel_enable_backlight(intel_dp->attached_connector);
2166 _intel_edp_backlight_on(intel_dp);
2169 /* Disable backlight in the panel power control. */
2170 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2172 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2173 struct drm_i915_private *dev_priv = to_i915(dev);
2175 i915_reg_t pp_ctrl_reg;
2177 if (!is_edp(intel_dp))
2182 pp = ironlake_get_pp_control(intel_dp);
2183 pp &= ~EDP_BLC_ENABLE;
2185 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2187 I915_WRITE(pp_ctrl_reg, pp);
2188 POSTING_READ(pp_ctrl_reg);
2190 pps_unlock(intel_dp);
2192 intel_dp->last_backlight_off = jiffies;
2193 edp_wait_backlight_off(intel_dp);
2196 /* Disable backlight PP control and backlight PWM. */
2197 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2199 if (!is_edp(intel_dp))
2202 DRM_DEBUG_KMS("\n");
2204 _intel_edp_backlight_off(intel_dp);
2205 intel_panel_disable_backlight(intel_dp->attached_connector);
2209 * Hook for controlling the panel power control backlight through the bl_power
2210 * sysfs attribute. Take care to handle multiple calls.
2212 static void intel_edp_backlight_power(struct intel_connector *connector,
2215 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2219 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2220 pps_unlock(intel_dp);
2222 if (is_enabled == enable)
2225 DRM_DEBUG_KMS("panel power control backlight %s\n",
2226 enable ? "enable" : "disable");
2229 _intel_edp_backlight_on(intel_dp);
2231 _intel_edp_backlight_off(intel_dp);
2234 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2236 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2237 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2238 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2240 I915_STATE_WARN(cur_state != state,
2241 "DP port %c state assertion failure (expected %s, current %s)\n",
2242 port_name(dig_port->port),
2243 onoff(state), onoff(cur_state));
2245 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2247 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2249 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2251 I915_STATE_WARN(cur_state != state,
2252 "eDP PLL state assertion failure (expected %s, current %s)\n",
2253 onoff(state), onoff(cur_state));
2255 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2256 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2258 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2259 struct intel_crtc_state *pipe_config)
2261 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2262 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2264 assert_pipe_disabled(dev_priv, crtc->pipe);
2265 assert_dp_port_disabled(intel_dp);
2266 assert_edp_pll_disabled(dev_priv);
2268 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2269 pipe_config->port_clock);
2271 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2273 if (pipe_config->port_clock == 162000)
2274 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2276 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2278 I915_WRITE(DP_A, intel_dp->DP);
2283 * [DevILK] Work around required when enabling DP PLL
2284 * while a pipe is enabled going to FDI:
2285 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2286 * 2. Program DP PLL enable
2288 if (IS_GEN5(dev_priv))
2289 intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe);
2291 intel_dp->DP |= DP_PLL_ENABLE;
2293 I915_WRITE(DP_A, intel_dp->DP);
2298 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2300 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2301 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2302 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2304 assert_pipe_disabled(dev_priv, crtc->pipe);
2305 assert_dp_port_disabled(intel_dp);
2306 assert_edp_pll_enabled(dev_priv);
2308 DRM_DEBUG_KMS("disabling eDP PLL\n");
2310 intel_dp->DP &= ~DP_PLL_ENABLE;
2312 I915_WRITE(DP_A, intel_dp->DP);
2317 /* If the sink supports it, try to set the power state appropriately */
2318 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2322 /* Should have a valid DPCD by this point */
2323 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2326 if (mode != DRM_MODE_DPMS_ON) {
2327 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2331 * When turning on, we need to retry for 1ms to give the sink
2334 for (i = 0; i < 3; i++) {
2335 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2344 DRM_DEBUG_KMS("failed to %s sink power state\n",
2345 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2348 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2351 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2352 enum port port = dp_to_dig_port(intel_dp)->port;
2353 struct drm_device *dev = encoder->base.dev;
2354 struct drm_i915_private *dev_priv = to_i915(dev);
2355 enum intel_display_power_domain power_domain;
2359 power_domain = intel_display_port_power_domain(encoder);
2360 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2365 tmp = I915_READ(intel_dp->output_reg);
2367 if (!(tmp & DP_PORT_EN))
2370 if (IS_GEN7(dev) && port == PORT_A) {
2371 *pipe = PORT_TO_PIPE_CPT(tmp);
2372 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2375 for_each_pipe(dev_priv, p) {
2376 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2377 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2385 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2386 i915_mmio_reg_offset(intel_dp->output_reg));
2387 } else if (IS_CHERRYVIEW(dev)) {
2388 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2390 *pipe = PORT_TO_PIPE(tmp);
2396 intel_display_power_put(dev_priv, power_domain);
2401 static void intel_dp_get_config(struct intel_encoder *encoder,
2402 struct intel_crtc_state *pipe_config)
2404 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2406 struct drm_device *dev = encoder->base.dev;
2407 struct drm_i915_private *dev_priv = to_i915(dev);
2408 enum port port = dp_to_dig_port(intel_dp)->port;
2409 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2411 tmp = I915_READ(intel_dp->output_reg);
2413 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2415 if (HAS_PCH_CPT(dev) && port != PORT_A) {
2416 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2418 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2419 flags |= DRM_MODE_FLAG_PHSYNC;
2421 flags |= DRM_MODE_FLAG_NHSYNC;
2423 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2424 flags |= DRM_MODE_FLAG_PVSYNC;
2426 flags |= DRM_MODE_FLAG_NVSYNC;
2428 if (tmp & DP_SYNC_HS_HIGH)
2429 flags |= DRM_MODE_FLAG_PHSYNC;
2431 flags |= DRM_MODE_FLAG_NHSYNC;
2433 if (tmp & DP_SYNC_VS_HIGH)
2434 flags |= DRM_MODE_FLAG_PVSYNC;
2436 flags |= DRM_MODE_FLAG_NVSYNC;
2439 pipe_config->base.adjusted_mode.flags |= flags;
2441 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2442 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
2443 pipe_config->limited_color_range = true;
2445 pipe_config->lane_count =
2446 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2448 intel_dp_get_m_n(crtc, pipe_config);
2450 if (port == PORT_A) {
2451 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2452 pipe_config->port_clock = 162000;
2454 pipe_config->port_clock = 270000;
2457 pipe_config->base.adjusted_mode.crtc_clock =
2458 intel_dotclock_calculate(pipe_config->port_clock,
2459 &pipe_config->dp_m_n);
2461 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2462 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2464 * This is a big fat ugly hack.
2466 * Some machines in UEFI boot mode provide us a VBT that has 18
2467 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2468 * unknown we fail to light up. Yet the same BIOS boots up with
2469 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2470 * max, not what it tells us to use.
2472 * Note: This will still be broken if the eDP panel is not lit
2473 * up by the BIOS, and thus we can't get the mode at module
2476 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2477 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2478 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2482 static void intel_disable_dp(struct intel_encoder *encoder,
2483 struct intel_crtc_state *old_crtc_state,
2484 struct drm_connector_state *old_conn_state)
2486 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2487 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2489 if (old_crtc_state->has_audio)
2490 intel_audio_codec_disable(encoder);
2492 if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2493 intel_psr_disable(intel_dp);
2495 /* Make sure the panel is off before trying to change the mode. But also
2496 * ensure that we have vdd while we switch off the panel. */
2497 intel_edp_panel_vdd_on(intel_dp);
2498 intel_edp_backlight_off(intel_dp);
2499 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2500 intel_edp_panel_off(intel_dp);
2502 /* disable the port before the pipe on g4x */
2503 if (INTEL_GEN(dev_priv) < 5)
2504 intel_dp_link_down(intel_dp);
2507 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2508 struct intel_crtc_state *old_crtc_state,
2509 struct drm_connector_state *old_conn_state)
2511 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2512 enum port port = dp_to_dig_port(intel_dp)->port;
2514 intel_dp_link_down(intel_dp);
2516 /* Only ilk+ has port A */
2518 ironlake_edp_pll_off(intel_dp);
2521 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2522 struct intel_crtc_state *old_crtc_state,
2523 struct drm_connector_state *old_conn_state)
2525 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2527 intel_dp_link_down(intel_dp);
2530 static void chv_post_disable_dp(struct intel_encoder *encoder,
2531 struct intel_crtc_state *old_crtc_state,
2532 struct drm_connector_state *old_conn_state)
2534 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2535 struct drm_device *dev = encoder->base.dev;
2536 struct drm_i915_private *dev_priv = to_i915(dev);
2538 intel_dp_link_down(intel_dp);
2540 mutex_lock(&dev_priv->sb_lock);
2542 /* Assert data lane reset */
2543 chv_data_lane_soft_reset(encoder, true);
2545 mutex_unlock(&dev_priv->sb_lock);
2549 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2551 uint8_t dp_train_pat)
2553 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2554 struct drm_device *dev = intel_dig_port->base.base.dev;
2555 struct drm_i915_private *dev_priv = to_i915(dev);
2556 enum port port = intel_dig_port->port;
2558 if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2559 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2560 dp_train_pat & DP_TRAINING_PATTERN_MASK);
2563 uint32_t temp = I915_READ(DP_TP_CTL(port));
2565 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2566 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2568 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2570 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2571 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2572 case DP_TRAINING_PATTERN_DISABLE:
2573 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2576 case DP_TRAINING_PATTERN_1:
2577 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2579 case DP_TRAINING_PATTERN_2:
2580 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2582 case DP_TRAINING_PATTERN_3:
2583 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2586 I915_WRITE(DP_TP_CTL(port), temp);
2588 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2589 (HAS_PCH_CPT(dev) && port != PORT_A)) {
2590 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2592 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2593 case DP_TRAINING_PATTERN_DISABLE:
2594 *DP |= DP_LINK_TRAIN_OFF_CPT;
2596 case DP_TRAINING_PATTERN_1:
2597 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2599 case DP_TRAINING_PATTERN_2:
2600 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2602 case DP_TRAINING_PATTERN_3:
2603 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2604 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2609 if (IS_CHERRYVIEW(dev))
2610 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2612 *DP &= ~DP_LINK_TRAIN_MASK;
2614 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2615 case DP_TRAINING_PATTERN_DISABLE:
2616 *DP |= DP_LINK_TRAIN_OFF;
2618 case DP_TRAINING_PATTERN_1:
2619 *DP |= DP_LINK_TRAIN_PAT_1;
2621 case DP_TRAINING_PATTERN_2:
2622 *DP |= DP_LINK_TRAIN_PAT_2;
2624 case DP_TRAINING_PATTERN_3:
2625 if (IS_CHERRYVIEW(dev)) {
2626 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2628 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2629 *DP |= DP_LINK_TRAIN_PAT_2;
2636 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2637 struct intel_crtc_state *old_crtc_state)
2639 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2640 struct drm_i915_private *dev_priv = to_i915(dev);
2642 /* enable with pattern 1 (as per spec) */
2644 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2647 * Magic for VLV/CHV. We _must_ first set up the register
2648 * without actually enabling the port, and then do another
2649 * write to enable the port. Otherwise link training will
2650 * fail when the power sequencer is freshly used for this port.
2652 intel_dp->DP |= DP_PORT_EN;
2653 if (old_crtc_state->has_audio)
2654 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2656 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2657 POSTING_READ(intel_dp->output_reg);
2660 static void intel_enable_dp(struct intel_encoder *encoder,
2661 struct intel_crtc_state *pipe_config)
2663 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2664 struct drm_device *dev = encoder->base.dev;
2665 struct drm_i915_private *dev_priv = to_i915(dev);
2666 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2667 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2668 enum pipe pipe = crtc->pipe;
2670 if (WARN_ON(dp_reg & DP_PORT_EN))
2675 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2676 vlv_init_panel_power_sequencer(intel_dp);
2678 intel_dp_enable_port(intel_dp, pipe_config);
2680 edp_panel_vdd_on(intel_dp);
2681 edp_panel_on(intel_dp);
2682 edp_panel_vdd_off(intel_dp, true);
2684 pps_unlock(intel_dp);
2686 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2687 unsigned int lane_mask = 0x0;
2689 if (IS_CHERRYVIEW(dev))
2690 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2692 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2696 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2697 intel_dp_start_link_train(intel_dp);
2698 intel_dp_stop_link_train(intel_dp);
2700 if (pipe_config->has_audio) {
2701 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2703 intel_audio_codec_enable(encoder);
2707 static void g4x_enable_dp(struct intel_encoder *encoder,
2708 struct intel_crtc_state *pipe_config,
2709 struct drm_connector_state *conn_state)
2711 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2713 intel_enable_dp(encoder, pipe_config);
2714 intel_edp_backlight_on(intel_dp);
2717 static void vlv_enable_dp(struct intel_encoder *encoder,
2718 struct intel_crtc_state *pipe_config,
2719 struct drm_connector_state *conn_state)
2721 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2723 intel_edp_backlight_on(intel_dp);
2724 intel_psr_enable(intel_dp);
2727 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2728 struct intel_crtc_state *pipe_config,
2729 struct drm_connector_state *conn_state)
2731 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2732 enum port port = dp_to_dig_port(intel_dp)->port;
2734 intel_dp_prepare(encoder, pipe_config);
2736 /* Only ilk+ has port A */
2738 ironlake_edp_pll_on(intel_dp, pipe_config);
2741 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2743 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2744 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2745 enum pipe pipe = intel_dp->pps_pipe;
2746 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2748 edp_panel_vdd_off_sync(intel_dp);
2751 * VLV seems to get confused when multiple power seqeuencers
2752 * have the same port selected (even if only one has power/vdd
2753 * enabled). The failure manifests as vlv_wait_port_ready() failing
2754 * CHV on the other hand doesn't seem to mind having the same port
2755 * selected in multiple power seqeuencers, but let's clear the
2756 * port select always when logically disconnecting a power sequencer
2759 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2760 pipe_name(pipe), port_name(intel_dig_port->port));
2761 I915_WRITE(pp_on_reg, 0);
2762 POSTING_READ(pp_on_reg);
2764 intel_dp->pps_pipe = INVALID_PIPE;
2767 static void vlv_steal_power_sequencer(struct drm_device *dev,
2770 struct drm_i915_private *dev_priv = to_i915(dev);
2771 struct intel_encoder *encoder;
2773 lockdep_assert_held(&dev_priv->pps_mutex);
2775 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2778 for_each_intel_encoder(dev, encoder) {
2779 struct intel_dp *intel_dp;
2782 if (encoder->type != INTEL_OUTPUT_EDP)
2785 intel_dp = enc_to_intel_dp(&encoder->base);
2786 port = dp_to_dig_port(intel_dp)->port;
2788 if (intel_dp->pps_pipe != pipe)
2791 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2792 pipe_name(pipe), port_name(port));
2794 WARN(encoder->base.crtc,
2795 "stealing pipe %c power sequencer from active eDP port %c\n",
2796 pipe_name(pipe), port_name(port));
2798 /* make sure vdd is off before we steal it */
2799 vlv_detach_power_sequencer(intel_dp);
2803 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2805 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2806 struct intel_encoder *encoder = &intel_dig_port->base;
2807 struct drm_device *dev = encoder->base.dev;
2808 struct drm_i915_private *dev_priv = to_i915(dev);
2809 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2811 lockdep_assert_held(&dev_priv->pps_mutex);
2813 if (!is_edp(intel_dp))
2816 if (intel_dp->pps_pipe == crtc->pipe)
2820 * If another power sequencer was being used on this
2821 * port previously make sure to turn off vdd there while
2822 * we still have control of it.
2824 if (intel_dp->pps_pipe != INVALID_PIPE)
2825 vlv_detach_power_sequencer(intel_dp);
2828 * We may be stealing the power
2829 * sequencer from another port.
2831 vlv_steal_power_sequencer(dev, crtc->pipe);
2833 /* now it's all ours */
2834 intel_dp->pps_pipe = crtc->pipe;
2836 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2837 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2839 /* init power sequencer on this pipe and port */
2840 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2841 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2844 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
2845 struct intel_crtc_state *pipe_config,
2846 struct drm_connector_state *conn_state)
2848 vlv_phy_pre_encoder_enable(encoder);
2850 intel_enable_dp(encoder, pipe_config);
2853 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
2854 struct intel_crtc_state *pipe_config,
2855 struct drm_connector_state *conn_state)
2857 intel_dp_prepare(encoder, pipe_config);
2859 vlv_phy_pre_pll_enable(encoder);
2862 static void chv_pre_enable_dp(struct intel_encoder *encoder,
2863 struct intel_crtc_state *pipe_config,
2864 struct drm_connector_state *conn_state)
2866 chv_phy_pre_encoder_enable(encoder);
2868 intel_enable_dp(encoder, pipe_config);
2870 /* Second common lane will stay alive on its own now */
2871 chv_phy_release_cl2_override(encoder);
2874 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
2875 struct intel_crtc_state *pipe_config,
2876 struct drm_connector_state *conn_state)
2878 intel_dp_prepare(encoder, pipe_config);
2880 chv_phy_pre_pll_enable(encoder);
2883 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
2884 struct intel_crtc_state *pipe_config,
2885 struct drm_connector_state *conn_state)
2887 chv_phy_post_pll_disable(encoder);
2891 * Fetch AUX CH registers 0x202 - 0x207 which contain
2892 * link status information
2895 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2897 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2898 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2901 /* These are source-specific values. */
2903 intel_dp_voltage_max(struct intel_dp *intel_dp)
2905 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2906 struct drm_i915_private *dev_priv = to_i915(dev);
2907 enum port port = dp_to_dig_port(intel_dp)->port;
2909 if (IS_BROXTON(dev))
2910 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2911 else if (INTEL_INFO(dev)->gen >= 9) {
2912 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
2913 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2914 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2915 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2916 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2917 else if (IS_GEN7(dev) && port == PORT_A)
2918 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2919 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2920 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2922 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2926 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2928 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2929 enum port port = dp_to_dig_port(intel_dp)->port;
2931 if (INTEL_INFO(dev)->gen >= 9) {
2932 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2934 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2936 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2938 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2940 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2942 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2944 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2945 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2946 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2947 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2949 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2950 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2951 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2954 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2956 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2957 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2958 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2959 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2960 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2961 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2962 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2963 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2964 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2966 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2968 } else if (IS_GEN7(dev) && port == PORT_A) {
2969 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2970 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2971 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2972 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2973 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2974 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2976 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2979 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2980 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2981 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2982 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2983 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2984 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2985 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2986 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2988 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2993 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
2995 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2996 unsigned long demph_reg_value, preemph_reg_value,
2997 uniqtranscale_reg_value;
2998 uint8_t train_set = intel_dp->train_set[0];
3000 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3001 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3002 preemph_reg_value = 0x0004000;
3003 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3004 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3005 demph_reg_value = 0x2B405555;
3006 uniqtranscale_reg_value = 0x552AB83A;
3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3009 demph_reg_value = 0x2B404040;
3010 uniqtranscale_reg_value = 0x5548B83A;
3012 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3013 demph_reg_value = 0x2B245555;
3014 uniqtranscale_reg_value = 0x5560B83A;
3016 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3017 demph_reg_value = 0x2B405555;
3018 uniqtranscale_reg_value = 0x5598DA3A;
3024 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3025 preemph_reg_value = 0x0002000;
3026 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3028 demph_reg_value = 0x2B404040;
3029 uniqtranscale_reg_value = 0x5552B83A;
3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3032 demph_reg_value = 0x2B404848;
3033 uniqtranscale_reg_value = 0x5580B83A;
3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3036 demph_reg_value = 0x2B404040;
3037 uniqtranscale_reg_value = 0x55ADDA3A;
3043 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3044 preemph_reg_value = 0x0000000;
3045 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3047 demph_reg_value = 0x2B305555;
3048 uniqtranscale_reg_value = 0x5570B83A;
3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3051 demph_reg_value = 0x2B2B4040;
3052 uniqtranscale_reg_value = 0x55ADDA3A;
3058 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3059 preemph_reg_value = 0x0006000;
3060 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3061 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3062 demph_reg_value = 0x1B405555;
3063 uniqtranscale_reg_value = 0x55ADDA3A;
3073 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3074 uniqtranscale_reg_value, 0);
3079 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3081 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3082 u32 deemph_reg_value, margin_reg_value;
3083 bool uniq_trans_scale = false;
3084 uint8_t train_set = intel_dp->train_set[0];
3086 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3087 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3088 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3090 deemph_reg_value = 128;
3091 margin_reg_value = 52;
3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3094 deemph_reg_value = 128;
3095 margin_reg_value = 77;
3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3098 deemph_reg_value = 128;
3099 margin_reg_value = 102;
3101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3102 deemph_reg_value = 128;
3103 margin_reg_value = 154;
3104 uniq_trans_scale = true;
3110 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3111 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3112 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3113 deemph_reg_value = 85;
3114 margin_reg_value = 78;
3116 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3117 deemph_reg_value = 85;
3118 margin_reg_value = 116;
3120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3121 deemph_reg_value = 85;
3122 margin_reg_value = 154;
3128 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3129 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3130 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3131 deemph_reg_value = 64;
3132 margin_reg_value = 104;
3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3135 deemph_reg_value = 64;
3136 margin_reg_value = 154;
3142 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3143 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3144 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3145 deemph_reg_value = 43;
3146 margin_reg_value = 154;
3156 chv_set_phy_signal_level(encoder, deemph_reg_value,
3157 margin_reg_value, uniq_trans_scale);
3163 gen4_signal_levels(uint8_t train_set)
3165 uint32_t signal_levels = 0;
3167 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3168 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3170 signal_levels |= DP_VOLTAGE_0_4;
3172 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3173 signal_levels |= DP_VOLTAGE_0_6;
3175 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3176 signal_levels |= DP_VOLTAGE_0_8;
3178 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3179 signal_levels |= DP_VOLTAGE_1_2;
3182 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3183 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3185 signal_levels |= DP_PRE_EMPHASIS_0;
3187 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3188 signal_levels |= DP_PRE_EMPHASIS_3_5;
3190 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3191 signal_levels |= DP_PRE_EMPHASIS_6;
3193 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3194 signal_levels |= DP_PRE_EMPHASIS_9_5;
3197 return signal_levels;
3200 /* Gen6's DP voltage swing and pre-emphasis control */
3202 gen6_edp_signal_levels(uint8_t train_set)
3204 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3205 DP_TRAIN_PRE_EMPHASIS_MASK);
3206 switch (signal_levels) {
3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3209 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3211 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3214 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3215 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3217 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3220 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3222 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3223 "0x%x\n", signal_levels);
3224 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3228 /* Gen7's DP voltage swing and pre-emphasis control */
3230 gen7_edp_signal_levels(uint8_t train_set)
3232 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3233 DP_TRAIN_PRE_EMPHASIS_MASK);
3234 switch (signal_levels) {
3235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3236 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3237 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3238 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3239 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3240 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3243 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3244 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3245 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3247 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3248 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3250 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3253 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3254 "0x%x\n", signal_levels);
3255 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3260 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3263 enum port port = intel_dig_port->port;
3264 struct drm_device *dev = intel_dig_port->base.base.dev;
3265 struct drm_i915_private *dev_priv = to_i915(dev);
3266 uint32_t signal_levels, mask = 0;
3267 uint8_t train_set = intel_dp->train_set[0];
3270 signal_levels = ddi_signal_levels(intel_dp);
3272 if (IS_BROXTON(dev))
3275 mask = DDI_BUF_EMP_MASK;
3276 } else if (IS_CHERRYVIEW(dev)) {
3277 signal_levels = chv_signal_levels(intel_dp);
3278 } else if (IS_VALLEYVIEW(dev)) {
3279 signal_levels = vlv_signal_levels(intel_dp);
3280 } else if (IS_GEN7(dev) && port == PORT_A) {
3281 signal_levels = gen7_edp_signal_levels(train_set);
3282 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3283 } else if (IS_GEN6(dev) && port == PORT_A) {
3284 signal_levels = gen6_edp_signal_levels(train_set);
3285 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3287 signal_levels = gen4_signal_levels(train_set);
3288 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3292 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3294 DRM_DEBUG_KMS("Using vswing level %d\n",
3295 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3296 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3297 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3298 DP_TRAIN_PRE_EMPHASIS_SHIFT);
3300 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3302 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3303 POSTING_READ(intel_dp->output_reg);
3307 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3308 uint8_t dp_train_pat)
3310 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3311 struct drm_i915_private *dev_priv =
3312 to_i915(intel_dig_port->base.base.dev);
3314 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3316 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3317 POSTING_READ(intel_dp->output_reg);
3320 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3323 struct drm_device *dev = intel_dig_port->base.base.dev;
3324 struct drm_i915_private *dev_priv = to_i915(dev);
3325 enum port port = intel_dig_port->port;
3331 val = I915_READ(DP_TP_CTL(port));
3332 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3333 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3334 I915_WRITE(DP_TP_CTL(port), val);
3337 * On PORT_A we can have only eDP in SST mode. There the only reason
3338 * we need to set idle transmission mode is to work around a HW issue
3339 * where we enable the pipe while not in idle link-training mode.
3340 * In this case there is requirement to wait for a minimum number of
3341 * idle patterns to be sent.
3346 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3347 DP_TP_STATUS_IDLE_DONE,
3348 DP_TP_STATUS_IDLE_DONE,
3350 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3354 intel_dp_link_down(struct intel_dp *intel_dp)
3356 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3357 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3358 enum port port = intel_dig_port->port;
3359 struct drm_device *dev = intel_dig_port->base.base.dev;
3360 struct drm_i915_private *dev_priv = to_i915(dev);
3361 uint32_t DP = intel_dp->DP;
3363 if (WARN_ON(HAS_DDI(dev)))
3366 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3369 DRM_DEBUG_KMS("\n");
3371 if ((IS_GEN7(dev) && port == PORT_A) ||
3372 (HAS_PCH_CPT(dev) && port != PORT_A)) {
3373 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3374 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3376 if (IS_CHERRYVIEW(dev))
3377 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3379 DP &= ~DP_LINK_TRAIN_MASK;
3380 DP |= DP_LINK_TRAIN_PAT_IDLE;
3382 I915_WRITE(intel_dp->output_reg, DP);
3383 POSTING_READ(intel_dp->output_reg);
3385 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3386 I915_WRITE(intel_dp->output_reg, DP);
3387 POSTING_READ(intel_dp->output_reg);
3390 * HW workaround for IBX, we need to move the port
3391 * to transcoder A after disabling it to allow the
3392 * matching HDMI port to be enabled on transcoder A.
3394 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3396 * We get CPU/PCH FIFO underruns on the other pipe when
3397 * doing the workaround. Sweep them under the rug.
3399 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3400 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3402 /* always enable with pattern 1 (as per spec) */
3403 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3404 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3405 I915_WRITE(intel_dp->output_reg, DP);
3406 POSTING_READ(intel_dp->output_reg);
3409 I915_WRITE(intel_dp->output_reg, DP);
3410 POSTING_READ(intel_dp->output_reg);
3412 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
3413 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3414 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3417 msleep(intel_dp->panel_power_down_delay);
3423 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3425 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3426 sizeof(intel_dp->dpcd)) < 0)
3427 return false; /* aux transfer failed */
3429 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3431 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3435 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3437 struct drm_i915_private *dev_priv =
3438 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3440 /* this function is meant to be called only once */
3441 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3443 if (!intel_dp_read_dpcd(intel_dp))
3446 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3447 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3448 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3450 /* Check if the panel supports PSR */
3451 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3453 sizeof(intel_dp->psr_dpcd));
3454 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3455 dev_priv->psr.sink_support = true;
3456 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3459 if (INTEL_GEN(dev_priv) >= 9 &&
3460 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3461 uint8_t frame_sync_cap;
3463 dev_priv->psr.sink_support = true;
3464 drm_dp_dpcd_read(&intel_dp->aux,
3465 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3466 &frame_sync_cap, 1);
3467 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3468 /* PSR2 needs frame sync as well */
3469 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3470 DRM_DEBUG_KMS("PSR2 %s on sink",
3471 dev_priv->psr.psr2_support ? "supported" : "not supported");
3474 /* Read the eDP Display control capabilities registers */
3475 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3476 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3477 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd) ==
3478 sizeof(intel_dp->edp_dpcd)))
3479 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3480 intel_dp->edp_dpcd);
3482 /* Intermediate frequency support */
3483 if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3484 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3487 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3488 sink_rates, sizeof(sink_rates));
3490 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3491 int val = le16_to_cpu(sink_rates[i]);
3496 /* Value read is in kHz while drm clock is saved in deca-kHz */
3497 intel_dp->sink_rates[i] = (val * 200) / 10;
3499 intel_dp->num_sink_rates = i;
3507 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3509 if (!intel_dp_read_dpcd(intel_dp))
3512 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3513 &intel_dp->sink_count, 1) < 0)
3517 * Sink count can change between short pulse hpd hence
3518 * a member variable in intel_dp will track any changes
3519 * between short pulse interrupts.
3521 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3524 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3525 * a dongle is present but no display. Unless we require to know
3526 * if a dongle is present or not, we don't need to update
3527 * downstream port information. So, an early return here saves
3528 * time from performing other operations which are not required.
3530 if (!is_edp(intel_dp) && !intel_dp->sink_count)
3533 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3534 DP_DWN_STRM_PORT_PRESENT))
3535 return true; /* native DP sink */
3537 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3538 return true; /* no per-port downstream info */
3540 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3541 intel_dp->downstream_ports,
3542 DP_MAX_DOWNSTREAM_PORTS) < 0)
3543 return false; /* downstream port status fetch failed */
3549 intel_dp_probe_oui(struct intel_dp *intel_dp)
3553 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3556 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3557 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3558 buf[0], buf[1], buf[2]);
3560 if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3561 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3562 buf[0], buf[1], buf[2]);
3566 intel_dp_can_mst(struct intel_dp *intel_dp)
3570 if (!i915.enable_dp_mst)
3573 if (!intel_dp->can_mst)
3576 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3579 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3582 return buf[0] & DP_MST_CAP;
3586 intel_dp_configure_mst(struct intel_dp *intel_dp)
3588 if (!i915.enable_dp_mst)
3591 if (!intel_dp->can_mst)
3594 intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3596 if (intel_dp->is_mst)
3597 DRM_DEBUG_KMS("Sink is MST capable\n");
3599 DRM_DEBUG_KMS("Sink is not MST capable\n");
3601 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3605 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3607 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3608 struct drm_device *dev = dig_port->base.base.dev;
3609 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3615 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3616 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3621 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3622 buf & ~DP_TEST_SINK_START) < 0) {
3623 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3629 intel_wait_for_vblank(dev, intel_crtc->pipe);
3631 if (drm_dp_dpcd_readb(&intel_dp->aux,
3632 DP_TEST_SINK_MISC, &buf) < 0) {
3636 count = buf & DP_TEST_COUNT_MASK;
3637 } while (--attempts && count);
3639 if (attempts == 0) {
3640 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3645 hsw_enable_ips(intel_crtc);
3649 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3651 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3652 struct drm_device *dev = dig_port->base.base.dev;
3653 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3657 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3660 if (!(buf & DP_TEST_CRC_SUPPORTED))
3663 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3666 if (buf & DP_TEST_SINK_START) {
3667 ret = intel_dp_sink_crc_stop(intel_dp);
3672 hsw_disable_ips(intel_crtc);
3674 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3675 buf | DP_TEST_SINK_START) < 0) {
3676 hsw_enable_ips(intel_crtc);
3680 intel_wait_for_vblank(dev, intel_crtc->pipe);
3684 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3686 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3687 struct drm_device *dev = dig_port->base.base.dev;
3688 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3693 ret = intel_dp_sink_crc_start(intel_dp);
3698 intel_wait_for_vblank(dev, intel_crtc->pipe);
3700 if (drm_dp_dpcd_readb(&intel_dp->aux,
3701 DP_TEST_SINK_MISC, &buf) < 0) {
3705 count = buf & DP_TEST_COUNT_MASK;
3707 } while (--attempts && count == 0);
3709 if (attempts == 0) {
3710 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3715 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3721 intel_dp_sink_crc_stop(intel_dp);
3726 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3728 return drm_dp_dpcd_read(&intel_dp->aux,
3729 DP_DEVICE_SERVICE_IRQ_VECTOR,
3730 sink_irq_vector, 1) == 1;
3734 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3738 ret = drm_dp_dpcd_read(&intel_dp->aux,
3740 sink_irq_vector, 14);
3747 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3749 uint8_t test_result = DP_TEST_ACK;
3753 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3755 uint8_t test_result = DP_TEST_NAK;
3759 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
3761 uint8_t test_result = DP_TEST_NAK;
3762 struct intel_connector *intel_connector = intel_dp->attached_connector;
3763 struct drm_connector *connector = &intel_connector->base;
3765 if (intel_connector->detect_edid == NULL ||
3766 connector->edid_corrupt ||
3767 intel_dp->aux.i2c_defer_count > 6) {
3768 /* Check EDID read for NACKs, DEFERs and corruption
3769 * (DP CTS 1.2 Core r1.1)
3770 * 4.2.2.4 : Failed EDID read, I2C_NAK
3771 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3772 * 4.2.2.6 : EDID corruption detected
3773 * Use failsafe mode for all cases
3775 if (intel_dp->aux.i2c_nack_count > 0 ||
3776 intel_dp->aux.i2c_defer_count > 0)
3777 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3778 intel_dp->aux.i2c_nack_count,
3779 intel_dp->aux.i2c_defer_count);
3780 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3782 struct edid *block = intel_connector->detect_edid;
3784 /* We have to write the checksum
3785 * of the last block read
3787 block += intel_connector->detect_edid->extensions;
3789 if (!drm_dp_dpcd_write(&intel_dp->aux,
3790 DP_TEST_EDID_CHECKSUM,
3793 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3795 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3796 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3799 /* Set test active flag here so userspace doesn't interrupt things */
3800 intel_dp->compliance_test_active = 1;
3805 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3807 uint8_t test_result = DP_TEST_NAK;
3811 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3813 uint8_t response = DP_TEST_NAK;
3817 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3819 DRM_DEBUG_KMS("Could not read test request from sink\n");
3824 case DP_TEST_LINK_TRAINING:
3825 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3826 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3827 response = intel_dp_autotest_link_training(intel_dp);
3829 case DP_TEST_LINK_VIDEO_PATTERN:
3830 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3831 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3832 response = intel_dp_autotest_video_pattern(intel_dp);
3834 case DP_TEST_LINK_EDID_READ:
3835 DRM_DEBUG_KMS("EDID test requested\n");
3836 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3837 response = intel_dp_autotest_edid(intel_dp);
3839 case DP_TEST_LINK_PHY_TEST_PATTERN:
3840 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3841 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3842 response = intel_dp_autotest_phy_pattern(intel_dp);
3845 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3850 status = drm_dp_dpcd_write(&intel_dp->aux,
3854 DRM_DEBUG_KMS("Could not write test response to sink\n");
3858 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3862 if (intel_dp->is_mst) {
3867 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3871 /* check link status - esi[10] = 0x200c */
3872 if (intel_dp->active_mst_links &&
3873 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3874 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3875 intel_dp_start_link_train(intel_dp);
3876 intel_dp_stop_link_train(intel_dp);
3879 DRM_DEBUG_KMS("got esi %3ph\n", esi);
3880 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3883 for (retry = 0; retry < 3; retry++) {
3885 wret = drm_dp_dpcd_write(&intel_dp->aux,
3886 DP_SINK_COUNT_ESI+1,
3893 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3895 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
3903 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3904 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3905 intel_dp->is_mst = false;
3906 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3907 /* send a hotplug event */
3908 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3915 intel_dp_check_link_status(struct intel_dp *intel_dp)
3917 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3918 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3919 u8 link_status[DP_LINK_STATUS_SIZE];
3921 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3923 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3924 DRM_ERROR("Failed to get link status\n");
3928 if (!intel_encoder->base.crtc)
3931 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3934 /* if link training is requested we should perform it always */
3935 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
3936 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
3937 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3938 intel_encoder->base.name);
3939 intel_dp_start_link_train(intel_dp);
3940 intel_dp_stop_link_train(intel_dp);
3945 * According to DP spec
3948 * 2. Configure link according to Receiver Capabilities
3949 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3950 * 4. Check link status on receipt of hot-plug interrupt
3952 * intel_dp_short_pulse - handles short pulse interrupts
3953 * when full detection is not required.
3954 * Returns %true if short pulse is handled and full detection
3955 * is NOT required and %false otherwise.
3958 intel_dp_short_pulse(struct intel_dp *intel_dp)
3960 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3961 u8 sink_irq_vector = 0;
3962 u8 old_sink_count = intel_dp->sink_count;
3966 * Clearing compliance test variables to allow capturing
3967 * of values for next automated test request.
3969 intel_dp->compliance_test_active = 0;
3970 intel_dp->compliance_test_type = 0;
3971 intel_dp->compliance_test_data = 0;
3974 * Now read the DPCD to see if it's actually running
3975 * If the current value of sink count doesn't match with
3976 * the value that was stored earlier or dpcd read failed
3977 * we need to do full detection
3979 ret = intel_dp_get_dpcd(intel_dp);
3981 if ((old_sink_count != intel_dp->sink_count) || !ret) {
3982 /* No need to proceed if we are going to do full detect */
3986 /* Try to read the source of the interrupt */
3987 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3988 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
3989 sink_irq_vector != 0) {
3990 /* Clear interrupt source */
3991 drm_dp_dpcd_writeb(&intel_dp->aux,
3992 DP_DEVICE_SERVICE_IRQ_VECTOR,
3995 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3996 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
3997 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3998 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4001 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4002 intel_dp_check_link_status(intel_dp);
4003 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4008 /* XXX this is probably wrong for multiple downstream ports */
4009 static enum drm_connector_status
4010 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4012 uint8_t *dpcd = intel_dp->dpcd;
4015 if (!intel_dp_get_dpcd(intel_dp))
4016 return connector_status_disconnected;
4018 if (is_edp(intel_dp))
4019 return connector_status_connected;
4021 /* if there's no downstream port, we're done */
4022 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4023 return connector_status_connected;
4025 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4026 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4027 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4029 return intel_dp->sink_count ?
4030 connector_status_connected : connector_status_disconnected;
4033 if (intel_dp_can_mst(intel_dp))
4034 return connector_status_connected;
4036 /* If no HPD, poke DDC gently */
4037 if (drm_probe_ddc(&intel_dp->aux.ddc))
4038 return connector_status_connected;
4040 /* Well we tried, say unknown for unreliable port types */
4041 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4042 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4043 if (type == DP_DS_PORT_TYPE_VGA ||
4044 type == DP_DS_PORT_TYPE_NON_EDID)
4045 return connector_status_unknown;
4047 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4048 DP_DWN_STRM_PORT_TYPE_MASK;
4049 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4050 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4051 return connector_status_unknown;
4054 /* Anything else is out of spec, warn and ignore */
4055 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4056 return connector_status_disconnected;
4059 static enum drm_connector_status
4060 edp_detect(struct intel_dp *intel_dp)
4062 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4063 enum drm_connector_status status;
4065 status = intel_panel_detect(dev);
4066 if (status == connector_status_unknown)
4067 status = connector_status_connected;
4072 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4073 struct intel_digital_port *port)
4077 switch (port->port) {
4081 bit = SDE_PORTB_HOTPLUG;
4084 bit = SDE_PORTC_HOTPLUG;
4087 bit = SDE_PORTD_HOTPLUG;
4090 MISSING_CASE(port->port);
4094 return I915_READ(SDEISR) & bit;
4097 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4098 struct intel_digital_port *port)
4102 switch (port->port) {
4106 bit = SDE_PORTB_HOTPLUG_CPT;
4109 bit = SDE_PORTC_HOTPLUG_CPT;
4112 bit = SDE_PORTD_HOTPLUG_CPT;
4115 bit = SDE_PORTE_HOTPLUG_SPT;
4118 MISSING_CASE(port->port);
4122 return I915_READ(SDEISR) & bit;
4125 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4126 struct intel_digital_port *port)
4130 switch (port->port) {
4132 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4135 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4138 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4141 MISSING_CASE(port->port);
4145 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4148 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4149 struct intel_digital_port *port)
4153 switch (port->port) {
4155 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4158 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4161 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4164 MISSING_CASE(port->port);
4168 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4171 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4172 struct intel_digital_port *intel_dig_port)
4174 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4178 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4181 bit = BXT_DE_PORT_HP_DDIA;
4184 bit = BXT_DE_PORT_HP_DDIB;
4187 bit = BXT_DE_PORT_HP_DDIC;
4194 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4198 * intel_digital_port_connected - is the specified port connected?
4199 * @dev_priv: i915 private structure
4200 * @port: the port to test
4202 * Return %true if @port is connected, %false otherwise.
4204 static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4205 struct intel_digital_port *port)
4207 if (HAS_PCH_IBX(dev_priv))
4208 return ibx_digital_port_connected(dev_priv, port);
4209 else if (HAS_PCH_SPLIT(dev_priv))
4210 return cpt_digital_port_connected(dev_priv, port);
4211 else if (IS_BROXTON(dev_priv))
4212 return bxt_digital_port_connected(dev_priv, port);
4213 else if (IS_GM45(dev_priv))
4214 return gm45_digital_port_connected(dev_priv, port);
4216 return g4x_digital_port_connected(dev_priv, port);
4219 static struct edid *
4220 intel_dp_get_edid(struct intel_dp *intel_dp)
4222 struct intel_connector *intel_connector = intel_dp->attached_connector;
4224 /* use cached edid if we have one */
4225 if (intel_connector->edid) {
4227 if (IS_ERR(intel_connector->edid))
4230 return drm_edid_duplicate(intel_connector->edid);
4232 return drm_get_edid(&intel_connector->base,
4233 &intel_dp->aux.ddc);
4237 intel_dp_set_edid(struct intel_dp *intel_dp)
4239 struct intel_connector *intel_connector = intel_dp->attached_connector;
4242 intel_dp_unset_edid(intel_dp);
4243 edid = intel_dp_get_edid(intel_dp);
4244 intel_connector->detect_edid = edid;
4246 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4247 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4249 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4253 intel_dp_unset_edid(struct intel_dp *intel_dp)
4255 struct intel_connector *intel_connector = intel_dp->attached_connector;
4257 kfree(intel_connector->detect_edid);
4258 intel_connector->detect_edid = NULL;
4260 intel_dp->has_audio = false;
4264 intel_dp_long_pulse(struct intel_connector *intel_connector)
4266 struct drm_connector *connector = &intel_connector->base;
4267 struct intel_dp *intel_dp = intel_attached_dp(connector);
4268 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4269 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4270 struct drm_device *dev = connector->dev;
4271 enum drm_connector_status status;
4272 enum intel_display_power_domain power_domain;
4273 u8 sink_irq_vector = 0;
4275 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4276 intel_display_power_get(to_i915(dev), power_domain);
4278 /* Can't disconnect eDP, but you can close the lid... */
4279 if (is_edp(intel_dp))
4280 status = edp_detect(intel_dp);
4281 else if (intel_digital_port_connected(to_i915(dev),
4282 dp_to_dig_port(intel_dp)))
4283 status = intel_dp_detect_dpcd(intel_dp);
4285 status = connector_status_disconnected;
4287 if (status != connector_status_connected) {
4288 intel_dp->compliance_test_active = 0;
4289 intel_dp->compliance_test_type = 0;
4290 intel_dp->compliance_test_data = 0;
4292 if (intel_dp->is_mst) {
4293 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4295 intel_dp->mst_mgr.mst_state);
4296 intel_dp->is_mst = false;
4297 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4304 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4305 intel_encoder->type = INTEL_OUTPUT_DP;
4307 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4308 yesno(intel_dp_source_supports_hbr2(intel_dp)),
4309 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4311 intel_dp_print_rates(intel_dp);
4313 intel_dp_probe_oui(intel_dp);
4315 intel_dp_configure_mst(intel_dp);
4317 if (intel_dp->is_mst) {
4319 * If we are in MST mode then this connector
4320 * won't appear connected or have anything
4323 status = connector_status_disconnected;
4325 } else if (connector->status == connector_status_connected) {
4327 * If display was connected already and is still connected
4328 * check links status, there has been known issues of
4329 * link loss triggerring long pulse!!!!
4331 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4332 intel_dp_check_link_status(intel_dp);
4333 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4338 * Clearing NACK and defer counts to get their exact values
4339 * while reading EDID which are required by Compliance tests
4340 * 4.2.2.4 and 4.2.2.5
4342 intel_dp->aux.i2c_nack_count = 0;
4343 intel_dp->aux.i2c_defer_count = 0;
4345 intel_dp_set_edid(intel_dp);
4347 status = connector_status_connected;
4348 intel_dp->detect_done = true;
4350 /* Try to read the source of the interrupt */
4351 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4352 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4353 sink_irq_vector != 0) {
4354 /* Clear interrupt source */
4355 drm_dp_dpcd_writeb(&intel_dp->aux,
4356 DP_DEVICE_SERVICE_IRQ_VECTOR,
4359 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4360 intel_dp_handle_test_request(intel_dp);
4361 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4362 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4366 if ((status != connector_status_connected) &&
4367 (intel_dp->is_mst == false))
4368 intel_dp_unset_edid(intel_dp);
4370 intel_display_power_put(to_i915(dev), power_domain);
4374 static enum drm_connector_status
4375 intel_dp_detect(struct drm_connector *connector, bool force)
4377 struct intel_dp *intel_dp = intel_attached_dp(connector);
4378 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4379 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4380 struct intel_connector *intel_connector = to_intel_connector(connector);
4382 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4383 connector->base.id, connector->name);
4385 if (intel_dp->is_mst) {
4386 /* MST devices are disconnected from a monitor POV */
4387 intel_dp_unset_edid(intel_dp);
4388 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4389 intel_encoder->type = INTEL_OUTPUT_DP;
4390 return connector_status_disconnected;
4393 /* If full detect is not performed yet, do a full detect */
4394 if (!intel_dp->detect_done)
4395 intel_dp_long_pulse(intel_dp->attached_connector);
4397 intel_dp->detect_done = false;
4399 if (is_edp(intel_dp) || intel_connector->detect_edid)
4400 return connector_status_connected;
4402 return connector_status_disconnected;
4406 intel_dp_force(struct drm_connector *connector)
4408 struct intel_dp *intel_dp = intel_attached_dp(connector);
4409 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4410 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4411 enum intel_display_power_domain power_domain;
4413 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4414 connector->base.id, connector->name);
4415 intel_dp_unset_edid(intel_dp);
4417 if (connector->status != connector_status_connected)
4420 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4421 intel_display_power_get(dev_priv, power_domain);
4423 intel_dp_set_edid(intel_dp);
4425 intel_display_power_put(dev_priv, power_domain);
4427 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4428 intel_encoder->type = INTEL_OUTPUT_DP;
4431 static int intel_dp_get_modes(struct drm_connector *connector)
4433 struct intel_connector *intel_connector = to_intel_connector(connector);
4436 edid = intel_connector->detect_edid;
4438 int ret = intel_connector_update_modes(connector, edid);
4443 /* if eDP has no EDID, fall back to fixed mode */
4444 if (is_edp(intel_attached_dp(connector)) &&
4445 intel_connector->panel.fixed_mode) {
4446 struct drm_display_mode *mode;
4448 mode = drm_mode_duplicate(connector->dev,
4449 intel_connector->panel.fixed_mode);
4451 drm_mode_probed_add(connector, mode);
4460 intel_dp_detect_audio(struct drm_connector *connector)
4462 bool has_audio = false;
4465 edid = to_intel_connector(connector)->detect_edid;
4467 has_audio = drm_detect_monitor_audio(edid);
4473 intel_dp_set_property(struct drm_connector *connector,
4474 struct drm_property *property,
4477 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4478 struct intel_connector *intel_connector = to_intel_connector(connector);
4479 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4480 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4483 ret = drm_object_property_set_value(&connector->base, property, val);
4487 if (property == dev_priv->force_audio_property) {
4491 if (i == intel_dp->force_audio)
4494 intel_dp->force_audio = i;
4496 if (i == HDMI_AUDIO_AUTO)
4497 has_audio = intel_dp_detect_audio(connector);
4499 has_audio = (i == HDMI_AUDIO_ON);
4501 if (has_audio == intel_dp->has_audio)
4504 intel_dp->has_audio = has_audio;
4508 if (property == dev_priv->broadcast_rgb_property) {
4509 bool old_auto = intel_dp->color_range_auto;
4510 bool old_range = intel_dp->limited_color_range;
4513 case INTEL_BROADCAST_RGB_AUTO:
4514 intel_dp->color_range_auto = true;
4516 case INTEL_BROADCAST_RGB_FULL:
4517 intel_dp->color_range_auto = false;
4518 intel_dp->limited_color_range = false;
4520 case INTEL_BROADCAST_RGB_LIMITED:
4521 intel_dp->color_range_auto = false;
4522 intel_dp->limited_color_range = true;
4528 if (old_auto == intel_dp->color_range_auto &&
4529 old_range == intel_dp->limited_color_range)
4535 if (is_edp(intel_dp) &&
4536 property == connector->dev->mode_config.scaling_mode_property) {
4537 if (val == DRM_MODE_SCALE_NONE) {
4538 DRM_DEBUG_KMS("no scaling not supported\n");
4541 if (HAS_GMCH_DISPLAY(dev_priv) &&
4542 val == DRM_MODE_SCALE_CENTER) {
4543 DRM_DEBUG_KMS("centering not supported\n");
4547 if (intel_connector->panel.fitting_mode == val) {
4548 /* the eDP scaling property is not changed */
4551 intel_connector->panel.fitting_mode = val;
4559 if (intel_encoder->base.crtc)
4560 intel_crtc_restore_mode(intel_encoder->base.crtc);
4566 intel_dp_connector_register(struct drm_connector *connector)
4568 struct intel_dp *intel_dp = intel_attached_dp(connector);
4571 ret = intel_connector_register(connector);
4575 i915_debugfs_connector_add(connector);
4577 DRM_DEBUG_KMS("registering %s bus for %s\n",
4578 intel_dp->aux.name, connector->kdev->kobj.name);
4580 intel_dp->aux.dev = connector->kdev;
4581 return drm_dp_aux_register(&intel_dp->aux);
4585 intel_dp_connector_unregister(struct drm_connector *connector)
4587 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4588 intel_connector_unregister(connector);
4592 intel_dp_connector_destroy(struct drm_connector *connector)
4594 struct intel_connector *intel_connector = to_intel_connector(connector);
4596 kfree(intel_connector->detect_edid);
4598 if (!IS_ERR_OR_NULL(intel_connector->edid))
4599 kfree(intel_connector->edid);
4601 /* Can't call is_edp() since the encoder may have been destroyed
4603 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4604 intel_panel_fini(&intel_connector->panel);
4606 drm_connector_cleanup(connector);
4610 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4612 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4613 struct intel_dp *intel_dp = &intel_dig_port->dp;
4615 intel_dp_mst_encoder_cleanup(intel_dig_port);
4616 if (is_edp(intel_dp)) {
4617 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4619 * vdd might still be enabled do to the delayed vdd off.
4620 * Make sure vdd is actually turned off here.
4623 edp_panel_vdd_off_sync(intel_dp);
4624 pps_unlock(intel_dp);
4626 if (intel_dp->edp_notifier.notifier_call) {
4627 unregister_reboot_notifier(&intel_dp->edp_notifier);
4628 intel_dp->edp_notifier.notifier_call = NULL;
4632 intel_dp_aux_fini(intel_dp);
4634 drm_encoder_cleanup(encoder);
4635 kfree(intel_dig_port);
4638 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4640 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4642 if (!is_edp(intel_dp))
4646 * vdd might still be enabled do to the delayed vdd off.
4647 * Make sure vdd is actually turned off here.
4649 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4651 edp_panel_vdd_off_sync(intel_dp);
4652 pps_unlock(intel_dp);
4655 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4657 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4658 struct drm_device *dev = intel_dig_port->base.base.dev;
4659 struct drm_i915_private *dev_priv = to_i915(dev);
4660 enum intel_display_power_domain power_domain;
4662 lockdep_assert_held(&dev_priv->pps_mutex);
4664 if (!edp_have_panel_vdd(intel_dp))
4668 * The VDD bit needs a power domain reference, so if the bit is
4669 * already enabled when we boot or resume, grab this reference and
4670 * schedule a vdd off, so we don't hold on to the reference
4673 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4674 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4675 intel_display_power_get(dev_priv, power_domain);
4677 edp_panel_vdd_schedule_off(intel_dp);
4680 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4682 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4683 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4685 if (!HAS_DDI(dev_priv))
4686 intel_dp->DP = I915_READ(intel_dp->output_reg);
4688 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4693 /* Reinit the power sequencer, in case BIOS did something with it. */
4694 intel_dp_pps_init(encoder->dev, intel_dp);
4695 intel_edp_panel_vdd_sanitize(intel_dp);
4697 pps_unlock(intel_dp);
4700 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4701 .dpms = drm_atomic_helper_connector_dpms,
4702 .detect = intel_dp_detect,
4703 .force = intel_dp_force,
4704 .fill_modes = drm_helper_probe_single_connector_modes,
4705 .set_property = intel_dp_set_property,
4706 .atomic_get_property = intel_connector_atomic_get_property,
4707 .late_register = intel_dp_connector_register,
4708 .early_unregister = intel_dp_connector_unregister,
4709 .destroy = intel_dp_connector_destroy,
4710 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4711 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4714 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4715 .get_modes = intel_dp_get_modes,
4716 .mode_valid = intel_dp_mode_valid,
4719 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4720 .reset = intel_dp_encoder_reset,
4721 .destroy = intel_dp_encoder_destroy,
4725 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4727 struct intel_dp *intel_dp = &intel_dig_port->dp;
4728 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4729 struct drm_device *dev = intel_dig_port->base.base.dev;
4730 struct drm_i915_private *dev_priv = to_i915(dev);
4731 enum intel_display_power_domain power_domain;
4732 enum irqreturn ret = IRQ_NONE;
4734 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4735 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4736 intel_dig_port->base.type = INTEL_OUTPUT_DP;
4738 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4740 * vdd off can generate a long pulse on eDP which
4741 * would require vdd on to handle it, and thus we
4742 * would end up in an endless cycle of
4743 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4745 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4746 port_name(intel_dig_port->port));
4750 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4751 port_name(intel_dig_port->port),
4752 long_hpd ? "long" : "short");
4754 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4755 intel_display_power_get(dev_priv, power_domain);
4758 intel_dp_long_pulse(intel_dp->attached_connector);
4759 if (intel_dp->is_mst)
4764 if (intel_dp->is_mst) {
4765 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4767 * If we were in MST mode, and device is not
4768 * there, get out of MST mode
4770 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4771 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4772 intel_dp->is_mst = false;
4773 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4779 if (!intel_dp->is_mst) {
4780 if (!intel_dp_short_pulse(intel_dp)) {
4781 intel_dp_long_pulse(intel_dp->attached_connector);
4790 intel_display_power_put(dev_priv, power_domain);
4795 /* check the VBT to see whether the eDP is on another port */
4796 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4798 struct drm_i915_private *dev_priv = to_i915(dev);
4801 * eDP not supported on g4x. so bail out early just
4802 * for a bit extra safety in case the VBT is bonkers.
4804 if (INTEL_INFO(dev)->gen < 5)
4810 return intel_bios_is_port_edp(dev_priv, port);
4814 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4816 struct intel_connector *intel_connector = to_intel_connector(connector);
4818 intel_attach_force_audio_property(connector);
4819 intel_attach_broadcast_rgb_property(connector);
4820 intel_dp->color_range_auto = true;
4822 if (is_edp(intel_dp)) {
4823 drm_mode_create_scaling_mode_property(connector->dev);
4824 drm_object_attach_property(
4826 connector->dev->mode_config.scaling_mode_property,
4827 DRM_MODE_SCALE_ASPECT);
4828 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4832 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4834 intel_dp->panel_power_off_time = ktime_get_boottime();
4835 intel_dp->last_power_on = jiffies;
4836 intel_dp->last_backlight_off = jiffies;
4840 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
4841 struct intel_dp *intel_dp, struct edp_power_seq *seq)
4843 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
4844 struct pps_registers regs;
4846 intel_pps_get_registers(dev_priv, intel_dp, ®s);
4848 /* Workaround: Need to write PP_CONTROL with the unlock key as
4849 * the very first thing. */
4850 pp_ctl = ironlake_get_pp_control(intel_dp);
4852 pp_on = I915_READ(regs.pp_on);
4853 pp_off = I915_READ(regs.pp_off);
4854 if (!IS_BROXTON(dev_priv)) {
4855 I915_WRITE(regs.pp_ctrl, pp_ctl);
4856 pp_div = I915_READ(regs.pp_div);
4859 /* Pull timing values out of registers */
4860 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4861 PANEL_POWER_UP_DELAY_SHIFT;
4863 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4864 PANEL_LIGHT_ON_DELAY_SHIFT;
4866 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4867 PANEL_LIGHT_OFF_DELAY_SHIFT;
4869 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4870 PANEL_POWER_DOWN_DELAY_SHIFT;
4872 if (IS_BROXTON(dev_priv)) {
4873 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4874 BXT_POWER_CYCLE_DELAY_SHIFT;
4876 seq->t11_t12 = (tmp - 1) * 1000;
4880 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4881 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4886 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
4888 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4890 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
4894 intel_pps_verify_state(struct drm_i915_private *dev_priv,
4895 struct intel_dp *intel_dp)
4897 struct edp_power_seq hw;
4898 struct edp_power_seq *sw = &intel_dp->pps_delays;
4900 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
4902 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
4903 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
4904 DRM_ERROR("PPS state mismatch\n");
4905 intel_pps_dump_state("sw", sw);
4906 intel_pps_dump_state("hw", &hw);
4911 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4912 struct intel_dp *intel_dp)
4914 struct drm_i915_private *dev_priv = to_i915(dev);
4915 struct edp_power_seq cur, vbt, spec,
4916 *final = &intel_dp->pps_delays;
4918 lockdep_assert_held(&dev_priv->pps_mutex);
4920 /* already initialized? */
4921 if (final->t11_t12 != 0)
4924 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
4926 intel_pps_dump_state("cur", &cur);
4928 vbt = dev_priv->vbt.edp.pps;
4930 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4931 * our hw here, which are all in 100usec. */
4932 spec.t1_t3 = 210 * 10;
4933 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4934 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4935 spec.t10 = 500 * 10;
4936 /* This one is special and actually in units of 100ms, but zero
4937 * based in the hw (so we need to add 100 ms). But the sw vbt
4938 * table multiplies it with 1000 to make it in units of 100usec,
4940 spec.t11_t12 = (510 + 100) * 10;
4942 intel_pps_dump_state("vbt", &vbt);
4944 /* Use the max of the register settings and vbt. If both are
4945 * unset, fall back to the spec limits. */
4946 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
4948 max(cur.field, vbt.field))
4949 assign_final(t1_t3);
4953 assign_final(t11_t12);
4956 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
4957 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4958 intel_dp->backlight_on_delay = get_delay(t8);
4959 intel_dp->backlight_off_delay = get_delay(t9);
4960 intel_dp->panel_power_down_delay = get_delay(t10);
4961 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4964 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4965 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4966 intel_dp->panel_power_cycle_delay);
4968 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4969 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4972 * We override the HW backlight delays to 1 because we do manual waits
4973 * on them. For T8, even BSpec recommends doing it. For T9, if we
4974 * don't do this, we'll end up waiting for the backlight off delay
4975 * twice: once when we do the manual sleep, and once when we disable
4976 * the panel and wait for the PP_STATUS bit to become zero.
4983 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4984 struct intel_dp *intel_dp)
4986 struct drm_i915_private *dev_priv = to_i915(dev);
4987 u32 pp_on, pp_off, pp_div, port_sel = 0;
4988 int div = dev_priv->rawclk_freq / 1000;
4989 struct pps_registers regs;
4990 enum port port = dp_to_dig_port(intel_dp)->port;
4991 const struct edp_power_seq *seq = &intel_dp->pps_delays;
4993 lockdep_assert_held(&dev_priv->pps_mutex);
4995 intel_pps_get_registers(dev_priv, intel_dp, ®s);
4997 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4998 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
4999 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5000 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5001 /* Compute the divisor for the pp clock, simply match the Bspec
5003 if (IS_BROXTON(dev)) {
5004 pp_div = I915_READ(regs.pp_ctrl);
5005 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5006 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5007 << BXT_POWER_CYCLE_DELAY_SHIFT);
5009 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5010 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5011 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5014 /* Haswell doesn't have any port selection bits for the panel
5015 * power sequencer any more. */
5016 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5017 port_sel = PANEL_PORT_SELECT_VLV(port);
5018 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5020 port_sel = PANEL_PORT_SELECT_DPA;
5022 port_sel = PANEL_PORT_SELECT_DPD;
5027 I915_WRITE(regs.pp_on, pp_on);
5028 I915_WRITE(regs.pp_off, pp_off);
5029 if (IS_BROXTON(dev))
5030 I915_WRITE(regs.pp_ctrl, pp_div);
5032 I915_WRITE(regs.pp_div, pp_div);
5034 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5035 I915_READ(regs.pp_on),
5036 I915_READ(regs.pp_off),
5038 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5039 I915_READ(regs.pp_div));
5042 static void intel_dp_pps_init(struct drm_device *dev,
5043 struct intel_dp *intel_dp)
5045 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5046 vlv_initial_power_sequencer_setup(intel_dp);
5048 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5049 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5054 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5055 * @dev_priv: i915 device
5056 * @crtc_state: a pointer to the active intel_crtc_state
5057 * @refresh_rate: RR to be programmed
5059 * This function gets called when refresh rate (RR) has to be changed from
5060 * one frequency to another. Switches can be between high and low RR
5061 * supported by the panel or to any other RR based on media playback (in
5062 * this case, RR value needs to be passed from user space).
5064 * The caller of this function needs to take a lock on dev_priv->drrs.
5066 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5067 struct intel_crtc_state *crtc_state,
5070 struct intel_encoder *encoder;
5071 struct intel_digital_port *dig_port = NULL;
5072 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5074 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5076 if (refresh_rate <= 0) {
5077 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5081 if (intel_dp == NULL) {
5082 DRM_DEBUG_KMS("DRRS not supported.\n");
5087 * FIXME: This needs proper synchronization with psr state for some
5088 * platforms that cannot have PSR and DRRS enabled at the same time.
5091 dig_port = dp_to_dig_port(intel_dp);
5092 encoder = &dig_port->base;
5093 intel_crtc = to_intel_crtc(encoder->base.crtc);
5096 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5100 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5101 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5105 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5107 index = DRRS_LOW_RR;
5109 if (index == dev_priv->drrs.refresh_rate_type) {
5111 "DRRS requested for previously set RR...ignoring\n");
5115 if (!crtc_state->base.active) {
5116 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5120 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5123 intel_dp_set_m_n(intel_crtc, M1_N1);
5126 intel_dp_set_m_n(intel_crtc, M2_N2);
5130 DRM_ERROR("Unsupported refreshrate type\n");
5132 } else if (INTEL_GEN(dev_priv) > 6) {
5133 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5136 val = I915_READ(reg);
5137 if (index > DRRS_HIGH_RR) {
5138 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5139 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5141 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5143 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5144 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5146 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5148 I915_WRITE(reg, val);
5151 dev_priv->drrs.refresh_rate_type = index;
5153 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5157 * intel_edp_drrs_enable - init drrs struct if supported
5158 * @intel_dp: DP struct
5159 * @crtc_state: A pointer to the active crtc state.
5161 * Initializes frontbuffer_bits and drrs.dp
5163 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5164 struct intel_crtc_state *crtc_state)
5166 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5167 struct drm_i915_private *dev_priv = to_i915(dev);
5169 if (!crtc_state->has_drrs) {
5170 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5174 mutex_lock(&dev_priv->drrs.mutex);
5175 if (WARN_ON(dev_priv->drrs.dp)) {
5176 DRM_ERROR("DRRS already enabled\n");
5180 dev_priv->drrs.busy_frontbuffer_bits = 0;
5182 dev_priv->drrs.dp = intel_dp;
5185 mutex_unlock(&dev_priv->drrs.mutex);
5189 * intel_edp_drrs_disable - Disable DRRS
5190 * @intel_dp: DP struct
5191 * @old_crtc_state: Pointer to old crtc_state.
5194 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5195 struct intel_crtc_state *old_crtc_state)
5197 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5198 struct drm_i915_private *dev_priv = to_i915(dev);
5200 if (!old_crtc_state->has_drrs)
5203 mutex_lock(&dev_priv->drrs.mutex);
5204 if (!dev_priv->drrs.dp) {
5205 mutex_unlock(&dev_priv->drrs.mutex);
5209 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5210 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5211 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5213 dev_priv->drrs.dp = NULL;
5214 mutex_unlock(&dev_priv->drrs.mutex);
5216 cancel_delayed_work_sync(&dev_priv->drrs.work);
5219 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5221 struct drm_i915_private *dev_priv =
5222 container_of(work, typeof(*dev_priv), drrs.work.work);
5223 struct intel_dp *intel_dp;
5225 mutex_lock(&dev_priv->drrs.mutex);
5227 intel_dp = dev_priv->drrs.dp;
5233 * The delayed work can race with an invalidate hence we need to
5237 if (dev_priv->drrs.busy_frontbuffer_bits)
5240 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5241 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5243 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5244 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5248 mutex_unlock(&dev_priv->drrs.mutex);
5252 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5253 * @dev_priv: i915 device
5254 * @frontbuffer_bits: frontbuffer plane tracking bits
5256 * This function gets called everytime rendering on the given planes start.
5257 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5259 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5261 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5262 unsigned int frontbuffer_bits)
5264 struct drm_crtc *crtc;
5267 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5270 cancel_delayed_work(&dev_priv->drrs.work);
5272 mutex_lock(&dev_priv->drrs.mutex);
5273 if (!dev_priv->drrs.dp) {
5274 mutex_unlock(&dev_priv->drrs.mutex);
5278 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5279 pipe = to_intel_crtc(crtc)->pipe;
5281 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5282 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5284 /* invalidate means busy screen hence upclock */
5285 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5286 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5287 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5289 mutex_unlock(&dev_priv->drrs.mutex);
5293 * intel_edp_drrs_flush - Restart Idleness DRRS
5294 * @dev_priv: i915 device
5295 * @frontbuffer_bits: frontbuffer plane tracking bits
5297 * This function gets called every time rendering on the given planes has
5298 * completed or flip on a crtc is completed. So DRRS should be upclocked
5299 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5300 * if no other planes are dirty.
5302 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5304 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5305 unsigned int frontbuffer_bits)
5307 struct drm_crtc *crtc;
5310 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5313 cancel_delayed_work(&dev_priv->drrs.work);
5315 mutex_lock(&dev_priv->drrs.mutex);
5316 if (!dev_priv->drrs.dp) {
5317 mutex_unlock(&dev_priv->drrs.mutex);
5321 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5322 pipe = to_intel_crtc(crtc)->pipe;
5324 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5325 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5327 /* flush means busy screen hence upclock */
5328 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5329 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5330 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5333 * flush also means no more activity hence schedule downclock, if all
5334 * other fbs are quiescent too
5336 if (!dev_priv->drrs.busy_frontbuffer_bits)
5337 schedule_delayed_work(&dev_priv->drrs.work,
5338 msecs_to_jiffies(1000));
5339 mutex_unlock(&dev_priv->drrs.mutex);
5343 * DOC: Display Refresh Rate Switching (DRRS)
5345 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5346 * which enables swtching between low and high refresh rates,
5347 * dynamically, based on the usage scenario. This feature is applicable
5348 * for internal panels.
5350 * Indication that the panel supports DRRS is given by the panel EDID, which
5351 * would list multiple refresh rates for one resolution.
5353 * DRRS is of 2 types - static and seamless.
5354 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5355 * (may appear as a blink on screen) and is used in dock-undock scenario.
5356 * Seamless DRRS involves changing RR without any visual effect to the user
5357 * and can be used during normal system usage. This is done by programming
5358 * certain registers.
5360 * Support for static/seamless DRRS may be indicated in the VBT based on
5361 * inputs from the panel spec.
5363 * DRRS saves power by switching to low RR based on usage scenarios.
5365 * The implementation is based on frontbuffer tracking implementation. When
5366 * there is a disturbance on the screen triggered by user activity or a periodic
5367 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5368 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5371 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5372 * and intel_edp_drrs_flush() are called.
5374 * DRRS can be further extended to support other internal panels and also
5375 * the scenario of video playback wherein RR is set based on the rate
5376 * requested by userspace.
5380 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5381 * @intel_connector: eDP connector
5382 * @fixed_mode: preferred mode of panel
5384 * This function is called only once at driver load to initialize basic
5388 * Downclock mode if panel supports it, else return NULL.
5389 * DRRS support is determined by the presence of downclock mode (apart
5390 * from VBT setting).
5392 static struct drm_display_mode *
5393 intel_dp_drrs_init(struct intel_connector *intel_connector,
5394 struct drm_display_mode *fixed_mode)
5396 struct drm_connector *connector = &intel_connector->base;
5397 struct drm_device *dev = connector->dev;
5398 struct drm_i915_private *dev_priv = to_i915(dev);
5399 struct drm_display_mode *downclock_mode = NULL;
5401 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5402 mutex_init(&dev_priv->drrs.mutex);
5404 if (INTEL_INFO(dev)->gen <= 6) {
5405 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5409 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5410 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5414 downclock_mode = intel_find_panel_downclock
5415 (dev, fixed_mode, connector);
5417 if (!downclock_mode) {
5418 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5422 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5424 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5425 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5426 return downclock_mode;
5429 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5430 struct intel_connector *intel_connector)
5432 struct drm_connector *connector = &intel_connector->base;
5433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5434 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5435 struct drm_device *dev = intel_encoder->base.dev;
5436 struct drm_i915_private *dev_priv = to_i915(dev);
5437 struct drm_display_mode *fixed_mode = NULL;
5438 struct drm_display_mode *downclock_mode = NULL;
5440 struct drm_display_mode *scan;
5442 enum pipe pipe = INVALID_PIPE;
5444 if (!is_edp(intel_dp))
5448 * On IBX/CPT we may get here with LVDS already registered. Since the
5449 * driver uses the only internal power sequencer available for both
5450 * eDP and LVDS bail out early in this case to prevent interfering
5451 * with an already powered-on LVDS power sequencer.
5453 if (intel_get_lvds_encoder(dev)) {
5454 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5455 DRM_INFO("LVDS was detected, not registering eDP\n");
5462 intel_dp_init_panel_power_timestamps(intel_dp);
5463 intel_dp_pps_init(dev, intel_dp);
5464 intel_edp_panel_vdd_sanitize(intel_dp);
5466 pps_unlock(intel_dp);
5468 /* Cache DPCD and EDID for edp. */
5469 has_dpcd = intel_edp_init_dpcd(intel_dp);
5472 /* if this fails, presume the device is a ghost */
5473 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5477 mutex_lock(&dev->mode_config.mutex);
5478 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5480 if (drm_add_edid_modes(connector, edid)) {
5481 drm_mode_connector_update_edid_property(connector,
5483 drm_edid_to_eld(connector, edid);
5486 edid = ERR_PTR(-EINVAL);
5489 edid = ERR_PTR(-ENOENT);
5491 intel_connector->edid = edid;
5493 /* prefer fixed mode from EDID if available */
5494 list_for_each_entry(scan, &connector->probed_modes, head) {
5495 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5496 fixed_mode = drm_mode_duplicate(dev, scan);
5497 downclock_mode = intel_dp_drrs_init(
5498 intel_connector, fixed_mode);
5503 /* fallback to VBT if available for eDP */
5504 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5505 fixed_mode = drm_mode_duplicate(dev,
5506 dev_priv->vbt.lfp_lvds_vbt_mode);
5508 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5509 connector->display_info.width_mm = fixed_mode->width_mm;
5510 connector->display_info.height_mm = fixed_mode->height_mm;
5513 mutex_unlock(&dev->mode_config.mutex);
5515 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5516 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5517 register_reboot_notifier(&intel_dp->edp_notifier);
5520 * Figure out the current pipe for the initial backlight setup.
5521 * If the current pipe isn't valid, try the PPS pipe, and if that
5522 * fails just assume pipe A.
5524 if (IS_CHERRYVIEW(dev))
5525 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5527 pipe = PORT_TO_PIPE(intel_dp->DP);
5529 if (pipe != PIPE_A && pipe != PIPE_B)
5530 pipe = intel_dp->pps_pipe;
5532 if (pipe != PIPE_A && pipe != PIPE_B)
5535 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5539 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5540 intel_connector->panel.backlight.power = intel_edp_backlight_power;
5541 intel_panel_setup_backlight(connector, pipe);
5546 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5548 * vdd might still be enabled do to the delayed vdd off.
5549 * Make sure vdd is actually turned off here.
5552 edp_panel_vdd_off_sync(intel_dp);
5553 pps_unlock(intel_dp);
5559 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5560 struct intel_connector *intel_connector)
5562 struct drm_connector *connector = &intel_connector->base;
5563 struct intel_dp *intel_dp = &intel_dig_port->dp;
5564 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5565 struct drm_device *dev = intel_encoder->base.dev;
5566 struct drm_i915_private *dev_priv = to_i915(dev);
5567 enum port port = intel_dig_port->port;
5570 if (WARN(intel_dig_port->max_lanes < 1,
5571 "Not enough lanes (%d) for DP on port %c\n",
5572 intel_dig_port->max_lanes, port_name(port)))
5575 intel_dp->pps_pipe = INVALID_PIPE;
5577 /* intel_dp vfuncs */
5578 if (INTEL_INFO(dev)->gen >= 9)
5579 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5580 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5581 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5582 else if (HAS_PCH_SPLIT(dev))
5583 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5585 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5587 if (INTEL_INFO(dev)->gen >= 9)
5588 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5590 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5593 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5595 /* Preserve the current hw state. */
5596 intel_dp->DP = I915_READ(intel_dp->output_reg);
5597 intel_dp->attached_connector = intel_connector;
5599 if (intel_dp_is_edp(dev, port))
5600 type = DRM_MODE_CONNECTOR_eDP;
5602 type = DRM_MODE_CONNECTOR_DisplayPort;
5605 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5606 * for DP the encoder type can be set by the caller to
5607 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5609 if (type == DRM_MODE_CONNECTOR_eDP)
5610 intel_encoder->type = INTEL_OUTPUT_EDP;
5612 /* eDP only on port B and/or C on vlv/chv */
5613 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5614 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5617 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5618 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5621 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5622 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5624 connector->interlace_allowed = true;
5625 connector->doublescan_allowed = 0;
5627 intel_dp_aux_init(intel_dp);
5629 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5630 edp_panel_vdd_work);
5632 intel_connector_attach_encoder(intel_connector, intel_encoder);
5635 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5637 intel_connector->get_hw_state = intel_connector_get_hw_state;
5639 /* Set up the hotplug pin. */
5642 intel_encoder->hpd_pin = HPD_PORT_A;
5645 intel_encoder->hpd_pin = HPD_PORT_B;
5646 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
5647 intel_encoder->hpd_pin = HPD_PORT_A;
5650 intel_encoder->hpd_pin = HPD_PORT_C;
5653 intel_encoder->hpd_pin = HPD_PORT_D;
5656 intel_encoder->hpd_pin = HPD_PORT_E;
5662 /* init MST on ports that can support it */
5663 if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
5664 (port == PORT_B || port == PORT_C || port == PORT_D))
5665 intel_dp_mst_encoder_init(intel_dig_port,
5666 intel_connector->base.base.id);
5668 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5669 intel_dp_aux_fini(intel_dp);
5670 intel_dp_mst_encoder_cleanup(intel_dig_port);
5674 intel_dp_add_properties(intel_dp, connector);
5676 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5677 * 0xd. Failure to do so will result in spurious interrupts being
5678 * generated on the port when a cable is not attached.
5680 if (IS_G4X(dev) && !IS_GM45(dev)) {
5681 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5682 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5688 drm_connector_cleanup(connector);
5693 bool intel_dp_init(struct drm_device *dev,
5694 i915_reg_t output_reg,
5697 struct drm_i915_private *dev_priv = to_i915(dev);
5698 struct intel_digital_port *intel_dig_port;
5699 struct intel_encoder *intel_encoder;
5700 struct drm_encoder *encoder;
5701 struct intel_connector *intel_connector;
5703 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5704 if (!intel_dig_port)
5707 intel_connector = intel_connector_alloc();
5708 if (!intel_connector)
5709 goto err_connector_alloc;
5711 intel_encoder = &intel_dig_port->base;
5712 encoder = &intel_encoder->base;
5714 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5715 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
5716 goto err_encoder_init;
5718 intel_encoder->compute_config = intel_dp_compute_config;
5719 intel_encoder->disable = intel_disable_dp;
5720 intel_encoder->get_hw_state = intel_dp_get_hw_state;
5721 intel_encoder->get_config = intel_dp_get_config;
5722 intel_encoder->suspend = intel_dp_encoder_suspend;
5723 if (IS_CHERRYVIEW(dev)) {
5724 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5725 intel_encoder->pre_enable = chv_pre_enable_dp;
5726 intel_encoder->enable = vlv_enable_dp;
5727 intel_encoder->post_disable = chv_post_disable_dp;
5728 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
5729 } else if (IS_VALLEYVIEW(dev)) {
5730 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5731 intel_encoder->pre_enable = vlv_pre_enable_dp;
5732 intel_encoder->enable = vlv_enable_dp;
5733 intel_encoder->post_disable = vlv_post_disable_dp;
5735 intel_encoder->pre_enable = g4x_pre_enable_dp;
5736 intel_encoder->enable = g4x_enable_dp;
5737 if (INTEL_INFO(dev)->gen >= 5)
5738 intel_encoder->post_disable = ilk_post_disable_dp;
5741 intel_dig_port->port = port;
5742 intel_dig_port->dp.output_reg = output_reg;
5743 intel_dig_port->max_lanes = 4;
5745 intel_encoder->type = INTEL_OUTPUT_DP;
5746 if (IS_CHERRYVIEW(dev)) {
5748 intel_encoder->crtc_mask = 1 << 2;
5750 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5752 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5754 intel_encoder->cloneable = 0;
5756 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5757 dev_priv->hotplug.irq_port[port] = intel_dig_port;
5759 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5760 goto err_init_connector;
5765 drm_encoder_cleanup(encoder);
5767 kfree(intel_connector);
5768 err_connector_alloc:
5769 kfree(intel_dig_port);
5773 void intel_dp_mst_suspend(struct drm_device *dev)
5775 struct drm_i915_private *dev_priv = to_i915(dev);
5779 for (i = 0; i < I915_MAX_PORTS; i++) {
5780 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5782 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5785 if (intel_dig_port->dp.is_mst)
5786 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5790 void intel_dp_mst_resume(struct drm_device *dev)
5792 struct drm_i915_private *dev_priv = to_i915(dev);
5795 for (i = 0; i < I915_MAX_PORTS; i++) {
5796 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5799 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5802 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5804 intel_dp_check_mst_status(&intel_dig_port->dp);