2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
48 static bool is_edp(struct intel_dp *intel_dp)
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
55 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
59 return intel_dig_port->base.base.dev;
63 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
64 * @intel_dp: DP struct
66 * Returns true if the given DP struct corresponds to a CPU eDP port.
68 static bool is_cpu_edp(struct intel_dp *intel_dp)
70 struct drm_device *dev = intel_dp_to_dev(intel_dp);
71 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
72 enum port port = intel_dig_port->port;
74 return is_edp(intel_dp) &&
75 (port == PORT_A || (port == PORT_C && IS_VALLEYVIEW(dev)));
78 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
80 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
83 static void intel_dp_link_down(struct intel_dp *intel_dp);
86 intel_dp_max_link_bw(struct intel_dp *intel_dp)
88 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
90 switch (max_link_bw) {
95 max_link_bw = DP_LINK_BW_1_62;
102 * The units on the numbers in the next two are... bizarre. Examples will
103 * make it clearer; this one parallels an example in the eDP spec.
105 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
107 * 270000 * 1 * 8 / 10 == 216000
109 * The actual data capacity of that configuration is 2.16Gbit/s, so the
110 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
111 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
112 * 119000. At 18bpp that's 2142000 kilobits per second.
114 * Thus the strange-looking division by 10 in intel_dp_link_required, to
115 * get the result in decakilobits instead of kilobits.
119 intel_dp_link_required(int pixel_clock, int bpp)
121 return (pixel_clock * bpp + 9) / 10;
125 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
127 return (max_link_clock * max_lanes * 8) / 10;
131 intel_dp_mode_valid(struct drm_connector *connector,
132 struct drm_display_mode *mode)
134 struct intel_dp *intel_dp = intel_attached_dp(connector);
135 struct intel_connector *intel_connector = to_intel_connector(connector);
136 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
137 int target_clock = mode->clock;
138 int max_rate, mode_rate, max_lanes, max_link_clock;
140 if (is_edp(intel_dp) && fixed_mode) {
141 if (mode->hdisplay > fixed_mode->hdisplay)
144 if (mode->vdisplay > fixed_mode->vdisplay)
147 target_clock = fixed_mode->clock;
150 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
151 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
153 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
154 mode_rate = intel_dp_link_required(target_clock, 18);
156 if (mode_rate > max_rate)
157 return MODE_CLOCK_HIGH;
159 if (mode->clock < 10000)
160 return MODE_CLOCK_LOW;
162 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
163 return MODE_H_ILLEGAL;
169 pack_aux(uint8_t *src, int src_bytes)
176 for (i = 0; i < src_bytes; i++)
177 v |= ((uint32_t) src[i]) << ((3-i) * 8);
182 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
187 for (i = 0; i < dst_bytes; i++)
188 dst[i] = src >> ((3-i) * 8);
191 /* hrawclock is 1/4 the FSB frequency */
193 intel_hrawclk(struct drm_device *dev)
195 struct drm_i915_private *dev_priv = dev->dev_private;
198 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
199 if (IS_VALLEYVIEW(dev))
202 clkcfg = I915_READ(CLKCFG);
203 switch (clkcfg & CLKCFG_FSB_MASK) {
212 case CLKCFG_FSB_1067:
214 case CLKCFG_FSB_1333:
216 /* these two are just a guess; one of them might be right */
217 case CLKCFG_FSB_1600:
218 case CLKCFG_FSB_1600_ALT:
225 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
227 struct drm_device *dev = intel_dp_to_dev(intel_dp);
228 struct drm_i915_private *dev_priv = dev->dev_private;
231 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
232 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
235 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
237 struct drm_device *dev = intel_dp_to_dev(intel_dp);
238 struct drm_i915_private *dev_priv = dev->dev_private;
241 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
242 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
246 intel_dp_check_edp(struct intel_dp *intel_dp)
248 struct drm_device *dev = intel_dp_to_dev(intel_dp);
249 struct drm_i915_private *dev_priv = dev->dev_private;
250 u32 pp_stat_reg, pp_ctrl_reg;
252 if (!is_edp(intel_dp))
255 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
256 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
258 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
259 WARN(1, "eDP powered off while attempting aux channel communication.\n");
260 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
261 I915_READ(pp_stat_reg),
262 I915_READ(pp_ctrl_reg));
267 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
269 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
270 struct drm_device *dev = intel_dig_port->base.base.dev;
271 struct drm_i915_private *dev_priv = dev->dev_private;
272 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
276 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
278 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
279 msecs_to_jiffies(10));
281 done = wait_for_atomic(C, 10) == 0;
283 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
291 intel_dp_aux_ch(struct intel_dp *intel_dp,
292 uint8_t *send, int send_bytes,
293 uint8_t *recv, int recv_size)
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct drm_device *dev = intel_dig_port->base.base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
299 uint32_t ch_data = ch_ctl + 4;
300 int i, ret, recv_bytes;
302 uint32_t aux_clock_divider;
304 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
306 /* dp aux is extremely sensitive to irq latency, hence request the
307 * lowest possible wakeup latency and so prevent the cpu from going into
310 pm_qos_update_request(&dev_priv->pm_qos, 0);
312 intel_dp_check_edp(intel_dp);
313 /* The clock divider is based off the hrawclk,
314 * and would like to run at 2MHz. So, take the
315 * hrawclk value and divide by 2 and use that
317 * Note that PCH attached eDP panels should use a 125MHz input
320 if (is_cpu_edp(intel_dp)) {
322 aux_clock_divider = DIV_ROUND_CLOSEST(
323 intel_ddi_get_cdclk_freq(dev_priv), 2000);
324 else if (IS_VALLEYVIEW(dev))
325 aux_clock_divider = 100;
326 else if (IS_GEN6(dev) || IS_GEN7(dev))
327 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
329 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
330 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
331 /* Workaround for non-ULT HSW */
332 aux_clock_divider = 74;
333 } else if (HAS_PCH_SPLIT(dev)) {
334 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
336 aux_clock_divider = intel_hrawclk(dev) / 2;
344 /* Try to wait for any previous AUX channel activity */
345 for (try = 0; try < 3; try++) {
346 status = I915_READ_NOTRACE(ch_ctl);
347 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
353 WARN(1, "dp_aux_ch not started status 0x%08x\n",
359 /* Must try at least 3 times according to DP spec */
360 for (try = 0; try < 5; try++) {
361 /* Load the send data into the aux channel data registers */
362 for (i = 0; i < send_bytes; i += 4)
363 I915_WRITE(ch_data + i,
364 pack_aux(send + i, send_bytes - i));
366 /* Send the command and wait for it to complete */
368 DP_AUX_CH_CTL_SEND_BUSY |
369 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
370 DP_AUX_CH_CTL_TIME_OUT_400us |
371 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
372 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
373 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
375 DP_AUX_CH_CTL_TIME_OUT_ERROR |
376 DP_AUX_CH_CTL_RECEIVE_ERROR);
378 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
380 /* Clear done status and any errors */
384 DP_AUX_CH_CTL_TIME_OUT_ERROR |
385 DP_AUX_CH_CTL_RECEIVE_ERROR);
387 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
388 DP_AUX_CH_CTL_RECEIVE_ERROR))
390 if (status & DP_AUX_CH_CTL_DONE)
394 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
395 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
400 /* Check for timeout or receive error.
401 * Timeouts occur when the sink is not connected
403 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
404 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
409 /* Timeouts occur when the device isn't connected, so they're
410 * "normal" -- don't fill the kernel log with these */
411 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
412 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
417 /* Unload any bytes sent back from the other side */
418 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
419 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
420 if (recv_bytes > recv_size)
421 recv_bytes = recv_size;
423 for (i = 0; i < recv_bytes; i += 4)
424 unpack_aux(I915_READ(ch_data + i),
425 recv + i, recv_bytes - i);
429 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
434 /* Write data to the aux channel in native mode */
436 intel_dp_aux_native_write(struct intel_dp *intel_dp,
437 uint16_t address, uint8_t *send, int send_bytes)
444 intel_dp_check_edp(intel_dp);
447 msg[0] = AUX_NATIVE_WRITE << 4;
448 msg[1] = address >> 8;
449 msg[2] = address & 0xff;
450 msg[3] = send_bytes - 1;
451 memcpy(&msg[4], send, send_bytes);
452 msg_bytes = send_bytes + 4;
454 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
457 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
459 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
467 /* Write a single byte to the aux channel in native mode */
469 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
470 uint16_t address, uint8_t byte)
472 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
475 /* read bytes from a native aux channel */
477 intel_dp_aux_native_read(struct intel_dp *intel_dp,
478 uint16_t address, uint8_t *recv, int recv_bytes)
487 intel_dp_check_edp(intel_dp);
488 msg[0] = AUX_NATIVE_READ << 4;
489 msg[1] = address >> 8;
490 msg[2] = address & 0xff;
491 msg[3] = recv_bytes - 1;
494 reply_bytes = recv_bytes + 1;
497 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
504 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
505 memcpy(recv, reply + 1, ret - 1);
508 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
516 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
517 uint8_t write_byte, uint8_t *read_byte)
519 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
520 struct intel_dp *intel_dp = container_of(adapter,
523 uint16_t address = algo_data->address;
531 intel_dp_check_edp(intel_dp);
532 /* Set up the command byte */
533 if (mode & MODE_I2C_READ)
534 msg[0] = AUX_I2C_READ << 4;
536 msg[0] = AUX_I2C_WRITE << 4;
538 if (!(mode & MODE_I2C_STOP))
539 msg[0] |= AUX_I2C_MOT << 4;
541 msg[1] = address >> 8;
562 for (retry = 0; retry < 5; retry++) {
563 ret = intel_dp_aux_ch(intel_dp,
567 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
571 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
572 case AUX_NATIVE_REPLY_ACK:
573 /* I2C-over-AUX Reply field is only valid
574 * when paired with AUX ACK.
577 case AUX_NATIVE_REPLY_NACK:
578 DRM_DEBUG_KMS("aux_ch native nack\n");
580 case AUX_NATIVE_REPLY_DEFER:
584 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
589 switch (reply[0] & AUX_I2C_REPLY_MASK) {
590 case AUX_I2C_REPLY_ACK:
591 if (mode == MODE_I2C_READ) {
592 *read_byte = reply[1];
594 return reply_bytes - 1;
595 case AUX_I2C_REPLY_NACK:
596 DRM_DEBUG_KMS("aux_i2c nack\n");
598 case AUX_I2C_REPLY_DEFER:
599 DRM_DEBUG_KMS("aux_i2c defer\n");
603 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
608 DRM_ERROR("too many retries, giving up\n");
613 intel_dp_i2c_init(struct intel_dp *intel_dp,
614 struct intel_connector *intel_connector, const char *name)
618 DRM_DEBUG_KMS("i2c_init %s\n", name);
619 intel_dp->algo.running = false;
620 intel_dp->algo.address = 0;
621 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
623 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
624 intel_dp->adapter.owner = THIS_MODULE;
625 intel_dp->adapter.class = I2C_CLASS_DDC;
626 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
627 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
628 intel_dp->adapter.algo_data = &intel_dp->algo;
629 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
631 ironlake_edp_panel_vdd_on(intel_dp);
632 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
633 ironlake_edp_panel_vdd_off(intel_dp, false);
638 intel_dp_set_clock(struct intel_encoder *encoder,
639 struct intel_crtc_config *pipe_config, int link_bw)
641 struct drm_device *dev = encoder->base.dev;
644 if (link_bw == DP_LINK_BW_1_62) {
645 pipe_config->dpll.p1 = 2;
646 pipe_config->dpll.p2 = 10;
647 pipe_config->dpll.n = 2;
648 pipe_config->dpll.m1 = 23;
649 pipe_config->dpll.m2 = 8;
651 pipe_config->dpll.p1 = 1;
652 pipe_config->dpll.p2 = 10;
653 pipe_config->dpll.n = 1;
654 pipe_config->dpll.m1 = 14;
655 pipe_config->dpll.m2 = 2;
657 pipe_config->clock_set = true;
658 } else if (IS_HASWELL(dev)) {
659 /* Haswell has special-purpose DP DDI clocks. */
660 } else if (HAS_PCH_SPLIT(dev)) {
661 if (link_bw == DP_LINK_BW_1_62) {
662 pipe_config->dpll.n = 1;
663 pipe_config->dpll.p1 = 2;
664 pipe_config->dpll.p2 = 10;
665 pipe_config->dpll.m1 = 12;
666 pipe_config->dpll.m2 = 9;
668 pipe_config->dpll.n = 2;
669 pipe_config->dpll.p1 = 1;
670 pipe_config->dpll.p2 = 10;
671 pipe_config->dpll.m1 = 14;
672 pipe_config->dpll.m2 = 8;
674 pipe_config->clock_set = true;
675 } else if (IS_VALLEYVIEW(dev)) {
676 /* FIXME: Need to figure out optimized DP clocks for vlv. */
681 intel_dp_compute_config(struct intel_encoder *encoder,
682 struct intel_crtc_config *pipe_config)
684 struct drm_device *dev = encoder->base.dev;
685 struct drm_i915_private *dev_priv = dev->dev_private;
686 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
687 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
688 struct intel_crtc *intel_crtc = encoder->new_crtc;
689 struct intel_connector *intel_connector = intel_dp->attached_connector;
690 int lane_count, clock;
691 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
692 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
694 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
695 int target_clock, link_avail, link_clock;
697 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
698 pipe_config->has_pch_encoder = true;
700 pipe_config->has_dp_encoder = true;
702 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
703 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
705 if (!HAS_PCH_SPLIT(dev))
706 intel_gmch_panel_fitting(intel_crtc, pipe_config,
707 intel_connector->panel.fitting_mode);
709 intel_pch_panel_fitting(intel_crtc, pipe_config,
710 intel_connector->panel.fitting_mode);
712 /* We need to take the panel's fixed mode into account. */
713 target_clock = adjusted_mode->clock;
715 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
718 DRM_DEBUG_KMS("DP link computation with max lane count %i "
719 "max bw %02x pixel clock %iKHz\n",
720 max_lane_count, bws[max_clock], adjusted_mode->clock);
722 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
724 bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
725 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
726 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
728 for (; bpp >= 6*3; bpp -= 2*3) {
729 mode_rate = intel_dp_link_required(target_clock, bpp);
731 for (clock = 0; clock <= max_clock; clock++) {
732 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
733 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
734 link_avail = intel_dp_max_data_rate(link_clock,
737 if (mode_rate <= link_avail) {
747 if (intel_dp->color_range_auto) {
750 * CEA-861-E - 5.1 Default Encoding Parameters
751 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
753 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
754 intel_dp->color_range = DP_COLOR_RANGE_16_235;
756 intel_dp->color_range = 0;
759 if (intel_dp->color_range)
760 pipe_config->limited_color_range = true;
762 intel_dp->link_bw = bws[clock];
763 intel_dp->lane_count = lane_count;
764 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
765 pipe_config->pipe_bpp = bpp;
766 pipe_config->pixel_target_clock = target_clock;
768 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
769 intel_dp->link_bw, intel_dp->lane_count,
770 adjusted_mode->clock, bpp);
771 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
772 mode_rate, link_avail);
774 intel_link_compute_m_n(bpp, lane_count,
775 target_clock, adjusted_mode->clock,
776 &pipe_config->dp_m_n);
778 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
783 void intel_dp_init_link_config(struct intel_dp *intel_dp)
785 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
786 intel_dp->link_configuration[0] = intel_dp->link_bw;
787 intel_dp->link_configuration[1] = intel_dp->lane_count;
788 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
790 * Check for DPCD version > 1.1 and enhanced framing support
792 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
793 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
794 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
798 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
800 struct drm_device *dev = crtc->dev;
801 struct drm_i915_private *dev_priv = dev->dev_private;
804 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
805 dpa_ctl = I915_READ(DP_A);
806 dpa_ctl &= ~DP_PLL_FREQ_MASK;
808 if (clock < 200000) {
809 /* For a long time we've carried around a ILK-DevA w/a for the
810 * 160MHz clock. If we're really unlucky, it's still required.
812 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
813 dpa_ctl |= DP_PLL_FREQ_160MHZ;
815 dpa_ctl |= DP_PLL_FREQ_270MHZ;
818 I915_WRITE(DP_A, dpa_ctl);
825 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
826 struct drm_display_mode *adjusted_mode)
828 struct drm_device *dev = encoder->dev;
829 struct drm_i915_private *dev_priv = dev->dev_private;
830 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
831 struct drm_crtc *crtc = encoder->crtc;
832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
835 * There are four kinds of DP registers:
842 * IBX PCH and CPU are the same for almost everything,
843 * except that the CPU DP PLL is configured in this
846 * CPT PCH is quite different, having many bits moved
847 * to the TRANS_DP_CTL register instead. That
848 * configuration happens (oddly) in ironlake_pch_enable
851 /* Preserve the BIOS-computed detected bit. This is
852 * supposed to be read-only.
854 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
856 /* Handle DP bits in common between all three register formats */
857 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
858 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
860 if (intel_dp->has_audio) {
861 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
862 pipe_name(intel_crtc->pipe));
863 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
864 intel_write_eld(encoder, adjusted_mode);
867 intel_dp_init_link_config(intel_dp);
869 /* Split out the IBX/CPU vs CPT settings */
871 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
872 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
873 intel_dp->DP |= DP_SYNC_HS_HIGH;
874 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
875 intel_dp->DP |= DP_SYNC_VS_HIGH;
876 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
878 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
879 intel_dp->DP |= DP_ENHANCED_FRAMING;
881 intel_dp->DP |= intel_crtc->pipe << 29;
883 /* don't miss out required setting for eDP */
884 if (adjusted_mode->clock < 200000)
885 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
887 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
888 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
889 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
890 intel_dp->DP |= intel_dp->color_range;
892 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
893 intel_dp->DP |= DP_SYNC_HS_HIGH;
894 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
895 intel_dp->DP |= DP_SYNC_VS_HIGH;
896 intel_dp->DP |= DP_LINK_TRAIN_OFF;
898 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
899 intel_dp->DP |= DP_ENHANCED_FRAMING;
901 if (intel_crtc->pipe == 1)
902 intel_dp->DP |= DP_PIPEB_SELECT;
904 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
905 /* don't miss out required setting for eDP */
906 if (adjusted_mode->clock < 200000)
907 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
909 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
912 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
915 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
916 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
919 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
920 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
922 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
923 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
925 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
926 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
928 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
932 struct drm_device *dev = intel_dp_to_dev(intel_dp);
933 struct drm_i915_private *dev_priv = dev->dev_private;
934 u32 pp_stat_reg, pp_ctrl_reg;
936 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
937 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
939 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
941 I915_READ(pp_stat_reg),
942 I915_READ(pp_ctrl_reg));
944 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
945 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
946 I915_READ(pp_stat_reg),
947 I915_READ(pp_ctrl_reg));
951 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
953 DRM_DEBUG_KMS("Wait for panel power on\n");
954 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
957 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
959 DRM_DEBUG_KMS("Wait for panel power off time\n");
960 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
963 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
965 DRM_DEBUG_KMS("Wait for panel power cycle\n");
966 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
970 /* Read the current pp_control value, unlocking the register if it
974 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
976 struct drm_device *dev = intel_dp_to_dev(intel_dp);
977 struct drm_i915_private *dev_priv = dev->dev_private;
981 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
982 control = I915_READ(pp_ctrl_reg);
984 control &= ~PANEL_UNLOCK_MASK;
985 control |= PANEL_UNLOCK_REGS;
989 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
991 struct drm_device *dev = intel_dp_to_dev(intel_dp);
992 struct drm_i915_private *dev_priv = dev->dev_private;
994 u32 pp_stat_reg, pp_ctrl_reg;
996 if (!is_edp(intel_dp))
998 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1000 WARN(intel_dp->want_panel_vdd,
1001 "eDP VDD already requested on\n");
1003 intel_dp->want_panel_vdd = true;
1005 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1006 DRM_DEBUG_KMS("eDP VDD already on\n");
1010 if (!ironlake_edp_have_panel_power(intel_dp))
1011 ironlake_wait_panel_power_cycle(intel_dp);
1013 pp = ironlake_get_pp_control(intel_dp);
1014 pp |= EDP_FORCE_VDD;
1016 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1017 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1019 I915_WRITE(pp_ctrl_reg, pp);
1020 POSTING_READ(pp_ctrl_reg);
1021 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1022 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1024 * If the panel wasn't on, delay before accessing aux channel
1026 if (!ironlake_edp_have_panel_power(intel_dp)) {
1027 DRM_DEBUG_KMS("eDP was not running\n");
1028 msleep(intel_dp->panel_power_up_delay);
1032 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1034 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1035 struct drm_i915_private *dev_priv = dev->dev_private;
1037 u32 pp_stat_reg, pp_ctrl_reg;
1039 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1041 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1042 pp = ironlake_get_pp_control(intel_dp);
1043 pp &= ~EDP_FORCE_VDD;
1045 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1046 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1048 I915_WRITE(pp_ctrl_reg, pp);
1049 POSTING_READ(pp_ctrl_reg);
1051 /* Make sure sequencer is idle before allowing subsequent activity */
1052 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1053 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1054 msleep(intel_dp->panel_power_down_delay);
1058 static void ironlake_panel_vdd_work(struct work_struct *__work)
1060 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1061 struct intel_dp, panel_vdd_work);
1062 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1064 mutex_lock(&dev->mode_config.mutex);
1065 ironlake_panel_vdd_off_sync(intel_dp);
1066 mutex_unlock(&dev->mode_config.mutex);
1069 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1071 if (!is_edp(intel_dp))
1074 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1075 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1077 intel_dp->want_panel_vdd = false;
1080 ironlake_panel_vdd_off_sync(intel_dp);
1083 * Queue the timer to fire a long
1084 * time from now (relative to the power down delay)
1085 * to keep the panel power up across a sequence of operations
1087 schedule_delayed_work(&intel_dp->panel_vdd_work,
1088 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1092 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1094 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1095 struct drm_i915_private *dev_priv = dev->dev_private;
1099 if (!is_edp(intel_dp))
1102 DRM_DEBUG_KMS("Turn eDP power on\n");
1104 if (ironlake_edp_have_panel_power(intel_dp)) {
1105 DRM_DEBUG_KMS("eDP power already on\n");
1109 ironlake_wait_panel_power_cycle(intel_dp);
1111 pp = ironlake_get_pp_control(intel_dp);
1113 /* ILK workaround: disable reset around power sequence */
1114 pp &= ~PANEL_POWER_RESET;
1115 I915_WRITE(PCH_PP_CONTROL, pp);
1116 POSTING_READ(PCH_PP_CONTROL);
1119 pp |= POWER_TARGET_ON;
1121 pp |= PANEL_POWER_RESET;
1123 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1125 I915_WRITE(pp_ctrl_reg, pp);
1126 POSTING_READ(pp_ctrl_reg);
1128 ironlake_wait_panel_on(intel_dp);
1131 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1132 I915_WRITE(PCH_PP_CONTROL, pp);
1133 POSTING_READ(PCH_PP_CONTROL);
1137 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1139 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1144 if (!is_edp(intel_dp))
1147 DRM_DEBUG_KMS("Turn eDP power off\n");
1149 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1151 pp = ironlake_get_pp_control(intel_dp);
1152 /* We need to switch off panel power _and_ force vdd, for otherwise some
1153 * panels get very unhappy and cease to work. */
1154 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1156 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1158 I915_WRITE(pp_ctrl_reg, pp);
1159 POSTING_READ(pp_ctrl_reg);
1161 intel_dp->want_panel_vdd = false;
1163 ironlake_wait_panel_off(intel_dp);
1166 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1168 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1169 struct drm_device *dev = intel_dig_port->base.base.dev;
1170 struct drm_i915_private *dev_priv = dev->dev_private;
1171 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1175 if (!is_edp(intel_dp))
1178 DRM_DEBUG_KMS("\n");
1180 * If we enable the backlight right away following a panel power
1181 * on, we may see slight flicker as the panel syncs with the eDP
1182 * link. So delay a bit to make sure the image is solid before
1183 * allowing it to appear.
1185 msleep(intel_dp->backlight_on_delay);
1186 pp = ironlake_get_pp_control(intel_dp);
1187 pp |= EDP_BLC_ENABLE;
1189 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1191 I915_WRITE(pp_ctrl_reg, pp);
1192 POSTING_READ(pp_ctrl_reg);
1194 intel_panel_enable_backlight(dev, pipe);
1197 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1199 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1200 struct drm_i915_private *dev_priv = dev->dev_private;
1204 if (!is_edp(intel_dp))
1207 intel_panel_disable_backlight(dev);
1209 DRM_DEBUG_KMS("\n");
1210 pp = ironlake_get_pp_control(intel_dp);
1211 pp &= ~EDP_BLC_ENABLE;
1213 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1215 I915_WRITE(pp_ctrl_reg, pp);
1216 POSTING_READ(pp_ctrl_reg);
1217 msleep(intel_dp->backlight_off_delay);
1220 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1222 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1223 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1224 struct drm_device *dev = crtc->dev;
1225 struct drm_i915_private *dev_priv = dev->dev_private;
1228 assert_pipe_disabled(dev_priv,
1229 to_intel_crtc(crtc)->pipe);
1231 DRM_DEBUG_KMS("\n");
1232 dpa_ctl = I915_READ(DP_A);
1233 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1234 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1236 /* We don't adjust intel_dp->DP while tearing down the link, to
1237 * facilitate link retraining (e.g. after hotplug). Hence clear all
1238 * enable bits here to ensure that we don't enable too much. */
1239 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1240 intel_dp->DP |= DP_PLL_ENABLE;
1241 I915_WRITE(DP_A, intel_dp->DP);
1246 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1248 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1249 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1250 struct drm_device *dev = crtc->dev;
1251 struct drm_i915_private *dev_priv = dev->dev_private;
1254 assert_pipe_disabled(dev_priv,
1255 to_intel_crtc(crtc)->pipe);
1257 dpa_ctl = I915_READ(DP_A);
1258 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1259 "dp pll off, should be on\n");
1260 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1262 /* We can't rely on the value tracked for the DP register in
1263 * intel_dp->DP because link_down must not change that (otherwise link
1264 * re-training will fail. */
1265 dpa_ctl &= ~DP_PLL_ENABLE;
1266 I915_WRITE(DP_A, dpa_ctl);
1271 /* If the sink supports it, try to set the power state appropriately */
1272 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1276 /* Should have a valid DPCD by this point */
1277 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1280 if (mode != DRM_MODE_DPMS_ON) {
1281 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1284 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1287 * When turning on, we need to retry for 1ms to give the sink
1290 for (i = 0; i < 3; i++) {
1291 ret = intel_dp_aux_native_write_1(intel_dp,
1301 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1304 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1305 struct drm_device *dev = encoder->base.dev;
1306 struct drm_i915_private *dev_priv = dev->dev_private;
1307 u32 tmp = I915_READ(intel_dp->output_reg);
1309 if (!(tmp & DP_PORT_EN))
1312 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1313 *pipe = PORT_TO_PIPE_CPT(tmp);
1314 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1315 *pipe = PORT_TO_PIPE(tmp);
1321 switch (intel_dp->output_reg) {
1323 trans_sel = TRANS_DP_PORT_SEL_B;
1326 trans_sel = TRANS_DP_PORT_SEL_C;
1329 trans_sel = TRANS_DP_PORT_SEL_D;
1336 trans_dp = I915_READ(TRANS_DP_CTL(i));
1337 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1343 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1344 intel_dp->output_reg);
1350 static void intel_dp_get_config(struct intel_encoder *encoder,
1351 struct intel_crtc_config *pipe_config)
1353 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1354 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1357 tmp = I915_READ(intel_dp->output_reg);
1359 if (tmp & DP_SYNC_HS_HIGH)
1360 flags |= DRM_MODE_FLAG_PHSYNC;
1362 flags |= DRM_MODE_FLAG_NHSYNC;
1364 if (tmp & DP_SYNC_VS_HIGH)
1365 flags |= DRM_MODE_FLAG_PVSYNC;
1367 flags |= DRM_MODE_FLAG_NVSYNC;
1369 pipe_config->adjusted_mode.flags |= flags;
1372 static void intel_disable_dp(struct intel_encoder *encoder)
1374 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1376 /* Make sure the panel is off before trying to change the mode. But also
1377 * ensure that we have vdd while we switch off the panel. */
1378 ironlake_edp_panel_vdd_on(intel_dp);
1379 ironlake_edp_backlight_off(intel_dp);
1380 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1381 ironlake_edp_panel_off(intel_dp);
1383 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1384 if (!is_cpu_edp(intel_dp))
1385 intel_dp_link_down(intel_dp);
1388 static void intel_post_disable_dp(struct intel_encoder *encoder)
1390 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1391 struct drm_device *dev = encoder->base.dev;
1393 if (is_cpu_edp(intel_dp)) {
1394 intel_dp_link_down(intel_dp);
1395 if (!IS_VALLEYVIEW(dev))
1396 ironlake_edp_pll_off(intel_dp);
1400 static void intel_enable_dp(struct intel_encoder *encoder)
1402 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1403 struct drm_device *dev = encoder->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1407 if (WARN_ON(dp_reg & DP_PORT_EN))
1410 ironlake_edp_panel_vdd_on(intel_dp);
1411 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1412 intel_dp_start_link_train(intel_dp);
1413 ironlake_edp_panel_on(intel_dp);
1414 ironlake_edp_panel_vdd_off(intel_dp, true);
1415 intel_dp_complete_link_train(intel_dp);
1416 intel_dp_stop_link_train(intel_dp);
1417 ironlake_edp_backlight_on(intel_dp);
1419 if (IS_VALLEYVIEW(dev)) {
1420 struct intel_digital_port *dport =
1421 enc_to_dig_port(&encoder->base);
1422 int channel = vlv_dport_to_channel(dport);
1424 vlv_wait_port_ready(dev_priv, channel);
1428 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1430 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1431 struct drm_device *dev = encoder->base.dev;
1432 struct drm_i915_private *dev_priv = dev->dev_private;
1434 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
1435 ironlake_edp_pll_on(intel_dp);
1437 if (IS_VALLEYVIEW(dev)) {
1438 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1439 struct intel_crtc *intel_crtc =
1440 to_intel_crtc(encoder->base.crtc);
1441 int port = vlv_dport_to_channel(dport);
1442 int pipe = intel_crtc->pipe;
1445 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1452 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1454 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1456 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1461 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1463 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1464 struct drm_device *dev = encoder->base.dev;
1465 struct drm_i915_private *dev_priv = dev->dev_private;
1466 int port = vlv_dport_to_channel(dport);
1468 if (!IS_VALLEYVIEW(dev))
1471 /* Program Tx lane resets to default */
1472 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1473 DPIO_PCS_TX_LANE2_RESET |
1474 DPIO_PCS_TX_LANE1_RESET);
1475 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1476 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1477 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1478 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1479 DPIO_PCS_CLK_SOFT_RESET);
1481 /* Fix up inter-pair skew failure */
1482 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1483 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1484 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1488 * Native read with retry for link status and receiver capability reads for
1489 * cases where the sink may still be asleep.
1492 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1493 uint8_t *recv, int recv_bytes)
1498 * Sinks are *supposed* to come up within 1ms from an off state,
1499 * but we're also supposed to retry 3 times per the spec.
1501 for (i = 0; i < 3; i++) {
1502 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1504 if (ret == recv_bytes)
1513 * Fetch AUX CH registers 0x202 - 0x207 which contain
1514 * link status information
1517 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1519 return intel_dp_aux_native_read_retry(intel_dp,
1522 DP_LINK_STATUS_SIZE);
1526 static char *voltage_names[] = {
1527 "0.4V", "0.6V", "0.8V", "1.2V"
1529 static char *pre_emph_names[] = {
1530 "0dB", "3.5dB", "6dB", "9.5dB"
1532 static char *link_train_names[] = {
1533 "pattern 1", "pattern 2", "idle", "off"
1538 * These are source-specific values; current Intel hardware supports
1539 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1543 intel_dp_voltage_max(struct intel_dp *intel_dp)
1545 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1547 if (IS_VALLEYVIEW(dev))
1548 return DP_TRAIN_VOLTAGE_SWING_1200;
1549 else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1550 return DP_TRAIN_VOLTAGE_SWING_800;
1551 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1552 return DP_TRAIN_VOLTAGE_SWING_1200;
1554 return DP_TRAIN_VOLTAGE_SWING_800;
1558 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1560 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1563 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1564 case DP_TRAIN_VOLTAGE_SWING_400:
1565 return DP_TRAIN_PRE_EMPHASIS_9_5;
1566 case DP_TRAIN_VOLTAGE_SWING_600:
1567 return DP_TRAIN_PRE_EMPHASIS_6;
1568 case DP_TRAIN_VOLTAGE_SWING_800:
1569 return DP_TRAIN_PRE_EMPHASIS_3_5;
1570 case DP_TRAIN_VOLTAGE_SWING_1200:
1572 return DP_TRAIN_PRE_EMPHASIS_0;
1574 } else if (IS_VALLEYVIEW(dev)) {
1575 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1576 case DP_TRAIN_VOLTAGE_SWING_400:
1577 return DP_TRAIN_PRE_EMPHASIS_9_5;
1578 case DP_TRAIN_VOLTAGE_SWING_600:
1579 return DP_TRAIN_PRE_EMPHASIS_6;
1580 case DP_TRAIN_VOLTAGE_SWING_800:
1581 return DP_TRAIN_PRE_EMPHASIS_3_5;
1582 case DP_TRAIN_VOLTAGE_SWING_1200:
1584 return DP_TRAIN_PRE_EMPHASIS_0;
1586 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1587 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1588 case DP_TRAIN_VOLTAGE_SWING_400:
1589 return DP_TRAIN_PRE_EMPHASIS_6;
1590 case DP_TRAIN_VOLTAGE_SWING_600:
1591 case DP_TRAIN_VOLTAGE_SWING_800:
1592 return DP_TRAIN_PRE_EMPHASIS_3_5;
1594 return DP_TRAIN_PRE_EMPHASIS_0;
1597 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1598 case DP_TRAIN_VOLTAGE_SWING_400:
1599 return DP_TRAIN_PRE_EMPHASIS_6;
1600 case DP_TRAIN_VOLTAGE_SWING_600:
1601 return DP_TRAIN_PRE_EMPHASIS_6;
1602 case DP_TRAIN_VOLTAGE_SWING_800:
1603 return DP_TRAIN_PRE_EMPHASIS_3_5;
1604 case DP_TRAIN_VOLTAGE_SWING_1200:
1606 return DP_TRAIN_PRE_EMPHASIS_0;
1611 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1613 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1614 struct drm_i915_private *dev_priv = dev->dev_private;
1615 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1616 unsigned long demph_reg_value, preemph_reg_value,
1617 uniqtranscale_reg_value;
1618 uint8_t train_set = intel_dp->train_set[0];
1619 int port = vlv_dport_to_channel(dport);
1621 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1622 case DP_TRAIN_PRE_EMPHASIS_0:
1623 preemph_reg_value = 0x0004000;
1624 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1625 case DP_TRAIN_VOLTAGE_SWING_400:
1626 demph_reg_value = 0x2B405555;
1627 uniqtranscale_reg_value = 0x552AB83A;
1629 case DP_TRAIN_VOLTAGE_SWING_600:
1630 demph_reg_value = 0x2B404040;
1631 uniqtranscale_reg_value = 0x5548B83A;
1633 case DP_TRAIN_VOLTAGE_SWING_800:
1634 demph_reg_value = 0x2B245555;
1635 uniqtranscale_reg_value = 0x5560B83A;
1637 case DP_TRAIN_VOLTAGE_SWING_1200:
1638 demph_reg_value = 0x2B405555;
1639 uniqtranscale_reg_value = 0x5598DA3A;
1645 case DP_TRAIN_PRE_EMPHASIS_3_5:
1646 preemph_reg_value = 0x0002000;
1647 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1648 case DP_TRAIN_VOLTAGE_SWING_400:
1649 demph_reg_value = 0x2B404040;
1650 uniqtranscale_reg_value = 0x5552B83A;
1652 case DP_TRAIN_VOLTAGE_SWING_600:
1653 demph_reg_value = 0x2B404848;
1654 uniqtranscale_reg_value = 0x5580B83A;
1656 case DP_TRAIN_VOLTAGE_SWING_800:
1657 demph_reg_value = 0x2B404040;
1658 uniqtranscale_reg_value = 0x55ADDA3A;
1664 case DP_TRAIN_PRE_EMPHASIS_6:
1665 preemph_reg_value = 0x0000000;
1666 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1667 case DP_TRAIN_VOLTAGE_SWING_400:
1668 demph_reg_value = 0x2B305555;
1669 uniqtranscale_reg_value = 0x5570B83A;
1671 case DP_TRAIN_VOLTAGE_SWING_600:
1672 demph_reg_value = 0x2B2B4040;
1673 uniqtranscale_reg_value = 0x55ADDA3A;
1679 case DP_TRAIN_PRE_EMPHASIS_9_5:
1680 preemph_reg_value = 0x0006000;
1681 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1682 case DP_TRAIN_VOLTAGE_SWING_400:
1683 demph_reg_value = 0x1B405555;
1684 uniqtranscale_reg_value = 0x55ADDA3A;
1694 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1695 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1696 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1697 uniqtranscale_reg_value);
1698 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1699 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1700 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1701 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1707 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1712 uint8_t voltage_max;
1713 uint8_t preemph_max;
1715 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1716 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1717 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1725 voltage_max = intel_dp_voltage_max(intel_dp);
1726 if (v >= voltage_max)
1727 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1729 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1730 if (p >= preemph_max)
1731 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1733 for (lane = 0; lane < 4; lane++)
1734 intel_dp->train_set[lane] = v | p;
1738 intel_gen4_signal_levels(uint8_t train_set)
1740 uint32_t signal_levels = 0;
1742 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1743 case DP_TRAIN_VOLTAGE_SWING_400:
1745 signal_levels |= DP_VOLTAGE_0_4;
1747 case DP_TRAIN_VOLTAGE_SWING_600:
1748 signal_levels |= DP_VOLTAGE_0_6;
1750 case DP_TRAIN_VOLTAGE_SWING_800:
1751 signal_levels |= DP_VOLTAGE_0_8;
1753 case DP_TRAIN_VOLTAGE_SWING_1200:
1754 signal_levels |= DP_VOLTAGE_1_2;
1757 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1758 case DP_TRAIN_PRE_EMPHASIS_0:
1760 signal_levels |= DP_PRE_EMPHASIS_0;
1762 case DP_TRAIN_PRE_EMPHASIS_3_5:
1763 signal_levels |= DP_PRE_EMPHASIS_3_5;
1765 case DP_TRAIN_PRE_EMPHASIS_6:
1766 signal_levels |= DP_PRE_EMPHASIS_6;
1768 case DP_TRAIN_PRE_EMPHASIS_9_5:
1769 signal_levels |= DP_PRE_EMPHASIS_9_5;
1772 return signal_levels;
1775 /* Gen6's DP voltage swing and pre-emphasis control */
1777 intel_gen6_edp_signal_levels(uint8_t train_set)
1779 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1780 DP_TRAIN_PRE_EMPHASIS_MASK);
1781 switch (signal_levels) {
1782 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1783 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1784 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1785 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1786 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1787 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1788 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1789 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1790 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1791 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1792 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1793 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1794 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1795 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1797 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1798 "0x%x\n", signal_levels);
1799 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1803 /* Gen7's DP voltage swing and pre-emphasis control */
1805 intel_gen7_edp_signal_levels(uint8_t train_set)
1807 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1808 DP_TRAIN_PRE_EMPHASIS_MASK);
1809 switch (signal_levels) {
1810 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1811 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1812 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1813 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1814 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1815 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1817 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1818 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1819 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1820 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1822 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1823 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1824 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1825 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1828 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1829 "0x%x\n", signal_levels);
1830 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1834 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1836 intel_hsw_signal_levels(uint8_t train_set)
1838 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1839 DP_TRAIN_PRE_EMPHASIS_MASK);
1840 switch (signal_levels) {
1841 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1842 return DDI_BUF_EMP_400MV_0DB_HSW;
1843 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1844 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1845 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1846 return DDI_BUF_EMP_400MV_6DB_HSW;
1847 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1848 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1850 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1851 return DDI_BUF_EMP_600MV_0DB_HSW;
1852 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1853 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1854 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1855 return DDI_BUF_EMP_600MV_6DB_HSW;
1857 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1858 return DDI_BUF_EMP_800MV_0DB_HSW;
1859 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1860 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1862 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1863 "0x%x\n", signal_levels);
1864 return DDI_BUF_EMP_400MV_0DB_HSW;
1868 /* Properly updates "DP" with the correct signal levels. */
1870 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1872 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1873 struct drm_device *dev = intel_dig_port->base.base.dev;
1874 uint32_t signal_levels, mask;
1875 uint8_t train_set = intel_dp->train_set[0];
1878 signal_levels = intel_hsw_signal_levels(train_set);
1879 mask = DDI_BUF_EMP_MASK;
1880 } else if (IS_VALLEYVIEW(dev)) {
1881 signal_levels = intel_vlv_signal_levels(intel_dp);
1883 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1884 signal_levels = intel_gen7_edp_signal_levels(train_set);
1885 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1886 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1887 signal_levels = intel_gen6_edp_signal_levels(train_set);
1888 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1890 signal_levels = intel_gen4_signal_levels(train_set);
1891 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1894 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1896 *DP = (*DP & ~mask) | signal_levels;
1900 intel_dp_set_link_train(struct intel_dp *intel_dp,
1901 uint32_t dp_reg_value,
1902 uint8_t dp_train_pat)
1904 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1905 struct drm_device *dev = intel_dig_port->base.base.dev;
1906 struct drm_i915_private *dev_priv = dev->dev_private;
1907 enum port port = intel_dig_port->port;
1911 uint32_t temp = I915_READ(DP_TP_CTL(port));
1913 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1914 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1916 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1918 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1919 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1920 case DP_TRAINING_PATTERN_DISABLE:
1921 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1924 case DP_TRAINING_PATTERN_1:
1925 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1927 case DP_TRAINING_PATTERN_2:
1928 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1930 case DP_TRAINING_PATTERN_3:
1931 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1934 I915_WRITE(DP_TP_CTL(port), temp);
1936 } else if (HAS_PCH_CPT(dev) &&
1937 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1938 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1940 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1941 case DP_TRAINING_PATTERN_DISABLE:
1942 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1944 case DP_TRAINING_PATTERN_1:
1945 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1947 case DP_TRAINING_PATTERN_2:
1948 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1950 case DP_TRAINING_PATTERN_3:
1951 DRM_ERROR("DP training pattern 3 not supported\n");
1952 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1957 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1959 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1960 case DP_TRAINING_PATTERN_DISABLE:
1961 dp_reg_value |= DP_LINK_TRAIN_OFF;
1963 case DP_TRAINING_PATTERN_1:
1964 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1966 case DP_TRAINING_PATTERN_2:
1967 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1969 case DP_TRAINING_PATTERN_3:
1970 DRM_ERROR("DP training pattern 3 not supported\n");
1971 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1976 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1977 POSTING_READ(intel_dp->output_reg);
1979 intel_dp_aux_native_write_1(intel_dp,
1980 DP_TRAINING_PATTERN_SET,
1983 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1984 DP_TRAINING_PATTERN_DISABLE) {
1985 ret = intel_dp_aux_native_write(intel_dp,
1986 DP_TRAINING_LANE0_SET,
1987 intel_dp->train_set,
1988 intel_dp->lane_count);
1989 if (ret != intel_dp->lane_count)
1996 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
1998 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1999 struct drm_device *dev = intel_dig_port->base.base.dev;
2000 struct drm_i915_private *dev_priv = dev->dev_private;
2001 enum port port = intel_dig_port->port;
2007 val = I915_READ(DP_TP_CTL(port));
2008 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2009 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2010 I915_WRITE(DP_TP_CTL(port), val);
2013 * On PORT_A we can have only eDP in SST mode. There the only reason
2014 * we need to set idle transmission mode is to work around a HW issue
2015 * where we enable the pipe while not in idle link-training mode.
2016 * In this case there is requirement to wait for a minimum number of
2017 * idle patterns to be sent.
2022 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2024 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2027 /* Enable corresponding port and start training pattern 1 */
2029 intel_dp_start_link_train(struct intel_dp *intel_dp)
2031 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2032 struct drm_device *dev = encoder->dev;
2035 bool clock_recovery = false;
2036 int voltage_tries, loop_tries;
2037 uint32_t DP = intel_dp->DP;
2040 intel_ddi_prepare_link_retrain(encoder);
2042 /* Write the link configuration data */
2043 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2044 intel_dp->link_configuration,
2045 DP_LINK_CONFIGURATION_SIZE);
2049 memset(intel_dp->train_set, 0, 4);
2053 clock_recovery = false;
2055 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2056 uint8_t link_status[DP_LINK_STATUS_SIZE];
2058 intel_dp_set_signal_levels(intel_dp, &DP);
2060 /* Set training pattern 1 */
2061 if (!intel_dp_set_link_train(intel_dp, DP,
2062 DP_TRAINING_PATTERN_1 |
2063 DP_LINK_SCRAMBLING_DISABLE))
2066 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2067 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2068 DRM_ERROR("failed to get link status\n");
2072 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2073 DRM_DEBUG_KMS("clock recovery OK\n");
2074 clock_recovery = true;
2078 /* Check to see if we've tried the max voltage */
2079 for (i = 0; i < intel_dp->lane_count; i++)
2080 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2082 if (i == intel_dp->lane_count) {
2084 if (loop_tries == 5) {
2085 DRM_DEBUG_KMS("too many full retries, give up\n");
2088 memset(intel_dp->train_set, 0, 4);
2093 /* Check to see if we've tried the same voltage 5 times */
2094 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2096 if (voltage_tries == 5) {
2097 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2102 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2104 /* Compute new intel_dp->train_set as requested by target */
2105 intel_get_adjust_train(intel_dp, link_status);
2112 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2114 bool channel_eq = false;
2115 int tries, cr_tries;
2116 uint32_t DP = intel_dp->DP;
2118 /* channel equalization */
2123 uint8_t link_status[DP_LINK_STATUS_SIZE];
2126 DRM_ERROR("failed to train DP, aborting\n");
2127 intel_dp_link_down(intel_dp);
2131 intel_dp_set_signal_levels(intel_dp, &DP);
2133 /* channel eq pattern */
2134 if (!intel_dp_set_link_train(intel_dp, DP,
2135 DP_TRAINING_PATTERN_2 |
2136 DP_LINK_SCRAMBLING_DISABLE))
2139 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2140 if (!intel_dp_get_link_status(intel_dp, link_status))
2143 /* Make sure clock is still ok */
2144 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2145 intel_dp_start_link_train(intel_dp);
2150 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2155 /* Try 5 times, then try clock recovery if that fails */
2157 intel_dp_link_down(intel_dp);
2158 intel_dp_start_link_train(intel_dp);
2164 /* Compute new intel_dp->train_set as requested by target */
2165 intel_get_adjust_train(intel_dp, link_status);
2169 intel_dp_set_idle_link_train(intel_dp);
2174 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2178 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2180 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2181 DP_TRAINING_PATTERN_DISABLE);
2185 intel_dp_link_down(struct intel_dp *intel_dp)
2187 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2188 struct drm_device *dev = intel_dig_port->base.base.dev;
2189 struct drm_i915_private *dev_priv = dev->dev_private;
2190 struct intel_crtc *intel_crtc =
2191 to_intel_crtc(intel_dig_port->base.base.crtc);
2192 uint32_t DP = intel_dp->DP;
2195 * DDI code has a strict mode set sequence and we should try to respect
2196 * it, otherwise we might hang the machine in many different ways. So we
2197 * really should be disabling the port only on a complete crtc_disable
2198 * sequence. This function is just called under two conditions on DDI
2200 * - Link train failed while doing crtc_enable, and on this case we
2201 * really should respect the mode set sequence and wait for a
2203 * - Someone turned the monitor off and intel_dp_check_link_status
2204 * called us. We don't need to disable the whole port on this case, so
2205 * when someone turns the monitor on again,
2206 * intel_ddi_prepare_link_retrain will take care of redoing the link
2212 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2215 DRM_DEBUG_KMS("\n");
2217 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2218 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2219 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2221 DP &= ~DP_LINK_TRAIN_MASK;
2222 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2224 POSTING_READ(intel_dp->output_reg);
2226 /* We don't really know why we're doing this */
2227 intel_wait_for_vblank(dev, intel_crtc->pipe);
2229 if (HAS_PCH_IBX(dev) &&
2230 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2231 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2233 /* Hardware workaround: leaving our transcoder select
2234 * set to transcoder B while it's off will prevent the
2235 * corresponding HDMI output on transcoder A.
2237 * Combine this with another hardware workaround:
2238 * transcoder select bit can only be cleared while the
2241 DP &= ~DP_PIPEB_SELECT;
2242 I915_WRITE(intel_dp->output_reg, DP);
2244 /* Changes to enable or select take place the vblank
2245 * after being written.
2247 if (WARN_ON(crtc == NULL)) {
2248 /* We should never try to disable a port without a crtc
2249 * attached. For paranoia keep the code around for a
2251 POSTING_READ(intel_dp->output_reg);
2254 intel_wait_for_vblank(dev, intel_crtc->pipe);
2257 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2258 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2259 POSTING_READ(intel_dp->output_reg);
2260 msleep(intel_dp->panel_power_down_delay);
2264 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2266 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2268 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2269 sizeof(intel_dp->dpcd)) == 0)
2270 return false; /* aux transfer failed */
2272 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2273 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2274 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2276 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2277 return false; /* DPCD not present */
2279 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2280 DP_DWN_STRM_PORT_PRESENT))
2281 return true; /* native DP sink */
2283 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2284 return true; /* no per-port downstream info */
2286 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2287 intel_dp->downstream_ports,
2288 DP_MAX_DOWNSTREAM_PORTS) == 0)
2289 return false; /* downstream port status fetch failed */
2295 intel_dp_probe_oui(struct intel_dp *intel_dp)
2299 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2302 ironlake_edp_panel_vdd_on(intel_dp);
2304 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2305 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2306 buf[0], buf[1], buf[2]);
2308 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2309 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2310 buf[0], buf[1], buf[2]);
2312 ironlake_edp_panel_vdd_off(intel_dp, false);
2316 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2320 ret = intel_dp_aux_native_read_retry(intel_dp,
2321 DP_DEVICE_SERVICE_IRQ_VECTOR,
2322 sink_irq_vector, 1);
2330 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2332 /* NAK by default */
2333 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2337 * According to DP spec
2340 * 2. Configure link according to Receiver Capabilities
2341 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2342 * 4. Check link status on receipt of hot-plug interrupt
2346 intel_dp_check_link_status(struct intel_dp *intel_dp)
2348 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2350 u8 link_status[DP_LINK_STATUS_SIZE];
2352 if (!intel_encoder->connectors_active)
2355 if (WARN_ON(!intel_encoder->base.crtc))
2358 /* Try to read receiver status if the link appears to be up */
2359 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2360 intel_dp_link_down(intel_dp);
2364 /* Now read the DPCD to see if it's actually running */
2365 if (!intel_dp_get_dpcd(intel_dp)) {
2366 intel_dp_link_down(intel_dp);
2370 /* Try to read the source of the interrupt */
2371 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2372 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2373 /* Clear interrupt source */
2374 intel_dp_aux_native_write_1(intel_dp,
2375 DP_DEVICE_SERVICE_IRQ_VECTOR,
2378 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2379 intel_dp_handle_test_request(intel_dp);
2380 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2381 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2384 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2385 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2386 drm_get_encoder_name(&intel_encoder->base));
2387 intel_dp_start_link_train(intel_dp);
2388 intel_dp_complete_link_train(intel_dp);
2389 intel_dp_stop_link_train(intel_dp);
2393 /* XXX this is probably wrong for multiple downstream ports */
2394 static enum drm_connector_status
2395 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2397 uint8_t *dpcd = intel_dp->dpcd;
2401 if (!intel_dp_get_dpcd(intel_dp))
2402 return connector_status_disconnected;
2404 /* if there's no downstream port, we're done */
2405 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2406 return connector_status_connected;
2408 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2409 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2412 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2414 return connector_status_unknown;
2415 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2416 : connector_status_disconnected;
2419 /* If no HPD, poke DDC gently */
2420 if (drm_probe_ddc(&intel_dp->adapter))
2421 return connector_status_connected;
2423 /* Well we tried, say unknown for unreliable port types */
2424 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2425 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2426 return connector_status_unknown;
2428 /* Anything else is out of spec, warn and ignore */
2429 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2430 return connector_status_disconnected;
2433 static enum drm_connector_status
2434 ironlake_dp_detect(struct intel_dp *intel_dp)
2436 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2437 struct drm_i915_private *dev_priv = dev->dev_private;
2438 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2439 enum drm_connector_status status;
2441 /* Can't disconnect eDP, but you can close the lid... */
2442 if (is_edp(intel_dp)) {
2443 status = intel_panel_detect(dev);
2444 if (status == connector_status_unknown)
2445 status = connector_status_connected;
2449 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2450 return connector_status_disconnected;
2452 return intel_dp_detect_dpcd(intel_dp);
2455 static enum drm_connector_status
2456 g4x_dp_detect(struct intel_dp *intel_dp)
2458 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2459 struct drm_i915_private *dev_priv = dev->dev_private;
2460 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2463 /* Can't disconnect eDP, but you can close the lid... */
2464 if (is_edp(intel_dp)) {
2465 enum drm_connector_status status;
2467 status = intel_panel_detect(dev);
2468 if (status == connector_status_unknown)
2469 status = connector_status_connected;
2473 switch (intel_dig_port->port) {
2475 bit = PORTB_HOTPLUG_LIVE_STATUS;
2478 bit = PORTC_HOTPLUG_LIVE_STATUS;
2481 bit = PORTD_HOTPLUG_LIVE_STATUS;
2484 return connector_status_unknown;
2487 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2488 return connector_status_disconnected;
2490 return intel_dp_detect_dpcd(intel_dp);
2493 static struct edid *
2494 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2496 struct intel_connector *intel_connector = to_intel_connector(connector);
2498 /* use cached edid if we have one */
2499 if (intel_connector->edid) {
2504 if (IS_ERR(intel_connector->edid))
2507 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2508 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
2515 return drm_get_edid(connector, adapter);
2519 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2521 struct intel_connector *intel_connector = to_intel_connector(connector);
2523 /* use cached edid if we have one */
2524 if (intel_connector->edid) {
2526 if (IS_ERR(intel_connector->edid))
2529 return intel_connector_update_modes(connector,
2530 intel_connector->edid);
2533 return intel_ddc_get_modes(connector, adapter);
2536 static enum drm_connector_status
2537 intel_dp_detect(struct drm_connector *connector, bool force)
2539 struct intel_dp *intel_dp = intel_attached_dp(connector);
2540 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2541 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2542 struct drm_device *dev = connector->dev;
2543 enum drm_connector_status status;
2544 struct edid *edid = NULL;
2546 intel_dp->has_audio = false;
2548 if (HAS_PCH_SPLIT(dev))
2549 status = ironlake_dp_detect(intel_dp);
2551 status = g4x_dp_detect(intel_dp);
2553 if (status != connector_status_connected)
2556 intel_dp_probe_oui(intel_dp);
2558 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2559 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2561 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2563 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2568 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2569 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2570 return connector_status_connected;
2573 static int intel_dp_get_modes(struct drm_connector *connector)
2575 struct intel_dp *intel_dp = intel_attached_dp(connector);
2576 struct intel_connector *intel_connector = to_intel_connector(connector);
2577 struct drm_device *dev = connector->dev;
2580 /* We should parse the EDID data and find out if it has an audio sink
2583 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2587 /* if eDP has no EDID, fall back to fixed mode */
2588 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2589 struct drm_display_mode *mode;
2590 mode = drm_mode_duplicate(dev,
2591 intel_connector->panel.fixed_mode);
2593 drm_mode_probed_add(connector, mode);
2601 intel_dp_detect_audio(struct drm_connector *connector)
2603 struct intel_dp *intel_dp = intel_attached_dp(connector);
2605 bool has_audio = false;
2607 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2609 has_audio = drm_detect_monitor_audio(edid);
2617 intel_dp_set_property(struct drm_connector *connector,
2618 struct drm_property *property,
2621 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2622 struct intel_connector *intel_connector = to_intel_connector(connector);
2623 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2624 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2627 ret = drm_object_property_set_value(&connector->base, property, val);
2631 if (property == dev_priv->force_audio_property) {
2635 if (i == intel_dp->force_audio)
2638 intel_dp->force_audio = i;
2640 if (i == HDMI_AUDIO_AUTO)
2641 has_audio = intel_dp_detect_audio(connector);
2643 has_audio = (i == HDMI_AUDIO_ON);
2645 if (has_audio == intel_dp->has_audio)
2648 intel_dp->has_audio = has_audio;
2652 if (property == dev_priv->broadcast_rgb_property) {
2653 bool old_auto = intel_dp->color_range_auto;
2654 uint32_t old_range = intel_dp->color_range;
2657 case INTEL_BROADCAST_RGB_AUTO:
2658 intel_dp->color_range_auto = true;
2660 case INTEL_BROADCAST_RGB_FULL:
2661 intel_dp->color_range_auto = false;
2662 intel_dp->color_range = 0;
2664 case INTEL_BROADCAST_RGB_LIMITED:
2665 intel_dp->color_range_auto = false;
2666 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2672 if (old_auto == intel_dp->color_range_auto &&
2673 old_range == intel_dp->color_range)
2679 if (is_edp(intel_dp) &&
2680 property == connector->dev->mode_config.scaling_mode_property) {
2681 if (val == DRM_MODE_SCALE_NONE) {
2682 DRM_DEBUG_KMS("no scaling not supported\n");
2686 if (intel_connector->panel.fitting_mode == val) {
2687 /* the eDP scaling property is not changed */
2690 intel_connector->panel.fitting_mode = val;
2698 if (intel_encoder->base.crtc)
2699 intel_crtc_restore_mode(intel_encoder->base.crtc);
2705 intel_dp_destroy(struct drm_connector *connector)
2707 struct intel_dp *intel_dp = intel_attached_dp(connector);
2708 struct intel_connector *intel_connector = to_intel_connector(connector);
2710 if (!IS_ERR_OR_NULL(intel_connector->edid))
2711 kfree(intel_connector->edid);
2713 if (is_edp(intel_dp))
2714 intel_panel_fini(&intel_connector->panel);
2716 drm_sysfs_connector_remove(connector);
2717 drm_connector_cleanup(connector);
2721 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2723 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2724 struct intel_dp *intel_dp = &intel_dig_port->dp;
2725 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2727 i2c_del_adapter(&intel_dp->adapter);
2728 drm_encoder_cleanup(encoder);
2729 if (is_edp(intel_dp)) {
2730 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2731 mutex_lock(&dev->mode_config.mutex);
2732 ironlake_panel_vdd_off_sync(intel_dp);
2733 mutex_unlock(&dev->mode_config.mutex);
2735 kfree(intel_dig_port);
2738 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2739 .mode_set = intel_dp_mode_set,
2742 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2743 .dpms = intel_connector_dpms,
2744 .detect = intel_dp_detect,
2745 .fill_modes = drm_helper_probe_single_connector_modes,
2746 .set_property = intel_dp_set_property,
2747 .destroy = intel_dp_destroy,
2750 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2751 .get_modes = intel_dp_get_modes,
2752 .mode_valid = intel_dp_mode_valid,
2753 .best_encoder = intel_best_encoder,
2756 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2757 .destroy = intel_dp_encoder_destroy,
2761 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2763 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2765 intel_dp_check_link_status(intel_dp);
2768 /* Return which DP Port should be selected for Transcoder DP control */
2770 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2772 struct drm_device *dev = crtc->dev;
2773 struct intel_encoder *intel_encoder;
2774 struct intel_dp *intel_dp;
2776 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2777 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2779 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2780 intel_encoder->type == INTEL_OUTPUT_EDP)
2781 return intel_dp->output_reg;
2787 /* check the VBT to see whether the eDP is on DP-D port */
2788 bool intel_dpd_is_edp(struct drm_device *dev)
2790 struct drm_i915_private *dev_priv = dev->dev_private;
2791 struct child_device_config *p_child;
2794 if (!dev_priv->vbt.child_dev_num)
2797 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2798 p_child = dev_priv->vbt.child_dev + i;
2800 if (p_child->dvo_port == PORT_IDPD &&
2801 p_child->device_type == DEVICE_TYPE_eDP)
2808 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2810 struct intel_connector *intel_connector = to_intel_connector(connector);
2812 intel_attach_force_audio_property(connector);
2813 intel_attach_broadcast_rgb_property(connector);
2814 intel_dp->color_range_auto = true;
2816 if (is_edp(intel_dp)) {
2817 drm_mode_create_scaling_mode_property(connector->dev);
2818 drm_object_attach_property(
2820 connector->dev->mode_config.scaling_mode_property,
2821 DRM_MODE_SCALE_ASPECT);
2822 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2827 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2828 struct intel_dp *intel_dp,
2829 struct edp_power_seq *out)
2831 struct drm_i915_private *dev_priv = dev->dev_private;
2832 struct edp_power_seq cur, vbt, spec, final;
2833 u32 pp_on, pp_off, pp_div, pp;
2834 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2836 if (HAS_PCH_SPLIT(dev)) {
2837 pp_control_reg = PCH_PP_CONTROL;
2838 pp_on_reg = PCH_PP_ON_DELAYS;
2839 pp_off_reg = PCH_PP_OFF_DELAYS;
2840 pp_div_reg = PCH_PP_DIVISOR;
2842 pp_control_reg = PIPEA_PP_CONTROL;
2843 pp_on_reg = PIPEA_PP_ON_DELAYS;
2844 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2845 pp_div_reg = PIPEA_PP_DIVISOR;
2848 /* Workaround: Need to write PP_CONTROL with the unlock key as
2849 * the very first thing. */
2850 pp = ironlake_get_pp_control(intel_dp);
2851 I915_WRITE(pp_control_reg, pp);
2853 pp_on = I915_READ(pp_on_reg);
2854 pp_off = I915_READ(pp_off_reg);
2855 pp_div = I915_READ(pp_div_reg);
2857 /* Pull timing values out of registers */
2858 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2859 PANEL_POWER_UP_DELAY_SHIFT;
2861 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2862 PANEL_LIGHT_ON_DELAY_SHIFT;
2864 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2865 PANEL_LIGHT_OFF_DELAY_SHIFT;
2867 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2868 PANEL_POWER_DOWN_DELAY_SHIFT;
2870 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2871 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2873 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2874 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2876 vbt = dev_priv->vbt.edp_pps;
2878 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2879 * our hw here, which are all in 100usec. */
2880 spec.t1_t3 = 210 * 10;
2881 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2882 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2883 spec.t10 = 500 * 10;
2884 /* This one is special and actually in units of 100ms, but zero
2885 * based in the hw (so we need to add 100 ms). But the sw vbt
2886 * table multiplies it with 1000 to make it in units of 100usec,
2888 spec.t11_t12 = (510 + 100) * 10;
2890 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2891 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2893 /* Use the max of the register settings and vbt. If both are
2894 * unset, fall back to the spec limits. */
2895 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2897 max(cur.field, vbt.field))
2898 assign_final(t1_t3);
2902 assign_final(t11_t12);
2905 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2906 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2907 intel_dp->backlight_on_delay = get_delay(t8);
2908 intel_dp->backlight_off_delay = get_delay(t9);
2909 intel_dp->panel_power_down_delay = get_delay(t10);
2910 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2913 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2914 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2915 intel_dp->panel_power_cycle_delay);
2917 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2918 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2925 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2926 struct intel_dp *intel_dp,
2927 struct edp_power_seq *seq)
2929 struct drm_i915_private *dev_priv = dev->dev_private;
2930 u32 pp_on, pp_off, pp_div, port_sel = 0;
2931 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2932 int pp_on_reg, pp_off_reg, pp_div_reg;
2934 if (HAS_PCH_SPLIT(dev)) {
2935 pp_on_reg = PCH_PP_ON_DELAYS;
2936 pp_off_reg = PCH_PP_OFF_DELAYS;
2937 pp_div_reg = PCH_PP_DIVISOR;
2939 pp_on_reg = PIPEA_PP_ON_DELAYS;
2940 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2941 pp_div_reg = PIPEA_PP_DIVISOR;
2944 if (IS_VALLEYVIEW(dev))
2945 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2947 /* And finally store the new values in the power sequencer. */
2948 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2949 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2950 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2951 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2952 /* Compute the divisor for the pp clock, simply match the Bspec
2954 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2955 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2956 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2958 /* Haswell doesn't have any port selection bits for the panel
2959 * power sequencer any more. */
2960 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2961 if (is_cpu_edp(intel_dp))
2962 port_sel = PANEL_POWER_PORT_DP_A;
2964 port_sel = PANEL_POWER_PORT_DP_D;
2969 I915_WRITE(pp_on_reg, pp_on);
2970 I915_WRITE(pp_off_reg, pp_off);
2971 I915_WRITE(pp_div_reg, pp_div);
2973 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2974 I915_READ(pp_on_reg),
2975 I915_READ(pp_off_reg),
2976 I915_READ(pp_div_reg));
2980 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2981 struct intel_connector *intel_connector)
2983 struct drm_connector *connector = &intel_connector->base;
2984 struct intel_dp *intel_dp = &intel_dig_port->dp;
2985 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2986 struct drm_device *dev = intel_encoder->base.dev;
2987 struct drm_i915_private *dev_priv = dev->dev_private;
2988 struct drm_display_mode *fixed_mode = NULL;
2989 struct edp_power_seq power_seq = { 0 };
2990 enum port port = intel_dig_port->port;
2991 const char *name = NULL;
2994 /* Preserve the current hw state. */
2995 intel_dp->DP = I915_READ(intel_dp->output_reg);
2996 intel_dp->attached_connector = intel_connector;
2998 type = DRM_MODE_CONNECTOR_DisplayPort;
3000 * FIXME : We need to initialize built-in panels before external panels.
3001 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3005 type = DRM_MODE_CONNECTOR_eDP;
3008 if (IS_VALLEYVIEW(dev))
3009 type = DRM_MODE_CONNECTOR_eDP;
3012 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3013 type = DRM_MODE_CONNECTOR_eDP;
3015 default: /* silence GCC warning */
3020 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3021 * for DP the encoder type can be set by the caller to
3022 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3024 if (type == DRM_MODE_CONNECTOR_eDP)
3025 intel_encoder->type = INTEL_OUTPUT_EDP;
3027 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3028 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3031 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3032 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3034 connector->interlace_allowed = true;
3035 connector->doublescan_allowed = 0;
3037 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3038 ironlake_panel_vdd_work);
3040 intel_connector_attach_encoder(intel_connector, intel_encoder);
3041 drm_sysfs_connector_add(connector);
3044 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3046 intel_connector->get_hw_state = intel_connector_get_hw_state;
3048 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3050 switch (intel_dig_port->port) {
3052 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3055 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3058 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3061 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3068 /* Set up the DDC bus. */
3071 intel_encoder->hpd_pin = HPD_PORT_A;
3075 intel_encoder->hpd_pin = HPD_PORT_B;
3079 intel_encoder->hpd_pin = HPD_PORT_C;
3083 intel_encoder->hpd_pin = HPD_PORT_D;
3090 if (is_edp(intel_dp))
3091 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3093 intel_dp_i2c_init(intel_dp, intel_connector, name);
3095 /* Cache DPCD and EDID for edp. */
3096 if (is_edp(intel_dp)) {
3098 struct drm_display_mode *scan;
3101 ironlake_edp_panel_vdd_on(intel_dp);
3102 ret = intel_dp_get_dpcd(intel_dp);
3103 ironlake_edp_panel_vdd_off(intel_dp, false);
3106 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3107 dev_priv->no_aux_handshake =
3108 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3109 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3111 /* if this fails, presume the device is a ghost */
3112 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3113 intel_dp_encoder_destroy(&intel_encoder->base);
3114 intel_dp_destroy(connector);
3118 /* We now know it's not a ghost, init power sequence regs. */
3119 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3122 ironlake_edp_panel_vdd_on(intel_dp);
3123 edid = drm_get_edid(connector, &intel_dp->adapter);
3125 if (drm_add_edid_modes(connector, edid)) {
3126 drm_mode_connector_update_edid_property(connector, edid);
3127 drm_edid_to_eld(connector, edid);
3130 edid = ERR_PTR(-EINVAL);
3133 edid = ERR_PTR(-ENOENT);
3135 intel_connector->edid = edid;
3137 /* prefer fixed mode from EDID if available */
3138 list_for_each_entry(scan, &connector->probed_modes, head) {
3139 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3140 fixed_mode = drm_mode_duplicate(dev, scan);
3145 /* fallback to VBT if available for eDP */
3146 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3147 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
3149 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3152 ironlake_edp_panel_vdd_off(intel_dp, false);
3155 if (is_edp(intel_dp)) {
3156 intel_panel_init(&intel_connector->panel, fixed_mode);
3157 intel_panel_setup_backlight(connector);
3160 intel_dp_add_properties(intel_dp, connector);
3162 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3163 * 0xd. Failure to do so will result in spurious interrupts being
3164 * generated on the port when a cable is not attached.
3166 if (IS_G4X(dev) && !IS_GM45(dev)) {
3167 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3168 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3173 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3175 struct intel_digital_port *intel_dig_port;
3176 struct intel_encoder *intel_encoder;
3177 struct drm_encoder *encoder;
3178 struct intel_connector *intel_connector;
3180 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3181 if (!intel_dig_port)
3184 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3185 if (!intel_connector) {
3186 kfree(intel_dig_port);
3190 intel_encoder = &intel_dig_port->base;
3191 encoder = &intel_encoder->base;
3193 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3194 DRM_MODE_ENCODER_TMDS);
3195 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
3197 intel_encoder->compute_config = intel_dp_compute_config;
3198 intel_encoder->enable = intel_enable_dp;
3199 intel_encoder->pre_enable = intel_pre_enable_dp;
3200 intel_encoder->disable = intel_disable_dp;
3201 intel_encoder->post_disable = intel_post_disable_dp;
3202 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3203 intel_encoder->get_config = intel_dp_get_config;
3204 if (IS_VALLEYVIEW(dev))
3205 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3207 intel_dig_port->port = port;
3208 intel_dig_port->dp.output_reg = output_reg;
3210 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3211 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3212 intel_encoder->cloneable = false;
3213 intel_encoder->hot_plug = intel_dp_hot_plug;
3215 intel_dp_init_connector(intel_dig_port, intel_connector);