drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_crtc_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 /* Compliance test status bits  */
  45 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  46 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  47 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  48 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49
  50 struct dp_link_dpll {
  51         int clock;
  52         struct dpll dpll;
  53 };
  54
  55 static const struct dp_link_dpll gen4_dpll[] = {
  56         { 162000,
  57                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  58         { 270000,
  59                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  60 };
  61
  62 static const struct dp_link_dpll pch_dpll[] = {
  63         { 162000,
  64                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  65         { 270000,
  66                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  67 };
  68
  69 static const struct dp_link_dpll vlv_dpll[] = {
  70         { 162000,
  71                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  72         { 270000,
  73                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  74 };
  75
  76 /*
  77  * CHV supports eDP 1.4 that have  more link rates.
  78  * Below only provides the fixed rate but exclude variable rate.
  79  */
  80 static const struct dp_link_dpll chv_dpll[] = {
  81         /*
  82          * CHV requires to program fractional division for m2.
  83          * m2 is stored in fixed point format using formula below
  84          * (m2_int << 22) | m2_fraction
  85          */
  86         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  87                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  88         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  89                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  90         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  92 };
  93
  94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  95                                   324000, 432000, 540000 };
  96 static const int skl_rates[] = { 162000, 216000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int default_rates[] = { 162000, 270000, 540000 };
  99
 100 /**
 101  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 102  * @intel_dp: DP struct
 103  *
 104  * If a CPU or PCH DP output is attached to an eDP panel, this function
 105  * will return true, and false otherwise.
 106  */
 107 static bool is_edp(struct intel_dp *intel_dp)
 108 {
 109         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 110
 111         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 112 }
 113
 114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 115 {
 116         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 117
 118         return intel_dig_port->base.base.dev;
 119 }
 120
 121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 122 {
 123         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 124 }
 125
 126 static void intel_dp_link_down(struct intel_dp *intel_dp);
 127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 130 static void vlv_steal_power_sequencer(struct drm_device *dev,
 131                                       enum pipe pipe);
 132
 133 static unsigned int intel_dp_unused_lane_mask(int lane_count)
 134 {
 135         return ~((1 << lane_count) - 1) & 0xf;
 136 }
 137
 138 static int
 139 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 140 {
 141         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 142
 143         switch (max_link_bw) {
 144         case DP_LINK_BW_1_62:
 145         case DP_LINK_BW_2_7:
 146         case DP_LINK_BW_5_4:
 147                 break;
 148         default:
 149                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 150                      max_link_bw);
 151                 max_link_bw = DP_LINK_BW_1_62;
 152                 break;
 153         }
 154         return max_link_bw;
 155 }
 156
 157 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 158 {
 159         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 160         u8 source_max, sink_max;
 161
 162         source_max = intel_dig_port->max_lanes;
 163         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 164
 165         return min(source_max, sink_max);
 166 }
 167
 168 /*
 169  * The units on the numbers in the next two are... bizarre.  Examples will
 170  * make it clearer; this one parallels an example in the eDP spec.
 171  *
 172  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 173  *
 174  *     270000 * 1 * 8 / 10 == 216000
 175  *
 176  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 177  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 178  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 179  * 119000.  At 18bpp that's 2142000 kilobits per second.
 180  *
 181  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 182  * get the result in decakilobits instead of kilobits.
 183  */
 184
 185 static int
 186 intel_dp_link_required(int pixel_clock, int bpp)
 187 {
 188         return (pixel_clock * bpp + 9) / 10;
 189 }
 190
 191 static int
 192 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 193 {
 194         return (max_link_clock * max_lanes * 8) / 10;
 195 }
 196
 197 static enum drm_mode_status
 198 intel_dp_mode_valid(struct drm_connector *connector,
 199                     struct drm_display_mode *mode)
 200 {
 201         struct intel_dp *intel_dp = intel_attached_dp(connector);
 202         struct intel_connector *intel_connector = to_intel_connector(connector);
 203         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 204         int target_clock = mode->clock;
 205         int max_rate, mode_rate, max_lanes, max_link_clock;
 206
 207         if (is_edp(intel_dp) && fixed_mode) {
 208                 if (mode->hdisplay > fixed_mode->hdisplay)
 209                         return MODE_PANEL;
 210
 211                 if (mode->vdisplay > fixed_mode->vdisplay)
 212                         return MODE_PANEL;
 213
 214                 target_clock = fixed_mode->clock;
 215         }
 216
 217         max_link_clock = intel_dp_max_link_rate(intel_dp);
 218         max_lanes = intel_dp_max_lane_count(intel_dp);
 219
 220         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 221         mode_rate = intel_dp_link_required(target_clock, 18);
 222
 223         if (mode_rate > max_rate)
 224                 return MODE_CLOCK_HIGH;
 225
 226         if (mode->clock < 10000)
 227                 return MODE_CLOCK_LOW;
 228
 229         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 230                 return MODE_H_ILLEGAL;
 231
 232         return MODE_OK;
 233 }
 234
 235 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 236 {
 237         int     i;
 238         uint32_t v = 0;
 239
 240         if (src_bytes > 4)
 241                 src_bytes = 4;
 242         for (i = 0; i < src_bytes; i++)
 243                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 244         return v;
 245 }
 246
 247 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 248 {
 249         int i;
 250         if (dst_bytes > 4)
 251                 dst_bytes = 4;
 252         for (i = 0; i < dst_bytes; i++)
 253                 dst[i] = src >> ((3-i) * 8);
 254 }
 255
 256 static void
 257 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 258                                     struct intel_dp *intel_dp);
 259 static void
 260 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 261                                               struct intel_dp *intel_dp);
 262
 263 static void pps_lock(struct intel_dp *intel_dp)
 264 {
 265         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 266         struct intel_encoder *encoder = &intel_dig_port->base;
 267         struct drm_device *dev = encoder->base.dev;
 268         struct drm_i915_private *dev_priv = dev->dev_private;
 269         enum intel_display_power_domain power_domain;
 270
 271         /*
 272          * See vlv_power_sequencer_reset() why we need
 273          * a power domain reference here.
 274          */
 275         power_domain = intel_display_port_aux_power_domain(encoder);
 276         intel_display_power_get(dev_priv, power_domain);
 277
 278         mutex_lock(&dev_priv->pps_mutex);
 279 }
 280
 281 static void pps_unlock(struct intel_dp *intel_dp)
 282 {
 283         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 284         struct intel_encoder *encoder = &intel_dig_port->base;
 285         struct drm_device *dev = encoder->base.dev;
 286         struct drm_i915_private *dev_priv = dev->dev_private;
 287         enum intel_display_power_domain power_domain;
 288
 289         mutex_unlock(&dev_priv->pps_mutex);
 290
 291         power_domain = intel_display_port_aux_power_domain(encoder);
 292         intel_display_power_put(dev_priv, power_domain);
 293 }
 294
 295 static void
 296 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 297 {
 298         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 299         struct drm_device *dev = intel_dig_port->base.base.dev;
 300         struct drm_i915_private *dev_priv = dev->dev_private;
 301         enum pipe pipe = intel_dp->pps_pipe;
 302         bool pll_enabled, release_cl_override = false;
 303         enum dpio_phy phy = DPIO_PHY(pipe);
 304         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 305         uint32_t DP;
 306
 307         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 308                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 309                  pipe_name(pipe), port_name(intel_dig_port->port)))
 310                 return;
 311
 312         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 313                       pipe_name(pipe), port_name(intel_dig_port->port));
 314
 315         /* Preserve the BIOS-computed detected bit. This is
 316          * supposed to be read-only.
 317          */
 318         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 319         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 320         DP |= DP_PORT_WIDTH(1);
 321         DP |= DP_LINK_TRAIN_PAT_1;
 322
 323         if (IS_CHERRYVIEW(dev))
 324                 DP |= DP_PIPE_SELECT_CHV(pipe);
 325         else if (pipe == PIPE_B)
 326                 DP |= DP_PIPEB_SELECT;
 327
 328         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 329
 330         /*
 331          * The DPLL for the pipe must be enabled for this to work.
 332          * So enable temporarily it if it's not already enabled.
 333          */
 334         if (!pll_enabled) {
 335                 release_cl_override = IS_CHERRYVIEW(dev) &&
 336                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 337
 338                 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 339                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 340                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 341                                   pipe_name(pipe));
 342                         return;
 343                 }
 344         }
 345
 346         /*
 347          * Similar magic as in intel_dp_enable_port().
 348          * We _must_ do this port enable + disable trick
 349          * to make this power seqeuencer lock onto the port.
 350          * Otherwise even VDD force bit won't work.
 351          */
 352         I915_WRITE(intel_dp->output_reg, DP);
 353         POSTING_READ(intel_dp->output_reg);
 354
 355         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 356         POSTING_READ(intel_dp->output_reg);
 357
 358         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 359         POSTING_READ(intel_dp->output_reg);
 360
 361         if (!pll_enabled) {
 362                 vlv_force_pll_off(dev, pipe);
 363
 364                 if (release_cl_override)
 365                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 366         }
 367 }
 368
 369 static enum pipe
 370 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 371 {
 372         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 373         struct drm_device *dev = intel_dig_port->base.base.dev;
 374         struct drm_i915_private *dev_priv = dev->dev_private;
 375         struct intel_encoder *encoder;
 376         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 377         enum pipe pipe;
 378
 379         lockdep_assert_held(&dev_priv->pps_mutex);
 380
 381         /* We should never land here with regular DP ports */
 382         WARN_ON(!is_edp(intel_dp));
 383
 384         if (intel_dp->pps_pipe != INVALID_PIPE)
 385                 return intel_dp->pps_pipe;
 386
 387         /*
 388          * We don't have power sequencer currently.
 389          * Pick one that's not used by other ports.
 390          */
 391         for_each_intel_encoder(dev, encoder) {
 392                 struct intel_dp *tmp;
 393
 394                 if (encoder->type != INTEL_OUTPUT_EDP)
 395                         continue;
 396
 397                 tmp = enc_to_intel_dp(&encoder->base);
 398
 399                 if (tmp->pps_pipe != INVALID_PIPE)
 400                         pipes &= ~(1 << tmp->pps_pipe);
 401         }
 402
 403         /*
 404          * Didn't find one. This should not happen since there
 405          * are two power sequencers and up to two eDP ports.
 406          */
 407         if (WARN_ON(pipes == 0))
 408                 pipe = PIPE_A;
 409         else
 410                 pipe = ffs(pipes) - 1;
 411
 412         vlv_steal_power_sequencer(dev, pipe);
 413         intel_dp->pps_pipe = pipe;
 414
 415         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 416                       pipe_name(intel_dp->pps_pipe),
 417                       port_name(intel_dig_port->port));
 418
 419         /* init power sequencer on this pipe and port */
 420         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 421         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 422
 423         /*
 424          * Even vdd force doesn't work until we've made
 425          * the power sequencer lock in on the port.
 426          */
 427         vlv_power_sequencer_kick(intel_dp);
 428
 429         return intel_dp->pps_pipe;
 430 }
 431
 432 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 433                                enum pipe pipe);
 434
 435 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 436                                enum pipe pipe)
 437 {
 438         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 439 }
 440
 441 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 442                                 enum pipe pipe)
 443 {
 444         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 445 }
 446
 447 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 448                          enum pipe pipe)
 449 {
 450         return true;
 451 }
 452
 453 static enum pipe
 454 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 455                      enum port port,
 456                      vlv_pipe_check pipe_check)
 457 {
 458         enum pipe pipe;
 459
 460         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 461                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 462                         PANEL_PORT_SELECT_MASK;
 463
 464                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 465                         continue;
 466
 467                 if (!pipe_check(dev_priv, pipe))
 468                         continue;
 469
 470                 return pipe;
 471         }
 472
 473         return INVALID_PIPE;
 474 }
 475
 476 static void
 477 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 478 {
 479         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 480         struct drm_device *dev = intel_dig_port->base.base.dev;
 481         struct drm_i915_private *dev_priv = dev->dev_private;
 482         enum port port = intel_dig_port->port;
 483
 484         lockdep_assert_held(&dev_priv->pps_mutex);
 485
 486         /* try to find a pipe with this port selected */
 487         /* first pick one where the panel is on */
 488         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 489                                                   vlv_pipe_has_pp_on);
 490         /* didn't find one? pick one where vdd is on */
 491         if (intel_dp->pps_pipe == INVALID_PIPE)
 492                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 493                                                           vlv_pipe_has_vdd_on);
 494         /* didn't find one? pick one with just the correct port */
 495         if (intel_dp->pps_pipe == INVALID_PIPE)
 496                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 497                                                           vlv_pipe_any);
 498
 499         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 500         if (intel_dp->pps_pipe == INVALID_PIPE) {
 501                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 502                               port_name(port));
 503                 return;
 504         }
 505
 506         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 507                       port_name(port), pipe_name(intel_dp->pps_pipe));
 508
 509         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 510         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 511 }
 512
 513 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 514 {
 515         struct drm_device *dev = dev_priv->dev;
 516         struct intel_encoder *encoder;
 517
 518         if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)))
 519                 return;
 520
 521         /*
 522          * We can't grab pps_mutex here due to deadlock with power_domain
 523          * mutex when power_domain functions are called while holding pps_mutex.
 524          * That also means that in order to use pps_pipe the code needs to
 525          * hold both a power domain reference and pps_mutex, and the power domain
 526          * reference get/put must be done while _not_ holding pps_mutex.
 527          * pps_{lock,unlock}() do these steps in the correct order, so one
 528          * should use them always.
 529          */
 530
 531         for_each_intel_encoder(dev, encoder) {
 532                 struct intel_dp *intel_dp;
 533
 534                 if (encoder->type != INTEL_OUTPUT_EDP)
 535                         continue;
 536
 537                 intel_dp = enc_to_intel_dp(&encoder->base);
 538                 intel_dp->pps_pipe = INVALID_PIPE;
 539         }
 540 }
 541
 542 static i915_reg_t
 543 _pp_ctrl_reg(struct intel_dp *intel_dp)
 544 {
 545         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 546
 547         if (IS_BROXTON(dev))
 548                 return BXT_PP_CONTROL(0);
 549         else if (HAS_PCH_SPLIT(dev))
 550                 return PCH_PP_CONTROL;
 551         else
 552                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 553 }
 554
 555 static i915_reg_t
 556 _pp_stat_reg(struct intel_dp *intel_dp)
 557 {
 558         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 559
 560         if (IS_BROXTON(dev))
 561                 return BXT_PP_STATUS(0);
 562         else if (HAS_PCH_SPLIT(dev))
 563                 return PCH_PP_STATUS;
 564         else
 565                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 566 }
 567
 568 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 569    This function only applicable when panel PM state is not to be tracked */
 570 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 571                               void *unused)
 572 {
 573         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 574                                                  edp_notifier);
 575         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 576         struct drm_i915_private *dev_priv = dev->dev_private;
 577
 578         if (!is_edp(intel_dp) || code != SYS_RESTART)
 579                 return 0;
 580
 581         pps_lock(intel_dp);
 582
 583         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 584                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 585                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 586                 u32 pp_div;
 587
 588                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 589                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 590                 pp_div = I915_READ(pp_div_reg);
 591                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 592
 593                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 594                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 595                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 596                 msleep(intel_dp->panel_power_cycle_delay);
 597         }
 598
 599         pps_unlock(intel_dp);
 600
 601         return 0;
 602 }
 603
 604 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 605 {
 606         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 607         struct drm_i915_private *dev_priv = dev->dev_private;
 608
 609         lockdep_assert_held(&dev_priv->pps_mutex);
 610
 611         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 612             intel_dp->pps_pipe == INVALID_PIPE)
 613                 return false;
 614
 615         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 616 }
 617
 618 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 619 {
 620         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 621         struct drm_i915_private *dev_priv = dev->dev_private;
 622
 623         lockdep_assert_held(&dev_priv->pps_mutex);
 624
 625         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 626             intel_dp->pps_pipe == INVALID_PIPE)
 627                 return false;
 628
 629         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 630 }
 631
 632 static void
 633 intel_dp_check_edp(struct intel_dp *intel_dp)
 634 {
 635         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 636         struct drm_i915_private *dev_priv = dev->dev_private;
 637
 638         if (!is_edp(intel_dp))
 639                 return;
 640
 641         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 642                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 643                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 644                               I915_READ(_pp_stat_reg(intel_dp)),
 645                               I915_READ(_pp_ctrl_reg(intel_dp)));
 646         }
 647 }
 648
 649 static uint32_t
 650 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 651 {
 652         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 653         struct drm_device *dev = intel_dig_port->base.base.dev;
 654         struct drm_i915_private *dev_priv = dev->dev_private;
 655         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 656         uint32_t status;
 657         bool done;
 658
 659 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 660         if (has_aux_irq)
 661                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 662                                           msecs_to_jiffies_timeout(10));
 663         else
 664                 done = wait_for_atomic(C, 10) == 0;
 665         if (!done)
 666                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 667                           has_aux_irq);
 668 #undef C
 669
 670         return status;
 671 }
 672
 673 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 674 {
 675         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 676         struct drm_device *dev = intel_dig_port->base.base.dev;
 677
 678         /*
 679          * The clock divider is based off the hrawclk, and would like to run at
 680          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 681          */
 682         return index ? 0 : DIV_ROUND_CLOSEST(intel_hrawclk(dev), 2);
 683 }
 684
 685 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 686 {
 687         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 688         struct drm_device *dev = intel_dig_port->base.base.dev;
 689         struct drm_i915_private *dev_priv = dev->dev_private;
 690
 691         if (index)
 692                 return 0;
 693
 694         if (intel_dig_port->port == PORT_A) {
 695                 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 696
 697         } else {
 698                 return DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2);
 699         }
 700 }
 701
 702 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 703 {
 704         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 705         struct drm_device *dev = intel_dig_port->base.base.dev;
 706         struct drm_i915_private *dev_priv = dev->dev_private;
 707
 708         if (intel_dig_port->port == PORT_A) {
 709                 if (index)
 710                         return 0;
 711                 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 712         } else if (HAS_PCH_LPT_H(dev_priv)) {
 713                 /* Workaround for non-ULT HSW */
 714                 switch (index) {
 715                 case 0: return 63;
 716                 case 1: return 72;
 717                 default: return 0;
 718                 }
 719         } else  {
 720                 return index ? 0 : DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2);
 721         }
 722 }
 723
 724 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 725 {
 726         return index ? 0 : 100;
 727 }
 728
 729 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 730 {
 731         /*
 732          * SKL doesn't need us to program the AUX clock divider (Hardware will
 733          * derive the clock from CDCLK automatically). We still implement the
 734          * get_aux_clock_divider vfunc to plug-in into the existing code.
 735          */
 736         return index ? 0 : 1;
 737 }
 738
 739 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 740                                       bool has_aux_irq,
 741                                       int send_bytes,
 742                                       uint32_t aux_clock_divider)
 743 {
 744         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 745         struct drm_device *dev = intel_dig_port->base.base.dev;
 746         uint32_t precharge, timeout;
 747
 748         if (IS_GEN6(dev))
 749                 precharge = 3;
 750         else
 751                 precharge = 5;
 752
 753         if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
 754                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 755         else
 756                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 757
 758         return DP_AUX_CH_CTL_SEND_BUSY |
 759                DP_AUX_CH_CTL_DONE |
 760                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 761                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 762                timeout |
 763                DP_AUX_CH_CTL_RECEIVE_ERROR |
 764                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 765                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 766                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 767 }
 768
 769 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 770                                       bool has_aux_irq,
 771                                       int send_bytes,
 772                                       uint32_t unused)
 773 {
 774         return DP_AUX_CH_CTL_SEND_BUSY |
 775                DP_AUX_CH_CTL_DONE |
 776                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 777                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 778                DP_AUX_CH_CTL_TIME_OUT_1600us |
 779                DP_AUX_CH_CTL_RECEIVE_ERROR |
 780                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 781                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 782 }
 783
 784 static int
 785 intel_dp_aux_ch(struct intel_dp *intel_dp,
 786                 const uint8_t *send, int send_bytes,
 787                 uint8_t *recv, int recv_size)
 788 {
 789         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 790         struct drm_device *dev = intel_dig_port->base.base.dev;
 791         struct drm_i915_private *dev_priv = dev->dev_private;
 792         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 793         uint32_t aux_clock_divider;
 794         int i, ret, recv_bytes;
 795         uint32_t status;
 796         int try, clock = 0;
 797         bool has_aux_irq = HAS_AUX_IRQ(dev);
 798         bool vdd;
 799
 800         pps_lock(intel_dp);
 801
 802         /*
 803          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 804          * In such cases we want to leave VDD enabled and it's up to upper layers
 805          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 806          * ourselves.
 807          */
 808         vdd = edp_panel_vdd_on(intel_dp);
 809
 810         /* dp aux is extremely sensitive to irq latency, hence request the
 811          * lowest possible wakeup latency and so prevent the cpu from going into
 812          * deep sleep states.
 813          */
 814         pm_qos_update_request(&dev_priv->pm_qos, 0);
 815
 816         intel_dp_check_edp(intel_dp);
 817
 818         /* Try to wait for any previous AUX channel activity */
 819         for (try = 0; try < 3; try++) {
 820                 status = I915_READ_NOTRACE(ch_ctl);
 821                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 822                         break;
 823                 msleep(1);
 824         }
 825
 826         if (try == 3) {
 827                 static u32 last_status = -1;
 828                 const u32 status = I915_READ(ch_ctl);
 829
 830                 if (status != last_status) {
 831                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
 832                              status);
 833                         last_status = status;
 834                 }
 835
 836                 ret = -EBUSY;
 837                 goto out;
 838         }
 839
 840         /* Only 5 data registers! */
 841         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 842                 ret = -E2BIG;
 843                 goto out;
 844         }
 845
 846         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 847                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 848                                                           has_aux_irq,
 849                                                           send_bytes,
 850                                                           aux_clock_divider);
 851
 852                 /* Must try at least 3 times according to DP spec */
 853                 for (try = 0; try < 5; try++) {
 854                         /* Load the send data into the aux channel data registers */
 855                         for (i = 0; i < send_bytes; i += 4)
 856                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
 857                                            intel_dp_pack_aux(send + i,
 858                                                              send_bytes - i));
 859
 860                         /* Send the command and wait for it to complete */
 861                         I915_WRITE(ch_ctl, send_ctl);
 862
 863                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 864
 865                         /* Clear done status and any errors */
 866                         I915_WRITE(ch_ctl,
 867                                    status |
 868                                    DP_AUX_CH_CTL_DONE |
 869                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 870                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 871
 872                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
 873                                 continue;
 874
 875                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
 876                          *   400us delay required for errors and timeouts
 877                          *   Timeout errors from the HW already meet this
 878                          *   requirement so skip to next iteration
 879                          */
 880                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 881                                 usleep_range(400, 500);
 882                                 continue;
 883                         }
 884                         if (status & DP_AUX_CH_CTL_DONE)
 885                                 goto done;
 886                 }
 887         }
 888
 889         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 890                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 891                 ret = -EBUSY;
 892                 goto out;
 893         }
 894
 895 done:
 896         /* Check for timeout or receive error.
 897          * Timeouts occur when the sink is not connected
 898          */
 899         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 900                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 901                 ret = -EIO;
 902                 goto out;
 903         }
 904
 905         /* Timeouts occur when the device isn't connected, so they're
 906          * "normal" -- don't fill the kernel log with these */
 907         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 908                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 909                 ret = -ETIMEDOUT;
 910                 goto out;
 911         }
 912
 913         /* Unload any bytes sent back from the other side */
 914         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 915                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 916
 917         /*
 918          * By BSpec: "Message sizes of 0 or >20 are not allowed."
 919          * We have no idea of what happened so we return -EBUSY so
 920          * drm layer takes care for the necessary retries.
 921          */
 922         if (recv_bytes == 0 || recv_bytes > 20) {
 923                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
 924                               recv_bytes);
 925                 /*
 926                  * FIXME: This patch was created on top of a series that
 927                  * organize the retries at drm level. There EBUSY should
 928                  * also take care for 1ms wait before retrying.
 929                  * That aux retries re-org is still needed and after that is
 930                  * merged we remove this sleep from here.
 931                  */
 932                 usleep_range(1000, 1500);
 933                 ret = -EBUSY;
 934                 goto out;
 935         }
 936
 937         if (recv_bytes > recv_size)
 938                 recv_bytes = recv_size;
 939
 940         for (i = 0; i < recv_bytes; i += 4)
 941                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
 942                                     recv + i, recv_bytes - i);
 943
 944         ret = recv_bytes;
 945 out:
 946         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 947
 948         if (vdd)
 949                 edp_panel_vdd_off(intel_dp, false);
 950
 951         pps_unlock(intel_dp);
 952
 953         return ret;
 954 }
 955
 956 #define BARE_ADDRESS_SIZE       3
 957 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 958 static ssize_t
 959 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 960 {
 961         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 962         uint8_t txbuf[20], rxbuf[20];
 963         size_t txsize, rxsize;
 964         int ret;
 965
 966         txbuf[0] = (msg->request << 4) |
 967                 ((msg->address >> 16) & 0xf);
 968         txbuf[1] = (msg->address >> 8) & 0xff;
 969         txbuf[2] = msg->address & 0xff;
 970         txbuf[3] = msg->size - 1;
 971
 972         switch (msg->request & ~DP_AUX_I2C_MOT) {
 973         case DP_AUX_NATIVE_WRITE:
 974         case DP_AUX_I2C_WRITE:
 975         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
 976                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 977                 rxsize = 2; /* 0 or 1 data bytes */
 978
 979                 if (WARN_ON(txsize > 20))
 980                         return -E2BIG;
 981
 982                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 983
 984                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 985                 if (ret > 0) {
 986                         msg->reply = rxbuf[0] >> 4;
 987
 988                         if (ret > 1) {
 989                                 /* Number of bytes written in a short write. */
 990                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
 991                         } else {
 992                                 /* Return payload size. */
 993                                 ret = msg->size;
 994                         }
 995                 }
 996                 break;
 997
 998         case DP_AUX_NATIVE_READ:
 999         case DP_AUX_I2C_READ:
1000                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1001                 rxsize = msg->size + 1;
1002
1003                 if (WARN_ON(rxsize > 20))
1004                         return -E2BIG;
1005
1006                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1007                 if (ret > 0) {
1008                         msg->reply = rxbuf[0] >> 4;
1009                         /*
1010                          * Assume happy day, and copy the data. The caller is
1011                          * expected to check msg->reply before touching it.
1012                          *
1013                          * Return payload size.
1014                          */
1015                         ret--;
1016                         memcpy(msg->buffer, rxbuf + 1, ret);
1017                 }
1018                 break;
1019
1020         default:
1021                 ret = -EINVAL;
1022                 break;
1023         }
1024
1025         return ret;
1026 }
1027
1028 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1029                                        enum port port)
1030 {
1031         switch (port) {
1032         case PORT_B:
1033         case PORT_C:
1034         case PORT_D:
1035                 return DP_AUX_CH_CTL(port);
1036         default:
1037                 MISSING_CASE(port);
1038                 return DP_AUX_CH_CTL(PORT_B);
1039         }
1040 }
1041
1042 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1043                                         enum port port, int index)
1044 {
1045         switch (port) {
1046         case PORT_B:
1047         case PORT_C:
1048         case PORT_D:
1049                 return DP_AUX_CH_DATA(port, index);
1050         default:
1051                 MISSING_CASE(port);
1052                 return DP_AUX_CH_DATA(PORT_B, index);
1053         }
1054 }
1055
1056 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1057                                        enum port port)
1058 {
1059         switch (port) {
1060         case PORT_A:
1061                 return DP_AUX_CH_CTL(port);
1062         case PORT_B:
1063         case PORT_C:
1064         case PORT_D:
1065                 return PCH_DP_AUX_CH_CTL(port);
1066         default:
1067                 MISSING_CASE(port);
1068                 return DP_AUX_CH_CTL(PORT_A);
1069         }
1070 }
1071
1072 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1073                                         enum port port, int index)
1074 {
1075         switch (port) {
1076         case PORT_A:
1077                 return DP_AUX_CH_DATA(port, index);
1078         case PORT_B:
1079         case PORT_C:
1080         case PORT_D:
1081                 return PCH_DP_AUX_CH_DATA(port, index);
1082         default:
1083                 MISSING_CASE(port);
1084                 return DP_AUX_CH_DATA(PORT_A, index);
1085         }
1086 }
1087
1088 /*
1089  * On SKL we don't have Aux for port E so we rely
1090  * on VBT to set a proper alternate aux channel.
1091  */
1092 static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1093 {
1094         const struct ddi_vbt_port_info *info =
1095                 &dev_priv->vbt.ddi_port_info[PORT_E];
1096
1097         switch (info->alternate_aux_channel) {
1098         case DP_AUX_A:
1099                 return PORT_A;
1100         case DP_AUX_B:
1101                 return PORT_B;
1102         case DP_AUX_C:
1103                 return PORT_C;
1104         case DP_AUX_D:
1105                 return PORT_D;
1106         default:
1107                 MISSING_CASE(info->alternate_aux_channel);
1108                 return PORT_A;
1109         }
1110 }
1111
1112 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1113                                        enum port port)
1114 {
1115         if (port == PORT_E)
1116                 port = skl_porte_aux_port(dev_priv);
1117
1118         switch (port) {
1119         case PORT_A:
1120         case PORT_B:
1121         case PORT_C:
1122         case PORT_D:
1123                 return DP_AUX_CH_CTL(port);
1124         default:
1125                 MISSING_CASE(port);
1126                 return DP_AUX_CH_CTL(PORT_A);
1127         }
1128 }
1129
1130 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1131                                         enum port port, int index)
1132 {
1133         if (port == PORT_E)
1134                 port = skl_porte_aux_port(dev_priv);
1135
1136         switch (port) {
1137         case PORT_A:
1138         case PORT_B:
1139         case PORT_C:
1140         case PORT_D:
1141                 return DP_AUX_CH_DATA(port, index);
1142         default:
1143                 MISSING_CASE(port);
1144                 return DP_AUX_CH_DATA(PORT_A, index);
1145         }
1146 }
1147
1148 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1149                                          enum port port)
1150 {
1151         if (INTEL_INFO(dev_priv)->gen >= 9)
1152                 return skl_aux_ctl_reg(dev_priv, port);
1153         else if (HAS_PCH_SPLIT(dev_priv))
1154                 return ilk_aux_ctl_reg(dev_priv, port);
1155         else
1156                 return g4x_aux_ctl_reg(dev_priv, port);
1157 }
1158
1159 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1160                                           enum port port, int index)
1161 {
1162         if (INTEL_INFO(dev_priv)->gen >= 9)
1163                 return skl_aux_data_reg(dev_priv, port, index);
1164         else if (HAS_PCH_SPLIT(dev_priv))
1165                 return ilk_aux_data_reg(dev_priv, port, index);
1166         else
1167                 return g4x_aux_data_reg(dev_priv, port, index);
1168 }
1169
1170 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1171 {
1172         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1173         enum port port = dp_to_dig_port(intel_dp)->port;
1174         int i;
1175
1176         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1177         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1178                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1179 }
1180
1181 static void
1182 intel_dp_aux_fini(struct intel_dp *intel_dp)
1183 {
1184         drm_dp_aux_unregister(&intel_dp->aux);
1185         kfree(intel_dp->aux.name);
1186 }
1187
1188 static int
1189 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1190 {
1191         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1192         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1193         enum port port = intel_dig_port->port;
1194         int ret;
1195
1196         intel_aux_reg_init(intel_dp);
1197
1198         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1199         if (!intel_dp->aux.name)
1200                 return -ENOMEM;
1201
1202         intel_dp->aux.dev = dev->dev;
1203         intel_dp->aux.transfer = intel_dp_aux_transfer;
1204
1205         DRM_DEBUG_KMS("registering %s bus for %s\n",
1206                       intel_dp->aux.name,
1207                       connector->base.kdev->kobj.name);
1208
1209         ret = drm_dp_aux_register(&intel_dp->aux);
1210         if (ret < 0) {
1211                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1212                           intel_dp->aux.name, ret);
1213                 kfree(intel_dp->aux.name);
1214                 return ret;
1215         }
1216
1217         ret = sysfs_create_link(&connector->base.kdev->kobj,
1218                                 &intel_dp->aux.ddc.dev.kobj,
1219                                 intel_dp->aux.ddc.dev.kobj.name);
1220         if (ret < 0) {
1221                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n",
1222                           intel_dp->aux.name, ret);
1223                 intel_dp_aux_fini(intel_dp);
1224                 return ret;
1225         }
1226
1227         return 0;
1228 }
1229
1230 static void
1231 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1232 {
1233         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1234
1235         if (!intel_connector->mst_port)
1236                 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1237                                   intel_dp->aux.ddc.dev.kobj.name);
1238         intel_connector_unregister(intel_connector);
1239 }
1240
1241 static void
1242 skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
1243 {
1244         u32 ctrl1;
1245
1246         memset(&pipe_config->dpll_hw_state, 0,
1247                sizeof(pipe_config->dpll_hw_state));
1248
1249         pipe_config->ddi_pll_sel = SKL_DPLL0;
1250         pipe_config->dpll_hw_state.cfgcr1 = 0;
1251         pipe_config->dpll_hw_state.cfgcr2 = 0;
1252
1253         ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1254         switch (pipe_config->port_clock / 2) {
1255         case 81000:
1256                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
1257                                               SKL_DPLL0);
1258                 break;
1259         case 135000:
1260                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
1261                                               SKL_DPLL0);
1262                 break;
1263         case 270000:
1264                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
1265                                               SKL_DPLL0);
1266                 break;
1267         case 162000:
1268                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
1269                                               SKL_DPLL0);
1270                 break;
1271         /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1272         results in CDCLK change. Need to handle the change of CDCLK by
1273         disabling pipes and re-enabling them */
1274         case 108000:
1275                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
1276                                               SKL_DPLL0);
1277                 break;
1278         case 216000:
1279                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
1280                                               SKL_DPLL0);
1281                 break;
1282
1283         }
1284         pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1285 }
1286
1287 void
1288 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
1289 {
1290         memset(&pipe_config->dpll_hw_state, 0,
1291                sizeof(pipe_config->dpll_hw_state));
1292
1293         switch (pipe_config->port_clock / 2) {
1294         case 81000:
1295                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1296                 break;
1297         case 135000:
1298                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1299                 break;
1300         case 270000:
1301                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1302                 break;
1303         }
1304 }
1305
1306 static int
1307 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1308 {
1309         if (intel_dp->num_sink_rates) {
1310                 *sink_rates = intel_dp->sink_rates;
1311                 return intel_dp->num_sink_rates;
1312         }
1313
1314         *sink_rates = default_rates;
1315
1316         return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1317 }
1318
1319 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1320 {
1321         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1322         struct drm_device *dev = dig_port->base.base.dev;
1323
1324         /* WaDisableHBR2:skl */
1325         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
1326                 return false;
1327
1328         if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1329             (INTEL_INFO(dev)->gen >= 9))
1330                 return true;
1331         else
1332                 return false;
1333 }
1334
1335 static int
1336 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
1337 {
1338         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1339         struct drm_device *dev = dig_port->base.base.dev;
1340         int size;
1341
1342         if (IS_BROXTON(dev)) {
1343                 *source_rates = bxt_rates;
1344                 size = ARRAY_SIZE(bxt_rates);
1345         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1346                 *source_rates = skl_rates;
1347                 size = ARRAY_SIZE(skl_rates);
1348         } else {
1349                 *source_rates = default_rates;
1350                 size = ARRAY_SIZE(default_rates);
1351         }
1352
1353         /* This depends on the fact that 5.4 is last value in the array */
1354         if (!intel_dp_source_supports_hbr2(intel_dp))
1355                 size--;
1356
1357         return size;
1358 }
1359
1360 static void
1361 intel_dp_set_clock(struct intel_encoder *encoder,
1362                    struct intel_crtc_state *pipe_config)
1363 {
1364         struct drm_device *dev = encoder->base.dev;
1365         const struct dp_link_dpll *divisor = NULL;
1366         int i, count = 0;
1367
1368         if (IS_G4X(dev)) {
1369                 divisor = gen4_dpll;
1370                 count = ARRAY_SIZE(gen4_dpll);
1371         } else if (HAS_PCH_SPLIT(dev)) {
1372                 divisor = pch_dpll;
1373                 count = ARRAY_SIZE(pch_dpll);
1374         } else if (IS_CHERRYVIEW(dev)) {
1375                 divisor = chv_dpll;
1376                 count = ARRAY_SIZE(chv_dpll);
1377         } else if (IS_VALLEYVIEW(dev)) {
1378                 divisor = vlv_dpll;
1379                 count = ARRAY_SIZE(vlv_dpll);
1380         }
1381
1382         if (divisor && count) {
1383                 for (i = 0; i < count; i++) {
1384                         if (pipe_config->port_clock == divisor[i].clock) {
1385                                 pipe_config->dpll = divisor[i].dpll;
1386                                 pipe_config->clock_set = true;
1387                                 break;
1388                         }
1389                 }
1390         }
1391 }
1392
1393 static int intersect_rates(const int *source_rates, int source_len,
1394                            const int *sink_rates, int sink_len,
1395                            int *common_rates)
1396 {
1397         int i = 0, j = 0, k = 0;
1398
1399         while (i < source_len && j < sink_len) {
1400                 if (source_rates[i] == sink_rates[j]) {
1401                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1402                                 return k;
1403                         common_rates[k] = source_rates[i];
1404                         ++k;
1405                         ++i;
1406                         ++j;
1407                 } else if (source_rates[i] < sink_rates[j]) {
1408                         ++i;
1409                 } else {
1410                         ++j;
1411                 }
1412         }
1413         return k;
1414 }
1415
1416 static int intel_dp_common_rates(struct intel_dp *intel_dp,
1417                                  int *common_rates)
1418 {
1419         const int *source_rates, *sink_rates;
1420         int source_len, sink_len;
1421
1422         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1423         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1424
1425         return intersect_rates(source_rates, source_len,
1426                                sink_rates, sink_len,
1427                                common_rates);
1428 }
1429
1430 static void snprintf_int_array(char *str, size_t len,
1431                                const int *array, int nelem)
1432 {
1433         int i;
1434
1435         str[0] = '\0';
1436
1437         for (i = 0; i < nelem; i++) {
1438                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1439                 if (r >= len)
1440                         return;
1441                 str += r;
1442                 len -= r;
1443         }
1444 }
1445
1446 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1447 {
1448         const int *source_rates, *sink_rates;
1449         int source_len, sink_len, common_len;
1450         int common_rates[DP_MAX_SUPPORTED_RATES];
1451         char str[128]; /* FIXME: too big for stack? */
1452
1453         if ((drm_debug & DRM_UT_KMS) == 0)
1454                 return;
1455
1456         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1457         snprintf_int_array(str, sizeof(str), source_rates, source_len);
1458         DRM_DEBUG_KMS("source rates: %s\n", str);
1459
1460         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1461         snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1462         DRM_DEBUG_KMS("sink rates: %s\n", str);
1463
1464         common_len = intel_dp_common_rates(intel_dp, common_rates);
1465         snprintf_int_array(str, sizeof(str), common_rates, common_len);
1466         DRM_DEBUG_KMS("common rates: %s\n", str);
1467 }
1468
1469 static int rate_to_index(int find, const int *rates)
1470 {
1471         int i = 0;
1472
1473         for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1474                 if (find == rates[i])
1475                         break;
1476
1477         return i;
1478 }
1479
1480 int
1481 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1482 {
1483         int rates[DP_MAX_SUPPORTED_RATES] = {};
1484         int len;
1485
1486         len = intel_dp_common_rates(intel_dp, rates);
1487         if (WARN_ON(len <= 0))
1488                 return 162000;
1489
1490         return rates[rate_to_index(0, rates) - 1];
1491 }
1492
1493 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1494 {
1495         return rate_to_index(rate, intel_dp->sink_rates);
1496 }
1497
1498 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1499                            uint8_t *link_bw, uint8_t *rate_select)
1500 {
1501         if (intel_dp->num_sink_rates) {
1502                 *link_bw = 0;
1503                 *rate_select =
1504                         intel_dp_rate_select(intel_dp, port_clock);
1505         } else {
1506                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1507                 *rate_select = 0;
1508         }
1509 }
1510
1511 bool
1512 intel_dp_compute_config(struct intel_encoder *encoder,
1513                         struct intel_crtc_state *pipe_config)
1514 {
1515         struct drm_device *dev = encoder->base.dev;
1516         struct drm_i915_private *dev_priv = dev->dev_private;
1517         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1518         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1519         enum port port = dp_to_dig_port(intel_dp)->port;
1520         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1521         struct intel_connector *intel_connector = intel_dp->attached_connector;
1522         int lane_count, clock;
1523         int min_lane_count = 1;
1524         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1525         /* Conveniently, the link BW constants become indices with a shift...*/
1526         int min_clock = 0;
1527         int max_clock;
1528         int bpp, mode_rate;
1529         int link_avail, link_clock;
1530         int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1531         int common_len;
1532         uint8_t link_bw, rate_select;
1533
1534         common_len = intel_dp_common_rates(intel_dp, common_rates);
1535
1536         /* No common link rates between source and sink */
1537         WARN_ON(common_len <= 0);
1538
1539         max_clock = common_len - 1;
1540
1541         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1542                 pipe_config->has_pch_encoder = true;
1543
1544         pipe_config->has_dp_encoder = true;
1545         pipe_config->has_drrs = false;
1546         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1547
1548         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1549                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1550                                        adjusted_mode);
1551
1552                 if (INTEL_INFO(dev)->gen >= 9) {
1553                         int ret;
1554                         ret = skl_update_scaler_crtc(pipe_config);
1555                         if (ret)
1556                                 return ret;
1557                 }
1558
1559                 if (HAS_GMCH_DISPLAY(dev))
1560                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1561                                                  intel_connector->panel.fitting_mode);
1562                 else
1563                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1564                                                 intel_connector->panel.fitting_mode);
1565         }
1566
1567         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1568                 return false;
1569
1570         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1571                       "max bw %d pixel clock %iKHz\n",
1572                       max_lane_count, common_rates[max_clock],
1573                       adjusted_mode->crtc_clock);
1574
1575         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1576          * bpc in between. */
1577         bpp = pipe_config->pipe_bpp;
1578         if (is_edp(intel_dp)) {
1579
1580                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1581                 if (intel_connector->base.display_info.bpc == 0 &&
1582                         (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) {
1583                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1584                                       dev_priv->vbt.edp_bpp);
1585                         bpp = dev_priv->vbt.edp_bpp;
1586                 }
1587
1588                 /*
1589                  * Use the maximum clock and number of lanes the eDP panel
1590                  * advertizes being capable of. The panels are generally
1591                  * designed to support only a single clock and lane
1592                  * configuration, and typically these values correspond to the
1593                  * native resolution of the panel.
1594                  */
1595                 min_lane_count = max_lane_count;
1596                 min_clock = max_clock;
1597         }
1598
1599         for (; bpp >= 6*3; bpp -= 2*3) {
1600                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1601                                                    bpp);
1602
1603                 for (clock = min_clock; clock <= max_clock; clock++) {
1604                         for (lane_count = min_lane_count;
1605                                 lane_count <= max_lane_count;
1606                                 lane_count <<= 1) {
1607
1608                                 link_clock = common_rates[clock];
1609                                 link_avail = intel_dp_max_data_rate(link_clock,
1610                                                                     lane_count);
1611
1612                                 if (mode_rate <= link_avail) {
1613                                         goto found;
1614                                 }
1615                         }
1616                 }
1617         }
1618
1619         return false;
1620
1621 found:
1622         if (intel_dp->color_range_auto) {
1623                 /*
1624                  * See:
1625                  * CEA-861-E - 5.1 Default Encoding Parameters
1626                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1627                  */
1628                 pipe_config->limited_color_range =
1629                         bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1630         } else {
1631                 pipe_config->limited_color_range =
1632                         intel_dp->limited_color_range;
1633         }
1634
1635         pipe_config->lane_count = lane_count;
1636
1637         pipe_config->pipe_bpp = bpp;
1638         pipe_config->port_clock = common_rates[clock];
1639
1640         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1641                               &link_bw, &rate_select);
1642
1643         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1644                       link_bw, rate_select, pipe_config->lane_count,
1645                       pipe_config->port_clock, bpp);
1646         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1647                       mode_rate, link_avail);
1648
1649         intel_link_compute_m_n(bpp, lane_count,
1650                                adjusted_mode->crtc_clock,
1651                                pipe_config->port_clock,
1652                                &pipe_config->dp_m_n);
1653
1654         if (intel_connector->panel.downclock_mode != NULL &&
1655                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1656                         pipe_config->has_drrs = true;
1657                         intel_link_compute_m_n(bpp, lane_count,
1658                                 intel_connector->panel.downclock_mode->clock,
1659                                 pipe_config->port_clock,
1660                                 &pipe_config->dp_m2_n2);
1661         }
1662
1663         if ((IS_SKYLAKE(dev)  || IS_KABYLAKE(dev)) && is_edp(intel_dp))
1664                 skl_edp_set_pll_config(pipe_config);
1665         else if (IS_BROXTON(dev))
1666                 /* handled in ddi */;
1667         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1668                 hsw_dp_set_ddi_pll_sel(pipe_config);
1669         else
1670                 intel_dp_set_clock(encoder, pipe_config);
1671
1672         return true;
1673 }
1674
1675 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1676                               const struct intel_crtc_state *pipe_config)
1677 {
1678         intel_dp->link_rate = pipe_config->port_clock;
1679         intel_dp->lane_count = pipe_config->lane_count;
1680 }
1681
1682 static void intel_dp_prepare(struct intel_encoder *encoder)
1683 {
1684         struct drm_device *dev = encoder->base.dev;
1685         struct drm_i915_private *dev_priv = dev->dev_private;
1686         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1687         enum port port = dp_to_dig_port(intel_dp)->port;
1688         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1689         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1690
1691         intel_dp_set_link_params(intel_dp, crtc->config);
1692
1693         /*
1694          * There are four kinds of DP registers:
1695          *
1696          *      IBX PCH
1697          *      SNB CPU
1698          *      IVB CPU
1699          *      CPT PCH
1700          *
1701          * IBX PCH and CPU are the same for almost everything,
1702          * except that the CPU DP PLL is configured in this
1703          * register
1704          *
1705          * CPT PCH is quite different, having many bits moved
1706          * to the TRANS_DP_CTL register instead. That
1707          * configuration happens (oddly) in ironlake_pch_enable
1708          */
1709
1710         /* Preserve the BIOS-computed detected bit. This is
1711          * supposed to be read-only.
1712          */
1713         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1714
1715         /* Handle DP bits in common between all three register formats */
1716         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1717         intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
1718
1719         /* Split out the IBX/CPU vs CPT settings */
1720
1721         if (IS_GEN7(dev) && port == PORT_A) {
1722                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1723                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1724                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1725                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1726                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1727
1728                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1729                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1730
1731                 intel_dp->DP |= crtc->pipe << 29;
1732         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1733                 u32 trans_dp;
1734
1735                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1736
1737                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1738                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1739                         trans_dp |= TRANS_DP_ENH_FRAMING;
1740                 else
1741                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1742                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1743         } else {
1744                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1745                     !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
1746                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1747
1748                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1749                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1750                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1751                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1752                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1753
1754                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1755                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1756
1757                 if (IS_CHERRYVIEW(dev))
1758                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1759                 else if (crtc->pipe == PIPE_B)
1760                         intel_dp->DP |= DP_PIPEB_SELECT;
1761         }
1762 }
1763
1764 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1765 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1766
1767 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1768 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1769
1770 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1771 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1772
1773 static void wait_panel_status(struct intel_dp *intel_dp,
1774                                        u32 mask,
1775                                        u32 value)
1776 {
1777         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1778         struct drm_i915_private *dev_priv = dev->dev_private;
1779         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1780
1781         lockdep_assert_held(&dev_priv->pps_mutex);
1782
1783         pp_stat_reg = _pp_stat_reg(intel_dp);
1784         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1785
1786         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1787                         mask, value,
1788                         I915_READ(pp_stat_reg),
1789                         I915_READ(pp_ctrl_reg));
1790
1791         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1792                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1793                                 I915_READ(pp_stat_reg),
1794                                 I915_READ(pp_ctrl_reg));
1795         }
1796
1797         DRM_DEBUG_KMS("Wait complete\n");
1798 }
1799
1800 static void wait_panel_on(struct intel_dp *intel_dp)
1801 {
1802         DRM_DEBUG_KMS("Wait for panel power on\n");
1803         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1804 }
1805
1806 static void wait_panel_off(struct intel_dp *intel_dp)
1807 {
1808         DRM_DEBUG_KMS("Wait for panel power off time\n");
1809         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1810 }
1811
1812 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1813 {
1814         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1815
1816         /* When we disable the VDD override bit last we have to do the manual
1817          * wait. */
1818         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1819                                        intel_dp->panel_power_cycle_delay);
1820
1821         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1822 }
1823
1824 static void wait_backlight_on(struct intel_dp *intel_dp)
1825 {
1826         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1827                                        intel_dp->backlight_on_delay);
1828 }
1829
1830 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1831 {
1832         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1833                                        intel_dp->backlight_off_delay);
1834 }
1835
1836 /* Read the current pp_control value, unlocking the register if it
1837  * is locked
1838  */
1839
1840 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1841 {
1842         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1843         struct drm_i915_private *dev_priv = dev->dev_private;
1844         u32 control;
1845
1846         lockdep_assert_held(&dev_priv->pps_mutex);
1847
1848         control = I915_READ(_pp_ctrl_reg(intel_dp));
1849         if (!IS_BROXTON(dev)) {
1850                 control &= ~PANEL_UNLOCK_MASK;
1851                 control |= PANEL_UNLOCK_REGS;
1852         }
1853         return control;
1854 }
1855
1856 /*
1857  * Must be paired with edp_panel_vdd_off().
1858  * Must hold pps_mutex around the whole on/off sequence.
1859  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1860  */
1861 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1862 {
1863         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1864         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1865         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1866         struct drm_i915_private *dev_priv = dev->dev_private;
1867         enum intel_display_power_domain power_domain;
1868         u32 pp;
1869         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1870         bool need_to_disable = !intel_dp->want_panel_vdd;
1871
1872         lockdep_assert_held(&dev_priv->pps_mutex);
1873
1874         if (!is_edp(intel_dp))
1875                 return false;
1876
1877         cancel_delayed_work(&intel_dp->panel_vdd_work);
1878         intel_dp->want_panel_vdd = true;
1879
1880         if (edp_have_panel_vdd(intel_dp))
1881                 return need_to_disable;
1882
1883         power_domain = intel_display_port_aux_power_domain(intel_encoder);
1884         intel_display_power_get(dev_priv, power_domain);
1885
1886         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1887                       port_name(intel_dig_port->port));
1888
1889         if (!edp_have_panel_power(intel_dp))
1890                 wait_panel_power_cycle(intel_dp);
1891
1892         pp = ironlake_get_pp_control(intel_dp);
1893         pp |= EDP_FORCE_VDD;
1894
1895         pp_stat_reg = _pp_stat_reg(intel_dp);
1896         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1897
1898         I915_WRITE(pp_ctrl_reg, pp);
1899         POSTING_READ(pp_ctrl_reg);
1900         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1901                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1902         /*
1903          * If the panel wasn't on, delay before accessing aux channel
1904          */
1905         if (!edp_have_panel_power(intel_dp)) {
1906                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1907                               port_name(intel_dig_port->port));
1908                 msleep(intel_dp->panel_power_up_delay);
1909         }
1910
1911         return need_to_disable;
1912 }
1913
1914 /*
1915  * Must be paired with intel_edp_panel_vdd_off() or
1916  * intel_edp_panel_off().
1917  * Nested calls to these functions are not allowed since
1918  * we drop the lock. Caller must use some higher level
1919  * locking to prevent nested calls from other threads.
1920  */
1921 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1922 {
1923         bool vdd;
1924
1925         if (!is_edp(intel_dp))
1926                 return;
1927
1928         pps_lock(intel_dp);
1929         vdd = edp_panel_vdd_on(intel_dp);
1930         pps_unlock(intel_dp);
1931
1932         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1933              port_name(dp_to_dig_port(intel_dp)->port));
1934 }
1935
1936 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1937 {
1938         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1939         struct drm_i915_private *dev_priv = dev->dev_private;
1940         struct intel_digital_port *intel_dig_port =
1941                 dp_to_dig_port(intel_dp);
1942         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1943         enum intel_display_power_domain power_domain;
1944         u32 pp;
1945         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1946
1947         lockdep_assert_held(&dev_priv->pps_mutex);
1948
1949         WARN_ON(intel_dp->want_panel_vdd);
1950
1951         if (!edp_have_panel_vdd(intel_dp))
1952                 return;
1953
1954         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1955                       port_name(intel_dig_port->port));
1956
1957         pp = ironlake_get_pp_control(intel_dp);
1958         pp &= ~EDP_FORCE_VDD;
1959
1960         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1961         pp_stat_reg = _pp_stat_reg(intel_dp);
1962
1963         I915_WRITE(pp_ctrl_reg, pp);
1964         POSTING_READ(pp_ctrl_reg);
1965
1966         /* Make sure sequencer is idle before allowing subsequent activity */
1967         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1968         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1969
1970         if ((pp & POWER_TARGET_ON) == 0)
1971                 intel_dp->last_power_cycle = jiffies;
1972
1973         power_domain = intel_display_port_aux_power_domain(intel_encoder);
1974         intel_display_power_put(dev_priv, power_domain);
1975 }
1976
1977 static void edp_panel_vdd_work(struct work_struct *__work)
1978 {
1979         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1980                                                  struct intel_dp, panel_vdd_work);
1981
1982         pps_lock(intel_dp);
1983         if (!intel_dp->want_panel_vdd)
1984                 edp_panel_vdd_off_sync(intel_dp);
1985         pps_unlock(intel_dp);
1986 }
1987
1988 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1989 {
1990         unsigned long delay;
1991
1992         /*
1993          * Queue the timer to fire a long time from now (relative to the power
1994          * down delay) to keep the panel power up across a sequence of
1995          * operations.
1996          */
1997         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1998         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1999 }
2000
2001 /*
2002  * Must be paired with edp_panel_vdd_on().
2003  * Must hold pps_mutex around the whole on/off sequence.
2004  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2005  */
2006 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2007 {
2008         struct drm_i915_private *dev_priv =
2009                 intel_dp_to_dev(intel_dp)->dev_private;
2010
2011         lockdep_assert_held(&dev_priv->pps_mutex);
2012
2013         if (!is_edp(intel_dp))
2014                 return;
2015
2016         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2017              port_name(dp_to_dig_port(intel_dp)->port));
2018
2019         intel_dp->want_panel_vdd = false;
2020
2021         if (sync)
2022                 edp_panel_vdd_off_sync(intel_dp);
2023         else
2024                 edp_panel_vdd_schedule_off(intel_dp);
2025 }
2026
2027 static void edp_panel_on(struct intel_dp *intel_dp)
2028 {
2029         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2030         struct drm_i915_private *dev_priv = dev->dev_private;
2031         u32 pp;
2032         i915_reg_t pp_ctrl_reg;
2033
2034         lockdep_assert_held(&dev_priv->pps_mutex);
2035
2036         if (!is_edp(intel_dp))
2037                 return;
2038
2039         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2040                       port_name(dp_to_dig_port(intel_dp)->port));
2041
2042         if (WARN(edp_have_panel_power(intel_dp),
2043                  "eDP port %c panel power already on\n",
2044                  port_name(dp_to_dig_port(intel_dp)->port)))
2045                 return;
2046
2047         wait_panel_power_cycle(intel_dp);
2048
2049         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2050         pp = ironlake_get_pp_control(intel_dp);
2051         if (IS_GEN5(dev)) {
2052                 /* ILK workaround: disable reset around power sequence */
2053                 pp &= ~PANEL_POWER_RESET;
2054                 I915_WRITE(pp_ctrl_reg, pp);
2055                 POSTING_READ(pp_ctrl_reg);
2056         }
2057
2058         pp |= POWER_TARGET_ON;
2059         if (!IS_GEN5(dev))
2060                 pp |= PANEL_POWER_RESET;
2061
2062         I915_WRITE(pp_ctrl_reg, pp);
2063         POSTING_READ(pp_ctrl_reg);
2064
2065         wait_panel_on(intel_dp);
2066         intel_dp->last_power_on = jiffies;
2067
2068         if (IS_GEN5(dev)) {
2069                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2070                 I915_WRITE(pp_ctrl_reg, pp);
2071                 POSTING_READ(pp_ctrl_reg);
2072         }
2073 }
2074
2075 void intel_edp_panel_on(struct intel_dp *intel_dp)
2076 {
2077         if (!is_edp(intel_dp))
2078                 return;
2079
2080         pps_lock(intel_dp);
2081         edp_panel_on(intel_dp);
2082         pps_unlock(intel_dp);
2083 }
2084
2085
2086 static void edp_panel_off(struct intel_dp *intel_dp)
2087 {
2088         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2089         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2090         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2091         struct drm_i915_private *dev_priv = dev->dev_private;
2092         enum intel_display_power_domain power_domain;
2093         u32 pp;
2094         i915_reg_t pp_ctrl_reg;
2095
2096         lockdep_assert_held(&dev_priv->pps_mutex);
2097
2098         if (!is_edp(intel_dp))
2099                 return;
2100
2101         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2102                       port_name(dp_to_dig_port(intel_dp)->port));
2103
2104         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2105              port_name(dp_to_dig_port(intel_dp)->port));
2106
2107         pp = ironlake_get_pp_control(intel_dp);
2108         /* We need to switch off panel power _and_ force vdd, for otherwise some
2109          * panels get very unhappy and cease to work. */
2110         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2111                 EDP_BLC_ENABLE);
2112
2113         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2114
2115         intel_dp->want_panel_vdd = false;
2116
2117         I915_WRITE(pp_ctrl_reg, pp);
2118         POSTING_READ(pp_ctrl_reg);
2119
2120         intel_dp->last_power_cycle = jiffies;
2121         wait_panel_off(intel_dp);
2122
2123         /* We got a reference when we enabled the VDD. */
2124         power_domain = intel_display_port_aux_power_domain(intel_encoder);
2125         intel_display_power_put(dev_priv, power_domain);
2126 }
2127
2128 void intel_edp_panel_off(struct intel_dp *intel_dp)
2129 {
2130         if (!is_edp(intel_dp))
2131                 return;
2132
2133         pps_lock(intel_dp);
2134         edp_panel_off(intel_dp);
2135         pps_unlock(intel_dp);
2136 }
2137
2138 /* Enable backlight in the panel power control. */
2139 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2140 {
2141         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2142         struct drm_device *dev = intel_dig_port->base.base.dev;
2143         struct drm_i915_private *dev_priv = dev->dev_private;
2144         u32 pp;
2145         i915_reg_t pp_ctrl_reg;
2146
2147         /*
2148          * If we enable the backlight right away following a panel power
2149          * on, we may see slight flicker as the panel syncs with the eDP
2150          * link.  So delay a bit to make sure the image is solid before
2151          * allowing it to appear.
2152          */
2153         wait_backlight_on(intel_dp);
2154
2155         pps_lock(intel_dp);
2156
2157         pp = ironlake_get_pp_control(intel_dp);
2158         pp |= EDP_BLC_ENABLE;
2159
2160         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2161
2162         I915_WRITE(pp_ctrl_reg, pp);
2163         POSTING_READ(pp_ctrl_reg);
2164
2165         pps_unlock(intel_dp);
2166 }
2167
2168 /* Enable backlight PWM and backlight PP control. */
2169 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2170 {
2171         if (!is_edp(intel_dp))
2172                 return;
2173
2174         DRM_DEBUG_KMS("\n");
2175
2176         intel_panel_enable_backlight(intel_dp->attached_connector);
2177         _intel_edp_backlight_on(intel_dp);
2178 }
2179
2180 /* Disable backlight in the panel power control. */
2181 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2182 {
2183         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2184         struct drm_i915_private *dev_priv = dev->dev_private;
2185         u32 pp;
2186         i915_reg_t pp_ctrl_reg;
2187
2188         if (!is_edp(intel_dp))
2189                 return;
2190
2191         pps_lock(intel_dp);
2192
2193         pp = ironlake_get_pp_control(intel_dp);
2194         pp &= ~EDP_BLC_ENABLE;
2195
2196         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2197
2198         I915_WRITE(pp_ctrl_reg, pp);
2199         POSTING_READ(pp_ctrl_reg);
2200
2201         pps_unlock(intel_dp);
2202
2203         intel_dp->last_backlight_off = jiffies;
2204         edp_wait_backlight_off(intel_dp);
2205 }
2206
2207 /* Disable backlight PP control and backlight PWM. */
2208 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2209 {
2210         if (!is_edp(intel_dp))
2211                 return;
2212
2213         DRM_DEBUG_KMS("\n");
2214
2215         _intel_edp_backlight_off(intel_dp);
2216         intel_panel_disable_backlight(intel_dp->attached_connector);
2217 }
2218
2219 /*
2220  * Hook for controlling the panel power control backlight through the bl_power
2221  * sysfs attribute. Take care to handle multiple calls.
2222  */
2223 static void intel_edp_backlight_power(struct intel_connector *connector,
2224                                       bool enable)
2225 {
2226         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2227         bool is_enabled;
2228
2229         pps_lock(intel_dp);
2230         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2231         pps_unlock(intel_dp);
2232
2233         if (is_enabled == enable)
2234                 return;
2235
2236         DRM_DEBUG_KMS("panel power control backlight %s\n",
2237                       enable ? "enable" : "disable");
2238
2239         if (enable)
2240                 _intel_edp_backlight_on(intel_dp);
2241         else
2242                 _intel_edp_backlight_off(intel_dp);
2243 }
2244
2245 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2246 {
2247         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2248         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2249         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2250
2251         I915_STATE_WARN(cur_state != state,
2252                         "DP port %c state assertion failure (expected %s, current %s)\n",
2253                         port_name(dig_port->port),
2254                         onoff(state), onoff(cur_state));
2255 }
2256 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2257
2258 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2259 {
2260         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2261
2262         I915_STATE_WARN(cur_state != state,
2263                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2264                         onoff(state), onoff(cur_state));
2265 }
2266 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2267 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2268
2269 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2270 {
2271         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2272         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2273         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2274
2275         assert_pipe_disabled(dev_priv, crtc->pipe);
2276         assert_dp_port_disabled(intel_dp);
2277         assert_edp_pll_disabled(dev_priv);
2278
2279         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2280                       crtc->config->port_clock);
2281
2282         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2283
2284         if (crtc->config->port_clock == 162000)
2285                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2286         else
2287                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2288
2289         I915_WRITE(DP_A, intel_dp->DP);
2290         POSTING_READ(DP_A);
2291         udelay(500);
2292
2293         intel_dp->DP |= DP_PLL_ENABLE;
2294
2295         I915_WRITE(DP_A, intel_dp->DP);
2296         POSTING_READ(DP_A);
2297         udelay(200);
2298 }
2299
2300 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2301 {
2302         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2303         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2304         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2305
2306         assert_pipe_disabled(dev_priv, crtc->pipe);
2307         assert_dp_port_disabled(intel_dp);
2308         assert_edp_pll_enabled(dev_priv);
2309
2310         DRM_DEBUG_KMS("disabling eDP PLL\n");
2311
2312         intel_dp->DP &= ~DP_PLL_ENABLE;
2313
2314         I915_WRITE(DP_A, intel_dp->DP);
2315         POSTING_READ(DP_A);
2316         udelay(200);
2317 }
2318
2319 /* If the sink supports it, try to set the power state appropriately */
2320 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2321 {
2322         int ret, i;
2323
2324         /* Should have a valid DPCD by this point */
2325         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2326                 return;
2327
2328         if (mode != DRM_MODE_DPMS_ON) {
2329                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2330                                          DP_SET_POWER_D3);
2331         } else {
2332                 /*
2333                  * When turning on, we need to retry for 1ms to give the sink
2334                  * time to wake up.
2335                  */
2336                 for (i = 0; i < 3; i++) {
2337                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2338                                                  DP_SET_POWER_D0);
2339                         if (ret == 1)
2340                                 break;
2341                         msleep(1);
2342                 }
2343         }
2344
2345         if (ret != 1)
2346                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2347                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2348 }
2349
2350 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2351                                   enum pipe *pipe)
2352 {
2353         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2354         enum port port = dp_to_dig_port(intel_dp)->port;
2355         struct drm_device *dev = encoder->base.dev;
2356         struct drm_i915_private *dev_priv = dev->dev_private;
2357         enum intel_display_power_domain power_domain;
2358         u32 tmp;
2359
2360         power_domain = intel_display_port_power_domain(encoder);
2361         if (!intel_display_power_is_enabled(dev_priv, power_domain))
2362                 return false;
2363
2364         tmp = I915_READ(intel_dp->output_reg);
2365
2366         if (!(tmp & DP_PORT_EN))
2367                 return false;
2368
2369         if (IS_GEN7(dev) && port == PORT_A) {
2370                 *pipe = PORT_TO_PIPE_CPT(tmp);
2371         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2372                 enum pipe p;
2373
2374                 for_each_pipe(dev_priv, p) {
2375                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2376                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2377                                 *pipe = p;
2378                                 return true;
2379                         }
2380                 }
2381
2382                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2383                               i915_mmio_reg_offset(intel_dp->output_reg));
2384         } else if (IS_CHERRYVIEW(dev)) {
2385                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2386         } else {
2387                 *pipe = PORT_TO_PIPE(tmp);
2388         }
2389
2390         return true;
2391 }
2392
2393 static void intel_dp_get_config(struct intel_encoder *encoder,
2394                                 struct intel_crtc_state *pipe_config)
2395 {
2396         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2397         u32 tmp, flags = 0;
2398         struct drm_device *dev = encoder->base.dev;
2399         struct drm_i915_private *dev_priv = dev->dev_private;
2400         enum port port = dp_to_dig_port(intel_dp)->port;
2401         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2402         int dotclock;
2403
2404         tmp = I915_READ(intel_dp->output_reg);
2405
2406         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2407
2408         if (HAS_PCH_CPT(dev) && port != PORT_A) {
2409                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2410
2411                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2412                         flags |= DRM_MODE_FLAG_PHSYNC;
2413                 else
2414                         flags |= DRM_MODE_FLAG_NHSYNC;
2415
2416                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2417                         flags |= DRM_MODE_FLAG_PVSYNC;
2418                 else
2419                         flags |= DRM_MODE_FLAG_NVSYNC;
2420         } else {
2421                 if (tmp & DP_SYNC_HS_HIGH)
2422                         flags |= DRM_MODE_FLAG_PHSYNC;
2423                 else
2424                         flags |= DRM_MODE_FLAG_NHSYNC;
2425
2426                 if (tmp & DP_SYNC_VS_HIGH)
2427                         flags |= DRM_MODE_FLAG_PVSYNC;
2428                 else
2429                         flags |= DRM_MODE_FLAG_NVSYNC;
2430         }
2431
2432         pipe_config->base.adjusted_mode.flags |= flags;
2433
2434         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2435             !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
2436                 pipe_config->limited_color_range = true;
2437
2438         pipe_config->has_dp_encoder = true;
2439
2440         pipe_config->lane_count =
2441                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2442
2443         intel_dp_get_m_n(crtc, pipe_config);
2444
2445         if (port == PORT_A) {
2446                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2447                         pipe_config->port_clock = 162000;
2448                 else
2449                         pipe_config->port_clock = 270000;
2450         }
2451
2452         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2453                                             &pipe_config->dp_m_n);
2454
2455         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2456                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2457
2458         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2459
2460         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2461             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2462                 /*
2463                  * This is a big fat ugly hack.
2464                  *
2465                  * Some machines in UEFI boot mode provide us a VBT that has 18
2466                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2467                  * unknown we fail to light up. Yet the same BIOS boots up with
2468                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2469                  * max, not what it tells us to use.
2470                  *
2471                  * Note: This will still be broken if the eDP panel is not lit
2472                  * up by the BIOS, and thus we can't get the mode at module
2473                  * load.
2474                  */
2475                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2476                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2477                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2478         }
2479 }
2480
2481 static void intel_disable_dp(struct intel_encoder *encoder)
2482 {
2483         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2484         struct drm_device *dev = encoder->base.dev;
2485         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2486
2487         if (crtc->config->has_audio)
2488                 intel_audio_codec_disable(encoder);
2489
2490         if (HAS_PSR(dev) && !HAS_DDI(dev))
2491                 intel_psr_disable(intel_dp);
2492
2493         /* Make sure the panel is off before trying to change the mode. But also
2494          * ensure that we have vdd while we switch off the panel. */
2495         intel_edp_panel_vdd_on(intel_dp);
2496         intel_edp_backlight_off(intel_dp);
2497         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2498         intel_edp_panel_off(intel_dp);
2499
2500         /* disable the port before the pipe on g4x */
2501         if (INTEL_INFO(dev)->gen < 5)
2502                 intel_dp_link_down(intel_dp);
2503 }
2504
2505 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2506 {
2507         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2508         enum port port = dp_to_dig_port(intel_dp)->port;
2509
2510         intel_dp_link_down(intel_dp);
2511
2512         /* Only ilk+ has port A */
2513         if (port == PORT_A)
2514                 ironlake_edp_pll_off(intel_dp);
2515 }
2516
2517 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2518 {
2519         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2520
2521         intel_dp_link_down(intel_dp);
2522 }
2523
2524 static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
2525                                      bool reset)
2526 {
2527         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2528         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
2529         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2530         enum pipe pipe = crtc->pipe;
2531         uint32_t val;
2532
2533         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2534         if (reset)
2535                 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2536         else
2537                 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2538         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2539
2540         if (crtc->config->lane_count > 2) {
2541                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2542                 if (reset)
2543                         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2544                 else
2545                         val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2546                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2547         }
2548
2549         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2550         val |= CHV_PCS_REQ_SOFTRESET_EN;
2551         if (reset)
2552                 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2553         else
2554                 val |= DPIO_PCS_CLK_SOFT_RESET;
2555         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2556
2557         if (crtc->config->lane_count > 2) {
2558                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2559                 val |= CHV_PCS_REQ_SOFTRESET_EN;
2560                 if (reset)
2561                         val &= ~DPIO_PCS_CLK_SOFT_RESET;
2562                 else
2563                         val |= DPIO_PCS_CLK_SOFT_RESET;
2564                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2565         }
2566 }
2567
2568 static void chv_post_disable_dp(struct intel_encoder *encoder)
2569 {
2570         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2571         struct drm_device *dev = encoder->base.dev;
2572         struct drm_i915_private *dev_priv = dev->dev_private;
2573
2574         intel_dp_link_down(intel_dp);
2575
2576         mutex_lock(&dev_priv->sb_lock);
2577
2578         /* Assert data lane reset */
2579         chv_data_lane_soft_reset(encoder, true);
2580
2581         mutex_unlock(&dev_priv->sb_lock);
2582 }
2583
2584 static void
2585 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2586                          uint32_t *DP,
2587                          uint8_t dp_train_pat)
2588 {
2589         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2590         struct drm_device *dev = intel_dig_port->base.base.dev;
2591         struct drm_i915_private *dev_priv = dev->dev_private;
2592         enum port port = intel_dig_port->port;
2593
2594         if (HAS_DDI(dev)) {
2595                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2596
2597                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2598                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2599                 else
2600                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2601
2602                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2603                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2604                 case DP_TRAINING_PATTERN_DISABLE:
2605                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2606
2607                         break;
2608                 case DP_TRAINING_PATTERN_1:
2609                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2610                         break;
2611                 case DP_TRAINING_PATTERN_2:
2612                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2613                         break;
2614                 case DP_TRAINING_PATTERN_3:
2615                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2616                         break;
2617                 }
2618                 I915_WRITE(DP_TP_CTL(port), temp);
2619
2620         } else if ((IS_GEN7(dev) && port == PORT_A) ||
2621                    (HAS_PCH_CPT(dev) && port != PORT_A)) {
2622                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2623
2624                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2625                 case DP_TRAINING_PATTERN_DISABLE:
2626                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2627                         break;
2628                 case DP_TRAINING_PATTERN_1:
2629                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2630                         break;
2631                 case DP_TRAINING_PATTERN_2:
2632                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2633                         break;
2634                 case DP_TRAINING_PATTERN_3:
2635                         DRM_ERROR("DP training pattern 3 not supported\n");
2636                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2637                         break;
2638                 }
2639
2640         } else {
2641                 if (IS_CHERRYVIEW(dev))
2642                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2643                 else
2644                         *DP &= ~DP_LINK_TRAIN_MASK;
2645
2646                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2647                 case DP_TRAINING_PATTERN_DISABLE:
2648                         *DP |= DP_LINK_TRAIN_OFF;
2649                         break;
2650                 case DP_TRAINING_PATTERN_1:
2651                         *DP |= DP_LINK_TRAIN_PAT_1;
2652                         break;
2653                 case DP_TRAINING_PATTERN_2:
2654                         *DP |= DP_LINK_TRAIN_PAT_2;
2655                         break;
2656                 case DP_TRAINING_PATTERN_3:
2657                         if (IS_CHERRYVIEW(dev)) {
2658                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2659                         } else {
2660                                 DRM_ERROR("DP training pattern 3 not supported\n");
2661                                 *DP |= DP_LINK_TRAIN_PAT_2;
2662                         }
2663                         break;
2664                 }
2665         }
2666 }
2667
2668 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2669 {
2670         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2671         struct drm_i915_private *dev_priv = dev->dev_private;
2672         struct intel_crtc *crtc =
2673                 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
2674
2675         /* enable with pattern 1 (as per spec) */
2676         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2677                                  DP_TRAINING_PATTERN_1);
2678
2679         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2680         POSTING_READ(intel_dp->output_reg);
2681
2682         /*
2683          * Magic for VLV/CHV. We _must_ first set up the register
2684          * without actually enabling the port, and then do another
2685          * write to enable the port. Otherwise link training will
2686          * fail when the power sequencer is freshly used for this port.
2687          */
2688         intel_dp->DP |= DP_PORT_EN;
2689         if (crtc->config->has_audio)
2690                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2691
2692         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2693         POSTING_READ(intel_dp->output_reg);
2694 }
2695
2696 static void intel_enable_dp(struct intel_encoder *encoder)
2697 {
2698         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2699         struct drm_device *dev = encoder->base.dev;
2700         struct drm_i915_private *dev_priv = dev->dev_private;
2701         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2702         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2703         enum port port = dp_to_dig_port(intel_dp)->port;
2704         enum pipe pipe = crtc->pipe;
2705
2706         if (WARN_ON(dp_reg & DP_PORT_EN))
2707                 return;
2708
2709         pps_lock(intel_dp);
2710
2711         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2712                 vlv_init_panel_power_sequencer(intel_dp);
2713
2714         /*
2715          * We get an occasional spurious underrun between the port
2716          * enable and vdd enable, when enabling port A eDP.
2717          *
2718          * FIXME: Not sure if this applies to (PCH) port D eDP as well
2719          */
2720         if (port == PORT_A)
2721                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2722
2723         intel_dp_enable_port(intel_dp);
2724
2725         if (port == PORT_A && IS_GEN5(dev_priv)) {
2726                 /*
2727                  * Underrun reporting for the other pipe was disabled in
2728                  * g4x_pre_enable_dp(). The eDP PLL and port have now been
2729                  * enabled, so it's now safe to re-enable underrun reporting.
2730                  */
2731                 intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
2732                 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
2733                 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
2734         }
2735
2736         edp_panel_vdd_on(intel_dp);
2737         edp_panel_on(intel_dp);
2738         edp_panel_vdd_off(intel_dp, true);
2739
2740         if (port == PORT_A)
2741                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2742
2743         pps_unlock(intel_dp);
2744
2745         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2746                 unsigned int lane_mask = 0x0;
2747
2748                 if (IS_CHERRYVIEW(dev))
2749                         lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2750
2751                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2752                                     lane_mask);
2753         }
2754
2755         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2756         intel_dp_start_link_train(intel_dp);
2757         intel_dp_stop_link_train(intel_dp);
2758
2759         if (crtc->config->has_audio) {
2760                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2761                                  pipe_name(pipe));
2762                 intel_audio_codec_enable(encoder);
2763         }
2764 }
2765
2766 static void g4x_enable_dp(struct intel_encoder *encoder)
2767 {
2768         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2769
2770         intel_enable_dp(encoder);
2771         intel_edp_backlight_on(intel_dp);
2772 }
2773
2774 static void vlv_enable_dp(struct intel_encoder *encoder)
2775 {
2776         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2777
2778         intel_edp_backlight_on(intel_dp);
2779         intel_psr_enable(intel_dp);
2780 }
2781
2782 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2783 {
2784         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2785         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2786         enum port port = dp_to_dig_port(intel_dp)->port;
2787         enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
2788
2789         intel_dp_prepare(encoder);
2790
2791         if (port == PORT_A && IS_GEN5(dev_priv)) {
2792                 /*
2793                  * We get FIFO underruns on the other pipe when
2794                  * enabling the CPU eDP PLL, and when enabling CPU
2795                  * eDP port. We could potentially avoid the PLL
2796                  * underrun with a vblank wait just prior to enabling
2797                  * the PLL, but that doesn't appear to help the port
2798                  * enable case. Just sweep it all under the rug.
2799                  */
2800                 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
2801                 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
2802         }
2803
2804         /* Only ilk+ has port A */
2805         if (port == PORT_A)
2806                 ironlake_edp_pll_on(intel_dp);
2807 }
2808
2809 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2810 {
2811         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2812         struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2813         enum pipe pipe = intel_dp->pps_pipe;
2814         i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2815
2816         edp_panel_vdd_off_sync(intel_dp);
2817
2818         /*
2819          * VLV seems to get confused when multiple power seqeuencers
2820          * have the same port selected (even if only one has power/vdd
2821          * enabled). The failure manifests as vlv_wait_port_ready() failing
2822          * CHV on the other hand doesn't seem to mind having the same port
2823          * selected in multiple power seqeuencers, but let's clear the
2824          * port select always when logically disconnecting a power sequencer
2825          * from a port.
2826          */
2827         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2828                       pipe_name(pipe), port_name(intel_dig_port->port));
2829         I915_WRITE(pp_on_reg, 0);
2830         POSTING_READ(pp_on_reg);
2831
2832         intel_dp->pps_pipe = INVALID_PIPE;
2833 }
2834
2835 static void vlv_steal_power_sequencer(struct drm_device *dev,
2836                                       enum pipe pipe)
2837 {
2838         struct drm_i915_private *dev_priv = dev->dev_private;
2839         struct intel_encoder *encoder;
2840
2841         lockdep_assert_held(&dev_priv->pps_mutex);
2842
2843         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2844                 return;
2845
2846         for_each_intel_encoder(dev, encoder) {
2847                 struct intel_dp *intel_dp;
2848                 enum port port;
2849
2850                 if (encoder->type != INTEL_OUTPUT_EDP)
2851                         continue;
2852
2853                 intel_dp = enc_to_intel_dp(&encoder->base);
2854                 port = dp_to_dig_port(intel_dp)->port;
2855
2856                 if (intel_dp->pps_pipe != pipe)
2857                         continue;
2858
2859                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2860                               pipe_name(pipe), port_name(port));
2861
2862                 WARN(encoder->base.crtc,
2863                      "stealing pipe %c power sequencer from active eDP port %c\n",
2864                      pipe_name(pipe), port_name(port));
2865
2866                 /* make sure vdd is off before we steal it */
2867                 vlv_detach_power_sequencer(intel_dp);
2868         }
2869 }
2870
2871 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2872 {
2873         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2874         struct intel_encoder *encoder = &intel_dig_port->base;
2875         struct drm_device *dev = encoder->base.dev;
2876         struct drm_i915_private *dev_priv = dev->dev_private;
2877         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2878
2879         lockdep_assert_held(&dev_priv->pps_mutex);
2880
2881         if (!is_edp(intel_dp))
2882                 return;
2883
2884         if (intel_dp->pps_pipe == crtc->pipe)
2885                 return;
2886
2887         /*
2888          * If another power sequencer was being used on this
2889          * port previously make sure to turn off vdd there while
2890          * we still have control of it.
2891          */
2892         if (intel_dp->pps_pipe != INVALID_PIPE)
2893                 vlv_detach_power_sequencer(intel_dp);
2894
2895         /*
2896          * We may be stealing the power
2897          * sequencer from another port.
2898          */
2899         vlv_steal_power_sequencer(dev, crtc->pipe);
2900
2901         /* now it's all ours */
2902         intel_dp->pps_pipe = crtc->pipe;
2903
2904         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2905                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2906
2907         /* init power sequencer on this pipe and port */
2908         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2909         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2910 }
2911
2912 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2913 {
2914         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2915         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2916         struct drm_device *dev = encoder->base.dev;
2917         struct drm_i915_private *dev_priv = dev->dev_private;
2918         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2919         enum dpio_channel port = vlv_dport_to_channel(dport);
2920         int pipe = intel_crtc->pipe;
2921         u32 val;
2922
2923         mutex_lock(&dev_priv->sb_lock);
2924
2925         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2926         val = 0;
2927         if (pipe)
2928                 val |= (1<<21);
2929         else
2930                 val &= ~(1<<21);
2931         val |= 0x001000c4;
2932         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2933         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2934         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2935
2936         mutex_unlock(&dev_priv->sb_lock);
2937
2938         intel_enable_dp(encoder);
2939 }
2940
2941 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2942 {
2943         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2944         struct drm_device *dev = encoder->base.dev;
2945         struct drm_i915_private *dev_priv = dev->dev_private;
2946         struct intel_crtc *intel_crtc =
2947                 to_intel_crtc(encoder->base.crtc);
2948         enum dpio_channel port = vlv_dport_to_channel(dport);
2949         int pipe = intel_crtc->pipe;
2950
2951         intel_dp_prepare(encoder);
2952
2953         /* Program Tx lane resets to default */
2954         mutex_lock(&dev_priv->sb_lock);
2955         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2956                          DPIO_PCS_TX_LANE2_RESET |
2957                          DPIO_PCS_TX_LANE1_RESET);
2958         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2959                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2960                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2961                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2962                                  DPIO_PCS_CLK_SOFT_RESET);
2963
2964         /* Fix up inter-pair skew failure */
2965         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2966         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2967         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2968         mutex_unlock(&dev_priv->sb_lock);
2969 }
2970
2971 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2972 {
2973         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2974         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2975         struct drm_device *dev = encoder->base.dev;
2976         struct drm_i915_private *dev_priv = dev->dev_private;
2977         struct intel_crtc *intel_crtc =
2978                 to_intel_crtc(encoder->base.crtc);
2979         enum dpio_channel ch = vlv_dport_to_channel(dport);
2980         int pipe = intel_crtc->pipe;
2981         int data, i, stagger;
2982         u32 val;
2983
2984         mutex_lock(&dev_priv->sb_lock);
2985
2986         /* allow hardware to manage TX FIFO reset source */
2987         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2988         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2989         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2990
2991         if (intel_crtc->config->lane_count > 2) {
2992                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2993                 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2994                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2995         }
2996
2997         /* Program Tx lane latency optimal setting*/
2998         for (i = 0; i < intel_crtc->config->lane_count; i++) {
2999                 /* Set the upar bit */
3000                 if (intel_crtc->config->lane_count == 1)
3001                         data = 0x0;
3002                 else
3003                         data = (i == 1) ? 0x0 : 0x1;
3004                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
3005                                 data << DPIO_UPAR_SHIFT);
3006         }
3007
3008         /* Data lane stagger programming */
3009         if (intel_crtc->config->port_clock > 270000)
3010                 stagger = 0x18;
3011         else if (intel_crtc->config->port_clock > 135000)
3012                 stagger = 0xd;
3013         else if (intel_crtc->config->port_clock > 67500)
3014                 stagger = 0x7;
3015         else if (intel_crtc->config->port_clock > 33750)
3016                 stagger = 0x4;
3017         else
3018                 stagger = 0x2;
3019
3020         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
3021         val |= DPIO_TX2_STAGGER_MASK(0x1f);
3022         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
3023
3024         if (intel_crtc->config->lane_count > 2) {
3025                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
3026                 val |= DPIO_TX2_STAGGER_MASK(0x1f);
3027                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
3028         }
3029
3030         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
3031                        DPIO_LANESTAGGER_STRAP(stagger) |
3032                        DPIO_LANESTAGGER_STRAP_OVRD |
3033                        DPIO_TX1_STAGGER_MASK(0x1f) |
3034                        DPIO_TX1_STAGGER_MULT(6) |
3035                        DPIO_TX2_STAGGER_MULT(0));
3036
3037         if (intel_crtc->config->lane_count > 2) {
3038                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
3039                                DPIO_LANESTAGGER_STRAP(stagger) |
3040                                DPIO_LANESTAGGER_STRAP_OVRD |
3041                                DPIO_TX1_STAGGER_MASK(0x1f) |
3042                                DPIO_TX1_STAGGER_MULT(7) |
3043                                DPIO_TX2_STAGGER_MULT(5));
3044         }
3045
3046         /* Deassert data lane reset */
3047         chv_data_lane_soft_reset(encoder, false);
3048
3049         mutex_unlock(&dev_priv->sb_lock);
3050
3051         intel_enable_dp(encoder);
3052
3053         /* Second common lane will stay alive on its own now */
3054         if (dport->release_cl2_override) {
3055                 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
3056                 dport->release_cl2_override = false;
3057         }
3058 }
3059
3060 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
3061 {
3062         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
3063         struct drm_device *dev = encoder->base.dev;
3064         struct drm_i915_private *dev_priv = dev->dev_private;
3065         struct intel_crtc *intel_crtc =
3066                 to_intel_crtc(encoder->base.crtc);
3067         enum dpio_channel ch = vlv_dport_to_channel(dport);
3068         enum pipe pipe = intel_crtc->pipe;
3069         unsigned int lane_mask =
3070                 intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
3071         u32 val;
3072
3073         intel_dp_prepare(encoder);
3074
3075         /*
3076          * Must trick the second common lane into life.
3077          * Otherwise we can't even access the PLL.
3078          */
3079         if (ch == DPIO_CH0 && pipe == PIPE_B)
3080                 dport->release_cl2_override =
3081                         !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
3082
3083         chv_phy_powergate_lanes(encoder, true, lane_mask);
3084
3085         mutex_lock(&dev_priv->sb_lock);
3086
3087         /* Assert data lane reset */
3088         chv_data_lane_soft_reset(encoder, true);
3089
3090         /* program left/right clock distribution */
3091         if (pipe != PIPE_B) {
3092                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3093                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3094                 if (ch == DPIO_CH0)
3095                         val |= CHV_BUFLEFTENA1_FORCE;
3096                 if (ch == DPIO_CH1)
3097                         val |= CHV_BUFRIGHTENA1_FORCE;
3098                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3099         } else {
3100                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3101                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3102                 if (ch == DPIO_CH0)
3103                         val |= CHV_BUFLEFTENA2_FORCE;
3104                 if (ch == DPIO_CH1)
3105                         val |= CHV_BUFRIGHTENA2_FORCE;
3106                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3107         }
3108
3109         /* program clock channel usage */
3110         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
3111         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3112         if (pipe != PIPE_B)
3113                 val &= ~CHV_PCS_USEDCLKCHANNEL;
3114         else
3115                 val |= CHV_PCS_USEDCLKCHANNEL;
3116         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
3117
3118         if (intel_crtc->config->lane_count > 2) {
3119                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
3120                 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3121                 if (pipe != PIPE_B)
3122                         val &= ~CHV_PCS_USEDCLKCHANNEL;
3123                 else
3124                         val |= CHV_PCS_USEDCLKCHANNEL;
3125                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
3126         }
3127
3128         /*
3129          * This a a bit weird since generally CL
3130          * matches the pipe, but here we need to
3131          * pick the CL based on the port.
3132          */
3133         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
3134         if (pipe != PIPE_B)
3135                 val &= ~CHV_CMN_USEDCLKCHANNEL;
3136         else
3137                 val |= CHV_CMN_USEDCLKCHANNEL;
3138         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
3139
3140         mutex_unlock(&dev_priv->sb_lock);
3141 }
3142
3143 static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
3144 {
3145         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3146         enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
3147         u32 val;
3148
3149         mutex_lock(&dev_priv->sb_lock);
3150
3151         /* disable left/right clock distribution */
3152         if (pipe != PIPE_B) {
3153                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3154                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3155                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3156         } else {
3157                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3158                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3159                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3160         }
3161
3162         mutex_unlock(&dev_priv->sb_lock);
3163
3164         /*
3165          * Leave the power down bit cleared for at least one
3166          * lane so that chv_powergate_phy_ch() will power
3167          * on something when the channel is otherwise unused.
3168          * When the port is off and the override is removed
3169          * the lanes power down anyway, so otherwise it doesn't
3170          * really matter what the state of power down bits is
3171          * after this.
3172          */
3173         chv_phy_powergate_lanes(encoder, false, 0x0);
3174 }
3175
3176 /*
3177  * Native read with retry for link status and receiver capability reads for
3178  * cases where the sink may still be asleep.
3179  *
3180  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
3181  * supposed to retry 3 times per the spec.
3182  */
3183 static ssize_t
3184 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
3185                         void *buffer, size_t size)
3186 {
3187         ssize_t ret;
3188         int i;
3189
3190         /*
3191          * Sometime we just get the same incorrect byte repeated
3192          * over the entire buffer. Doing just one throw away read
3193          * initially seems to "solve" it.
3194          */
3195         drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
3196
3197         for (i = 0; i < 3; i++) {
3198                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
3199                 if (ret == size)
3200                         return ret;
3201                 msleep(1);
3202         }
3203
3204         return ret;
3205 }
3206
3207 /*
3208  * Fetch AUX CH registers 0x202 - 0x207 which contain
3209  * link status information
3210  */
3211 bool
3212 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3213 {
3214         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3215                                        DP_LANE0_1_STATUS,
3216                                        link_status,
3217                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3218 }
3219
3220 /* These are source-specific values. */
3221 uint8_t
3222 intel_dp_voltage_max(struct intel_dp *intel_dp)
3223 {
3224         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3225         struct drm_i915_private *dev_priv = dev->dev_private;
3226         enum port port = dp_to_dig_port(intel_dp)->port;
3227
3228         if (IS_BROXTON(dev))
3229                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3230         else if (INTEL_INFO(dev)->gen >= 9) {
3231                 if (dev_priv->edp_low_vswing && port == PORT_A)
3232                         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3233                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3234         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3235                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3236         else if (IS_GEN7(dev) && port == PORT_A)
3237                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3238         else if (HAS_PCH_CPT(dev) && port != PORT_A)
3239                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3240         else
3241                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3242 }
3243
3244 uint8_t
3245 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3246 {
3247         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3248         enum port port = dp_to_dig_port(intel_dp)->port;
3249
3250         if (INTEL_INFO(dev)->gen >= 9) {
3251                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3252                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3253                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3254                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3255                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3256                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3257                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3258                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3259                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3260                 default:
3261                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3262                 }
3263         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3264                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3265                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3266                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3267                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3268                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3269                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3270                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3271                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3272                 default:
3273                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3274                 }
3275         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
3276                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3277                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3278                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3279                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3280                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3281                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3282                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3283                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3284                 default:
3285                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3286                 }
3287         } else if (IS_GEN7(dev) && port == PORT_A) {
3288                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3289                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3290                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3291                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3292                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3293                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3294                 default:
3295                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3296                 }
3297         } else {
3298                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3299                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3300                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3301                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3302                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3303                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3304                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3305                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3306                 default:
3307                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3308                 }
3309         }
3310 }
3311
3312 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3313 {
3314         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3315         struct drm_i915_private *dev_priv = dev->dev_private;
3316         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3317         struct intel_crtc *intel_crtc =
3318                 to_intel_crtc(dport->base.base.crtc);
3319         unsigned long demph_reg_value, preemph_reg_value,
3320                 uniqtranscale_reg_value;
3321         uint8_t train_set = intel_dp->train_set[0];
3322         enum dpio_channel port = vlv_dport_to_channel(dport);
3323         int pipe = intel_crtc->pipe;
3324
3325         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3326         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3327                 preemph_reg_value = 0x0004000;
3328                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3329                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3330                         demph_reg_value = 0x2B405555;
3331                         uniqtranscale_reg_value = 0x552AB83A;
3332                         break;
3333                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3334                         demph_reg_value = 0x2B404040;
3335                         uniqtranscale_reg_value = 0x5548B83A;
3336                         break;
3337                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3338                         demph_reg_value = 0x2B245555;
3339                         uniqtranscale_reg_value = 0x5560B83A;
3340                         break;
3341                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3342                         demph_reg_value = 0x2B405555;
3343                         uniqtranscale_reg_value = 0x5598DA3A;
3344                         break;
3345                 default:
3346                         return 0;
3347                 }
3348                 break;
3349         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3350                 preemph_reg_value = 0x0002000;
3351                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3352                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3353                         demph_reg_value = 0x2B404040;
3354                         uniqtranscale_reg_value = 0x5552B83A;
3355                         break;
3356                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3357                         demph_reg_value = 0x2B404848;
3358                         uniqtranscale_reg_value = 0x5580B83A;
3359                         break;
3360                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3361                         demph_reg_value = 0x2B404040;
3362                         uniqtranscale_reg_value = 0x55ADDA3A;
3363                         break;
3364                 default:
3365                         return 0;
3366                 }
3367                 break;
3368         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3369                 preemph_reg_value = 0x0000000;
3370                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3371                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3372                         demph_reg_value = 0x2B305555;
3373                         uniqtranscale_reg_value = 0x5570B83A;
3374                         break;
3375                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3376                         demph_reg_value = 0x2B2B4040;
3377                         uniqtranscale_reg_value = 0x55ADDA3A;
3378                         break;
3379                 default:
3380                         return 0;
3381                 }
3382                 break;
3383         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3384                 preemph_reg_value = 0x0006000;
3385                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3386                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3387                         demph_reg_value = 0x1B405555;
3388                         uniqtranscale_reg_value = 0x55ADDA3A;
3389                         break;
3390                 default:
3391                         return 0;
3392                 }
3393                 break;
3394         default:
3395                 return 0;
3396         }
3397
3398         mutex_lock(&dev_priv->sb_lock);
3399         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3400         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3401         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3402                          uniqtranscale_reg_value);
3403         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3404         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3405         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3406         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
3407         mutex_unlock(&dev_priv->sb_lock);
3408
3409         return 0;
3410 }
3411
3412 static bool chv_need_uniq_trans_scale(uint8_t train_set)
3413 {
3414         return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
3415                 (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3416 }
3417
3418 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3419 {
3420         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3421         struct drm_i915_private *dev_priv = dev->dev_private;
3422         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3423         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3424         u32 deemph_reg_value, margin_reg_value, val;
3425         uint8_t train_set = intel_dp->train_set[0];
3426         enum dpio_channel ch = vlv_dport_to_channel(dport);
3427         enum pipe pipe = intel_crtc->pipe;
3428         int i;
3429
3430         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3431         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3432                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3433                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3434                         deemph_reg_value = 128;
3435                         margin_reg_value = 52;
3436                         break;
3437                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3438                         deemph_reg_value = 128;
3439                         margin_reg_value = 77;
3440                         break;
3441                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3442                         deemph_reg_value = 128;
3443                         margin_reg_value = 102;
3444                         break;
3445                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3446                         deemph_reg_value = 128;
3447                         margin_reg_value = 154;
3448                         /* FIXME extra to set for 1200 */
3449                         break;
3450                 default:
3451                         return 0;
3452                 }
3453                 break;
3454         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3455                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3456                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3457                         deemph_reg_value = 85;
3458                         margin_reg_value = 78;
3459                         break;
3460                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3461                         deemph_reg_value = 85;
3462                         margin_reg_value = 116;
3463                         break;
3464                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3465                         deemph_reg_value = 85;
3466                         margin_reg_value = 154;
3467                         break;
3468                 default:
3469                         return 0;
3470                 }
3471                 break;
3472         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3473                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3474                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3475                         deemph_reg_value = 64;
3476                         margin_reg_value = 104;
3477                         break;
3478                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3479                         deemph_reg_value = 64;
3480                         margin_reg_value = 154;
3481                         break;
3482                 default:
3483                         return 0;
3484                 }
3485                 break;
3486         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3487                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3488                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3489                         deemph_reg_value = 43;
3490                         margin_reg_value = 154;
3491                         break;
3492                 default:
3493                         return 0;
3494                 }
3495                 break;
3496         default:
3497                 return 0;
3498         }
3499
3500         mutex_lock(&dev_priv->sb_lock);
3501
3502         /* Clear calc init */
3503         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3504         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3505         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3506         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3507         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3508
3509         if (intel_crtc->config->lane_count > 2) {
3510                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3511                 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3512                 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3513                 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3514                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3515         }
3516
3517         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3518         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3519         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3520         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3521
3522         if (intel_crtc->config->lane_count > 2) {
3523                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3524                 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3525                 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3526                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3527         }
3528
3529         /* Program swing deemph */
3530         for (i = 0; i < intel_crtc->config->lane_count; i++) {
3531                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3532                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3533                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3534                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3535         }
3536
3537         /* Program swing margin */
3538         for (i = 0; i < intel_crtc->config->lane_count; i++) {
3539                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3540
3541                 val &= ~DPIO_SWING_MARGIN000_MASK;
3542                 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3543
3544                 /*
3545                  * Supposedly this value shouldn't matter when unique transition
3546                  * scale is disabled, but in fact it does matter. Let's just
3547                  * always program the same value and hope it's OK.
3548                  */
3549                 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3550                 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
3551
3552                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3553         }
3554
3555         /*
3556          * The document said it needs to set bit 27 for ch0 and bit 26
3557          * for ch1. Might be a typo in the doc.
3558          * For now, for this unique transition scale selection, set bit
3559          * 27 for ch0 and ch1.
3560          */
3561         for (i = 0; i < intel_crtc->config->lane_count; i++) {
3562                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3563                 if (chv_need_uniq_trans_scale(train_set))
3564                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3565                 else
3566                         val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3567                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3568         }
3569
3570         /* Start swing calculation */
3571         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3572         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3573         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3574
3575         if (intel_crtc->config->lane_count > 2) {
3576                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3577                 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3578                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3579         }
3580
3581         mutex_unlock(&dev_priv->sb_lock);
3582
3583         return 0;
3584 }
3585
3586 static uint32_t
3587 gen4_signal_levels(uint8_t train_set)
3588 {
3589         uint32_t        signal_levels = 0;
3590
3591         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3592         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3593         default:
3594                 signal_levels |= DP_VOLTAGE_0_4;
3595                 break;
3596         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3597                 signal_levels |= DP_VOLTAGE_0_6;
3598                 break;
3599         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3600                 signal_levels |= DP_VOLTAGE_0_8;
3601                 break;
3602         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3603                 signal_levels |= DP_VOLTAGE_1_2;
3604                 break;
3605         }
3606         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3607         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3608         default:
3609                 signal_levels |= DP_PRE_EMPHASIS_0;
3610                 break;
3611         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3612                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3613                 break;
3614         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3615                 signal_levels |= DP_PRE_EMPHASIS_6;
3616                 break;
3617         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3618                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3619                 break;
3620         }
3621         return signal_levels;
3622 }
3623
3624 /* Gen6's DP voltage swing and pre-emphasis control */
3625 static uint32_t
3626 gen6_edp_signal_levels(uint8_t train_set)
3627 {
3628         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3629                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3630         switch (signal_levels) {
3631         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3632         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3633                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3634         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3635                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3636         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3637         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3638                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3639         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3640         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3641                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3642         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3643         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3644                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3645         default:
3646                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3647                               "0x%x\n", signal_levels);
3648                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3649         }
3650 }
3651
3652 /* Gen7's DP voltage swing and pre-emphasis control */
3653 static uint32_t
3654 gen7_edp_signal_levels(uint8_t train_set)
3655 {
3656         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3657                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3658         switch (signal_levels) {
3659         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3660                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3661         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3662                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3663         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3664                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3665
3666         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3667                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3668         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3669                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3670
3671         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3672                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3673         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3674                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3675
3676         default:
3677                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3678                               "0x%x\n", signal_levels);
3679                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3680         }
3681 }
3682
3683 void
3684 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3685 {
3686         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3687         enum port port = intel_dig_port->port;
3688         struct drm_device *dev = intel_dig_port->base.base.dev;
3689         struct drm_i915_private *dev_priv = to_i915(dev);
3690         uint32_t signal_levels, mask = 0;
3691         uint8_t train_set = intel_dp->train_set[0];
3692
3693         if (HAS_DDI(dev)) {
3694                 signal_levels = ddi_signal_levels(intel_dp);
3695
3696                 if (IS_BROXTON(dev))
3697                         signal_levels = 0;
3698                 else
3699                         mask = DDI_BUF_EMP_MASK;
3700         } else if (IS_CHERRYVIEW(dev)) {
3701                 signal_levels = chv_signal_levels(intel_dp);
3702         } else if (IS_VALLEYVIEW(dev)) {
3703                 signal_levels = vlv_signal_levels(intel_dp);
3704         } else if (IS_GEN7(dev) && port == PORT_A) {
3705                 signal_levels = gen7_edp_signal_levels(train_set);
3706                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3707         } else if (IS_GEN6(dev) && port == PORT_A) {
3708                 signal_levels = gen6_edp_signal_levels(train_set);
3709                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3710         } else {
3711                 signal_levels = gen4_signal_levels(train_set);
3712                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3713         }
3714
3715         if (mask)
3716                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3717
3718         DRM_DEBUG_KMS("Using vswing level %d\n",
3719                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3720         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3721                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3722                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3723
3724         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3725
3726         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3727         POSTING_READ(intel_dp->output_reg);
3728 }
3729
3730 void
3731 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3732                                        uint8_t dp_train_pat)
3733 {
3734         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3735         struct drm_i915_private *dev_priv =
3736                 to_i915(intel_dig_port->base.base.dev);
3737
3738         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3739
3740         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3741         POSTING_READ(intel_dp->output_reg);
3742 }
3743
3744 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3745 {
3746         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3747         struct drm_device *dev = intel_dig_port->base.base.dev;
3748         struct drm_i915_private *dev_priv = dev->dev_private;
3749         enum port port = intel_dig_port->port;
3750         uint32_t val;
3751
3752         if (!HAS_DDI(dev))
3753                 return;
3754
3755         val = I915_READ(DP_TP_CTL(port));
3756         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3757         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3758         I915_WRITE(DP_TP_CTL(port), val);
3759
3760         /*
3761          * On PORT_A we can have only eDP in SST mode. There the only reason
3762          * we need to set idle transmission mode is to work around a HW issue
3763          * where we enable the pipe while not in idle link-training mode.
3764          * In this case there is requirement to wait for a minimum number of
3765          * idle patterns to be sent.
3766          */
3767         if (port == PORT_A)
3768                 return;
3769
3770         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3771                      1))
3772                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3773 }
3774
3775 static void
3776 intel_dp_link_down(struct intel_dp *intel_dp)
3777 {
3778         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3779         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3780         enum port port = intel_dig_port->port;
3781         struct drm_device *dev = intel_dig_port->base.base.dev;
3782         struct drm_i915_private *dev_priv = dev->dev_private;
3783         uint32_t DP = intel_dp->DP;
3784
3785         if (WARN_ON(HAS_DDI(dev)))
3786                 return;
3787
3788         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3789                 return;
3790
3791         DRM_DEBUG_KMS("\n");
3792
3793         if ((IS_GEN7(dev) && port == PORT_A) ||
3794             (HAS_PCH_CPT(dev) && port != PORT_A)) {
3795                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3796                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3797         } else {
3798                 if (IS_CHERRYVIEW(dev))
3799                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3800                 else
3801                         DP &= ~DP_LINK_TRAIN_MASK;
3802                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3803         }
3804         I915_WRITE(intel_dp->output_reg, DP);
3805         POSTING_READ(intel_dp->output_reg);
3806
3807         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3808         I915_WRITE(intel_dp->output_reg, DP);
3809         POSTING_READ(intel_dp->output_reg);
3810
3811         /*
3812          * HW workaround for IBX, we need to move the port
3813          * to transcoder A after disabling it to allow the
3814          * matching HDMI port to be enabled on transcoder A.
3815          */
3816         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3817                 /*
3818                  * We get CPU/PCH FIFO underruns on the other pipe when
3819                  * doing the workaround. Sweep them under the rug.
3820                  */
3821                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3822                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3823
3824                 /* always enable with pattern 1 (as per spec) */
3825                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3826                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3827                 I915_WRITE(intel_dp->output_reg, DP);
3828                 POSTING_READ(intel_dp->output_reg);
3829
3830                 DP &= ~DP_PORT_EN;
3831                 I915_WRITE(intel_dp->output_reg, DP);
3832                 POSTING_READ(intel_dp->output_reg);
3833
3834                 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3835                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3836                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3837         }
3838
3839         msleep(intel_dp->panel_power_down_delay);
3840
3841         intel_dp->DP = DP;
3842 }
3843
3844 static bool
3845 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3846 {
3847         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3848         struct drm_device *dev = dig_port->base.base.dev;
3849         struct drm_i915_private *dev_priv = dev->dev_private;
3850         uint8_t rev;
3851
3852         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3853                                     sizeof(intel_dp->dpcd)) < 0)
3854                 return false; /* aux transfer failed */
3855
3856         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3857
3858         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3859                 return false; /* DPCD not present */
3860
3861         /* Check if the panel supports PSR */
3862         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3863         if (is_edp(intel_dp)) {
3864                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3865                                         intel_dp->psr_dpcd,
3866                                         sizeof(intel_dp->psr_dpcd));
3867                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3868                         dev_priv->psr.sink_support = true;
3869                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3870                 }
3871
3872                 if (INTEL_INFO(dev)->gen >= 9 &&
3873                         (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3874                         uint8_t frame_sync_cap;
3875
3876                         dev_priv->psr.sink_support = true;
3877                         intel_dp_dpcd_read_wake(&intel_dp->aux,
3878                                         DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3879                                         &frame_sync_cap, 1);
3880                         dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3881                         /* PSR2 needs frame sync as well */
3882                         dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3883                         DRM_DEBUG_KMS("PSR2 %s on sink",
3884                                 dev_priv->psr.psr2_support ? "supported" : "not supported");
3885                 }
3886         }
3887
3888         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
3889                       yesno(intel_dp_source_supports_hbr2(intel_dp)),
3890                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
3891
3892         /* Intermediate frequency support */
3893         if (is_edp(intel_dp) &&
3894             (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3895             (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3896             (rev >= 0x03)) { /* eDp v1.4 or higher */
3897                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3898                 int i;
3899
3900                 intel_dp_dpcd_read_wake(&intel_dp->aux,
3901                                 DP_SUPPORTED_LINK_RATES,
3902                                 sink_rates,
3903                                 sizeof(sink_rates));
3904
3905                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3906                         int val = le16_to_cpu(sink_rates[i]);
3907
3908                         if (val == 0)
3909                                 break;
3910
3911                         /* Value read is in kHz while drm clock is saved in deca-kHz */
3912                         intel_dp->sink_rates[i] = (val * 200) / 10;
3913                 }
3914                 intel_dp->num_sink_rates = i;
3915         }
3916
3917         intel_dp_print_rates(intel_dp);
3918
3919         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3920               DP_DWN_STRM_PORT_PRESENT))
3921                 return true; /* native DP sink */
3922
3923         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3924                 return true; /* no per-port downstream info */
3925
3926         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3927                                     intel_dp->downstream_ports,
3928                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3929                 return false; /* downstream port status fetch failed */
3930
3931         return true;
3932 }
3933
3934 static void
3935 intel_dp_probe_oui(struct intel_dp *intel_dp)
3936 {
3937         u8 buf[3];
3938
3939         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3940                 return;
3941
3942         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3943                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3944                               buf[0], buf[1], buf[2]);
3945
3946         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3947                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3948                               buf[0], buf[1], buf[2]);
3949 }
3950
3951 static bool
3952 intel_dp_probe_mst(struct intel_dp *intel_dp)
3953 {
3954         u8 buf[1];
3955
3956         if (!intel_dp->can_mst)
3957                 return false;
3958
3959         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3960                 return false;
3961
3962         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3963                 if (buf[0] & DP_MST_CAP) {
3964                         DRM_DEBUG_KMS("Sink is MST capable\n");
3965                         intel_dp->is_mst = true;
3966                 } else {
3967                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3968                         intel_dp->is_mst = false;
3969                 }
3970         }
3971
3972         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3973         return intel_dp->is_mst;
3974 }
3975
3976 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3977 {
3978         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3979         struct drm_device *dev = dig_port->base.base.dev;
3980         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3981         u8 buf;
3982         int ret = 0;
3983         int count = 0;
3984         int attempts = 10;
3985
3986         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3987                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3988                 ret = -EIO;
3989                 goto out;
3990         }
3991
3992         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3993                                buf & ~DP_TEST_SINK_START) < 0) {
3994                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3995                 ret = -EIO;
3996                 goto out;
3997         }
3998
3999         do {
4000                 intel_wait_for_vblank(dev, intel_crtc->pipe);
4001
4002                 if (drm_dp_dpcd_readb(&intel_dp->aux,
4003                                       DP_TEST_SINK_MISC, &buf) < 0) {
4004                         ret = -EIO;
4005                         goto out;
4006                 }
4007                 count = buf & DP_TEST_COUNT_MASK;
4008         } while (--attempts && count);
4009
4010         if (attempts == 0) {
4011                 DRM_ERROR("TIMEOUT: Sink CRC counter is not zeroed\n");
4012                 ret = -ETIMEDOUT;
4013         }
4014
4015  out:
4016         hsw_enable_ips(intel_crtc);
4017         return ret;
4018 }
4019
4020 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
4021 {
4022         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4023         struct drm_device *dev = dig_port->base.base.dev;
4024         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
4025         u8 buf;
4026         int ret;
4027
4028         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
4029                 return -EIO;
4030
4031         if (!(buf & DP_TEST_CRC_SUPPORTED))
4032                 return -ENOTTY;
4033
4034         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4035                 return -EIO;
4036
4037         if (buf & DP_TEST_SINK_START) {
4038                 ret = intel_dp_sink_crc_stop(intel_dp);
4039                 if (ret)
4040                         return ret;
4041         }
4042
4043         hsw_disable_ips(intel_crtc);
4044
4045         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4046                                buf | DP_TEST_SINK_START) < 0) {
4047                 hsw_enable_ips(intel_crtc);
4048                 return -EIO;
4049         }
4050
4051         intel_wait_for_vblank(dev, intel_crtc->pipe);
4052         return 0;
4053 }
4054
4055 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
4056 {
4057         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4058         struct drm_device *dev = dig_port->base.base.dev;
4059         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
4060         u8 buf;
4061         int count, ret;
4062         int attempts = 6;
4063
4064         ret = intel_dp_sink_crc_start(intel_dp);
4065         if (ret)
4066                 return ret;
4067
4068         do {
4069                 intel_wait_for_vblank(dev, intel_crtc->pipe);
4070
4071                 if (drm_dp_dpcd_readb(&intel_dp->aux,
4072                                       DP_TEST_SINK_MISC, &buf) < 0) {
4073                         ret = -EIO;
4074                         goto stop;
4075                 }
4076                 count = buf & DP_TEST_COUNT_MASK;
4077
4078         } while (--attempts && count == 0);
4079
4080         if (attempts == 0) {
4081                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4082                 ret = -ETIMEDOUT;
4083                 goto stop;
4084         }
4085
4086         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4087                 ret = -EIO;
4088                 goto stop;
4089         }
4090
4091 stop:
4092         intel_dp_sink_crc_stop(intel_dp);
4093         return ret;
4094 }
4095
4096 static bool
4097 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4098 {
4099         return intel_dp_dpcd_read_wake(&intel_dp->aux,
4100                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
4101                                        sink_irq_vector, 1) == 1;
4102 }
4103
4104 static bool
4105 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4106 {
4107         int ret;
4108
4109         ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4110                                              DP_SINK_COUNT_ESI,
4111                                              sink_irq_vector, 14);
4112         if (ret != 14)
4113                 return false;
4114
4115         return true;
4116 }
4117
4118 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4119 {
4120         uint8_t test_result = DP_TEST_ACK;
4121         return test_result;
4122 }
4123
4124 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4125 {
4126         uint8_t test_result = DP_TEST_NAK;
4127         return test_result;
4128 }
4129
4130 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4131 {
4132         uint8_t test_result = DP_TEST_NAK;
4133         struct intel_connector *intel_connector = intel_dp->attached_connector;
4134         struct drm_connector *connector = &intel_connector->base;
4135
4136         if (intel_connector->detect_edid == NULL ||
4137             connector->edid_corrupt ||
4138             intel_dp->aux.i2c_defer_count > 6) {
4139                 /* Check EDID read for NACKs, DEFERs and corruption
4140                  * (DP CTS 1.2 Core r1.1)
4141                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4142                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4143                  *    4.2.2.6 : EDID corruption detected
4144                  * Use failsafe mode for all cases
4145                  */
4146                 if (intel_dp->aux.i2c_nack_count > 0 ||
4147                         intel_dp->aux.i2c_defer_count > 0)
4148                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4149                                       intel_dp->aux.i2c_nack_count,
4150                                       intel_dp->aux.i2c_defer_count);
4151                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4152         } else {
4153                 struct edid *block = intel_connector->detect_edid;
4154
4155                 /* We have to write the checksum
4156                  * of the last block read
4157                  */
4158                 block += intel_connector->detect_edid->extensions;
4159
4160                 if (!drm_dp_dpcd_write(&intel_dp->aux,
4161                                         DP_TEST_EDID_CHECKSUM,
4162                                         &block->checksum,
4163                                         1))
4164                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4165
4166                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4167                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4168         }
4169
4170         /* Set test active flag here so userspace doesn't interrupt things */
4171         intel_dp->compliance_test_active = 1;
4172
4173         return test_result;
4174 }
4175
4176 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4177 {
4178         uint8_t test_result = DP_TEST_NAK;
4179         return test_result;
4180 }
4181
4182 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4183 {
4184         uint8_t response = DP_TEST_NAK;
4185         uint8_t rxdata = 0;
4186         int status = 0;
4187
4188         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4189         if (status <= 0) {
4190                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4191                 goto update_status;
4192         }
4193
4194         switch (rxdata) {
4195         case DP_TEST_LINK_TRAINING:
4196                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4197                 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4198                 response = intel_dp_autotest_link_training(intel_dp);
4199                 break;
4200         case DP_TEST_LINK_VIDEO_PATTERN:
4201                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4202                 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4203                 response = intel_dp_autotest_video_pattern(intel_dp);
4204                 break;
4205         case DP_TEST_LINK_EDID_READ:
4206                 DRM_DEBUG_KMS("EDID test requested\n");
4207                 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4208                 response = intel_dp_autotest_edid(intel_dp);
4209                 break;
4210         case DP_TEST_LINK_PHY_TEST_PATTERN:
4211                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4212                 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4213                 response = intel_dp_autotest_phy_pattern(intel_dp);
4214                 break;
4215         default:
4216                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4217                 break;
4218         }
4219
4220 update_status:
4221         status = drm_dp_dpcd_write(&intel_dp->aux,
4222                                    DP_TEST_RESPONSE,
4223                                    &response, 1);
4224         if (status <= 0)
4225                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4226 }
4227
4228 static int
4229 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4230 {
4231         bool bret;
4232
4233         if (intel_dp->is_mst) {
4234                 u8 esi[16] = { 0 };
4235                 int ret = 0;
4236                 int retry;
4237                 bool handled;
4238                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4239 go_again:
4240                 if (bret == true) {
4241
4242                         /* check link status - esi[10] = 0x200c */
4243                         if (intel_dp->active_mst_links &&
4244                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4245                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4246                                 intel_dp_start_link_train(intel_dp);
4247                                 intel_dp_stop_link_train(intel_dp);
4248                         }
4249
4250                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4251                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4252
4253                         if (handled) {
4254                                 for (retry = 0; retry < 3; retry++) {
4255                                         int wret;
4256                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4257                                                                  DP_SINK_COUNT_ESI+1,
4258                                                                  &esi[1], 3);
4259                                         if (wret == 3) {
4260                                                 break;
4261                                         }
4262                                 }
4263
4264                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4265                                 if (bret == true) {
4266                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4267                                         goto go_again;
4268                                 }
4269                         } else
4270                                 ret = 0;
4271
4272                         return ret;
4273                 } else {
4274                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4275                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4276                         intel_dp->is_mst = false;
4277                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4278                         /* send a hotplug event */
4279                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4280                 }
4281         }
4282         return -EINVAL;
4283 }
4284
4285 /*
4286  * According to DP spec
4287  * 5.1.2:
4288  *  1. Read DPCD
4289  *  2. Configure link according to Receiver Capabilities
4290  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4291  *  4. Check link status on receipt of hot-plug interrupt
4292  */
4293 static void
4294 intel_dp_check_link_status(struct intel_dp *intel_dp)
4295 {
4296         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4297         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4298         u8 sink_irq_vector;
4299         u8 link_status[DP_LINK_STATUS_SIZE];
4300
4301         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4302
4303         /*
4304          * Clearing compliance test variables to allow capturing
4305          * of values for next automated test request.
4306          */
4307         intel_dp->compliance_test_active = 0;
4308         intel_dp->compliance_test_type = 0;
4309         intel_dp->compliance_test_data = 0;
4310
4311         if (!intel_encoder->base.crtc)
4312                 return;
4313
4314         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4315                 return;
4316
4317         /* Try to read receiver status if the link appears to be up */
4318         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4319                 return;
4320         }
4321
4322         /* Now read the DPCD to see if it's actually running */
4323         if (!intel_dp_get_dpcd(intel_dp)) {
4324                 return;
4325         }
4326
4327         /* Try to read the source of the interrupt */
4328         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4329             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4330                 /* Clear interrupt source */
4331                 drm_dp_dpcd_writeb(&intel_dp->aux,
4332                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4333                                    sink_irq_vector);
4334
4335                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4336                         DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4337                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4338                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4339         }
4340
4341         /* if link training is requested we should perform it always */
4342         if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4343                 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4344                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4345                               intel_encoder->base.name);
4346                 intel_dp_start_link_train(intel_dp);
4347                 intel_dp_stop_link_train(intel_dp);
4348         }
4349 }
4350
4351 /* XXX this is probably wrong for multiple downstream ports */
4352 static enum drm_connector_status
4353 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4354 {
4355         uint8_t *dpcd = intel_dp->dpcd;
4356         uint8_t type;
4357
4358         if (!intel_dp_get_dpcd(intel_dp))
4359                 return connector_status_disconnected;
4360
4361         /* if there's no downstream port, we're done */
4362         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4363                 return connector_status_connected;
4364
4365         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4366         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4367             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4368                 uint8_t reg;
4369
4370                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4371                                             &reg, 1) < 0)
4372                         return connector_status_unknown;
4373
4374                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4375                                               : connector_status_disconnected;
4376         }
4377
4378         /* If no HPD, poke DDC gently */
4379         if (drm_probe_ddc(&intel_dp->aux.ddc))
4380                 return connector_status_connected;
4381
4382         /* Well we tried, say unknown for unreliable port types */
4383         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4384                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4385                 if (type == DP_DS_PORT_TYPE_VGA ||
4386                     type == DP_DS_PORT_TYPE_NON_EDID)
4387                         return connector_status_unknown;
4388         } else {
4389                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4390                         DP_DWN_STRM_PORT_TYPE_MASK;
4391                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4392                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4393                         return connector_status_unknown;
4394         }
4395
4396         /* Anything else is out of spec, warn and ignore */
4397         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4398         return connector_status_disconnected;
4399 }
4400
4401 static enum drm_connector_status
4402 edp_detect(struct intel_dp *intel_dp)
4403 {
4404         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4405         enum drm_connector_status status;
4406
4407         status = intel_panel_detect(dev);
4408         if (status == connector_status_unknown)
4409                 status = connector_status_connected;
4410
4411         return status;
4412 }
4413
4414 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4415                                        struct intel_digital_port *port)
4416 {
4417         u32 bit;
4418
4419         switch (port->port) {
4420         case PORT_A:
4421                 return true;
4422         case PORT_B:
4423                 bit = SDE_PORTB_HOTPLUG;
4424                 break;
4425         case PORT_C:
4426                 bit = SDE_PORTC_HOTPLUG;
4427                 break;
4428         case PORT_D:
4429                 bit = SDE_PORTD_HOTPLUG;
4430                 break;
4431         default:
4432                 MISSING_CASE(port->port);
4433                 return false;
4434         }
4435
4436         return I915_READ(SDEISR) & bit;
4437 }
4438
4439 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4440                                        struct intel_digital_port *port)
4441 {
4442         u32 bit;
4443
4444         switch (port->port) {
4445         case PORT_A:
4446                 return true;
4447         case PORT_B:
4448                 bit = SDE_PORTB_HOTPLUG_CPT;
4449                 break;
4450         case PORT_C:
4451                 bit = SDE_PORTC_HOTPLUG_CPT;
4452                 break;
4453         case PORT_D:
4454                 bit = SDE_PORTD_HOTPLUG_CPT;
4455                 break;
4456         case PORT_E:
4457                 bit = SDE_PORTE_HOTPLUG_SPT;
4458                 break;
4459         default:
4460                 MISSING_CASE(port->port);
4461                 return false;
4462         }
4463
4464         return I915_READ(SDEISR) & bit;
4465 }
4466
4467 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4468                                        struct intel_digital_port *port)
4469 {
4470         u32 bit;
4471
4472         switch (port->port) {
4473         case PORT_B:
4474                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4475                 break;
4476         case PORT_C:
4477                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4478                 break;
4479         case PORT_D:
4480                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4481                 break;
4482         default:
4483                 MISSING_CASE(port->port);
4484                 return false;
4485         }
4486
4487         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4488 }
4489
4490 static bool vlv_digital_port_connected(struct drm_i915_private *dev_priv,
4491                                        struct intel_digital_port *port)
4492 {
4493         u32 bit;
4494
4495         switch (port->port) {
4496         case PORT_B:
4497                 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4498                 break;
4499         case PORT_C:
4500                 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4501                 break;
4502         case PORT_D:
4503                 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4504                 break;
4505         default:
4506                 MISSING_CASE(port->port);
4507                 return false;
4508         }
4509
4510         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4511 }
4512
4513 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4514                                        struct intel_digital_port *intel_dig_port)
4515 {
4516         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4517         enum port port;
4518         u32 bit;
4519
4520         intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4521         switch (port) {
4522         case PORT_A:
4523                 bit = BXT_DE_PORT_HP_DDIA;
4524                 break;
4525         case PORT_B:
4526                 bit = BXT_DE_PORT_HP_DDIB;
4527                 break;
4528         case PORT_C:
4529                 bit = BXT_DE_PORT_HP_DDIC;
4530                 break;
4531         default:
4532                 MISSING_CASE(port);
4533                 return false;
4534         }
4535
4536         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4537 }
4538
4539 /*
4540  * intel_digital_port_connected - is the specified port connected?
4541  * @dev_priv: i915 private structure
4542  * @port: the port to test
4543  *
4544  * Return %true if @port is connected, %false otherwise.
4545  */
4546 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4547                                          struct intel_digital_port *port)
4548 {
4549         if (HAS_PCH_IBX(dev_priv))
4550                 return ibx_digital_port_connected(dev_priv, port);
4551         if (HAS_PCH_SPLIT(dev_priv))
4552                 return cpt_digital_port_connected(dev_priv, port);
4553         else if (IS_BROXTON(dev_priv))
4554                 return bxt_digital_port_connected(dev_priv, port);
4555         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4556                 return vlv_digital_port_connected(dev_priv, port);
4557         else
4558                 return g4x_digital_port_connected(dev_priv, port);
4559 }
4560
4561 static struct edid *
4562 intel_dp_get_edid(struct intel_dp *intel_dp)
4563 {
4564         struct intel_connector *intel_connector = intel_dp->attached_connector;
4565
4566         /* use cached edid if we have one */
4567         if (intel_connector->edid) {
4568                 /* invalid edid */
4569                 if (IS_ERR(intel_connector->edid))
4570                         return NULL;
4571
4572                 return drm_edid_duplicate(intel_connector->edid);
4573         } else
4574                 return drm_get_edid(&intel_connector->base,
4575                                     &intel_dp->aux.ddc);
4576 }
4577
4578 static void
4579 intel_dp_set_edid(struct intel_dp *intel_dp)
4580 {
4581         struct intel_connector *intel_connector = intel_dp->attached_connector;
4582         struct edid *edid;
4583
4584         edid = intel_dp_get_edid(intel_dp);
4585         intel_connector->detect_edid = edid;
4586
4587         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4588                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4589         else
4590                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4591 }
4592
4593 static void
4594 intel_dp_unset_edid(struct intel_dp *intel_dp)
4595 {
4596         struct intel_connector *intel_connector = intel_dp->attached_connector;
4597
4598         kfree(intel_connector->detect_edid);
4599         intel_connector->detect_edid = NULL;
4600
4601         intel_dp->has_audio = false;
4602 }
4603
4604 static enum drm_connector_status
4605 intel_dp_detect(struct drm_connector *connector, bool force)
4606 {
4607         struct intel_dp *intel_dp = intel_attached_dp(connector);
4608         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4609         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4610         struct drm_device *dev = connector->dev;
4611         enum drm_connector_status status;
4612         enum intel_display_power_domain power_domain;
4613         bool ret;
4614         u8 sink_irq_vector;
4615
4616         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4617                       connector->base.id, connector->name);
4618         intel_dp_unset_edid(intel_dp);
4619
4620         if (intel_dp->is_mst) {
4621                 /* MST devices are disconnected from a monitor POV */
4622                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4623                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4624                 return connector_status_disconnected;
4625         }
4626
4627         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4628         intel_display_power_get(to_i915(dev), power_domain);
4629
4630         /* Can't disconnect eDP, but you can close the lid... */
4631         if (is_edp(intel_dp))
4632                 status = edp_detect(intel_dp);
4633         else if (intel_digital_port_connected(to_i915(dev),
4634                                               dp_to_dig_port(intel_dp)))
4635                 status = intel_dp_detect_dpcd(intel_dp);
4636         else
4637                 status = connector_status_disconnected;
4638
4639         if (status != connector_status_connected) {
4640                 intel_dp->compliance_test_active = 0;
4641                 intel_dp->compliance_test_type = 0;
4642                 intel_dp->compliance_test_data = 0;
4643
4644                 goto out;
4645         }
4646
4647         intel_dp_probe_oui(intel_dp);
4648
4649         ret = intel_dp_probe_mst(intel_dp);
4650         if (ret) {
4651                 /* if we are in MST mode then this connector
4652                    won't appear connected or have anything with EDID on it */
4653                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4654                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4655                 status = connector_status_disconnected;
4656                 goto out;
4657         }
4658
4659         /*
4660          * Clearing NACK and defer counts to get their exact values
4661          * while reading EDID which are required by Compliance tests
4662          * 4.2.2.4 and 4.2.2.5
4663          */
4664         intel_dp->aux.i2c_nack_count = 0;
4665         intel_dp->aux.i2c_defer_count = 0;
4666
4667         intel_dp_set_edid(intel_dp);
4668
4669         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4670                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4671         status = connector_status_connected;
4672
4673         /* Try to read the source of the interrupt */
4674         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4675             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4676                 /* Clear interrupt source */
4677                 drm_dp_dpcd_writeb(&intel_dp->aux,
4678                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4679                                    sink_irq_vector);
4680
4681                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4682                         intel_dp_handle_test_request(intel_dp);
4683                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4684                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4685         }
4686
4687 out:
4688         intel_display_power_put(to_i915(dev), power_domain);
4689         return status;
4690 }
4691
4692 static void
4693 intel_dp_force(struct drm_connector *connector)
4694 {
4695         struct intel_dp *intel_dp = intel_attached_dp(connector);
4696         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4697         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4698         enum intel_display_power_domain power_domain;
4699
4700         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4701                       connector->base.id, connector->name);
4702         intel_dp_unset_edid(intel_dp);
4703
4704         if (connector->status != connector_status_connected)
4705                 return;
4706
4707         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4708         intel_display_power_get(dev_priv, power_domain);
4709
4710         intel_dp_set_edid(intel_dp);
4711
4712         intel_display_power_put(dev_priv, power_domain);
4713
4714         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4715                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4716 }
4717
4718 static int intel_dp_get_modes(struct drm_connector *connector)
4719 {
4720         struct intel_connector *intel_connector = to_intel_connector(connector);
4721         struct edid *edid;
4722
4723         edid = intel_connector->detect_edid;
4724         if (edid) {
4725                 int ret = intel_connector_update_modes(connector, edid);
4726                 if (ret)
4727                         return ret;
4728         }
4729
4730         /* if eDP has no EDID, fall back to fixed mode */
4731         if (is_edp(intel_attached_dp(connector)) &&
4732             intel_connector->panel.fixed_mode) {
4733                 struct drm_display_mode *mode;
4734
4735                 mode = drm_mode_duplicate(connector->dev,
4736                                           intel_connector->panel.fixed_mode);
4737                 if (mode) {
4738                         drm_mode_probed_add(connector, mode);
4739                         return 1;
4740                 }
4741         }
4742
4743         return 0;
4744 }
4745
4746 static bool
4747 intel_dp_detect_audio(struct drm_connector *connector)
4748 {
4749         bool has_audio = false;
4750         struct edid *edid;
4751
4752         edid = to_intel_connector(connector)->detect_edid;
4753         if (edid)
4754                 has_audio = drm_detect_monitor_audio(edid);
4755
4756         return has_audio;
4757 }
4758
4759 static int
4760 intel_dp_set_property(struct drm_connector *connector,
4761                       struct drm_property *property,
4762                       uint64_t val)
4763 {
4764         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4765         struct intel_connector *intel_connector = to_intel_connector(connector);
4766         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4767         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4768         int ret;
4769
4770         ret = drm_object_property_set_value(&connector->base, property, val);
4771         if (ret)
4772                 return ret;
4773
4774         if (property == dev_priv->force_audio_property) {
4775                 int i = val;
4776                 bool has_audio;
4777
4778                 if (i == intel_dp->force_audio)
4779                         return 0;
4780
4781                 intel_dp->force_audio = i;
4782
4783                 if (i == HDMI_AUDIO_AUTO)
4784                         has_audio = intel_dp_detect_audio(connector);
4785                 else
4786                         has_audio = (i == HDMI_AUDIO_ON);
4787
4788                 if (has_audio == intel_dp->has_audio)
4789                         return 0;
4790
4791                 intel_dp->has_audio = has_audio;
4792                 goto done;
4793         }
4794
4795         if (property == dev_priv->broadcast_rgb_property) {
4796                 bool old_auto = intel_dp->color_range_auto;
4797                 bool old_range = intel_dp->limited_color_range;
4798
4799                 switch (val) {
4800                 case INTEL_BROADCAST_RGB_AUTO:
4801                         intel_dp->color_range_auto = true;
4802                         break;
4803                 case INTEL_BROADCAST_RGB_FULL:
4804                         intel_dp->color_range_auto = false;
4805                         intel_dp->limited_color_range = false;
4806                         break;
4807                 case INTEL_BROADCAST_RGB_LIMITED:
4808                         intel_dp->color_range_auto = false;
4809                         intel_dp->limited_color_range = true;
4810                         break;
4811                 default:
4812                         return -EINVAL;
4813                 }
4814
4815                 if (old_auto == intel_dp->color_range_auto &&
4816                     old_range == intel_dp->limited_color_range)
4817                         return 0;
4818
4819                 goto done;
4820         }
4821
4822         if (is_edp(intel_dp) &&
4823             property == connector->dev->mode_config.scaling_mode_property) {
4824                 if (val == DRM_MODE_SCALE_NONE) {
4825                         DRM_DEBUG_KMS("no scaling not supported\n");
4826                         return -EINVAL;
4827                 }
4828
4829                 if (intel_connector->panel.fitting_mode == val) {
4830                         /* the eDP scaling property is not changed */
4831                         return 0;
4832                 }
4833                 intel_connector->panel.fitting_mode = val;
4834
4835                 goto done;
4836         }
4837
4838         return -EINVAL;
4839
4840 done:
4841         if (intel_encoder->base.crtc)
4842                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4843
4844         return 0;
4845 }
4846
4847 static void
4848 intel_dp_connector_destroy(struct drm_connector *connector)
4849 {
4850         struct intel_connector *intel_connector = to_intel_connector(connector);
4851
4852         kfree(intel_connector->detect_edid);
4853
4854         if (!IS_ERR_OR_NULL(intel_connector->edid))
4855                 kfree(intel_connector->edid);
4856
4857         /* Can't call is_edp() since the encoder may have been destroyed
4858          * already. */
4859         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4860                 intel_panel_fini(&intel_connector->panel);
4861
4862         drm_connector_cleanup(connector);
4863         kfree(connector);
4864 }
4865
4866 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4867 {
4868         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4869         struct intel_dp *intel_dp = &intel_dig_port->dp;
4870
4871         intel_dp_aux_fini(intel_dp);
4872         intel_dp_mst_encoder_cleanup(intel_dig_port);
4873         if (is_edp(intel_dp)) {
4874                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4875                 /*
4876                  * vdd might still be enabled do to the delayed vdd off.
4877                  * Make sure vdd is actually turned off here.
4878                  */
4879                 pps_lock(intel_dp);
4880                 edp_panel_vdd_off_sync(intel_dp);
4881                 pps_unlock(intel_dp);
4882
4883                 if (intel_dp->edp_notifier.notifier_call) {
4884                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4885                         intel_dp->edp_notifier.notifier_call = NULL;
4886                 }
4887         }
4888         drm_encoder_cleanup(encoder);
4889         kfree(intel_dig_port);
4890 }
4891
4892 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4893 {
4894         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4895
4896         if (!is_edp(intel_dp))
4897                 return;
4898
4899         /*
4900          * vdd might still be enabled do to the delayed vdd off.
4901          * Make sure vdd is actually turned off here.
4902          */
4903         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4904         pps_lock(intel_dp);
4905         edp_panel_vdd_off_sync(intel_dp);
4906         pps_unlock(intel_dp);
4907 }
4908
4909 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4910 {
4911         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4912         struct drm_device *dev = intel_dig_port->base.base.dev;
4913         struct drm_i915_private *dev_priv = dev->dev_private;
4914         enum intel_display_power_domain power_domain;
4915
4916         lockdep_assert_held(&dev_priv->pps_mutex);
4917
4918         if (!edp_have_panel_vdd(intel_dp))
4919                 return;
4920
4921         /*
4922          * The VDD bit needs a power domain reference, so if the bit is
4923          * already enabled when we boot or resume, grab this reference and
4924          * schedule a vdd off, so we don't hold on to the reference
4925          * indefinitely.
4926          */
4927         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4928         power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4929         intel_display_power_get(dev_priv, power_domain);
4930
4931         edp_panel_vdd_schedule_off(intel_dp);
4932 }
4933
4934 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4935 {
4936         struct intel_dp *intel_dp;
4937
4938         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4939                 return;
4940
4941         intel_dp = enc_to_intel_dp(encoder);
4942
4943         pps_lock(intel_dp);
4944
4945         /*
4946          * Read out the current power sequencer assignment,
4947          * in case the BIOS did something with it.
4948          */
4949         if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
4950                 vlv_initial_power_sequencer_setup(intel_dp);
4951
4952         intel_edp_panel_vdd_sanitize(intel_dp);
4953
4954         pps_unlock(intel_dp);
4955 }
4956
4957 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4958         .dpms = drm_atomic_helper_connector_dpms,
4959         .detect = intel_dp_detect,
4960         .force = intel_dp_force,
4961         .fill_modes = drm_helper_probe_single_connector_modes,
4962         .set_property = intel_dp_set_property,
4963         .atomic_get_property = intel_connector_atomic_get_property,
4964         .destroy = intel_dp_connector_destroy,
4965         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4966         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4967 };
4968
4969 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4970         .get_modes = intel_dp_get_modes,
4971         .mode_valid = intel_dp_mode_valid,
4972         .best_encoder = intel_best_encoder,
4973 };
4974
4975 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4976         .reset = intel_dp_encoder_reset,
4977         .destroy = intel_dp_encoder_destroy,
4978 };
4979
4980 enum irqreturn
4981 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4982 {
4983         struct intel_dp *intel_dp = &intel_dig_port->dp;
4984         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4985         struct drm_device *dev = intel_dig_port->base.base.dev;
4986         struct drm_i915_private *dev_priv = dev->dev_private;
4987         enum intel_display_power_domain power_domain;
4988         enum irqreturn ret = IRQ_NONE;
4989
4990         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4991             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4992                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4993
4994         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4995                 /*
4996                  * vdd off can generate a long pulse on eDP which
4997                  * would require vdd on to handle it, and thus we
4998                  * would end up in an endless cycle of
4999                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5000                  */
5001                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5002                               port_name(intel_dig_port->port));
5003                 return IRQ_HANDLED;
5004         }
5005
5006         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5007                       port_name(intel_dig_port->port),
5008                       long_hpd ? "long" : "short");
5009
5010         power_domain = intel_display_port_aux_power_domain(intel_encoder);
5011         intel_display_power_get(dev_priv, power_domain);
5012
5013         if (long_hpd) {
5014                 /* indicate that we need to restart link training */
5015                 intel_dp->train_set_valid = false;
5016
5017                 if (!intel_digital_port_connected(dev_priv, intel_dig_port))
5018                         goto mst_fail;
5019
5020                 if (!intel_dp_get_dpcd(intel_dp)) {
5021                         goto mst_fail;
5022                 }
5023
5024                 intel_dp_probe_oui(intel_dp);
5025
5026                 if (!intel_dp_probe_mst(intel_dp)) {
5027                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
5028                         intel_dp_check_link_status(intel_dp);
5029                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
5030                         goto mst_fail;
5031                 }
5032         } else {
5033                 if (intel_dp->is_mst) {
5034                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
5035                                 goto mst_fail;
5036                 }
5037
5038                 if (!intel_dp->is_mst) {
5039                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
5040                         intel_dp_check_link_status(intel_dp);
5041                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
5042                 }
5043         }
5044
5045         ret = IRQ_HANDLED;
5046
5047         goto put_power;
5048 mst_fail:
5049         /* if we were in MST mode, and device is not there get out of MST mode */
5050         if (intel_dp->is_mst) {
5051                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5052                 intel_dp->is_mst = false;
5053                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
5054         }
5055 put_power:
5056         intel_display_power_put(dev_priv, power_domain);
5057
5058         return ret;
5059 }
5060
5061 /* check the VBT to see whether the eDP is on another port */
5062 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
5063 {
5064         struct drm_i915_private *dev_priv = dev->dev_private;
5065         union child_device_config *p_child;
5066         int i;
5067         static const short port_mapping[] = {
5068                 [PORT_B] = DVO_PORT_DPB,
5069                 [PORT_C] = DVO_PORT_DPC,
5070                 [PORT_D] = DVO_PORT_DPD,
5071                 [PORT_E] = DVO_PORT_DPE,
5072         };
5073
5074         /*
5075          * eDP not supported on g4x. so bail out early just
5076          * for a bit extra safety in case the VBT is bonkers.
5077          */
5078         if (INTEL_INFO(dev)->gen < 5)
5079                 return false;
5080
5081         if (port == PORT_A)
5082                 return true;
5083
5084         if (!dev_priv->vbt.child_dev_num)
5085                 return false;
5086
5087         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
5088                 p_child = dev_priv->vbt.child_dev + i;
5089
5090                 if (p_child->common.dvo_port == port_mapping[port] &&
5091                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
5092                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
5093                         return true;
5094         }
5095         return false;
5096 }
5097
5098 void
5099 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5100 {
5101         struct intel_connector *intel_connector = to_intel_connector(connector);
5102
5103         intel_attach_force_audio_property(connector);
5104         intel_attach_broadcast_rgb_property(connector);
5105         intel_dp->color_range_auto = true;
5106
5107         if (is_edp(intel_dp)) {
5108                 drm_mode_create_scaling_mode_property(connector->dev);
5109                 drm_object_attach_property(
5110                         &connector->base,
5111                         connector->dev->mode_config.scaling_mode_property,
5112                         DRM_MODE_SCALE_ASPECT);
5113                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5114         }
5115 }
5116
5117 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5118 {
5119         intel_dp->last_power_cycle = jiffies;
5120         intel_dp->last_power_on = jiffies;
5121         intel_dp->last_backlight_off = jiffies;
5122 }
5123
5124 static void
5125 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5126                                     struct intel_dp *intel_dp)
5127 {
5128         struct drm_i915_private *dev_priv = dev->dev_private;
5129         struct edp_power_seq cur, vbt, spec,
5130                 *final = &intel_dp->pps_delays;
5131         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5132         i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
5133
5134         lockdep_assert_held(&dev_priv->pps_mutex);
5135
5136         /* already initialized? */
5137         if (final->t11_t12 != 0)
5138                 return;
5139
5140         if (IS_BROXTON(dev)) {
5141                 /*
5142                  * TODO: BXT has 2 sets of PPS registers.
5143                  * Correct Register for Broxton need to be identified
5144                  * using VBT. hardcoding for now
5145                  */
5146                 pp_ctrl_reg = BXT_PP_CONTROL(0);
5147                 pp_on_reg = BXT_PP_ON_DELAYS(0);
5148                 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5149         } else if (HAS_PCH_SPLIT(dev)) {
5150                 pp_ctrl_reg = PCH_PP_CONTROL;
5151                 pp_on_reg = PCH_PP_ON_DELAYS;
5152                 pp_off_reg = PCH_PP_OFF_DELAYS;
5153                 pp_div_reg = PCH_PP_DIVISOR;
5154         } else {
5155                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5156
5157                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5158                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5159                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5160                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5161         }
5162
5163         /* Workaround: Need to write PP_CONTROL with the unlock key as
5164          * the very first thing. */
5165         pp_ctl = ironlake_get_pp_control(intel_dp);
5166
5167         pp_on = I915_READ(pp_on_reg);
5168         pp_off = I915_READ(pp_off_reg);
5169         if (!IS_BROXTON(dev)) {
5170                 I915_WRITE(pp_ctrl_reg, pp_ctl);
5171                 pp_div = I915_READ(pp_div_reg);
5172         }
5173
5174         /* Pull timing values out of registers */
5175         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5176                 PANEL_POWER_UP_DELAY_SHIFT;
5177
5178         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5179                 PANEL_LIGHT_ON_DELAY_SHIFT;
5180
5181         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5182                 PANEL_LIGHT_OFF_DELAY_SHIFT;
5183
5184         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5185                 PANEL_POWER_DOWN_DELAY_SHIFT;
5186
5187         if (IS_BROXTON(dev)) {
5188                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5189                         BXT_POWER_CYCLE_DELAY_SHIFT;
5190                 if (tmp > 0)
5191                         cur.t11_t12 = (tmp - 1) * 1000;
5192                 else
5193                         cur.t11_t12 = 0;
5194         } else {
5195                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5196                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5197         }
5198
5199         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5200                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5201
5202         vbt = dev_priv->vbt.edp_pps;
5203
5204         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5205          * our hw here, which are all in 100usec. */
5206         spec.t1_t3 = 210 * 10;
5207         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5208         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5209         spec.t10 = 500 * 10;
5210         /* This one is special and actually in units of 100ms, but zero
5211          * based in the hw (so we need to add 100 ms). But the sw vbt
5212          * table multiplies it with 1000 to make it in units of 100usec,
5213          * too. */
5214         spec.t11_t12 = (510 + 100) * 10;
5215
5216         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5217                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5218
5219         /* Use the max of the register settings and vbt. If both are
5220          * unset, fall back to the spec limits. */
5221 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5222                                        spec.field : \
5223                                        max(cur.field, vbt.field))
5224         assign_final(t1_t3);
5225         assign_final(t8);
5226         assign_final(t9);
5227         assign_final(t10);
5228         assign_final(t11_t12);
5229 #undef assign_final
5230
5231 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5232         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5233         intel_dp->backlight_on_delay = get_delay(t8);
5234         intel_dp->backlight_off_delay = get_delay(t9);
5235         intel_dp->panel_power_down_delay = get_delay(t10);
5236         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5237 #undef get_delay
5238
5239         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5240                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5241                       intel_dp->panel_power_cycle_delay);
5242
5243         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5244                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5245 }
5246
5247 static void
5248 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5249                                               struct intel_dp *intel_dp)
5250 {
5251         struct drm_i915_private *dev_priv = dev->dev_private;
5252         u32 pp_on, pp_off, pp_div, port_sel = 0;
5253         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
5254         i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg;
5255         enum port port = dp_to_dig_port(intel_dp)->port;
5256         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5257
5258         lockdep_assert_held(&dev_priv->pps_mutex);
5259
5260         if (IS_BROXTON(dev)) {
5261                 /*
5262                  * TODO: BXT has 2 sets of PPS registers.
5263                  * Correct Register for Broxton need to be identified
5264                  * using VBT. hardcoding for now
5265                  */
5266                 pp_ctrl_reg = BXT_PP_CONTROL(0);
5267                 pp_on_reg = BXT_PP_ON_DELAYS(0);
5268                 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5269
5270         } else if (HAS_PCH_SPLIT(dev)) {
5271                 pp_on_reg = PCH_PP_ON_DELAYS;
5272                 pp_off_reg = PCH_PP_OFF_DELAYS;
5273                 pp_div_reg = PCH_PP_DIVISOR;
5274         } else {
5275                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5276
5277                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5278                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5279                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5280         }
5281
5282         /*
5283          * And finally store the new values in the power sequencer. The
5284          * backlight delays are set to 1 because we do manual waits on them. For
5285          * T8, even BSpec recommends doing it. For T9, if we don't do this,
5286          * we'll end up waiting for the backlight off delay twice: once when we
5287          * do the manual sleep, and once when we disable the panel and wait for
5288          * the PP_STATUS bit to become zero.
5289          */
5290         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5291                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5292         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5293                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5294         /* Compute the divisor for the pp clock, simply match the Bspec
5295          * formula. */
5296         if (IS_BROXTON(dev)) {
5297                 pp_div = I915_READ(pp_ctrl_reg);
5298                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5299                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5300                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5301         } else {
5302                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5303                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5304                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5305         }
5306
5307         /* Haswell doesn't have any port selection bits for the panel
5308          * power sequencer any more. */
5309         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5310                 port_sel = PANEL_PORT_SELECT_VLV(port);
5311         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5312                 if (port == PORT_A)
5313                         port_sel = PANEL_PORT_SELECT_DPA;
5314                 else
5315                         port_sel = PANEL_PORT_SELECT_DPD;
5316         }
5317
5318         pp_on |= port_sel;
5319
5320         I915_WRITE(pp_on_reg, pp_on);
5321         I915_WRITE(pp_off_reg, pp_off);
5322         if (IS_BROXTON(dev))
5323                 I915_WRITE(pp_ctrl_reg, pp_div);
5324         else
5325                 I915_WRITE(pp_div_reg, pp_div);
5326
5327         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5328                       I915_READ(pp_on_reg),
5329                       I915_READ(pp_off_reg),
5330                       IS_BROXTON(dev) ?
5331                       (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
5332                       I915_READ(pp_div_reg));
5333 }
5334
5335 /**
5336  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5337  * @dev: DRM device
5338  * @refresh_rate: RR to be programmed
5339  *
5340  * This function gets called when refresh rate (RR) has to be changed from
5341  * one frequency to another. Switches can be between high and low RR
5342  * supported by the panel or to any other RR based on media playback (in
5343  * this case, RR value needs to be passed from user space).
5344  *
5345  * The caller of this function needs to take a lock on dev_priv->drrs.
5346  */
5347 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5348 {
5349         struct drm_i915_private *dev_priv = dev->dev_private;
5350         struct intel_encoder *encoder;
5351         struct intel_digital_port *dig_port = NULL;
5352         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5353         struct intel_crtc_state *config = NULL;
5354         struct intel_crtc *intel_crtc = NULL;
5355         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5356
5357         if (refresh_rate <= 0) {
5358                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5359                 return;
5360         }
5361
5362         if (intel_dp == NULL) {
5363                 DRM_DEBUG_KMS("DRRS not supported.\n");
5364                 return;
5365         }
5366
5367         /*
5368          * FIXME: This needs proper synchronization with psr state for some
5369          * platforms that cannot have PSR and DRRS enabled at the same time.
5370          */
5371
5372         dig_port = dp_to_dig_port(intel_dp);
5373         encoder = &dig_port->base;
5374         intel_crtc = to_intel_crtc(encoder->base.crtc);
5375
5376         if (!intel_crtc) {
5377                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5378                 return;
5379         }
5380
5381         config = intel_crtc->config;
5382
5383         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5384                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5385                 return;
5386         }
5387
5388         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5389                         refresh_rate)
5390                 index = DRRS_LOW_RR;
5391
5392         if (index == dev_priv->drrs.refresh_rate_type) {
5393                 DRM_DEBUG_KMS(
5394                         "DRRS requested for previously set RR...ignoring\n");
5395                 return;
5396         }
5397
5398         if (!intel_crtc->active) {
5399                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5400                 return;
5401         }
5402
5403         if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
5404                 switch (index) {
5405                 case DRRS_HIGH_RR:
5406                         intel_dp_set_m_n(intel_crtc, M1_N1);
5407                         break;
5408                 case DRRS_LOW_RR:
5409                         intel_dp_set_m_n(intel_crtc, M2_N2);
5410                         break;
5411                 case DRRS_MAX_RR:
5412                 default:
5413                         DRM_ERROR("Unsupported refreshrate type\n");
5414                 }
5415         } else if (INTEL_INFO(dev)->gen > 6) {
5416                 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5417                 u32 val;
5418
5419                 val = I915_READ(reg);
5420                 if (index > DRRS_HIGH_RR) {
5421                         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5422                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5423                         else
5424                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5425                 } else {
5426                         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5427                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5428                         else
5429                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5430                 }
5431                 I915_WRITE(reg, val);
5432         }
5433
5434         dev_priv->drrs.refresh_rate_type = index;
5435
5436         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5437 }
5438
5439 /**
5440  * intel_edp_drrs_enable - init drrs struct if supported
5441  * @intel_dp: DP struct
5442  *
5443  * Initializes frontbuffer_bits and drrs.dp
5444  */
5445 void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5446 {
5447         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5448         struct drm_i915_private *dev_priv = dev->dev_private;
5449         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5450         struct drm_crtc *crtc = dig_port->base.base.crtc;
5451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5452
5453         if (!intel_crtc->config->has_drrs) {
5454                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5455                 return;
5456         }
5457
5458         mutex_lock(&dev_priv->drrs.mutex);
5459         if (WARN_ON(dev_priv->drrs.dp)) {
5460                 DRM_ERROR("DRRS already enabled\n");
5461                 goto unlock;
5462         }
5463
5464         dev_priv->drrs.busy_frontbuffer_bits = 0;
5465
5466         dev_priv->drrs.dp = intel_dp;
5467
5468 unlock:
5469         mutex_unlock(&dev_priv->drrs.mutex);
5470 }
5471
5472 /**
5473  * intel_edp_drrs_disable - Disable DRRS
5474  * @intel_dp: DP struct
5475  *
5476  */
5477 void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5478 {
5479         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5480         struct drm_i915_private *dev_priv = dev->dev_private;
5481         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5482         struct drm_crtc *crtc = dig_port->base.base.crtc;
5483         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5484
5485         if (!intel_crtc->config->has_drrs)
5486                 return;
5487
5488         mutex_lock(&dev_priv->drrs.mutex);
5489         if (!dev_priv->drrs.dp) {
5490                 mutex_unlock(&dev_priv->drrs.mutex);
5491                 return;
5492         }
5493
5494         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5495                 intel_dp_set_drrs_state(dev_priv->dev,
5496                         intel_dp->attached_connector->panel.
5497                         fixed_mode->vrefresh);
5498
5499         dev_priv->drrs.dp = NULL;
5500         mutex_unlock(&dev_priv->drrs.mutex);
5501
5502         cancel_delayed_work_sync(&dev_priv->drrs.work);
5503 }
5504
5505 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5506 {
5507         struct drm_i915_private *dev_priv =
5508                 container_of(work, typeof(*dev_priv), drrs.work.work);
5509         struct intel_dp *intel_dp;
5510
5511         mutex_lock(&dev_priv->drrs.mutex);
5512
5513         intel_dp = dev_priv->drrs.dp;
5514
5515         if (!intel_dp)
5516                 goto unlock;
5517
5518         /*
5519          * The delayed work can race with an invalidate hence we need to
5520          * recheck.
5521          */
5522
5523         if (dev_priv->drrs.busy_frontbuffer_bits)
5524                 goto unlock;
5525
5526         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5527                 intel_dp_set_drrs_state(dev_priv->dev,
5528                         intel_dp->attached_connector->panel.
5529                         downclock_mode->vrefresh);
5530
5531 unlock:
5532         mutex_unlock(&dev_priv->drrs.mutex);
5533 }
5534
5535 /**
5536  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5537  * @dev: DRM device
5538  * @frontbuffer_bits: frontbuffer plane tracking bits
5539  *
5540  * This function gets called everytime rendering on the given planes start.
5541  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5542  *
5543  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5544  */
5545 void intel_edp_drrs_invalidate(struct drm_device *dev,
5546                 unsigned frontbuffer_bits)
5547 {
5548         struct drm_i915_private *dev_priv = dev->dev_private;
5549         struct drm_crtc *crtc;
5550         enum pipe pipe;
5551
5552         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5553                 return;
5554
5555         cancel_delayed_work(&dev_priv->drrs.work);
5556
5557         mutex_lock(&dev_priv->drrs.mutex);
5558         if (!dev_priv->drrs.dp) {
5559                 mutex_unlock(&dev_priv->drrs.mutex);
5560                 return;
5561         }
5562
5563         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5564         pipe = to_intel_crtc(crtc)->pipe;
5565
5566         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5567         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5568
5569         /* invalidate means busy screen hence upclock */
5570         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5571                 intel_dp_set_drrs_state(dev_priv->dev,
5572                                 dev_priv->drrs.dp->attached_connector->panel.
5573                                 fixed_mode->vrefresh);
5574
5575         mutex_unlock(&dev_priv->drrs.mutex);
5576 }
5577
5578 /**
5579  * intel_edp_drrs_flush - Restart Idleness DRRS
5580  * @dev: DRM device
5581  * @frontbuffer_bits: frontbuffer plane tracking bits
5582  *
5583  * This function gets called every time rendering on the given planes has
5584  * completed or flip on a crtc is completed. So DRRS should be upclocked
5585  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5586  * if no other planes are dirty.
5587  *
5588  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5589  */
5590 void intel_edp_drrs_flush(struct drm_device *dev,
5591                 unsigned frontbuffer_bits)
5592 {
5593         struct drm_i915_private *dev_priv = dev->dev_private;
5594         struct drm_crtc *crtc;
5595         enum pipe pipe;
5596
5597         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5598                 return;
5599
5600         cancel_delayed_work(&dev_priv->drrs.work);
5601
5602         mutex_lock(&dev_priv->drrs.mutex);
5603         if (!dev_priv->drrs.dp) {
5604                 mutex_unlock(&dev_priv->drrs.mutex);
5605                 return;
5606         }
5607
5608         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5609         pipe = to_intel_crtc(crtc)->pipe;
5610
5611         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5612         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5613
5614         /* flush means busy screen hence upclock */
5615         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5616                 intel_dp_set_drrs_state(dev_priv->dev,
5617                                 dev_priv->drrs.dp->attached_connector->panel.
5618                                 fixed_mode->vrefresh);
5619
5620         /*
5621          * flush also means no more activity hence schedule downclock, if all
5622          * other fbs are quiescent too
5623          */
5624         if (!dev_priv->drrs.busy_frontbuffer_bits)
5625                 schedule_delayed_work(&dev_priv->drrs.work,
5626                                 msecs_to_jiffies(1000));
5627         mutex_unlock(&dev_priv->drrs.mutex);
5628 }
5629
5630 /**
5631  * DOC: Display Refresh Rate Switching (DRRS)
5632  *
5633  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5634  * which enables swtching between low and high refresh rates,
5635  * dynamically, based on the usage scenario. This feature is applicable
5636  * for internal panels.
5637  *
5638  * Indication that the panel supports DRRS is given by the panel EDID, which
5639  * would list multiple refresh rates for one resolution.
5640  *
5641  * DRRS is of 2 types - static and seamless.
5642  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5643  * (may appear as a blink on screen) and is used in dock-undock scenario.
5644  * Seamless DRRS involves changing RR without any visual effect to the user
5645  * and can be used during normal system usage. This is done by programming
5646  * certain registers.
5647  *
5648  * Support for static/seamless DRRS may be indicated in the VBT based on
5649  * inputs from the panel spec.
5650  *
5651  * DRRS saves power by switching to low RR based on usage scenarios.
5652  *
5653  * eDP DRRS:-
5654  *        The implementation is based on frontbuffer tracking implementation.
5655  * When there is a disturbance on the screen triggered by user activity or a
5656  * periodic system activity, DRRS is disabled (RR is changed to high RR).
5657  * When there is no movement on screen, after a timeout of 1 second, a switch
5658  * to low RR is made.
5659  *        For integration with frontbuffer tracking code,
5660  * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5661  *
5662  * DRRS can be further extended to support other internal panels and also
5663  * the scenario of video playback wherein RR is set based on the rate
5664  * requested by userspace.
5665  */
5666
5667 /**
5668  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5669  * @intel_connector: eDP connector
5670  * @fixed_mode: preferred mode of panel
5671  *
5672  * This function is  called only once at driver load to initialize basic
5673  * DRRS stuff.
5674  *
5675  * Returns:
5676  * Downclock mode if panel supports it, else return NULL.
5677  * DRRS support is determined by the presence of downclock mode (apart
5678  * from VBT setting).
5679  */
5680 static struct drm_display_mode *
5681 intel_dp_drrs_init(struct intel_connector *intel_connector,
5682                 struct drm_display_mode *fixed_mode)
5683 {
5684         struct drm_connector *connector = &intel_connector->base;
5685         struct drm_device *dev = connector->dev;
5686         struct drm_i915_private *dev_priv = dev->dev_private;
5687         struct drm_display_mode *downclock_mode = NULL;
5688
5689         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5690         mutex_init(&dev_priv->drrs.mutex);
5691
5692         if (INTEL_INFO(dev)->gen <= 6) {
5693                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5694                 return NULL;
5695         }
5696
5697         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5698                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5699                 return NULL;
5700         }
5701
5702         downclock_mode = intel_find_panel_downclock
5703                                         (dev, fixed_mode, connector);
5704
5705         if (!downclock_mode) {
5706                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5707                 return NULL;
5708         }
5709
5710         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5711
5712         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5713         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5714         return downclock_mode;
5715 }
5716
5717 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5718                                      struct intel_connector *intel_connector)
5719 {
5720         struct drm_connector *connector = &intel_connector->base;
5721         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5722         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5723         struct drm_device *dev = intel_encoder->base.dev;
5724         struct drm_i915_private *dev_priv = dev->dev_private;
5725         struct drm_display_mode *fixed_mode = NULL;
5726         struct drm_display_mode *downclock_mode = NULL;
5727         bool has_dpcd;
5728         struct drm_display_mode *scan;
5729         struct edid *edid;
5730         enum pipe pipe = INVALID_PIPE;
5731
5732         if (!is_edp(intel_dp))
5733                 return true;
5734
5735         pps_lock(intel_dp);
5736         intel_edp_panel_vdd_sanitize(intel_dp);
5737         pps_unlock(intel_dp);
5738
5739         /* Cache DPCD and EDID for edp. */
5740         has_dpcd = intel_dp_get_dpcd(intel_dp);
5741
5742         if (has_dpcd) {
5743                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5744                         dev_priv->no_aux_handshake =
5745                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5746                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5747         } else {
5748                 /* if this fails, presume the device is a ghost */
5749                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5750                 return false;
5751         }
5752
5753         /* We now know it's not a ghost, init power sequence regs. */
5754         pps_lock(intel_dp);
5755         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5756         pps_unlock(intel_dp);
5757
5758         mutex_lock(&dev->mode_config.mutex);
5759         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5760         if (edid) {
5761                 if (drm_add_edid_modes(connector, edid)) {
5762                         drm_mode_connector_update_edid_property(connector,
5763                                                                 edid);
5764                         drm_edid_to_eld(connector, edid);
5765                 } else {
5766                         kfree(edid);
5767                         edid = ERR_PTR(-EINVAL);
5768                 }
5769         } else {
5770                 edid = ERR_PTR(-ENOENT);
5771         }
5772         intel_connector->edid = edid;
5773
5774         /* prefer fixed mode from EDID if available */
5775         list_for_each_entry(scan, &connector->probed_modes, head) {
5776                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5777                         fixed_mode = drm_mode_duplicate(dev, scan);
5778                         downclock_mode = intel_dp_drrs_init(
5779                                                 intel_connector, fixed_mode);
5780                         break;
5781                 }
5782         }
5783
5784         /* fallback to VBT if available for eDP */
5785         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5786                 fixed_mode = drm_mode_duplicate(dev,
5787                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5788                 if (fixed_mode)
5789                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5790         }
5791         mutex_unlock(&dev->mode_config.mutex);
5792
5793         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5794                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5795                 register_reboot_notifier(&intel_dp->edp_notifier);
5796
5797                 /*
5798                  * Figure out the current pipe for the initial backlight setup.
5799                  * If the current pipe isn't valid, try the PPS pipe, and if that
5800                  * fails just assume pipe A.
5801                  */
5802                 if (IS_CHERRYVIEW(dev))
5803                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5804                 else
5805                         pipe = PORT_TO_PIPE(intel_dp->DP);
5806
5807                 if (pipe != PIPE_A && pipe != PIPE_B)
5808                         pipe = intel_dp->pps_pipe;
5809
5810                 if (pipe != PIPE_A && pipe != PIPE_B)
5811                         pipe = PIPE_A;
5812
5813                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5814                               pipe_name(pipe));
5815         }
5816
5817         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5818         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5819         intel_panel_setup_backlight(connector, pipe);
5820
5821         return true;
5822 }
5823
5824 bool
5825 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5826                         struct intel_connector *intel_connector)
5827 {
5828         struct drm_connector *connector = &intel_connector->base;
5829         struct intel_dp *intel_dp = &intel_dig_port->dp;
5830         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5831         struct drm_device *dev = intel_encoder->base.dev;
5832         struct drm_i915_private *dev_priv = dev->dev_private;
5833         enum port port = intel_dig_port->port;
5834         int type, ret;
5835
5836         if (WARN(intel_dig_port->max_lanes < 1,
5837                  "Not enough lanes (%d) for DP on port %c\n",
5838                  intel_dig_port->max_lanes, port_name(port)))
5839                 return false;
5840
5841         intel_dp->pps_pipe = INVALID_PIPE;
5842
5843         /* intel_dp vfuncs */
5844         if (INTEL_INFO(dev)->gen >= 9)
5845                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5846         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5847                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5848         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5849                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5850         else if (HAS_PCH_SPLIT(dev))
5851                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5852         else
5853                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5854
5855         if (INTEL_INFO(dev)->gen >= 9)
5856                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5857         else
5858                 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5859
5860         if (HAS_DDI(dev))
5861                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5862
5863         /* Preserve the current hw state. */
5864         intel_dp->DP = I915_READ(intel_dp->output_reg);
5865         intel_dp->attached_connector = intel_connector;
5866
5867         if (intel_dp_is_edp(dev, port))
5868                 type = DRM_MODE_CONNECTOR_eDP;
5869         else
5870                 type = DRM_MODE_CONNECTOR_DisplayPort;
5871
5872         /*
5873          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5874          * for DP the encoder type can be set by the caller to
5875          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5876          */
5877         if (type == DRM_MODE_CONNECTOR_eDP)
5878                 intel_encoder->type = INTEL_OUTPUT_EDP;
5879
5880         /* eDP only on port B and/or C on vlv/chv */
5881         if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5882                     is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5883                 return false;
5884
5885         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5886                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5887                         port_name(port));
5888
5889         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5890         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5891
5892         connector->interlace_allowed = true;
5893         connector->doublescan_allowed = 0;
5894
5895         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5896                           edp_panel_vdd_work);
5897
5898         intel_connector_attach_encoder(intel_connector, intel_encoder);
5899         drm_connector_register(connector);
5900
5901         if (HAS_DDI(dev))
5902                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5903         else
5904                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5905         intel_connector->unregister = intel_dp_connector_unregister;
5906
5907         /* Set up the hotplug pin. */
5908         switch (port) {
5909         case PORT_A:
5910                 intel_encoder->hpd_pin = HPD_PORT_A;
5911                 break;
5912         case PORT_B:
5913                 intel_encoder->hpd_pin = HPD_PORT_B;
5914                 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
5915                         intel_encoder->hpd_pin = HPD_PORT_A;
5916                 break;
5917         case PORT_C:
5918                 intel_encoder->hpd_pin = HPD_PORT_C;
5919                 break;
5920         case PORT_D:
5921                 intel_encoder->hpd_pin = HPD_PORT_D;
5922                 break;
5923         case PORT_E:
5924                 intel_encoder->hpd_pin = HPD_PORT_E;
5925                 break;
5926         default:
5927                 BUG();
5928         }
5929
5930         if (is_edp(intel_dp)) {
5931                 pps_lock(intel_dp);
5932                 intel_dp_init_panel_power_timestamps(intel_dp);
5933                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5934                         vlv_initial_power_sequencer_setup(intel_dp);
5935                 else
5936                         intel_dp_init_panel_power_sequencer(dev, intel_dp);
5937                 pps_unlock(intel_dp);
5938         }
5939
5940         ret = intel_dp_aux_init(intel_dp, intel_connector);
5941         if (ret)
5942                 goto fail;
5943
5944         /* init MST on ports that can support it */
5945         if (HAS_DP_MST(dev) &&
5946             (port == PORT_B || port == PORT_C || port == PORT_D))
5947                 intel_dp_mst_encoder_init(intel_dig_port,
5948                                           intel_connector->base.base.id);
5949
5950         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5951                 intel_dp_aux_fini(intel_dp);
5952                 intel_dp_mst_encoder_cleanup(intel_dig_port);
5953                 goto fail;
5954         }
5955
5956         intel_dp_add_properties(intel_dp, connector);
5957
5958         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5959          * 0xd.  Failure to do so will result in spurious interrupts being
5960          * generated on the port when a cable is not attached.
5961          */
5962         if (IS_G4X(dev) && !IS_GM45(dev)) {
5963                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5964                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5965         }
5966
5967         i915_debugfs_connector_add(connector);
5968
5969         return true;
5970
5971 fail:
5972         if (is_edp(intel_dp)) {
5973                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5974                 /*
5975                  * vdd might still be enabled do to the delayed vdd off.
5976                  * Make sure vdd is actually turned off here.
5977                  */
5978                 pps_lock(intel_dp);
5979                 edp_panel_vdd_off_sync(intel_dp);
5980                 pps_unlock(intel_dp);
5981         }
5982         drm_connector_unregister(connector);
5983         drm_connector_cleanup(connector);
5984
5985         return false;
5986 }
5987
5988 void
5989 intel_dp_init(struct drm_device *dev,
5990               i915_reg_t output_reg, enum port port)
5991 {
5992         struct drm_i915_private *dev_priv = dev->dev_private;
5993         struct intel_digital_port *intel_dig_port;
5994         struct intel_encoder *intel_encoder;
5995         struct drm_encoder *encoder;
5996         struct intel_connector *intel_connector;
5997
5998         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5999         if (!intel_dig_port)
6000                 return;
6001
6002         intel_connector = intel_connector_alloc();
6003         if (!intel_connector)
6004                 goto err_connector_alloc;
6005
6006         intel_encoder = &intel_dig_port->base;
6007         encoder = &intel_encoder->base;
6008
6009         if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
6010                              DRM_MODE_ENCODER_TMDS, NULL))
6011                 goto err_encoder_init;
6012
6013         intel_encoder->compute_config = intel_dp_compute_config;
6014         intel_encoder->disable = intel_disable_dp;
6015         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6016         intel_encoder->get_config = intel_dp_get_config;
6017         intel_encoder->suspend = intel_dp_encoder_suspend;
6018         if (IS_CHERRYVIEW(dev)) {
6019                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6020                 intel_encoder->pre_enable = chv_pre_enable_dp;
6021                 intel_encoder->enable = vlv_enable_dp;
6022                 intel_encoder->post_disable = chv_post_disable_dp;
6023                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6024         } else if (IS_VALLEYVIEW(dev)) {
6025                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6026                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6027                 intel_encoder->enable = vlv_enable_dp;
6028                 intel_encoder->post_disable = vlv_post_disable_dp;
6029         } else {
6030                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6031                 intel_encoder->enable = g4x_enable_dp;
6032                 if (INTEL_INFO(dev)->gen >= 5)
6033                         intel_encoder->post_disable = ilk_post_disable_dp;
6034         }
6035
6036         intel_dig_port->port = port;
6037         dev_priv->dig_port_map[port] = intel_encoder;
6038         intel_dig_port->dp.output_reg = output_reg;
6039         intel_dig_port->max_lanes = 4;
6040
6041         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
6042         if (IS_CHERRYVIEW(dev)) {
6043                 if (port == PORT_D)
6044                         intel_encoder->crtc_mask = 1 << 2;
6045                 else
6046                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6047         } else {
6048                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6049         }
6050         intel_encoder->cloneable = 0;
6051
6052         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6053         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6054
6055         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6056                 goto err_init_connector;
6057
6058         return;
6059
6060 err_init_connector:
6061         drm_encoder_cleanup(encoder);
6062 err_encoder_init:
6063         kfree(intel_connector);
6064 err_connector_alloc:
6065         kfree(intel_dig_port);
6066
6067         return;
6068 }
6069
6070 void intel_dp_mst_suspend(struct drm_device *dev)
6071 {
6072         struct drm_i915_private *dev_priv = dev->dev_private;
6073         int i;
6074
6075         /* disable MST */
6076         for (i = 0; i < I915_MAX_PORTS; i++) {
6077                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6078                 if (!intel_dig_port)
6079                         continue;
6080
6081                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6082                         if (!intel_dig_port->dp.can_mst)
6083                                 continue;
6084                         if (intel_dig_port->dp.is_mst)
6085                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6086                 }
6087         }
6088 }
6089
6090 void intel_dp_mst_resume(struct drm_device *dev)
6091 {
6092         struct drm_i915_private *dev_priv = dev->dev_private;
6093         int i;
6094
6095         for (i = 0; i < I915_MAX_PORTS; i++) {
6096                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6097                 if (!intel_dig_port)
6098                         continue;
6099                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6100                         int ret;
6101
6102                         if (!intel_dig_port->dp.can_mst)
6103                                 continue;
6104
6105                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6106                         if (ret != 0) {
6107                                 intel_dp_check_mst_status(&intel_dig_port->dp);
6108                         }
6109                 }
6110         }
6111 }