2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_edid.h>
40 #include "intel_drv.h"
41 #include <drm/i915_drm.h>
44 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 /* Compliance test status bits */
47 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
48 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
50 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
57 static const struct dp_link_dpll gen4_dpll[] = {
59 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
61 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
64 static const struct dp_link_dpll pch_dpll[] = {
66 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
68 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
71 static const struct dp_link_dpll vlv_dpll[] = {
73 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
75 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
79 * CHV supports eDP 1.4 that have more link rates.
80 * Below only provides the fixed rate but exclude variable rate.
82 static const struct dp_link_dpll chv_dpll[] = {
84 * CHV requires to program fractional division for m2.
85 * m2 is stored in fixed point format using formula below
86 * (m2_int << 22) | m2_fraction
88 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
89 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
90 { 270000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
92 { 540000, /* m2_int = 27, m2_fraction = 0 */
93 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
96 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
97 324000, 432000, 540000 };
98 static const int skl_rates[] = { 162000, 216000, 270000,
99 324000, 432000, 540000 };
100 static const int default_rates[] = { 162000, 270000, 540000 };
103 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
104 * @intel_dp: DP struct
106 * If a CPU or PCH DP output is attached to an eDP panel, this function
107 * will return true, and false otherwise.
109 static bool is_edp(struct intel_dp *intel_dp)
111 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
113 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
116 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
118 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
120 return intel_dig_port->base.base.dev;
123 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
125 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
128 static void intel_dp_link_down(struct intel_dp *intel_dp);
129 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
130 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
131 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
132 static void vlv_steal_power_sequencer(struct drm_device *dev,
134 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
137 intel_dp_max_link_bw(struct intel_dp *intel_dp)
139 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
141 switch (max_link_bw) {
142 case DP_LINK_BW_1_62:
147 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
149 max_link_bw = DP_LINK_BW_1_62;
155 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
157 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
158 u8 source_max, sink_max;
160 source_max = intel_dig_port->max_lanes;
161 sink_max = intel_dp->max_sink_lane_count;
163 return min(source_max, sink_max);
167 intel_dp_link_required(int pixel_clock, int bpp)
169 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
170 return DIV_ROUND_UP(pixel_clock * bpp, 8);
174 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
176 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
177 * link rate that is generally expressed in Gbps. Since, 8 bits of data
178 * is transmitted every LS_Clk per lane, there is no need to account for
179 * the channel encoding that is done in the PHY layer here.
182 return max_link_clock * max_lanes;
186 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
188 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
189 struct intel_encoder *encoder = &intel_dig_port->base;
190 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
191 int max_dotclk = dev_priv->max_dotclk_freq;
194 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
196 if (type != DP_DS_PORT_TYPE_VGA)
199 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
200 intel_dp->downstream_ports);
202 if (ds_max_dotclk != 0)
203 max_dotclk = min(max_dotclk, ds_max_dotclk);
209 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
211 if (intel_dp->num_sink_rates) {
212 *sink_rates = intel_dp->sink_rates;
213 return intel_dp->num_sink_rates;
216 *sink_rates = default_rates;
218 return (intel_dp->max_sink_link_bw >> 3) + 1;
222 intel_dp_set_source_rates(struct intel_dp *intel_dp)
224 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
225 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
226 const int *source_rates;
229 /* This should only be done once */
230 WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
232 if (IS_GEN9_LP(dev_priv)) {
233 source_rates = bxt_rates;
234 size = ARRAY_SIZE(bxt_rates);
235 } else if (IS_GEN9_BC(dev_priv)) {
236 source_rates = skl_rates;
237 size = ARRAY_SIZE(skl_rates);
239 source_rates = default_rates;
240 size = ARRAY_SIZE(default_rates);
243 /* This depends on the fact that 5.4 is last value in the array */
244 if (!intel_dp_source_supports_hbr2(intel_dp))
247 intel_dp->source_rates = source_rates;
248 intel_dp->num_source_rates = size;
251 static int intersect_rates(const int *source_rates, int source_len,
252 const int *sink_rates, int sink_len,
255 int i = 0, j = 0, k = 0;
257 while (i < source_len && j < sink_len) {
258 if (source_rates[i] == sink_rates[j]) {
259 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
261 common_rates[k] = source_rates[i];
265 } else if (source_rates[i] < sink_rates[j]) {
274 /* return index of rate in rates array, or -1 if not found */
275 static int intel_dp_rate_index(const int *rates, int len, int rate)
279 for (i = 0; i < len; i++)
280 if (rate == rates[i])
286 static int intel_dp_common_rates(struct intel_dp *intel_dp,
289 const int *sink_rates;
292 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
294 return intersect_rates(intel_dp->source_rates,
295 intel_dp->num_source_rates,
296 sink_rates, sink_len,
300 static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
301 int *common_rates, int link_rate)
305 common_len = intel_dp_common_rates(intel_dp, common_rates);
307 return intel_dp_rate_index(common_rates, common_len, link_rate);
310 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
311 int link_rate, uint8_t lane_count)
313 int common_rates[DP_MAX_SUPPORTED_RATES];
316 link_rate_index = intel_dp_link_rate_index(intel_dp,
319 if (link_rate_index > 0) {
320 intel_dp->max_sink_link_bw = drm_dp_link_rate_to_bw_code(common_rates[link_rate_index - 1]);
321 intel_dp->max_sink_lane_count = lane_count;
322 } else if (lane_count > 1) {
323 intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
324 intel_dp->max_sink_lane_count = lane_count >> 1;
326 DRM_ERROR("Link Training Unsuccessful\n");
333 static enum drm_mode_status
334 intel_dp_mode_valid(struct drm_connector *connector,
335 struct drm_display_mode *mode)
337 struct intel_dp *intel_dp = intel_attached_dp(connector);
338 struct intel_connector *intel_connector = to_intel_connector(connector);
339 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
340 int target_clock = mode->clock;
341 int max_rate, mode_rate, max_lanes, max_link_clock;
344 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
346 if (is_edp(intel_dp) && fixed_mode) {
347 if (mode->hdisplay > fixed_mode->hdisplay)
350 if (mode->vdisplay > fixed_mode->vdisplay)
353 target_clock = fixed_mode->clock;
356 max_link_clock = intel_dp_max_link_rate(intel_dp);
357 max_lanes = intel_dp_max_lane_count(intel_dp);
359 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
360 mode_rate = intel_dp_link_required(target_clock, 18);
362 if (mode_rate > max_rate || target_clock > max_dotclk)
363 return MODE_CLOCK_HIGH;
365 if (mode->clock < 10000)
366 return MODE_CLOCK_LOW;
368 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
369 return MODE_H_ILLEGAL;
374 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
381 for (i = 0; i < src_bytes; i++)
382 v |= ((uint32_t) src[i]) << ((3-i) * 8);
386 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
391 for (i = 0; i < dst_bytes; i++)
392 dst[i] = src >> ((3-i) * 8);
396 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
397 struct intel_dp *intel_dp);
399 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
400 struct intel_dp *intel_dp,
401 bool force_disable_vdd);
403 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
405 static void pps_lock(struct intel_dp *intel_dp)
407 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
408 struct intel_encoder *encoder = &intel_dig_port->base;
409 struct drm_device *dev = encoder->base.dev;
410 struct drm_i915_private *dev_priv = to_i915(dev);
413 * See vlv_power_sequencer_reset() why we need
414 * a power domain reference here.
416 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
418 mutex_lock(&dev_priv->pps_mutex);
421 static void pps_unlock(struct intel_dp *intel_dp)
423 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
424 struct intel_encoder *encoder = &intel_dig_port->base;
425 struct drm_device *dev = encoder->base.dev;
426 struct drm_i915_private *dev_priv = to_i915(dev);
428 mutex_unlock(&dev_priv->pps_mutex);
430 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
434 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
436 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
437 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
438 enum pipe pipe = intel_dp->pps_pipe;
439 bool pll_enabled, release_cl_override = false;
440 enum dpio_phy phy = DPIO_PHY(pipe);
441 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
444 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
445 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
446 pipe_name(pipe), port_name(intel_dig_port->port)))
449 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
450 pipe_name(pipe), port_name(intel_dig_port->port));
452 /* Preserve the BIOS-computed detected bit. This is
453 * supposed to be read-only.
455 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
456 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
457 DP |= DP_PORT_WIDTH(1);
458 DP |= DP_LINK_TRAIN_PAT_1;
460 if (IS_CHERRYVIEW(dev_priv))
461 DP |= DP_PIPE_SELECT_CHV(pipe);
462 else if (pipe == PIPE_B)
463 DP |= DP_PIPEB_SELECT;
465 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
468 * The DPLL for the pipe must be enabled for this to work.
469 * So enable temporarily it if it's not already enabled.
472 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
473 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
475 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
476 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
477 DRM_ERROR("Failed to force on pll for pipe %c!\n",
484 * Similar magic as in intel_dp_enable_port().
485 * We _must_ do this port enable + disable trick
486 * to make this power seqeuencer lock onto the port.
487 * Otherwise even VDD force bit won't work.
489 I915_WRITE(intel_dp->output_reg, DP);
490 POSTING_READ(intel_dp->output_reg);
492 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
493 POSTING_READ(intel_dp->output_reg);
495 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
496 POSTING_READ(intel_dp->output_reg);
499 vlv_force_pll_off(dev_priv, pipe);
501 if (release_cl_override)
502 chv_phy_powergate_ch(dev_priv, phy, ch, false);
506 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
508 struct intel_encoder *encoder;
509 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
512 * We don't have power sequencer currently.
513 * Pick one that's not used by other ports.
515 for_each_intel_encoder(&dev_priv->drm, encoder) {
516 struct intel_dp *intel_dp;
518 if (encoder->type != INTEL_OUTPUT_DP &&
519 encoder->type != INTEL_OUTPUT_EDP)
522 intel_dp = enc_to_intel_dp(&encoder->base);
524 if (encoder->type == INTEL_OUTPUT_EDP) {
525 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
526 intel_dp->active_pipe != intel_dp->pps_pipe);
528 if (intel_dp->pps_pipe != INVALID_PIPE)
529 pipes &= ~(1 << intel_dp->pps_pipe);
531 WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
533 if (intel_dp->active_pipe != INVALID_PIPE)
534 pipes &= ~(1 << intel_dp->active_pipe);
541 return ffs(pipes) - 1;
545 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
547 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
548 struct drm_device *dev = intel_dig_port->base.base.dev;
549 struct drm_i915_private *dev_priv = to_i915(dev);
552 lockdep_assert_held(&dev_priv->pps_mutex);
554 /* We should never land here with regular DP ports */
555 WARN_ON(!is_edp(intel_dp));
557 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
558 intel_dp->active_pipe != intel_dp->pps_pipe);
560 if (intel_dp->pps_pipe != INVALID_PIPE)
561 return intel_dp->pps_pipe;
563 pipe = vlv_find_free_pps(dev_priv);
566 * Didn't find one. This should not happen since there
567 * are two power sequencers and up to two eDP ports.
569 if (WARN_ON(pipe == INVALID_PIPE))
572 vlv_steal_power_sequencer(dev, pipe);
573 intel_dp->pps_pipe = pipe;
575 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
576 pipe_name(intel_dp->pps_pipe),
577 port_name(intel_dig_port->port));
579 /* init power sequencer on this pipe and port */
580 intel_dp_init_panel_power_sequencer(dev, intel_dp);
581 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
584 * Even vdd force doesn't work until we've made
585 * the power sequencer lock in on the port.
587 vlv_power_sequencer_kick(intel_dp);
589 return intel_dp->pps_pipe;
593 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
595 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
596 struct drm_device *dev = intel_dig_port->base.base.dev;
597 struct drm_i915_private *dev_priv = to_i915(dev);
599 lockdep_assert_held(&dev_priv->pps_mutex);
601 /* We should never land here with regular DP ports */
602 WARN_ON(!is_edp(intel_dp));
605 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
606 * mapping needs to be retrieved from VBT, for now just hard-code to
607 * use instance #0 always.
609 if (!intel_dp->pps_reset)
612 intel_dp->pps_reset = false;
615 * Only the HW needs to be reprogrammed, the SW state is fixed and
616 * has been setup during connector init.
618 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
623 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
626 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
629 return I915_READ(PP_STATUS(pipe)) & PP_ON;
632 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
635 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
638 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
645 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
647 vlv_pipe_check pipe_check)
651 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
652 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
653 PANEL_PORT_SELECT_MASK;
655 if (port_sel != PANEL_PORT_SELECT_VLV(port))
658 if (!pipe_check(dev_priv, pipe))
668 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
670 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
671 struct drm_device *dev = intel_dig_port->base.base.dev;
672 struct drm_i915_private *dev_priv = to_i915(dev);
673 enum port port = intel_dig_port->port;
675 lockdep_assert_held(&dev_priv->pps_mutex);
677 /* try to find a pipe with this port selected */
678 /* first pick one where the panel is on */
679 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
681 /* didn't find one? pick one where vdd is on */
682 if (intel_dp->pps_pipe == INVALID_PIPE)
683 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
684 vlv_pipe_has_vdd_on);
685 /* didn't find one? pick one with just the correct port */
686 if (intel_dp->pps_pipe == INVALID_PIPE)
687 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
690 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
691 if (intel_dp->pps_pipe == INVALID_PIPE) {
692 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
697 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
698 port_name(port), pipe_name(intel_dp->pps_pipe));
700 intel_dp_init_panel_power_sequencer(dev, intel_dp);
701 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
704 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
706 struct drm_device *dev = &dev_priv->drm;
707 struct intel_encoder *encoder;
709 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
710 !IS_GEN9_LP(dev_priv)))
714 * We can't grab pps_mutex here due to deadlock with power_domain
715 * mutex when power_domain functions are called while holding pps_mutex.
716 * That also means that in order to use pps_pipe the code needs to
717 * hold both a power domain reference and pps_mutex, and the power domain
718 * reference get/put must be done while _not_ holding pps_mutex.
719 * pps_{lock,unlock}() do these steps in the correct order, so one
720 * should use them always.
723 for_each_intel_encoder(dev, encoder) {
724 struct intel_dp *intel_dp;
726 if (encoder->type != INTEL_OUTPUT_DP &&
727 encoder->type != INTEL_OUTPUT_EDP)
730 intel_dp = enc_to_intel_dp(&encoder->base);
732 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
734 if (encoder->type != INTEL_OUTPUT_EDP)
737 if (IS_GEN9_LP(dev_priv))
738 intel_dp->pps_reset = true;
740 intel_dp->pps_pipe = INVALID_PIPE;
744 struct pps_registers {
752 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
753 struct intel_dp *intel_dp,
754 struct pps_registers *regs)
758 memset(regs, 0, sizeof(*regs));
760 if (IS_GEN9_LP(dev_priv))
761 pps_idx = bxt_power_sequencer_idx(intel_dp);
762 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
763 pps_idx = vlv_power_sequencer_pipe(intel_dp);
765 regs->pp_ctrl = PP_CONTROL(pps_idx);
766 regs->pp_stat = PP_STATUS(pps_idx);
767 regs->pp_on = PP_ON_DELAYS(pps_idx);
768 regs->pp_off = PP_OFF_DELAYS(pps_idx);
769 if (!IS_GEN9_LP(dev_priv))
770 regs->pp_div = PP_DIVISOR(pps_idx);
774 _pp_ctrl_reg(struct intel_dp *intel_dp)
776 struct pps_registers regs;
778 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
785 _pp_stat_reg(struct intel_dp *intel_dp)
787 struct pps_registers regs;
789 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
795 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
796 This function only applicable when panel PM state is not to be tracked */
797 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
800 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
802 struct drm_device *dev = intel_dp_to_dev(intel_dp);
803 struct drm_i915_private *dev_priv = to_i915(dev);
805 if (!is_edp(intel_dp) || code != SYS_RESTART)
810 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
811 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
812 i915_reg_t pp_ctrl_reg, pp_div_reg;
815 pp_ctrl_reg = PP_CONTROL(pipe);
816 pp_div_reg = PP_DIVISOR(pipe);
817 pp_div = I915_READ(pp_div_reg);
818 pp_div &= PP_REFERENCE_DIVIDER_MASK;
820 /* 0x1F write to PP_DIV_REG sets max cycle delay */
821 I915_WRITE(pp_div_reg, pp_div | 0x1F);
822 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
823 msleep(intel_dp->panel_power_cycle_delay);
826 pps_unlock(intel_dp);
831 static bool edp_have_panel_power(struct intel_dp *intel_dp)
833 struct drm_device *dev = intel_dp_to_dev(intel_dp);
834 struct drm_i915_private *dev_priv = to_i915(dev);
836 lockdep_assert_held(&dev_priv->pps_mutex);
838 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
839 intel_dp->pps_pipe == INVALID_PIPE)
842 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
845 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
847 struct drm_device *dev = intel_dp_to_dev(intel_dp);
848 struct drm_i915_private *dev_priv = to_i915(dev);
850 lockdep_assert_held(&dev_priv->pps_mutex);
852 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
853 intel_dp->pps_pipe == INVALID_PIPE)
856 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
860 intel_dp_check_edp(struct intel_dp *intel_dp)
862 struct drm_device *dev = intel_dp_to_dev(intel_dp);
863 struct drm_i915_private *dev_priv = to_i915(dev);
865 if (!is_edp(intel_dp))
868 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
869 WARN(1, "eDP powered off while attempting aux channel communication.\n");
870 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
871 I915_READ(_pp_stat_reg(intel_dp)),
872 I915_READ(_pp_ctrl_reg(intel_dp)));
877 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
879 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
880 struct drm_device *dev = intel_dig_port->base.base.dev;
881 struct drm_i915_private *dev_priv = to_i915(dev);
882 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
886 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
888 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
889 msecs_to_jiffies_timeout(10));
891 done = wait_for(C, 10) == 0;
893 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
900 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
902 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
903 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
909 * The clock divider is based off the hrawclk, and would like to run at
910 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
912 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
915 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
917 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
918 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
924 * The clock divider is based off the cdclk or PCH rawclk, and would
925 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
926 * divide by 2000 and use that
928 if (intel_dig_port->port == PORT_A)
929 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
931 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
934 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
936 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
937 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
939 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
940 /* Workaround for non-ULT HSW */
948 return ilk_get_aux_clock_divider(intel_dp, index);
951 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
954 * SKL doesn't need us to program the AUX clock divider (Hardware will
955 * derive the clock from CDCLK automatically). We still implement the
956 * get_aux_clock_divider vfunc to plug-in into the existing code.
958 return index ? 0 : 1;
961 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
964 uint32_t aux_clock_divider)
966 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
967 struct drm_i915_private *dev_priv =
968 to_i915(intel_dig_port->base.base.dev);
969 uint32_t precharge, timeout;
971 if (IS_GEN6(dev_priv))
976 if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
977 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
979 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
981 return DP_AUX_CH_CTL_SEND_BUSY |
983 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
984 DP_AUX_CH_CTL_TIME_OUT_ERROR |
986 DP_AUX_CH_CTL_RECEIVE_ERROR |
987 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
988 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
989 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
992 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
997 return DP_AUX_CH_CTL_SEND_BUSY |
999 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1000 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1001 DP_AUX_CH_CTL_TIME_OUT_1600us |
1002 DP_AUX_CH_CTL_RECEIVE_ERROR |
1003 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1004 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1005 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1009 intel_dp_aux_ch(struct intel_dp *intel_dp,
1010 const uint8_t *send, int send_bytes,
1011 uint8_t *recv, int recv_size)
1013 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1014 struct drm_i915_private *dev_priv =
1015 to_i915(intel_dig_port->base.base.dev);
1016 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1017 uint32_t aux_clock_divider;
1018 int i, ret, recv_bytes;
1021 bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1027 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1028 * In such cases we want to leave VDD enabled and it's up to upper layers
1029 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1032 vdd = edp_panel_vdd_on(intel_dp);
1034 /* dp aux is extremely sensitive to irq latency, hence request the
1035 * lowest possible wakeup latency and so prevent the cpu from going into
1036 * deep sleep states.
1038 pm_qos_update_request(&dev_priv->pm_qos, 0);
1040 intel_dp_check_edp(intel_dp);
1042 /* Try to wait for any previous AUX channel activity */
1043 for (try = 0; try < 3; try++) {
1044 status = I915_READ_NOTRACE(ch_ctl);
1045 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1051 static u32 last_status = -1;
1052 const u32 status = I915_READ(ch_ctl);
1054 if (status != last_status) {
1055 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1057 last_status = status;
1064 /* Only 5 data registers! */
1065 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1070 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1071 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1076 /* Must try at least 3 times according to DP spec */
1077 for (try = 0; try < 5; try++) {
1078 /* Load the send data into the aux channel data registers */
1079 for (i = 0; i < send_bytes; i += 4)
1080 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1081 intel_dp_pack_aux(send + i,
1084 /* Send the command and wait for it to complete */
1085 I915_WRITE(ch_ctl, send_ctl);
1087 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1089 /* Clear done status and any errors */
1092 DP_AUX_CH_CTL_DONE |
1093 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1094 DP_AUX_CH_CTL_RECEIVE_ERROR);
1096 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1099 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1100 * 400us delay required for errors and timeouts
1101 * Timeout errors from the HW already meet this
1102 * requirement so skip to next iteration
1104 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1105 usleep_range(400, 500);
1108 if (status & DP_AUX_CH_CTL_DONE)
1113 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1114 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1120 /* Check for timeout or receive error.
1121 * Timeouts occur when the sink is not connected
1123 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1124 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1129 /* Timeouts occur when the device isn't connected, so they're
1130 * "normal" -- don't fill the kernel log with these */
1131 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1132 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1137 /* Unload any bytes sent back from the other side */
1138 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1139 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1142 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1143 * We have no idea of what happened so we return -EBUSY so
1144 * drm layer takes care for the necessary retries.
1146 if (recv_bytes == 0 || recv_bytes > 20) {
1147 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1150 * FIXME: This patch was created on top of a series that
1151 * organize the retries at drm level. There EBUSY should
1152 * also take care for 1ms wait before retrying.
1153 * That aux retries re-org is still needed and after that is
1154 * merged we remove this sleep from here.
1156 usleep_range(1000, 1500);
1161 if (recv_bytes > recv_size)
1162 recv_bytes = recv_size;
1164 for (i = 0; i < recv_bytes; i += 4)
1165 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1166 recv + i, recv_bytes - i);
1170 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1173 edp_panel_vdd_off(intel_dp, false);
1175 pps_unlock(intel_dp);
1180 #define BARE_ADDRESS_SIZE 3
1181 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1183 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1185 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1186 uint8_t txbuf[20], rxbuf[20];
1187 size_t txsize, rxsize;
1190 txbuf[0] = (msg->request << 4) |
1191 ((msg->address >> 16) & 0xf);
1192 txbuf[1] = (msg->address >> 8) & 0xff;
1193 txbuf[2] = msg->address & 0xff;
1194 txbuf[3] = msg->size - 1;
1196 switch (msg->request & ~DP_AUX_I2C_MOT) {
1197 case DP_AUX_NATIVE_WRITE:
1198 case DP_AUX_I2C_WRITE:
1199 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1200 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1201 rxsize = 2; /* 0 or 1 data bytes */
1203 if (WARN_ON(txsize > 20))
1206 WARN_ON(!msg->buffer != !msg->size);
1209 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1211 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1213 msg->reply = rxbuf[0] >> 4;
1216 /* Number of bytes written in a short write. */
1217 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1219 /* Return payload size. */
1225 case DP_AUX_NATIVE_READ:
1226 case DP_AUX_I2C_READ:
1227 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1228 rxsize = msg->size + 1;
1230 if (WARN_ON(rxsize > 20))
1233 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1235 msg->reply = rxbuf[0] >> 4;
1237 * Assume happy day, and copy the data. The caller is
1238 * expected to check msg->reply before touching it.
1240 * Return payload size.
1243 memcpy(msg->buffer, rxbuf + 1, ret);
1255 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1258 const struct ddi_vbt_port_info *info =
1259 &dev_priv->vbt.ddi_port_info[port];
1262 if (!info->alternate_aux_channel) {
1263 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1264 port_name(port), port_name(port));
1268 switch (info->alternate_aux_channel) {
1282 MISSING_CASE(info->alternate_aux_channel);
1287 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1288 port_name(aux_port), port_name(port));
1293 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1300 return DP_AUX_CH_CTL(port);
1303 return DP_AUX_CH_CTL(PORT_B);
1307 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1308 enum port port, int index)
1314 return DP_AUX_CH_DATA(port, index);
1317 return DP_AUX_CH_DATA(PORT_B, index);
1321 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1326 return DP_AUX_CH_CTL(port);
1330 return PCH_DP_AUX_CH_CTL(port);
1333 return DP_AUX_CH_CTL(PORT_A);
1337 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1338 enum port port, int index)
1342 return DP_AUX_CH_DATA(port, index);
1346 return PCH_DP_AUX_CH_DATA(port, index);
1349 return DP_AUX_CH_DATA(PORT_A, index);
1353 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1361 return DP_AUX_CH_CTL(port);
1364 return DP_AUX_CH_CTL(PORT_A);
1368 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1369 enum port port, int index)
1376 return DP_AUX_CH_DATA(port, index);
1379 return DP_AUX_CH_DATA(PORT_A, index);
1383 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1386 if (INTEL_INFO(dev_priv)->gen >= 9)
1387 return skl_aux_ctl_reg(dev_priv, port);
1388 else if (HAS_PCH_SPLIT(dev_priv))
1389 return ilk_aux_ctl_reg(dev_priv, port);
1391 return g4x_aux_ctl_reg(dev_priv, port);
1394 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1395 enum port port, int index)
1397 if (INTEL_INFO(dev_priv)->gen >= 9)
1398 return skl_aux_data_reg(dev_priv, port, index);
1399 else if (HAS_PCH_SPLIT(dev_priv))
1400 return ilk_aux_data_reg(dev_priv, port, index);
1402 return g4x_aux_data_reg(dev_priv, port, index);
1405 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1407 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1408 enum port port = intel_aux_port(dev_priv,
1409 dp_to_dig_port(intel_dp)->port);
1412 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1413 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1414 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1418 intel_dp_aux_fini(struct intel_dp *intel_dp)
1420 kfree(intel_dp->aux.name);
1424 intel_dp_aux_init(struct intel_dp *intel_dp)
1426 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1427 enum port port = intel_dig_port->port;
1429 intel_aux_reg_init(intel_dp);
1430 drm_dp_aux_init(&intel_dp->aux);
1432 /* Failure to allocate our preferred name is not critical */
1433 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1434 intel_dp->aux.transfer = intel_dp_aux_transfer;
1437 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1439 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1440 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1442 if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1443 IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
1450 intel_dp_set_clock(struct intel_encoder *encoder,
1451 struct intel_crtc_state *pipe_config)
1453 struct drm_device *dev = encoder->base.dev;
1454 struct drm_i915_private *dev_priv = to_i915(dev);
1455 const struct dp_link_dpll *divisor = NULL;
1458 if (IS_G4X(dev_priv)) {
1459 divisor = gen4_dpll;
1460 count = ARRAY_SIZE(gen4_dpll);
1461 } else if (HAS_PCH_SPLIT(dev_priv)) {
1463 count = ARRAY_SIZE(pch_dpll);
1464 } else if (IS_CHERRYVIEW(dev_priv)) {
1466 count = ARRAY_SIZE(chv_dpll);
1467 } else if (IS_VALLEYVIEW(dev_priv)) {
1469 count = ARRAY_SIZE(vlv_dpll);
1472 if (divisor && count) {
1473 for (i = 0; i < count; i++) {
1474 if (pipe_config->port_clock == divisor[i].clock) {
1475 pipe_config->dpll = divisor[i].dpll;
1476 pipe_config->clock_set = true;
1483 static void snprintf_int_array(char *str, size_t len,
1484 const int *array, int nelem)
1490 for (i = 0; i < nelem; i++) {
1491 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1499 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1501 const int *sink_rates;
1502 int sink_len, common_len;
1503 int common_rates[DP_MAX_SUPPORTED_RATES];
1504 char str[128]; /* FIXME: too big for stack? */
1506 if ((drm_debug & DRM_UT_KMS) == 0)
1509 snprintf_int_array(str, sizeof(str),
1510 intel_dp->source_rates, intel_dp->num_source_rates);
1511 DRM_DEBUG_KMS("source rates: %s\n", str);
1513 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1514 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1515 DRM_DEBUG_KMS("sink rates: %s\n", str);
1517 common_len = intel_dp_common_rates(intel_dp, common_rates);
1518 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1519 DRM_DEBUG_KMS("common rates: %s\n", str);
1523 __intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc)
1525 u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI :
1528 return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) ==
1532 bool intel_dp_read_desc(struct intel_dp *intel_dp)
1534 struct intel_dp_desc *desc = &intel_dp->desc;
1535 bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] &
1539 if (!__intel_dp_read_desc(intel_dp, desc))
1542 dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id));
1543 DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n",
1544 drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink",
1545 (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)",
1546 dev_id_len, desc->device_id,
1547 desc->hw_rev >> 4, desc->hw_rev & 0xf,
1548 desc->sw_major_rev, desc->sw_minor_rev);
1554 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1556 int rates[DP_MAX_SUPPORTED_RATES] = {};
1559 len = intel_dp_common_rates(intel_dp, rates);
1560 if (WARN_ON(len <= 0))
1563 return rates[len - 1];
1566 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1568 int i = intel_dp_rate_index(intel_dp->sink_rates,
1569 intel_dp->num_sink_rates, rate);
1577 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1578 uint8_t *link_bw, uint8_t *rate_select)
1580 if (intel_dp->num_sink_rates) {
1583 intel_dp_rate_select(intel_dp, port_clock);
1585 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1590 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1591 struct intel_crtc_state *pipe_config)
1595 bpp = pipe_config->pipe_bpp;
1596 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1599 bpp = min(bpp, 3*bpc);
1601 /* For DP Compliance we override the computed bpp for the pipe */
1602 if (intel_dp->compliance.test_data.bpc != 0) {
1603 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
1604 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
1605 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1606 pipe_config->pipe_bpp);
1612 intel_dp_compute_config(struct intel_encoder *encoder,
1613 struct intel_crtc_state *pipe_config,
1614 struct drm_connector_state *conn_state)
1616 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1617 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1618 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1619 enum port port = dp_to_dig_port(intel_dp)->port;
1620 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1621 struct intel_connector *intel_connector = intel_dp->attached_connector;
1622 int lane_count, clock;
1623 int min_lane_count = 1;
1624 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1625 /* Conveniently, the link BW constants become indices with a shift...*/
1628 int link_rate_index;
1630 int link_avail, link_clock;
1631 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1633 uint8_t link_bw, rate_select;
1635 common_len = intel_dp_common_rates(intel_dp, common_rates);
1637 /* No common link rates between source and sink */
1638 WARN_ON(common_len <= 0);
1640 max_clock = common_len - 1;
1642 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1643 pipe_config->has_pch_encoder = true;
1645 pipe_config->has_drrs = false;
1646 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1648 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1649 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1652 if (INTEL_GEN(dev_priv) >= 9) {
1654 ret = skl_update_scaler_crtc(pipe_config);
1659 if (HAS_GMCH_DISPLAY(dev_priv))
1660 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1661 intel_connector->panel.fitting_mode);
1663 intel_pch_panel_fitting(intel_crtc, pipe_config,
1664 intel_connector->panel.fitting_mode);
1667 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1670 /* Use values requested by Compliance Test Request */
1671 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1672 link_rate_index = intel_dp_link_rate_index(intel_dp,
1674 intel_dp->compliance.test_link_rate);
1675 if (link_rate_index >= 0)
1676 min_clock = max_clock = link_rate_index;
1677 min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
1679 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1680 "max bw %d pixel clock %iKHz\n",
1681 max_lane_count, common_rates[max_clock],
1682 adjusted_mode->crtc_clock);
1684 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1685 * bpc in between. */
1686 bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1687 if (is_edp(intel_dp)) {
1689 /* Get bpp from vbt only for panels that dont have bpp in edid */
1690 if (intel_connector->base.display_info.bpc == 0 &&
1691 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1692 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1693 dev_priv->vbt.edp.bpp);
1694 bpp = dev_priv->vbt.edp.bpp;
1698 * Use the maximum clock and number of lanes the eDP panel
1699 * advertizes being capable of. The panels are generally
1700 * designed to support only a single clock and lane
1701 * configuration, and typically these values correspond to the
1702 * native resolution of the panel.
1704 min_lane_count = max_lane_count;
1705 min_clock = max_clock;
1708 for (; bpp >= 6*3; bpp -= 2*3) {
1709 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1712 for (clock = min_clock; clock <= max_clock; clock++) {
1713 for (lane_count = min_lane_count;
1714 lane_count <= max_lane_count;
1717 link_clock = common_rates[clock];
1718 link_avail = intel_dp_max_data_rate(link_clock,
1721 if (mode_rate <= link_avail) {
1731 if (intel_dp->color_range_auto) {
1734 * CEA-861-E - 5.1 Default Encoding Parameters
1735 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1737 pipe_config->limited_color_range =
1739 drm_default_rgb_quant_range(adjusted_mode) ==
1740 HDMI_QUANTIZATION_RANGE_LIMITED;
1742 pipe_config->limited_color_range =
1743 intel_dp->limited_color_range;
1746 pipe_config->lane_count = lane_count;
1748 pipe_config->pipe_bpp = bpp;
1749 pipe_config->port_clock = common_rates[clock];
1751 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1752 &link_bw, &rate_select);
1754 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1755 link_bw, rate_select, pipe_config->lane_count,
1756 pipe_config->port_clock, bpp);
1757 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1758 mode_rate, link_avail);
1760 intel_link_compute_m_n(bpp, lane_count,
1761 adjusted_mode->crtc_clock,
1762 pipe_config->port_clock,
1763 &pipe_config->dp_m_n);
1765 if (intel_connector->panel.downclock_mode != NULL &&
1766 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1767 pipe_config->has_drrs = true;
1768 intel_link_compute_m_n(bpp, lane_count,
1769 intel_connector->panel.downclock_mode->clock,
1770 pipe_config->port_clock,
1771 &pipe_config->dp_m2_n2);
1775 * DPLL0 VCO may need to be adjusted to get the correct
1776 * clock for eDP. This will affect cdclk as well.
1778 if (is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1781 switch (pipe_config->port_clock / 2) {
1791 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1794 if (!HAS_DDI(dev_priv))
1795 intel_dp_set_clock(encoder, pipe_config);
1800 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1801 int link_rate, uint8_t lane_count,
1804 intel_dp->link_rate = link_rate;
1805 intel_dp->lane_count = lane_count;
1806 intel_dp->link_mst = link_mst;
1809 static void intel_dp_prepare(struct intel_encoder *encoder,
1810 struct intel_crtc_state *pipe_config)
1812 struct drm_device *dev = encoder->base.dev;
1813 struct drm_i915_private *dev_priv = to_i915(dev);
1814 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1815 enum port port = dp_to_dig_port(intel_dp)->port;
1816 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1817 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1819 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1820 pipe_config->lane_count,
1821 intel_crtc_has_type(pipe_config,
1822 INTEL_OUTPUT_DP_MST));
1825 * There are four kinds of DP registers:
1832 * IBX PCH and CPU are the same for almost everything,
1833 * except that the CPU DP PLL is configured in this
1836 * CPT PCH is quite different, having many bits moved
1837 * to the TRANS_DP_CTL register instead. That
1838 * configuration happens (oddly) in ironlake_pch_enable
1841 /* Preserve the BIOS-computed detected bit. This is
1842 * supposed to be read-only.
1844 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1846 /* Handle DP bits in common between all three register formats */
1847 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1848 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1850 /* Split out the IBX/CPU vs CPT settings */
1852 if (IS_GEN7(dev_priv) && port == PORT_A) {
1853 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1854 intel_dp->DP |= DP_SYNC_HS_HIGH;
1855 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1856 intel_dp->DP |= DP_SYNC_VS_HIGH;
1857 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1859 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1860 intel_dp->DP |= DP_ENHANCED_FRAMING;
1862 intel_dp->DP |= crtc->pipe << 29;
1863 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1866 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1868 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1869 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1870 trans_dp |= TRANS_DP_ENH_FRAMING;
1872 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1873 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1875 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1876 intel_dp->DP |= DP_COLOR_RANGE_16_235;
1878 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1879 intel_dp->DP |= DP_SYNC_HS_HIGH;
1880 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1881 intel_dp->DP |= DP_SYNC_VS_HIGH;
1882 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1884 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1885 intel_dp->DP |= DP_ENHANCED_FRAMING;
1887 if (IS_CHERRYVIEW(dev_priv))
1888 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1889 else if (crtc->pipe == PIPE_B)
1890 intel_dp->DP |= DP_PIPEB_SELECT;
1894 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1895 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1897 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1898 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1900 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1901 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1903 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1904 struct intel_dp *intel_dp);
1906 static void wait_panel_status(struct intel_dp *intel_dp,
1910 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1911 struct drm_i915_private *dev_priv = to_i915(dev);
1912 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1914 lockdep_assert_held(&dev_priv->pps_mutex);
1916 intel_pps_verify_state(dev_priv, intel_dp);
1918 pp_stat_reg = _pp_stat_reg(intel_dp);
1919 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1921 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1923 I915_READ(pp_stat_reg),
1924 I915_READ(pp_ctrl_reg));
1926 if (intel_wait_for_register(dev_priv,
1927 pp_stat_reg, mask, value,
1929 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1930 I915_READ(pp_stat_reg),
1931 I915_READ(pp_ctrl_reg));
1933 DRM_DEBUG_KMS("Wait complete\n");
1936 static void wait_panel_on(struct intel_dp *intel_dp)
1938 DRM_DEBUG_KMS("Wait for panel power on\n");
1939 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1942 static void wait_panel_off(struct intel_dp *intel_dp)
1944 DRM_DEBUG_KMS("Wait for panel power off time\n");
1945 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1948 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1950 ktime_t panel_power_on_time;
1951 s64 panel_power_off_duration;
1953 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1955 /* take the difference of currrent time and panel power off time
1956 * and then make panel wait for t11_t12 if needed. */
1957 panel_power_on_time = ktime_get_boottime();
1958 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1960 /* When we disable the VDD override bit last we have to do the manual
1962 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1963 wait_remaining_ms_from_jiffies(jiffies,
1964 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1966 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1969 static void wait_backlight_on(struct intel_dp *intel_dp)
1971 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1972 intel_dp->backlight_on_delay);
1975 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1977 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1978 intel_dp->backlight_off_delay);
1981 /* Read the current pp_control value, unlocking the register if it
1985 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1987 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1988 struct drm_i915_private *dev_priv = to_i915(dev);
1991 lockdep_assert_held(&dev_priv->pps_mutex);
1993 control = I915_READ(_pp_ctrl_reg(intel_dp));
1994 if (WARN_ON(!HAS_DDI(dev_priv) &&
1995 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
1996 control &= ~PANEL_UNLOCK_MASK;
1997 control |= PANEL_UNLOCK_REGS;
2003 * Must be paired with edp_panel_vdd_off().
2004 * Must hold pps_mutex around the whole on/off sequence.
2005 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2007 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2009 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2010 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2011 struct drm_i915_private *dev_priv = to_i915(dev);
2013 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2014 bool need_to_disable = !intel_dp->want_panel_vdd;
2016 lockdep_assert_held(&dev_priv->pps_mutex);
2018 if (!is_edp(intel_dp))
2021 cancel_delayed_work(&intel_dp->panel_vdd_work);
2022 intel_dp->want_panel_vdd = true;
2024 if (edp_have_panel_vdd(intel_dp))
2025 return need_to_disable;
2027 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2029 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2030 port_name(intel_dig_port->port));
2032 if (!edp_have_panel_power(intel_dp))
2033 wait_panel_power_cycle(intel_dp);
2035 pp = ironlake_get_pp_control(intel_dp);
2036 pp |= EDP_FORCE_VDD;
2038 pp_stat_reg = _pp_stat_reg(intel_dp);
2039 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2041 I915_WRITE(pp_ctrl_reg, pp);
2042 POSTING_READ(pp_ctrl_reg);
2043 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2044 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2046 * If the panel wasn't on, delay before accessing aux channel
2048 if (!edp_have_panel_power(intel_dp)) {
2049 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2050 port_name(intel_dig_port->port));
2051 msleep(intel_dp->panel_power_up_delay);
2054 return need_to_disable;
2058 * Must be paired with intel_edp_panel_vdd_off() or
2059 * intel_edp_panel_off().
2060 * Nested calls to these functions are not allowed since
2061 * we drop the lock. Caller must use some higher level
2062 * locking to prevent nested calls from other threads.
2064 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2068 if (!is_edp(intel_dp))
2072 vdd = edp_panel_vdd_on(intel_dp);
2073 pps_unlock(intel_dp);
2075 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2076 port_name(dp_to_dig_port(intel_dp)->port));
2079 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2081 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2082 struct drm_i915_private *dev_priv = to_i915(dev);
2083 struct intel_digital_port *intel_dig_port =
2084 dp_to_dig_port(intel_dp);
2086 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2088 lockdep_assert_held(&dev_priv->pps_mutex);
2090 WARN_ON(intel_dp->want_panel_vdd);
2092 if (!edp_have_panel_vdd(intel_dp))
2095 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2096 port_name(intel_dig_port->port));
2098 pp = ironlake_get_pp_control(intel_dp);
2099 pp &= ~EDP_FORCE_VDD;
2101 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2102 pp_stat_reg = _pp_stat_reg(intel_dp);
2104 I915_WRITE(pp_ctrl_reg, pp);
2105 POSTING_READ(pp_ctrl_reg);
2107 /* Make sure sequencer is idle before allowing subsequent activity */
2108 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2109 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2111 if ((pp & PANEL_POWER_ON) == 0)
2112 intel_dp->panel_power_off_time = ktime_get_boottime();
2114 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2117 static void edp_panel_vdd_work(struct work_struct *__work)
2119 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2120 struct intel_dp, panel_vdd_work);
2123 if (!intel_dp->want_panel_vdd)
2124 edp_panel_vdd_off_sync(intel_dp);
2125 pps_unlock(intel_dp);
2128 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2130 unsigned long delay;
2133 * Queue the timer to fire a long time from now (relative to the power
2134 * down delay) to keep the panel power up across a sequence of
2137 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2138 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2142 * Must be paired with edp_panel_vdd_on().
2143 * Must hold pps_mutex around the whole on/off sequence.
2144 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2146 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2148 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2150 lockdep_assert_held(&dev_priv->pps_mutex);
2152 if (!is_edp(intel_dp))
2155 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2156 port_name(dp_to_dig_port(intel_dp)->port));
2158 intel_dp->want_panel_vdd = false;
2161 edp_panel_vdd_off_sync(intel_dp);
2163 edp_panel_vdd_schedule_off(intel_dp);
2166 static void edp_panel_on(struct intel_dp *intel_dp)
2168 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2169 struct drm_i915_private *dev_priv = to_i915(dev);
2171 i915_reg_t pp_ctrl_reg;
2173 lockdep_assert_held(&dev_priv->pps_mutex);
2175 if (!is_edp(intel_dp))
2178 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2179 port_name(dp_to_dig_port(intel_dp)->port));
2181 if (WARN(edp_have_panel_power(intel_dp),
2182 "eDP port %c panel power already on\n",
2183 port_name(dp_to_dig_port(intel_dp)->port)))
2186 wait_panel_power_cycle(intel_dp);
2188 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2189 pp = ironlake_get_pp_control(intel_dp);
2190 if (IS_GEN5(dev_priv)) {
2191 /* ILK workaround: disable reset around power sequence */
2192 pp &= ~PANEL_POWER_RESET;
2193 I915_WRITE(pp_ctrl_reg, pp);
2194 POSTING_READ(pp_ctrl_reg);
2197 pp |= PANEL_POWER_ON;
2198 if (!IS_GEN5(dev_priv))
2199 pp |= PANEL_POWER_RESET;
2201 I915_WRITE(pp_ctrl_reg, pp);
2202 POSTING_READ(pp_ctrl_reg);
2204 wait_panel_on(intel_dp);
2205 intel_dp->last_power_on = jiffies;
2207 if (IS_GEN5(dev_priv)) {
2208 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2209 I915_WRITE(pp_ctrl_reg, pp);
2210 POSTING_READ(pp_ctrl_reg);
2214 void intel_edp_panel_on(struct intel_dp *intel_dp)
2216 if (!is_edp(intel_dp))
2220 edp_panel_on(intel_dp);
2221 pps_unlock(intel_dp);
2225 static void edp_panel_off(struct intel_dp *intel_dp)
2227 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2228 struct drm_i915_private *dev_priv = to_i915(dev);
2230 i915_reg_t pp_ctrl_reg;
2232 lockdep_assert_held(&dev_priv->pps_mutex);
2234 if (!is_edp(intel_dp))
2237 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2238 port_name(dp_to_dig_port(intel_dp)->port));
2240 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2241 port_name(dp_to_dig_port(intel_dp)->port));
2243 pp = ironlake_get_pp_control(intel_dp);
2244 /* We need to switch off panel power _and_ force vdd, for otherwise some
2245 * panels get very unhappy and cease to work. */
2246 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2249 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2251 intel_dp->want_panel_vdd = false;
2253 I915_WRITE(pp_ctrl_reg, pp);
2254 POSTING_READ(pp_ctrl_reg);
2256 intel_dp->panel_power_off_time = ktime_get_boottime();
2257 wait_panel_off(intel_dp);
2259 /* We got a reference when we enabled the VDD. */
2260 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2263 void intel_edp_panel_off(struct intel_dp *intel_dp)
2265 if (!is_edp(intel_dp))
2269 edp_panel_off(intel_dp);
2270 pps_unlock(intel_dp);
2273 /* Enable backlight in the panel power control. */
2274 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2276 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2277 struct drm_device *dev = intel_dig_port->base.base.dev;
2278 struct drm_i915_private *dev_priv = to_i915(dev);
2280 i915_reg_t pp_ctrl_reg;
2283 * If we enable the backlight right away following a panel power
2284 * on, we may see slight flicker as the panel syncs with the eDP
2285 * link. So delay a bit to make sure the image is solid before
2286 * allowing it to appear.
2288 wait_backlight_on(intel_dp);
2292 pp = ironlake_get_pp_control(intel_dp);
2293 pp |= EDP_BLC_ENABLE;
2295 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2297 I915_WRITE(pp_ctrl_reg, pp);
2298 POSTING_READ(pp_ctrl_reg);
2300 pps_unlock(intel_dp);
2303 /* Enable backlight PWM and backlight PP control. */
2304 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2306 if (!is_edp(intel_dp))
2309 DRM_DEBUG_KMS("\n");
2311 intel_panel_enable_backlight(intel_dp->attached_connector);
2312 _intel_edp_backlight_on(intel_dp);
2315 /* Disable backlight in the panel power control. */
2316 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2318 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2319 struct drm_i915_private *dev_priv = to_i915(dev);
2321 i915_reg_t pp_ctrl_reg;
2323 if (!is_edp(intel_dp))
2328 pp = ironlake_get_pp_control(intel_dp);
2329 pp &= ~EDP_BLC_ENABLE;
2331 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2333 I915_WRITE(pp_ctrl_reg, pp);
2334 POSTING_READ(pp_ctrl_reg);
2336 pps_unlock(intel_dp);
2338 intel_dp->last_backlight_off = jiffies;
2339 edp_wait_backlight_off(intel_dp);
2342 /* Disable backlight PP control and backlight PWM. */
2343 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2345 if (!is_edp(intel_dp))
2348 DRM_DEBUG_KMS("\n");
2350 _intel_edp_backlight_off(intel_dp);
2351 intel_panel_disable_backlight(intel_dp->attached_connector);
2355 * Hook for controlling the panel power control backlight through the bl_power
2356 * sysfs attribute. Take care to handle multiple calls.
2358 static void intel_edp_backlight_power(struct intel_connector *connector,
2361 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2365 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2366 pps_unlock(intel_dp);
2368 if (is_enabled == enable)
2371 DRM_DEBUG_KMS("panel power control backlight %s\n",
2372 enable ? "enable" : "disable");
2375 _intel_edp_backlight_on(intel_dp);
2377 _intel_edp_backlight_off(intel_dp);
2380 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2382 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2383 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2384 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2386 I915_STATE_WARN(cur_state != state,
2387 "DP port %c state assertion failure (expected %s, current %s)\n",
2388 port_name(dig_port->port),
2389 onoff(state), onoff(cur_state));
2391 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2393 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2395 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2397 I915_STATE_WARN(cur_state != state,
2398 "eDP PLL state assertion failure (expected %s, current %s)\n",
2399 onoff(state), onoff(cur_state));
2401 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2402 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2404 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2405 struct intel_crtc_state *pipe_config)
2407 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2408 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2410 assert_pipe_disabled(dev_priv, crtc->pipe);
2411 assert_dp_port_disabled(intel_dp);
2412 assert_edp_pll_disabled(dev_priv);
2414 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2415 pipe_config->port_clock);
2417 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2419 if (pipe_config->port_clock == 162000)
2420 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2422 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2424 I915_WRITE(DP_A, intel_dp->DP);
2429 * [DevILK] Work around required when enabling DP PLL
2430 * while a pipe is enabled going to FDI:
2431 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2432 * 2. Program DP PLL enable
2434 if (IS_GEN5(dev_priv))
2435 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2437 intel_dp->DP |= DP_PLL_ENABLE;
2439 I915_WRITE(DP_A, intel_dp->DP);
2444 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2447 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2448 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2450 assert_pipe_disabled(dev_priv, crtc->pipe);
2451 assert_dp_port_disabled(intel_dp);
2452 assert_edp_pll_enabled(dev_priv);
2454 DRM_DEBUG_KMS("disabling eDP PLL\n");
2456 intel_dp->DP &= ~DP_PLL_ENABLE;
2458 I915_WRITE(DP_A, intel_dp->DP);
2463 /* If the sink supports it, try to set the power state appropriately */
2464 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2468 /* Should have a valid DPCD by this point */
2469 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2472 if (mode != DRM_MODE_DPMS_ON) {
2473 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2476 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2479 * When turning on, we need to retry for 1ms to give the sink
2482 for (i = 0; i < 3; i++) {
2483 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2490 if (ret == 1 && lspcon->active)
2491 lspcon_wait_pcon_mode(lspcon);
2495 DRM_DEBUG_KMS("failed to %s sink power state\n",
2496 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2499 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2502 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2503 enum port port = dp_to_dig_port(intel_dp)->port;
2504 struct drm_device *dev = encoder->base.dev;
2505 struct drm_i915_private *dev_priv = to_i915(dev);
2509 if (!intel_display_power_get_if_enabled(dev_priv,
2510 encoder->power_domain))
2515 tmp = I915_READ(intel_dp->output_reg);
2517 if (!(tmp & DP_PORT_EN))
2520 if (IS_GEN7(dev_priv) && port == PORT_A) {
2521 *pipe = PORT_TO_PIPE_CPT(tmp);
2522 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2525 for_each_pipe(dev_priv, p) {
2526 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2527 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2535 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2536 i915_mmio_reg_offset(intel_dp->output_reg));
2537 } else if (IS_CHERRYVIEW(dev_priv)) {
2538 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2540 *pipe = PORT_TO_PIPE(tmp);
2546 intel_display_power_put(dev_priv, encoder->power_domain);
2551 static void intel_dp_get_config(struct intel_encoder *encoder,
2552 struct intel_crtc_state *pipe_config)
2554 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2556 struct drm_device *dev = encoder->base.dev;
2557 struct drm_i915_private *dev_priv = to_i915(dev);
2558 enum port port = dp_to_dig_port(intel_dp)->port;
2559 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2561 tmp = I915_READ(intel_dp->output_reg);
2563 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2565 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2566 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2568 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2569 flags |= DRM_MODE_FLAG_PHSYNC;
2571 flags |= DRM_MODE_FLAG_NHSYNC;
2573 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2574 flags |= DRM_MODE_FLAG_PVSYNC;
2576 flags |= DRM_MODE_FLAG_NVSYNC;
2578 if (tmp & DP_SYNC_HS_HIGH)
2579 flags |= DRM_MODE_FLAG_PHSYNC;
2581 flags |= DRM_MODE_FLAG_NHSYNC;
2583 if (tmp & DP_SYNC_VS_HIGH)
2584 flags |= DRM_MODE_FLAG_PVSYNC;
2586 flags |= DRM_MODE_FLAG_NVSYNC;
2589 pipe_config->base.adjusted_mode.flags |= flags;
2591 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2592 pipe_config->limited_color_range = true;
2594 pipe_config->lane_count =
2595 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2597 intel_dp_get_m_n(crtc, pipe_config);
2599 if (port == PORT_A) {
2600 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2601 pipe_config->port_clock = 162000;
2603 pipe_config->port_clock = 270000;
2606 pipe_config->base.adjusted_mode.crtc_clock =
2607 intel_dotclock_calculate(pipe_config->port_clock,
2608 &pipe_config->dp_m_n);
2610 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2611 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2613 * This is a big fat ugly hack.
2615 * Some machines in UEFI boot mode provide us a VBT that has 18
2616 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2617 * unknown we fail to light up. Yet the same BIOS boots up with
2618 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2619 * max, not what it tells us to use.
2621 * Note: This will still be broken if the eDP panel is not lit
2622 * up by the BIOS, and thus we can't get the mode at module
2625 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2626 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2627 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2631 static void intel_disable_dp(struct intel_encoder *encoder,
2632 struct intel_crtc_state *old_crtc_state,
2633 struct drm_connector_state *old_conn_state)
2635 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2636 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2638 if (old_crtc_state->has_audio)
2639 intel_audio_codec_disable(encoder);
2641 if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2642 intel_psr_disable(intel_dp);
2644 /* Make sure the panel is off before trying to change the mode. But also
2645 * ensure that we have vdd while we switch off the panel. */
2646 intel_edp_panel_vdd_on(intel_dp);
2647 intel_edp_backlight_off(intel_dp);
2648 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2649 intel_edp_panel_off(intel_dp);
2651 /* disable the port before the pipe on g4x */
2652 if (INTEL_GEN(dev_priv) < 5)
2653 intel_dp_link_down(intel_dp);
2656 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2657 struct intel_crtc_state *old_crtc_state,
2658 struct drm_connector_state *old_conn_state)
2660 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2661 enum port port = dp_to_dig_port(intel_dp)->port;
2663 intel_dp_link_down(intel_dp);
2665 /* Only ilk+ has port A */
2667 ironlake_edp_pll_off(intel_dp);
2670 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2671 struct intel_crtc_state *old_crtc_state,
2672 struct drm_connector_state *old_conn_state)
2674 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2676 intel_dp_link_down(intel_dp);
2679 static void chv_post_disable_dp(struct intel_encoder *encoder,
2680 struct intel_crtc_state *old_crtc_state,
2681 struct drm_connector_state *old_conn_state)
2683 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2684 struct drm_device *dev = encoder->base.dev;
2685 struct drm_i915_private *dev_priv = to_i915(dev);
2687 intel_dp_link_down(intel_dp);
2689 mutex_lock(&dev_priv->sb_lock);
2691 /* Assert data lane reset */
2692 chv_data_lane_soft_reset(encoder, true);
2694 mutex_unlock(&dev_priv->sb_lock);
2698 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2700 uint8_t dp_train_pat)
2702 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2703 struct drm_device *dev = intel_dig_port->base.base.dev;
2704 struct drm_i915_private *dev_priv = to_i915(dev);
2705 enum port port = intel_dig_port->port;
2707 if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2708 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2709 dp_train_pat & DP_TRAINING_PATTERN_MASK);
2711 if (HAS_DDI(dev_priv)) {
2712 uint32_t temp = I915_READ(DP_TP_CTL(port));
2714 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2715 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2717 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2719 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2720 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2721 case DP_TRAINING_PATTERN_DISABLE:
2722 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2725 case DP_TRAINING_PATTERN_1:
2726 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2728 case DP_TRAINING_PATTERN_2:
2729 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2731 case DP_TRAINING_PATTERN_3:
2732 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2735 I915_WRITE(DP_TP_CTL(port), temp);
2737 } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2738 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2739 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2741 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2742 case DP_TRAINING_PATTERN_DISABLE:
2743 *DP |= DP_LINK_TRAIN_OFF_CPT;
2745 case DP_TRAINING_PATTERN_1:
2746 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2748 case DP_TRAINING_PATTERN_2:
2749 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2751 case DP_TRAINING_PATTERN_3:
2752 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2753 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2758 if (IS_CHERRYVIEW(dev_priv))
2759 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2761 *DP &= ~DP_LINK_TRAIN_MASK;
2763 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2764 case DP_TRAINING_PATTERN_DISABLE:
2765 *DP |= DP_LINK_TRAIN_OFF;
2767 case DP_TRAINING_PATTERN_1:
2768 *DP |= DP_LINK_TRAIN_PAT_1;
2770 case DP_TRAINING_PATTERN_2:
2771 *DP |= DP_LINK_TRAIN_PAT_2;
2773 case DP_TRAINING_PATTERN_3:
2774 if (IS_CHERRYVIEW(dev_priv)) {
2775 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2777 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2778 *DP |= DP_LINK_TRAIN_PAT_2;
2785 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2786 struct intel_crtc_state *old_crtc_state)
2788 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2789 struct drm_i915_private *dev_priv = to_i915(dev);
2791 /* enable with pattern 1 (as per spec) */
2793 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2796 * Magic for VLV/CHV. We _must_ first set up the register
2797 * without actually enabling the port, and then do another
2798 * write to enable the port. Otherwise link training will
2799 * fail when the power sequencer is freshly used for this port.
2801 intel_dp->DP |= DP_PORT_EN;
2802 if (old_crtc_state->has_audio)
2803 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2805 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2806 POSTING_READ(intel_dp->output_reg);
2809 static void intel_enable_dp(struct intel_encoder *encoder,
2810 struct intel_crtc_state *pipe_config,
2811 struct drm_connector_state *conn_state)
2813 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2814 struct drm_device *dev = encoder->base.dev;
2815 struct drm_i915_private *dev_priv = to_i915(dev);
2816 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2817 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2818 enum pipe pipe = crtc->pipe;
2820 if (WARN_ON(dp_reg & DP_PORT_EN))
2825 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2826 vlv_init_panel_power_sequencer(intel_dp);
2828 intel_dp_enable_port(intel_dp, pipe_config);
2830 edp_panel_vdd_on(intel_dp);
2831 edp_panel_on(intel_dp);
2832 edp_panel_vdd_off(intel_dp, true);
2834 pps_unlock(intel_dp);
2836 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2837 unsigned int lane_mask = 0x0;
2839 if (IS_CHERRYVIEW(dev_priv))
2840 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2842 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2846 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2847 intel_dp_start_link_train(intel_dp);
2848 intel_dp_stop_link_train(intel_dp);
2850 if (pipe_config->has_audio) {
2851 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2853 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2857 static void g4x_enable_dp(struct intel_encoder *encoder,
2858 struct intel_crtc_state *pipe_config,
2859 struct drm_connector_state *conn_state)
2861 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2863 intel_enable_dp(encoder, pipe_config, conn_state);
2864 intel_edp_backlight_on(intel_dp);
2867 static void vlv_enable_dp(struct intel_encoder *encoder,
2868 struct intel_crtc_state *pipe_config,
2869 struct drm_connector_state *conn_state)
2871 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2873 intel_edp_backlight_on(intel_dp);
2874 intel_psr_enable(intel_dp);
2877 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2878 struct intel_crtc_state *pipe_config,
2879 struct drm_connector_state *conn_state)
2881 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2882 enum port port = dp_to_dig_port(intel_dp)->port;
2884 intel_dp_prepare(encoder, pipe_config);
2886 /* Only ilk+ has port A */
2888 ironlake_edp_pll_on(intel_dp, pipe_config);
2891 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2893 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2894 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2895 enum pipe pipe = intel_dp->pps_pipe;
2896 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2898 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2900 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2903 edp_panel_vdd_off_sync(intel_dp);
2906 * VLV seems to get confused when multiple power seqeuencers
2907 * have the same port selected (even if only one has power/vdd
2908 * enabled). The failure manifests as vlv_wait_port_ready() failing
2909 * CHV on the other hand doesn't seem to mind having the same port
2910 * selected in multiple power seqeuencers, but let's clear the
2911 * port select always when logically disconnecting a power sequencer
2914 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2915 pipe_name(pipe), port_name(intel_dig_port->port));
2916 I915_WRITE(pp_on_reg, 0);
2917 POSTING_READ(pp_on_reg);
2919 intel_dp->pps_pipe = INVALID_PIPE;
2922 static void vlv_steal_power_sequencer(struct drm_device *dev,
2925 struct drm_i915_private *dev_priv = to_i915(dev);
2926 struct intel_encoder *encoder;
2928 lockdep_assert_held(&dev_priv->pps_mutex);
2930 for_each_intel_encoder(dev, encoder) {
2931 struct intel_dp *intel_dp;
2934 if (encoder->type != INTEL_OUTPUT_DP &&
2935 encoder->type != INTEL_OUTPUT_EDP)
2938 intel_dp = enc_to_intel_dp(&encoder->base);
2939 port = dp_to_dig_port(intel_dp)->port;
2941 WARN(intel_dp->active_pipe == pipe,
2942 "stealing pipe %c power sequencer from active (e)DP port %c\n",
2943 pipe_name(pipe), port_name(port));
2945 if (intel_dp->pps_pipe != pipe)
2948 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2949 pipe_name(pipe), port_name(port));
2951 /* make sure vdd is off before we steal it */
2952 vlv_detach_power_sequencer(intel_dp);
2956 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2958 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2959 struct intel_encoder *encoder = &intel_dig_port->base;
2960 struct drm_device *dev = encoder->base.dev;
2961 struct drm_i915_private *dev_priv = to_i915(dev);
2962 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2964 lockdep_assert_held(&dev_priv->pps_mutex);
2966 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2968 if (intel_dp->pps_pipe != INVALID_PIPE &&
2969 intel_dp->pps_pipe != crtc->pipe) {
2971 * If another power sequencer was being used on this
2972 * port previously make sure to turn off vdd there while
2973 * we still have control of it.
2975 vlv_detach_power_sequencer(intel_dp);
2979 * We may be stealing the power
2980 * sequencer from another port.
2982 vlv_steal_power_sequencer(dev, crtc->pipe);
2984 intel_dp->active_pipe = crtc->pipe;
2986 if (!is_edp(intel_dp))
2989 /* now it's all ours */
2990 intel_dp->pps_pipe = crtc->pipe;
2992 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2993 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2995 /* init power sequencer on this pipe and port */
2996 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2997 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
3000 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3001 struct intel_crtc_state *pipe_config,
3002 struct drm_connector_state *conn_state)
3004 vlv_phy_pre_encoder_enable(encoder);
3006 intel_enable_dp(encoder, pipe_config, conn_state);
3009 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3010 struct intel_crtc_state *pipe_config,
3011 struct drm_connector_state *conn_state)
3013 intel_dp_prepare(encoder, pipe_config);
3015 vlv_phy_pre_pll_enable(encoder);
3018 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3019 struct intel_crtc_state *pipe_config,
3020 struct drm_connector_state *conn_state)
3022 chv_phy_pre_encoder_enable(encoder);
3024 intel_enable_dp(encoder, pipe_config, conn_state);
3026 /* Second common lane will stay alive on its own now */
3027 chv_phy_release_cl2_override(encoder);
3030 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3031 struct intel_crtc_state *pipe_config,
3032 struct drm_connector_state *conn_state)
3034 intel_dp_prepare(encoder, pipe_config);
3036 chv_phy_pre_pll_enable(encoder);
3039 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3040 struct intel_crtc_state *pipe_config,
3041 struct drm_connector_state *conn_state)
3043 chv_phy_post_pll_disable(encoder);
3047 * Fetch AUX CH registers 0x202 - 0x207 which contain
3048 * link status information
3051 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3053 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3054 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3057 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3059 uint8_t psr_caps = 0;
3061 drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps);
3062 return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3065 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3069 drm_dp_dpcd_readb(&intel_dp->aux,
3070 DP_DPRX_FEATURE_ENUMERATION_LIST,
3072 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3075 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3077 uint8_t alpm_caps = 0;
3079 drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &alpm_caps);
3080 return alpm_caps & DP_ALPM_CAP;
3083 /* These are source-specific values. */
3085 intel_dp_voltage_max(struct intel_dp *intel_dp)
3087 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3088 enum port port = dp_to_dig_port(intel_dp)->port;
3090 if (IS_GEN9_LP(dev_priv))
3091 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3092 else if (INTEL_GEN(dev_priv) >= 9) {
3093 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3094 return intel_ddi_dp_voltage_max(encoder);
3095 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3096 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3097 else if (IS_GEN7(dev_priv) && port == PORT_A)
3098 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3099 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3100 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3102 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3106 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3108 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3109 enum port port = dp_to_dig_port(intel_dp)->port;
3111 if (INTEL_GEN(dev_priv) >= 9) {
3112 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3113 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3114 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3115 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3116 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3117 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3118 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3119 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3120 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3122 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3124 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3125 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3126 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3127 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3128 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3129 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3130 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3131 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3132 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3134 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3136 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3137 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3138 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3139 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3140 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3141 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3142 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3143 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3144 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3146 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3148 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3149 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3150 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3151 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3152 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3153 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3154 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3156 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3159 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3160 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3161 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3162 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3163 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3164 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3165 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3168 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3173 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3175 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3176 unsigned long demph_reg_value, preemph_reg_value,
3177 uniqtranscale_reg_value;
3178 uint8_t train_set = intel_dp->train_set[0];
3180 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3181 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3182 preemph_reg_value = 0x0004000;
3183 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3184 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3185 demph_reg_value = 0x2B405555;
3186 uniqtranscale_reg_value = 0x552AB83A;
3188 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3189 demph_reg_value = 0x2B404040;
3190 uniqtranscale_reg_value = 0x5548B83A;
3192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3193 demph_reg_value = 0x2B245555;
3194 uniqtranscale_reg_value = 0x5560B83A;
3196 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3197 demph_reg_value = 0x2B405555;
3198 uniqtranscale_reg_value = 0x5598DA3A;
3204 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3205 preemph_reg_value = 0x0002000;
3206 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3208 demph_reg_value = 0x2B404040;
3209 uniqtranscale_reg_value = 0x5552B83A;
3211 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3212 demph_reg_value = 0x2B404848;
3213 uniqtranscale_reg_value = 0x5580B83A;
3215 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3216 demph_reg_value = 0x2B404040;
3217 uniqtranscale_reg_value = 0x55ADDA3A;
3223 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3224 preemph_reg_value = 0x0000000;
3225 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3227 demph_reg_value = 0x2B305555;
3228 uniqtranscale_reg_value = 0x5570B83A;
3230 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3231 demph_reg_value = 0x2B2B4040;
3232 uniqtranscale_reg_value = 0x55ADDA3A;
3238 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3239 preemph_reg_value = 0x0006000;
3240 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3241 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3242 demph_reg_value = 0x1B405555;
3243 uniqtranscale_reg_value = 0x55ADDA3A;
3253 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3254 uniqtranscale_reg_value, 0);
3259 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3261 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3262 u32 deemph_reg_value, margin_reg_value;
3263 bool uniq_trans_scale = false;
3264 uint8_t train_set = intel_dp->train_set[0];
3266 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3267 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3268 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3269 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3270 deemph_reg_value = 128;
3271 margin_reg_value = 52;
3273 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3274 deemph_reg_value = 128;
3275 margin_reg_value = 77;
3277 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3278 deemph_reg_value = 128;
3279 margin_reg_value = 102;
3281 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3282 deemph_reg_value = 128;
3283 margin_reg_value = 154;
3284 uniq_trans_scale = true;
3290 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3291 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3292 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3293 deemph_reg_value = 85;
3294 margin_reg_value = 78;
3296 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3297 deemph_reg_value = 85;
3298 margin_reg_value = 116;
3300 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3301 deemph_reg_value = 85;
3302 margin_reg_value = 154;
3308 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3309 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3310 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3311 deemph_reg_value = 64;
3312 margin_reg_value = 104;
3314 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3315 deemph_reg_value = 64;
3316 margin_reg_value = 154;
3322 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3323 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3324 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3325 deemph_reg_value = 43;
3326 margin_reg_value = 154;
3336 chv_set_phy_signal_level(encoder, deemph_reg_value,
3337 margin_reg_value, uniq_trans_scale);
3343 gen4_signal_levels(uint8_t train_set)
3345 uint32_t signal_levels = 0;
3347 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3348 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3350 signal_levels |= DP_VOLTAGE_0_4;
3352 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3353 signal_levels |= DP_VOLTAGE_0_6;
3355 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3356 signal_levels |= DP_VOLTAGE_0_8;
3358 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3359 signal_levels |= DP_VOLTAGE_1_2;
3362 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3363 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3365 signal_levels |= DP_PRE_EMPHASIS_0;
3367 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3368 signal_levels |= DP_PRE_EMPHASIS_3_5;
3370 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3371 signal_levels |= DP_PRE_EMPHASIS_6;
3373 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3374 signal_levels |= DP_PRE_EMPHASIS_9_5;
3377 return signal_levels;
3380 /* Gen6's DP voltage swing and pre-emphasis control */
3382 gen6_edp_signal_levels(uint8_t train_set)
3384 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3385 DP_TRAIN_PRE_EMPHASIS_MASK);
3386 switch (signal_levels) {
3387 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3388 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3389 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3390 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3391 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3392 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3393 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3394 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3395 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3396 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3397 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3398 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3399 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3400 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3402 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3403 "0x%x\n", signal_levels);
3404 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3408 /* Gen7's DP voltage swing and pre-emphasis control */
3410 gen7_edp_signal_levels(uint8_t train_set)
3412 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3413 DP_TRAIN_PRE_EMPHASIS_MASK);
3414 switch (signal_levels) {
3415 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3416 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3417 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3418 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3419 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3420 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3422 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3423 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3424 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3425 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3427 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3428 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3429 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3430 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3433 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3434 "0x%x\n", signal_levels);
3435 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3440 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3442 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3443 enum port port = intel_dig_port->port;
3444 struct drm_device *dev = intel_dig_port->base.base.dev;
3445 struct drm_i915_private *dev_priv = to_i915(dev);
3446 uint32_t signal_levels, mask = 0;
3447 uint8_t train_set = intel_dp->train_set[0];
3449 if (HAS_DDI(dev_priv)) {
3450 signal_levels = ddi_signal_levels(intel_dp);
3452 if (IS_GEN9_LP(dev_priv))
3455 mask = DDI_BUF_EMP_MASK;
3456 } else if (IS_CHERRYVIEW(dev_priv)) {
3457 signal_levels = chv_signal_levels(intel_dp);
3458 } else if (IS_VALLEYVIEW(dev_priv)) {
3459 signal_levels = vlv_signal_levels(intel_dp);
3460 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3461 signal_levels = gen7_edp_signal_levels(train_set);
3462 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3463 } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3464 signal_levels = gen6_edp_signal_levels(train_set);
3465 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3467 signal_levels = gen4_signal_levels(train_set);
3468 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3472 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3474 DRM_DEBUG_KMS("Using vswing level %d\n",
3475 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3476 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3477 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3478 DP_TRAIN_PRE_EMPHASIS_SHIFT);
3480 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3482 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3483 POSTING_READ(intel_dp->output_reg);
3487 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3488 uint8_t dp_train_pat)
3490 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3491 struct drm_i915_private *dev_priv =
3492 to_i915(intel_dig_port->base.base.dev);
3494 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3496 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3497 POSTING_READ(intel_dp->output_reg);
3500 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3502 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3503 struct drm_device *dev = intel_dig_port->base.base.dev;
3504 struct drm_i915_private *dev_priv = to_i915(dev);
3505 enum port port = intel_dig_port->port;
3508 if (!HAS_DDI(dev_priv))
3511 val = I915_READ(DP_TP_CTL(port));
3512 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3513 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3514 I915_WRITE(DP_TP_CTL(port), val);
3517 * On PORT_A we can have only eDP in SST mode. There the only reason
3518 * we need to set idle transmission mode is to work around a HW issue
3519 * where we enable the pipe while not in idle link-training mode.
3520 * In this case there is requirement to wait for a minimum number of
3521 * idle patterns to be sent.
3526 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3527 DP_TP_STATUS_IDLE_DONE,
3528 DP_TP_STATUS_IDLE_DONE,
3530 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3534 intel_dp_link_down(struct intel_dp *intel_dp)
3536 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3537 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3538 enum port port = intel_dig_port->port;
3539 struct drm_device *dev = intel_dig_port->base.base.dev;
3540 struct drm_i915_private *dev_priv = to_i915(dev);
3541 uint32_t DP = intel_dp->DP;
3543 if (WARN_ON(HAS_DDI(dev_priv)))
3546 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3549 DRM_DEBUG_KMS("\n");
3551 if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3552 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3553 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3554 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3556 if (IS_CHERRYVIEW(dev_priv))
3557 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3559 DP &= ~DP_LINK_TRAIN_MASK;
3560 DP |= DP_LINK_TRAIN_PAT_IDLE;
3562 I915_WRITE(intel_dp->output_reg, DP);
3563 POSTING_READ(intel_dp->output_reg);
3565 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3566 I915_WRITE(intel_dp->output_reg, DP);
3567 POSTING_READ(intel_dp->output_reg);
3570 * HW workaround for IBX, we need to move the port
3571 * to transcoder A after disabling it to allow the
3572 * matching HDMI port to be enabled on transcoder A.
3574 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3576 * We get CPU/PCH FIFO underruns on the other pipe when
3577 * doing the workaround. Sweep them under the rug.
3579 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3580 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3582 /* always enable with pattern 1 (as per spec) */
3583 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3584 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3585 I915_WRITE(intel_dp->output_reg, DP);
3586 POSTING_READ(intel_dp->output_reg);
3589 I915_WRITE(intel_dp->output_reg, DP);
3590 POSTING_READ(intel_dp->output_reg);
3592 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3593 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3594 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3597 msleep(intel_dp->panel_power_down_delay);
3601 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3603 intel_dp->active_pipe = INVALID_PIPE;
3604 pps_unlock(intel_dp);
3609 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3611 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3612 sizeof(intel_dp->dpcd)) < 0)
3613 return false; /* aux transfer failed */
3615 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3617 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3621 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3623 struct drm_i915_private *dev_priv =
3624 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3626 /* this function is meant to be called only once */
3627 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3629 if (!intel_dp_read_dpcd(intel_dp))
3632 intel_dp_read_desc(intel_dp);
3634 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3635 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3636 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3638 /* Check if the panel supports PSR */
3639 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3641 sizeof(intel_dp->psr_dpcd));
3642 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3643 dev_priv->psr.sink_support = true;
3644 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3647 if (INTEL_GEN(dev_priv) >= 9 &&
3648 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3649 uint8_t frame_sync_cap;
3651 dev_priv->psr.sink_support = true;
3652 drm_dp_dpcd_read(&intel_dp->aux,
3653 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3654 &frame_sync_cap, 1);
3655 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3656 /* PSR2 needs frame sync as well */
3657 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3658 DRM_DEBUG_KMS("PSR2 %s on sink",
3659 dev_priv->psr.psr2_support ? "supported" : "not supported");
3661 if (dev_priv->psr.psr2_support) {
3662 dev_priv->psr.y_cord_support =
3663 intel_dp_get_y_cord_status(intel_dp);
3664 dev_priv->psr.colorimetry_support =
3665 intel_dp_get_colorimetry_status(intel_dp);
3666 dev_priv->psr.alpm =
3667 intel_dp_get_alpm_status(intel_dp);
3672 /* Read the eDP Display control capabilities registers */
3673 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3674 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3675 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3676 sizeof(intel_dp->edp_dpcd))
3677 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3678 intel_dp->edp_dpcd);
3680 /* Intermediate frequency support */
3681 if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3682 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3685 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3686 sink_rates, sizeof(sink_rates));
3688 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3689 int val = le16_to_cpu(sink_rates[i]);
3694 /* Value read multiplied by 200kHz gives the per-lane
3695 * link rate in kHz. The source rates are, however,
3696 * stored in terms of LS_Clk kHz. The full conversion
3697 * back to symbols is
3698 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3700 intel_dp->sink_rates[i] = (val * 200) / 10;
3702 intel_dp->num_sink_rates = i;
3710 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3712 if (!intel_dp_read_dpcd(intel_dp))
3715 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3716 &intel_dp->sink_count, 1) < 0)
3720 * Sink count can change between short pulse hpd hence
3721 * a member variable in intel_dp will track any changes
3722 * between short pulse interrupts.
3724 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3727 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3728 * a dongle is present but no display. Unless we require to know
3729 * if a dongle is present or not, we don't need to update
3730 * downstream port information. So, an early return here saves
3731 * time from performing other operations which are not required.
3733 if (!is_edp(intel_dp) && !intel_dp->sink_count)
3736 if (!drm_dp_is_branch(intel_dp->dpcd))
3737 return true; /* native DP sink */
3739 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3740 return true; /* no per-port downstream info */
3742 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3743 intel_dp->downstream_ports,
3744 DP_MAX_DOWNSTREAM_PORTS) < 0)
3745 return false; /* downstream port status fetch failed */
3751 intel_dp_can_mst(struct intel_dp *intel_dp)
3755 if (!i915.enable_dp_mst)
3758 if (!intel_dp->can_mst)
3761 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3764 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3767 return buf[0] & DP_MST_CAP;
3771 intel_dp_configure_mst(struct intel_dp *intel_dp)
3773 if (!i915.enable_dp_mst)
3776 if (!intel_dp->can_mst)
3779 intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3781 if (intel_dp->is_mst)
3782 DRM_DEBUG_KMS("Sink is MST capable\n");
3784 DRM_DEBUG_KMS("Sink is not MST capable\n");
3786 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3790 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3792 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3793 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3794 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3800 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3801 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3806 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3807 buf & ~DP_TEST_SINK_START) < 0) {
3808 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3814 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3816 if (drm_dp_dpcd_readb(&intel_dp->aux,
3817 DP_TEST_SINK_MISC, &buf) < 0) {
3821 count = buf & DP_TEST_COUNT_MASK;
3822 } while (--attempts && count);
3824 if (attempts == 0) {
3825 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3830 hsw_enable_ips(intel_crtc);
3834 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3836 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3837 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3838 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3842 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3845 if (!(buf & DP_TEST_CRC_SUPPORTED))
3848 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3851 if (buf & DP_TEST_SINK_START) {
3852 ret = intel_dp_sink_crc_stop(intel_dp);
3857 hsw_disable_ips(intel_crtc);
3859 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3860 buf | DP_TEST_SINK_START) < 0) {
3861 hsw_enable_ips(intel_crtc);
3865 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3869 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3871 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3872 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3873 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3878 ret = intel_dp_sink_crc_start(intel_dp);
3883 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3885 if (drm_dp_dpcd_readb(&intel_dp->aux,
3886 DP_TEST_SINK_MISC, &buf) < 0) {
3890 count = buf & DP_TEST_COUNT_MASK;
3892 } while (--attempts && count == 0);
3894 if (attempts == 0) {
3895 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3900 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3906 intel_dp_sink_crc_stop(intel_dp);
3911 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3913 return drm_dp_dpcd_read(&intel_dp->aux,
3914 DP_DEVICE_SERVICE_IRQ_VECTOR,
3915 sink_irq_vector, 1) == 1;
3919 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3923 ret = drm_dp_dpcd_read(&intel_dp->aux,
3925 sink_irq_vector, 14);
3932 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3935 int min_lane_count = 1;
3936 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
3937 int link_rate_index, test_link_rate;
3938 uint8_t test_lane_count, test_link_bw;
3942 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3943 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3947 DRM_DEBUG_KMS("Lane count read failed\n");
3950 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3951 /* Validate the requested lane count */
3952 if (test_lane_count < min_lane_count ||
3953 test_lane_count > intel_dp->max_sink_lane_count)
3956 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3959 DRM_DEBUG_KMS("Link Rate read failed\n");
3962 /* Validate the requested link rate */
3963 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3964 link_rate_index = intel_dp_link_rate_index(intel_dp,
3967 if (link_rate_index < 0)
3970 intel_dp->compliance.test_lane_count = test_lane_count;
3971 intel_dp->compliance.test_link_rate = test_link_rate;
3976 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3978 uint8_t test_pattern;
3980 __be16 h_width, v_height;
3983 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3984 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_PATTERN,
3987 DRM_DEBUG_KMS("Test pattern read failed\n");
3990 if (test_pattern != DP_COLOR_RAMP)
3993 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3996 DRM_DEBUG_KMS("H Width read failed\n");
4000 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4003 DRM_DEBUG_KMS("V Height read failed\n");
4007 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_MISC0,
4010 DRM_DEBUG_KMS("TEST MISC read failed\n");
4013 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4015 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4017 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4018 case DP_TEST_BIT_DEPTH_6:
4019 intel_dp->compliance.test_data.bpc = 6;
4021 case DP_TEST_BIT_DEPTH_8:
4022 intel_dp->compliance.test_data.bpc = 8;
4028 intel_dp->compliance.test_data.video_pattern = test_pattern;
4029 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4030 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4031 /* Set test active flag here so userspace doesn't interrupt things */
4032 intel_dp->compliance.test_active = 1;
4037 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4039 uint8_t test_result = DP_TEST_ACK;
4040 struct intel_connector *intel_connector = intel_dp->attached_connector;
4041 struct drm_connector *connector = &intel_connector->base;
4043 if (intel_connector->detect_edid == NULL ||
4044 connector->edid_corrupt ||
4045 intel_dp->aux.i2c_defer_count > 6) {
4046 /* Check EDID read for NACKs, DEFERs and corruption
4047 * (DP CTS 1.2 Core r1.1)
4048 * 4.2.2.4 : Failed EDID read, I2C_NAK
4049 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4050 * 4.2.2.6 : EDID corruption detected
4051 * Use failsafe mode for all cases
4053 if (intel_dp->aux.i2c_nack_count > 0 ||
4054 intel_dp->aux.i2c_defer_count > 0)
4055 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4056 intel_dp->aux.i2c_nack_count,
4057 intel_dp->aux.i2c_defer_count);
4058 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4060 struct edid *block = intel_connector->detect_edid;
4062 /* We have to write the checksum
4063 * of the last block read
4065 block += intel_connector->detect_edid->extensions;
4067 if (!drm_dp_dpcd_write(&intel_dp->aux,
4068 DP_TEST_EDID_CHECKSUM,
4071 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4073 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4074 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4077 /* Set test active flag here so userspace doesn't interrupt things */
4078 intel_dp->compliance.test_active = 1;
4083 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4085 uint8_t test_result = DP_TEST_NAK;
4089 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4091 uint8_t response = DP_TEST_NAK;
4092 uint8_t request = 0;
4095 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4097 DRM_DEBUG_KMS("Could not read test request from sink\n");
4102 case DP_TEST_LINK_TRAINING:
4103 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4104 response = intel_dp_autotest_link_training(intel_dp);
4106 case DP_TEST_LINK_VIDEO_PATTERN:
4107 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4108 response = intel_dp_autotest_video_pattern(intel_dp);
4110 case DP_TEST_LINK_EDID_READ:
4111 DRM_DEBUG_KMS("EDID test requested\n");
4112 response = intel_dp_autotest_edid(intel_dp);
4114 case DP_TEST_LINK_PHY_TEST_PATTERN:
4115 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4116 response = intel_dp_autotest_phy_pattern(intel_dp);
4119 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4123 if (response & DP_TEST_ACK)
4124 intel_dp->compliance.test_type = request;
4127 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4129 DRM_DEBUG_KMS("Could not write test response to sink\n");
4133 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4137 if (intel_dp->is_mst) {
4142 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4146 /* check link status - esi[10] = 0x200c */
4147 if (intel_dp->active_mst_links &&
4148 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4149 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4150 intel_dp_start_link_train(intel_dp);
4151 intel_dp_stop_link_train(intel_dp);
4154 DRM_DEBUG_KMS("got esi %3ph\n", esi);
4155 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4158 for (retry = 0; retry < 3; retry++) {
4160 wret = drm_dp_dpcd_write(&intel_dp->aux,
4161 DP_SINK_COUNT_ESI+1,
4168 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4170 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4178 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4179 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4180 intel_dp->is_mst = false;
4181 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4182 /* send a hotplug event */
4183 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4190 intel_dp_retrain_link(struct intel_dp *intel_dp)
4192 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4193 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4194 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4196 /* Suppress underruns caused by re-training */
4197 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4198 if (crtc->config->has_pch_encoder)
4199 intel_set_pch_fifo_underrun_reporting(dev_priv,
4200 intel_crtc_pch_transcoder(crtc), false);
4202 intel_dp_start_link_train(intel_dp);
4203 intel_dp_stop_link_train(intel_dp);
4205 /* Keep underrun reporting disabled until things are stable */
4206 intel_wait_for_vblank(dev_priv, crtc->pipe);
4208 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4209 if (crtc->config->has_pch_encoder)
4210 intel_set_pch_fifo_underrun_reporting(dev_priv,
4211 intel_crtc_pch_transcoder(crtc), true);
4215 intel_dp_check_link_status(struct intel_dp *intel_dp)
4217 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4218 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4219 u8 link_status[DP_LINK_STATUS_SIZE];
4221 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4223 if (!intel_dp_get_link_status(intel_dp, link_status)) {
4224 DRM_ERROR("Failed to get link status\n");
4228 if (!intel_encoder->base.crtc)
4231 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4234 /* FIXME: we need to synchronize this sort of stuff with hardware
4235 * readout. Currently fast link training doesn't work on boot-up. */
4236 if (!intel_dp->lane_count)
4239 /* Retrain if Channel EQ or CR not ok */
4240 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4241 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4242 intel_encoder->base.name);
4244 intel_dp_retrain_link(intel_dp);
4249 * According to DP spec
4252 * 2. Configure link according to Receiver Capabilities
4253 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4254 * 4. Check link status on receipt of hot-plug interrupt
4256 * intel_dp_short_pulse - handles short pulse interrupts
4257 * when full detection is not required.
4258 * Returns %true if short pulse is handled and full detection
4259 * is NOT required and %false otherwise.
4262 intel_dp_short_pulse(struct intel_dp *intel_dp)
4264 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4265 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4266 u8 sink_irq_vector = 0;
4267 u8 old_sink_count = intel_dp->sink_count;
4271 * Clearing compliance test variables to allow capturing
4272 * of values for next automated test request.
4274 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4277 * Now read the DPCD to see if it's actually running
4278 * If the current value of sink count doesn't match with
4279 * the value that was stored earlier or dpcd read failed
4280 * we need to do full detection
4282 ret = intel_dp_get_dpcd(intel_dp);
4284 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4285 /* No need to proceed if we are going to do full detect */
4289 /* Try to read the source of the interrupt */
4290 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4291 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4292 sink_irq_vector != 0) {
4293 /* Clear interrupt source */
4294 drm_dp_dpcd_writeb(&intel_dp->aux,
4295 DP_DEVICE_SERVICE_IRQ_VECTOR,
4298 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4299 intel_dp_handle_test_request(intel_dp);
4300 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4301 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4304 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4305 intel_dp_check_link_status(intel_dp);
4306 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4307 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4308 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4309 /* Send a Hotplug Uevent to userspace to start modeset */
4310 drm_kms_helper_hotplug_event(intel_encoder->base.dev);
4316 /* XXX this is probably wrong for multiple downstream ports */
4317 static enum drm_connector_status
4318 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4320 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4321 uint8_t *dpcd = intel_dp->dpcd;
4325 lspcon_resume(lspcon);
4327 if (!intel_dp_get_dpcd(intel_dp))
4328 return connector_status_disconnected;
4330 if (is_edp(intel_dp))
4331 return connector_status_connected;
4333 /* if there's no downstream port, we're done */
4334 if (!drm_dp_is_branch(dpcd))
4335 return connector_status_connected;
4337 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4338 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4339 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4341 return intel_dp->sink_count ?
4342 connector_status_connected : connector_status_disconnected;
4345 if (intel_dp_can_mst(intel_dp))
4346 return connector_status_connected;
4348 /* If no HPD, poke DDC gently */
4349 if (drm_probe_ddc(&intel_dp->aux.ddc))
4350 return connector_status_connected;
4352 /* Well we tried, say unknown for unreliable port types */
4353 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4354 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4355 if (type == DP_DS_PORT_TYPE_VGA ||
4356 type == DP_DS_PORT_TYPE_NON_EDID)
4357 return connector_status_unknown;
4359 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4360 DP_DWN_STRM_PORT_TYPE_MASK;
4361 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4362 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4363 return connector_status_unknown;
4366 /* Anything else is out of spec, warn and ignore */
4367 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4368 return connector_status_disconnected;
4371 static enum drm_connector_status
4372 edp_detect(struct intel_dp *intel_dp)
4374 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4375 struct drm_i915_private *dev_priv = to_i915(dev);
4376 enum drm_connector_status status;
4378 status = intel_panel_detect(dev_priv);
4379 if (status == connector_status_unknown)
4380 status = connector_status_connected;
4385 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4386 struct intel_digital_port *port)
4390 switch (port->port) {
4394 bit = SDE_PORTB_HOTPLUG;
4397 bit = SDE_PORTC_HOTPLUG;
4400 bit = SDE_PORTD_HOTPLUG;
4403 MISSING_CASE(port->port);
4407 return I915_READ(SDEISR) & bit;
4410 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4411 struct intel_digital_port *port)
4415 switch (port->port) {
4419 bit = SDE_PORTB_HOTPLUG_CPT;
4422 bit = SDE_PORTC_HOTPLUG_CPT;
4425 bit = SDE_PORTD_HOTPLUG_CPT;
4428 bit = SDE_PORTE_HOTPLUG_SPT;
4431 MISSING_CASE(port->port);
4435 return I915_READ(SDEISR) & bit;
4438 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4439 struct intel_digital_port *port)
4443 switch (port->port) {
4445 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4448 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4451 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4454 MISSING_CASE(port->port);
4458 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4461 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4462 struct intel_digital_port *port)
4466 switch (port->port) {
4468 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4471 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4474 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4477 MISSING_CASE(port->port);
4481 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4484 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4485 struct intel_digital_port *intel_dig_port)
4487 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4491 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4494 bit = BXT_DE_PORT_HP_DDIA;
4497 bit = BXT_DE_PORT_HP_DDIB;
4500 bit = BXT_DE_PORT_HP_DDIC;
4507 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4511 * intel_digital_port_connected - is the specified port connected?
4512 * @dev_priv: i915 private structure
4513 * @port: the port to test
4515 * Return %true if @port is connected, %false otherwise.
4517 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4518 struct intel_digital_port *port)
4520 if (HAS_PCH_IBX(dev_priv))
4521 return ibx_digital_port_connected(dev_priv, port);
4522 else if (HAS_PCH_SPLIT(dev_priv))
4523 return cpt_digital_port_connected(dev_priv, port);
4524 else if (IS_GEN9_LP(dev_priv))
4525 return bxt_digital_port_connected(dev_priv, port);
4526 else if (IS_GM45(dev_priv))
4527 return gm45_digital_port_connected(dev_priv, port);
4529 return g4x_digital_port_connected(dev_priv, port);
4532 static struct edid *
4533 intel_dp_get_edid(struct intel_dp *intel_dp)
4535 struct intel_connector *intel_connector = intel_dp->attached_connector;
4537 /* use cached edid if we have one */
4538 if (intel_connector->edid) {
4540 if (IS_ERR(intel_connector->edid))
4543 return drm_edid_duplicate(intel_connector->edid);
4545 return drm_get_edid(&intel_connector->base,
4546 &intel_dp->aux.ddc);
4550 intel_dp_set_edid(struct intel_dp *intel_dp)
4552 struct intel_connector *intel_connector = intel_dp->attached_connector;
4555 intel_dp_unset_edid(intel_dp);
4556 edid = intel_dp_get_edid(intel_dp);
4557 intel_connector->detect_edid = edid;
4559 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4560 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4562 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4566 intel_dp_unset_edid(struct intel_dp *intel_dp)
4568 struct intel_connector *intel_connector = intel_dp->attached_connector;
4570 kfree(intel_connector->detect_edid);
4571 intel_connector->detect_edid = NULL;
4573 intel_dp->has_audio = false;
4576 static enum drm_connector_status
4577 intel_dp_long_pulse(struct intel_connector *intel_connector)
4579 struct drm_connector *connector = &intel_connector->base;
4580 struct intel_dp *intel_dp = intel_attached_dp(connector);
4581 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4582 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4583 struct drm_device *dev = connector->dev;
4584 enum drm_connector_status status;
4585 u8 sink_irq_vector = 0;
4587 intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain);
4589 /* Can't disconnect eDP, but you can close the lid... */
4590 if (is_edp(intel_dp))
4591 status = edp_detect(intel_dp);
4592 else if (intel_digital_port_connected(to_i915(dev),
4593 dp_to_dig_port(intel_dp)))
4594 status = intel_dp_detect_dpcd(intel_dp);
4596 status = connector_status_disconnected;
4598 if (status == connector_status_disconnected) {
4599 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4601 if (intel_dp->is_mst) {
4602 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4604 intel_dp->mst_mgr.mst_state);
4605 intel_dp->is_mst = false;
4606 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4613 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4614 intel_encoder->type = INTEL_OUTPUT_DP;
4616 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4617 yesno(intel_dp_source_supports_hbr2(intel_dp)),
4618 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4620 if (intel_dp->reset_link_params) {
4621 /* Set the max lane count for sink */
4622 intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
4624 /* Set the max link BW for sink */
4625 intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
4627 intel_dp->reset_link_params = false;
4630 intel_dp_print_rates(intel_dp);
4632 intel_dp_read_desc(intel_dp);
4634 intel_dp_configure_mst(intel_dp);
4636 if (intel_dp->is_mst) {
4638 * If we are in MST mode then this connector
4639 * won't appear connected or have anything
4642 status = connector_status_disconnected;
4644 } else if (connector->status == connector_status_connected) {
4646 * If display was connected already and is still connected
4647 * check links status, there has been known issues of
4648 * link loss triggerring long pulse!!!!
4650 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4651 intel_dp_check_link_status(intel_dp);
4652 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4657 * Clearing NACK and defer counts to get their exact values
4658 * while reading EDID which are required by Compliance tests
4659 * 4.2.2.4 and 4.2.2.5
4661 intel_dp->aux.i2c_nack_count = 0;
4662 intel_dp->aux.i2c_defer_count = 0;
4664 intel_dp_set_edid(intel_dp);
4665 if (is_edp(intel_dp) || intel_connector->detect_edid)
4666 status = connector_status_connected;
4667 intel_dp->detect_done = true;
4669 /* Try to read the source of the interrupt */
4670 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4671 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4672 sink_irq_vector != 0) {
4673 /* Clear interrupt source */
4674 drm_dp_dpcd_writeb(&intel_dp->aux,
4675 DP_DEVICE_SERVICE_IRQ_VECTOR,
4678 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4679 intel_dp_handle_test_request(intel_dp);
4680 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4681 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4685 if (status != connector_status_connected && !intel_dp->is_mst)
4686 intel_dp_unset_edid(intel_dp);
4688 intel_display_power_put(to_i915(dev), intel_dp->aux_power_domain);
4692 static enum drm_connector_status
4693 intel_dp_detect(struct drm_connector *connector, bool force)
4695 struct intel_dp *intel_dp = intel_attached_dp(connector);
4696 enum drm_connector_status status = connector->status;
4698 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4699 connector->base.id, connector->name);
4701 /* If full detect is not performed yet, do a full detect */
4702 if (!intel_dp->detect_done)
4703 status = intel_dp_long_pulse(intel_dp->attached_connector);
4705 intel_dp->detect_done = false;
4711 intel_dp_force(struct drm_connector *connector)
4713 struct intel_dp *intel_dp = intel_attached_dp(connector);
4714 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4715 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4717 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4718 connector->base.id, connector->name);
4719 intel_dp_unset_edid(intel_dp);
4721 if (connector->status != connector_status_connected)
4724 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4726 intel_dp_set_edid(intel_dp);
4728 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4730 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4731 intel_encoder->type = INTEL_OUTPUT_DP;
4734 static int intel_dp_get_modes(struct drm_connector *connector)
4736 struct intel_connector *intel_connector = to_intel_connector(connector);
4739 edid = intel_connector->detect_edid;
4741 int ret = intel_connector_update_modes(connector, edid);
4746 /* if eDP has no EDID, fall back to fixed mode */
4747 if (is_edp(intel_attached_dp(connector)) &&
4748 intel_connector->panel.fixed_mode) {
4749 struct drm_display_mode *mode;
4751 mode = drm_mode_duplicate(connector->dev,
4752 intel_connector->panel.fixed_mode);
4754 drm_mode_probed_add(connector, mode);
4763 intel_dp_detect_audio(struct drm_connector *connector)
4765 bool has_audio = false;
4768 edid = to_intel_connector(connector)->detect_edid;
4770 has_audio = drm_detect_monitor_audio(edid);
4776 intel_dp_set_property(struct drm_connector *connector,
4777 struct drm_property *property,
4780 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4781 struct intel_connector *intel_connector = to_intel_connector(connector);
4782 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4783 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4786 ret = drm_object_property_set_value(&connector->base, property, val);
4790 if (property == dev_priv->force_audio_property) {
4794 if (i == intel_dp->force_audio)
4797 intel_dp->force_audio = i;
4799 if (i == HDMI_AUDIO_AUTO)
4800 has_audio = intel_dp_detect_audio(connector);
4802 has_audio = (i == HDMI_AUDIO_ON);
4804 if (has_audio == intel_dp->has_audio)
4807 intel_dp->has_audio = has_audio;
4811 if (property == dev_priv->broadcast_rgb_property) {
4812 bool old_auto = intel_dp->color_range_auto;
4813 bool old_range = intel_dp->limited_color_range;
4816 case INTEL_BROADCAST_RGB_AUTO:
4817 intel_dp->color_range_auto = true;
4819 case INTEL_BROADCAST_RGB_FULL:
4820 intel_dp->color_range_auto = false;
4821 intel_dp->limited_color_range = false;
4823 case INTEL_BROADCAST_RGB_LIMITED:
4824 intel_dp->color_range_auto = false;
4825 intel_dp->limited_color_range = true;
4831 if (old_auto == intel_dp->color_range_auto &&
4832 old_range == intel_dp->limited_color_range)
4838 if (is_edp(intel_dp) &&
4839 property == connector->dev->mode_config.scaling_mode_property) {
4840 if (val == DRM_MODE_SCALE_NONE) {
4841 DRM_DEBUG_KMS("no scaling not supported\n");
4844 if (HAS_GMCH_DISPLAY(dev_priv) &&
4845 val == DRM_MODE_SCALE_CENTER) {
4846 DRM_DEBUG_KMS("centering not supported\n");
4850 if (intel_connector->panel.fitting_mode == val) {
4851 /* the eDP scaling property is not changed */
4854 intel_connector->panel.fitting_mode = val;
4862 if (intel_encoder->base.crtc)
4863 intel_crtc_restore_mode(intel_encoder->base.crtc);
4869 intel_dp_connector_register(struct drm_connector *connector)
4871 struct intel_dp *intel_dp = intel_attached_dp(connector);
4874 ret = intel_connector_register(connector);
4878 i915_debugfs_connector_add(connector);
4880 DRM_DEBUG_KMS("registering %s bus for %s\n",
4881 intel_dp->aux.name, connector->kdev->kobj.name);
4883 intel_dp->aux.dev = connector->kdev;
4884 return drm_dp_aux_register(&intel_dp->aux);
4888 intel_dp_connector_unregister(struct drm_connector *connector)
4890 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4891 intel_connector_unregister(connector);
4895 intel_dp_connector_destroy(struct drm_connector *connector)
4897 struct intel_connector *intel_connector = to_intel_connector(connector);
4899 kfree(intel_connector->detect_edid);
4901 if (!IS_ERR_OR_NULL(intel_connector->edid))
4902 kfree(intel_connector->edid);
4904 /* Can't call is_edp() since the encoder may have been destroyed
4906 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4907 intel_panel_fini(&intel_connector->panel);
4909 drm_connector_cleanup(connector);
4913 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4915 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4916 struct intel_dp *intel_dp = &intel_dig_port->dp;
4918 intel_dp_mst_encoder_cleanup(intel_dig_port);
4919 if (is_edp(intel_dp)) {
4920 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4922 * vdd might still be enabled do to the delayed vdd off.
4923 * Make sure vdd is actually turned off here.
4926 edp_panel_vdd_off_sync(intel_dp);
4927 pps_unlock(intel_dp);
4929 if (intel_dp->edp_notifier.notifier_call) {
4930 unregister_reboot_notifier(&intel_dp->edp_notifier);
4931 intel_dp->edp_notifier.notifier_call = NULL;
4935 intel_dp_aux_fini(intel_dp);
4937 drm_encoder_cleanup(encoder);
4938 kfree(intel_dig_port);
4941 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4943 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4945 if (!is_edp(intel_dp))
4949 * vdd might still be enabled do to the delayed vdd off.
4950 * Make sure vdd is actually turned off here.
4952 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4954 edp_panel_vdd_off_sync(intel_dp);
4955 pps_unlock(intel_dp);
4958 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4960 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4961 struct drm_device *dev = intel_dig_port->base.base.dev;
4962 struct drm_i915_private *dev_priv = to_i915(dev);
4964 lockdep_assert_held(&dev_priv->pps_mutex);
4966 if (!edp_have_panel_vdd(intel_dp))
4970 * The VDD bit needs a power domain reference, so if the bit is
4971 * already enabled when we boot or resume, grab this reference and
4972 * schedule a vdd off, so we don't hold on to the reference
4975 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4976 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4978 edp_panel_vdd_schedule_off(intel_dp);
4981 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
4983 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4985 if ((intel_dp->DP & DP_PORT_EN) == 0)
4986 return INVALID_PIPE;
4988 if (IS_CHERRYVIEW(dev_priv))
4989 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
4991 return PORT_TO_PIPE(intel_dp->DP);
4994 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4996 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4997 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4998 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5000 if (!HAS_DDI(dev_priv))
5001 intel_dp->DP = I915_READ(intel_dp->output_reg);
5004 lspcon_resume(lspcon);
5006 intel_dp->reset_link_params = true;
5010 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5011 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5013 if (is_edp(intel_dp)) {
5014 /* Reinit the power sequencer, in case BIOS did something with it. */
5015 intel_dp_pps_init(encoder->dev, intel_dp);
5016 intel_edp_panel_vdd_sanitize(intel_dp);
5019 pps_unlock(intel_dp);
5022 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5023 .dpms = drm_atomic_helper_connector_dpms,
5024 .detect = intel_dp_detect,
5025 .force = intel_dp_force,
5026 .fill_modes = drm_helper_probe_single_connector_modes,
5027 .set_property = intel_dp_set_property,
5028 .atomic_get_property = intel_connector_atomic_get_property,
5029 .late_register = intel_dp_connector_register,
5030 .early_unregister = intel_dp_connector_unregister,
5031 .destroy = intel_dp_connector_destroy,
5032 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5033 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
5036 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5037 .get_modes = intel_dp_get_modes,
5038 .mode_valid = intel_dp_mode_valid,
5041 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5042 .reset = intel_dp_encoder_reset,
5043 .destroy = intel_dp_encoder_destroy,
5047 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5049 struct intel_dp *intel_dp = &intel_dig_port->dp;
5050 struct drm_device *dev = intel_dig_port->base.base.dev;
5051 struct drm_i915_private *dev_priv = to_i915(dev);
5052 enum irqreturn ret = IRQ_NONE;
5054 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
5055 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
5056 intel_dig_port->base.type = INTEL_OUTPUT_DP;
5058 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5060 * vdd off can generate a long pulse on eDP which
5061 * would require vdd on to handle it, and thus we
5062 * would end up in an endless cycle of
5063 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5065 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5066 port_name(intel_dig_port->port));
5070 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5071 port_name(intel_dig_port->port),
5072 long_hpd ? "long" : "short");
5075 intel_dp->reset_link_params = true;
5076 intel_dp->detect_done = false;
5080 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5082 if (intel_dp->is_mst) {
5083 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5085 * If we were in MST mode, and device is not
5086 * there, get out of MST mode
5088 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5089 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5090 intel_dp->is_mst = false;
5091 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5093 intel_dp->detect_done = false;
5098 if (!intel_dp->is_mst) {
5099 if (!intel_dp_short_pulse(intel_dp)) {
5100 intel_dp->detect_done = false;
5108 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5113 /* check the VBT to see whether the eDP is on another port */
5114 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port)
5117 * eDP not supported on g4x. so bail out early just
5118 * for a bit extra safety in case the VBT is bonkers.
5120 if (INTEL_GEN(dev_priv) < 5)
5123 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5126 return intel_bios_is_port_edp(dev_priv, port);
5130 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5132 struct intel_connector *intel_connector = to_intel_connector(connector);
5134 intel_attach_force_audio_property(connector);
5135 intel_attach_broadcast_rgb_property(connector);
5136 intel_dp->color_range_auto = true;
5138 if (is_edp(intel_dp)) {
5139 drm_mode_create_scaling_mode_property(connector->dev);
5140 drm_object_attach_property(
5142 connector->dev->mode_config.scaling_mode_property,
5143 DRM_MODE_SCALE_ASPECT);
5144 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5148 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5150 intel_dp->panel_power_off_time = ktime_get_boottime();
5151 intel_dp->last_power_on = jiffies;
5152 intel_dp->last_backlight_off = jiffies;
5156 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
5157 struct intel_dp *intel_dp, struct edp_power_seq *seq)
5159 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5160 struct pps_registers regs;
5162 intel_pps_get_registers(dev_priv, intel_dp, ®s);
5164 /* Workaround: Need to write PP_CONTROL with the unlock key as
5165 * the very first thing. */
5166 pp_ctl = ironlake_get_pp_control(intel_dp);
5168 pp_on = I915_READ(regs.pp_on);
5169 pp_off = I915_READ(regs.pp_off);
5170 if (!IS_GEN9_LP(dev_priv)) {
5171 I915_WRITE(regs.pp_ctrl, pp_ctl);
5172 pp_div = I915_READ(regs.pp_div);
5175 /* Pull timing values out of registers */
5176 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5177 PANEL_POWER_UP_DELAY_SHIFT;
5179 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5180 PANEL_LIGHT_ON_DELAY_SHIFT;
5182 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5183 PANEL_LIGHT_OFF_DELAY_SHIFT;
5185 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5186 PANEL_POWER_DOWN_DELAY_SHIFT;
5188 if (IS_GEN9_LP(dev_priv)) {
5189 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5190 BXT_POWER_CYCLE_DELAY_SHIFT;
5192 seq->t11_t12 = (tmp - 1) * 1000;
5196 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5197 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5202 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5204 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5206 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5210 intel_pps_verify_state(struct drm_i915_private *dev_priv,
5211 struct intel_dp *intel_dp)
5213 struct edp_power_seq hw;
5214 struct edp_power_seq *sw = &intel_dp->pps_delays;
5216 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
5218 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5219 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5220 DRM_ERROR("PPS state mismatch\n");
5221 intel_pps_dump_state("sw", sw);
5222 intel_pps_dump_state("hw", &hw);
5227 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5228 struct intel_dp *intel_dp)
5230 struct drm_i915_private *dev_priv = to_i915(dev);
5231 struct edp_power_seq cur, vbt, spec,
5232 *final = &intel_dp->pps_delays;
5234 lockdep_assert_held(&dev_priv->pps_mutex);
5236 /* already initialized? */
5237 if (final->t11_t12 != 0)
5240 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5242 intel_pps_dump_state("cur", &cur);
5244 vbt = dev_priv->vbt.edp.pps;
5246 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5247 * our hw here, which are all in 100usec. */
5248 spec.t1_t3 = 210 * 10;
5249 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5250 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5251 spec.t10 = 500 * 10;
5252 /* This one is special and actually in units of 100ms, but zero
5253 * based in the hw (so we need to add 100 ms). But the sw vbt
5254 * table multiplies it with 1000 to make it in units of 100usec,
5256 spec.t11_t12 = (510 + 100) * 10;
5258 intel_pps_dump_state("vbt", &vbt);
5260 /* Use the max of the register settings and vbt. If both are
5261 * unset, fall back to the spec limits. */
5262 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5264 max(cur.field, vbt.field))
5265 assign_final(t1_t3);
5269 assign_final(t11_t12);
5272 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5273 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5274 intel_dp->backlight_on_delay = get_delay(t8);
5275 intel_dp->backlight_off_delay = get_delay(t9);
5276 intel_dp->panel_power_down_delay = get_delay(t10);
5277 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5280 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5281 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5282 intel_dp->panel_power_cycle_delay);
5284 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5285 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5288 * We override the HW backlight delays to 1 because we do manual waits
5289 * on them. For T8, even BSpec recommends doing it. For T9, if we
5290 * don't do this, we'll end up waiting for the backlight off delay
5291 * twice: once when we do the manual sleep, and once when we disable
5292 * the panel and wait for the PP_STATUS bit to become zero.
5299 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5300 struct intel_dp *intel_dp,
5301 bool force_disable_vdd)
5303 struct drm_i915_private *dev_priv = to_i915(dev);
5304 u32 pp_on, pp_off, pp_div, port_sel = 0;
5305 int div = dev_priv->rawclk_freq / 1000;
5306 struct pps_registers regs;
5307 enum port port = dp_to_dig_port(intel_dp)->port;
5308 const struct edp_power_seq *seq = &intel_dp->pps_delays;
5310 lockdep_assert_held(&dev_priv->pps_mutex);
5312 intel_pps_get_registers(dev_priv, intel_dp, ®s);
5315 * On some VLV machines the BIOS can leave the VDD
5316 * enabled even on power seqeuencers which aren't
5317 * hooked up to any port. This would mess up the
5318 * power domain tracking the first time we pick
5319 * one of these power sequencers for use since
5320 * edp_panel_vdd_on() would notice that the VDD was
5321 * already on and therefore wouldn't grab the power
5322 * domain reference. Disable VDD first to avoid this.
5323 * This also avoids spuriously turning the VDD on as
5324 * soon as the new power seqeuencer gets initialized.
5326 if (force_disable_vdd) {
5327 u32 pp = ironlake_get_pp_control(intel_dp);
5329 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5331 if (pp & EDP_FORCE_VDD)
5332 DRM_DEBUG_KMS("VDD already on, disabling first\n");
5334 pp &= ~EDP_FORCE_VDD;
5336 I915_WRITE(regs.pp_ctrl, pp);
5339 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5340 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5341 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5342 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5343 /* Compute the divisor for the pp clock, simply match the Bspec
5345 if (IS_GEN9_LP(dev_priv)) {
5346 pp_div = I915_READ(regs.pp_ctrl);
5347 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5348 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5349 << BXT_POWER_CYCLE_DELAY_SHIFT);
5351 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5352 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5353 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5356 /* Haswell doesn't have any port selection bits for the panel
5357 * power sequencer any more. */
5358 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5359 port_sel = PANEL_PORT_SELECT_VLV(port);
5360 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5362 port_sel = PANEL_PORT_SELECT_DPA;
5364 port_sel = PANEL_PORT_SELECT_DPD;
5369 I915_WRITE(regs.pp_on, pp_on);
5370 I915_WRITE(regs.pp_off, pp_off);
5371 if (IS_GEN9_LP(dev_priv))
5372 I915_WRITE(regs.pp_ctrl, pp_div);
5374 I915_WRITE(regs.pp_div, pp_div);
5376 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5377 I915_READ(regs.pp_on),
5378 I915_READ(regs.pp_off),
5379 IS_GEN9_LP(dev_priv) ?
5380 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5381 I915_READ(regs.pp_div));
5384 static void intel_dp_pps_init(struct drm_device *dev,
5385 struct intel_dp *intel_dp)
5387 struct drm_i915_private *dev_priv = to_i915(dev);
5389 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5390 vlv_initial_power_sequencer_setup(intel_dp);
5392 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5393 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
5398 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5399 * @dev_priv: i915 device
5400 * @crtc_state: a pointer to the active intel_crtc_state
5401 * @refresh_rate: RR to be programmed
5403 * This function gets called when refresh rate (RR) has to be changed from
5404 * one frequency to another. Switches can be between high and low RR
5405 * supported by the panel or to any other RR based on media playback (in
5406 * this case, RR value needs to be passed from user space).
5408 * The caller of this function needs to take a lock on dev_priv->drrs.
5410 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5411 struct intel_crtc_state *crtc_state,
5414 struct intel_encoder *encoder;
5415 struct intel_digital_port *dig_port = NULL;
5416 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5418 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5420 if (refresh_rate <= 0) {
5421 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5425 if (intel_dp == NULL) {
5426 DRM_DEBUG_KMS("DRRS not supported.\n");
5431 * FIXME: This needs proper synchronization with psr state for some
5432 * platforms that cannot have PSR and DRRS enabled at the same time.
5435 dig_port = dp_to_dig_port(intel_dp);
5436 encoder = &dig_port->base;
5437 intel_crtc = to_intel_crtc(encoder->base.crtc);
5440 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5444 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5445 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5449 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5451 index = DRRS_LOW_RR;
5453 if (index == dev_priv->drrs.refresh_rate_type) {
5455 "DRRS requested for previously set RR...ignoring\n");
5459 if (!crtc_state->base.active) {
5460 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5464 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5467 intel_dp_set_m_n(intel_crtc, M1_N1);
5470 intel_dp_set_m_n(intel_crtc, M2_N2);
5474 DRM_ERROR("Unsupported refreshrate type\n");
5476 } else if (INTEL_GEN(dev_priv) > 6) {
5477 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5480 val = I915_READ(reg);
5481 if (index > DRRS_HIGH_RR) {
5482 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5483 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5485 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5487 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5488 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5490 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5492 I915_WRITE(reg, val);
5495 dev_priv->drrs.refresh_rate_type = index;
5497 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5501 * intel_edp_drrs_enable - init drrs struct if supported
5502 * @intel_dp: DP struct
5503 * @crtc_state: A pointer to the active crtc state.
5505 * Initializes frontbuffer_bits and drrs.dp
5507 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5508 struct intel_crtc_state *crtc_state)
5510 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5511 struct drm_i915_private *dev_priv = to_i915(dev);
5513 if (!crtc_state->has_drrs) {
5514 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5518 mutex_lock(&dev_priv->drrs.mutex);
5519 if (WARN_ON(dev_priv->drrs.dp)) {
5520 DRM_ERROR("DRRS already enabled\n");
5524 dev_priv->drrs.busy_frontbuffer_bits = 0;
5526 dev_priv->drrs.dp = intel_dp;
5529 mutex_unlock(&dev_priv->drrs.mutex);
5533 * intel_edp_drrs_disable - Disable DRRS
5534 * @intel_dp: DP struct
5535 * @old_crtc_state: Pointer to old crtc_state.
5538 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5539 struct intel_crtc_state *old_crtc_state)
5541 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5542 struct drm_i915_private *dev_priv = to_i915(dev);
5544 if (!old_crtc_state->has_drrs)
5547 mutex_lock(&dev_priv->drrs.mutex);
5548 if (!dev_priv->drrs.dp) {
5549 mutex_unlock(&dev_priv->drrs.mutex);
5553 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5554 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5555 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5557 dev_priv->drrs.dp = NULL;
5558 mutex_unlock(&dev_priv->drrs.mutex);
5560 cancel_delayed_work_sync(&dev_priv->drrs.work);
5563 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5565 struct drm_i915_private *dev_priv =
5566 container_of(work, typeof(*dev_priv), drrs.work.work);
5567 struct intel_dp *intel_dp;
5569 mutex_lock(&dev_priv->drrs.mutex);
5571 intel_dp = dev_priv->drrs.dp;
5577 * The delayed work can race with an invalidate hence we need to
5581 if (dev_priv->drrs.busy_frontbuffer_bits)
5584 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5585 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5587 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5588 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5592 mutex_unlock(&dev_priv->drrs.mutex);
5596 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5597 * @dev_priv: i915 device
5598 * @frontbuffer_bits: frontbuffer plane tracking bits
5600 * This function gets called everytime rendering on the given planes start.
5601 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5603 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5605 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5606 unsigned int frontbuffer_bits)
5608 struct drm_crtc *crtc;
5611 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5614 cancel_delayed_work(&dev_priv->drrs.work);
5616 mutex_lock(&dev_priv->drrs.mutex);
5617 if (!dev_priv->drrs.dp) {
5618 mutex_unlock(&dev_priv->drrs.mutex);
5622 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5623 pipe = to_intel_crtc(crtc)->pipe;
5625 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5626 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5628 /* invalidate means busy screen hence upclock */
5629 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5630 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5631 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5633 mutex_unlock(&dev_priv->drrs.mutex);
5637 * intel_edp_drrs_flush - Restart Idleness DRRS
5638 * @dev_priv: i915 device
5639 * @frontbuffer_bits: frontbuffer plane tracking bits
5641 * This function gets called every time rendering on the given planes has
5642 * completed or flip on a crtc is completed. So DRRS should be upclocked
5643 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5644 * if no other planes are dirty.
5646 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5648 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5649 unsigned int frontbuffer_bits)
5651 struct drm_crtc *crtc;
5654 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5657 cancel_delayed_work(&dev_priv->drrs.work);
5659 mutex_lock(&dev_priv->drrs.mutex);
5660 if (!dev_priv->drrs.dp) {
5661 mutex_unlock(&dev_priv->drrs.mutex);
5665 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5666 pipe = to_intel_crtc(crtc)->pipe;
5668 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5669 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5671 /* flush means busy screen hence upclock */
5672 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5673 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5674 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5677 * flush also means no more activity hence schedule downclock, if all
5678 * other fbs are quiescent too
5680 if (!dev_priv->drrs.busy_frontbuffer_bits)
5681 schedule_delayed_work(&dev_priv->drrs.work,
5682 msecs_to_jiffies(1000));
5683 mutex_unlock(&dev_priv->drrs.mutex);
5687 * DOC: Display Refresh Rate Switching (DRRS)
5689 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5690 * which enables swtching between low and high refresh rates,
5691 * dynamically, based on the usage scenario. This feature is applicable
5692 * for internal panels.
5694 * Indication that the panel supports DRRS is given by the panel EDID, which
5695 * would list multiple refresh rates for one resolution.
5697 * DRRS is of 2 types - static and seamless.
5698 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5699 * (may appear as a blink on screen) and is used in dock-undock scenario.
5700 * Seamless DRRS involves changing RR without any visual effect to the user
5701 * and can be used during normal system usage. This is done by programming
5702 * certain registers.
5704 * Support for static/seamless DRRS may be indicated in the VBT based on
5705 * inputs from the panel spec.
5707 * DRRS saves power by switching to low RR based on usage scenarios.
5709 * The implementation is based on frontbuffer tracking implementation. When
5710 * there is a disturbance on the screen triggered by user activity or a periodic
5711 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5712 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5715 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5716 * and intel_edp_drrs_flush() are called.
5718 * DRRS can be further extended to support other internal panels and also
5719 * the scenario of video playback wherein RR is set based on the rate
5720 * requested by userspace.
5724 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5725 * @intel_connector: eDP connector
5726 * @fixed_mode: preferred mode of panel
5728 * This function is called only once at driver load to initialize basic
5732 * Downclock mode if panel supports it, else return NULL.
5733 * DRRS support is determined by the presence of downclock mode (apart
5734 * from VBT setting).
5736 static struct drm_display_mode *
5737 intel_dp_drrs_init(struct intel_connector *intel_connector,
5738 struct drm_display_mode *fixed_mode)
5740 struct drm_connector *connector = &intel_connector->base;
5741 struct drm_device *dev = connector->dev;
5742 struct drm_i915_private *dev_priv = to_i915(dev);
5743 struct drm_display_mode *downclock_mode = NULL;
5745 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5746 mutex_init(&dev_priv->drrs.mutex);
5748 if (INTEL_GEN(dev_priv) <= 6) {
5749 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5753 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5754 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5758 downclock_mode = intel_find_panel_downclock
5759 (dev_priv, fixed_mode, connector);
5761 if (!downclock_mode) {
5762 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5766 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5768 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5769 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5770 return downclock_mode;
5773 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5774 struct intel_connector *intel_connector)
5776 struct drm_connector *connector = &intel_connector->base;
5777 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5778 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5779 struct drm_device *dev = intel_encoder->base.dev;
5780 struct drm_i915_private *dev_priv = to_i915(dev);
5781 struct drm_display_mode *fixed_mode = NULL;
5782 struct drm_display_mode *downclock_mode = NULL;
5784 struct drm_display_mode *scan;
5786 enum pipe pipe = INVALID_PIPE;
5788 if (!is_edp(intel_dp))
5792 * On IBX/CPT we may get here with LVDS already registered. Since the
5793 * driver uses the only internal power sequencer available for both
5794 * eDP and LVDS bail out early in this case to prevent interfering
5795 * with an already powered-on LVDS power sequencer.
5797 if (intel_get_lvds_encoder(dev)) {
5798 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5799 DRM_INFO("LVDS was detected, not registering eDP\n");
5806 intel_dp_init_panel_power_timestamps(intel_dp);
5807 intel_dp_pps_init(dev, intel_dp);
5808 intel_edp_panel_vdd_sanitize(intel_dp);
5810 pps_unlock(intel_dp);
5812 /* Cache DPCD and EDID for edp. */
5813 has_dpcd = intel_edp_init_dpcd(intel_dp);
5816 /* if this fails, presume the device is a ghost */
5817 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5821 mutex_lock(&dev->mode_config.mutex);
5822 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5824 if (drm_add_edid_modes(connector, edid)) {
5825 drm_mode_connector_update_edid_property(connector,
5827 drm_edid_to_eld(connector, edid);
5830 edid = ERR_PTR(-EINVAL);
5833 edid = ERR_PTR(-ENOENT);
5835 intel_connector->edid = edid;
5837 /* prefer fixed mode from EDID if available */
5838 list_for_each_entry(scan, &connector->probed_modes, head) {
5839 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5840 fixed_mode = drm_mode_duplicate(dev, scan);
5841 downclock_mode = intel_dp_drrs_init(
5842 intel_connector, fixed_mode);
5847 /* fallback to VBT if available for eDP */
5848 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5849 fixed_mode = drm_mode_duplicate(dev,
5850 dev_priv->vbt.lfp_lvds_vbt_mode);
5852 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5853 connector->display_info.width_mm = fixed_mode->width_mm;
5854 connector->display_info.height_mm = fixed_mode->height_mm;
5857 mutex_unlock(&dev->mode_config.mutex);
5859 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5860 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5861 register_reboot_notifier(&intel_dp->edp_notifier);
5864 * Figure out the current pipe for the initial backlight setup.
5865 * If the current pipe isn't valid, try the PPS pipe, and if that
5866 * fails just assume pipe A.
5868 pipe = vlv_active_pipe(intel_dp);
5870 if (pipe != PIPE_A && pipe != PIPE_B)
5871 pipe = intel_dp->pps_pipe;
5873 if (pipe != PIPE_A && pipe != PIPE_B)
5876 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5880 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5881 intel_connector->panel.backlight.power = intel_edp_backlight_power;
5882 intel_panel_setup_backlight(connector, pipe);
5887 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5889 * vdd might still be enabled do to the delayed vdd off.
5890 * Make sure vdd is actually turned off here.
5893 edp_panel_vdd_off_sync(intel_dp);
5894 pps_unlock(intel_dp);
5899 /* Set up the hotplug pin and aux power domain. */
5901 intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
5903 struct intel_encoder *encoder = &intel_dig_port->base;
5904 struct intel_dp *intel_dp = &intel_dig_port->dp;
5906 switch (intel_dig_port->port) {
5908 encoder->hpd_pin = HPD_PORT_A;
5909 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A;
5912 encoder->hpd_pin = HPD_PORT_B;
5913 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B;
5916 encoder->hpd_pin = HPD_PORT_C;
5917 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C;
5920 encoder->hpd_pin = HPD_PORT_D;
5921 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5924 encoder->hpd_pin = HPD_PORT_E;
5926 /* FIXME: Check VBT for actual wiring of PORT E */
5927 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5930 MISSING_CASE(intel_dig_port->port);
5935 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5936 struct intel_connector *intel_connector)
5938 struct drm_connector *connector = &intel_connector->base;
5939 struct intel_dp *intel_dp = &intel_dig_port->dp;
5940 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5941 struct drm_device *dev = intel_encoder->base.dev;
5942 struct drm_i915_private *dev_priv = to_i915(dev);
5943 enum port port = intel_dig_port->port;
5946 if (WARN(intel_dig_port->max_lanes < 1,
5947 "Not enough lanes (%d) for DP on port %c\n",
5948 intel_dig_port->max_lanes, port_name(port)))
5951 intel_dp_set_source_rates(intel_dp);
5953 intel_dp->reset_link_params = true;
5954 intel_dp->pps_pipe = INVALID_PIPE;
5955 intel_dp->active_pipe = INVALID_PIPE;
5957 /* intel_dp vfuncs */
5958 if (INTEL_GEN(dev_priv) >= 9)
5959 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5960 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5961 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5962 else if (HAS_PCH_SPLIT(dev_priv))
5963 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5965 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5967 if (INTEL_GEN(dev_priv) >= 9)
5968 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5970 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5972 if (HAS_DDI(dev_priv))
5973 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5975 /* Preserve the current hw state. */
5976 intel_dp->DP = I915_READ(intel_dp->output_reg);
5977 intel_dp->attached_connector = intel_connector;
5979 if (intel_dp_is_edp(dev_priv, port))
5980 type = DRM_MODE_CONNECTOR_eDP;
5982 type = DRM_MODE_CONNECTOR_DisplayPort;
5984 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5985 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5988 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5989 * for DP the encoder type can be set by the caller to
5990 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5992 if (type == DRM_MODE_CONNECTOR_eDP)
5993 intel_encoder->type = INTEL_OUTPUT_EDP;
5995 /* eDP only on port B and/or C on vlv/chv */
5996 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
5997 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
6000 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6001 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6004 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6005 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6007 connector->interlace_allowed = true;
6008 connector->doublescan_allowed = 0;
6010 intel_dp_init_connector_port_info(intel_dig_port);
6012 intel_dp_aux_init(intel_dp);
6014 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6015 edp_panel_vdd_work);
6017 intel_connector_attach_encoder(intel_connector, intel_encoder);
6019 if (HAS_DDI(dev_priv))
6020 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6022 intel_connector->get_hw_state = intel_connector_get_hw_state;
6024 /* init MST on ports that can support it */
6025 if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
6026 (port == PORT_B || port == PORT_C || port == PORT_D))
6027 intel_dp_mst_encoder_init(intel_dig_port,
6028 intel_connector->base.base.id);
6030 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6031 intel_dp_aux_fini(intel_dp);
6032 intel_dp_mst_encoder_cleanup(intel_dig_port);
6036 intel_dp_add_properties(intel_dp, connector);
6038 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6039 * 0xd. Failure to do so will result in spurious interrupts being
6040 * generated on the port when a cable is not attached.
6042 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6043 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6044 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6050 drm_connector_cleanup(connector);
6055 bool intel_dp_init(struct drm_i915_private *dev_priv,
6056 i915_reg_t output_reg,
6059 struct intel_digital_port *intel_dig_port;
6060 struct intel_encoder *intel_encoder;
6061 struct drm_encoder *encoder;
6062 struct intel_connector *intel_connector;
6064 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6065 if (!intel_dig_port)
6068 intel_connector = intel_connector_alloc();
6069 if (!intel_connector)
6070 goto err_connector_alloc;
6072 intel_encoder = &intel_dig_port->base;
6073 encoder = &intel_encoder->base;
6075 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6076 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6077 "DP %c", port_name(port)))
6078 goto err_encoder_init;
6080 intel_encoder->compute_config = intel_dp_compute_config;
6081 intel_encoder->disable = intel_disable_dp;
6082 intel_encoder->get_hw_state = intel_dp_get_hw_state;
6083 intel_encoder->get_config = intel_dp_get_config;
6084 intel_encoder->suspend = intel_dp_encoder_suspend;
6085 if (IS_CHERRYVIEW(dev_priv)) {
6086 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6087 intel_encoder->pre_enable = chv_pre_enable_dp;
6088 intel_encoder->enable = vlv_enable_dp;
6089 intel_encoder->post_disable = chv_post_disable_dp;
6090 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6091 } else if (IS_VALLEYVIEW(dev_priv)) {
6092 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6093 intel_encoder->pre_enable = vlv_pre_enable_dp;
6094 intel_encoder->enable = vlv_enable_dp;
6095 intel_encoder->post_disable = vlv_post_disable_dp;
6097 intel_encoder->pre_enable = g4x_pre_enable_dp;
6098 intel_encoder->enable = g4x_enable_dp;
6099 if (INTEL_GEN(dev_priv) >= 5)
6100 intel_encoder->post_disable = ilk_post_disable_dp;
6103 intel_dig_port->port = port;
6104 intel_dig_port->dp.output_reg = output_reg;
6105 intel_dig_port->max_lanes = 4;
6107 intel_encoder->type = INTEL_OUTPUT_DP;
6108 intel_encoder->power_domain = intel_port_to_power_domain(port);
6109 if (IS_CHERRYVIEW(dev_priv)) {
6111 intel_encoder->crtc_mask = 1 << 2;
6113 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6115 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6117 intel_encoder->cloneable = 0;
6118 intel_encoder->port = port;
6120 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6121 dev_priv->hotplug.irq_port[port] = intel_dig_port;
6123 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6124 goto err_init_connector;
6129 drm_encoder_cleanup(encoder);
6131 kfree(intel_connector);
6132 err_connector_alloc:
6133 kfree(intel_dig_port);
6137 void intel_dp_mst_suspend(struct drm_device *dev)
6139 struct drm_i915_private *dev_priv = to_i915(dev);
6143 for (i = 0; i < I915_MAX_PORTS; i++) {
6144 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6146 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6149 if (intel_dig_port->dp.is_mst)
6150 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6154 void intel_dp_mst_resume(struct drm_device *dev)
6156 struct drm_i915_private *dev_priv = to_i915(dev);
6159 for (i = 0; i < I915_MAX_PORTS; i++) {
6160 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6163 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6166 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6168 intel_dp_check_mst_status(&intel_dig_port->dp);