2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
37 #include "drm_dp_helper.h"
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43 #define DP_LINK_CONFIGURATION_SIZE 9
46 struct intel_encoder base;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
56 struct i2c_adapter adapter;
57 struct i2c_algo_dp_aux_data algo;
60 uint8_t link_status[DP_LINK_STATUS_SIZE];
62 struct drm_property *force_audio_property;
66 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
67 * @intel_dp: DP struct
69 * If a CPU or PCH DP output is attached to an eDP panel, this function
70 * will return true, and false otherwise.
72 static bool is_edp(struct intel_dp *intel_dp)
74 return intel_dp->base.type == INTEL_OUTPUT_EDP;
78 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
79 * @intel_dp: DP struct
81 * Returns true if the given DP struct corresponds to a PCH DP port attached
82 * to an eDP panel, false otherwise. Helpful for determining whether we
83 * may need FDI resources for a given DP output or not.
85 static bool is_pch_edp(struct intel_dp *intel_dp)
87 return intel_dp->is_pch_edp;
90 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
92 return container_of(encoder, struct intel_dp, base.base);
95 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
97 return container_of(intel_attached_encoder(connector),
98 struct intel_dp, base);
102 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
103 * @encoder: DRM encoder
105 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
106 * by intel_display.c.
108 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
110 struct intel_dp *intel_dp;
115 intel_dp = enc_to_intel_dp(encoder);
117 return is_pch_edp(intel_dp);
120 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
121 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
122 static void intel_dp_link_down(struct intel_dp *intel_dp);
125 intel_edp_link_config (struct intel_encoder *intel_encoder,
126 int *lane_num, int *link_bw)
128 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
130 *lane_num = intel_dp->lane_count;
131 if (intel_dp->link_bw == DP_LINK_BW_1_62)
133 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
138 intel_dp_max_lane_count(struct intel_dp *intel_dp)
140 int max_lane_count = 4;
142 if (intel_dp->dpcd[0] >= 0x11) {
143 max_lane_count = intel_dp->dpcd[2] & 0x1f;
144 switch (max_lane_count) {
145 case 1: case 2: case 4:
151 return max_lane_count;
155 intel_dp_max_link_bw(struct intel_dp *intel_dp)
157 int max_link_bw = intel_dp->dpcd[1];
159 switch (max_link_bw) {
160 case DP_LINK_BW_1_62:
164 max_link_bw = DP_LINK_BW_1_62;
171 intel_dp_link_clock(uint8_t link_bw)
173 if (link_bw == DP_LINK_BW_2_7)
179 /* I think this is a fiction */
181 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
183 struct drm_i915_private *dev_priv = dev->dev_private;
185 if (is_edp(intel_dp))
186 return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
188 return pixel_clock * 3;
192 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
194 return (max_link_clock * max_lanes * 8) / 10;
198 intel_dp_mode_valid(struct drm_connector *connector,
199 struct drm_display_mode *mode)
201 struct intel_dp *intel_dp = intel_attached_dp(connector);
202 struct drm_device *dev = connector->dev;
203 struct drm_i915_private *dev_priv = dev->dev_private;
204 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
205 int max_lanes = intel_dp_max_lane_count(intel_dp);
207 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
208 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
211 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
215 /* only refuse the mode on non eDP since we have seen some wierd eDP panels
216 which are outside spec tolerances but somehow work by magic */
217 if (!is_edp(intel_dp) &&
218 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
219 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
220 return MODE_CLOCK_HIGH;
222 if (mode->clock < 10000)
223 return MODE_CLOCK_LOW;
229 pack_aux(uint8_t *src, int src_bytes)
236 for (i = 0; i < src_bytes; i++)
237 v |= ((uint32_t) src[i]) << ((3-i) * 8);
242 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
247 for (i = 0; i < dst_bytes; i++)
248 dst[i] = src >> ((3-i) * 8);
251 /* hrawclock is 1/4 the FSB frequency */
253 intel_hrawclk(struct drm_device *dev)
255 struct drm_i915_private *dev_priv = dev->dev_private;
258 clkcfg = I915_READ(CLKCFG);
259 switch (clkcfg & CLKCFG_FSB_MASK) {
268 case CLKCFG_FSB_1067:
270 case CLKCFG_FSB_1333:
272 /* these two are just a guess; one of them might be right */
273 case CLKCFG_FSB_1600:
274 case CLKCFG_FSB_1600_ALT:
282 intel_dp_aux_ch(struct intel_dp *intel_dp,
283 uint8_t *send, int send_bytes,
284 uint8_t *recv, int recv_size)
286 uint32_t output_reg = intel_dp->output_reg;
287 struct drm_device *dev = intel_dp->base.base.dev;
288 struct drm_i915_private *dev_priv = dev->dev_private;
289 uint32_t ch_ctl = output_reg + 0x10;
290 uint32_t ch_data = ch_ctl + 4;
294 uint32_t aux_clock_divider;
297 /* The clock divider is based off the hrawclk,
298 * and would like to run at 2MHz. So, take the
299 * hrawclk value and divide by 2 and use that
301 * Note that PCH attached eDP panels should use a 125MHz input
304 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
306 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
308 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
309 } else if (HAS_PCH_SPLIT(dev))
310 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
312 aux_clock_divider = intel_hrawclk(dev) / 2;
319 if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
320 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
325 /* Must try at least 3 times according to DP spec */
326 for (try = 0; try < 5; try++) {
327 /* Load the send data into the aux channel data registers */
328 for (i = 0; i < send_bytes; i += 4)
329 I915_WRITE(ch_data + i,
330 pack_aux(send + i, send_bytes - i));
332 /* Send the command and wait for it to complete */
334 DP_AUX_CH_CTL_SEND_BUSY |
335 DP_AUX_CH_CTL_TIME_OUT_400us |
336 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
337 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
338 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
340 DP_AUX_CH_CTL_TIME_OUT_ERROR |
341 DP_AUX_CH_CTL_RECEIVE_ERROR);
343 status = I915_READ(ch_ctl);
344 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
349 /* Clear done status and any errors */
353 DP_AUX_CH_CTL_TIME_OUT_ERROR |
354 DP_AUX_CH_CTL_RECEIVE_ERROR);
355 if (status & DP_AUX_CH_CTL_DONE)
359 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
360 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
364 /* Check for timeout or receive error.
365 * Timeouts occur when the sink is not connected
367 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
368 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
372 /* Timeouts occur when the device isn't connected, so they're
373 * "normal" -- don't fill the kernel log with these */
374 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
375 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
379 /* Unload any bytes sent back from the other side */
380 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
381 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
382 if (recv_bytes > recv_size)
383 recv_bytes = recv_size;
385 for (i = 0; i < recv_bytes; i += 4)
386 unpack_aux(I915_READ(ch_data + i),
387 recv + i, recv_bytes - i);
392 /* Write data to the aux channel in native mode */
394 intel_dp_aux_native_write(struct intel_dp *intel_dp,
395 uint16_t address, uint8_t *send, int send_bytes)
404 msg[0] = AUX_NATIVE_WRITE << 4;
405 msg[1] = address >> 8;
406 msg[2] = address & 0xff;
407 msg[3] = send_bytes - 1;
408 memcpy(&msg[4], send, send_bytes);
409 msg_bytes = send_bytes + 4;
411 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
414 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
416 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
424 /* Write a single byte to the aux channel in native mode */
426 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
427 uint16_t address, uint8_t byte)
429 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
432 /* read bytes from a native aux channel */
434 intel_dp_aux_native_read(struct intel_dp *intel_dp,
435 uint16_t address, uint8_t *recv, int recv_bytes)
444 msg[0] = AUX_NATIVE_READ << 4;
445 msg[1] = address >> 8;
446 msg[2] = address & 0xff;
447 msg[3] = recv_bytes - 1;
450 reply_bytes = recv_bytes + 1;
453 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
460 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
461 memcpy(recv, reply + 1, ret - 1);
464 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
472 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
473 uint8_t write_byte, uint8_t *read_byte)
475 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
476 struct intel_dp *intel_dp = container_of(adapter,
479 uint16_t address = algo_data->address;
486 /* Set up the command byte */
487 if (mode & MODE_I2C_READ)
488 msg[0] = AUX_I2C_READ << 4;
490 msg[0] = AUX_I2C_WRITE << 4;
492 if (!(mode & MODE_I2C_STOP))
493 msg[0] |= AUX_I2C_MOT << 4;
495 msg[1] = address >> 8;
517 ret = intel_dp_aux_ch(intel_dp,
521 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
524 switch (reply[0] & AUX_I2C_REPLY_MASK) {
525 case AUX_I2C_REPLY_ACK:
526 if (mode == MODE_I2C_READ) {
527 *read_byte = reply[1];
529 return reply_bytes - 1;
530 case AUX_I2C_REPLY_NACK:
531 DRM_DEBUG_KMS("aux_ch nack\n");
533 case AUX_I2C_REPLY_DEFER:
534 DRM_DEBUG_KMS("aux_ch defer\n");
538 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
545 intel_dp_i2c_init(struct intel_dp *intel_dp,
546 struct intel_connector *intel_connector, const char *name)
548 DRM_DEBUG_KMS("i2c_init %s\n", name);
549 intel_dp->algo.running = false;
550 intel_dp->algo.address = 0;
551 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
553 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
554 intel_dp->adapter.owner = THIS_MODULE;
555 intel_dp->adapter.class = I2C_CLASS_DDC;
556 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
557 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
558 intel_dp->adapter.algo_data = &intel_dp->algo;
559 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
561 return i2c_dp_aux_add_bus(&intel_dp->adapter);
565 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
566 struct drm_display_mode *adjusted_mode)
568 struct drm_device *dev = encoder->dev;
569 struct drm_i915_private *dev_priv = dev->dev_private;
570 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
571 int lane_count, clock;
572 int max_lane_count = intel_dp_max_lane_count(intel_dp);
573 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
574 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
576 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
577 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
578 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
579 mode, adjusted_mode);
581 * the mode->clock is used to calculate the Data&Link M/N
582 * of the pipe. For the eDP the fixed clock should be used.
584 mode->clock = dev_priv->panel_fixed_mode->clock;
587 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
588 for (clock = 0; clock <= max_clock; clock++) {
589 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
591 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
593 intel_dp->link_bw = bws[clock];
594 intel_dp->lane_count = lane_count;
595 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
596 DRM_DEBUG_KMS("Display port link bw %02x lane "
597 "count %d clock %d\n",
598 intel_dp->link_bw, intel_dp->lane_count,
599 adjusted_mode->clock);
605 if (is_edp(intel_dp)) {
606 /* okay we failed just pick the highest */
607 intel_dp->lane_count = max_lane_count;
608 intel_dp->link_bw = bws[max_clock];
609 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
610 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
611 "count %d clock %d\n",
612 intel_dp->link_bw, intel_dp->lane_count,
613 adjusted_mode->clock);
621 struct intel_dp_m_n {
630 intel_reduce_ratio(uint32_t *num, uint32_t *den)
632 while (*num > 0xffffff || *den > 0xffffff) {
639 intel_dp_compute_m_n(int bpp,
643 struct intel_dp_m_n *m_n)
646 m_n->gmch_m = (pixel_clock * bpp) >> 3;
647 m_n->gmch_n = link_clock * nlanes;
648 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
649 m_n->link_m = pixel_clock;
650 m_n->link_n = link_clock;
651 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
655 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
656 struct drm_display_mode *adjusted_mode)
658 struct drm_device *dev = crtc->dev;
659 struct drm_mode_config *mode_config = &dev->mode_config;
660 struct drm_encoder *encoder;
661 struct drm_i915_private *dev_priv = dev->dev_private;
662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
663 int lane_count = 4, bpp = 24;
664 struct intel_dp_m_n m_n;
667 * Find the lane count in the intel_encoder private
669 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
670 struct intel_dp *intel_dp;
672 if (encoder->crtc != crtc)
675 intel_dp = enc_to_intel_dp(encoder);
676 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
677 lane_count = intel_dp->lane_count;
679 } else if (is_edp(intel_dp)) {
680 lane_count = dev_priv->edp.lanes;
681 bpp = dev_priv->edp.bpp;
687 * Compute the GMCH and Link ratios. The '3' here is
688 * the number of bytes_per_pixel post-LUT, which we always
689 * set up for 8-bits of R/G/B, or 3 bytes total.
691 intel_dp_compute_m_n(bpp, lane_count,
692 mode->clock, adjusted_mode->clock, &m_n);
694 if (HAS_PCH_SPLIT(dev)) {
695 if (intel_crtc->pipe == 0) {
696 I915_WRITE(TRANSA_DATA_M1,
697 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
699 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
700 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
701 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
703 I915_WRITE(TRANSB_DATA_M1,
704 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
706 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
707 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
708 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
711 if (intel_crtc->pipe == 0) {
712 I915_WRITE(PIPEA_GMCH_DATA_M,
713 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
715 I915_WRITE(PIPEA_GMCH_DATA_N,
717 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
718 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
720 I915_WRITE(PIPEB_GMCH_DATA_M,
721 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
723 I915_WRITE(PIPEB_GMCH_DATA_N,
725 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
726 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
732 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
733 struct drm_display_mode *adjusted_mode)
735 struct drm_device *dev = encoder->dev;
736 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
737 struct drm_crtc *crtc = intel_dp->base.base.crtc;
738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
740 intel_dp->DP = (DP_VOLTAGE_0_4 |
743 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
744 intel_dp->DP |= DP_SYNC_HS_HIGH;
745 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
746 intel_dp->DP |= DP_SYNC_VS_HIGH;
748 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
749 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
751 intel_dp->DP |= DP_LINK_TRAIN_OFF;
753 switch (intel_dp->lane_count) {
755 intel_dp->DP |= DP_PORT_WIDTH_1;
758 intel_dp->DP |= DP_PORT_WIDTH_2;
761 intel_dp->DP |= DP_PORT_WIDTH_4;
764 if (intel_dp->has_audio)
765 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
767 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
768 intel_dp->link_configuration[0] = intel_dp->link_bw;
769 intel_dp->link_configuration[1] = intel_dp->lane_count;
772 * Check for DPCD version > 1.1 and enhanced framing support
774 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
775 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
776 intel_dp->DP |= DP_ENHANCED_FRAMING;
779 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
780 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
781 intel_dp->DP |= DP_PIPEB_SELECT;
783 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
784 /* don't miss out required setting for eDP */
785 intel_dp->DP |= DP_PLL_ENABLE;
786 if (adjusted_mode->clock < 200000)
787 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
789 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
793 /* Returns true if the panel was already on when called */
794 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
796 struct drm_device *dev = intel_dp->base.base.dev;
797 struct drm_i915_private *dev_priv = dev->dev_private;
798 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
800 if (I915_READ(PCH_PP_STATUS) & PP_ON)
803 pp = I915_READ(PCH_PP_CONTROL);
805 /* ILK workaround: disable reset around power sequence */
806 pp &= ~PANEL_POWER_RESET;
807 I915_WRITE(PCH_PP_CONTROL, pp);
808 POSTING_READ(PCH_PP_CONTROL);
810 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
811 I915_WRITE(PCH_PP_CONTROL, pp);
812 POSTING_READ(PCH_PP_CONTROL);
814 /* Ouch. We need to wait here for some panels, like Dell e6510
815 * https://bugs.freedesktop.org/show_bug.cgi?id=29278i
819 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
821 DRM_ERROR("panel on wait timed out: 0x%08x\n",
822 I915_READ(PCH_PP_STATUS));
824 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
825 I915_WRITE(PCH_PP_CONTROL, pp);
826 POSTING_READ(PCH_PP_CONTROL);
831 static void ironlake_edp_panel_off (struct drm_device *dev)
833 struct drm_i915_private *dev_priv = dev->dev_private;
834 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
835 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
837 pp = I915_READ(PCH_PP_CONTROL);
839 /* ILK workaround: disable reset around power sequence */
840 pp &= ~PANEL_POWER_RESET;
841 I915_WRITE(PCH_PP_CONTROL, pp);
842 POSTING_READ(PCH_PP_CONTROL);
844 pp &= ~POWER_TARGET_ON;
845 I915_WRITE(PCH_PP_CONTROL, pp);
846 POSTING_READ(PCH_PP_CONTROL);
848 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
849 DRM_ERROR("panel off wait timed out: 0x%08x\n",
850 I915_READ(PCH_PP_STATUS));
852 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
853 I915_WRITE(PCH_PP_CONTROL, pp);
854 POSTING_READ(PCH_PP_CONTROL);
856 /* Ouch. We need to wait here for some panels, like Dell e6510
857 * https://bugs.freedesktop.org/show_bug.cgi?id=29278i
862 static void ironlake_edp_backlight_on (struct drm_device *dev)
864 struct drm_i915_private *dev_priv = dev->dev_private;
869 * If we enable the backlight right away following a panel power
870 * on, we may see slight flicker as the panel syncs with the eDP
871 * link. So delay a bit to make sure the image is solid before
872 * allowing it to appear.
875 pp = I915_READ(PCH_PP_CONTROL);
876 pp |= EDP_BLC_ENABLE;
877 I915_WRITE(PCH_PP_CONTROL, pp);
880 static void ironlake_edp_backlight_off (struct drm_device *dev)
882 struct drm_i915_private *dev_priv = dev->dev_private;
886 pp = I915_READ(PCH_PP_CONTROL);
887 pp &= ~EDP_BLC_ENABLE;
888 I915_WRITE(PCH_PP_CONTROL, pp);
891 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
893 struct drm_device *dev = encoder->dev;
894 struct drm_i915_private *dev_priv = dev->dev_private;
898 dpa_ctl = I915_READ(DP_A);
899 dpa_ctl |= DP_PLL_ENABLE;
900 I915_WRITE(DP_A, dpa_ctl);
905 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
907 struct drm_device *dev = encoder->dev;
908 struct drm_i915_private *dev_priv = dev->dev_private;
911 dpa_ctl = I915_READ(DP_A);
912 dpa_ctl &= ~DP_PLL_ENABLE;
913 I915_WRITE(DP_A, dpa_ctl);
918 static void intel_dp_prepare(struct drm_encoder *encoder)
920 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
921 struct drm_device *dev = encoder->dev;
923 if (is_edp(intel_dp)) {
924 ironlake_edp_backlight_off(dev);
925 ironlake_edp_panel_on(intel_dp);
926 if (!is_pch_edp(intel_dp))
927 ironlake_edp_pll_on(encoder);
929 ironlake_edp_pll_off(encoder);
931 intel_dp_link_down(intel_dp);
934 static void intel_dp_commit(struct drm_encoder *encoder)
936 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
937 struct drm_device *dev = encoder->dev;
939 intel_dp_start_link_train(intel_dp);
941 if (is_edp(intel_dp))
942 ironlake_edp_panel_on(intel_dp);
944 intel_dp_complete_link_train(intel_dp);
946 if (is_edp(intel_dp))
947 ironlake_edp_backlight_on(dev);
951 intel_dp_dpms(struct drm_encoder *encoder, int mode)
953 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
954 struct drm_device *dev = encoder->dev;
955 struct drm_i915_private *dev_priv = dev->dev_private;
956 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
958 if (mode != DRM_MODE_DPMS_ON) {
959 if (is_edp(intel_dp))
960 ironlake_edp_backlight_off(dev);
961 intel_dp_link_down(intel_dp);
962 if (is_edp(intel_dp))
963 ironlake_edp_panel_off(dev);
964 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
965 ironlake_edp_pll_off(encoder);
967 if (is_edp(intel_dp))
968 ironlake_edp_panel_on(intel_dp);
969 if (!(dp_reg & DP_PORT_EN)) {
970 intel_dp_start_link_train(intel_dp);
971 intel_dp_complete_link_train(intel_dp);
973 if (is_edp(intel_dp))
974 ironlake_edp_backlight_on(dev);
976 intel_dp->dpms_mode = mode;
980 * Fetch AUX CH registers 0x202 - 0x207 which contain
981 * link status information
984 intel_dp_get_link_status(struct intel_dp *intel_dp)
988 ret = intel_dp_aux_native_read(intel_dp,
990 intel_dp->link_status, DP_LINK_STATUS_SIZE);
991 if (ret != DP_LINK_STATUS_SIZE)
997 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1000 return link_status[r - DP_LANE0_1_STATUS];
1004 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1007 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1008 int s = ((lane & 1) ?
1009 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1010 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1011 uint8_t l = intel_dp_link_status(link_status, i);
1013 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1017 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1020 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1021 int s = ((lane & 1) ?
1022 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1023 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1024 uint8_t l = intel_dp_link_status(link_status, i);
1026 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1031 static char *voltage_names[] = {
1032 "0.4V", "0.6V", "0.8V", "1.2V"
1034 static char *pre_emph_names[] = {
1035 "0dB", "3.5dB", "6dB", "9.5dB"
1037 static char *link_train_names[] = {
1038 "pattern 1", "pattern 2", "idle", "off"
1043 * These are source-specific values; current Intel hardware supports
1044 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1046 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1049 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1051 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1052 case DP_TRAIN_VOLTAGE_SWING_400:
1053 return DP_TRAIN_PRE_EMPHASIS_6;
1054 case DP_TRAIN_VOLTAGE_SWING_600:
1055 return DP_TRAIN_PRE_EMPHASIS_6;
1056 case DP_TRAIN_VOLTAGE_SWING_800:
1057 return DP_TRAIN_PRE_EMPHASIS_3_5;
1058 case DP_TRAIN_VOLTAGE_SWING_1200:
1060 return DP_TRAIN_PRE_EMPHASIS_0;
1065 intel_get_adjust_train(struct intel_dp *intel_dp)
1071 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1072 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1073 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1081 if (v >= I830_DP_VOLTAGE_MAX)
1082 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1084 if (p >= intel_dp_pre_emphasis_max(v))
1085 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1087 for (lane = 0; lane < 4; lane++)
1088 intel_dp->train_set[lane] = v | p;
1092 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1094 uint32_t signal_levels = 0;
1096 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1097 case DP_TRAIN_VOLTAGE_SWING_400:
1099 signal_levels |= DP_VOLTAGE_0_4;
1101 case DP_TRAIN_VOLTAGE_SWING_600:
1102 signal_levels |= DP_VOLTAGE_0_6;
1104 case DP_TRAIN_VOLTAGE_SWING_800:
1105 signal_levels |= DP_VOLTAGE_0_8;
1107 case DP_TRAIN_VOLTAGE_SWING_1200:
1108 signal_levels |= DP_VOLTAGE_1_2;
1111 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1112 case DP_TRAIN_PRE_EMPHASIS_0:
1114 signal_levels |= DP_PRE_EMPHASIS_0;
1116 case DP_TRAIN_PRE_EMPHASIS_3_5:
1117 signal_levels |= DP_PRE_EMPHASIS_3_5;
1119 case DP_TRAIN_PRE_EMPHASIS_6:
1120 signal_levels |= DP_PRE_EMPHASIS_6;
1122 case DP_TRAIN_PRE_EMPHASIS_9_5:
1123 signal_levels |= DP_PRE_EMPHASIS_9_5;
1126 return signal_levels;
1129 /* Gen6's DP voltage swing and pre-emphasis control */
1131 intel_gen6_edp_signal_levels(uint8_t train_set)
1133 switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
1134 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1135 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1136 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1137 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
1138 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1139 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
1140 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1141 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
1143 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1144 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1149 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1152 int i = DP_LANE0_1_STATUS + (lane >> 1);
1153 int s = (lane & 1) * 4;
1154 uint8_t l = intel_dp_link_status(link_status, i);
1156 return (l >> s) & 0xf;
1159 /* Check for clock recovery is done on all channels */
1161 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1164 uint8_t lane_status;
1166 for (lane = 0; lane < lane_count; lane++) {
1167 lane_status = intel_get_lane_status(link_status, lane);
1168 if ((lane_status & DP_LANE_CR_DONE) == 0)
1174 /* Check to see if channel eq is done on all channels */
1175 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1176 DP_LANE_CHANNEL_EQ_DONE|\
1177 DP_LANE_SYMBOL_LOCKED)
1179 intel_channel_eq_ok(struct intel_dp *intel_dp)
1182 uint8_t lane_status;
1185 lane_align = intel_dp_link_status(intel_dp->link_status,
1186 DP_LANE_ALIGN_STATUS_UPDATED);
1187 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1189 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1190 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1191 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1198 intel_dp_set_link_train(struct intel_dp *intel_dp,
1199 uint32_t dp_reg_value,
1200 uint8_t dp_train_pat)
1202 struct drm_device *dev = intel_dp->base.base.dev;
1203 struct drm_i915_private *dev_priv = dev->dev_private;
1206 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1207 POSTING_READ(intel_dp->output_reg);
1209 intel_dp_aux_native_write_1(intel_dp,
1210 DP_TRAINING_PATTERN_SET,
1213 ret = intel_dp_aux_native_write(intel_dp,
1214 DP_TRAINING_LANE0_SET,
1215 intel_dp->train_set, 4);
1222 /* Enable corresponding port and start training pattern 1 */
1224 intel_dp_start_link_train(struct intel_dp *intel_dp)
1226 struct drm_device *dev = intel_dp->base.base.dev;
1227 struct drm_i915_private *dev_priv = dev->dev_private;
1228 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1231 bool clock_recovery = false;
1234 uint32_t DP = intel_dp->DP;
1236 /* Enable output, wait for it to become active */
1237 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1238 POSTING_READ(intel_dp->output_reg);
1239 intel_wait_for_vblank(dev, intel_crtc->pipe);
1241 /* Write the link configuration data */
1242 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1243 intel_dp->link_configuration,
1244 DP_LINK_CONFIGURATION_SIZE);
1247 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1248 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1250 DP &= ~DP_LINK_TRAIN_MASK;
1251 memset(intel_dp->train_set, 0, 4);
1254 clock_recovery = false;
1256 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1257 uint32_t signal_levels;
1258 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1259 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1260 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1262 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1263 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1266 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1267 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1269 reg = DP | DP_LINK_TRAIN_PAT_1;
1271 if (!intel_dp_set_link_train(intel_dp, reg,
1272 DP_TRAINING_PATTERN_1))
1274 /* Set training pattern 1 */
1277 if (!intel_dp_get_link_status(intel_dp))
1280 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1281 clock_recovery = true;
1285 /* Check to see if we've tried the max voltage */
1286 for (i = 0; i < intel_dp->lane_count; i++)
1287 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1289 if (i == intel_dp->lane_count)
1292 /* Check to see if we've tried the same voltage 5 times */
1293 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1299 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1301 /* Compute new intel_dp->train_set as requested by target */
1302 intel_get_adjust_train(intel_dp);
1309 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1311 struct drm_device *dev = intel_dp->base.base.dev;
1312 struct drm_i915_private *dev_priv = dev->dev_private;
1313 bool channel_eq = false;
1316 uint32_t DP = intel_dp->DP;
1318 /* channel equalization */
1322 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1323 uint32_t signal_levels;
1325 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1326 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1327 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1329 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1330 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1333 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1334 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1336 reg = DP | DP_LINK_TRAIN_PAT_2;
1338 /* channel eq pattern */
1339 if (!intel_dp_set_link_train(intel_dp, reg,
1340 DP_TRAINING_PATTERN_2))
1344 if (!intel_dp_get_link_status(intel_dp))
1347 if (intel_channel_eq_ok(intel_dp)) {
1356 /* Compute new intel_dp->train_set as requested by target */
1357 intel_get_adjust_train(intel_dp);
1361 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1362 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1364 reg = DP | DP_LINK_TRAIN_OFF;
1366 I915_WRITE(intel_dp->output_reg, reg);
1367 POSTING_READ(intel_dp->output_reg);
1368 intel_dp_aux_native_write_1(intel_dp,
1369 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1373 intel_dp_link_down(struct intel_dp *intel_dp)
1375 struct drm_device *dev = intel_dp->base.base.dev;
1376 struct drm_i915_private *dev_priv = dev->dev_private;
1377 uint32_t DP = intel_dp->DP;
1379 DRM_DEBUG_KMS("\n");
1381 if (is_edp(intel_dp)) {
1382 DP &= ~DP_PLL_ENABLE;
1383 I915_WRITE(intel_dp->output_reg, DP);
1384 POSTING_READ(intel_dp->output_reg);
1388 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1389 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1390 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1392 DP &= ~DP_LINK_TRAIN_MASK;
1393 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1395 POSTING_READ(intel_dp->output_reg);
1399 if (is_edp(intel_dp))
1400 DP |= DP_LINK_TRAIN_OFF;
1401 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1402 POSTING_READ(intel_dp->output_reg);
1406 * According to DP spec
1409 * 2. Configure link according to Receiver Capabilities
1410 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1411 * 4. Check link status on receipt of hot-plug interrupt
1415 intel_dp_check_link_status(struct intel_dp *intel_dp)
1417 if (!intel_dp->base.base.crtc)
1420 if (!intel_dp_get_link_status(intel_dp)) {
1421 intel_dp_link_down(intel_dp);
1425 if (!intel_channel_eq_ok(intel_dp)) {
1426 intel_dp_start_link_train(intel_dp);
1427 intel_dp_complete_link_train(intel_dp);
1431 static enum drm_connector_status
1432 ironlake_dp_detect(struct intel_dp *intel_dp)
1434 enum drm_connector_status status;
1436 /* Can't disconnect eDP */
1437 if (is_edp(intel_dp))
1438 return connector_status_connected;
1440 status = connector_status_disconnected;
1441 if (intel_dp_aux_native_read(intel_dp,
1442 0x000, intel_dp->dpcd,
1443 sizeof (intel_dp->dpcd))
1444 == sizeof(intel_dp->dpcd)) {
1445 if (intel_dp->dpcd[0] != 0)
1446 status = connector_status_connected;
1448 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1449 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1453 static enum drm_connector_status
1454 g4x_dp_detect(struct intel_dp *intel_dp)
1456 struct drm_device *dev = intel_dp->base.base.dev;
1457 struct drm_i915_private *dev_priv = dev->dev_private;
1458 enum drm_connector_status status;
1461 switch (intel_dp->output_reg) {
1463 bit = DPB_HOTPLUG_INT_STATUS;
1466 bit = DPC_HOTPLUG_INT_STATUS;
1469 bit = DPD_HOTPLUG_INT_STATUS;
1472 return connector_status_unknown;
1475 temp = I915_READ(PORT_HOTPLUG_STAT);
1477 if ((temp & bit) == 0)
1478 return connector_status_disconnected;
1480 status = connector_status_disconnected;
1481 if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd,
1482 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1484 if (intel_dp->dpcd[0] != 0)
1485 status = connector_status_connected;
1492 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1494 * \return true if DP port is connected.
1495 * \return false if DP port is disconnected.
1497 static enum drm_connector_status
1498 intel_dp_detect(struct drm_connector *connector, bool force)
1500 struct intel_dp *intel_dp = intel_attached_dp(connector);
1501 struct drm_device *dev = intel_dp->base.base.dev;
1502 enum drm_connector_status status;
1503 struct edid *edid = NULL;
1505 intel_dp->has_audio = false;
1507 if (HAS_PCH_SPLIT(dev))
1508 status = ironlake_dp_detect(intel_dp);
1510 status = g4x_dp_detect(intel_dp);
1511 if (status != connector_status_connected)
1514 if (intel_dp->force_audio) {
1515 intel_dp->has_audio = intel_dp->force_audio > 0;
1517 edid = drm_get_edid(connector, &intel_dp->adapter);
1519 intel_dp->has_audio = drm_detect_monitor_audio(edid);
1520 connector->display_info.raw_edid = NULL;
1525 return connector_status_connected;
1528 static int intel_dp_get_modes(struct drm_connector *connector)
1530 struct intel_dp *intel_dp = intel_attached_dp(connector);
1531 struct drm_device *dev = intel_dp->base.base.dev;
1532 struct drm_i915_private *dev_priv = dev->dev_private;
1535 /* We should parse the EDID data and find out if it has an audio sink
1538 ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1540 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1541 struct drm_display_mode *newmode;
1542 list_for_each_entry(newmode, &connector->probed_modes,
1544 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1545 dev_priv->panel_fixed_mode =
1546 drm_mode_duplicate(dev, newmode);
1555 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1556 if (is_edp(intel_dp)) {
1557 if (dev_priv->panel_fixed_mode != NULL) {
1558 struct drm_display_mode *mode;
1559 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1560 drm_mode_probed_add(connector, mode);
1568 intel_dp_set_property(struct drm_connector *connector,
1569 struct drm_property *property,
1572 struct intel_dp *intel_dp = intel_attached_dp(connector);
1575 ret = drm_connector_property_set_value(connector, property, val);
1579 if (property == intel_dp->force_audio_property) {
1580 if (val == intel_dp->force_audio)
1583 intel_dp->force_audio = val;
1585 if (val > 0 && intel_dp->has_audio)
1587 if (val < 0 && !intel_dp->has_audio)
1590 intel_dp->has_audio = val > 0;
1597 if (intel_dp->base.base.crtc) {
1598 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1599 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1608 intel_dp_destroy (struct drm_connector *connector)
1610 drm_sysfs_connector_remove(connector);
1611 drm_connector_cleanup(connector);
1615 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1617 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1619 i2c_del_adapter(&intel_dp->adapter);
1620 drm_encoder_cleanup(encoder);
1624 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1625 .dpms = intel_dp_dpms,
1626 .mode_fixup = intel_dp_mode_fixup,
1627 .prepare = intel_dp_prepare,
1628 .mode_set = intel_dp_mode_set,
1629 .commit = intel_dp_commit,
1632 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1633 .dpms = drm_helper_connector_dpms,
1634 .detect = intel_dp_detect,
1635 .fill_modes = drm_helper_probe_single_connector_modes,
1636 .set_property = intel_dp_set_property,
1637 .destroy = intel_dp_destroy,
1640 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1641 .get_modes = intel_dp_get_modes,
1642 .mode_valid = intel_dp_mode_valid,
1643 .best_encoder = intel_best_encoder,
1646 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1647 .destroy = intel_dp_encoder_destroy,
1651 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1653 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1655 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1656 intel_dp_check_link_status(intel_dp);
1659 /* Return which DP Port should be selected for Transcoder DP control */
1661 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1663 struct drm_device *dev = crtc->dev;
1664 struct drm_mode_config *mode_config = &dev->mode_config;
1665 struct drm_encoder *encoder;
1667 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1668 struct intel_dp *intel_dp;
1670 if (encoder->crtc != crtc)
1673 intel_dp = enc_to_intel_dp(encoder);
1674 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1675 return intel_dp->output_reg;
1681 /* check the VBT to see whether the eDP is on DP-D port */
1682 bool intel_dpd_is_edp(struct drm_device *dev)
1684 struct drm_i915_private *dev_priv = dev->dev_private;
1685 struct child_device_config *p_child;
1688 if (!dev_priv->child_dev_num)
1691 for (i = 0; i < dev_priv->child_dev_num; i++) {
1692 p_child = dev_priv->child_dev + i;
1694 if (p_child->dvo_port == PORT_IDPD &&
1695 p_child->device_type == DEVICE_TYPE_eDP)
1702 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1704 struct drm_device *dev = connector->dev;
1706 intel_dp->force_audio_property =
1707 drm_property_create(dev, DRM_MODE_PROP_RANGE, "force_audio", 2);
1708 if (intel_dp->force_audio_property) {
1709 intel_dp->force_audio_property->values[0] = -1;
1710 intel_dp->force_audio_property->values[1] = 1;
1711 drm_connector_attach_property(connector, intel_dp->force_audio_property, 0);
1716 intel_dp_init(struct drm_device *dev, int output_reg)
1718 struct drm_i915_private *dev_priv = dev->dev_private;
1719 struct drm_connector *connector;
1720 struct intel_dp *intel_dp;
1721 struct intel_encoder *intel_encoder;
1722 struct intel_connector *intel_connector;
1723 const char *name = NULL;
1726 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1730 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1731 if (!intel_connector) {
1735 intel_encoder = &intel_dp->base;
1737 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1738 if (intel_dpd_is_edp(dev))
1739 intel_dp->is_pch_edp = true;
1741 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1742 type = DRM_MODE_CONNECTOR_eDP;
1743 intel_encoder->type = INTEL_OUTPUT_EDP;
1745 type = DRM_MODE_CONNECTOR_DisplayPort;
1746 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1749 connector = &intel_connector->base;
1750 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1751 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1753 connector->polled = DRM_CONNECTOR_POLL_HPD;
1755 if (output_reg == DP_B || output_reg == PCH_DP_B)
1756 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1757 else if (output_reg == DP_C || output_reg == PCH_DP_C)
1758 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1759 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1760 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1762 if (is_edp(intel_dp))
1763 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1765 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1766 connector->interlace_allowed = true;
1767 connector->doublescan_allowed = 0;
1769 intel_dp->output_reg = output_reg;
1770 intel_dp->has_audio = false;
1771 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1773 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1774 DRM_MODE_ENCODER_TMDS);
1775 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1777 intel_connector_attach_encoder(intel_connector, intel_encoder);
1778 drm_sysfs_connector_add(connector);
1780 /* Set up the DDC bus. */
1781 switch (output_reg) {
1787 dev_priv->hotplug_supported_mask |=
1788 HDMIB_HOTPLUG_INT_STATUS;
1793 dev_priv->hotplug_supported_mask |=
1794 HDMIC_HOTPLUG_INT_STATUS;
1799 dev_priv->hotplug_supported_mask |=
1800 HDMID_HOTPLUG_INT_STATUS;
1805 intel_dp_i2c_init(intel_dp, intel_connector, name);
1807 /* Cache some DPCD data in the eDP case */
1808 if (is_edp(intel_dp)) {
1812 was_on = ironlake_edp_panel_on(intel_dp);
1813 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
1815 sizeof(intel_dp->dpcd));
1816 if (ret == sizeof(intel_dp->dpcd)) {
1817 if (intel_dp->dpcd[0] >= 0x11)
1818 dev_priv->no_aux_handshake = intel_dp->dpcd[3] &
1819 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
1821 DRM_ERROR("failed to retrieve link info\n");
1824 ironlake_edp_panel_off(dev);
1827 intel_encoder->hot_plug = intel_dp_hot_plug;
1829 if (is_edp(intel_dp)) {
1830 /* initialize panel mode from VBT if available for eDP */
1831 if (dev_priv->lfp_lvds_vbt_mode) {
1832 dev_priv->panel_fixed_mode =
1833 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1834 if (dev_priv->panel_fixed_mode) {
1835 dev_priv->panel_fixed_mode->type |=
1836 DRM_MODE_TYPE_PREFERRED;
1841 intel_dp_add_properties(intel_dp, connector);
1843 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1844 * 0xd. Failure to do so will result in spurious interrupts being
1845 * generated on the port when a cable is not attached.
1847 if (IS_G4X(dev) && !IS_GM45(dev)) {
1848 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1849 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);