2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
48 static bool is_edp(struct intel_dp *intel_dp)
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
55 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
59 return intel_dig_port->base.base.dev;
62 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
64 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
67 static void intel_dp_link_down(struct intel_dp *intel_dp);
70 intel_dp_max_link_bw(struct intel_dp *intel_dp)
72 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
74 switch (max_link_bw) {
78 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
79 max_link_bw = DP_LINK_BW_2_7;
82 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
84 max_link_bw = DP_LINK_BW_1_62;
91 * The units on the numbers in the next two are... bizarre. Examples will
92 * make it clearer; this one parallels an example in the eDP spec.
94 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
96 * 270000 * 1 * 8 / 10 == 216000
98 * The actual data capacity of that configuration is 2.16Gbit/s, so the
99 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
100 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
101 * 119000. At 18bpp that's 2142000 kilobits per second.
103 * Thus the strange-looking division by 10 in intel_dp_link_required, to
104 * get the result in decakilobits instead of kilobits.
108 intel_dp_link_required(int pixel_clock, int bpp)
110 return (pixel_clock * bpp + 9) / 10;
114 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
116 return (max_link_clock * max_lanes * 8) / 10;
120 intel_dp_mode_valid(struct drm_connector *connector,
121 struct drm_display_mode *mode)
123 struct intel_dp *intel_dp = intel_attached_dp(connector);
124 struct intel_connector *intel_connector = to_intel_connector(connector);
125 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
126 int target_clock = mode->clock;
127 int max_rate, mode_rate, max_lanes, max_link_clock;
129 if (is_edp(intel_dp) && fixed_mode) {
130 if (mode->hdisplay > fixed_mode->hdisplay)
133 if (mode->vdisplay > fixed_mode->vdisplay)
136 target_clock = fixed_mode->clock;
139 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
140 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
142 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
143 mode_rate = intel_dp_link_required(target_clock, 18);
145 if (mode_rate > max_rate)
146 return MODE_CLOCK_HIGH;
148 if (mode->clock < 10000)
149 return MODE_CLOCK_LOW;
151 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
152 return MODE_H_ILLEGAL;
158 pack_aux(uint8_t *src, int src_bytes)
165 for (i = 0; i < src_bytes; i++)
166 v |= ((uint32_t) src[i]) << ((3-i) * 8);
171 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
176 for (i = 0; i < dst_bytes; i++)
177 dst[i] = src >> ((3-i) * 8);
180 /* hrawclock is 1/4 the FSB frequency */
182 intel_hrawclk(struct drm_device *dev)
184 struct drm_i915_private *dev_priv = dev->dev_private;
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
201 case CLKCFG_FSB_1067:
203 case CLKCFG_FSB_1333:
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
214 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
216 struct drm_device *dev = intel_dp_to_dev(intel_dp);
217 struct drm_i915_private *dev_priv = dev->dev_private;
220 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
221 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
224 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
226 struct drm_device *dev = intel_dp_to_dev(intel_dp);
227 struct drm_i915_private *dev_priv = dev->dev_private;
230 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
231 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
235 intel_dp_check_edp(struct intel_dp *intel_dp)
237 struct drm_device *dev = intel_dp_to_dev(intel_dp);
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 u32 pp_stat_reg, pp_ctrl_reg;
241 if (!is_edp(intel_dp))
244 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
245 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
247 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
248 WARN(1, "eDP powered off while attempting aux channel communication.\n");
249 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
250 I915_READ(pp_stat_reg),
251 I915_READ(pp_ctrl_reg));
256 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
259 struct drm_device *dev = intel_dig_port->base.base.dev;
260 struct drm_i915_private *dev_priv = dev->dev_private;
261 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
265 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
267 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
268 msecs_to_jiffies_timeout(10));
270 done = wait_for_atomic(C, 10) == 0;
272 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
279 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
283 struct drm_device *dev = intel_dig_port->base.base.dev;
284 struct drm_i915_private *dev_priv = dev->dev_private;
286 /* The clock divider is based off the hrawclk,
287 * and would like to run at 2MHz. So, take the
288 * hrawclk value and divide by 2 and use that
290 * Note that PCH attached eDP panels should use a 125MHz input
293 if (IS_VALLEYVIEW(dev)) {
294 return index ? 0 : 100;
295 } else if (intel_dig_port->port == PORT_A) {
299 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
300 else if (IS_GEN6(dev) || IS_GEN7(dev))
301 return 200; /* SNB & IVB eDP input clock at 400Mhz */
303 return 225; /* eDP input clock at 450Mhz */
304 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
305 /* Workaround for non-ULT HSW */
311 } else if (HAS_PCH_SPLIT(dev)) {
312 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
314 return index ? 0 :intel_hrawclk(dev) / 2;
319 intel_dp_aux_ch(struct intel_dp *intel_dp,
320 uint8_t *send, int send_bytes,
321 uint8_t *recv, int recv_size)
323 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
324 struct drm_device *dev = intel_dig_port->base.base.dev;
325 struct drm_i915_private *dev_priv = dev->dev_private;
326 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
327 uint32_t ch_data = ch_ctl + 4;
328 uint32_t aux_clock_divider;
329 int i, ret, recv_bytes;
331 int try, precharge, clock = 0;
332 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
334 /* dp aux is extremely sensitive to irq latency, hence request the
335 * lowest possible wakeup latency and so prevent the cpu from going into
338 pm_qos_update_request(&dev_priv->pm_qos, 0);
340 intel_dp_check_edp(intel_dp);
347 intel_aux_display_runtime_get(dev_priv);
349 /* Try to wait for any previous AUX channel activity */
350 for (try = 0; try < 3; try++) {
351 status = I915_READ_NOTRACE(ch_ctl);
352 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
358 WARN(1, "dp_aux_ch not started status 0x%08x\n",
364 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
365 /* Must try at least 3 times according to DP spec */
366 for (try = 0; try < 5; try++) {
367 /* Load the send data into the aux channel data registers */
368 for (i = 0; i < send_bytes; i += 4)
369 I915_WRITE(ch_data + i,
370 pack_aux(send + i, send_bytes - i));
372 /* Send the command and wait for it to complete */
374 DP_AUX_CH_CTL_SEND_BUSY |
375 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
376 DP_AUX_CH_CTL_TIME_OUT_400us |
377 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
378 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
379 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
381 DP_AUX_CH_CTL_TIME_OUT_ERROR |
382 DP_AUX_CH_CTL_RECEIVE_ERROR);
384 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
386 /* Clear done status and any errors */
390 DP_AUX_CH_CTL_TIME_OUT_ERROR |
391 DP_AUX_CH_CTL_RECEIVE_ERROR);
393 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
394 DP_AUX_CH_CTL_RECEIVE_ERROR))
396 if (status & DP_AUX_CH_CTL_DONE)
399 if (status & DP_AUX_CH_CTL_DONE)
403 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
404 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
409 /* Check for timeout or receive error.
410 * Timeouts occur when the sink is not connected
412 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
413 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
418 /* Timeouts occur when the device isn't connected, so they're
419 * "normal" -- don't fill the kernel log with these */
420 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
421 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
426 /* Unload any bytes sent back from the other side */
427 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
428 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
429 if (recv_bytes > recv_size)
430 recv_bytes = recv_size;
432 for (i = 0; i < recv_bytes; i += 4)
433 unpack_aux(I915_READ(ch_data + i),
434 recv + i, recv_bytes - i);
438 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
439 intel_aux_display_runtime_put(dev_priv);
444 /* Write data to the aux channel in native mode */
446 intel_dp_aux_native_write(struct intel_dp *intel_dp,
447 uint16_t address, uint8_t *send, int send_bytes)
454 intel_dp_check_edp(intel_dp);
457 msg[0] = AUX_NATIVE_WRITE << 4;
458 msg[1] = address >> 8;
459 msg[2] = address & 0xff;
460 msg[3] = send_bytes - 1;
461 memcpy(&msg[4], send, send_bytes);
462 msg_bytes = send_bytes + 4;
464 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
467 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
469 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
477 /* Write a single byte to the aux channel in native mode */
479 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
480 uint16_t address, uint8_t byte)
482 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
485 /* read bytes from a native aux channel */
487 intel_dp_aux_native_read(struct intel_dp *intel_dp,
488 uint16_t address, uint8_t *recv, int recv_bytes)
497 intel_dp_check_edp(intel_dp);
498 msg[0] = AUX_NATIVE_READ << 4;
499 msg[1] = address >> 8;
500 msg[2] = address & 0xff;
501 msg[3] = recv_bytes - 1;
504 reply_bytes = recv_bytes + 1;
507 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
514 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
515 memcpy(recv, reply + 1, ret - 1);
518 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
526 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
527 uint8_t write_byte, uint8_t *read_byte)
529 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
530 struct intel_dp *intel_dp = container_of(adapter,
533 uint16_t address = algo_data->address;
541 intel_dp_check_edp(intel_dp);
542 /* Set up the command byte */
543 if (mode & MODE_I2C_READ)
544 msg[0] = AUX_I2C_READ << 4;
546 msg[0] = AUX_I2C_WRITE << 4;
548 if (!(mode & MODE_I2C_STOP))
549 msg[0] |= AUX_I2C_MOT << 4;
551 msg[1] = address >> 8;
572 for (retry = 0; retry < 5; retry++) {
573 ret = intel_dp_aux_ch(intel_dp,
577 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
581 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
582 case AUX_NATIVE_REPLY_ACK:
583 /* I2C-over-AUX Reply field is only valid
584 * when paired with AUX ACK.
587 case AUX_NATIVE_REPLY_NACK:
588 DRM_DEBUG_KMS("aux_ch native nack\n");
590 case AUX_NATIVE_REPLY_DEFER:
592 * For now, just give more slack to branch devices. We
593 * could check the DPCD for I2C bit rate capabilities,
594 * and if available, adjust the interval. We could also
595 * be more careful with DP-to-Legacy adapters where a
596 * long legacy cable may force very low I2C bit rates.
598 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
599 DP_DWN_STRM_PORT_PRESENT)
600 usleep_range(500, 600);
602 usleep_range(300, 400);
605 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
610 switch (reply[0] & AUX_I2C_REPLY_MASK) {
611 case AUX_I2C_REPLY_ACK:
612 if (mode == MODE_I2C_READ) {
613 *read_byte = reply[1];
615 return reply_bytes - 1;
616 case AUX_I2C_REPLY_NACK:
617 DRM_DEBUG_KMS("aux_i2c nack\n");
619 case AUX_I2C_REPLY_DEFER:
620 DRM_DEBUG_KMS("aux_i2c defer\n");
624 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
629 DRM_ERROR("too many retries, giving up\n");
634 intel_dp_i2c_init(struct intel_dp *intel_dp,
635 struct intel_connector *intel_connector, const char *name)
639 DRM_DEBUG_KMS("i2c_init %s\n", name);
640 intel_dp->algo.running = false;
641 intel_dp->algo.address = 0;
642 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
644 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
645 intel_dp->adapter.owner = THIS_MODULE;
646 intel_dp->adapter.class = I2C_CLASS_DDC;
647 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
648 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
649 intel_dp->adapter.algo_data = &intel_dp->algo;
650 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
652 ironlake_edp_panel_vdd_on(intel_dp);
653 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
654 ironlake_edp_panel_vdd_off(intel_dp, false);
659 intel_dp_set_clock(struct intel_encoder *encoder,
660 struct intel_crtc_config *pipe_config, int link_bw)
662 struct drm_device *dev = encoder->base.dev;
665 if (link_bw == DP_LINK_BW_1_62) {
666 pipe_config->dpll.p1 = 2;
667 pipe_config->dpll.p2 = 10;
668 pipe_config->dpll.n = 2;
669 pipe_config->dpll.m1 = 23;
670 pipe_config->dpll.m2 = 8;
672 pipe_config->dpll.p1 = 1;
673 pipe_config->dpll.p2 = 10;
674 pipe_config->dpll.n = 1;
675 pipe_config->dpll.m1 = 14;
676 pipe_config->dpll.m2 = 2;
678 pipe_config->clock_set = true;
679 } else if (IS_HASWELL(dev)) {
680 /* Haswell has special-purpose DP DDI clocks. */
681 } else if (HAS_PCH_SPLIT(dev)) {
682 if (link_bw == DP_LINK_BW_1_62) {
683 pipe_config->dpll.n = 1;
684 pipe_config->dpll.p1 = 2;
685 pipe_config->dpll.p2 = 10;
686 pipe_config->dpll.m1 = 12;
687 pipe_config->dpll.m2 = 9;
689 pipe_config->dpll.n = 2;
690 pipe_config->dpll.p1 = 1;
691 pipe_config->dpll.p2 = 10;
692 pipe_config->dpll.m1 = 14;
693 pipe_config->dpll.m2 = 8;
695 pipe_config->clock_set = true;
696 } else if (IS_VALLEYVIEW(dev)) {
697 /* FIXME: Need to figure out optimized DP clocks for vlv. */
702 intel_dp_compute_config(struct intel_encoder *encoder,
703 struct intel_crtc_config *pipe_config)
705 struct drm_device *dev = encoder->base.dev;
706 struct drm_i915_private *dev_priv = dev->dev_private;
707 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
708 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
709 enum port port = dp_to_dig_port(intel_dp)->port;
710 struct intel_crtc *intel_crtc = encoder->new_crtc;
711 struct intel_connector *intel_connector = intel_dp->attached_connector;
712 int lane_count, clock;
713 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
714 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
716 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
717 int link_avail, link_clock;
719 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
720 pipe_config->has_pch_encoder = true;
722 pipe_config->has_dp_encoder = true;
724 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
725 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
727 if (!HAS_PCH_SPLIT(dev))
728 intel_gmch_panel_fitting(intel_crtc, pipe_config,
729 intel_connector->panel.fitting_mode);
731 intel_pch_panel_fitting(intel_crtc, pipe_config,
732 intel_connector->panel.fitting_mode);
735 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
738 DRM_DEBUG_KMS("DP link computation with max lane count %i "
739 "max bw %02x pixel clock %iKHz\n",
740 max_lane_count, bws[max_clock], adjusted_mode->clock);
742 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
744 bpp = pipe_config->pipe_bpp;
745 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
746 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
747 dev_priv->vbt.edp_bpp);
748 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
751 for (; bpp >= 6*3; bpp -= 2*3) {
752 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
754 for (clock = 0; clock <= max_clock; clock++) {
755 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
756 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
757 link_avail = intel_dp_max_data_rate(link_clock,
760 if (mode_rate <= link_avail) {
770 if (intel_dp->color_range_auto) {
773 * CEA-861-E - 5.1 Default Encoding Parameters
774 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
776 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
777 intel_dp->color_range = DP_COLOR_RANGE_16_235;
779 intel_dp->color_range = 0;
782 if (intel_dp->color_range)
783 pipe_config->limited_color_range = true;
785 intel_dp->link_bw = bws[clock];
786 intel_dp->lane_count = lane_count;
787 pipe_config->pipe_bpp = bpp;
788 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
790 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
791 intel_dp->link_bw, intel_dp->lane_count,
792 pipe_config->port_clock, bpp);
793 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
794 mode_rate, link_avail);
796 intel_link_compute_m_n(bpp, lane_count,
797 adjusted_mode->clock, pipe_config->port_clock,
798 &pipe_config->dp_m_n);
800 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
805 void intel_dp_init_link_config(struct intel_dp *intel_dp)
807 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
808 intel_dp->link_configuration[0] = intel_dp->link_bw;
809 intel_dp->link_configuration[1] = intel_dp->lane_count;
810 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
812 * Check for DPCD version > 1.1 and enhanced framing support
814 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
815 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
816 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
820 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
822 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
823 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
824 struct drm_device *dev = crtc->base.dev;
825 struct drm_i915_private *dev_priv = dev->dev_private;
828 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
829 dpa_ctl = I915_READ(DP_A);
830 dpa_ctl &= ~DP_PLL_FREQ_MASK;
832 if (crtc->config.port_clock == 162000) {
833 /* For a long time we've carried around a ILK-DevA w/a for the
834 * 160MHz clock. If we're really unlucky, it's still required.
836 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
837 dpa_ctl |= DP_PLL_FREQ_160MHZ;
838 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
840 dpa_ctl |= DP_PLL_FREQ_270MHZ;
841 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
844 I915_WRITE(DP_A, dpa_ctl);
850 static void intel_dp_mode_set(struct intel_encoder *encoder)
852 struct drm_device *dev = encoder->base.dev;
853 struct drm_i915_private *dev_priv = dev->dev_private;
854 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
855 enum port port = dp_to_dig_port(intel_dp)->port;
856 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
857 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
860 * There are four kinds of DP registers:
867 * IBX PCH and CPU are the same for almost everything,
868 * except that the CPU DP PLL is configured in this
871 * CPT PCH is quite different, having many bits moved
872 * to the TRANS_DP_CTL register instead. That
873 * configuration happens (oddly) in ironlake_pch_enable
876 /* Preserve the BIOS-computed detected bit. This is
877 * supposed to be read-only.
879 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
881 /* Handle DP bits in common between all three register formats */
882 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
883 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
885 if (intel_dp->has_audio) {
886 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
887 pipe_name(crtc->pipe));
888 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
889 intel_write_eld(&encoder->base, adjusted_mode);
892 intel_dp_init_link_config(intel_dp);
894 /* Split out the IBX/CPU vs CPT settings */
896 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
897 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
898 intel_dp->DP |= DP_SYNC_HS_HIGH;
899 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
900 intel_dp->DP |= DP_SYNC_VS_HIGH;
901 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
903 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
904 intel_dp->DP |= DP_ENHANCED_FRAMING;
906 intel_dp->DP |= crtc->pipe << 29;
907 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
908 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
909 intel_dp->DP |= intel_dp->color_range;
911 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
912 intel_dp->DP |= DP_SYNC_HS_HIGH;
913 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
914 intel_dp->DP |= DP_SYNC_VS_HIGH;
915 intel_dp->DP |= DP_LINK_TRAIN_OFF;
917 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
918 intel_dp->DP |= DP_ENHANCED_FRAMING;
921 intel_dp->DP |= DP_PIPEB_SELECT;
923 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
926 if (port == PORT_A && !IS_VALLEYVIEW(dev))
927 ironlake_set_pll_cpu_edp(intel_dp);
930 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
931 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
933 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
934 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
936 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
937 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
939 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
943 struct drm_device *dev = intel_dp_to_dev(intel_dp);
944 struct drm_i915_private *dev_priv = dev->dev_private;
945 u32 pp_stat_reg, pp_ctrl_reg;
947 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
948 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
950 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
952 I915_READ(pp_stat_reg),
953 I915_READ(pp_ctrl_reg));
955 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
956 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
957 I915_READ(pp_stat_reg),
958 I915_READ(pp_ctrl_reg));
962 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
964 DRM_DEBUG_KMS("Wait for panel power on\n");
965 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
968 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
970 DRM_DEBUG_KMS("Wait for panel power off time\n");
971 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
974 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
976 DRM_DEBUG_KMS("Wait for panel power cycle\n");
977 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
981 /* Read the current pp_control value, unlocking the register if it
985 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
987 struct drm_device *dev = intel_dp_to_dev(intel_dp);
988 struct drm_i915_private *dev_priv = dev->dev_private;
992 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
993 control = I915_READ(pp_ctrl_reg);
995 control &= ~PANEL_UNLOCK_MASK;
996 control |= PANEL_UNLOCK_REGS;
1000 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1002 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1003 struct drm_i915_private *dev_priv = dev->dev_private;
1005 u32 pp_stat_reg, pp_ctrl_reg;
1007 if (!is_edp(intel_dp))
1009 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1011 WARN(intel_dp->want_panel_vdd,
1012 "eDP VDD already requested on\n");
1014 intel_dp->want_panel_vdd = true;
1016 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1017 DRM_DEBUG_KMS("eDP VDD already on\n");
1021 if (!ironlake_edp_have_panel_power(intel_dp))
1022 ironlake_wait_panel_power_cycle(intel_dp);
1024 pp = ironlake_get_pp_control(intel_dp);
1025 pp |= EDP_FORCE_VDD;
1027 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1028 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1030 I915_WRITE(pp_ctrl_reg, pp);
1031 POSTING_READ(pp_ctrl_reg);
1032 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1033 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1035 * If the panel wasn't on, delay before accessing aux channel
1037 if (!ironlake_edp_have_panel_power(intel_dp)) {
1038 DRM_DEBUG_KMS("eDP was not running\n");
1039 msleep(intel_dp->panel_power_up_delay);
1043 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1045 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1046 struct drm_i915_private *dev_priv = dev->dev_private;
1048 u32 pp_stat_reg, pp_ctrl_reg;
1050 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1052 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1053 pp = ironlake_get_pp_control(intel_dp);
1054 pp &= ~EDP_FORCE_VDD;
1056 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1057 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1059 I915_WRITE(pp_ctrl_reg, pp);
1060 POSTING_READ(pp_ctrl_reg);
1062 /* Make sure sequencer is idle before allowing subsequent activity */
1063 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1064 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1065 msleep(intel_dp->panel_power_down_delay);
1069 static void ironlake_panel_vdd_work(struct work_struct *__work)
1071 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1072 struct intel_dp, panel_vdd_work);
1073 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1075 mutex_lock(&dev->mode_config.mutex);
1076 ironlake_panel_vdd_off_sync(intel_dp);
1077 mutex_unlock(&dev->mode_config.mutex);
1080 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1082 if (!is_edp(intel_dp))
1085 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1086 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1088 intel_dp->want_panel_vdd = false;
1091 ironlake_panel_vdd_off_sync(intel_dp);
1094 * Queue the timer to fire a long
1095 * time from now (relative to the power down delay)
1096 * to keep the panel power up across a sequence of operations
1098 schedule_delayed_work(&intel_dp->panel_vdd_work,
1099 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1103 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1105 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1106 struct drm_i915_private *dev_priv = dev->dev_private;
1110 if (!is_edp(intel_dp))
1113 DRM_DEBUG_KMS("Turn eDP power on\n");
1115 if (ironlake_edp_have_panel_power(intel_dp)) {
1116 DRM_DEBUG_KMS("eDP power already on\n");
1120 ironlake_wait_panel_power_cycle(intel_dp);
1122 pp = ironlake_get_pp_control(intel_dp);
1124 /* ILK workaround: disable reset around power sequence */
1125 pp &= ~PANEL_POWER_RESET;
1126 I915_WRITE(PCH_PP_CONTROL, pp);
1127 POSTING_READ(PCH_PP_CONTROL);
1130 pp |= POWER_TARGET_ON;
1132 pp |= PANEL_POWER_RESET;
1134 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1136 I915_WRITE(pp_ctrl_reg, pp);
1137 POSTING_READ(pp_ctrl_reg);
1139 ironlake_wait_panel_on(intel_dp);
1142 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1143 I915_WRITE(PCH_PP_CONTROL, pp);
1144 POSTING_READ(PCH_PP_CONTROL);
1148 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1150 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1155 if (!is_edp(intel_dp))
1158 DRM_DEBUG_KMS("Turn eDP power off\n");
1160 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1162 pp = ironlake_get_pp_control(intel_dp);
1163 /* We need to switch off panel power _and_ force vdd, for otherwise some
1164 * panels get very unhappy and cease to work. */
1165 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1167 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1169 I915_WRITE(pp_ctrl_reg, pp);
1170 POSTING_READ(pp_ctrl_reg);
1172 intel_dp->want_panel_vdd = false;
1174 ironlake_wait_panel_off(intel_dp);
1177 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1179 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1180 struct drm_device *dev = intel_dig_port->base.base.dev;
1181 struct drm_i915_private *dev_priv = dev->dev_private;
1182 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1186 if (!is_edp(intel_dp))
1189 DRM_DEBUG_KMS("\n");
1191 * If we enable the backlight right away following a panel power
1192 * on, we may see slight flicker as the panel syncs with the eDP
1193 * link. So delay a bit to make sure the image is solid before
1194 * allowing it to appear.
1196 msleep(intel_dp->backlight_on_delay);
1197 pp = ironlake_get_pp_control(intel_dp);
1198 pp |= EDP_BLC_ENABLE;
1200 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1202 I915_WRITE(pp_ctrl_reg, pp);
1203 POSTING_READ(pp_ctrl_reg);
1205 intel_panel_enable_backlight(dev, pipe);
1208 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1210 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1211 struct drm_i915_private *dev_priv = dev->dev_private;
1215 if (!is_edp(intel_dp))
1218 intel_panel_disable_backlight(dev);
1220 DRM_DEBUG_KMS("\n");
1221 pp = ironlake_get_pp_control(intel_dp);
1222 pp &= ~EDP_BLC_ENABLE;
1224 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1226 I915_WRITE(pp_ctrl_reg, pp);
1227 POSTING_READ(pp_ctrl_reg);
1228 msleep(intel_dp->backlight_off_delay);
1231 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1233 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1234 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1235 struct drm_device *dev = crtc->dev;
1236 struct drm_i915_private *dev_priv = dev->dev_private;
1239 assert_pipe_disabled(dev_priv,
1240 to_intel_crtc(crtc)->pipe);
1242 DRM_DEBUG_KMS("\n");
1243 dpa_ctl = I915_READ(DP_A);
1244 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1245 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1247 /* We don't adjust intel_dp->DP while tearing down the link, to
1248 * facilitate link retraining (e.g. after hotplug). Hence clear all
1249 * enable bits here to ensure that we don't enable too much. */
1250 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1251 intel_dp->DP |= DP_PLL_ENABLE;
1252 I915_WRITE(DP_A, intel_dp->DP);
1257 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1261 struct drm_device *dev = crtc->dev;
1262 struct drm_i915_private *dev_priv = dev->dev_private;
1265 assert_pipe_disabled(dev_priv,
1266 to_intel_crtc(crtc)->pipe);
1268 dpa_ctl = I915_READ(DP_A);
1269 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1270 "dp pll off, should be on\n");
1271 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1273 /* We can't rely on the value tracked for the DP register in
1274 * intel_dp->DP because link_down must not change that (otherwise link
1275 * re-training will fail. */
1276 dpa_ctl &= ~DP_PLL_ENABLE;
1277 I915_WRITE(DP_A, dpa_ctl);
1282 /* If the sink supports it, try to set the power state appropriately */
1283 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1287 /* Should have a valid DPCD by this point */
1288 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1291 if (mode != DRM_MODE_DPMS_ON) {
1292 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1295 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1298 * When turning on, we need to retry for 1ms to give the sink
1301 for (i = 0; i < 3; i++) {
1302 ret = intel_dp_aux_native_write_1(intel_dp,
1312 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1315 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1316 enum port port = dp_to_dig_port(intel_dp)->port;
1317 struct drm_device *dev = encoder->base.dev;
1318 struct drm_i915_private *dev_priv = dev->dev_private;
1319 u32 tmp = I915_READ(intel_dp->output_reg);
1321 if (!(tmp & DP_PORT_EN))
1324 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1325 *pipe = PORT_TO_PIPE_CPT(tmp);
1326 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1327 *pipe = PORT_TO_PIPE(tmp);
1333 switch (intel_dp->output_reg) {
1335 trans_sel = TRANS_DP_PORT_SEL_B;
1338 trans_sel = TRANS_DP_PORT_SEL_C;
1341 trans_sel = TRANS_DP_PORT_SEL_D;
1348 trans_dp = I915_READ(TRANS_DP_CTL(i));
1349 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1355 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1356 intel_dp->output_reg);
1362 static void intel_dp_get_config(struct intel_encoder *encoder,
1363 struct intel_crtc_config *pipe_config)
1365 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1367 struct drm_device *dev = encoder->base.dev;
1368 struct drm_i915_private *dev_priv = dev->dev_private;
1369 enum port port = dp_to_dig_port(intel_dp)->port;
1370 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1372 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1373 tmp = I915_READ(intel_dp->output_reg);
1374 if (tmp & DP_SYNC_HS_HIGH)
1375 flags |= DRM_MODE_FLAG_PHSYNC;
1377 flags |= DRM_MODE_FLAG_NHSYNC;
1379 if (tmp & DP_SYNC_VS_HIGH)
1380 flags |= DRM_MODE_FLAG_PVSYNC;
1382 flags |= DRM_MODE_FLAG_NVSYNC;
1384 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1385 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1386 flags |= DRM_MODE_FLAG_PHSYNC;
1388 flags |= DRM_MODE_FLAG_NHSYNC;
1390 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1391 flags |= DRM_MODE_FLAG_PVSYNC;
1393 flags |= DRM_MODE_FLAG_NVSYNC;
1396 pipe_config->adjusted_mode.flags |= flags;
1398 if (dp_to_dig_port(intel_dp)->port == PORT_A) {
1399 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1400 pipe_config->port_clock = 162000;
1402 pipe_config->port_clock = 270000;
1406 static bool is_edp_psr(struct intel_dp *intel_dp)
1408 return is_edp(intel_dp) &&
1409 intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1412 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1414 struct drm_i915_private *dev_priv = dev->dev_private;
1416 if (!IS_HASWELL(dev))
1419 return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
1422 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1423 struct edp_vsc_psr *vsc_psr)
1425 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1426 struct drm_device *dev = dig_port->base.base.dev;
1427 struct drm_i915_private *dev_priv = dev->dev_private;
1428 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1429 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1430 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1431 uint32_t *data = (uint32_t *) vsc_psr;
1434 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1435 the video DIP being updated before program video DIP data buffer
1436 registers for DIP being updated. */
1437 I915_WRITE(ctl_reg, 0);
1438 POSTING_READ(ctl_reg);
1440 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1441 if (i < sizeof(struct edp_vsc_psr))
1442 I915_WRITE(data_reg + i, *data++);
1444 I915_WRITE(data_reg + i, 0);
1447 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1448 POSTING_READ(ctl_reg);
1451 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1453 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1454 struct drm_i915_private *dev_priv = dev->dev_private;
1455 struct edp_vsc_psr psr_vsc;
1457 if (intel_dp->psr_setup_done)
1460 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1461 memset(&psr_vsc, 0, sizeof(psr_vsc));
1462 psr_vsc.sdp_header.HB0 = 0;
1463 psr_vsc.sdp_header.HB1 = 0x7;
1464 psr_vsc.sdp_header.HB2 = 0x2;
1465 psr_vsc.sdp_header.HB3 = 0x8;
1466 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1468 /* Avoid continuous PSR exit by masking memup and hpd */
1469 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
1470 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1472 intel_dp->psr_setup_done = true;
1475 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1477 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1478 struct drm_i915_private *dev_priv = dev->dev_private;
1479 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1480 int precharge = 0x3;
1481 int msg_size = 5; /* Header(4) + Message(1) */
1483 /* Enable PSR in sink */
1484 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1485 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1487 ~DP_PSR_MAIN_LINK_ACTIVE);
1489 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1491 DP_PSR_MAIN_LINK_ACTIVE);
1493 /* Setup AUX registers */
1494 I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
1495 I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
1496 I915_WRITE(EDP_PSR_AUX_CTL,
1497 DP_AUX_CH_CTL_TIME_OUT_400us |
1498 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1499 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1500 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1503 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1505 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1506 struct drm_i915_private *dev_priv = dev->dev_private;
1507 uint32_t max_sleep_time = 0x1f;
1508 uint32_t idle_frames = 1;
1511 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1512 val |= EDP_PSR_LINK_STANDBY;
1513 val |= EDP_PSR_TP2_TP3_TIME_0us;
1514 val |= EDP_PSR_TP1_TIME_0us;
1515 val |= EDP_PSR_SKIP_AUX_EXIT;
1517 val |= EDP_PSR_LINK_DISABLE;
1519 I915_WRITE(EDP_PSR_CTL, val |
1520 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1521 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1522 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1526 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1528 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1529 struct drm_device *dev = dig_port->base.base.dev;
1530 struct drm_i915_private *dev_priv = dev->dev_private;
1531 struct drm_crtc *crtc = dig_port->base.base.crtc;
1532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1533 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1534 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1536 if (!IS_HASWELL(dev)) {
1537 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1538 dev_priv->no_psr_reason = PSR_NO_SOURCE;
1542 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1543 (dig_port->port != PORT_A)) {
1544 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1545 dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
1549 if (!is_edp_psr(intel_dp)) {
1550 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1551 dev_priv->no_psr_reason = PSR_NO_SINK;
1555 if (!i915_enable_psr) {
1556 DRM_DEBUG_KMS("PSR disable by flag\n");
1557 dev_priv->no_psr_reason = PSR_MODULE_PARAM;
1561 crtc = dig_port->base.base.crtc;
1563 DRM_DEBUG_KMS("crtc not active for PSR\n");
1564 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1568 intel_crtc = to_intel_crtc(crtc);
1569 if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) {
1570 DRM_DEBUG_KMS("crtc not active for PSR\n");
1571 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1575 obj = to_intel_framebuffer(crtc->fb)->obj;
1576 if (obj->tiling_mode != I915_TILING_X ||
1577 obj->fence_reg == I915_FENCE_REG_NONE) {
1578 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1579 dev_priv->no_psr_reason = PSR_NOT_TILED;
1583 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1584 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1585 dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
1589 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1591 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1592 dev_priv->no_psr_reason = PSR_S3D_ENABLED;
1596 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
1597 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1598 dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
1605 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1607 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1609 if (!intel_edp_psr_match_conditions(intel_dp) ||
1610 intel_edp_is_psr_enabled(dev))
1613 /* Setup PSR once */
1614 intel_edp_psr_setup(intel_dp);
1616 /* Enable PSR on the panel */
1617 intel_edp_psr_enable_sink(intel_dp);
1619 /* Enable PSR on the host */
1620 intel_edp_psr_enable_source(intel_dp);
1623 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1625 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1627 if (intel_edp_psr_match_conditions(intel_dp) &&
1628 !intel_edp_is_psr_enabled(dev))
1629 intel_edp_psr_do_enable(intel_dp);
1632 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1634 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1635 struct drm_i915_private *dev_priv = dev->dev_private;
1637 if (!intel_edp_is_psr_enabled(dev))
1640 I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
1642 /* Wait till PSR is idle */
1643 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
1644 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1645 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1648 void intel_edp_psr_update(struct drm_device *dev)
1650 struct intel_encoder *encoder;
1651 struct intel_dp *intel_dp = NULL;
1653 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1654 if (encoder->type == INTEL_OUTPUT_EDP) {
1655 intel_dp = enc_to_intel_dp(&encoder->base);
1657 if (!is_edp_psr(intel_dp))
1660 if (!intel_edp_psr_match_conditions(intel_dp))
1661 intel_edp_psr_disable(intel_dp);
1663 if (!intel_edp_is_psr_enabled(dev))
1664 intel_edp_psr_do_enable(intel_dp);
1668 static void intel_disable_dp(struct intel_encoder *encoder)
1670 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1671 enum port port = dp_to_dig_port(intel_dp)->port;
1672 struct drm_device *dev = encoder->base.dev;
1674 /* Make sure the panel is off before trying to change the mode. But also
1675 * ensure that we have vdd while we switch off the panel. */
1676 ironlake_edp_panel_vdd_on(intel_dp);
1677 ironlake_edp_backlight_off(intel_dp);
1678 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1679 ironlake_edp_panel_off(intel_dp);
1681 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1682 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1683 intel_dp_link_down(intel_dp);
1686 static void intel_post_disable_dp(struct intel_encoder *encoder)
1688 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1689 enum port port = dp_to_dig_port(intel_dp)->port;
1690 struct drm_device *dev = encoder->base.dev;
1692 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1693 intel_dp_link_down(intel_dp);
1694 if (!IS_VALLEYVIEW(dev))
1695 ironlake_edp_pll_off(intel_dp);
1699 static void intel_enable_dp(struct intel_encoder *encoder)
1701 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1702 struct drm_device *dev = encoder->base.dev;
1703 struct drm_i915_private *dev_priv = dev->dev_private;
1704 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1706 if (WARN_ON(dp_reg & DP_PORT_EN))
1709 ironlake_edp_panel_vdd_on(intel_dp);
1710 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1711 intel_dp_start_link_train(intel_dp);
1712 ironlake_edp_panel_on(intel_dp);
1713 ironlake_edp_panel_vdd_off(intel_dp, true);
1714 intel_dp_complete_link_train(intel_dp);
1715 intel_dp_stop_link_train(intel_dp);
1716 ironlake_edp_backlight_on(intel_dp);
1719 static void vlv_enable_dp(struct intel_encoder *encoder)
1723 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1725 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1726 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1728 if (dport->port == PORT_A)
1729 ironlake_edp_pll_on(intel_dp);
1732 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1734 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1735 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1736 struct drm_device *dev = encoder->base.dev;
1737 struct drm_i915_private *dev_priv = dev->dev_private;
1738 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1739 int port = vlv_dport_to_channel(dport);
1740 int pipe = intel_crtc->pipe;
1743 mutex_lock(&dev_priv->dpio_lock);
1745 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1752 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1753 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1754 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
1756 mutex_unlock(&dev_priv->dpio_lock);
1758 intel_enable_dp(encoder);
1760 vlv_wait_port_ready(dev_priv, port);
1763 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1765 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1766 struct drm_device *dev = encoder->base.dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 int port = vlv_dport_to_channel(dport);
1770 if (!IS_VALLEYVIEW(dev))
1773 /* Program Tx lane resets to default */
1774 mutex_lock(&dev_priv->dpio_lock);
1775 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1776 DPIO_PCS_TX_LANE2_RESET |
1777 DPIO_PCS_TX_LANE1_RESET);
1778 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1779 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1780 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1781 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1782 DPIO_PCS_CLK_SOFT_RESET);
1784 /* Fix up inter-pair skew failure */
1785 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1786 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1787 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1788 mutex_unlock(&dev_priv->dpio_lock);
1792 * Native read with retry for link status and receiver capability reads for
1793 * cases where the sink may still be asleep.
1796 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1797 uint8_t *recv, int recv_bytes)
1802 * Sinks are *supposed* to come up within 1ms from an off state,
1803 * but we're also supposed to retry 3 times per the spec.
1805 for (i = 0; i < 3; i++) {
1806 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1808 if (ret == recv_bytes)
1817 * Fetch AUX CH registers 0x202 - 0x207 which contain
1818 * link status information
1821 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1823 return intel_dp_aux_native_read_retry(intel_dp,
1826 DP_LINK_STATUS_SIZE);
1830 static char *voltage_names[] = {
1831 "0.4V", "0.6V", "0.8V", "1.2V"
1833 static char *pre_emph_names[] = {
1834 "0dB", "3.5dB", "6dB", "9.5dB"
1836 static char *link_train_names[] = {
1837 "pattern 1", "pattern 2", "idle", "off"
1842 * These are source-specific values; current Intel hardware supports
1843 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1847 intel_dp_voltage_max(struct intel_dp *intel_dp)
1849 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1850 enum port port = dp_to_dig_port(intel_dp)->port;
1852 if (IS_VALLEYVIEW(dev))
1853 return DP_TRAIN_VOLTAGE_SWING_1200;
1854 else if (IS_GEN7(dev) && port == PORT_A)
1855 return DP_TRAIN_VOLTAGE_SWING_800;
1856 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1857 return DP_TRAIN_VOLTAGE_SWING_1200;
1859 return DP_TRAIN_VOLTAGE_SWING_800;
1863 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1865 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1866 enum port port = dp_to_dig_port(intel_dp)->port;
1869 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1870 case DP_TRAIN_VOLTAGE_SWING_400:
1871 return DP_TRAIN_PRE_EMPHASIS_9_5;
1872 case DP_TRAIN_VOLTAGE_SWING_600:
1873 return DP_TRAIN_PRE_EMPHASIS_6;
1874 case DP_TRAIN_VOLTAGE_SWING_800:
1875 return DP_TRAIN_PRE_EMPHASIS_3_5;
1876 case DP_TRAIN_VOLTAGE_SWING_1200:
1878 return DP_TRAIN_PRE_EMPHASIS_0;
1880 } else if (IS_VALLEYVIEW(dev)) {
1881 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1882 case DP_TRAIN_VOLTAGE_SWING_400:
1883 return DP_TRAIN_PRE_EMPHASIS_9_5;
1884 case DP_TRAIN_VOLTAGE_SWING_600:
1885 return DP_TRAIN_PRE_EMPHASIS_6;
1886 case DP_TRAIN_VOLTAGE_SWING_800:
1887 return DP_TRAIN_PRE_EMPHASIS_3_5;
1888 case DP_TRAIN_VOLTAGE_SWING_1200:
1890 return DP_TRAIN_PRE_EMPHASIS_0;
1892 } else if (IS_GEN7(dev) && port == PORT_A) {
1893 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1894 case DP_TRAIN_VOLTAGE_SWING_400:
1895 return DP_TRAIN_PRE_EMPHASIS_6;
1896 case DP_TRAIN_VOLTAGE_SWING_600:
1897 case DP_TRAIN_VOLTAGE_SWING_800:
1898 return DP_TRAIN_PRE_EMPHASIS_3_5;
1900 return DP_TRAIN_PRE_EMPHASIS_0;
1903 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1904 case DP_TRAIN_VOLTAGE_SWING_400:
1905 return DP_TRAIN_PRE_EMPHASIS_6;
1906 case DP_TRAIN_VOLTAGE_SWING_600:
1907 return DP_TRAIN_PRE_EMPHASIS_6;
1908 case DP_TRAIN_VOLTAGE_SWING_800:
1909 return DP_TRAIN_PRE_EMPHASIS_3_5;
1910 case DP_TRAIN_VOLTAGE_SWING_1200:
1912 return DP_TRAIN_PRE_EMPHASIS_0;
1917 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1919 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1920 struct drm_i915_private *dev_priv = dev->dev_private;
1921 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1922 unsigned long demph_reg_value, preemph_reg_value,
1923 uniqtranscale_reg_value;
1924 uint8_t train_set = intel_dp->train_set[0];
1925 int port = vlv_dport_to_channel(dport);
1927 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1928 case DP_TRAIN_PRE_EMPHASIS_0:
1929 preemph_reg_value = 0x0004000;
1930 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1931 case DP_TRAIN_VOLTAGE_SWING_400:
1932 demph_reg_value = 0x2B405555;
1933 uniqtranscale_reg_value = 0x552AB83A;
1935 case DP_TRAIN_VOLTAGE_SWING_600:
1936 demph_reg_value = 0x2B404040;
1937 uniqtranscale_reg_value = 0x5548B83A;
1939 case DP_TRAIN_VOLTAGE_SWING_800:
1940 demph_reg_value = 0x2B245555;
1941 uniqtranscale_reg_value = 0x5560B83A;
1943 case DP_TRAIN_VOLTAGE_SWING_1200:
1944 demph_reg_value = 0x2B405555;
1945 uniqtranscale_reg_value = 0x5598DA3A;
1951 case DP_TRAIN_PRE_EMPHASIS_3_5:
1952 preemph_reg_value = 0x0002000;
1953 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1954 case DP_TRAIN_VOLTAGE_SWING_400:
1955 demph_reg_value = 0x2B404040;
1956 uniqtranscale_reg_value = 0x5552B83A;
1958 case DP_TRAIN_VOLTAGE_SWING_600:
1959 demph_reg_value = 0x2B404848;
1960 uniqtranscale_reg_value = 0x5580B83A;
1962 case DP_TRAIN_VOLTAGE_SWING_800:
1963 demph_reg_value = 0x2B404040;
1964 uniqtranscale_reg_value = 0x55ADDA3A;
1970 case DP_TRAIN_PRE_EMPHASIS_6:
1971 preemph_reg_value = 0x0000000;
1972 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1973 case DP_TRAIN_VOLTAGE_SWING_400:
1974 demph_reg_value = 0x2B305555;
1975 uniqtranscale_reg_value = 0x5570B83A;
1977 case DP_TRAIN_VOLTAGE_SWING_600:
1978 demph_reg_value = 0x2B2B4040;
1979 uniqtranscale_reg_value = 0x55ADDA3A;
1985 case DP_TRAIN_PRE_EMPHASIS_9_5:
1986 preemph_reg_value = 0x0006000;
1987 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1988 case DP_TRAIN_VOLTAGE_SWING_400:
1989 demph_reg_value = 0x1B405555;
1990 uniqtranscale_reg_value = 0x55ADDA3A;
2000 mutex_lock(&dev_priv->dpio_lock);
2001 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
2002 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
2003 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
2004 uniqtranscale_reg_value);
2005 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
2006 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
2007 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
2008 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
2009 mutex_unlock(&dev_priv->dpio_lock);
2015 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2020 uint8_t voltage_max;
2021 uint8_t preemph_max;
2023 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2024 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2025 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2033 voltage_max = intel_dp_voltage_max(intel_dp);
2034 if (v >= voltage_max)
2035 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2037 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2038 if (p >= preemph_max)
2039 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2041 for (lane = 0; lane < 4; lane++)
2042 intel_dp->train_set[lane] = v | p;
2046 intel_gen4_signal_levels(uint8_t train_set)
2048 uint32_t signal_levels = 0;
2050 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2051 case DP_TRAIN_VOLTAGE_SWING_400:
2053 signal_levels |= DP_VOLTAGE_0_4;
2055 case DP_TRAIN_VOLTAGE_SWING_600:
2056 signal_levels |= DP_VOLTAGE_0_6;
2058 case DP_TRAIN_VOLTAGE_SWING_800:
2059 signal_levels |= DP_VOLTAGE_0_8;
2061 case DP_TRAIN_VOLTAGE_SWING_1200:
2062 signal_levels |= DP_VOLTAGE_1_2;
2065 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2066 case DP_TRAIN_PRE_EMPHASIS_0:
2068 signal_levels |= DP_PRE_EMPHASIS_0;
2070 case DP_TRAIN_PRE_EMPHASIS_3_5:
2071 signal_levels |= DP_PRE_EMPHASIS_3_5;
2073 case DP_TRAIN_PRE_EMPHASIS_6:
2074 signal_levels |= DP_PRE_EMPHASIS_6;
2076 case DP_TRAIN_PRE_EMPHASIS_9_5:
2077 signal_levels |= DP_PRE_EMPHASIS_9_5;
2080 return signal_levels;
2083 /* Gen6's DP voltage swing and pre-emphasis control */
2085 intel_gen6_edp_signal_levels(uint8_t train_set)
2087 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2088 DP_TRAIN_PRE_EMPHASIS_MASK);
2089 switch (signal_levels) {
2090 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2091 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2092 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2093 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2094 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2095 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2096 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2097 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2098 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2099 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2100 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2101 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2102 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2103 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2105 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2106 "0x%x\n", signal_levels);
2107 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2111 /* Gen7's DP voltage swing and pre-emphasis control */
2113 intel_gen7_edp_signal_levels(uint8_t train_set)
2115 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2116 DP_TRAIN_PRE_EMPHASIS_MASK);
2117 switch (signal_levels) {
2118 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2119 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2120 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2121 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2122 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2123 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2125 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2126 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2127 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2128 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2130 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2131 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2132 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2133 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2136 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2137 "0x%x\n", signal_levels);
2138 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2142 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2144 intel_hsw_signal_levels(uint8_t train_set)
2146 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2147 DP_TRAIN_PRE_EMPHASIS_MASK);
2148 switch (signal_levels) {
2149 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2150 return DDI_BUF_EMP_400MV_0DB_HSW;
2151 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2152 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2153 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2154 return DDI_BUF_EMP_400MV_6DB_HSW;
2155 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2156 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2158 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2159 return DDI_BUF_EMP_600MV_0DB_HSW;
2160 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2161 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2162 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2163 return DDI_BUF_EMP_600MV_6DB_HSW;
2165 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2166 return DDI_BUF_EMP_800MV_0DB_HSW;
2167 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2168 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2170 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2171 "0x%x\n", signal_levels);
2172 return DDI_BUF_EMP_400MV_0DB_HSW;
2176 /* Properly updates "DP" with the correct signal levels. */
2178 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2180 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2181 enum port port = intel_dig_port->port;
2182 struct drm_device *dev = intel_dig_port->base.base.dev;
2183 uint32_t signal_levels, mask;
2184 uint8_t train_set = intel_dp->train_set[0];
2187 signal_levels = intel_hsw_signal_levels(train_set);
2188 mask = DDI_BUF_EMP_MASK;
2189 } else if (IS_VALLEYVIEW(dev)) {
2190 signal_levels = intel_vlv_signal_levels(intel_dp);
2192 } else if (IS_GEN7(dev) && port == PORT_A) {
2193 signal_levels = intel_gen7_edp_signal_levels(train_set);
2194 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2195 } else if (IS_GEN6(dev) && port == PORT_A) {
2196 signal_levels = intel_gen6_edp_signal_levels(train_set);
2197 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2199 signal_levels = intel_gen4_signal_levels(train_set);
2200 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2203 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2205 *DP = (*DP & ~mask) | signal_levels;
2209 intel_dp_set_link_train(struct intel_dp *intel_dp,
2210 uint32_t dp_reg_value,
2211 uint8_t dp_train_pat)
2213 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2214 struct drm_device *dev = intel_dig_port->base.base.dev;
2215 struct drm_i915_private *dev_priv = dev->dev_private;
2216 enum port port = intel_dig_port->port;
2220 uint32_t temp = I915_READ(DP_TP_CTL(port));
2222 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2223 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2225 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2227 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2228 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2229 case DP_TRAINING_PATTERN_DISABLE:
2230 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2233 case DP_TRAINING_PATTERN_1:
2234 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2236 case DP_TRAINING_PATTERN_2:
2237 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2239 case DP_TRAINING_PATTERN_3:
2240 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2243 I915_WRITE(DP_TP_CTL(port), temp);
2245 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2246 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
2248 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2249 case DP_TRAINING_PATTERN_DISABLE:
2250 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
2252 case DP_TRAINING_PATTERN_1:
2253 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
2255 case DP_TRAINING_PATTERN_2:
2256 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2258 case DP_TRAINING_PATTERN_3:
2259 DRM_ERROR("DP training pattern 3 not supported\n");
2260 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2265 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2267 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2268 case DP_TRAINING_PATTERN_DISABLE:
2269 dp_reg_value |= DP_LINK_TRAIN_OFF;
2271 case DP_TRAINING_PATTERN_1:
2272 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2274 case DP_TRAINING_PATTERN_2:
2275 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2277 case DP_TRAINING_PATTERN_3:
2278 DRM_ERROR("DP training pattern 3 not supported\n");
2279 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2284 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2285 POSTING_READ(intel_dp->output_reg);
2287 intel_dp_aux_native_write_1(intel_dp,
2288 DP_TRAINING_PATTERN_SET,
2291 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2292 DP_TRAINING_PATTERN_DISABLE) {
2293 ret = intel_dp_aux_native_write(intel_dp,
2294 DP_TRAINING_LANE0_SET,
2295 intel_dp->train_set,
2296 intel_dp->lane_count);
2297 if (ret != intel_dp->lane_count)
2304 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2306 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2307 struct drm_device *dev = intel_dig_port->base.base.dev;
2308 struct drm_i915_private *dev_priv = dev->dev_private;
2309 enum port port = intel_dig_port->port;
2315 val = I915_READ(DP_TP_CTL(port));
2316 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2317 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2318 I915_WRITE(DP_TP_CTL(port), val);
2321 * On PORT_A we can have only eDP in SST mode. There the only reason
2322 * we need to set idle transmission mode is to work around a HW issue
2323 * where we enable the pipe while not in idle link-training mode.
2324 * In this case there is requirement to wait for a minimum number of
2325 * idle patterns to be sent.
2330 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2332 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2335 /* Enable corresponding port and start training pattern 1 */
2337 intel_dp_start_link_train(struct intel_dp *intel_dp)
2339 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2340 struct drm_device *dev = encoder->dev;
2343 int voltage_tries, loop_tries;
2344 uint32_t DP = intel_dp->DP;
2347 intel_ddi_prepare_link_retrain(encoder);
2349 /* Write the link configuration data */
2350 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2351 intel_dp->link_configuration,
2352 DP_LINK_CONFIGURATION_SIZE);
2356 memset(intel_dp->train_set, 0, 4);
2361 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2362 uint8_t link_status[DP_LINK_STATUS_SIZE];
2364 intel_dp_set_signal_levels(intel_dp, &DP);
2366 /* Set training pattern 1 */
2367 if (!intel_dp_set_link_train(intel_dp, DP,
2368 DP_TRAINING_PATTERN_1 |
2369 DP_LINK_SCRAMBLING_DISABLE))
2372 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2373 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2374 DRM_ERROR("failed to get link status\n");
2378 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2379 DRM_DEBUG_KMS("clock recovery OK\n");
2383 /* Check to see if we've tried the max voltage */
2384 for (i = 0; i < intel_dp->lane_count; i++)
2385 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2387 if (i == intel_dp->lane_count) {
2389 if (loop_tries == 5) {
2390 DRM_DEBUG_KMS("too many full retries, give up\n");
2393 memset(intel_dp->train_set, 0, 4);
2398 /* Check to see if we've tried the same voltage 5 times */
2399 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2401 if (voltage_tries == 5) {
2402 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2407 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2409 /* Compute new intel_dp->train_set as requested by target */
2410 intel_get_adjust_train(intel_dp, link_status);
2417 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2419 bool channel_eq = false;
2420 int tries, cr_tries;
2421 uint32_t DP = intel_dp->DP;
2423 /* channel equalization */
2428 uint8_t link_status[DP_LINK_STATUS_SIZE];
2431 DRM_ERROR("failed to train DP, aborting\n");
2432 intel_dp_link_down(intel_dp);
2436 intel_dp_set_signal_levels(intel_dp, &DP);
2438 /* channel eq pattern */
2439 if (!intel_dp_set_link_train(intel_dp, DP,
2440 DP_TRAINING_PATTERN_2 |
2441 DP_LINK_SCRAMBLING_DISABLE))
2444 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2445 if (!intel_dp_get_link_status(intel_dp, link_status))
2448 /* Make sure clock is still ok */
2449 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2450 intel_dp_start_link_train(intel_dp);
2455 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2460 /* Try 5 times, then try clock recovery if that fails */
2462 intel_dp_link_down(intel_dp);
2463 intel_dp_start_link_train(intel_dp);
2469 /* Compute new intel_dp->train_set as requested by target */
2470 intel_get_adjust_train(intel_dp, link_status);
2474 intel_dp_set_idle_link_train(intel_dp);
2479 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2483 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2485 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2486 DP_TRAINING_PATTERN_DISABLE);
2490 intel_dp_link_down(struct intel_dp *intel_dp)
2492 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2493 enum port port = intel_dig_port->port;
2494 struct drm_device *dev = intel_dig_port->base.base.dev;
2495 struct drm_i915_private *dev_priv = dev->dev_private;
2496 struct intel_crtc *intel_crtc =
2497 to_intel_crtc(intel_dig_port->base.base.crtc);
2498 uint32_t DP = intel_dp->DP;
2501 * DDI code has a strict mode set sequence and we should try to respect
2502 * it, otherwise we might hang the machine in many different ways. So we
2503 * really should be disabling the port only on a complete crtc_disable
2504 * sequence. This function is just called under two conditions on DDI
2506 * - Link train failed while doing crtc_enable, and on this case we
2507 * really should respect the mode set sequence and wait for a
2509 * - Someone turned the monitor off and intel_dp_check_link_status
2510 * called us. We don't need to disable the whole port on this case, so
2511 * when someone turns the monitor on again,
2512 * intel_ddi_prepare_link_retrain will take care of redoing the link
2518 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2521 DRM_DEBUG_KMS("\n");
2523 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2524 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2525 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2527 DP &= ~DP_LINK_TRAIN_MASK;
2528 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2530 POSTING_READ(intel_dp->output_reg);
2532 /* We don't really know why we're doing this */
2533 intel_wait_for_vblank(dev, intel_crtc->pipe);
2535 if (HAS_PCH_IBX(dev) &&
2536 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2537 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2539 /* Hardware workaround: leaving our transcoder select
2540 * set to transcoder B while it's off will prevent the
2541 * corresponding HDMI output on transcoder A.
2543 * Combine this with another hardware workaround:
2544 * transcoder select bit can only be cleared while the
2547 DP &= ~DP_PIPEB_SELECT;
2548 I915_WRITE(intel_dp->output_reg, DP);
2550 /* Changes to enable or select take place the vblank
2551 * after being written.
2553 if (WARN_ON(crtc == NULL)) {
2554 /* We should never try to disable a port without a crtc
2555 * attached. For paranoia keep the code around for a
2557 POSTING_READ(intel_dp->output_reg);
2560 intel_wait_for_vblank(dev, intel_crtc->pipe);
2563 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2564 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2565 POSTING_READ(intel_dp->output_reg);
2566 msleep(intel_dp->panel_power_down_delay);
2570 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2572 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2574 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2575 sizeof(intel_dp->dpcd)) == 0)
2576 return false; /* aux transfer failed */
2578 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2579 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2580 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2582 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2583 return false; /* DPCD not present */
2585 /* Check if the panel supports PSR */
2586 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2587 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2589 sizeof(intel_dp->psr_dpcd));
2590 if (is_edp_psr(intel_dp))
2591 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2592 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2593 DP_DWN_STRM_PORT_PRESENT))
2594 return true; /* native DP sink */
2596 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2597 return true; /* no per-port downstream info */
2599 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2600 intel_dp->downstream_ports,
2601 DP_MAX_DOWNSTREAM_PORTS) == 0)
2602 return false; /* downstream port status fetch failed */
2608 intel_dp_probe_oui(struct intel_dp *intel_dp)
2612 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2615 ironlake_edp_panel_vdd_on(intel_dp);
2617 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2618 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2619 buf[0], buf[1], buf[2]);
2621 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2622 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2623 buf[0], buf[1], buf[2]);
2625 ironlake_edp_panel_vdd_off(intel_dp, false);
2629 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2633 ret = intel_dp_aux_native_read_retry(intel_dp,
2634 DP_DEVICE_SERVICE_IRQ_VECTOR,
2635 sink_irq_vector, 1);
2643 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2645 /* NAK by default */
2646 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2650 * According to DP spec
2653 * 2. Configure link according to Receiver Capabilities
2654 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2655 * 4. Check link status on receipt of hot-plug interrupt
2659 intel_dp_check_link_status(struct intel_dp *intel_dp)
2661 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2663 u8 link_status[DP_LINK_STATUS_SIZE];
2665 if (!intel_encoder->connectors_active)
2668 if (WARN_ON(!intel_encoder->base.crtc))
2671 /* Try to read receiver status if the link appears to be up */
2672 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2673 intel_dp_link_down(intel_dp);
2677 /* Now read the DPCD to see if it's actually running */
2678 if (!intel_dp_get_dpcd(intel_dp)) {
2679 intel_dp_link_down(intel_dp);
2683 /* Try to read the source of the interrupt */
2684 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2685 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2686 /* Clear interrupt source */
2687 intel_dp_aux_native_write_1(intel_dp,
2688 DP_DEVICE_SERVICE_IRQ_VECTOR,
2691 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2692 intel_dp_handle_test_request(intel_dp);
2693 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2694 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2697 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2698 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2699 drm_get_encoder_name(&intel_encoder->base));
2700 intel_dp_start_link_train(intel_dp);
2701 intel_dp_complete_link_train(intel_dp);
2702 intel_dp_stop_link_train(intel_dp);
2706 /* XXX this is probably wrong for multiple downstream ports */
2707 static enum drm_connector_status
2708 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2710 uint8_t *dpcd = intel_dp->dpcd;
2714 if (!intel_dp_get_dpcd(intel_dp))
2715 return connector_status_disconnected;
2717 /* if there's no downstream port, we're done */
2718 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2719 return connector_status_connected;
2721 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2722 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2725 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2727 return connector_status_unknown;
2728 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2729 : connector_status_disconnected;
2732 /* If no HPD, poke DDC gently */
2733 if (drm_probe_ddc(&intel_dp->adapter))
2734 return connector_status_connected;
2736 /* Well we tried, say unknown for unreliable port types */
2737 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2738 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2739 return connector_status_unknown;
2741 /* Anything else is out of spec, warn and ignore */
2742 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2743 return connector_status_disconnected;
2746 static enum drm_connector_status
2747 ironlake_dp_detect(struct intel_dp *intel_dp)
2749 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2750 struct drm_i915_private *dev_priv = dev->dev_private;
2751 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2752 enum drm_connector_status status;
2754 /* Can't disconnect eDP, but you can close the lid... */
2755 if (is_edp(intel_dp)) {
2756 status = intel_panel_detect(dev);
2757 if (status == connector_status_unknown)
2758 status = connector_status_connected;
2762 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2763 return connector_status_disconnected;
2765 return intel_dp_detect_dpcd(intel_dp);
2768 static enum drm_connector_status
2769 g4x_dp_detect(struct intel_dp *intel_dp)
2771 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2772 struct drm_i915_private *dev_priv = dev->dev_private;
2773 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2776 /* Can't disconnect eDP, but you can close the lid... */
2777 if (is_edp(intel_dp)) {
2778 enum drm_connector_status status;
2780 status = intel_panel_detect(dev);
2781 if (status == connector_status_unknown)
2782 status = connector_status_connected;
2786 switch (intel_dig_port->port) {
2788 bit = PORTB_HOTPLUG_LIVE_STATUS;
2791 bit = PORTC_HOTPLUG_LIVE_STATUS;
2794 bit = PORTD_HOTPLUG_LIVE_STATUS;
2797 return connector_status_unknown;
2800 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2801 return connector_status_disconnected;
2803 return intel_dp_detect_dpcd(intel_dp);
2806 static struct edid *
2807 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2809 struct intel_connector *intel_connector = to_intel_connector(connector);
2811 /* use cached edid if we have one */
2812 if (intel_connector->edid) {
2817 if (IS_ERR(intel_connector->edid))
2820 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2821 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
2828 return drm_get_edid(connector, adapter);
2832 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2834 struct intel_connector *intel_connector = to_intel_connector(connector);
2836 /* use cached edid if we have one */
2837 if (intel_connector->edid) {
2839 if (IS_ERR(intel_connector->edid))
2842 return intel_connector_update_modes(connector,
2843 intel_connector->edid);
2846 return intel_ddc_get_modes(connector, adapter);
2849 static enum drm_connector_status
2850 intel_dp_detect(struct drm_connector *connector, bool force)
2852 struct intel_dp *intel_dp = intel_attached_dp(connector);
2853 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2854 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2855 struct drm_device *dev = connector->dev;
2856 enum drm_connector_status status;
2857 struct edid *edid = NULL;
2859 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2860 connector->base.id, drm_get_connector_name(connector));
2862 intel_dp->has_audio = false;
2864 if (HAS_PCH_SPLIT(dev))
2865 status = ironlake_dp_detect(intel_dp);
2867 status = g4x_dp_detect(intel_dp);
2869 if (status != connector_status_connected)
2872 intel_dp_probe_oui(intel_dp);
2874 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2875 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2877 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2879 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2884 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2885 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2886 return connector_status_connected;
2889 static int intel_dp_get_modes(struct drm_connector *connector)
2891 struct intel_dp *intel_dp = intel_attached_dp(connector);
2892 struct intel_connector *intel_connector = to_intel_connector(connector);
2893 struct drm_device *dev = connector->dev;
2896 /* We should parse the EDID data and find out if it has an audio sink
2899 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2903 /* if eDP has no EDID, fall back to fixed mode */
2904 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2905 struct drm_display_mode *mode;
2906 mode = drm_mode_duplicate(dev,
2907 intel_connector->panel.fixed_mode);
2909 drm_mode_probed_add(connector, mode);
2917 intel_dp_detect_audio(struct drm_connector *connector)
2919 struct intel_dp *intel_dp = intel_attached_dp(connector);
2921 bool has_audio = false;
2923 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2925 has_audio = drm_detect_monitor_audio(edid);
2933 intel_dp_set_property(struct drm_connector *connector,
2934 struct drm_property *property,
2937 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2938 struct intel_connector *intel_connector = to_intel_connector(connector);
2939 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2940 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2943 ret = drm_object_property_set_value(&connector->base, property, val);
2947 if (property == dev_priv->force_audio_property) {
2951 if (i == intel_dp->force_audio)
2954 intel_dp->force_audio = i;
2956 if (i == HDMI_AUDIO_AUTO)
2957 has_audio = intel_dp_detect_audio(connector);
2959 has_audio = (i == HDMI_AUDIO_ON);
2961 if (has_audio == intel_dp->has_audio)
2964 intel_dp->has_audio = has_audio;
2968 if (property == dev_priv->broadcast_rgb_property) {
2969 bool old_auto = intel_dp->color_range_auto;
2970 uint32_t old_range = intel_dp->color_range;
2973 case INTEL_BROADCAST_RGB_AUTO:
2974 intel_dp->color_range_auto = true;
2976 case INTEL_BROADCAST_RGB_FULL:
2977 intel_dp->color_range_auto = false;
2978 intel_dp->color_range = 0;
2980 case INTEL_BROADCAST_RGB_LIMITED:
2981 intel_dp->color_range_auto = false;
2982 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2988 if (old_auto == intel_dp->color_range_auto &&
2989 old_range == intel_dp->color_range)
2995 if (is_edp(intel_dp) &&
2996 property == connector->dev->mode_config.scaling_mode_property) {
2997 if (val == DRM_MODE_SCALE_NONE) {
2998 DRM_DEBUG_KMS("no scaling not supported\n");
3002 if (intel_connector->panel.fitting_mode == val) {
3003 /* the eDP scaling property is not changed */
3006 intel_connector->panel.fitting_mode = val;
3014 if (intel_encoder->base.crtc)
3015 intel_crtc_restore_mode(intel_encoder->base.crtc);
3021 intel_dp_connector_destroy(struct drm_connector *connector)
3023 struct intel_connector *intel_connector = to_intel_connector(connector);
3025 if (!IS_ERR_OR_NULL(intel_connector->edid))
3026 kfree(intel_connector->edid);
3028 /* Can't call is_edp() since the encoder may have been destroyed
3030 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3031 intel_panel_fini(&intel_connector->panel);
3033 drm_sysfs_connector_remove(connector);
3034 drm_connector_cleanup(connector);
3038 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3040 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3041 struct intel_dp *intel_dp = &intel_dig_port->dp;
3042 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3044 i2c_del_adapter(&intel_dp->adapter);
3045 drm_encoder_cleanup(encoder);
3046 if (is_edp(intel_dp)) {
3047 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3048 mutex_lock(&dev->mode_config.mutex);
3049 ironlake_panel_vdd_off_sync(intel_dp);
3050 mutex_unlock(&dev->mode_config.mutex);
3052 kfree(intel_dig_port);
3055 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3056 .dpms = intel_connector_dpms,
3057 .detect = intel_dp_detect,
3058 .fill_modes = drm_helper_probe_single_connector_modes,
3059 .set_property = intel_dp_set_property,
3060 .destroy = intel_dp_connector_destroy,
3063 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3064 .get_modes = intel_dp_get_modes,
3065 .mode_valid = intel_dp_mode_valid,
3066 .best_encoder = intel_best_encoder,
3069 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3070 .destroy = intel_dp_encoder_destroy,
3074 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3076 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3078 intel_dp_check_link_status(intel_dp);
3081 /* Return which DP Port should be selected for Transcoder DP control */
3083 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3085 struct drm_device *dev = crtc->dev;
3086 struct intel_encoder *intel_encoder;
3087 struct intel_dp *intel_dp;
3089 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3090 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3092 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3093 intel_encoder->type == INTEL_OUTPUT_EDP)
3094 return intel_dp->output_reg;
3100 /* check the VBT to see whether the eDP is on DP-D port */
3101 bool intel_dpd_is_edp(struct drm_device *dev)
3103 struct drm_i915_private *dev_priv = dev->dev_private;
3104 struct child_device_config *p_child;
3107 if (!dev_priv->vbt.child_dev_num)
3110 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3111 p_child = dev_priv->vbt.child_dev + i;
3113 if (p_child->dvo_port == PORT_IDPD &&
3114 p_child->device_type == DEVICE_TYPE_eDP)
3121 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3123 struct intel_connector *intel_connector = to_intel_connector(connector);
3125 intel_attach_force_audio_property(connector);
3126 intel_attach_broadcast_rgb_property(connector);
3127 intel_dp->color_range_auto = true;
3129 if (is_edp(intel_dp)) {
3130 drm_mode_create_scaling_mode_property(connector->dev);
3131 drm_object_attach_property(
3133 connector->dev->mode_config.scaling_mode_property,
3134 DRM_MODE_SCALE_ASPECT);
3135 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3140 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3141 struct intel_dp *intel_dp,
3142 struct edp_power_seq *out)
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 struct edp_power_seq cur, vbt, spec, final;
3146 u32 pp_on, pp_off, pp_div, pp;
3147 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3149 if (HAS_PCH_SPLIT(dev)) {
3150 pp_control_reg = PCH_PP_CONTROL;
3151 pp_on_reg = PCH_PP_ON_DELAYS;
3152 pp_off_reg = PCH_PP_OFF_DELAYS;
3153 pp_div_reg = PCH_PP_DIVISOR;
3155 pp_control_reg = PIPEA_PP_CONTROL;
3156 pp_on_reg = PIPEA_PP_ON_DELAYS;
3157 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3158 pp_div_reg = PIPEA_PP_DIVISOR;
3161 /* Workaround: Need to write PP_CONTROL with the unlock key as
3162 * the very first thing. */
3163 pp = ironlake_get_pp_control(intel_dp);
3164 I915_WRITE(pp_control_reg, pp);
3166 pp_on = I915_READ(pp_on_reg);
3167 pp_off = I915_READ(pp_off_reg);
3168 pp_div = I915_READ(pp_div_reg);
3170 /* Pull timing values out of registers */
3171 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3172 PANEL_POWER_UP_DELAY_SHIFT;
3174 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3175 PANEL_LIGHT_ON_DELAY_SHIFT;
3177 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3178 PANEL_LIGHT_OFF_DELAY_SHIFT;
3180 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3181 PANEL_POWER_DOWN_DELAY_SHIFT;
3183 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3184 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3186 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3187 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3189 vbt = dev_priv->vbt.edp_pps;
3191 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3192 * our hw here, which are all in 100usec. */
3193 spec.t1_t3 = 210 * 10;
3194 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3195 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3196 spec.t10 = 500 * 10;
3197 /* This one is special and actually in units of 100ms, but zero
3198 * based in the hw (so we need to add 100 ms). But the sw vbt
3199 * table multiplies it with 1000 to make it in units of 100usec,
3201 spec.t11_t12 = (510 + 100) * 10;
3203 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3204 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3206 /* Use the max of the register settings and vbt. If both are
3207 * unset, fall back to the spec limits. */
3208 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3210 max(cur.field, vbt.field))
3211 assign_final(t1_t3);
3215 assign_final(t11_t12);
3218 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3219 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3220 intel_dp->backlight_on_delay = get_delay(t8);
3221 intel_dp->backlight_off_delay = get_delay(t9);
3222 intel_dp->panel_power_down_delay = get_delay(t10);
3223 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3226 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3227 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3228 intel_dp->panel_power_cycle_delay);
3230 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3231 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3238 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3239 struct intel_dp *intel_dp,
3240 struct edp_power_seq *seq)
3242 struct drm_i915_private *dev_priv = dev->dev_private;
3243 u32 pp_on, pp_off, pp_div, port_sel = 0;
3244 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3245 int pp_on_reg, pp_off_reg, pp_div_reg;
3247 if (HAS_PCH_SPLIT(dev)) {
3248 pp_on_reg = PCH_PP_ON_DELAYS;
3249 pp_off_reg = PCH_PP_OFF_DELAYS;
3250 pp_div_reg = PCH_PP_DIVISOR;
3252 pp_on_reg = PIPEA_PP_ON_DELAYS;
3253 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3254 pp_div_reg = PIPEA_PP_DIVISOR;
3257 /* And finally store the new values in the power sequencer. */
3258 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3259 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3260 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3261 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3262 /* Compute the divisor for the pp clock, simply match the Bspec
3264 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3265 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3266 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3268 /* Haswell doesn't have any port selection bits for the panel
3269 * power sequencer any more. */
3270 if (IS_VALLEYVIEW(dev)) {
3271 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
3272 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3273 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3274 port_sel = PANEL_POWER_PORT_DP_A;
3276 port_sel = PANEL_POWER_PORT_DP_D;
3281 I915_WRITE(pp_on_reg, pp_on);
3282 I915_WRITE(pp_off_reg, pp_off);
3283 I915_WRITE(pp_div_reg, pp_div);
3285 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3286 I915_READ(pp_on_reg),
3287 I915_READ(pp_off_reg),
3288 I915_READ(pp_div_reg));
3291 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3292 struct intel_connector *intel_connector)
3294 struct drm_connector *connector = &intel_connector->base;
3295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3296 struct drm_device *dev = intel_dig_port->base.base.dev;
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298 struct drm_display_mode *fixed_mode = NULL;
3299 struct edp_power_seq power_seq = { 0 };
3301 struct drm_display_mode *scan;
3304 if (!is_edp(intel_dp))
3307 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3309 /* Cache DPCD and EDID for edp. */
3310 ironlake_edp_panel_vdd_on(intel_dp);
3311 has_dpcd = intel_dp_get_dpcd(intel_dp);
3312 ironlake_edp_panel_vdd_off(intel_dp, false);
3315 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3316 dev_priv->no_aux_handshake =
3317 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3318 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3320 /* if this fails, presume the device is a ghost */
3321 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3325 /* We now know it's not a ghost, init power sequence regs. */
3326 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3329 ironlake_edp_panel_vdd_on(intel_dp);
3330 edid = drm_get_edid(connector, &intel_dp->adapter);
3332 if (drm_add_edid_modes(connector, edid)) {
3333 drm_mode_connector_update_edid_property(connector,
3335 drm_edid_to_eld(connector, edid);
3338 edid = ERR_PTR(-EINVAL);
3341 edid = ERR_PTR(-ENOENT);
3343 intel_connector->edid = edid;
3345 /* prefer fixed mode from EDID if available */
3346 list_for_each_entry(scan, &connector->probed_modes, head) {
3347 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3348 fixed_mode = drm_mode_duplicate(dev, scan);
3353 /* fallback to VBT if available for eDP */
3354 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3355 fixed_mode = drm_mode_duplicate(dev,
3356 dev_priv->vbt.lfp_lvds_vbt_mode);
3358 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3361 ironlake_edp_panel_vdd_off(intel_dp, false);
3363 intel_panel_init(&intel_connector->panel, fixed_mode);
3364 intel_panel_setup_backlight(connector);
3370 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3371 struct intel_connector *intel_connector)
3373 struct drm_connector *connector = &intel_connector->base;
3374 struct intel_dp *intel_dp = &intel_dig_port->dp;
3375 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3376 struct drm_device *dev = intel_encoder->base.dev;
3377 struct drm_i915_private *dev_priv = dev->dev_private;
3378 enum port port = intel_dig_port->port;
3379 const char *name = NULL;
3382 /* Preserve the current hw state. */
3383 intel_dp->DP = I915_READ(intel_dp->output_reg);
3384 intel_dp->attached_connector = intel_connector;
3386 type = DRM_MODE_CONNECTOR_DisplayPort;
3388 * FIXME : We need to initialize built-in panels before external panels.
3389 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3393 type = DRM_MODE_CONNECTOR_eDP;
3396 if (IS_VALLEYVIEW(dev))
3397 type = DRM_MODE_CONNECTOR_eDP;
3400 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3401 type = DRM_MODE_CONNECTOR_eDP;
3403 default: /* silence GCC warning */
3408 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3409 * for DP the encoder type can be set by the caller to
3410 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3412 if (type == DRM_MODE_CONNECTOR_eDP)
3413 intel_encoder->type = INTEL_OUTPUT_EDP;
3415 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3416 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3419 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3420 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3422 connector->interlace_allowed = true;
3423 connector->doublescan_allowed = 0;
3425 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3426 ironlake_panel_vdd_work);
3428 intel_connector_attach_encoder(intel_connector, intel_encoder);
3429 drm_sysfs_connector_add(connector);
3432 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3434 intel_connector->get_hw_state = intel_connector_get_hw_state;
3436 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3438 switch (intel_dig_port->port) {
3440 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3443 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3446 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3449 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3456 /* Set up the DDC bus. */
3459 intel_encoder->hpd_pin = HPD_PORT_A;
3463 intel_encoder->hpd_pin = HPD_PORT_B;
3467 intel_encoder->hpd_pin = HPD_PORT_C;
3471 intel_encoder->hpd_pin = HPD_PORT_D;
3478 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3479 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3480 error, port_name(port));
3482 intel_dp->psr_setup_done = false;
3484 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3485 i2c_del_adapter(&intel_dp->adapter);
3486 if (is_edp(intel_dp)) {
3487 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3488 mutex_lock(&dev->mode_config.mutex);
3489 ironlake_panel_vdd_off_sync(intel_dp);
3490 mutex_unlock(&dev->mode_config.mutex);
3492 drm_sysfs_connector_remove(connector);
3493 drm_connector_cleanup(connector);
3497 intel_dp_add_properties(intel_dp, connector);
3499 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3500 * 0xd. Failure to do so will result in spurious interrupts being
3501 * generated on the port when a cable is not attached.
3503 if (IS_G4X(dev) && !IS_GM45(dev)) {
3504 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3505 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3512 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3514 struct intel_digital_port *intel_dig_port;
3515 struct intel_encoder *intel_encoder;
3516 struct drm_encoder *encoder;
3517 struct intel_connector *intel_connector;
3519 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3520 if (!intel_dig_port)
3523 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3524 if (!intel_connector) {
3525 kfree(intel_dig_port);
3529 intel_encoder = &intel_dig_port->base;
3530 encoder = &intel_encoder->base;
3532 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3533 DRM_MODE_ENCODER_TMDS);
3535 intel_encoder->compute_config = intel_dp_compute_config;
3536 intel_encoder->mode_set = intel_dp_mode_set;
3537 intel_encoder->disable = intel_disable_dp;
3538 intel_encoder->post_disable = intel_post_disable_dp;
3539 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3540 intel_encoder->get_config = intel_dp_get_config;
3541 if (IS_VALLEYVIEW(dev)) {
3542 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3543 intel_encoder->pre_enable = vlv_pre_enable_dp;
3544 intel_encoder->enable = vlv_enable_dp;
3546 intel_encoder->pre_enable = intel_pre_enable_dp;
3547 intel_encoder->enable = intel_enable_dp;
3550 intel_dig_port->port = port;
3551 intel_dig_port->dp.output_reg = output_reg;
3553 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3554 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3555 intel_encoder->cloneable = false;
3556 intel_encoder->hot_plug = intel_dp_hot_plug;
3558 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3559 drm_encoder_cleanup(encoder);
3560 kfree(intel_dig_port);
3561 kfree(intel_connector);