2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_edid.h>
40 #include "intel_drv.h"
41 #include <drm/i915_drm.h>
44 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 /* Compliance test status bits */
47 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
48 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
50 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
57 static const struct dp_link_dpll gen4_dpll[] = {
59 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
61 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
64 static const struct dp_link_dpll pch_dpll[] = {
66 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
68 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
71 static const struct dp_link_dpll vlv_dpll[] = {
73 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
75 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
79 * CHV supports eDP 1.4 that have more link rates.
80 * Below only provides the fixed rate but exclude variable rate.
82 static const struct dp_link_dpll chv_dpll[] = {
84 * CHV requires to program fractional division for m2.
85 * m2 is stored in fixed point format using formula below
86 * (m2_int << 22) | m2_fraction
88 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
89 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
90 { 270000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
92 { 540000, /* m2_int = 27, m2_fraction = 0 */
93 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
96 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
97 324000, 432000, 540000 };
98 static const int skl_rates[] = { 162000, 216000, 270000,
99 324000, 432000, 540000 };
100 static const int default_rates[] = { 162000, 270000, 540000 };
103 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
104 * @intel_dp: DP struct
106 * If a CPU or PCH DP output is attached to an eDP panel, this function
107 * will return true, and false otherwise.
109 static bool is_edp(struct intel_dp *intel_dp)
111 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
113 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
116 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
118 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
120 return intel_dig_port->base.base.dev;
123 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
125 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
128 static void intel_dp_link_down(struct intel_dp *intel_dp);
129 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
130 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
131 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
132 static void vlv_steal_power_sequencer(struct drm_device *dev,
134 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
137 intel_dp_max_link_bw(struct intel_dp *intel_dp)
139 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
141 switch (max_link_bw) {
142 case DP_LINK_BW_1_62:
147 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
149 max_link_bw = DP_LINK_BW_1_62;
155 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
157 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
158 u8 source_max, sink_max;
160 source_max = intel_dig_port->max_lanes;
161 sink_max = intel_dp->max_sink_lane_count;
163 return min(source_max, sink_max);
167 intel_dp_link_required(int pixel_clock, int bpp)
169 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
170 return DIV_ROUND_UP(pixel_clock * bpp, 8);
174 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
176 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
177 * link rate that is generally expressed in Gbps. Since, 8 bits of data
178 * is transmitted every LS_Clk per lane, there is no need to account for
179 * the channel encoding that is done in the PHY layer here.
182 return max_link_clock * max_lanes;
186 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
188 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
189 struct intel_encoder *encoder = &intel_dig_port->base;
190 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
191 int max_dotclk = dev_priv->max_dotclk_freq;
194 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
196 if (type != DP_DS_PORT_TYPE_VGA)
199 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
200 intel_dp->downstream_ports);
202 if (ds_max_dotclk != 0)
203 max_dotclk = min(max_dotclk, ds_max_dotclk);
209 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
211 if (intel_dp->num_sink_rates) {
212 *sink_rates = intel_dp->sink_rates;
213 return intel_dp->num_sink_rates;
216 *sink_rates = default_rates;
218 return (intel_dp->max_sink_link_bw >> 3) + 1;
222 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
224 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
225 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
228 if (IS_GEN9_LP(dev_priv)) {
229 *source_rates = bxt_rates;
230 size = ARRAY_SIZE(bxt_rates);
231 } else if (IS_GEN9_BC(dev_priv)) {
232 *source_rates = skl_rates;
233 size = ARRAY_SIZE(skl_rates);
235 *source_rates = default_rates;
236 size = ARRAY_SIZE(default_rates);
239 /* This depends on the fact that 5.4 is last value in the array */
240 if (!intel_dp_source_supports_hbr2(intel_dp))
246 static int intersect_rates(const int *source_rates, int source_len,
247 const int *sink_rates, int sink_len,
250 int i = 0, j = 0, k = 0;
252 while (i < source_len && j < sink_len) {
253 if (source_rates[i] == sink_rates[j]) {
254 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
256 common_rates[k] = source_rates[i];
260 } else if (source_rates[i] < sink_rates[j]) {
269 static int intel_dp_common_rates(struct intel_dp *intel_dp,
272 const int *source_rates, *sink_rates;
273 int source_len, sink_len;
275 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
276 source_len = intel_dp_source_rates(intel_dp, &source_rates);
278 return intersect_rates(source_rates, source_len,
279 sink_rates, sink_len,
283 static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
284 int *common_rates, int link_rate)
289 common_len = intel_dp_common_rates(intel_dp, common_rates);
290 for (index = 0; index < common_len; index++) {
291 if (link_rate == common_rates[common_len - index - 1])
292 return common_len - index - 1;
298 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
299 int link_rate, uint8_t lane_count)
301 int common_rates[DP_MAX_SUPPORTED_RATES];
304 link_rate_index = intel_dp_link_rate_index(intel_dp,
307 if (link_rate_index > 0) {
308 intel_dp->max_sink_link_bw = drm_dp_link_rate_to_bw_code(common_rates[link_rate_index - 1]);
309 intel_dp->max_sink_lane_count = lane_count;
310 } else if (lane_count > 1) {
311 intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
312 intel_dp->max_sink_lane_count = lane_count >> 1;
314 DRM_ERROR("Link Training Unsuccessful\n");
321 static enum drm_mode_status
322 intel_dp_mode_valid(struct drm_connector *connector,
323 struct drm_display_mode *mode)
325 struct intel_dp *intel_dp = intel_attached_dp(connector);
326 struct intel_connector *intel_connector = to_intel_connector(connector);
327 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
328 int target_clock = mode->clock;
329 int max_rate, mode_rate, max_lanes, max_link_clock;
332 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
334 if (is_edp(intel_dp) && fixed_mode) {
335 if (mode->hdisplay > fixed_mode->hdisplay)
338 if (mode->vdisplay > fixed_mode->vdisplay)
341 target_clock = fixed_mode->clock;
344 max_link_clock = intel_dp_max_link_rate(intel_dp);
345 max_lanes = intel_dp_max_lane_count(intel_dp);
347 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
348 mode_rate = intel_dp_link_required(target_clock, 18);
350 if (mode_rate > max_rate || target_clock > max_dotclk)
351 return MODE_CLOCK_HIGH;
353 if (mode->clock < 10000)
354 return MODE_CLOCK_LOW;
356 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
357 return MODE_H_ILLEGAL;
362 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
369 for (i = 0; i < src_bytes; i++)
370 v |= ((uint32_t) src[i]) << ((3-i) * 8);
374 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
379 for (i = 0; i < dst_bytes; i++)
380 dst[i] = src >> ((3-i) * 8);
384 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
385 struct intel_dp *intel_dp);
387 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
388 struct intel_dp *intel_dp,
389 bool force_disable_vdd);
391 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
393 static void pps_lock(struct intel_dp *intel_dp)
395 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
396 struct intel_encoder *encoder = &intel_dig_port->base;
397 struct drm_device *dev = encoder->base.dev;
398 struct drm_i915_private *dev_priv = to_i915(dev);
401 * See vlv_power_sequencer_reset() why we need
402 * a power domain reference here.
404 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
406 mutex_lock(&dev_priv->pps_mutex);
409 static void pps_unlock(struct intel_dp *intel_dp)
411 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
412 struct intel_encoder *encoder = &intel_dig_port->base;
413 struct drm_device *dev = encoder->base.dev;
414 struct drm_i915_private *dev_priv = to_i915(dev);
416 mutex_unlock(&dev_priv->pps_mutex);
418 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
422 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
425 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
426 enum pipe pipe = intel_dp->pps_pipe;
427 bool pll_enabled, release_cl_override = false;
428 enum dpio_phy phy = DPIO_PHY(pipe);
429 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
432 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
433 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
434 pipe_name(pipe), port_name(intel_dig_port->port)))
437 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
438 pipe_name(pipe), port_name(intel_dig_port->port));
440 /* Preserve the BIOS-computed detected bit. This is
441 * supposed to be read-only.
443 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
444 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
445 DP |= DP_PORT_WIDTH(1);
446 DP |= DP_LINK_TRAIN_PAT_1;
448 if (IS_CHERRYVIEW(dev_priv))
449 DP |= DP_PIPE_SELECT_CHV(pipe);
450 else if (pipe == PIPE_B)
451 DP |= DP_PIPEB_SELECT;
453 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
456 * The DPLL for the pipe must be enabled for this to work.
457 * So enable temporarily it if it's not already enabled.
460 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
461 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
463 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
464 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
465 DRM_ERROR("Failed to force on pll for pipe %c!\n",
472 * Similar magic as in intel_dp_enable_port().
473 * We _must_ do this port enable + disable trick
474 * to make this power seqeuencer lock onto the port.
475 * Otherwise even VDD force bit won't work.
477 I915_WRITE(intel_dp->output_reg, DP);
478 POSTING_READ(intel_dp->output_reg);
480 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
481 POSTING_READ(intel_dp->output_reg);
483 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
484 POSTING_READ(intel_dp->output_reg);
487 vlv_force_pll_off(dev_priv, pipe);
489 if (release_cl_override)
490 chv_phy_powergate_ch(dev_priv, phy, ch, false);
494 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
496 struct intel_encoder *encoder;
497 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
500 * We don't have power sequencer currently.
501 * Pick one that's not used by other ports.
503 for_each_intel_encoder(&dev_priv->drm, encoder) {
504 struct intel_dp *intel_dp;
506 if (encoder->type != INTEL_OUTPUT_DP &&
507 encoder->type != INTEL_OUTPUT_EDP)
510 intel_dp = enc_to_intel_dp(&encoder->base);
512 if (encoder->type == INTEL_OUTPUT_EDP) {
513 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
514 intel_dp->active_pipe != intel_dp->pps_pipe);
516 if (intel_dp->pps_pipe != INVALID_PIPE)
517 pipes &= ~(1 << intel_dp->pps_pipe);
519 WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
521 if (intel_dp->active_pipe != INVALID_PIPE)
522 pipes &= ~(1 << intel_dp->active_pipe);
529 return ffs(pipes) - 1;
533 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
535 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
536 struct drm_device *dev = intel_dig_port->base.base.dev;
537 struct drm_i915_private *dev_priv = to_i915(dev);
540 lockdep_assert_held(&dev_priv->pps_mutex);
542 /* We should never land here with regular DP ports */
543 WARN_ON(!is_edp(intel_dp));
545 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
546 intel_dp->active_pipe != intel_dp->pps_pipe);
548 if (intel_dp->pps_pipe != INVALID_PIPE)
549 return intel_dp->pps_pipe;
551 pipe = vlv_find_free_pps(dev_priv);
554 * Didn't find one. This should not happen since there
555 * are two power sequencers and up to two eDP ports.
557 if (WARN_ON(pipe == INVALID_PIPE))
560 vlv_steal_power_sequencer(dev, pipe);
561 intel_dp->pps_pipe = pipe;
563 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
564 pipe_name(intel_dp->pps_pipe),
565 port_name(intel_dig_port->port));
567 /* init power sequencer on this pipe and port */
568 intel_dp_init_panel_power_sequencer(dev, intel_dp);
569 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
572 * Even vdd force doesn't work until we've made
573 * the power sequencer lock in on the port.
575 vlv_power_sequencer_kick(intel_dp);
577 return intel_dp->pps_pipe;
581 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
583 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
584 struct drm_device *dev = intel_dig_port->base.base.dev;
585 struct drm_i915_private *dev_priv = to_i915(dev);
587 lockdep_assert_held(&dev_priv->pps_mutex);
589 /* We should never land here with regular DP ports */
590 WARN_ON(!is_edp(intel_dp));
593 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
594 * mapping needs to be retrieved from VBT, for now just hard-code to
595 * use instance #0 always.
597 if (!intel_dp->pps_reset)
600 intel_dp->pps_reset = false;
603 * Only the HW needs to be reprogrammed, the SW state is fixed and
604 * has been setup during connector init.
606 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
611 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
614 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
617 return I915_READ(PP_STATUS(pipe)) & PP_ON;
620 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
623 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
626 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
633 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
635 vlv_pipe_check pipe_check)
639 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
640 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
641 PANEL_PORT_SELECT_MASK;
643 if (port_sel != PANEL_PORT_SELECT_VLV(port))
646 if (!pipe_check(dev_priv, pipe))
656 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
658 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
659 struct drm_device *dev = intel_dig_port->base.base.dev;
660 struct drm_i915_private *dev_priv = to_i915(dev);
661 enum port port = intel_dig_port->port;
663 lockdep_assert_held(&dev_priv->pps_mutex);
665 /* try to find a pipe with this port selected */
666 /* first pick one where the panel is on */
667 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
669 /* didn't find one? pick one where vdd is on */
670 if (intel_dp->pps_pipe == INVALID_PIPE)
671 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
672 vlv_pipe_has_vdd_on);
673 /* didn't find one? pick one with just the correct port */
674 if (intel_dp->pps_pipe == INVALID_PIPE)
675 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
678 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
679 if (intel_dp->pps_pipe == INVALID_PIPE) {
680 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
685 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
686 port_name(port), pipe_name(intel_dp->pps_pipe));
688 intel_dp_init_panel_power_sequencer(dev, intel_dp);
689 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
692 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
694 struct drm_device *dev = &dev_priv->drm;
695 struct intel_encoder *encoder;
697 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
698 !IS_GEN9_LP(dev_priv)))
702 * We can't grab pps_mutex here due to deadlock with power_domain
703 * mutex when power_domain functions are called while holding pps_mutex.
704 * That also means that in order to use pps_pipe the code needs to
705 * hold both a power domain reference and pps_mutex, and the power domain
706 * reference get/put must be done while _not_ holding pps_mutex.
707 * pps_{lock,unlock}() do these steps in the correct order, so one
708 * should use them always.
711 for_each_intel_encoder(dev, encoder) {
712 struct intel_dp *intel_dp;
714 if (encoder->type != INTEL_OUTPUT_DP &&
715 encoder->type != INTEL_OUTPUT_EDP)
718 intel_dp = enc_to_intel_dp(&encoder->base);
720 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
722 if (encoder->type != INTEL_OUTPUT_EDP)
725 if (IS_GEN9_LP(dev_priv))
726 intel_dp->pps_reset = true;
728 intel_dp->pps_pipe = INVALID_PIPE;
732 struct pps_registers {
740 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
741 struct intel_dp *intel_dp,
742 struct pps_registers *regs)
746 memset(regs, 0, sizeof(*regs));
748 if (IS_GEN9_LP(dev_priv))
749 pps_idx = bxt_power_sequencer_idx(intel_dp);
750 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
751 pps_idx = vlv_power_sequencer_pipe(intel_dp);
753 regs->pp_ctrl = PP_CONTROL(pps_idx);
754 regs->pp_stat = PP_STATUS(pps_idx);
755 regs->pp_on = PP_ON_DELAYS(pps_idx);
756 regs->pp_off = PP_OFF_DELAYS(pps_idx);
757 if (!IS_GEN9_LP(dev_priv))
758 regs->pp_div = PP_DIVISOR(pps_idx);
762 _pp_ctrl_reg(struct intel_dp *intel_dp)
764 struct pps_registers regs;
766 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
773 _pp_stat_reg(struct intel_dp *intel_dp)
775 struct pps_registers regs;
777 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
783 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
784 This function only applicable when panel PM state is not to be tracked */
785 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
788 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
790 struct drm_device *dev = intel_dp_to_dev(intel_dp);
791 struct drm_i915_private *dev_priv = to_i915(dev);
793 if (!is_edp(intel_dp) || code != SYS_RESTART)
798 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
799 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
800 i915_reg_t pp_ctrl_reg, pp_div_reg;
803 pp_ctrl_reg = PP_CONTROL(pipe);
804 pp_div_reg = PP_DIVISOR(pipe);
805 pp_div = I915_READ(pp_div_reg);
806 pp_div &= PP_REFERENCE_DIVIDER_MASK;
808 /* 0x1F write to PP_DIV_REG sets max cycle delay */
809 I915_WRITE(pp_div_reg, pp_div | 0x1F);
810 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
811 msleep(intel_dp->panel_power_cycle_delay);
814 pps_unlock(intel_dp);
819 static bool edp_have_panel_power(struct intel_dp *intel_dp)
821 struct drm_device *dev = intel_dp_to_dev(intel_dp);
822 struct drm_i915_private *dev_priv = to_i915(dev);
824 lockdep_assert_held(&dev_priv->pps_mutex);
826 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
827 intel_dp->pps_pipe == INVALID_PIPE)
830 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
833 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
835 struct drm_device *dev = intel_dp_to_dev(intel_dp);
836 struct drm_i915_private *dev_priv = to_i915(dev);
838 lockdep_assert_held(&dev_priv->pps_mutex);
840 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
841 intel_dp->pps_pipe == INVALID_PIPE)
844 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
848 intel_dp_check_edp(struct intel_dp *intel_dp)
850 struct drm_device *dev = intel_dp_to_dev(intel_dp);
851 struct drm_i915_private *dev_priv = to_i915(dev);
853 if (!is_edp(intel_dp))
856 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
857 WARN(1, "eDP powered off while attempting aux channel communication.\n");
858 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
859 I915_READ(_pp_stat_reg(intel_dp)),
860 I915_READ(_pp_ctrl_reg(intel_dp)));
865 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
867 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
868 struct drm_device *dev = intel_dig_port->base.base.dev;
869 struct drm_i915_private *dev_priv = to_i915(dev);
870 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
874 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
876 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
877 msecs_to_jiffies_timeout(10));
879 done = wait_for(C, 10) == 0;
881 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
888 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
890 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
891 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
897 * The clock divider is based off the hrawclk, and would like to run at
898 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
900 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
903 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
905 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
906 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
912 * The clock divider is based off the cdclk or PCH rawclk, and would
913 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
914 * divide by 2000 and use that
916 if (intel_dig_port->port == PORT_A)
917 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
919 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
922 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
924 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
925 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
927 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
928 /* Workaround for non-ULT HSW */
936 return ilk_get_aux_clock_divider(intel_dp, index);
939 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
942 * SKL doesn't need us to program the AUX clock divider (Hardware will
943 * derive the clock from CDCLK automatically). We still implement the
944 * get_aux_clock_divider vfunc to plug-in into the existing code.
946 return index ? 0 : 1;
949 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
952 uint32_t aux_clock_divider)
954 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
955 struct drm_i915_private *dev_priv =
956 to_i915(intel_dig_port->base.base.dev);
957 uint32_t precharge, timeout;
959 if (IS_GEN6(dev_priv))
964 if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
965 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
967 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
969 return DP_AUX_CH_CTL_SEND_BUSY |
971 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
972 DP_AUX_CH_CTL_TIME_OUT_ERROR |
974 DP_AUX_CH_CTL_RECEIVE_ERROR |
975 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
976 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
977 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
980 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
985 return DP_AUX_CH_CTL_SEND_BUSY |
987 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
988 DP_AUX_CH_CTL_TIME_OUT_ERROR |
989 DP_AUX_CH_CTL_TIME_OUT_1600us |
990 DP_AUX_CH_CTL_RECEIVE_ERROR |
991 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
992 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
993 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
997 intel_dp_aux_ch(struct intel_dp *intel_dp,
998 const uint8_t *send, int send_bytes,
999 uint8_t *recv, int recv_size)
1001 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1002 struct drm_i915_private *dev_priv =
1003 to_i915(intel_dig_port->base.base.dev);
1004 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1005 uint32_t aux_clock_divider;
1006 int i, ret, recv_bytes;
1009 bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1015 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1016 * In such cases we want to leave VDD enabled and it's up to upper layers
1017 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1020 vdd = edp_panel_vdd_on(intel_dp);
1022 /* dp aux is extremely sensitive to irq latency, hence request the
1023 * lowest possible wakeup latency and so prevent the cpu from going into
1024 * deep sleep states.
1026 pm_qos_update_request(&dev_priv->pm_qos, 0);
1028 intel_dp_check_edp(intel_dp);
1030 /* Try to wait for any previous AUX channel activity */
1031 for (try = 0; try < 3; try++) {
1032 status = I915_READ_NOTRACE(ch_ctl);
1033 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1039 static u32 last_status = -1;
1040 const u32 status = I915_READ(ch_ctl);
1042 if (status != last_status) {
1043 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1045 last_status = status;
1052 /* Only 5 data registers! */
1053 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1058 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1059 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1064 /* Must try at least 3 times according to DP spec */
1065 for (try = 0; try < 5; try++) {
1066 /* Load the send data into the aux channel data registers */
1067 for (i = 0; i < send_bytes; i += 4)
1068 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1069 intel_dp_pack_aux(send + i,
1072 /* Send the command and wait for it to complete */
1073 I915_WRITE(ch_ctl, send_ctl);
1075 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1077 /* Clear done status and any errors */
1080 DP_AUX_CH_CTL_DONE |
1081 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1082 DP_AUX_CH_CTL_RECEIVE_ERROR);
1084 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1087 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1088 * 400us delay required for errors and timeouts
1089 * Timeout errors from the HW already meet this
1090 * requirement so skip to next iteration
1092 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1093 usleep_range(400, 500);
1096 if (status & DP_AUX_CH_CTL_DONE)
1101 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1102 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1108 /* Check for timeout or receive error.
1109 * Timeouts occur when the sink is not connected
1111 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1112 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1117 /* Timeouts occur when the device isn't connected, so they're
1118 * "normal" -- don't fill the kernel log with these */
1119 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1120 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1125 /* Unload any bytes sent back from the other side */
1126 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1127 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1130 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1131 * We have no idea of what happened so we return -EBUSY so
1132 * drm layer takes care for the necessary retries.
1134 if (recv_bytes == 0 || recv_bytes > 20) {
1135 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1138 * FIXME: This patch was created on top of a series that
1139 * organize the retries at drm level. There EBUSY should
1140 * also take care for 1ms wait before retrying.
1141 * That aux retries re-org is still needed and after that is
1142 * merged we remove this sleep from here.
1144 usleep_range(1000, 1500);
1149 if (recv_bytes > recv_size)
1150 recv_bytes = recv_size;
1152 for (i = 0; i < recv_bytes; i += 4)
1153 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1154 recv + i, recv_bytes - i);
1158 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1161 edp_panel_vdd_off(intel_dp, false);
1163 pps_unlock(intel_dp);
1168 #define BARE_ADDRESS_SIZE 3
1169 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1171 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1173 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1174 uint8_t txbuf[20], rxbuf[20];
1175 size_t txsize, rxsize;
1178 txbuf[0] = (msg->request << 4) |
1179 ((msg->address >> 16) & 0xf);
1180 txbuf[1] = (msg->address >> 8) & 0xff;
1181 txbuf[2] = msg->address & 0xff;
1182 txbuf[3] = msg->size - 1;
1184 switch (msg->request & ~DP_AUX_I2C_MOT) {
1185 case DP_AUX_NATIVE_WRITE:
1186 case DP_AUX_I2C_WRITE:
1187 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1188 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1189 rxsize = 2; /* 0 or 1 data bytes */
1191 if (WARN_ON(txsize > 20))
1194 WARN_ON(!msg->buffer != !msg->size);
1197 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1199 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1201 msg->reply = rxbuf[0] >> 4;
1204 /* Number of bytes written in a short write. */
1205 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1207 /* Return payload size. */
1213 case DP_AUX_NATIVE_READ:
1214 case DP_AUX_I2C_READ:
1215 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1216 rxsize = msg->size + 1;
1218 if (WARN_ON(rxsize > 20))
1221 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1223 msg->reply = rxbuf[0] >> 4;
1225 * Assume happy day, and copy the data. The caller is
1226 * expected to check msg->reply before touching it.
1228 * Return payload size.
1231 memcpy(msg->buffer, rxbuf + 1, ret);
1243 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1246 const struct ddi_vbt_port_info *info =
1247 &dev_priv->vbt.ddi_port_info[port];
1250 if (!info->alternate_aux_channel) {
1251 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1252 port_name(port), port_name(port));
1256 switch (info->alternate_aux_channel) {
1270 MISSING_CASE(info->alternate_aux_channel);
1275 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1276 port_name(aux_port), port_name(port));
1281 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1288 return DP_AUX_CH_CTL(port);
1291 return DP_AUX_CH_CTL(PORT_B);
1295 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1296 enum port port, int index)
1302 return DP_AUX_CH_DATA(port, index);
1305 return DP_AUX_CH_DATA(PORT_B, index);
1309 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1314 return DP_AUX_CH_CTL(port);
1318 return PCH_DP_AUX_CH_CTL(port);
1321 return DP_AUX_CH_CTL(PORT_A);
1325 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1326 enum port port, int index)
1330 return DP_AUX_CH_DATA(port, index);
1334 return PCH_DP_AUX_CH_DATA(port, index);
1337 return DP_AUX_CH_DATA(PORT_A, index);
1341 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1349 return DP_AUX_CH_CTL(port);
1352 return DP_AUX_CH_CTL(PORT_A);
1356 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1357 enum port port, int index)
1364 return DP_AUX_CH_DATA(port, index);
1367 return DP_AUX_CH_DATA(PORT_A, index);
1371 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1374 if (INTEL_INFO(dev_priv)->gen >= 9)
1375 return skl_aux_ctl_reg(dev_priv, port);
1376 else if (HAS_PCH_SPLIT(dev_priv))
1377 return ilk_aux_ctl_reg(dev_priv, port);
1379 return g4x_aux_ctl_reg(dev_priv, port);
1382 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1383 enum port port, int index)
1385 if (INTEL_INFO(dev_priv)->gen >= 9)
1386 return skl_aux_data_reg(dev_priv, port, index);
1387 else if (HAS_PCH_SPLIT(dev_priv))
1388 return ilk_aux_data_reg(dev_priv, port, index);
1390 return g4x_aux_data_reg(dev_priv, port, index);
1393 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1395 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1396 enum port port = intel_aux_port(dev_priv,
1397 dp_to_dig_port(intel_dp)->port);
1400 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1401 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1402 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1406 intel_dp_aux_fini(struct intel_dp *intel_dp)
1408 kfree(intel_dp->aux.name);
1412 intel_dp_aux_init(struct intel_dp *intel_dp)
1414 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1415 enum port port = intel_dig_port->port;
1417 intel_aux_reg_init(intel_dp);
1418 drm_dp_aux_init(&intel_dp->aux);
1420 /* Failure to allocate our preferred name is not critical */
1421 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1422 intel_dp->aux.transfer = intel_dp_aux_transfer;
1425 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1427 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1428 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1430 if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1431 IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
1438 intel_dp_set_clock(struct intel_encoder *encoder,
1439 struct intel_crtc_state *pipe_config)
1441 struct drm_device *dev = encoder->base.dev;
1442 struct drm_i915_private *dev_priv = to_i915(dev);
1443 const struct dp_link_dpll *divisor = NULL;
1446 if (IS_G4X(dev_priv)) {
1447 divisor = gen4_dpll;
1448 count = ARRAY_SIZE(gen4_dpll);
1449 } else if (HAS_PCH_SPLIT(dev_priv)) {
1451 count = ARRAY_SIZE(pch_dpll);
1452 } else if (IS_CHERRYVIEW(dev_priv)) {
1454 count = ARRAY_SIZE(chv_dpll);
1455 } else if (IS_VALLEYVIEW(dev_priv)) {
1457 count = ARRAY_SIZE(vlv_dpll);
1460 if (divisor && count) {
1461 for (i = 0; i < count; i++) {
1462 if (pipe_config->port_clock == divisor[i].clock) {
1463 pipe_config->dpll = divisor[i].dpll;
1464 pipe_config->clock_set = true;
1471 static void snprintf_int_array(char *str, size_t len,
1472 const int *array, int nelem)
1478 for (i = 0; i < nelem; i++) {
1479 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1487 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1489 const int *source_rates, *sink_rates;
1490 int source_len, sink_len, common_len;
1491 int common_rates[DP_MAX_SUPPORTED_RATES];
1492 char str[128]; /* FIXME: too big for stack? */
1494 if ((drm_debug & DRM_UT_KMS) == 0)
1497 source_len = intel_dp_source_rates(intel_dp, &source_rates);
1498 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1499 DRM_DEBUG_KMS("source rates: %s\n", str);
1501 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1502 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1503 DRM_DEBUG_KMS("sink rates: %s\n", str);
1505 common_len = intel_dp_common_rates(intel_dp, common_rates);
1506 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1507 DRM_DEBUG_KMS("common rates: %s\n", str);
1510 static int rate_to_index(int find, const int *rates)
1514 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1515 if (find == rates[i])
1522 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1524 int rates[DP_MAX_SUPPORTED_RATES] = {};
1527 len = intel_dp_common_rates(intel_dp, rates);
1528 if (WARN_ON(len <= 0))
1531 return rates[len - 1];
1534 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1536 return rate_to_index(rate, intel_dp->sink_rates);
1539 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1540 uint8_t *link_bw, uint8_t *rate_select)
1542 if (intel_dp->num_sink_rates) {
1545 intel_dp_rate_select(intel_dp, port_clock);
1547 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1552 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1553 struct intel_crtc_state *pipe_config)
1557 bpp = pipe_config->pipe_bpp;
1558 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1561 bpp = min(bpp, 3*bpc);
1563 /* For DP Compliance we override the computed bpp for the pipe */
1564 if (intel_dp->compliance.test_data.bpc != 0) {
1565 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
1566 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
1567 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1568 pipe_config->pipe_bpp);
1574 intel_dp_compute_config(struct intel_encoder *encoder,
1575 struct intel_crtc_state *pipe_config,
1576 struct drm_connector_state *conn_state)
1578 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1579 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1580 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1581 enum port port = dp_to_dig_port(intel_dp)->port;
1582 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1583 struct intel_connector *intel_connector = intel_dp->attached_connector;
1584 int lane_count, clock;
1585 int min_lane_count = 1;
1586 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1587 /* Conveniently, the link BW constants become indices with a shift...*/
1590 int link_rate_index;
1592 int link_avail, link_clock;
1593 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1595 uint8_t link_bw, rate_select;
1596 bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1597 DP_DPCD_QUIRK_LIMITED_M_N);
1599 common_len = intel_dp_common_rates(intel_dp, common_rates);
1601 /* No common link rates between source and sink */
1602 WARN_ON(common_len <= 0);
1604 max_clock = common_len - 1;
1606 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1607 pipe_config->has_pch_encoder = true;
1609 pipe_config->has_drrs = false;
1610 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1612 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1613 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1616 if (INTEL_GEN(dev_priv) >= 9) {
1618 ret = skl_update_scaler_crtc(pipe_config);
1623 if (HAS_GMCH_DISPLAY(dev_priv))
1624 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1625 intel_connector->panel.fitting_mode);
1627 intel_pch_panel_fitting(intel_crtc, pipe_config,
1628 intel_connector->panel.fitting_mode);
1631 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1634 /* Use values requested by Compliance Test Request */
1635 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1636 link_rate_index = intel_dp_link_rate_index(intel_dp,
1638 intel_dp->compliance.test_link_rate);
1639 if (link_rate_index >= 0)
1640 min_clock = max_clock = link_rate_index;
1641 min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
1643 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1644 "max bw %d pixel clock %iKHz\n",
1645 max_lane_count, common_rates[max_clock],
1646 adjusted_mode->crtc_clock);
1648 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1649 * bpc in between. */
1650 bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1651 if (is_edp(intel_dp)) {
1653 /* Get bpp from vbt only for panels that dont have bpp in edid */
1654 if (intel_connector->base.display_info.bpc == 0 &&
1655 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1656 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1657 dev_priv->vbt.edp.bpp);
1658 bpp = dev_priv->vbt.edp.bpp;
1662 * Use the maximum clock and number of lanes the eDP panel
1663 * advertizes being capable of. The panels are generally
1664 * designed to support only a single clock and lane
1665 * configuration, and typically these values correspond to the
1666 * native resolution of the panel.
1668 min_lane_count = max_lane_count;
1669 min_clock = max_clock;
1672 for (; bpp >= 6*3; bpp -= 2*3) {
1673 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1676 for (clock = min_clock; clock <= max_clock; clock++) {
1677 for (lane_count = min_lane_count;
1678 lane_count <= max_lane_count;
1681 link_clock = common_rates[clock];
1682 link_avail = intel_dp_max_data_rate(link_clock,
1685 if (mode_rate <= link_avail) {
1695 if (intel_dp->color_range_auto) {
1698 * CEA-861-E - 5.1 Default Encoding Parameters
1699 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1701 pipe_config->limited_color_range =
1703 drm_default_rgb_quant_range(adjusted_mode) ==
1704 HDMI_QUANTIZATION_RANGE_LIMITED;
1706 pipe_config->limited_color_range =
1707 intel_dp->limited_color_range;
1710 pipe_config->lane_count = lane_count;
1712 pipe_config->pipe_bpp = bpp;
1713 pipe_config->port_clock = common_rates[clock];
1715 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1716 &link_bw, &rate_select);
1718 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1719 link_bw, rate_select, pipe_config->lane_count,
1720 pipe_config->port_clock, bpp);
1721 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1722 mode_rate, link_avail);
1724 intel_link_compute_m_n(bpp, lane_count,
1725 adjusted_mode->crtc_clock,
1726 pipe_config->port_clock,
1727 &pipe_config->dp_m_n,
1730 if (intel_connector->panel.downclock_mode != NULL &&
1731 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1732 pipe_config->has_drrs = true;
1733 intel_link_compute_m_n(bpp, lane_count,
1734 intel_connector->panel.downclock_mode->clock,
1735 pipe_config->port_clock,
1736 &pipe_config->dp_m2_n2,
1741 * DPLL0 VCO may need to be adjusted to get the correct
1742 * clock for eDP. This will affect cdclk as well.
1744 if (is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1747 switch (pipe_config->port_clock / 2) {
1757 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1760 if (!HAS_DDI(dev_priv))
1761 intel_dp_set_clock(encoder, pipe_config);
1766 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1767 int link_rate, uint8_t lane_count,
1770 intel_dp->link_rate = link_rate;
1771 intel_dp->lane_count = lane_count;
1772 intel_dp->link_mst = link_mst;
1775 static void intel_dp_prepare(struct intel_encoder *encoder,
1776 struct intel_crtc_state *pipe_config)
1778 struct drm_device *dev = encoder->base.dev;
1779 struct drm_i915_private *dev_priv = to_i915(dev);
1780 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1781 enum port port = dp_to_dig_port(intel_dp)->port;
1782 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1783 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1785 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1786 pipe_config->lane_count,
1787 intel_crtc_has_type(pipe_config,
1788 INTEL_OUTPUT_DP_MST));
1791 * There are four kinds of DP registers:
1798 * IBX PCH and CPU are the same for almost everything,
1799 * except that the CPU DP PLL is configured in this
1802 * CPT PCH is quite different, having many bits moved
1803 * to the TRANS_DP_CTL register instead. That
1804 * configuration happens (oddly) in ironlake_pch_enable
1807 /* Preserve the BIOS-computed detected bit. This is
1808 * supposed to be read-only.
1810 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1812 /* Handle DP bits in common between all three register formats */
1813 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1814 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1816 /* Split out the IBX/CPU vs CPT settings */
1818 if (IS_GEN7(dev_priv) && port == PORT_A) {
1819 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1820 intel_dp->DP |= DP_SYNC_HS_HIGH;
1821 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1822 intel_dp->DP |= DP_SYNC_VS_HIGH;
1823 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1825 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1826 intel_dp->DP |= DP_ENHANCED_FRAMING;
1828 intel_dp->DP |= crtc->pipe << 29;
1829 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1832 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1834 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1835 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1836 trans_dp |= TRANS_DP_ENH_FRAMING;
1838 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1839 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1841 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1842 intel_dp->DP |= DP_COLOR_RANGE_16_235;
1844 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1845 intel_dp->DP |= DP_SYNC_HS_HIGH;
1846 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1847 intel_dp->DP |= DP_SYNC_VS_HIGH;
1848 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1850 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1851 intel_dp->DP |= DP_ENHANCED_FRAMING;
1853 if (IS_CHERRYVIEW(dev_priv))
1854 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1855 else if (crtc->pipe == PIPE_B)
1856 intel_dp->DP |= DP_PIPEB_SELECT;
1860 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1861 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1863 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1864 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1866 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1867 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1869 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1870 struct intel_dp *intel_dp);
1872 static void wait_panel_status(struct intel_dp *intel_dp,
1876 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1877 struct drm_i915_private *dev_priv = to_i915(dev);
1878 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1880 lockdep_assert_held(&dev_priv->pps_mutex);
1882 intel_pps_verify_state(dev_priv, intel_dp);
1884 pp_stat_reg = _pp_stat_reg(intel_dp);
1885 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1887 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1889 I915_READ(pp_stat_reg),
1890 I915_READ(pp_ctrl_reg));
1892 if (intel_wait_for_register(dev_priv,
1893 pp_stat_reg, mask, value,
1895 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1896 I915_READ(pp_stat_reg),
1897 I915_READ(pp_ctrl_reg));
1899 DRM_DEBUG_KMS("Wait complete\n");
1902 static void wait_panel_on(struct intel_dp *intel_dp)
1904 DRM_DEBUG_KMS("Wait for panel power on\n");
1905 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1908 static void wait_panel_off(struct intel_dp *intel_dp)
1910 DRM_DEBUG_KMS("Wait for panel power off time\n");
1911 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1914 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1916 ktime_t panel_power_on_time;
1917 s64 panel_power_off_duration;
1919 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1921 /* take the difference of currrent time and panel power off time
1922 * and then make panel wait for t11_t12 if needed. */
1923 panel_power_on_time = ktime_get_boottime();
1924 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1926 /* When we disable the VDD override bit last we have to do the manual
1928 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1929 wait_remaining_ms_from_jiffies(jiffies,
1930 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1932 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1935 static void wait_backlight_on(struct intel_dp *intel_dp)
1937 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1938 intel_dp->backlight_on_delay);
1941 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1943 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1944 intel_dp->backlight_off_delay);
1947 /* Read the current pp_control value, unlocking the register if it
1951 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1953 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1954 struct drm_i915_private *dev_priv = to_i915(dev);
1957 lockdep_assert_held(&dev_priv->pps_mutex);
1959 control = I915_READ(_pp_ctrl_reg(intel_dp));
1960 if (WARN_ON(!HAS_DDI(dev_priv) &&
1961 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
1962 control &= ~PANEL_UNLOCK_MASK;
1963 control |= PANEL_UNLOCK_REGS;
1969 * Must be paired with edp_panel_vdd_off().
1970 * Must hold pps_mutex around the whole on/off sequence.
1971 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1973 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1975 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1976 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1977 struct drm_i915_private *dev_priv = to_i915(dev);
1979 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1980 bool need_to_disable = !intel_dp->want_panel_vdd;
1982 lockdep_assert_held(&dev_priv->pps_mutex);
1984 if (!is_edp(intel_dp))
1987 cancel_delayed_work(&intel_dp->panel_vdd_work);
1988 intel_dp->want_panel_vdd = true;
1990 if (edp_have_panel_vdd(intel_dp))
1991 return need_to_disable;
1993 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
1995 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1996 port_name(intel_dig_port->port));
1998 if (!edp_have_panel_power(intel_dp))
1999 wait_panel_power_cycle(intel_dp);
2001 pp = ironlake_get_pp_control(intel_dp);
2002 pp |= EDP_FORCE_VDD;
2004 pp_stat_reg = _pp_stat_reg(intel_dp);
2005 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2007 I915_WRITE(pp_ctrl_reg, pp);
2008 POSTING_READ(pp_ctrl_reg);
2009 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2010 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2012 * If the panel wasn't on, delay before accessing aux channel
2014 if (!edp_have_panel_power(intel_dp)) {
2015 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2016 port_name(intel_dig_port->port));
2017 msleep(intel_dp->panel_power_up_delay);
2020 return need_to_disable;
2024 * Must be paired with intel_edp_panel_vdd_off() or
2025 * intel_edp_panel_off().
2026 * Nested calls to these functions are not allowed since
2027 * we drop the lock. Caller must use some higher level
2028 * locking to prevent nested calls from other threads.
2030 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2034 if (!is_edp(intel_dp))
2038 vdd = edp_panel_vdd_on(intel_dp);
2039 pps_unlock(intel_dp);
2041 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2042 port_name(dp_to_dig_port(intel_dp)->port));
2045 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2047 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2048 struct drm_i915_private *dev_priv = to_i915(dev);
2049 struct intel_digital_port *intel_dig_port =
2050 dp_to_dig_port(intel_dp);
2052 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2054 lockdep_assert_held(&dev_priv->pps_mutex);
2056 WARN_ON(intel_dp->want_panel_vdd);
2058 if (!edp_have_panel_vdd(intel_dp))
2061 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2062 port_name(intel_dig_port->port));
2064 pp = ironlake_get_pp_control(intel_dp);
2065 pp &= ~EDP_FORCE_VDD;
2067 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2068 pp_stat_reg = _pp_stat_reg(intel_dp);
2070 I915_WRITE(pp_ctrl_reg, pp);
2071 POSTING_READ(pp_ctrl_reg);
2073 /* Make sure sequencer is idle before allowing subsequent activity */
2074 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2075 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2077 if ((pp & PANEL_POWER_ON) == 0)
2078 intel_dp->panel_power_off_time = ktime_get_boottime();
2080 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2083 static void edp_panel_vdd_work(struct work_struct *__work)
2085 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2086 struct intel_dp, panel_vdd_work);
2089 if (!intel_dp->want_panel_vdd)
2090 edp_panel_vdd_off_sync(intel_dp);
2091 pps_unlock(intel_dp);
2094 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2096 unsigned long delay;
2099 * Queue the timer to fire a long time from now (relative to the power
2100 * down delay) to keep the panel power up across a sequence of
2103 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2104 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2108 * Must be paired with edp_panel_vdd_on().
2109 * Must hold pps_mutex around the whole on/off sequence.
2110 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2112 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2114 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2116 lockdep_assert_held(&dev_priv->pps_mutex);
2118 if (!is_edp(intel_dp))
2121 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2122 port_name(dp_to_dig_port(intel_dp)->port));
2124 intel_dp->want_panel_vdd = false;
2127 edp_panel_vdd_off_sync(intel_dp);
2129 edp_panel_vdd_schedule_off(intel_dp);
2132 static void edp_panel_on(struct intel_dp *intel_dp)
2134 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2135 struct drm_i915_private *dev_priv = to_i915(dev);
2137 i915_reg_t pp_ctrl_reg;
2139 lockdep_assert_held(&dev_priv->pps_mutex);
2141 if (!is_edp(intel_dp))
2144 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2145 port_name(dp_to_dig_port(intel_dp)->port));
2147 if (WARN(edp_have_panel_power(intel_dp),
2148 "eDP port %c panel power already on\n",
2149 port_name(dp_to_dig_port(intel_dp)->port)))
2152 wait_panel_power_cycle(intel_dp);
2154 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2155 pp = ironlake_get_pp_control(intel_dp);
2156 if (IS_GEN5(dev_priv)) {
2157 /* ILK workaround: disable reset around power sequence */
2158 pp &= ~PANEL_POWER_RESET;
2159 I915_WRITE(pp_ctrl_reg, pp);
2160 POSTING_READ(pp_ctrl_reg);
2163 pp |= PANEL_POWER_ON;
2164 if (!IS_GEN5(dev_priv))
2165 pp |= PANEL_POWER_RESET;
2167 I915_WRITE(pp_ctrl_reg, pp);
2168 POSTING_READ(pp_ctrl_reg);
2170 wait_panel_on(intel_dp);
2171 intel_dp->last_power_on = jiffies;
2173 if (IS_GEN5(dev_priv)) {
2174 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2175 I915_WRITE(pp_ctrl_reg, pp);
2176 POSTING_READ(pp_ctrl_reg);
2180 void intel_edp_panel_on(struct intel_dp *intel_dp)
2182 if (!is_edp(intel_dp))
2186 edp_panel_on(intel_dp);
2187 pps_unlock(intel_dp);
2191 static void edp_panel_off(struct intel_dp *intel_dp)
2193 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2194 struct drm_i915_private *dev_priv = to_i915(dev);
2196 i915_reg_t pp_ctrl_reg;
2198 lockdep_assert_held(&dev_priv->pps_mutex);
2200 if (!is_edp(intel_dp))
2203 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2204 port_name(dp_to_dig_port(intel_dp)->port));
2206 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2207 port_name(dp_to_dig_port(intel_dp)->port));
2209 pp = ironlake_get_pp_control(intel_dp);
2210 /* We need to switch off panel power _and_ force vdd, for otherwise some
2211 * panels get very unhappy and cease to work. */
2212 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2215 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2217 intel_dp->want_panel_vdd = false;
2219 I915_WRITE(pp_ctrl_reg, pp);
2220 POSTING_READ(pp_ctrl_reg);
2222 intel_dp->panel_power_off_time = ktime_get_boottime();
2223 wait_panel_off(intel_dp);
2225 /* We got a reference when we enabled the VDD. */
2226 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2229 void intel_edp_panel_off(struct intel_dp *intel_dp)
2231 if (!is_edp(intel_dp))
2235 edp_panel_off(intel_dp);
2236 pps_unlock(intel_dp);
2239 /* Enable backlight in the panel power control. */
2240 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2242 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2243 struct drm_device *dev = intel_dig_port->base.base.dev;
2244 struct drm_i915_private *dev_priv = to_i915(dev);
2246 i915_reg_t pp_ctrl_reg;
2249 * If we enable the backlight right away following a panel power
2250 * on, we may see slight flicker as the panel syncs with the eDP
2251 * link. So delay a bit to make sure the image is solid before
2252 * allowing it to appear.
2254 wait_backlight_on(intel_dp);
2258 pp = ironlake_get_pp_control(intel_dp);
2259 pp |= EDP_BLC_ENABLE;
2261 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2263 I915_WRITE(pp_ctrl_reg, pp);
2264 POSTING_READ(pp_ctrl_reg);
2266 pps_unlock(intel_dp);
2269 /* Enable backlight PWM and backlight PP control. */
2270 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2272 if (!is_edp(intel_dp))
2275 DRM_DEBUG_KMS("\n");
2277 intel_panel_enable_backlight(intel_dp->attached_connector);
2278 _intel_edp_backlight_on(intel_dp);
2281 /* Disable backlight in the panel power control. */
2282 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2284 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2285 struct drm_i915_private *dev_priv = to_i915(dev);
2287 i915_reg_t pp_ctrl_reg;
2289 if (!is_edp(intel_dp))
2294 pp = ironlake_get_pp_control(intel_dp);
2295 pp &= ~EDP_BLC_ENABLE;
2297 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2299 I915_WRITE(pp_ctrl_reg, pp);
2300 POSTING_READ(pp_ctrl_reg);
2302 pps_unlock(intel_dp);
2304 intel_dp->last_backlight_off = jiffies;
2305 edp_wait_backlight_off(intel_dp);
2308 /* Disable backlight PP control and backlight PWM. */
2309 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2311 if (!is_edp(intel_dp))
2314 DRM_DEBUG_KMS("\n");
2316 _intel_edp_backlight_off(intel_dp);
2317 intel_panel_disable_backlight(intel_dp->attached_connector);
2321 * Hook for controlling the panel power control backlight through the bl_power
2322 * sysfs attribute. Take care to handle multiple calls.
2324 static void intel_edp_backlight_power(struct intel_connector *connector,
2327 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2331 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2332 pps_unlock(intel_dp);
2334 if (is_enabled == enable)
2337 DRM_DEBUG_KMS("panel power control backlight %s\n",
2338 enable ? "enable" : "disable");
2341 _intel_edp_backlight_on(intel_dp);
2343 _intel_edp_backlight_off(intel_dp);
2346 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2348 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2349 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2350 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2352 I915_STATE_WARN(cur_state != state,
2353 "DP port %c state assertion failure (expected %s, current %s)\n",
2354 port_name(dig_port->port),
2355 onoff(state), onoff(cur_state));
2357 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2359 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2361 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2363 I915_STATE_WARN(cur_state != state,
2364 "eDP PLL state assertion failure (expected %s, current %s)\n",
2365 onoff(state), onoff(cur_state));
2367 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2368 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2370 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2371 struct intel_crtc_state *pipe_config)
2373 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2374 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2376 assert_pipe_disabled(dev_priv, crtc->pipe);
2377 assert_dp_port_disabled(intel_dp);
2378 assert_edp_pll_disabled(dev_priv);
2380 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2381 pipe_config->port_clock);
2383 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2385 if (pipe_config->port_clock == 162000)
2386 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2388 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2390 I915_WRITE(DP_A, intel_dp->DP);
2395 * [DevILK] Work around required when enabling DP PLL
2396 * while a pipe is enabled going to FDI:
2397 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2398 * 2. Program DP PLL enable
2400 if (IS_GEN5(dev_priv))
2401 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2403 intel_dp->DP |= DP_PLL_ENABLE;
2405 I915_WRITE(DP_A, intel_dp->DP);
2410 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2412 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2413 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2414 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2416 assert_pipe_disabled(dev_priv, crtc->pipe);
2417 assert_dp_port_disabled(intel_dp);
2418 assert_edp_pll_enabled(dev_priv);
2420 DRM_DEBUG_KMS("disabling eDP PLL\n");
2422 intel_dp->DP &= ~DP_PLL_ENABLE;
2424 I915_WRITE(DP_A, intel_dp->DP);
2429 /* If the sink supports it, try to set the power state appropriately */
2430 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2434 /* Should have a valid DPCD by this point */
2435 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2438 if (mode != DRM_MODE_DPMS_ON) {
2439 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2442 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2445 * When turning on, we need to retry for 1ms to give the sink
2448 for (i = 0; i < 3; i++) {
2449 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2456 if (ret == 1 && lspcon->active)
2457 lspcon_wait_pcon_mode(lspcon);
2461 DRM_DEBUG_KMS("failed to %s sink power state\n",
2462 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2465 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2468 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2469 enum port port = dp_to_dig_port(intel_dp)->port;
2470 struct drm_device *dev = encoder->base.dev;
2471 struct drm_i915_private *dev_priv = to_i915(dev);
2475 if (!intel_display_power_get_if_enabled(dev_priv,
2476 encoder->power_domain))
2481 tmp = I915_READ(intel_dp->output_reg);
2483 if (!(tmp & DP_PORT_EN))
2486 if (IS_GEN7(dev_priv) && port == PORT_A) {
2487 *pipe = PORT_TO_PIPE_CPT(tmp);
2488 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2491 for_each_pipe(dev_priv, p) {
2492 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2493 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2501 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2502 i915_mmio_reg_offset(intel_dp->output_reg));
2503 } else if (IS_CHERRYVIEW(dev_priv)) {
2504 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2506 *pipe = PORT_TO_PIPE(tmp);
2512 intel_display_power_put(dev_priv, encoder->power_domain);
2517 static void intel_dp_get_config(struct intel_encoder *encoder,
2518 struct intel_crtc_state *pipe_config)
2520 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2522 struct drm_device *dev = encoder->base.dev;
2523 struct drm_i915_private *dev_priv = to_i915(dev);
2524 enum port port = dp_to_dig_port(intel_dp)->port;
2525 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2527 tmp = I915_READ(intel_dp->output_reg);
2529 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2531 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2532 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2534 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2535 flags |= DRM_MODE_FLAG_PHSYNC;
2537 flags |= DRM_MODE_FLAG_NHSYNC;
2539 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2540 flags |= DRM_MODE_FLAG_PVSYNC;
2542 flags |= DRM_MODE_FLAG_NVSYNC;
2544 if (tmp & DP_SYNC_HS_HIGH)
2545 flags |= DRM_MODE_FLAG_PHSYNC;
2547 flags |= DRM_MODE_FLAG_NHSYNC;
2549 if (tmp & DP_SYNC_VS_HIGH)
2550 flags |= DRM_MODE_FLAG_PVSYNC;
2552 flags |= DRM_MODE_FLAG_NVSYNC;
2555 pipe_config->base.adjusted_mode.flags |= flags;
2557 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2558 pipe_config->limited_color_range = true;
2560 pipe_config->lane_count =
2561 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2563 intel_dp_get_m_n(crtc, pipe_config);
2565 if (port == PORT_A) {
2566 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2567 pipe_config->port_clock = 162000;
2569 pipe_config->port_clock = 270000;
2572 pipe_config->base.adjusted_mode.crtc_clock =
2573 intel_dotclock_calculate(pipe_config->port_clock,
2574 &pipe_config->dp_m_n);
2576 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2577 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2579 * This is a big fat ugly hack.
2581 * Some machines in UEFI boot mode provide us a VBT that has 18
2582 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2583 * unknown we fail to light up. Yet the same BIOS boots up with
2584 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2585 * max, not what it tells us to use.
2587 * Note: This will still be broken if the eDP panel is not lit
2588 * up by the BIOS, and thus we can't get the mode at module
2591 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2592 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2593 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2597 static void intel_disable_dp(struct intel_encoder *encoder,
2598 struct intel_crtc_state *old_crtc_state,
2599 struct drm_connector_state *old_conn_state)
2601 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2602 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2604 if (old_crtc_state->has_audio)
2605 intel_audio_codec_disable(encoder);
2607 if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2608 intel_psr_disable(intel_dp);
2610 /* Make sure the panel is off before trying to change the mode. But also
2611 * ensure that we have vdd while we switch off the panel. */
2612 intel_edp_panel_vdd_on(intel_dp);
2613 intel_edp_backlight_off(intel_dp);
2614 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2615 intel_edp_panel_off(intel_dp);
2617 /* disable the port before the pipe on g4x */
2618 if (INTEL_GEN(dev_priv) < 5)
2619 intel_dp_link_down(intel_dp);
2622 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2623 struct intel_crtc_state *old_crtc_state,
2624 struct drm_connector_state *old_conn_state)
2626 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2627 enum port port = dp_to_dig_port(intel_dp)->port;
2629 intel_dp_link_down(intel_dp);
2631 /* Only ilk+ has port A */
2633 ironlake_edp_pll_off(intel_dp);
2636 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2637 struct intel_crtc_state *old_crtc_state,
2638 struct drm_connector_state *old_conn_state)
2640 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2642 intel_dp_link_down(intel_dp);
2645 static void chv_post_disable_dp(struct intel_encoder *encoder,
2646 struct intel_crtc_state *old_crtc_state,
2647 struct drm_connector_state *old_conn_state)
2649 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2650 struct drm_device *dev = encoder->base.dev;
2651 struct drm_i915_private *dev_priv = to_i915(dev);
2653 intel_dp_link_down(intel_dp);
2655 mutex_lock(&dev_priv->sb_lock);
2657 /* Assert data lane reset */
2658 chv_data_lane_soft_reset(encoder, true);
2660 mutex_unlock(&dev_priv->sb_lock);
2664 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2666 uint8_t dp_train_pat)
2668 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2669 struct drm_device *dev = intel_dig_port->base.base.dev;
2670 struct drm_i915_private *dev_priv = to_i915(dev);
2671 enum port port = intel_dig_port->port;
2673 if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2674 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2675 dp_train_pat & DP_TRAINING_PATTERN_MASK);
2677 if (HAS_DDI(dev_priv)) {
2678 uint32_t temp = I915_READ(DP_TP_CTL(port));
2680 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2681 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2683 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2685 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2686 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2687 case DP_TRAINING_PATTERN_DISABLE:
2688 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2691 case DP_TRAINING_PATTERN_1:
2692 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2694 case DP_TRAINING_PATTERN_2:
2695 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2697 case DP_TRAINING_PATTERN_3:
2698 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2701 I915_WRITE(DP_TP_CTL(port), temp);
2703 } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2704 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2705 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2707 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2708 case DP_TRAINING_PATTERN_DISABLE:
2709 *DP |= DP_LINK_TRAIN_OFF_CPT;
2711 case DP_TRAINING_PATTERN_1:
2712 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2714 case DP_TRAINING_PATTERN_2:
2715 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2717 case DP_TRAINING_PATTERN_3:
2718 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2719 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2724 if (IS_CHERRYVIEW(dev_priv))
2725 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2727 *DP &= ~DP_LINK_TRAIN_MASK;
2729 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2730 case DP_TRAINING_PATTERN_DISABLE:
2731 *DP |= DP_LINK_TRAIN_OFF;
2733 case DP_TRAINING_PATTERN_1:
2734 *DP |= DP_LINK_TRAIN_PAT_1;
2736 case DP_TRAINING_PATTERN_2:
2737 *DP |= DP_LINK_TRAIN_PAT_2;
2739 case DP_TRAINING_PATTERN_3:
2740 if (IS_CHERRYVIEW(dev_priv)) {
2741 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2743 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2744 *DP |= DP_LINK_TRAIN_PAT_2;
2751 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2752 struct intel_crtc_state *old_crtc_state)
2754 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2755 struct drm_i915_private *dev_priv = to_i915(dev);
2757 /* enable with pattern 1 (as per spec) */
2759 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2762 * Magic for VLV/CHV. We _must_ first set up the register
2763 * without actually enabling the port, and then do another
2764 * write to enable the port. Otherwise link training will
2765 * fail when the power sequencer is freshly used for this port.
2767 intel_dp->DP |= DP_PORT_EN;
2768 if (old_crtc_state->has_audio)
2769 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2771 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2772 POSTING_READ(intel_dp->output_reg);
2775 static void intel_enable_dp(struct intel_encoder *encoder,
2776 struct intel_crtc_state *pipe_config,
2777 struct drm_connector_state *conn_state)
2779 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2780 struct drm_device *dev = encoder->base.dev;
2781 struct drm_i915_private *dev_priv = to_i915(dev);
2782 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2783 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2784 enum pipe pipe = crtc->pipe;
2786 if (WARN_ON(dp_reg & DP_PORT_EN))
2791 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2792 vlv_init_panel_power_sequencer(intel_dp);
2794 intel_dp_enable_port(intel_dp, pipe_config);
2796 edp_panel_vdd_on(intel_dp);
2797 edp_panel_on(intel_dp);
2798 edp_panel_vdd_off(intel_dp, true);
2800 pps_unlock(intel_dp);
2802 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2803 unsigned int lane_mask = 0x0;
2805 if (IS_CHERRYVIEW(dev_priv))
2806 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2808 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2812 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2813 intel_dp_start_link_train(intel_dp);
2814 intel_dp_stop_link_train(intel_dp);
2816 if (pipe_config->has_audio) {
2817 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2819 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2823 static void g4x_enable_dp(struct intel_encoder *encoder,
2824 struct intel_crtc_state *pipe_config,
2825 struct drm_connector_state *conn_state)
2827 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2829 intel_enable_dp(encoder, pipe_config, conn_state);
2830 intel_edp_backlight_on(intel_dp);
2833 static void vlv_enable_dp(struct intel_encoder *encoder,
2834 struct intel_crtc_state *pipe_config,
2835 struct drm_connector_state *conn_state)
2837 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2839 intel_edp_backlight_on(intel_dp);
2840 intel_psr_enable(intel_dp);
2843 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2844 struct intel_crtc_state *pipe_config,
2845 struct drm_connector_state *conn_state)
2847 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2848 enum port port = dp_to_dig_port(intel_dp)->port;
2850 intel_dp_prepare(encoder, pipe_config);
2852 /* Only ilk+ has port A */
2854 ironlake_edp_pll_on(intel_dp, pipe_config);
2857 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2859 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2860 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2861 enum pipe pipe = intel_dp->pps_pipe;
2862 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2864 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2866 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2869 edp_panel_vdd_off_sync(intel_dp);
2872 * VLV seems to get confused when multiple power seqeuencers
2873 * have the same port selected (even if only one has power/vdd
2874 * enabled). The failure manifests as vlv_wait_port_ready() failing
2875 * CHV on the other hand doesn't seem to mind having the same port
2876 * selected in multiple power seqeuencers, but let's clear the
2877 * port select always when logically disconnecting a power sequencer
2880 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2881 pipe_name(pipe), port_name(intel_dig_port->port));
2882 I915_WRITE(pp_on_reg, 0);
2883 POSTING_READ(pp_on_reg);
2885 intel_dp->pps_pipe = INVALID_PIPE;
2888 static void vlv_steal_power_sequencer(struct drm_device *dev,
2891 struct drm_i915_private *dev_priv = to_i915(dev);
2892 struct intel_encoder *encoder;
2894 lockdep_assert_held(&dev_priv->pps_mutex);
2896 for_each_intel_encoder(dev, encoder) {
2897 struct intel_dp *intel_dp;
2900 if (encoder->type != INTEL_OUTPUT_DP &&
2901 encoder->type != INTEL_OUTPUT_EDP)
2904 intel_dp = enc_to_intel_dp(&encoder->base);
2905 port = dp_to_dig_port(intel_dp)->port;
2907 WARN(intel_dp->active_pipe == pipe,
2908 "stealing pipe %c power sequencer from active (e)DP port %c\n",
2909 pipe_name(pipe), port_name(port));
2911 if (intel_dp->pps_pipe != pipe)
2914 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2915 pipe_name(pipe), port_name(port));
2917 /* make sure vdd is off before we steal it */
2918 vlv_detach_power_sequencer(intel_dp);
2922 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2924 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2925 struct intel_encoder *encoder = &intel_dig_port->base;
2926 struct drm_device *dev = encoder->base.dev;
2927 struct drm_i915_private *dev_priv = to_i915(dev);
2928 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2930 lockdep_assert_held(&dev_priv->pps_mutex);
2932 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2934 if (intel_dp->pps_pipe != INVALID_PIPE &&
2935 intel_dp->pps_pipe != crtc->pipe) {
2937 * If another power sequencer was being used on this
2938 * port previously make sure to turn off vdd there while
2939 * we still have control of it.
2941 vlv_detach_power_sequencer(intel_dp);
2945 * We may be stealing the power
2946 * sequencer from another port.
2948 vlv_steal_power_sequencer(dev, crtc->pipe);
2950 intel_dp->active_pipe = crtc->pipe;
2952 if (!is_edp(intel_dp))
2955 /* now it's all ours */
2956 intel_dp->pps_pipe = crtc->pipe;
2958 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2959 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2961 /* init power sequencer on this pipe and port */
2962 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2963 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
2966 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
2967 struct intel_crtc_state *pipe_config,
2968 struct drm_connector_state *conn_state)
2970 vlv_phy_pre_encoder_enable(encoder);
2972 intel_enable_dp(encoder, pipe_config, conn_state);
2975 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
2976 struct intel_crtc_state *pipe_config,
2977 struct drm_connector_state *conn_state)
2979 intel_dp_prepare(encoder, pipe_config);
2981 vlv_phy_pre_pll_enable(encoder);
2984 static void chv_pre_enable_dp(struct intel_encoder *encoder,
2985 struct intel_crtc_state *pipe_config,
2986 struct drm_connector_state *conn_state)
2988 chv_phy_pre_encoder_enable(encoder);
2990 intel_enable_dp(encoder, pipe_config, conn_state);
2992 /* Second common lane will stay alive on its own now */
2993 chv_phy_release_cl2_override(encoder);
2996 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
2997 struct intel_crtc_state *pipe_config,
2998 struct drm_connector_state *conn_state)
3000 intel_dp_prepare(encoder, pipe_config);
3002 chv_phy_pre_pll_enable(encoder);
3005 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3006 struct intel_crtc_state *pipe_config,
3007 struct drm_connector_state *conn_state)
3009 chv_phy_post_pll_disable(encoder);
3013 * Fetch AUX CH registers 0x202 - 0x207 which contain
3014 * link status information
3017 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3019 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3020 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3023 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3025 uint8_t psr_caps = 0;
3027 drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps);
3028 return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3031 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3035 drm_dp_dpcd_readb(&intel_dp->aux,
3036 DP_DPRX_FEATURE_ENUMERATION_LIST,
3038 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3041 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3043 uint8_t alpm_caps = 0;
3045 drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &alpm_caps);
3046 return alpm_caps & DP_ALPM_CAP;
3049 /* These are source-specific values. */
3051 intel_dp_voltage_max(struct intel_dp *intel_dp)
3053 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3054 enum port port = dp_to_dig_port(intel_dp)->port;
3056 if (IS_GEN9_LP(dev_priv))
3057 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3058 else if (INTEL_GEN(dev_priv) >= 9) {
3059 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3060 return intel_ddi_dp_voltage_max(encoder);
3061 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3062 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3063 else if (IS_GEN7(dev_priv) && port == PORT_A)
3064 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3065 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3066 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3068 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3072 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3074 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3075 enum port port = dp_to_dig_port(intel_dp)->port;
3077 if (INTEL_GEN(dev_priv) >= 9) {
3078 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3079 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3080 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3081 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3082 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3083 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3084 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3085 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3086 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3088 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3090 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3091 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3092 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3093 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3094 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3095 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3096 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3097 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3098 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3100 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3102 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3103 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3104 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3105 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3106 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3107 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3108 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3109 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3110 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3112 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3114 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3115 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3116 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3117 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3118 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3119 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3120 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3122 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3125 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3126 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3127 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3128 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3129 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3130 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3131 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3132 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3134 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3139 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3141 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3142 unsigned long demph_reg_value, preemph_reg_value,
3143 uniqtranscale_reg_value;
3144 uint8_t train_set = intel_dp->train_set[0];
3146 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3147 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3148 preemph_reg_value = 0x0004000;
3149 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3150 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3151 demph_reg_value = 0x2B405555;
3152 uniqtranscale_reg_value = 0x552AB83A;
3154 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3155 demph_reg_value = 0x2B404040;
3156 uniqtranscale_reg_value = 0x5548B83A;
3158 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3159 demph_reg_value = 0x2B245555;
3160 uniqtranscale_reg_value = 0x5560B83A;
3162 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3163 demph_reg_value = 0x2B405555;
3164 uniqtranscale_reg_value = 0x5598DA3A;
3170 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3171 preemph_reg_value = 0x0002000;
3172 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3173 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3174 demph_reg_value = 0x2B404040;
3175 uniqtranscale_reg_value = 0x5552B83A;
3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3178 demph_reg_value = 0x2B404848;
3179 uniqtranscale_reg_value = 0x5580B83A;
3181 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3182 demph_reg_value = 0x2B404040;
3183 uniqtranscale_reg_value = 0x55ADDA3A;
3189 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3190 preemph_reg_value = 0x0000000;
3191 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3193 demph_reg_value = 0x2B305555;
3194 uniqtranscale_reg_value = 0x5570B83A;
3196 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3197 demph_reg_value = 0x2B2B4040;
3198 uniqtranscale_reg_value = 0x55ADDA3A;
3204 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3205 preemph_reg_value = 0x0006000;
3206 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3208 demph_reg_value = 0x1B405555;
3209 uniqtranscale_reg_value = 0x55ADDA3A;
3219 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3220 uniqtranscale_reg_value, 0);
3225 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3227 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3228 u32 deemph_reg_value, margin_reg_value;
3229 bool uniq_trans_scale = false;
3230 uint8_t train_set = intel_dp->train_set[0];
3232 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3233 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3234 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3236 deemph_reg_value = 128;
3237 margin_reg_value = 52;
3239 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3240 deemph_reg_value = 128;
3241 margin_reg_value = 77;
3243 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3244 deemph_reg_value = 128;
3245 margin_reg_value = 102;
3247 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3248 deemph_reg_value = 128;
3249 margin_reg_value = 154;
3250 uniq_trans_scale = true;
3256 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3257 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3258 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3259 deemph_reg_value = 85;
3260 margin_reg_value = 78;
3262 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3263 deemph_reg_value = 85;
3264 margin_reg_value = 116;
3266 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3267 deemph_reg_value = 85;
3268 margin_reg_value = 154;
3274 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3275 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3276 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3277 deemph_reg_value = 64;
3278 margin_reg_value = 104;
3280 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3281 deemph_reg_value = 64;
3282 margin_reg_value = 154;
3288 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3289 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3291 deemph_reg_value = 43;
3292 margin_reg_value = 154;
3302 chv_set_phy_signal_level(encoder, deemph_reg_value,
3303 margin_reg_value, uniq_trans_scale);
3309 gen4_signal_levels(uint8_t train_set)
3311 uint32_t signal_levels = 0;
3313 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3314 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3316 signal_levels |= DP_VOLTAGE_0_4;
3318 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3319 signal_levels |= DP_VOLTAGE_0_6;
3321 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3322 signal_levels |= DP_VOLTAGE_0_8;
3324 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3325 signal_levels |= DP_VOLTAGE_1_2;
3328 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3329 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3331 signal_levels |= DP_PRE_EMPHASIS_0;
3333 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3334 signal_levels |= DP_PRE_EMPHASIS_3_5;
3336 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3337 signal_levels |= DP_PRE_EMPHASIS_6;
3339 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3340 signal_levels |= DP_PRE_EMPHASIS_9_5;
3343 return signal_levels;
3346 /* Gen6's DP voltage swing and pre-emphasis control */
3348 gen6_edp_signal_levels(uint8_t train_set)
3350 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3351 DP_TRAIN_PRE_EMPHASIS_MASK);
3352 switch (signal_levels) {
3353 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3354 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3355 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3356 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3357 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3358 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3359 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3360 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3361 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3362 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3363 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3364 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3365 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3366 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3368 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3369 "0x%x\n", signal_levels);
3370 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3374 /* Gen7's DP voltage swing and pre-emphasis control */
3376 gen7_edp_signal_levels(uint8_t train_set)
3378 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3379 DP_TRAIN_PRE_EMPHASIS_MASK);
3380 switch (signal_levels) {
3381 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3382 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3383 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3384 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3385 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3386 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3388 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3389 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3390 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3391 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3393 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3394 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3395 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3396 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3399 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3400 "0x%x\n", signal_levels);
3401 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3406 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3408 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3409 enum port port = intel_dig_port->port;
3410 struct drm_device *dev = intel_dig_port->base.base.dev;
3411 struct drm_i915_private *dev_priv = to_i915(dev);
3412 uint32_t signal_levels, mask = 0;
3413 uint8_t train_set = intel_dp->train_set[0];
3415 if (HAS_DDI(dev_priv)) {
3416 signal_levels = ddi_signal_levels(intel_dp);
3418 if (IS_GEN9_LP(dev_priv))
3421 mask = DDI_BUF_EMP_MASK;
3422 } else if (IS_CHERRYVIEW(dev_priv)) {
3423 signal_levels = chv_signal_levels(intel_dp);
3424 } else if (IS_VALLEYVIEW(dev_priv)) {
3425 signal_levels = vlv_signal_levels(intel_dp);
3426 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3427 signal_levels = gen7_edp_signal_levels(train_set);
3428 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3429 } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3430 signal_levels = gen6_edp_signal_levels(train_set);
3431 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3433 signal_levels = gen4_signal_levels(train_set);
3434 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3438 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3440 DRM_DEBUG_KMS("Using vswing level %d\n",
3441 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3442 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3443 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3444 DP_TRAIN_PRE_EMPHASIS_SHIFT);
3446 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3448 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3449 POSTING_READ(intel_dp->output_reg);
3453 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3454 uint8_t dp_train_pat)
3456 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3457 struct drm_i915_private *dev_priv =
3458 to_i915(intel_dig_port->base.base.dev);
3460 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3462 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3463 POSTING_READ(intel_dp->output_reg);
3466 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3468 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3469 struct drm_device *dev = intel_dig_port->base.base.dev;
3470 struct drm_i915_private *dev_priv = to_i915(dev);
3471 enum port port = intel_dig_port->port;
3474 if (!HAS_DDI(dev_priv))
3477 val = I915_READ(DP_TP_CTL(port));
3478 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3479 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3480 I915_WRITE(DP_TP_CTL(port), val);
3483 * On PORT_A we can have only eDP in SST mode. There the only reason
3484 * we need to set idle transmission mode is to work around a HW issue
3485 * where we enable the pipe while not in idle link-training mode.
3486 * In this case there is requirement to wait for a minimum number of
3487 * idle patterns to be sent.
3492 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3493 DP_TP_STATUS_IDLE_DONE,
3494 DP_TP_STATUS_IDLE_DONE,
3496 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3500 intel_dp_link_down(struct intel_dp *intel_dp)
3502 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3503 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3504 enum port port = intel_dig_port->port;
3505 struct drm_device *dev = intel_dig_port->base.base.dev;
3506 struct drm_i915_private *dev_priv = to_i915(dev);
3507 uint32_t DP = intel_dp->DP;
3509 if (WARN_ON(HAS_DDI(dev_priv)))
3512 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3515 DRM_DEBUG_KMS("\n");
3517 if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3518 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3519 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3520 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3522 if (IS_CHERRYVIEW(dev_priv))
3523 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3525 DP &= ~DP_LINK_TRAIN_MASK;
3526 DP |= DP_LINK_TRAIN_PAT_IDLE;
3528 I915_WRITE(intel_dp->output_reg, DP);
3529 POSTING_READ(intel_dp->output_reg);
3531 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3532 I915_WRITE(intel_dp->output_reg, DP);
3533 POSTING_READ(intel_dp->output_reg);
3536 * HW workaround for IBX, we need to move the port
3537 * to transcoder A after disabling it to allow the
3538 * matching HDMI port to be enabled on transcoder A.
3540 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3542 * We get CPU/PCH FIFO underruns on the other pipe when
3543 * doing the workaround. Sweep them under the rug.
3545 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3546 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3548 /* always enable with pattern 1 (as per spec) */
3549 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3550 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3551 I915_WRITE(intel_dp->output_reg, DP);
3552 POSTING_READ(intel_dp->output_reg);
3555 I915_WRITE(intel_dp->output_reg, DP);
3556 POSTING_READ(intel_dp->output_reg);
3558 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3559 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3560 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3563 msleep(intel_dp->panel_power_down_delay);
3567 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3569 intel_dp->active_pipe = INVALID_PIPE;
3570 pps_unlock(intel_dp);
3575 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3577 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3578 sizeof(intel_dp->dpcd)) < 0)
3579 return false; /* aux transfer failed */
3581 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3583 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3587 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3589 struct drm_i915_private *dev_priv =
3590 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3592 /* this function is meant to be called only once */
3593 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3595 if (!intel_dp_read_dpcd(intel_dp))
3598 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3599 drm_dp_is_branch(intel_dp->dpcd));
3601 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3602 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3603 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3605 /* Check if the panel supports PSR */
3606 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3608 sizeof(intel_dp->psr_dpcd));
3609 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3610 dev_priv->psr.sink_support = true;
3611 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3614 if (INTEL_GEN(dev_priv) >= 9 &&
3615 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3616 uint8_t frame_sync_cap;
3618 dev_priv->psr.sink_support = true;
3619 drm_dp_dpcd_read(&intel_dp->aux,
3620 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3621 &frame_sync_cap, 1);
3622 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3623 /* PSR2 needs frame sync as well */
3624 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3625 DRM_DEBUG_KMS("PSR2 %s on sink",
3626 dev_priv->psr.psr2_support ? "supported" : "not supported");
3628 if (dev_priv->psr.psr2_support) {
3629 dev_priv->psr.y_cord_support =
3630 intel_dp_get_y_cord_status(intel_dp);
3631 dev_priv->psr.colorimetry_support =
3632 intel_dp_get_colorimetry_status(intel_dp);
3633 dev_priv->psr.alpm =
3634 intel_dp_get_alpm_status(intel_dp);
3639 /* Read the eDP Display control capabilities registers */
3640 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3641 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3642 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3643 sizeof(intel_dp->edp_dpcd))
3644 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3645 intel_dp->edp_dpcd);
3647 /* Intermediate frequency support */
3648 if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3649 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3652 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3653 sink_rates, sizeof(sink_rates));
3655 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3656 int val = le16_to_cpu(sink_rates[i]);
3661 /* Value read multiplied by 200kHz gives the per-lane
3662 * link rate in kHz. The source rates are, however,
3663 * stored in terms of LS_Clk kHz. The full conversion
3664 * back to symbols is
3665 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3667 intel_dp->sink_rates[i] = (val * 200) / 10;
3669 intel_dp->num_sink_rates = i;
3677 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3679 if (!intel_dp_read_dpcd(intel_dp))
3682 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3683 &intel_dp->sink_count, 1) < 0)
3687 * Sink count can change between short pulse hpd hence
3688 * a member variable in intel_dp will track any changes
3689 * between short pulse interrupts.
3691 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3694 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3695 * a dongle is present but no display. Unless we require to know
3696 * if a dongle is present or not, we don't need to update
3697 * downstream port information. So, an early return here saves
3698 * time from performing other operations which are not required.
3700 if (!is_edp(intel_dp) && !intel_dp->sink_count)
3703 if (!drm_dp_is_branch(intel_dp->dpcd))
3704 return true; /* native DP sink */
3706 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3707 return true; /* no per-port downstream info */
3709 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3710 intel_dp->downstream_ports,
3711 DP_MAX_DOWNSTREAM_PORTS) < 0)
3712 return false; /* downstream port status fetch failed */
3718 intel_dp_can_mst(struct intel_dp *intel_dp)
3722 if (!i915.enable_dp_mst)
3725 if (!intel_dp->can_mst)
3728 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3731 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3734 return buf[0] & DP_MST_CAP;
3738 intel_dp_configure_mst(struct intel_dp *intel_dp)
3740 if (!i915.enable_dp_mst)
3743 if (!intel_dp->can_mst)
3746 intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3748 if (intel_dp->is_mst)
3749 DRM_DEBUG_KMS("Sink is MST capable\n");
3751 DRM_DEBUG_KMS("Sink is not MST capable\n");
3753 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3757 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3759 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3760 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3761 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3767 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3768 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3773 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3774 buf & ~DP_TEST_SINK_START) < 0) {
3775 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3781 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3783 if (drm_dp_dpcd_readb(&intel_dp->aux,
3784 DP_TEST_SINK_MISC, &buf) < 0) {
3788 count = buf & DP_TEST_COUNT_MASK;
3789 } while (--attempts && count);
3791 if (attempts == 0) {
3792 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3797 hsw_enable_ips(intel_crtc);
3801 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3803 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3804 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3805 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3809 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3812 if (!(buf & DP_TEST_CRC_SUPPORTED))
3815 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3818 if (buf & DP_TEST_SINK_START) {
3819 ret = intel_dp_sink_crc_stop(intel_dp);
3824 hsw_disable_ips(intel_crtc);
3826 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3827 buf | DP_TEST_SINK_START) < 0) {
3828 hsw_enable_ips(intel_crtc);
3832 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3836 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3838 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3839 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3840 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3845 ret = intel_dp_sink_crc_start(intel_dp);
3850 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3852 if (drm_dp_dpcd_readb(&intel_dp->aux,
3853 DP_TEST_SINK_MISC, &buf) < 0) {
3857 count = buf & DP_TEST_COUNT_MASK;
3859 } while (--attempts && count == 0);
3861 if (attempts == 0) {
3862 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3867 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3873 intel_dp_sink_crc_stop(intel_dp);
3878 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3880 return drm_dp_dpcd_read(&intel_dp->aux,
3881 DP_DEVICE_SERVICE_IRQ_VECTOR,
3882 sink_irq_vector, 1) == 1;
3886 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3890 ret = drm_dp_dpcd_read(&intel_dp->aux,
3892 sink_irq_vector, 14);
3899 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3902 int min_lane_count = 1;
3903 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
3904 int link_rate_index, test_link_rate;
3905 uint8_t test_lane_count, test_link_bw;
3909 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3910 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3914 DRM_DEBUG_KMS("Lane count read failed\n");
3917 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3918 /* Validate the requested lane count */
3919 if (test_lane_count < min_lane_count ||
3920 test_lane_count > intel_dp->max_sink_lane_count)
3923 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3926 DRM_DEBUG_KMS("Link Rate read failed\n");
3929 /* Validate the requested link rate */
3930 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3931 link_rate_index = intel_dp_link_rate_index(intel_dp,
3934 if (link_rate_index < 0)
3937 intel_dp->compliance.test_lane_count = test_lane_count;
3938 intel_dp->compliance.test_link_rate = test_link_rate;
3943 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3945 uint8_t test_pattern;
3947 __be16 h_width, v_height;
3950 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3951 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_PATTERN,
3954 DRM_DEBUG_KMS("Test pattern read failed\n");
3957 if (test_pattern != DP_COLOR_RAMP)
3960 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3963 DRM_DEBUG_KMS("H Width read failed\n");
3967 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3970 DRM_DEBUG_KMS("V Height read failed\n");
3974 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_MISC0,
3977 DRM_DEBUG_KMS("TEST MISC read failed\n");
3980 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3982 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3984 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3985 case DP_TEST_BIT_DEPTH_6:
3986 intel_dp->compliance.test_data.bpc = 6;
3988 case DP_TEST_BIT_DEPTH_8:
3989 intel_dp->compliance.test_data.bpc = 8;
3995 intel_dp->compliance.test_data.video_pattern = test_pattern;
3996 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3997 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3998 /* Set test active flag here so userspace doesn't interrupt things */
3999 intel_dp->compliance.test_active = 1;
4004 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4006 uint8_t test_result = DP_TEST_ACK;
4007 struct intel_connector *intel_connector = intel_dp->attached_connector;
4008 struct drm_connector *connector = &intel_connector->base;
4010 if (intel_connector->detect_edid == NULL ||
4011 connector->edid_corrupt ||
4012 intel_dp->aux.i2c_defer_count > 6) {
4013 /* Check EDID read for NACKs, DEFERs and corruption
4014 * (DP CTS 1.2 Core r1.1)
4015 * 4.2.2.4 : Failed EDID read, I2C_NAK
4016 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4017 * 4.2.2.6 : EDID corruption detected
4018 * Use failsafe mode for all cases
4020 if (intel_dp->aux.i2c_nack_count > 0 ||
4021 intel_dp->aux.i2c_defer_count > 0)
4022 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4023 intel_dp->aux.i2c_nack_count,
4024 intel_dp->aux.i2c_defer_count);
4025 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4027 struct edid *block = intel_connector->detect_edid;
4029 /* We have to write the checksum
4030 * of the last block read
4032 block += intel_connector->detect_edid->extensions;
4034 if (!drm_dp_dpcd_write(&intel_dp->aux,
4035 DP_TEST_EDID_CHECKSUM,
4038 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4040 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4041 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4044 /* Set test active flag here so userspace doesn't interrupt things */
4045 intel_dp->compliance.test_active = 1;
4050 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4052 uint8_t test_result = DP_TEST_NAK;
4056 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4058 uint8_t response = DP_TEST_NAK;
4059 uint8_t request = 0;
4062 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4064 DRM_DEBUG_KMS("Could not read test request from sink\n");
4069 case DP_TEST_LINK_TRAINING:
4070 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4071 response = intel_dp_autotest_link_training(intel_dp);
4073 case DP_TEST_LINK_VIDEO_PATTERN:
4074 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4075 response = intel_dp_autotest_video_pattern(intel_dp);
4077 case DP_TEST_LINK_EDID_READ:
4078 DRM_DEBUG_KMS("EDID test requested\n");
4079 response = intel_dp_autotest_edid(intel_dp);
4081 case DP_TEST_LINK_PHY_TEST_PATTERN:
4082 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4083 response = intel_dp_autotest_phy_pattern(intel_dp);
4086 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4090 if (response & DP_TEST_ACK)
4091 intel_dp->compliance.test_type = request;
4094 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4096 DRM_DEBUG_KMS("Could not write test response to sink\n");
4100 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4104 if (intel_dp->is_mst) {
4109 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4113 /* check link status - esi[10] = 0x200c */
4114 if (intel_dp->active_mst_links &&
4115 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4116 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4117 intel_dp_start_link_train(intel_dp);
4118 intel_dp_stop_link_train(intel_dp);
4121 DRM_DEBUG_KMS("got esi %3ph\n", esi);
4122 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4125 for (retry = 0; retry < 3; retry++) {
4127 wret = drm_dp_dpcd_write(&intel_dp->aux,
4128 DP_SINK_COUNT_ESI+1,
4135 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4137 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4145 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4146 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4147 intel_dp->is_mst = false;
4148 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4149 /* send a hotplug event */
4150 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4157 intel_dp_retrain_link(struct intel_dp *intel_dp)
4159 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4160 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4161 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4163 /* Suppress underruns caused by re-training */
4164 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4165 if (crtc->config->has_pch_encoder)
4166 intel_set_pch_fifo_underrun_reporting(dev_priv,
4167 intel_crtc_pch_transcoder(crtc), false);
4169 intel_dp_start_link_train(intel_dp);
4170 intel_dp_stop_link_train(intel_dp);
4172 /* Keep underrun reporting disabled until things are stable */
4173 intel_wait_for_vblank(dev_priv, crtc->pipe);
4175 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4176 if (crtc->config->has_pch_encoder)
4177 intel_set_pch_fifo_underrun_reporting(dev_priv,
4178 intel_crtc_pch_transcoder(crtc), true);
4182 intel_dp_check_link_status(struct intel_dp *intel_dp)
4184 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4185 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4186 u8 link_status[DP_LINK_STATUS_SIZE];
4188 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4190 if (!intel_dp_get_link_status(intel_dp, link_status)) {
4191 DRM_ERROR("Failed to get link status\n");
4195 if (!intel_encoder->base.crtc)
4198 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4201 /* FIXME: we need to synchronize this sort of stuff with hardware
4202 * readout. Currently fast link training doesn't work on boot-up. */
4203 if (!intel_dp->lane_count)
4206 /* Retrain if Channel EQ or CR not ok */
4207 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4208 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4209 intel_encoder->base.name);
4211 intel_dp_retrain_link(intel_dp);
4216 * According to DP spec
4219 * 2. Configure link according to Receiver Capabilities
4220 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4221 * 4. Check link status on receipt of hot-plug interrupt
4223 * intel_dp_short_pulse - handles short pulse interrupts
4224 * when full detection is not required.
4225 * Returns %true if short pulse is handled and full detection
4226 * is NOT required and %false otherwise.
4229 intel_dp_short_pulse(struct intel_dp *intel_dp)
4231 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4232 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4233 u8 sink_irq_vector = 0;
4234 u8 old_sink_count = intel_dp->sink_count;
4238 * Clearing compliance test variables to allow capturing
4239 * of values for next automated test request.
4241 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4244 * Now read the DPCD to see if it's actually running
4245 * If the current value of sink count doesn't match with
4246 * the value that was stored earlier or dpcd read failed
4247 * we need to do full detection
4249 ret = intel_dp_get_dpcd(intel_dp);
4251 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4252 /* No need to proceed if we are going to do full detect */
4256 /* Try to read the source of the interrupt */
4257 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4258 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4259 sink_irq_vector != 0) {
4260 /* Clear interrupt source */
4261 drm_dp_dpcd_writeb(&intel_dp->aux,
4262 DP_DEVICE_SERVICE_IRQ_VECTOR,
4265 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4266 intel_dp_handle_test_request(intel_dp);
4267 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4268 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4271 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4272 intel_dp_check_link_status(intel_dp);
4273 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4274 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4275 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4276 /* Send a Hotplug Uevent to userspace to start modeset */
4277 drm_kms_helper_hotplug_event(intel_encoder->base.dev);
4283 /* XXX this is probably wrong for multiple downstream ports */
4284 static enum drm_connector_status
4285 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4287 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4288 uint8_t *dpcd = intel_dp->dpcd;
4292 lspcon_resume(lspcon);
4294 if (!intel_dp_get_dpcd(intel_dp))
4295 return connector_status_disconnected;
4297 if (is_edp(intel_dp))
4298 return connector_status_connected;
4300 /* if there's no downstream port, we're done */
4301 if (!drm_dp_is_branch(dpcd))
4302 return connector_status_connected;
4304 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4305 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4306 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4308 return intel_dp->sink_count ?
4309 connector_status_connected : connector_status_disconnected;
4312 if (intel_dp_can_mst(intel_dp))
4313 return connector_status_connected;
4315 /* If no HPD, poke DDC gently */
4316 if (drm_probe_ddc(&intel_dp->aux.ddc))
4317 return connector_status_connected;
4319 /* Well we tried, say unknown for unreliable port types */
4320 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4321 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4322 if (type == DP_DS_PORT_TYPE_VGA ||
4323 type == DP_DS_PORT_TYPE_NON_EDID)
4324 return connector_status_unknown;
4326 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4327 DP_DWN_STRM_PORT_TYPE_MASK;
4328 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4329 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4330 return connector_status_unknown;
4333 /* Anything else is out of spec, warn and ignore */
4334 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4335 return connector_status_disconnected;
4338 static enum drm_connector_status
4339 edp_detect(struct intel_dp *intel_dp)
4341 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4342 struct drm_i915_private *dev_priv = to_i915(dev);
4343 enum drm_connector_status status;
4345 status = intel_panel_detect(dev_priv);
4346 if (status == connector_status_unknown)
4347 status = connector_status_connected;
4352 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4353 struct intel_digital_port *port)
4357 switch (port->port) {
4361 bit = SDE_PORTB_HOTPLUG;
4364 bit = SDE_PORTC_HOTPLUG;
4367 bit = SDE_PORTD_HOTPLUG;
4370 MISSING_CASE(port->port);
4374 return I915_READ(SDEISR) & bit;
4377 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4378 struct intel_digital_port *port)
4382 switch (port->port) {
4386 bit = SDE_PORTB_HOTPLUG_CPT;
4389 bit = SDE_PORTC_HOTPLUG_CPT;
4392 bit = SDE_PORTD_HOTPLUG_CPT;
4395 bit = SDE_PORTE_HOTPLUG_SPT;
4398 MISSING_CASE(port->port);
4402 return I915_READ(SDEISR) & bit;
4405 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4406 struct intel_digital_port *port)
4410 switch (port->port) {
4412 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4415 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4418 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4421 MISSING_CASE(port->port);
4425 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4428 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4429 struct intel_digital_port *port)
4433 switch (port->port) {
4435 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4438 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4441 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4444 MISSING_CASE(port->port);
4448 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4451 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4452 struct intel_digital_port *intel_dig_port)
4454 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4458 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4461 bit = BXT_DE_PORT_HP_DDIA;
4464 bit = BXT_DE_PORT_HP_DDIB;
4467 bit = BXT_DE_PORT_HP_DDIC;
4474 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4478 * intel_digital_port_connected - is the specified port connected?
4479 * @dev_priv: i915 private structure
4480 * @port: the port to test
4482 * Return %true if @port is connected, %false otherwise.
4484 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4485 struct intel_digital_port *port)
4487 if (HAS_PCH_IBX(dev_priv))
4488 return ibx_digital_port_connected(dev_priv, port);
4489 else if (HAS_PCH_SPLIT(dev_priv))
4490 return cpt_digital_port_connected(dev_priv, port);
4491 else if (IS_GEN9_LP(dev_priv))
4492 return bxt_digital_port_connected(dev_priv, port);
4493 else if (IS_GM45(dev_priv))
4494 return gm45_digital_port_connected(dev_priv, port);
4496 return g4x_digital_port_connected(dev_priv, port);
4499 static struct edid *
4500 intel_dp_get_edid(struct intel_dp *intel_dp)
4502 struct intel_connector *intel_connector = intel_dp->attached_connector;
4504 /* use cached edid if we have one */
4505 if (intel_connector->edid) {
4507 if (IS_ERR(intel_connector->edid))
4510 return drm_edid_duplicate(intel_connector->edid);
4512 return drm_get_edid(&intel_connector->base,
4513 &intel_dp->aux.ddc);
4517 intel_dp_set_edid(struct intel_dp *intel_dp)
4519 struct intel_connector *intel_connector = intel_dp->attached_connector;
4522 intel_dp_unset_edid(intel_dp);
4523 edid = intel_dp_get_edid(intel_dp);
4524 intel_connector->detect_edid = edid;
4526 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4527 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4529 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4533 intel_dp_unset_edid(struct intel_dp *intel_dp)
4535 struct intel_connector *intel_connector = intel_dp->attached_connector;
4537 kfree(intel_connector->detect_edid);
4538 intel_connector->detect_edid = NULL;
4540 intel_dp->has_audio = false;
4544 intel_dp_long_pulse(struct intel_connector *intel_connector)
4546 struct drm_connector *connector = &intel_connector->base;
4547 struct intel_dp *intel_dp = intel_attached_dp(connector);
4548 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4549 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4550 struct drm_device *dev = connector->dev;
4551 enum drm_connector_status status;
4552 u8 sink_irq_vector = 0;
4554 WARN_ON(!drm_modeset_is_locked(&connector->dev->mode_config.connection_mutex));
4556 intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain);
4558 /* Can't disconnect eDP, but you can close the lid... */
4559 if (is_edp(intel_dp))
4560 status = edp_detect(intel_dp);
4561 else if (intel_digital_port_connected(to_i915(dev),
4562 dp_to_dig_port(intel_dp)))
4563 status = intel_dp_detect_dpcd(intel_dp);
4565 status = connector_status_disconnected;
4567 if (status == connector_status_disconnected) {
4568 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4570 if (intel_dp->is_mst) {
4571 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4573 intel_dp->mst_mgr.mst_state);
4574 intel_dp->is_mst = false;
4575 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4582 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4583 intel_encoder->type = INTEL_OUTPUT_DP;
4585 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4586 yesno(intel_dp_source_supports_hbr2(intel_dp)),
4587 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4589 if (intel_dp->reset_link_params) {
4590 /* Set the max lane count for sink */
4591 intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
4593 /* Set the max link BW for sink */
4594 intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
4596 intel_dp->reset_link_params = false;
4599 intel_dp_print_rates(intel_dp);
4601 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4602 drm_dp_is_branch(intel_dp->dpcd));
4604 intel_dp_configure_mst(intel_dp);
4606 if (intel_dp->is_mst) {
4608 * If we are in MST mode then this connector
4609 * won't appear connected or have anything
4612 status = connector_status_disconnected;
4616 * If display is now connected check links status,
4617 * there has been known issues of link loss triggerring
4620 * Some sinks (eg. ASUS PB287Q) seem to perform some
4621 * weird HPD ping pong during modesets. So we can apparently
4622 * end up with HPD going low during a modeset, and then
4623 * going back up soon after. And once that happens we must
4624 * retrain the link to get a picture. That's in case no
4625 * userspace component reacted to intermittent HPD dip.
4627 intel_dp_check_link_status(intel_dp);
4631 * Clearing NACK and defer counts to get their exact values
4632 * while reading EDID which are required by Compliance tests
4633 * 4.2.2.4 and 4.2.2.5
4635 intel_dp->aux.i2c_nack_count = 0;
4636 intel_dp->aux.i2c_defer_count = 0;
4638 intel_dp_set_edid(intel_dp);
4639 if (is_edp(intel_dp) || intel_connector->detect_edid)
4640 status = connector_status_connected;
4641 intel_dp->detect_done = true;
4643 /* Try to read the source of the interrupt */
4644 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4645 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4646 sink_irq_vector != 0) {
4647 /* Clear interrupt source */
4648 drm_dp_dpcd_writeb(&intel_dp->aux,
4649 DP_DEVICE_SERVICE_IRQ_VECTOR,
4652 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4653 intel_dp_handle_test_request(intel_dp);
4654 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4655 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4659 if (status != connector_status_connected && !intel_dp->is_mst)
4660 intel_dp_unset_edid(intel_dp);
4662 intel_display_power_put(to_i915(dev), intel_dp->aux_power_domain);
4667 intel_dp_detect(struct drm_connector *connector,
4668 struct drm_modeset_acquire_ctx *ctx,
4671 struct intel_dp *intel_dp = intel_attached_dp(connector);
4672 int status = connector->status;
4674 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4675 connector->base.id, connector->name);
4677 /* If full detect is not performed yet, do a full detect */
4678 if (!intel_dp->detect_done)
4679 status = intel_dp_long_pulse(intel_dp->attached_connector);
4681 intel_dp->detect_done = false;
4687 intel_dp_force(struct drm_connector *connector)
4689 struct intel_dp *intel_dp = intel_attached_dp(connector);
4690 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4691 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4693 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4694 connector->base.id, connector->name);
4695 intel_dp_unset_edid(intel_dp);
4697 if (connector->status != connector_status_connected)
4700 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4702 intel_dp_set_edid(intel_dp);
4704 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4706 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4707 intel_encoder->type = INTEL_OUTPUT_DP;
4710 static int intel_dp_get_modes(struct drm_connector *connector)
4712 struct intel_connector *intel_connector = to_intel_connector(connector);
4715 edid = intel_connector->detect_edid;
4717 int ret = intel_connector_update_modes(connector, edid);
4722 /* if eDP has no EDID, fall back to fixed mode */
4723 if (is_edp(intel_attached_dp(connector)) &&
4724 intel_connector->panel.fixed_mode) {
4725 struct drm_display_mode *mode;
4727 mode = drm_mode_duplicate(connector->dev,
4728 intel_connector->panel.fixed_mode);
4730 drm_mode_probed_add(connector, mode);
4739 intel_dp_detect_audio(struct drm_connector *connector)
4741 bool has_audio = false;
4744 edid = to_intel_connector(connector)->detect_edid;
4746 has_audio = drm_detect_monitor_audio(edid);
4752 intel_dp_set_property(struct drm_connector *connector,
4753 struct drm_property *property,
4756 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4757 struct intel_connector *intel_connector = to_intel_connector(connector);
4758 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4759 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4762 ret = drm_object_property_set_value(&connector->base, property, val);
4766 if (property == dev_priv->force_audio_property) {
4770 if (i == intel_dp->force_audio)
4773 intel_dp->force_audio = i;
4775 if (i == HDMI_AUDIO_AUTO)
4776 has_audio = intel_dp_detect_audio(connector);
4778 has_audio = (i == HDMI_AUDIO_ON);
4780 if (has_audio == intel_dp->has_audio)
4783 intel_dp->has_audio = has_audio;
4787 if (property == dev_priv->broadcast_rgb_property) {
4788 bool old_auto = intel_dp->color_range_auto;
4789 bool old_range = intel_dp->limited_color_range;
4792 case INTEL_BROADCAST_RGB_AUTO:
4793 intel_dp->color_range_auto = true;
4795 case INTEL_BROADCAST_RGB_FULL:
4796 intel_dp->color_range_auto = false;
4797 intel_dp->limited_color_range = false;
4799 case INTEL_BROADCAST_RGB_LIMITED:
4800 intel_dp->color_range_auto = false;
4801 intel_dp->limited_color_range = true;
4807 if (old_auto == intel_dp->color_range_auto &&
4808 old_range == intel_dp->limited_color_range)
4814 if (is_edp(intel_dp) &&
4815 property == connector->dev->mode_config.scaling_mode_property) {
4816 if (val == DRM_MODE_SCALE_NONE) {
4817 DRM_DEBUG_KMS("no scaling not supported\n");
4820 if (HAS_GMCH_DISPLAY(dev_priv) &&
4821 val == DRM_MODE_SCALE_CENTER) {
4822 DRM_DEBUG_KMS("centering not supported\n");
4826 if (intel_connector->panel.fitting_mode == val) {
4827 /* the eDP scaling property is not changed */
4830 intel_connector->panel.fitting_mode = val;
4838 if (intel_encoder->base.crtc)
4839 intel_crtc_restore_mode(intel_encoder->base.crtc);
4845 intel_dp_connector_register(struct drm_connector *connector)
4847 struct intel_dp *intel_dp = intel_attached_dp(connector);
4850 ret = intel_connector_register(connector);
4854 i915_debugfs_connector_add(connector);
4856 DRM_DEBUG_KMS("registering %s bus for %s\n",
4857 intel_dp->aux.name, connector->kdev->kobj.name);
4859 intel_dp->aux.dev = connector->kdev;
4860 return drm_dp_aux_register(&intel_dp->aux);
4864 intel_dp_connector_unregister(struct drm_connector *connector)
4866 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4867 intel_connector_unregister(connector);
4871 intel_dp_connector_destroy(struct drm_connector *connector)
4873 struct intel_connector *intel_connector = to_intel_connector(connector);
4875 kfree(intel_connector->detect_edid);
4877 if (!IS_ERR_OR_NULL(intel_connector->edid))
4878 kfree(intel_connector->edid);
4880 /* Can't call is_edp() since the encoder may have been destroyed
4882 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4883 intel_panel_fini(&intel_connector->panel);
4885 drm_connector_cleanup(connector);
4889 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4891 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4892 struct intel_dp *intel_dp = &intel_dig_port->dp;
4894 intel_dp_mst_encoder_cleanup(intel_dig_port);
4895 if (is_edp(intel_dp)) {
4896 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4898 * vdd might still be enabled do to the delayed vdd off.
4899 * Make sure vdd is actually turned off here.
4902 edp_panel_vdd_off_sync(intel_dp);
4903 pps_unlock(intel_dp);
4905 if (intel_dp->edp_notifier.notifier_call) {
4906 unregister_reboot_notifier(&intel_dp->edp_notifier);
4907 intel_dp->edp_notifier.notifier_call = NULL;
4911 intel_dp_aux_fini(intel_dp);
4913 drm_encoder_cleanup(encoder);
4914 kfree(intel_dig_port);
4917 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4919 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4921 if (!is_edp(intel_dp))
4925 * vdd might still be enabled do to the delayed vdd off.
4926 * Make sure vdd is actually turned off here.
4928 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4930 edp_panel_vdd_off_sync(intel_dp);
4931 pps_unlock(intel_dp);
4934 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4936 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4937 struct drm_device *dev = intel_dig_port->base.base.dev;
4938 struct drm_i915_private *dev_priv = to_i915(dev);
4940 lockdep_assert_held(&dev_priv->pps_mutex);
4942 if (!edp_have_panel_vdd(intel_dp))
4946 * The VDD bit needs a power domain reference, so if the bit is
4947 * already enabled when we boot or resume, grab this reference and
4948 * schedule a vdd off, so we don't hold on to the reference
4951 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4952 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4954 edp_panel_vdd_schedule_off(intel_dp);
4957 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
4959 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4961 if ((intel_dp->DP & DP_PORT_EN) == 0)
4962 return INVALID_PIPE;
4964 if (IS_CHERRYVIEW(dev_priv))
4965 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
4967 return PORT_TO_PIPE(intel_dp->DP);
4970 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4972 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4973 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4974 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4976 if (!HAS_DDI(dev_priv))
4977 intel_dp->DP = I915_READ(intel_dp->output_reg);
4980 lspcon_resume(lspcon);
4982 intel_dp->reset_link_params = true;
4986 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4987 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
4989 if (is_edp(intel_dp)) {
4990 /* Reinit the power sequencer, in case BIOS did something with it. */
4991 intel_dp_pps_init(encoder->dev, intel_dp);
4992 intel_edp_panel_vdd_sanitize(intel_dp);
4995 pps_unlock(intel_dp);
4998 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4999 .dpms = drm_atomic_helper_connector_dpms,
5000 .force = intel_dp_force,
5001 .fill_modes = drm_helper_probe_single_connector_modes,
5002 .set_property = intel_dp_set_property,
5003 .atomic_get_property = intel_connector_atomic_get_property,
5004 .late_register = intel_dp_connector_register,
5005 .early_unregister = intel_dp_connector_unregister,
5006 .destroy = intel_dp_connector_destroy,
5007 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5008 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
5011 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5012 .detect_ctx = intel_dp_detect,
5013 .get_modes = intel_dp_get_modes,
5014 .mode_valid = intel_dp_mode_valid,
5017 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5018 .reset = intel_dp_encoder_reset,
5019 .destroy = intel_dp_encoder_destroy,
5023 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5025 struct intel_dp *intel_dp = &intel_dig_port->dp;
5026 struct drm_device *dev = intel_dig_port->base.base.dev;
5027 struct drm_i915_private *dev_priv = to_i915(dev);
5028 enum irqreturn ret = IRQ_NONE;
5030 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
5031 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
5032 intel_dig_port->base.type = INTEL_OUTPUT_DP;
5034 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5036 * vdd off can generate a long pulse on eDP which
5037 * would require vdd on to handle it, and thus we
5038 * would end up in an endless cycle of
5039 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5041 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5042 port_name(intel_dig_port->port));
5046 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5047 port_name(intel_dig_port->port),
5048 long_hpd ? "long" : "short");
5051 intel_dp->reset_link_params = true;
5052 intel_dp->detect_done = false;
5056 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5058 if (intel_dp->is_mst) {
5059 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5061 * If we were in MST mode, and device is not
5062 * there, get out of MST mode
5064 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5065 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5066 intel_dp->is_mst = false;
5067 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5069 intel_dp->detect_done = false;
5074 if (!intel_dp->is_mst) {
5075 if (!intel_dp_short_pulse(intel_dp)) {
5076 intel_dp->detect_done = false;
5084 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5089 /* check the VBT to see whether the eDP is on another port */
5090 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port)
5093 * eDP not supported on g4x. so bail out early just
5094 * for a bit extra safety in case the VBT is bonkers.
5096 if (INTEL_GEN(dev_priv) < 5)
5099 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5102 return intel_bios_is_port_edp(dev_priv, port);
5106 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5108 struct intel_connector *intel_connector = to_intel_connector(connector);
5110 intel_attach_force_audio_property(connector);
5111 intel_attach_broadcast_rgb_property(connector);
5112 intel_dp->color_range_auto = true;
5114 if (is_edp(intel_dp)) {
5115 drm_mode_create_scaling_mode_property(connector->dev);
5116 drm_object_attach_property(
5118 connector->dev->mode_config.scaling_mode_property,
5119 DRM_MODE_SCALE_ASPECT);
5120 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5124 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5126 intel_dp->panel_power_off_time = ktime_get_boottime();
5127 intel_dp->last_power_on = jiffies;
5128 intel_dp->last_backlight_off = jiffies;
5132 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
5133 struct intel_dp *intel_dp, struct edp_power_seq *seq)
5135 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5136 struct pps_registers regs;
5138 intel_pps_get_registers(dev_priv, intel_dp, ®s);
5140 /* Workaround: Need to write PP_CONTROL with the unlock key as
5141 * the very first thing. */
5142 pp_ctl = ironlake_get_pp_control(intel_dp);
5144 pp_on = I915_READ(regs.pp_on);
5145 pp_off = I915_READ(regs.pp_off);
5146 if (!IS_GEN9_LP(dev_priv)) {
5147 I915_WRITE(regs.pp_ctrl, pp_ctl);
5148 pp_div = I915_READ(regs.pp_div);
5151 /* Pull timing values out of registers */
5152 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5153 PANEL_POWER_UP_DELAY_SHIFT;
5155 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5156 PANEL_LIGHT_ON_DELAY_SHIFT;
5158 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5159 PANEL_LIGHT_OFF_DELAY_SHIFT;
5161 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5162 PANEL_POWER_DOWN_DELAY_SHIFT;
5164 if (IS_GEN9_LP(dev_priv)) {
5165 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5166 BXT_POWER_CYCLE_DELAY_SHIFT;
5168 seq->t11_t12 = (tmp - 1) * 1000;
5172 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5173 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5178 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5180 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5182 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5186 intel_pps_verify_state(struct drm_i915_private *dev_priv,
5187 struct intel_dp *intel_dp)
5189 struct edp_power_seq hw;
5190 struct edp_power_seq *sw = &intel_dp->pps_delays;
5192 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
5194 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5195 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5196 DRM_ERROR("PPS state mismatch\n");
5197 intel_pps_dump_state("sw", sw);
5198 intel_pps_dump_state("hw", &hw);
5203 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5204 struct intel_dp *intel_dp)
5206 struct drm_i915_private *dev_priv = to_i915(dev);
5207 struct edp_power_seq cur, vbt, spec,
5208 *final = &intel_dp->pps_delays;
5210 lockdep_assert_held(&dev_priv->pps_mutex);
5212 /* already initialized? */
5213 if (final->t11_t12 != 0)
5216 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5218 intel_pps_dump_state("cur", &cur);
5220 vbt = dev_priv->vbt.edp.pps;
5222 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5223 * our hw here, which are all in 100usec. */
5224 spec.t1_t3 = 210 * 10;
5225 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5226 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5227 spec.t10 = 500 * 10;
5228 /* This one is special and actually in units of 100ms, but zero
5229 * based in the hw (so we need to add 100 ms). But the sw vbt
5230 * table multiplies it with 1000 to make it in units of 100usec,
5232 spec.t11_t12 = (510 + 100) * 10;
5234 intel_pps_dump_state("vbt", &vbt);
5236 /* Use the max of the register settings and vbt. If both are
5237 * unset, fall back to the spec limits. */
5238 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5240 max(cur.field, vbt.field))
5241 assign_final(t1_t3);
5245 assign_final(t11_t12);
5248 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5249 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5250 intel_dp->backlight_on_delay = get_delay(t8);
5251 intel_dp->backlight_off_delay = get_delay(t9);
5252 intel_dp->panel_power_down_delay = get_delay(t10);
5253 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5256 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5257 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5258 intel_dp->panel_power_cycle_delay);
5260 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5261 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5264 * We override the HW backlight delays to 1 because we do manual waits
5265 * on them. For T8, even BSpec recommends doing it. For T9, if we
5266 * don't do this, we'll end up waiting for the backlight off delay
5267 * twice: once when we do the manual sleep, and once when we disable
5268 * the panel and wait for the PP_STATUS bit to become zero.
5275 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5276 struct intel_dp *intel_dp,
5277 bool force_disable_vdd)
5279 struct drm_i915_private *dev_priv = to_i915(dev);
5280 u32 pp_on, pp_off, pp_div, port_sel = 0;
5281 int div = dev_priv->rawclk_freq / 1000;
5282 struct pps_registers regs;
5283 enum port port = dp_to_dig_port(intel_dp)->port;
5284 const struct edp_power_seq *seq = &intel_dp->pps_delays;
5286 lockdep_assert_held(&dev_priv->pps_mutex);
5288 intel_pps_get_registers(dev_priv, intel_dp, ®s);
5291 * On some VLV machines the BIOS can leave the VDD
5292 * enabled even on power seqeuencers which aren't
5293 * hooked up to any port. This would mess up the
5294 * power domain tracking the first time we pick
5295 * one of these power sequencers for use since
5296 * edp_panel_vdd_on() would notice that the VDD was
5297 * already on and therefore wouldn't grab the power
5298 * domain reference. Disable VDD first to avoid this.
5299 * This also avoids spuriously turning the VDD on as
5300 * soon as the new power seqeuencer gets initialized.
5302 if (force_disable_vdd) {
5303 u32 pp = ironlake_get_pp_control(intel_dp);
5305 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5307 if (pp & EDP_FORCE_VDD)
5308 DRM_DEBUG_KMS("VDD already on, disabling first\n");
5310 pp &= ~EDP_FORCE_VDD;
5312 I915_WRITE(regs.pp_ctrl, pp);
5315 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5316 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5317 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5318 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5319 /* Compute the divisor for the pp clock, simply match the Bspec
5321 if (IS_GEN9_LP(dev_priv)) {
5322 pp_div = I915_READ(regs.pp_ctrl);
5323 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5324 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5325 << BXT_POWER_CYCLE_DELAY_SHIFT);
5327 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5328 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5329 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5332 /* Haswell doesn't have any port selection bits for the panel
5333 * power sequencer any more. */
5334 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5335 port_sel = PANEL_PORT_SELECT_VLV(port);
5336 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5338 port_sel = PANEL_PORT_SELECT_DPA;
5340 port_sel = PANEL_PORT_SELECT_DPD;
5345 I915_WRITE(regs.pp_on, pp_on);
5346 I915_WRITE(regs.pp_off, pp_off);
5347 if (IS_GEN9_LP(dev_priv))
5348 I915_WRITE(regs.pp_ctrl, pp_div);
5350 I915_WRITE(regs.pp_div, pp_div);
5352 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5353 I915_READ(regs.pp_on),
5354 I915_READ(regs.pp_off),
5355 IS_GEN9_LP(dev_priv) ?
5356 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5357 I915_READ(regs.pp_div));
5360 static void intel_dp_pps_init(struct drm_device *dev,
5361 struct intel_dp *intel_dp)
5363 struct drm_i915_private *dev_priv = to_i915(dev);
5365 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5366 vlv_initial_power_sequencer_setup(intel_dp);
5368 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5369 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
5374 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5375 * @dev_priv: i915 device
5376 * @crtc_state: a pointer to the active intel_crtc_state
5377 * @refresh_rate: RR to be programmed
5379 * This function gets called when refresh rate (RR) has to be changed from
5380 * one frequency to another. Switches can be between high and low RR
5381 * supported by the panel or to any other RR based on media playback (in
5382 * this case, RR value needs to be passed from user space).
5384 * The caller of this function needs to take a lock on dev_priv->drrs.
5386 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5387 struct intel_crtc_state *crtc_state,
5390 struct intel_encoder *encoder;
5391 struct intel_digital_port *dig_port = NULL;
5392 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5394 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5396 if (refresh_rate <= 0) {
5397 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5401 if (intel_dp == NULL) {
5402 DRM_DEBUG_KMS("DRRS not supported.\n");
5407 * FIXME: This needs proper synchronization with psr state for some
5408 * platforms that cannot have PSR and DRRS enabled at the same time.
5411 dig_port = dp_to_dig_port(intel_dp);
5412 encoder = &dig_port->base;
5413 intel_crtc = to_intel_crtc(encoder->base.crtc);
5416 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5420 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5421 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5425 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5427 index = DRRS_LOW_RR;
5429 if (index == dev_priv->drrs.refresh_rate_type) {
5431 "DRRS requested for previously set RR...ignoring\n");
5435 if (!crtc_state->base.active) {
5436 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5440 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5443 intel_dp_set_m_n(intel_crtc, M1_N1);
5446 intel_dp_set_m_n(intel_crtc, M2_N2);
5450 DRM_ERROR("Unsupported refreshrate type\n");
5452 } else if (INTEL_GEN(dev_priv) > 6) {
5453 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5456 val = I915_READ(reg);
5457 if (index > DRRS_HIGH_RR) {
5458 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5459 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5461 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5463 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5464 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5466 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5468 I915_WRITE(reg, val);
5471 dev_priv->drrs.refresh_rate_type = index;
5473 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5477 * intel_edp_drrs_enable - init drrs struct if supported
5478 * @intel_dp: DP struct
5479 * @crtc_state: A pointer to the active crtc state.
5481 * Initializes frontbuffer_bits and drrs.dp
5483 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5484 struct intel_crtc_state *crtc_state)
5486 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5487 struct drm_i915_private *dev_priv = to_i915(dev);
5489 if (!crtc_state->has_drrs) {
5490 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5494 mutex_lock(&dev_priv->drrs.mutex);
5495 if (WARN_ON(dev_priv->drrs.dp)) {
5496 DRM_ERROR("DRRS already enabled\n");
5500 dev_priv->drrs.busy_frontbuffer_bits = 0;
5502 dev_priv->drrs.dp = intel_dp;
5505 mutex_unlock(&dev_priv->drrs.mutex);
5509 * intel_edp_drrs_disable - Disable DRRS
5510 * @intel_dp: DP struct
5511 * @old_crtc_state: Pointer to old crtc_state.
5514 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5515 struct intel_crtc_state *old_crtc_state)
5517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5518 struct drm_i915_private *dev_priv = to_i915(dev);
5520 if (!old_crtc_state->has_drrs)
5523 mutex_lock(&dev_priv->drrs.mutex);
5524 if (!dev_priv->drrs.dp) {
5525 mutex_unlock(&dev_priv->drrs.mutex);
5529 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5530 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5531 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5533 dev_priv->drrs.dp = NULL;
5534 mutex_unlock(&dev_priv->drrs.mutex);
5536 cancel_delayed_work_sync(&dev_priv->drrs.work);
5539 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5541 struct drm_i915_private *dev_priv =
5542 container_of(work, typeof(*dev_priv), drrs.work.work);
5543 struct intel_dp *intel_dp;
5545 mutex_lock(&dev_priv->drrs.mutex);
5547 intel_dp = dev_priv->drrs.dp;
5553 * The delayed work can race with an invalidate hence we need to
5557 if (dev_priv->drrs.busy_frontbuffer_bits)
5560 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5561 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5563 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5564 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5568 mutex_unlock(&dev_priv->drrs.mutex);
5572 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5573 * @dev_priv: i915 device
5574 * @frontbuffer_bits: frontbuffer plane tracking bits
5576 * This function gets called everytime rendering on the given planes start.
5577 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5579 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5581 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5582 unsigned int frontbuffer_bits)
5584 struct drm_crtc *crtc;
5587 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5590 cancel_delayed_work(&dev_priv->drrs.work);
5592 mutex_lock(&dev_priv->drrs.mutex);
5593 if (!dev_priv->drrs.dp) {
5594 mutex_unlock(&dev_priv->drrs.mutex);
5598 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5599 pipe = to_intel_crtc(crtc)->pipe;
5601 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5602 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5604 /* invalidate means busy screen hence upclock */
5605 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5606 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5607 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5609 mutex_unlock(&dev_priv->drrs.mutex);
5613 * intel_edp_drrs_flush - Restart Idleness DRRS
5614 * @dev_priv: i915 device
5615 * @frontbuffer_bits: frontbuffer plane tracking bits
5617 * This function gets called every time rendering on the given planes has
5618 * completed or flip on a crtc is completed. So DRRS should be upclocked
5619 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5620 * if no other planes are dirty.
5622 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5624 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5625 unsigned int frontbuffer_bits)
5627 struct drm_crtc *crtc;
5630 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5633 cancel_delayed_work(&dev_priv->drrs.work);
5635 mutex_lock(&dev_priv->drrs.mutex);
5636 if (!dev_priv->drrs.dp) {
5637 mutex_unlock(&dev_priv->drrs.mutex);
5641 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5642 pipe = to_intel_crtc(crtc)->pipe;
5644 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5645 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5647 /* flush means busy screen hence upclock */
5648 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5649 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5650 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5653 * flush also means no more activity hence schedule downclock, if all
5654 * other fbs are quiescent too
5656 if (!dev_priv->drrs.busy_frontbuffer_bits)
5657 schedule_delayed_work(&dev_priv->drrs.work,
5658 msecs_to_jiffies(1000));
5659 mutex_unlock(&dev_priv->drrs.mutex);
5663 * DOC: Display Refresh Rate Switching (DRRS)
5665 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5666 * which enables swtching between low and high refresh rates,
5667 * dynamically, based on the usage scenario. This feature is applicable
5668 * for internal panels.
5670 * Indication that the panel supports DRRS is given by the panel EDID, which
5671 * would list multiple refresh rates for one resolution.
5673 * DRRS is of 2 types - static and seamless.
5674 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5675 * (may appear as a blink on screen) and is used in dock-undock scenario.
5676 * Seamless DRRS involves changing RR without any visual effect to the user
5677 * and can be used during normal system usage. This is done by programming
5678 * certain registers.
5680 * Support for static/seamless DRRS may be indicated in the VBT based on
5681 * inputs from the panel spec.
5683 * DRRS saves power by switching to low RR based on usage scenarios.
5685 * The implementation is based on frontbuffer tracking implementation. When
5686 * there is a disturbance on the screen triggered by user activity or a periodic
5687 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5688 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5691 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5692 * and intel_edp_drrs_flush() are called.
5694 * DRRS can be further extended to support other internal panels and also
5695 * the scenario of video playback wherein RR is set based on the rate
5696 * requested by userspace.
5700 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5701 * @intel_connector: eDP connector
5702 * @fixed_mode: preferred mode of panel
5704 * This function is called only once at driver load to initialize basic
5708 * Downclock mode if panel supports it, else return NULL.
5709 * DRRS support is determined by the presence of downclock mode (apart
5710 * from VBT setting).
5712 static struct drm_display_mode *
5713 intel_dp_drrs_init(struct intel_connector *intel_connector,
5714 struct drm_display_mode *fixed_mode)
5716 struct drm_connector *connector = &intel_connector->base;
5717 struct drm_device *dev = connector->dev;
5718 struct drm_i915_private *dev_priv = to_i915(dev);
5719 struct drm_display_mode *downclock_mode = NULL;
5721 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5722 mutex_init(&dev_priv->drrs.mutex);
5724 if (INTEL_GEN(dev_priv) <= 6) {
5725 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5729 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5730 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5734 downclock_mode = intel_find_panel_downclock
5735 (dev_priv, fixed_mode, connector);
5737 if (!downclock_mode) {
5738 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5742 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5744 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5745 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5746 return downclock_mode;
5749 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5750 struct intel_connector *intel_connector)
5752 struct drm_connector *connector = &intel_connector->base;
5753 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5754 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5755 struct drm_device *dev = intel_encoder->base.dev;
5756 struct drm_i915_private *dev_priv = to_i915(dev);
5757 struct drm_display_mode *fixed_mode = NULL;
5758 struct drm_display_mode *downclock_mode = NULL;
5760 struct drm_display_mode *scan;
5762 enum pipe pipe = INVALID_PIPE;
5764 if (!is_edp(intel_dp))
5768 * On IBX/CPT we may get here with LVDS already registered. Since the
5769 * driver uses the only internal power sequencer available for both
5770 * eDP and LVDS bail out early in this case to prevent interfering
5771 * with an already powered-on LVDS power sequencer.
5773 if (intel_get_lvds_encoder(dev)) {
5774 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5775 DRM_INFO("LVDS was detected, not registering eDP\n");
5782 intel_dp_init_panel_power_timestamps(intel_dp);
5783 intel_dp_pps_init(dev, intel_dp);
5784 intel_edp_panel_vdd_sanitize(intel_dp);
5786 pps_unlock(intel_dp);
5788 /* Cache DPCD and EDID for edp. */
5789 has_dpcd = intel_edp_init_dpcd(intel_dp);
5792 /* if this fails, presume the device is a ghost */
5793 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5797 mutex_lock(&dev->mode_config.mutex);
5798 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5800 if (drm_add_edid_modes(connector, edid)) {
5801 drm_mode_connector_update_edid_property(connector,
5803 drm_edid_to_eld(connector, edid);
5806 edid = ERR_PTR(-EINVAL);
5809 edid = ERR_PTR(-ENOENT);
5811 intel_connector->edid = edid;
5813 /* prefer fixed mode from EDID if available */
5814 list_for_each_entry(scan, &connector->probed_modes, head) {
5815 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5816 fixed_mode = drm_mode_duplicate(dev, scan);
5817 downclock_mode = intel_dp_drrs_init(
5818 intel_connector, fixed_mode);
5823 /* fallback to VBT if available for eDP */
5824 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5825 fixed_mode = drm_mode_duplicate(dev,
5826 dev_priv->vbt.lfp_lvds_vbt_mode);
5828 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5829 connector->display_info.width_mm = fixed_mode->width_mm;
5830 connector->display_info.height_mm = fixed_mode->height_mm;
5833 mutex_unlock(&dev->mode_config.mutex);
5835 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5836 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5837 register_reboot_notifier(&intel_dp->edp_notifier);
5840 * Figure out the current pipe for the initial backlight setup.
5841 * If the current pipe isn't valid, try the PPS pipe, and if that
5842 * fails just assume pipe A.
5844 pipe = vlv_active_pipe(intel_dp);
5846 if (pipe != PIPE_A && pipe != PIPE_B)
5847 pipe = intel_dp->pps_pipe;
5849 if (pipe != PIPE_A && pipe != PIPE_B)
5852 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5856 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5857 intel_connector->panel.backlight.power = intel_edp_backlight_power;
5858 intel_panel_setup_backlight(connector, pipe);
5863 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5865 * vdd might still be enabled do to the delayed vdd off.
5866 * Make sure vdd is actually turned off here.
5869 edp_panel_vdd_off_sync(intel_dp);
5870 pps_unlock(intel_dp);
5875 /* Set up the hotplug pin and aux power domain. */
5877 intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
5879 struct intel_encoder *encoder = &intel_dig_port->base;
5880 struct intel_dp *intel_dp = &intel_dig_port->dp;
5882 switch (intel_dig_port->port) {
5884 encoder->hpd_pin = HPD_PORT_A;
5885 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A;
5888 encoder->hpd_pin = HPD_PORT_B;
5889 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B;
5892 encoder->hpd_pin = HPD_PORT_C;
5893 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C;
5896 encoder->hpd_pin = HPD_PORT_D;
5897 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5900 encoder->hpd_pin = HPD_PORT_E;
5902 /* FIXME: Check VBT for actual wiring of PORT E */
5903 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5906 MISSING_CASE(intel_dig_port->port);
5911 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5912 struct intel_connector *intel_connector)
5914 struct drm_connector *connector = &intel_connector->base;
5915 struct intel_dp *intel_dp = &intel_dig_port->dp;
5916 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5917 struct drm_device *dev = intel_encoder->base.dev;
5918 struct drm_i915_private *dev_priv = to_i915(dev);
5919 enum port port = intel_dig_port->port;
5922 if (WARN(intel_dig_port->max_lanes < 1,
5923 "Not enough lanes (%d) for DP on port %c\n",
5924 intel_dig_port->max_lanes, port_name(port)))
5927 intel_dp->reset_link_params = true;
5928 intel_dp->pps_pipe = INVALID_PIPE;
5929 intel_dp->active_pipe = INVALID_PIPE;
5931 /* intel_dp vfuncs */
5932 if (INTEL_GEN(dev_priv) >= 9)
5933 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5934 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5935 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5936 else if (HAS_PCH_SPLIT(dev_priv))
5937 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5939 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5941 if (INTEL_GEN(dev_priv) >= 9)
5942 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5944 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5946 if (HAS_DDI(dev_priv))
5947 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5949 /* Preserve the current hw state. */
5950 intel_dp->DP = I915_READ(intel_dp->output_reg);
5951 intel_dp->attached_connector = intel_connector;
5953 if (intel_dp_is_edp(dev_priv, port))
5954 type = DRM_MODE_CONNECTOR_eDP;
5956 type = DRM_MODE_CONNECTOR_DisplayPort;
5958 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5959 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5962 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5963 * for DP the encoder type can be set by the caller to
5964 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5966 if (type == DRM_MODE_CONNECTOR_eDP)
5967 intel_encoder->type = INTEL_OUTPUT_EDP;
5969 /* eDP only on port B and/or C on vlv/chv */
5970 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
5971 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5974 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5975 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5978 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5979 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5981 connector->interlace_allowed = true;
5982 connector->doublescan_allowed = 0;
5984 intel_dp_init_connector_port_info(intel_dig_port);
5986 intel_dp_aux_init(intel_dp);
5988 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5989 edp_panel_vdd_work);
5991 intel_connector_attach_encoder(intel_connector, intel_encoder);
5993 if (HAS_DDI(dev_priv))
5994 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5996 intel_connector->get_hw_state = intel_connector_get_hw_state;
5998 /* init MST on ports that can support it */
5999 if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
6000 (port == PORT_B || port == PORT_C || port == PORT_D))
6001 intel_dp_mst_encoder_init(intel_dig_port,
6002 intel_connector->base.base.id);
6004 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6005 intel_dp_aux_fini(intel_dp);
6006 intel_dp_mst_encoder_cleanup(intel_dig_port);
6010 intel_dp_add_properties(intel_dp, connector);
6012 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6013 * 0xd. Failure to do so will result in spurious interrupts being
6014 * generated on the port when a cable is not attached.
6016 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6017 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6018 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6024 drm_connector_cleanup(connector);
6029 bool intel_dp_init(struct drm_i915_private *dev_priv,
6030 i915_reg_t output_reg,
6033 struct intel_digital_port *intel_dig_port;
6034 struct intel_encoder *intel_encoder;
6035 struct drm_encoder *encoder;
6036 struct intel_connector *intel_connector;
6038 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6039 if (!intel_dig_port)
6042 intel_connector = intel_connector_alloc();
6043 if (!intel_connector)
6044 goto err_connector_alloc;
6046 intel_encoder = &intel_dig_port->base;
6047 encoder = &intel_encoder->base;
6049 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6050 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6051 "DP %c", port_name(port)))
6052 goto err_encoder_init;
6054 intel_encoder->compute_config = intel_dp_compute_config;
6055 intel_encoder->disable = intel_disable_dp;
6056 intel_encoder->get_hw_state = intel_dp_get_hw_state;
6057 intel_encoder->get_config = intel_dp_get_config;
6058 intel_encoder->suspend = intel_dp_encoder_suspend;
6059 if (IS_CHERRYVIEW(dev_priv)) {
6060 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6061 intel_encoder->pre_enable = chv_pre_enable_dp;
6062 intel_encoder->enable = vlv_enable_dp;
6063 intel_encoder->post_disable = chv_post_disable_dp;
6064 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6065 } else if (IS_VALLEYVIEW(dev_priv)) {
6066 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6067 intel_encoder->pre_enable = vlv_pre_enable_dp;
6068 intel_encoder->enable = vlv_enable_dp;
6069 intel_encoder->post_disable = vlv_post_disable_dp;
6071 intel_encoder->pre_enable = g4x_pre_enable_dp;
6072 intel_encoder->enable = g4x_enable_dp;
6073 if (INTEL_GEN(dev_priv) >= 5)
6074 intel_encoder->post_disable = ilk_post_disable_dp;
6077 intel_dig_port->port = port;
6078 intel_dig_port->dp.output_reg = output_reg;
6079 intel_dig_port->max_lanes = 4;
6081 intel_encoder->type = INTEL_OUTPUT_DP;
6082 intel_encoder->power_domain = intel_port_to_power_domain(port);
6083 if (IS_CHERRYVIEW(dev_priv)) {
6085 intel_encoder->crtc_mask = 1 << 2;
6087 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6089 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6091 intel_encoder->cloneable = 0;
6092 intel_encoder->port = port;
6094 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6095 dev_priv->hotplug.irq_port[port] = intel_dig_port;
6097 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6098 goto err_init_connector;
6103 drm_encoder_cleanup(encoder);
6105 kfree(intel_connector);
6106 err_connector_alloc:
6107 kfree(intel_dig_port);
6111 void intel_dp_mst_suspend(struct drm_device *dev)
6113 struct drm_i915_private *dev_priv = to_i915(dev);
6117 for (i = 0; i < I915_MAX_PORTS; i++) {
6118 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6120 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6123 if (intel_dig_port->dp.is_mst)
6124 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6128 void intel_dp_mst_resume(struct drm_device *dev)
6130 struct drm_i915_private *dev_priv = to_i915(dev);
6133 for (i = 0; i < I915_MAX_PORTS; i++) {
6134 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6137 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6140 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6142 intel_dp_check_mst_status(&intel_dig_port->dp);