2 * Copyright © 2014-2016 Intel Corporation
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21 * DEALINGS IN THE SOFTWARE.
24 #include "intel_drv.h"
29 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
30 * ports. DPIO is the name given to such a display PHY. These PHYs
31 * don't follow the standard programming model using direct MMIO
32 * registers, and instead their registers must be accessed trough IOSF
33 * sideband. VLV has one such PHY for driving ports B and C, and CHV
34 * adds another PHY for driving port D. Each PHY responds to specific
37 * Each display PHY is made up of one or two channels. Each channel
38 * houses a common lane part which contains the PLL and other common
39 * logic. CH0 common lane also contains the IOSF-SB logic for the
40 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
41 * must be running when any DPIO registers are accessed.
43 * In addition to having their own registers, the PHYs are also
44 * controlled through some dedicated signals from the display
45 * controller. These include PLL reference clock enable, PLL enable,
46 * and CRI clock selection, for example.
48 * Eeach channel also has two splines (also called data lanes), and
49 * each spline is made up of one Physical Access Coding Sub-Layer
50 * (PCS) block and two TX lanes. So each channel has two PCS blocks
51 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
52 * data/clock pairs depending on the output type.
54 * Additionally the PHY also contains an AUX lane with AUX blocks
55 * for each channel. This is used for DP AUX communication, but
56 * this fact isn't really relevant for the driver since AUX is
57 * controlled from the display controller side. No DPIO registers
58 * need to be accessed during AUX communication,
60 * Generally on VLV/CHV the common lane corresponds to the pipe and
61 * the spline (PCS/TX) corresponds to the port.
63 * For dual channel PHY (VLV/CHV):
65 * pipe A == CMN/PLL/REF CH0
67 * pipe B == CMN/PLL/REF CH1
69 * port B == PCS/TX CH0
71 * port C == PCS/TX CH1
73 * This is especially important when we cross the streams
74 * ie. drive port B with pipe B, or port C with pipe A.
76 * For single channel PHY (CHV):
78 * pipe C == CMN/PLL/REF CH0
80 * port D == PCS/TX CH0
82 * On BXT the entire PHY channel corresponds to the port. That means
83 * the PLL is also now associated with the port rather than the pipe,
84 * and so the clock needs to be routed to the appropriate transcoder.
85 * Port A PLL is directly connected to transcoder EDP and port B/C
86 * PLLs can be routed to any transcoder A/B/C.
88 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
89 * digital port D (CHV) or port A (BXT). ::
92 * Dual channel PHY (VLV/CHV/BXT)
93 * ---------------------------------
95 * | CMN/PLL/REF | CMN/PLL/REF |
96 * |---------------|---------------| Display PHY
97 * | PCS01 | PCS23 | PCS01 | PCS23 |
98 * |-------|-------|-------|-------|
99 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
100 * ---------------------------------
101 * | DDI0 | DDI1 | DP/HDMI ports
102 * ---------------------------------
104 * Single channel PHY (CHV/BXT)
108 * |---------------| Display PHY
113 * | DDI2 | DP/HDMI port
118 * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
120 struct bxt_ddi_phy_info {
122 * @dual_channel: true if this phy has a second channel.
127 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
128 * Otherwise the GRC value will be copied from the phy indicated by
131 enum dpio_phy rcomp_phy;
134 * @channel: struct containing per channel information.
138 * @port: which port maps to this channel.
144 static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
146 .dual_channel = true,
147 .rcomp_phy = DPIO_PHY1,
150 [DPIO_CH0] = { .port = PORT_B },
151 [DPIO_CH1] = { .port = PORT_C },
155 .dual_channel = false,
159 [DPIO_CH0] = { .port = PORT_A },
164 static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)
166 return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) |
167 BIT(phy_info->channel[DPIO_CH0].port);
170 void bxt_port_to_phy_channel(enum port port,
171 enum dpio_phy *phy, enum dpio_channel *ch)
173 const struct bxt_ddi_phy_info *phy_info;
176 for (i = 0; i < ARRAY_SIZE(bxt_ddi_phy_info); i++) {
177 phy_info = &bxt_ddi_phy_info[i];
179 if (port == phy_info->channel[DPIO_CH0].port) {
185 if (phy_info->dual_channel &&
186 port == phy_info->channel[DPIO_CH1].port) {
193 WARN(1, "PHY not found for PORT %c", port_name(port));
198 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
199 enum port port, u32 margin, u32 scale,
200 u32 enable, u32 deemphasis)
204 enum dpio_channel ch;
206 bxt_port_to_phy_channel(port, &phy, &ch);
209 * While we write to the group register to program all lanes at once we
210 * can read only lane registers and we pick lanes 0/1 for that.
212 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
213 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
214 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
216 val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch));
217 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
218 val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT;
219 I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val);
221 val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch));
222 val &= ~SCALE_DCOMP_METHOD;
224 val |= SCALE_DCOMP_METHOD;
226 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
227 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
229 I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val);
231 val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch));
233 val |= deemphasis << DEEMPH_SHIFT;
234 I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val);
236 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
237 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
238 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
241 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
244 const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
247 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
250 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
251 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
252 DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
258 if (phy_info->rcomp_phy == -1 &&
259 !(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE)) {
260 DRM_DEBUG_DRIVER("DDI PHY %d powered, but GRC isn't done\n",
266 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
267 DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
273 for_each_port_masked(port, bxt_phy_port_mask(phy_info)) {
274 u32 tmp = I915_READ(BXT_PHY_CTL(port));
276 if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
277 DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
278 "for port %c powered down "
280 phy, port_name(port), tmp);
289 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
291 u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
293 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
296 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
299 if (intel_wait_for_register(dev_priv,
300 BXT_PORT_REF_DW3(phy),
303 DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
306 static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
309 const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
312 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
313 /* Still read out the GRC value for state verification */
314 if (phy_info->rcomp_phy != -1)
315 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
317 if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
318 DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
319 "won't reprogram it\n", phy);
324 DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
325 "force reprogramming it\n", phy);
328 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
329 val |= GT_DISPLAY_POWER_ON(phy);
330 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
333 * The PHY registers start out inaccessible and respond to reads with
334 * all 1s. Eventually they become accessible as they power up, then
335 * the reserved bit will give the default 0. Poll on the reserved bit
336 * becoming 0 to find when the PHY is accessible.
337 * HW team confirmed that the time to reach phypowergood status is
338 * anywhere between 50 us and 100us.
340 if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
341 (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
342 DRM_ERROR("timeout during PHY%d power on\n", phy);
345 /* Program PLL Rcomp code offset */
346 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
347 val &= ~IREF0RC_OFFSET_MASK;
348 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
349 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
351 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
352 val &= ~IREF1RC_OFFSET_MASK;
353 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
354 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
356 /* Program power gating */
357 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
358 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
360 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
362 if (phy_info->dual_channel) {
363 val = I915_READ(BXT_PORT_CL2CM_DW6(phy));
364 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
365 I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
368 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
369 val &= ~OCL2_LDOFUSE_PWR_DIS;
371 * On PHY1 disable power on the second channel, since no port is
372 * connected there. On PHY0 both channels have a port, so leave it
374 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
375 * power down the second channel on PHY0 as well.
377 * FIXME: Clarify programming of the following, the register is
378 * read-only with bit 6 fixed at 0 at least in stepping A.
380 if (!phy_info->dual_channel)
381 val |= OCL2_LDOFUSE_PWR_DIS;
382 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
384 if (phy_info->rcomp_phy != -1) {
387 * PHY0 isn't connected to an RCOMP resistor so copy over
388 * the corresponding calibrated value from PHY1, and disable
389 * the automatic calibration on PHY0.
391 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
392 phy_info->rcomp_phy);
393 grc_code = val << GRC_CODE_FAST_SHIFT |
394 val << GRC_CODE_SLOW_SHIFT |
396 I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code);
398 val = I915_READ(BXT_PORT_REF_DW8(phy));
399 val |= GRC_DIS | GRC_RDY_OVRD;
400 I915_WRITE(BXT_PORT_REF_DW8(phy), val);
403 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
404 val |= COMMON_RESET_DIS;
405 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
407 if (phy_info->rcomp_phy == -1)
408 bxt_phy_wait_grc_done(dev_priv, phy);
412 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
416 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
417 val &= ~COMMON_RESET_DIS;
418 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
420 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
421 val &= ~GT_DISPLAY_POWER_ON(phy);
422 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
425 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
427 const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
428 enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
431 lockdep_assert_held(&dev_priv->power_domains.lock);
433 if (rcomp_phy != -1) {
434 was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy);
437 * We need to copy the GRC calibration value from rcomp_phy,
438 * so make sure it's powered up.
441 _bxt_ddi_phy_init(dev_priv, rcomp_phy);
444 _bxt_ddi_phy_init(dev_priv, phy);
446 if (rcomp_phy != -1 && !was_enabled)
447 bxt_ddi_phy_uninit(dev_priv, phy_info->rcomp_phy);
450 static bool __printf(6, 7)
451 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
452 i915_reg_t reg, u32 mask, u32 expected,
453 const char *reg_fmt, ...)
455 struct va_format vaf;
459 val = I915_READ(reg);
460 if ((val & mask) == expected)
463 va_start(args, reg_fmt);
467 DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
468 "current %08x, expected %08x (mask %08x)\n",
469 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
477 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
480 const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
484 #define _CHK(reg, mask, exp, fmt, ...) \
485 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
488 if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
493 /* PLL Rcomp code offset */
494 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
495 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
496 "BXT_PORT_CL1CM_DW9(%d)", phy);
497 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
498 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
499 "BXT_PORT_CL1CM_DW10(%d)", phy);
502 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
503 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
504 "BXT_PORT_CL1CM_DW28(%d)", phy);
506 if (phy_info->dual_channel)
507 ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
508 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
509 "BXT_PORT_CL2CM_DW6(%d)", phy);
512 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
513 * at least on stepping A this bit is read-only and fixed at 0.
516 if (phy_info->rcomp_phy != -1) {
517 u32 grc_code = dev_priv->bxt_phy_grc;
519 grc_code = grc_code << GRC_CODE_FAST_SHIFT |
520 grc_code << GRC_CODE_SLOW_SHIFT |
522 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
524 ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
525 "BXT_PORT_REF_DW6(%d)", phy);
527 mask = GRC_DIS | GRC_RDY_OVRD;
528 ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
529 "BXT_PORT_REF_DW8(%d)", phy);
537 bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
540 switch (lane_count) {
544 return BIT(2) | BIT(0);
546 return BIT(3) | BIT(2) | BIT(0);
548 MISSING_CASE(lane_count);
554 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
555 uint8_t lane_lat_optim_mask)
557 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
558 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
559 enum port port = dport->port;
561 enum dpio_channel ch;
564 bxt_port_to_phy_channel(port, &phy, &ch);
566 for (lane = 0; lane < 4; lane++) {
567 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
570 * Note that on CHV this flag is called UPAR, but has
573 val &= ~LATENCY_OPTIM;
574 if (lane_lat_optim_mask & BIT(lane))
575 val |= LATENCY_OPTIM;
577 I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val);
582 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
584 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
585 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
586 enum port port = dport->port;
588 enum dpio_channel ch;
592 bxt_port_to_phy_channel(port, &phy, &ch);
595 for (lane = 0; lane < 4; lane++) {
596 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
598 if (val & LATENCY_OPTIM)
606 void chv_set_phy_signal_level(struct intel_encoder *encoder,
607 u32 deemph_reg_value, u32 margin_reg_value,
608 bool uniq_trans_scale)
610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
611 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
612 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
613 enum dpio_channel ch = vlv_dport_to_channel(dport);
614 enum pipe pipe = intel_crtc->pipe;
618 mutex_lock(&dev_priv->sb_lock);
620 /* Clear calc init */
621 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
622 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
623 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
624 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
625 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
627 if (intel_crtc->config->lane_count > 2) {
628 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
629 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
630 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
631 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
632 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
635 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
636 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
637 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
638 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
640 if (intel_crtc->config->lane_count > 2) {
641 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
642 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
643 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
644 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
647 /* Program swing deemph */
648 for (i = 0; i < intel_crtc->config->lane_count; i++) {
649 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
650 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
651 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
652 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
655 /* Program swing margin */
656 for (i = 0; i < intel_crtc->config->lane_count; i++) {
657 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
659 val &= ~DPIO_SWING_MARGIN000_MASK;
660 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
663 * Supposedly this value shouldn't matter when unique transition
664 * scale is disabled, but in fact it does matter. Let's just
665 * always program the same value and hope it's OK.
667 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
668 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
670 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
674 * The document said it needs to set bit 27 for ch0 and bit 26
675 * for ch1. Might be a typo in the doc.
676 * For now, for this unique transition scale selection, set bit
677 * 27 for ch0 and ch1.
679 for (i = 0; i < intel_crtc->config->lane_count; i++) {
680 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
681 if (uniq_trans_scale)
682 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
684 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
685 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
688 /* Start swing calculation */
689 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
690 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
691 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
693 if (intel_crtc->config->lane_count > 2) {
694 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
695 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
696 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
699 mutex_unlock(&dev_priv->sb_lock);
703 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
706 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
707 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
708 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
709 enum pipe pipe = crtc->pipe;
712 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
714 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
716 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
717 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
719 if (crtc->config->lane_count > 2) {
720 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
722 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
724 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
725 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
728 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
729 val |= CHV_PCS_REQ_SOFTRESET_EN;
731 val &= ~DPIO_PCS_CLK_SOFT_RESET;
733 val |= DPIO_PCS_CLK_SOFT_RESET;
734 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
736 if (crtc->config->lane_count > 2) {
737 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
738 val |= CHV_PCS_REQ_SOFTRESET_EN;
740 val &= ~DPIO_PCS_CLK_SOFT_RESET;
742 val |= DPIO_PCS_CLK_SOFT_RESET;
743 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
747 void chv_phy_pre_pll_enable(struct intel_encoder *encoder)
749 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
750 struct drm_device *dev = encoder->base.dev;
751 struct drm_i915_private *dev_priv = to_i915(dev);
752 struct intel_crtc *intel_crtc =
753 to_intel_crtc(encoder->base.crtc);
754 enum dpio_channel ch = vlv_dport_to_channel(dport);
755 enum pipe pipe = intel_crtc->pipe;
756 unsigned int lane_mask =
757 intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
761 * Must trick the second common lane into life.
762 * Otherwise we can't even access the PLL.
764 if (ch == DPIO_CH0 && pipe == PIPE_B)
765 dport->release_cl2_override =
766 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
768 chv_phy_powergate_lanes(encoder, true, lane_mask);
770 mutex_lock(&dev_priv->sb_lock);
772 /* Assert data lane reset */
773 chv_data_lane_soft_reset(encoder, true);
775 /* program left/right clock distribution */
776 if (pipe != PIPE_B) {
777 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
778 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
780 val |= CHV_BUFLEFTENA1_FORCE;
782 val |= CHV_BUFRIGHTENA1_FORCE;
783 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
785 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
786 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
788 val |= CHV_BUFLEFTENA2_FORCE;
790 val |= CHV_BUFRIGHTENA2_FORCE;
791 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
794 /* program clock channel usage */
795 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
796 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
798 val &= ~CHV_PCS_USEDCLKCHANNEL;
800 val |= CHV_PCS_USEDCLKCHANNEL;
801 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
803 if (intel_crtc->config->lane_count > 2) {
804 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
805 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
807 val &= ~CHV_PCS_USEDCLKCHANNEL;
809 val |= CHV_PCS_USEDCLKCHANNEL;
810 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
814 * This a a bit weird since generally CL
815 * matches the pipe, but here we need to
816 * pick the CL based on the port.
818 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
820 val &= ~CHV_CMN_USEDCLKCHANNEL;
822 val |= CHV_CMN_USEDCLKCHANNEL;
823 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
825 mutex_unlock(&dev_priv->sb_lock);
828 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder)
830 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
831 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
832 struct drm_device *dev = encoder->base.dev;
833 struct drm_i915_private *dev_priv = to_i915(dev);
834 struct intel_crtc *intel_crtc =
835 to_intel_crtc(encoder->base.crtc);
836 enum dpio_channel ch = vlv_dport_to_channel(dport);
837 int pipe = intel_crtc->pipe;
838 int data, i, stagger;
841 mutex_lock(&dev_priv->sb_lock);
843 /* allow hardware to manage TX FIFO reset source */
844 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
845 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
846 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
848 if (intel_crtc->config->lane_count > 2) {
849 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
850 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
851 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
854 /* Program Tx lane latency optimal setting*/
855 for (i = 0; i < intel_crtc->config->lane_count; i++) {
856 /* Set the upar bit */
857 if (intel_crtc->config->lane_count == 1)
860 data = (i == 1) ? 0x0 : 0x1;
861 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
862 data << DPIO_UPAR_SHIFT);
865 /* Data lane stagger programming */
866 if (intel_crtc->config->port_clock > 270000)
868 else if (intel_crtc->config->port_clock > 135000)
870 else if (intel_crtc->config->port_clock > 67500)
872 else if (intel_crtc->config->port_clock > 33750)
877 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
878 val |= DPIO_TX2_STAGGER_MASK(0x1f);
879 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
881 if (intel_crtc->config->lane_count > 2) {
882 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
883 val |= DPIO_TX2_STAGGER_MASK(0x1f);
884 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
887 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
888 DPIO_LANESTAGGER_STRAP(stagger) |
889 DPIO_LANESTAGGER_STRAP_OVRD |
890 DPIO_TX1_STAGGER_MASK(0x1f) |
891 DPIO_TX1_STAGGER_MULT(6) |
892 DPIO_TX2_STAGGER_MULT(0));
894 if (intel_crtc->config->lane_count > 2) {
895 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
896 DPIO_LANESTAGGER_STRAP(stagger) |
897 DPIO_LANESTAGGER_STRAP_OVRD |
898 DPIO_TX1_STAGGER_MASK(0x1f) |
899 DPIO_TX1_STAGGER_MULT(7) |
900 DPIO_TX2_STAGGER_MULT(5));
903 /* Deassert data lane reset */
904 chv_data_lane_soft_reset(encoder, false);
906 mutex_unlock(&dev_priv->sb_lock);
909 void chv_phy_release_cl2_override(struct intel_encoder *encoder)
911 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
912 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
914 if (dport->release_cl2_override) {
915 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
916 dport->release_cl2_override = false;
920 void chv_phy_post_pll_disable(struct intel_encoder *encoder)
922 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
923 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
926 mutex_lock(&dev_priv->sb_lock);
928 /* disable left/right clock distribution */
929 if (pipe != PIPE_B) {
930 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
931 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
932 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
934 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
935 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
936 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
939 mutex_unlock(&dev_priv->sb_lock);
942 * Leave the power down bit cleared for at least one
943 * lane so that chv_powergate_phy_ch() will power
944 * on something when the channel is otherwise unused.
945 * When the port is off and the override is removed
946 * the lanes power down anyway, so otherwise it doesn't
947 * really matter what the state of power down bits is
950 chv_phy_powergate_lanes(encoder, false, 0x0);
953 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
954 u32 demph_reg_value, u32 preemph_reg_value,
955 u32 uniqtranscale_reg_value, u32 tx3_demph)
957 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
958 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
959 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
960 enum dpio_channel port = vlv_dport_to_channel(dport);
961 int pipe = intel_crtc->pipe;
963 mutex_lock(&dev_priv->sb_lock);
964 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
965 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
966 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
967 uniqtranscale_reg_value);
968 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
971 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
973 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
974 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
975 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
976 mutex_unlock(&dev_priv->sb_lock);
979 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder)
981 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
982 struct drm_device *dev = encoder->base.dev;
983 struct drm_i915_private *dev_priv = to_i915(dev);
984 struct intel_crtc *intel_crtc =
985 to_intel_crtc(encoder->base.crtc);
986 enum dpio_channel port = vlv_dport_to_channel(dport);
987 int pipe = intel_crtc->pipe;
989 /* Program Tx lane resets to default */
990 mutex_lock(&dev_priv->sb_lock);
991 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
992 DPIO_PCS_TX_LANE2_RESET |
993 DPIO_PCS_TX_LANE1_RESET);
994 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
995 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
996 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
997 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
998 DPIO_PCS_CLK_SOFT_RESET);
1000 /* Fix up inter-pair skew failure */
1001 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1002 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1003 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1004 mutex_unlock(&dev_priv->sb_lock);
1007 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder)
1009 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1010 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1011 struct drm_device *dev = encoder->base.dev;
1012 struct drm_i915_private *dev_priv = to_i915(dev);
1013 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1014 enum dpio_channel port = vlv_dport_to_channel(dport);
1015 int pipe = intel_crtc->pipe;
1018 mutex_lock(&dev_priv->sb_lock);
1020 /* Enable clock channels for this port */
1021 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1028 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1030 /* Program lane clock */
1031 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1032 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1034 mutex_unlock(&dev_priv->sb_lock);
1037 void vlv_phy_reset_lanes(struct intel_encoder *encoder)
1039 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1040 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1041 struct intel_crtc *intel_crtc =
1042 to_intel_crtc(encoder->base.crtc);
1043 enum dpio_channel port = vlv_dport_to_channel(dport);
1044 int pipe = intel_crtc->pipe;
1046 mutex_lock(&dev_priv->sb_lock);
1047 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1048 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1049 mutex_unlock(&dev_priv->sb_lock);