2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_encoder.h>
36 #include <drm/drm_fb_helper.h>
37 #include <drm/drm_dp_dual_mode_helper.h>
38 #include <drm/drm_dp_mst_helper.h>
39 #include <drm/drm_rect.h>
40 #include <drm/drm_atomic.h>
43 * _wait_for - magic (register) wait macro
45 * Does the right thing for modeset paths when run under kdgb or similar atomic
46 * contexts. Note that it's important that we check the condition again after
47 * having timed out, since the timeout could be due to preemption or similar and
48 * we've never had a chance to check the condition before the timeout.
50 * TODO: When modesetting has fully transitioned to atomic, the below
51 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
54 #define _wait_for(COND, US, W) ({ \
55 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
58 bool expired__ = time_after(jiffies, timeout__); \
67 if ((W) && drm_can_sleep()) { \
68 usleep_range((W), (W)*2); \
76 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
78 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
79 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
80 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
82 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
85 #define _wait_for_atomic(COND, US, ATOMIC) \
87 int cpu, ret, timeout = (US) * 1000; \
89 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
90 BUILD_BUG_ON((US) > 50000); \
93 cpu = smp_processor_id(); \
95 base = local_clock(); \
97 u64 now = local_clock(); \
104 if (now - base >= timeout) { \
111 if (unlikely(cpu != smp_processor_id())) { \
112 timeout -= now - base; \
113 cpu = smp_processor_id(); \
114 base = local_clock(); \
121 #define wait_for_us(COND, US) \
124 BUILD_BUG_ON(!__builtin_constant_p(US)); \
126 ret__ = _wait_for((COND), (US), 10); \
128 ret__ = _wait_for_atomic((COND), (US), 0); \
132 #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000, 1)
133 #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US), 1)
135 #define KHz(x) (1000 * (x))
136 #define MHz(x) KHz(1000 * (x))
139 * Display related stuff
142 /* store information about an Ixxx DVO */
143 /* The i830->i865 use multiple DVOs with multiple i2cs */
144 /* the i915, i945 have a single sDVO i2c bus - which is different */
145 #define MAX_OUTPUTS 6
146 /* maximum connectors per crtcs in the mode set */
148 /* Maximum cursor sizes */
149 #define GEN2_CURSOR_WIDTH 64
150 #define GEN2_CURSOR_HEIGHT 64
151 #define MAX_CURSOR_WIDTH 256
152 #define MAX_CURSOR_HEIGHT 256
154 #define INTEL_I2C_BUS_DVO 1
155 #define INTEL_I2C_BUS_SDVO 2
157 /* these are outputs from the chip - integrated only
158 external chips are via DVO or SDVO output */
159 enum intel_output_type {
160 INTEL_OUTPUT_UNUSED = 0,
161 INTEL_OUTPUT_ANALOG = 1,
162 INTEL_OUTPUT_DVO = 2,
163 INTEL_OUTPUT_SDVO = 3,
164 INTEL_OUTPUT_LVDS = 4,
165 INTEL_OUTPUT_TVOUT = 5,
166 INTEL_OUTPUT_HDMI = 6,
168 INTEL_OUTPUT_EDP = 8,
169 INTEL_OUTPUT_DSI = 9,
170 INTEL_OUTPUT_UNKNOWN = 10,
171 INTEL_OUTPUT_DP_MST = 11,
174 #define INTEL_DVO_CHIP_NONE 0
175 #define INTEL_DVO_CHIP_LVDS 1
176 #define INTEL_DVO_CHIP_TMDS 2
177 #define INTEL_DVO_CHIP_TVOUT 4
179 #define INTEL_DSI_VIDEO_MODE 0
180 #define INTEL_DSI_COMMAND_MODE 1
182 struct intel_framebuffer {
183 struct drm_framebuffer base;
184 struct drm_i915_gem_object *obj;
185 struct intel_rotation_info rot_info;
187 /* for each plane in the normal GTT view */
191 /* for each plane in the rotated GTT view */
194 unsigned int pitch; /* pixels */
199 struct drm_fb_helper helper;
200 struct intel_framebuffer *fb;
201 struct i915_vma *vma;
202 async_cookie_t cookie;
206 struct intel_encoder {
207 struct drm_encoder base;
209 enum intel_output_type type;
211 unsigned int cloneable;
212 void (*hot_plug)(struct intel_encoder *);
213 bool (*compute_config)(struct intel_encoder *,
214 struct intel_crtc_state *,
215 struct drm_connector_state *);
216 void (*pre_pll_enable)(struct intel_encoder *,
217 struct intel_crtc_state *,
218 struct drm_connector_state *);
219 void (*pre_enable)(struct intel_encoder *,
220 struct intel_crtc_state *,
221 struct drm_connector_state *);
222 void (*enable)(struct intel_encoder *,
223 struct intel_crtc_state *,
224 struct drm_connector_state *);
225 void (*disable)(struct intel_encoder *,
226 struct intel_crtc_state *,
227 struct drm_connector_state *);
228 void (*post_disable)(struct intel_encoder *,
229 struct intel_crtc_state *,
230 struct drm_connector_state *);
231 void (*post_pll_disable)(struct intel_encoder *,
232 struct intel_crtc_state *,
233 struct drm_connector_state *);
234 /* Read out the current hw state of this connector, returning true if
235 * the encoder is active. If the encoder is enabled it also set the pipe
236 * it is connected to in the pipe parameter. */
237 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
238 /* Reconstructs the equivalent mode flags for the current hardware
239 * state. This must be called _after_ display->get_pipe_config has
240 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
241 * be set correctly before calling this function. */
242 void (*get_config)(struct intel_encoder *,
243 struct intel_crtc_state *pipe_config);
245 * Called during system suspend after all pending requests for the
246 * encoder are flushed (for example for DP AUX transactions) and
247 * device interrupts are disabled.
249 void (*suspend)(struct intel_encoder *);
251 enum hpd_pin hpd_pin;
252 /* for communication with audio component; protected by av_mutex */
253 const struct drm_connector *audio_connector;
257 struct drm_display_mode *fixed_mode;
258 struct drm_display_mode *downclock_mode;
268 bool combination_mode; /* gen 2/4 only */
270 bool alternate_pwm_increment; /* lpt+ */
273 bool util_pin_active_low; /* bxt+ */
274 u8 controller; /* bxt+ only */
275 struct pwm_device *pwm;
277 struct backlight_device *device;
279 /* Connector and platform specific backlight functions */
280 int (*setup)(struct intel_connector *connector, enum pipe pipe);
281 uint32_t (*get)(struct intel_connector *connector);
282 void (*set)(struct intel_connector *connector, uint32_t level);
283 void (*disable)(struct intel_connector *connector);
284 void (*enable)(struct intel_connector *connector);
285 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
287 void (*power)(struct intel_connector *, bool enable);
291 struct intel_connector {
292 struct drm_connector base;
294 * The fixed encoder this connector is connected to.
296 struct intel_encoder *encoder;
298 /* ACPI device id for ACPI and driver cooperation */
301 /* Reads out the current hw, returning true if the connector is enabled
302 * and active (i.e. dpms ON state). */
303 bool (*get_hw_state)(struct intel_connector *);
305 /* Panel info for eDP and LVDS */
306 struct intel_panel panel;
308 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
310 struct edid *detect_edid;
312 /* since POLL and HPD connectors may use the same HPD line keep the native
313 state of connector->polled in case hotplug storm detection changes it */
316 void *port; /* store this opaque as its illegal to dereference it */
318 struct intel_dp *mst_port;
333 struct intel_atomic_state {
334 struct drm_atomic_state base;
339 * Calculated device cdclk, can be different from cdclk
340 * only when all crtc's are DPMS off.
342 unsigned int dev_cdclk;
344 bool dpll_set, modeset;
347 * Does this transaction change the pipes that are active? This mask
348 * tracks which CRTC's have changed their active state at the end of
349 * the transaction (not counting the temporary disable during modesets).
350 * This mask should only be non-zero when intel_state->modeset is true,
351 * but the converse is not necessarily true; simply changing a mode may
352 * not flip the final active status of any CRTC's
354 unsigned int active_pipe_changes;
356 unsigned int active_crtcs;
357 unsigned int min_pixclk[I915_MAX_PIPES];
360 unsigned int cdclk_pll_vco;
362 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
365 * Current watermarks can't be trusted during hardware readout, so
366 * don't bother calculating intermediate watermarks.
368 bool skip_intermediate_wm;
371 struct skl_wm_values wm_results;
373 struct i915_sw_fence commit_ready;
376 struct intel_plane_state {
377 struct drm_plane_state base;
378 struct drm_rect clip;
391 * = -1 : not using a scaler
392 * >= 0 : using a scalers
394 * plane requiring a scaler:
395 * - During check_plane, its bit is set in
396 * crtc_state->scaler_state.scaler_users by calling helper function
397 * update_scaler_plane.
398 * - scaler_id indicates the scaler it got assigned.
400 * plane doesn't require a scaler:
401 * - this can happen when scaling is no more required or plane simply
403 * - During check_plane, corresponding bit is reset in
404 * crtc_state->scaler_state.scaler_users by calling helper function
405 * update_scaler_plane.
409 struct drm_intel_sprite_colorkey ckey;
412 struct intel_initial_plane_config {
413 struct intel_framebuffer *fb;
419 #define SKL_MIN_SRC_W 8
420 #define SKL_MAX_SRC_W 4096
421 #define SKL_MIN_SRC_H 8
422 #define SKL_MAX_SRC_H 4096
423 #define SKL_MIN_DST_W 8
424 #define SKL_MAX_DST_W 4096
425 #define SKL_MIN_DST_H 8
426 #define SKL_MAX_DST_H 4096
428 struct intel_scaler {
433 struct intel_crtc_scaler_state {
434 #define SKL_NUM_SCALERS 2
435 struct intel_scaler scalers[SKL_NUM_SCALERS];
438 * scaler_users: keeps track of users requesting scalers on this crtc.
440 * If a bit is set, a user is using a scaler.
441 * Here user can be a plane or crtc as defined below:
442 * bits 0-30 - plane (bit position is index from drm_plane_index)
445 * Instead of creating a new index to cover planes and crtc, using
446 * existing drm_plane_index for planes which is well less than 31
447 * planes and bit 31 for crtc. This should be fine to cover all
450 * intel_atomic_setup_scalers will setup available scalers to users
451 * requesting scalers. It will gracefully fail if request exceeds
454 #define SKL_CRTC_INDEX 31
455 unsigned scaler_users;
457 /* scaler used by crtc for panel fitting purpose */
461 /* drm_mode->private_flags */
462 #define I915_MODE_FLAG_INHERITED 1
464 struct intel_pipe_wm {
465 struct intel_wm_level wm[5];
466 struct intel_wm_level raw_wm[5];
470 bool sprites_enabled;
474 struct skl_plane_wm {
475 struct skl_wm_level wm[8];
476 struct skl_wm_level trans_wm;
480 struct skl_plane_wm planes[I915_MAX_PLANES];
484 struct intel_crtc_wm_state {
488 * Intermediate watermarks; these can be
489 * programmed immediately since they satisfy
490 * both the current configuration we're
491 * switching away from and the new
492 * configuration we're switching to.
494 struct intel_pipe_wm intermediate;
497 * Optimal watermarks, programmed post-vblank
498 * when this state is committed.
500 struct intel_pipe_wm optimal;
504 /* gen9+ only needs 1-step wm programming */
505 struct skl_pipe_wm optimal;
506 struct skl_ddb_entry ddb;
511 * Platforms with two-step watermark programming will need to
512 * update watermark programming post-vblank to switch from the
513 * safe intermediate watermarks to the optimal final
516 bool need_postvbl_update;
519 struct intel_crtc_state {
520 struct drm_crtc_state base;
523 * quirks - bitfield with hw state readout quirks
525 * For various reasons the hw state readout code might not be able to
526 * completely faithfully read out the current state. These cases are
527 * tracked with quirk flags so that fastboot and state checker can act
530 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
531 unsigned long quirks;
533 unsigned fb_bits; /* framebuffers to flip */
534 bool update_pipe; /* can a fast modeset be performed? */
536 bool update_wm_pre, update_wm_post; /* watermarks are updated */
537 bool fb_changed; /* fb on any of the planes is changed */
539 /* Pipe source size (ie. panel fitter input size)
540 * All planes will be positioned inside this space,
541 * and get clipped at the edges. */
542 int pipe_src_w, pipe_src_h;
544 /* Whether to set up the PCH/FDI. Note that we never allow sharing
545 * between pch encoders and cpu encoders. */
546 bool has_pch_encoder;
548 /* Are we sending infoframes on the attached port */
551 /* CPU Transcoder for the pipe. Currently this can only differ from the
552 * pipe on Haswell and later (where we have a special eDP transcoder)
553 * and Broxton (where we have special DSI transcoders). */
554 enum transcoder cpu_transcoder;
557 * Use reduced/limited/broadcast rbg range, compressing from the full
558 * range fed into the crtcs.
560 bool limited_color_range;
562 /* Bitmask of encoder types (enum intel_output_type)
563 * driven by the pipe.
565 unsigned int output_types;
567 /* Whether we should send NULL infoframes. Required for audio. */
570 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
571 * has_dp_encoder is set. */
575 * Enable dithering, used when the selected pipe bpp doesn't match the
580 /* Controls for the clock computation, to override various stages. */
583 /* SDVO TV has a bunch of special case. To make multifunction encoders
584 * work correctly, we need to track this at runtime.*/
588 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
589 * required. This is set in the 2nd loop of calling encoder's
590 * ->compute_config if the first pick doesn't work out.
594 /* Settings for the intel dpll used on pretty much everything but
598 /* Selected dpll when shared or NULL. */
599 struct intel_shared_dpll *shared_dpll;
601 /* Actual register state of the dpll, for shared dpll cross-checking. */
602 struct intel_dpll_hw_state dpll_hw_state;
604 /* DSI PLL registers */
610 struct intel_link_m_n dp_m_n;
612 /* m2_n2 for eDP downclock */
613 struct intel_link_m_n dp_m2_n2;
617 * Frequence the dpll for the port should run at. Differs from the
618 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
619 * already multiplied by pixel_multiplier.
623 /* Used by SDVO (and if we ever fix it, HDMI). */
624 unsigned pixel_multiplier;
629 * Used by platforms having DP/HDMI PHY with programmable lane
630 * latency optimization.
632 uint8_t lane_lat_optim_mask;
634 /* Panel fitter controls for gen2-gen4 + VLV */
638 u32 lvds_border_bits;
641 /* Panel fitter placement and size for Ironlake+ */
649 /* FDI configuration, only valid if has_pch_encoder is set. */
651 struct intel_link_m_n fdi_m_n;
661 struct intel_crtc_scaler_state scaler_state;
663 /* w/a for waiting 2 vblanks during crtc enable */
664 enum pipe hsw_workaround_pipe;
666 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
669 struct intel_crtc_wm_state wm;
671 /* Gamma mode programmed on the pipe */
675 struct vlv_wm_state {
676 struct vlv_pipe_wm wm[3];
677 struct vlv_sr_wm sr[3];
678 uint8_t num_active_planes;
685 struct drm_crtc base;
688 u8 lut_r[256], lut_g[256], lut_b[256];
690 * Whether the crtc and the connected output pipeline is active. Implies
691 * that crtc->enabled is set, i.e. the current mode configuration has
692 * some outputs connected to this crtc.
695 unsigned long enabled_power_domains;
697 struct intel_overlay *overlay;
698 struct intel_flip_work *flip_work;
700 atomic_t unpin_work_count;
702 /* Display surface base address adjustement for pageflips. Note that on
703 * gen4+ this only adjusts up to a tile, offsets within a tile are
704 * handled in the hw itself (with the TILEOFF register). */
709 uint32_t cursor_addr;
710 uint32_t cursor_cntl;
711 uint32_t cursor_size;
712 uint32_t cursor_base;
714 struct intel_crtc_state *config;
716 /* global reset count when the last flip was submitted */
717 unsigned int reset_count;
719 /* Access to these should be protected by dev_priv->irq_lock. */
720 bool cpu_fifo_underrun_disabled;
721 bool pch_fifo_underrun_disabled;
723 /* per-pipe watermark state */
725 /* watermarks currently being used */
727 struct intel_pipe_wm ilk;
730 /* allow CxSR on this pipe */
737 unsigned start_vbl_count;
738 ktime_t start_vbl_time;
739 int min_vbl, max_vbl;
743 /* scalers available on this crtc */
746 struct vlv_wm_state wm_state;
749 struct intel_plane_wm_parameters {
750 uint32_t horiz_pixels;
751 uint32_t vert_pixels;
753 * For packed pixel formats:
754 * bytes_per_pixel - holds bytes per pixel
755 * For planar pixel formats:
756 * bytes_per_pixel - holds bytes per pixel for uv-plane
757 * y_bytes_per_pixel - holds bytes per pixel for y-plane
759 uint8_t bytes_per_pixel;
760 uint8_t y_bytes_per_pixel;
764 unsigned int rotation;
769 struct drm_plane base;
774 uint32_t frontbuffer_bit;
776 /* Since we need to change the watermarks before/after
777 * enabling/disabling the planes, we need to store the parameters here
778 * as the other pieces of the struct may not reflect the values we want
779 * for the watermark calculations. Currently only Haswell uses this.
781 struct intel_plane_wm_parameters wm;
784 * NOTE: Do not place new plane state fields here (e.g., when adding
785 * new plane properties). New runtime state should now be placed in
786 * the intel_plane_state structure and accessed via plane_state.
789 void (*update_plane)(struct drm_plane *plane,
790 const struct intel_crtc_state *crtc_state,
791 const struct intel_plane_state *plane_state);
792 void (*disable_plane)(struct drm_plane *plane,
793 struct drm_crtc *crtc);
794 int (*check_plane)(struct drm_plane *plane,
795 struct intel_crtc_state *crtc_state,
796 struct intel_plane_state *state);
799 struct intel_watermark_params {
807 struct cxsr_latency {
813 u16 display_hpll_disable;
815 u16 cursor_hpll_disable;
818 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
819 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
820 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
821 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
822 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
823 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
824 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
825 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
826 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
832 enum drm_dp_dual_mode_type type;
835 bool limited_color_range;
836 bool color_range_auto;
839 enum hdmi_force_audio force_audio;
840 bool rgb_quant_range_selectable;
841 enum hdmi_picture_aspect aspect_ratio;
842 struct intel_connector *attached_connector;
843 void (*write_infoframe)(struct drm_encoder *encoder,
844 enum hdmi_infoframe_type type,
845 const void *frame, ssize_t len);
846 void (*set_infoframes)(struct drm_encoder *encoder,
848 const struct drm_display_mode *adjusted_mode);
849 bool (*infoframe_enabled)(struct drm_encoder *encoder,
850 const struct intel_crtc_state *pipe_config);
853 struct intel_dp_mst_encoder;
854 #define DP_MAX_DOWNSTREAM_PORTS 0x10
858 * When platform provides two set of M_N registers for dp, we can
859 * program them and switch between them incase of DRRS.
860 * But When only one such register is provided, we have to program the
861 * required divider value on that registers itself based on the DRRS state.
863 * M1_N1 : Program dp_m_n on M1_N1 registers
864 * dp_m2_n2 on M2_N2 registers (If supported)
866 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
867 * M2_N2 registers are not supported
871 /* Sets the m1_n1 and m2_n2 */
876 struct intel_dp_desc {
885 i915_reg_t output_reg;
886 i915_reg_t aux_ch_ctl_reg;
887 i915_reg_t aux_ch_data_reg[5];
895 bool channel_eq_status;
896 enum hdmi_force_audio force_audio;
897 bool limited_color_range;
898 bool color_range_auto;
899 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
900 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
901 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
902 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
903 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
904 uint8_t num_sink_rates;
905 int sink_rates[DP_MAX_SUPPORTED_RATES];
906 /* sink or branch descriptor */
907 struct intel_dp_desc desc;
908 struct drm_dp_aux aux;
909 uint8_t train_set[4];
910 int panel_power_up_delay;
911 int panel_power_down_delay;
912 int panel_power_cycle_delay;
913 int backlight_on_delay;
914 int backlight_off_delay;
915 struct delayed_work panel_vdd_work;
917 unsigned long last_power_on;
918 unsigned long last_backlight_off;
919 ktime_t panel_power_off_time;
921 struct notifier_block edp_notifier;
924 * Pipe whose power sequencer is currently locked into
925 * this port. Only relevant on VLV/CHV.
929 * Set if the sequencer may be reset due to a power transition,
930 * requiring a reinitialization. Only relevant on BXT.
933 struct edp_power_seq pps_delays;
935 bool can_mst; /* this port supports mst */
937 int active_mst_links;
938 /* connector directly attached - won't be use for modeset in mst world */
939 struct intel_connector *attached_connector;
941 /* mst connector list */
942 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
943 struct drm_dp_mst_topology_mgr mst_mgr;
945 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
947 * This function returns the value we have to program the AUX_CTL
948 * register with to kick off an AUX transaction.
950 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
953 uint32_t aux_clock_divider);
955 /* This is called before a link training is starterd */
956 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
958 /* Displayport compliance testing */
959 unsigned long compliance_test_type;
960 unsigned long compliance_test_data;
961 bool compliance_test_active;
964 struct intel_lspcon {
966 enum drm_lspcon_mode mode;
970 struct intel_digital_port {
971 struct intel_encoder base;
975 struct intel_hdmi hdmi;
976 struct intel_lspcon lspcon;
977 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
978 bool release_cl2_override;
982 struct intel_dp_mst_encoder {
983 struct intel_encoder base;
985 struct intel_digital_port *primary;
986 struct intel_connector *connector;
989 static inline enum dpio_channel
990 vlv_dport_to_channel(struct intel_digital_port *dport)
992 switch (dport->port) {
1003 static inline enum dpio_phy
1004 vlv_dport_to_phy(struct intel_digital_port *dport)
1006 switch (dport->port) {
1017 static inline enum dpio_channel
1018 vlv_pipe_to_channel(enum pipe pipe)
1031 static inline struct intel_crtc *
1032 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1034 return dev_priv->pipe_to_crtc_mapping[pipe];
1037 static inline struct intel_crtc *
1038 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1040 return dev_priv->plane_to_crtc_mapping[plane];
1043 struct intel_flip_work {
1044 struct work_struct unpin_work;
1045 struct work_struct mmio_work;
1047 struct drm_crtc *crtc;
1048 struct drm_framebuffer *old_fb;
1049 struct drm_i915_gem_object *pending_flip_obj;
1050 struct drm_pending_vblank_event *event;
1054 struct drm_i915_gem_request *flip_queued_req;
1055 u32 flip_queued_vblank;
1056 u32 flip_ready_vblank;
1057 unsigned int rotation;
1060 struct intel_load_detect_pipe {
1061 struct drm_atomic_state *restore_state;
1064 static inline struct intel_encoder *
1065 intel_attached_encoder(struct drm_connector *connector)
1067 return to_intel_connector(connector)->encoder;
1070 static inline struct intel_digital_port *
1071 enc_to_dig_port(struct drm_encoder *encoder)
1073 return container_of(encoder, struct intel_digital_port, base.base);
1076 static inline struct intel_dp_mst_encoder *
1077 enc_to_mst(struct drm_encoder *encoder)
1079 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1082 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1084 return &enc_to_dig_port(encoder)->dp;
1087 static inline struct intel_digital_port *
1088 dp_to_dig_port(struct intel_dp *intel_dp)
1090 return container_of(intel_dp, struct intel_digital_port, dp);
1093 static inline struct intel_digital_port *
1094 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1096 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1099 /* intel_fifo_underrun.c */
1100 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool enable);
1102 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1103 enum transcoder pch_transcoder,
1105 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1107 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1108 enum transcoder pch_transcoder);
1109 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1110 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1113 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1114 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1115 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1116 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1117 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1118 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1119 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1120 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1121 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1122 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1123 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1124 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1125 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1126 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1129 * We only use drm_irq_uninstall() at unload and VT switch, so
1130 * this is the only thing we need to check.
1132 return dev_priv->pm.irqs_enabled;
1135 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1136 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1137 unsigned int pipe_mask);
1138 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1139 unsigned int pipe_mask);
1140 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1141 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1142 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1145 void intel_crt_init(struct drm_device *dev);
1146 void intel_crt_reset(struct drm_encoder *encoder);
1149 void intel_ddi_clk_select(struct intel_encoder *encoder,
1150 struct intel_shared_dpll *pll);
1151 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1152 struct intel_crtc_state *old_crtc_state,
1153 struct drm_connector_state *old_conn_state);
1154 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1155 void hsw_fdi_link_train(struct drm_crtc *crtc);
1156 void intel_ddi_init(struct drm_device *dev, enum port port);
1157 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1158 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1159 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1160 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1161 enum transcoder cpu_transcoder);
1162 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1163 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1164 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1165 struct intel_crtc_state *crtc_state);
1166 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1167 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1168 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1169 void intel_ddi_get_config(struct intel_encoder *encoder,
1170 struct intel_crtc_state *pipe_config);
1171 struct intel_encoder *
1172 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1174 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1175 void intel_ddi_clock_get(struct intel_encoder *encoder,
1176 struct intel_crtc_state *pipe_config);
1177 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1178 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1179 struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
1181 unsigned int intel_fb_align_height(struct drm_device *dev,
1182 unsigned int height,
1183 uint32_t pixel_format,
1184 uint64_t fb_format_modifier);
1185 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1186 uint64_t fb_modifier, uint32_t pixel_format);
1189 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1190 void intel_audio_codec_enable(struct intel_encoder *encoder,
1191 const struct intel_crtc_state *crtc_state,
1192 const struct drm_connector_state *conn_state);
1193 void intel_audio_codec_disable(struct intel_encoder *encoder);
1194 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1195 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1197 /* intel_display.c */
1198 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1199 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1200 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1201 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1202 const char *name, u32 reg, int ref_freq);
1203 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1204 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1205 extern const struct drm_plane_funcs intel_plane_funcs;
1206 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1207 unsigned int intel_fb_xy_to_linear(int x, int y,
1208 const struct intel_plane_state *state,
1210 void intel_add_fb_offsets(int *x, int *y,
1211 const struct intel_plane_state *state, int plane);
1212 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1213 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1214 void intel_mark_busy(struct drm_i915_private *dev_priv);
1215 void intel_mark_idle(struct drm_i915_private *dev_priv);
1216 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1217 int intel_display_suspend(struct drm_device *dev);
1218 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1219 void intel_encoder_destroy(struct drm_encoder *encoder);
1220 int intel_connector_init(struct intel_connector *);
1221 struct intel_connector *intel_connector_alloc(void);
1222 bool intel_connector_get_hw_state(struct intel_connector *connector);
1223 void intel_connector_attach_encoder(struct intel_connector *connector,
1224 struct intel_encoder *encoder);
1225 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1226 struct drm_crtc *crtc);
1227 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1228 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1229 struct drm_file *file_priv);
1230 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1233 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1234 enum intel_output_type type)
1236 return crtc_state->output_types & (1 << type);
1239 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1241 return crtc_state->output_types &
1242 ((1 << INTEL_OUTPUT_DP) |
1243 (1 << INTEL_OUTPUT_DP_MST) |
1244 (1 << INTEL_OUTPUT_EDP));
1247 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1249 drm_wait_one_vblank(&dev_priv->drm, pipe);
1252 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1254 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1257 intel_wait_for_vblank(dev_priv, pipe);
1260 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1262 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1263 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1264 struct intel_digital_port *dport,
1265 unsigned int expected_mask);
1266 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1267 struct drm_display_mode *mode,
1268 struct intel_load_detect_pipe *old,
1269 struct drm_modeset_acquire_ctx *ctx);
1270 void intel_release_load_detect_pipe(struct drm_connector *connector,
1271 struct intel_load_detect_pipe *old,
1272 struct drm_modeset_acquire_ctx *ctx);
1274 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1275 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1276 struct drm_framebuffer *
1277 __intel_framebuffer_create(struct drm_device *dev,
1278 struct drm_mode_fb_cmd2 *mode_cmd,
1279 struct drm_i915_gem_object *obj);
1280 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1281 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1282 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1283 int intel_prepare_plane_fb(struct drm_plane *plane,
1284 struct drm_plane_state *new_state);
1285 void intel_cleanup_plane_fb(struct drm_plane *plane,
1286 struct drm_plane_state *old_state);
1287 int intel_plane_atomic_get_property(struct drm_plane *plane,
1288 const struct drm_plane_state *state,
1289 struct drm_property *property,
1291 int intel_plane_atomic_set_property(struct drm_plane *plane,
1292 struct drm_plane_state *state,
1293 struct drm_property *property,
1295 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1296 struct drm_plane_state *plane_state);
1298 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1299 uint64_t fb_modifier, unsigned int cpp);
1301 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1304 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1305 const struct dpll *dpll);
1306 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1307 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1309 /* modesetting asserts */
1310 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1312 void assert_pll(struct drm_i915_private *dev_priv,
1313 enum pipe pipe, bool state);
1314 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1315 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1316 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1317 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1318 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1319 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1320 enum pipe pipe, bool state);
1321 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1322 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1323 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1324 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1325 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1326 u32 intel_compute_tile_offset(int *x, int *y,
1327 const struct intel_plane_state *state, int plane);
1328 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1329 void intel_finish_reset(struct drm_i915_private *dev_priv);
1330 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1331 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1332 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1333 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1334 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1335 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1336 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1337 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1338 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1339 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1340 unsigned int skl_cdclk_get_vco(unsigned int freq);
1341 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1342 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1343 void intel_dp_get_m_n(struct intel_crtc *crtc,
1344 struct intel_crtc_state *pipe_config);
1345 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1346 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1347 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1348 struct dpll *best_clock);
1349 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1351 bool intel_crtc_active(struct intel_crtc *crtc);
1352 void hsw_enable_ips(struct intel_crtc *crtc);
1353 void hsw_disable_ips(struct intel_crtc *crtc);
1354 enum intel_display_power_domain
1355 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1356 enum intel_display_power_domain
1357 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1358 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1359 struct intel_crtc_state *pipe_config);
1361 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1362 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1364 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, unsigned int rotation);
1366 u32 skl_plane_ctl_format(uint32_t pixel_format);
1367 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1368 u32 skl_plane_ctl_rotation(unsigned int rotation);
1369 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1370 unsigned int rotation);
1371 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1374 void intel_csr_ucode_init(struct drm_i915_private *);
1375 void intel_csr_load_program(struct drm_i915_private *);
1376 void intel_csr_ucode_fini(struct drm_i915_private *);
1377 void intel_csr_ucode_suspend(struct drm_i915_private *);
1378 void intel_csr_ucode_resume(struct drm_i915_private *);
1381 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1382 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1383 struct intel_connector *intel_connector);
1384 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1385 int link_rate, uint8_t lane_count,
1387 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1388 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1389 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1390 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1391 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1392 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1393 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1394 bool intel_dp_compute_config(struct intel_encoder *encoder,
1395 struct intel_crtc_state *pipe_config,
1396 struct drm_connector_state *conn_state);
1397 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1398 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1400 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1401 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1402 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1403 void intel_edp_panel_on(struct intel_dp *intel_dp);
1404 void intel_edp_panel_off(struct intel_dp *intel_dp);
1405 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1406 void intel_dp_mst_suspend(struct drm_device *dev);
1407 void intel_dp_mst_resume(struct drm_device *dev);
1408 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1409 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1410 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1411 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1412 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1413 void intel_plane_destroy(struct drm_plane *plane);
1414 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1415 struct intel_crtc_state *crtc_state);
1416 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1417 struct intel_crtc_state *crtc_state);
1418 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1419 unsigned int frontbuffer_bits);
1420 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1421 unsigned int frontbuffer_bits);
1424 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1425 uint8_t dp_train_pat);
1427 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1428 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1430 intel_dp_voltage_max(struct intel_dp *intel_dp);
1432 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1433 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1434 uint8_t *link_bw, uint8_t *rate_select);
1435 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1437 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1439 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1441 return ~((1 << lane_count) - 1) & 0xf;
1444 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1445 bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1446 struct intel_dp_desc *desc);
1447 bool intel_dp_read_desc(struct intel_dp *intel_dp);
1449 /* intel_dp_aux_backlight.c */
1450 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1452 /* intel_dp_mst.c */
1453 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1454 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1456 void intel_dsi_init(struct drm_device *dev);
1458 /* intel_dsi_dcs_backlight.c */
1459 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1462 void intel_dvo_init(struct drm_device *dev);
1463 /* intel_hotplug.c */
1464 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1467 /* legacy fbdev emulation in intel_fbdev.c */
1468 #ifdef CONFIG_DRM_FBDEV_EMULATION
1469 extern int intel_fbdev_init(struct drm_device *dev);
1470 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1471 extern void intel_fbdev_fini(struct drm_device *dev);
1472 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1473 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1474 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1476 static inline int intel_fbdev_init(struct drm_device *dev)
1481 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1485 static inline void intel_fbdev_fini(struct drm_device *dev)
1489 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1493 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1497 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1503 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1504 struct drm_atomic_state *state);
1505 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1506 void intel_fbc_pre_update(struct intel_crtc *crtc,
1507 struct intel_crtc_state *crtc_state,
1508 struct intel_plane_state *plane_state);
1509 void intel_fbc_post_update(struct intel_crtc *crtc);
1510 void intel_fbc_init(struct drm_i915_private *dev_priv);
1511 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1512 void intel_fbc_enable(struct intel_crtc *crtc,
1513 struct intel_crtc_state *crtc_state,
1514 struct intel_plane_state *plane_state);
1515 void intel_fbc_disable(struct intel_crtc *crtc);
1516 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1517 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1518 unsigned int frontbuffer_bits,
1519 enum fb_op_origin origin);
1520 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1521 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1522 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1523 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1526 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1527 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1528 struct intel_connector *intel_connector);
1529 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1530 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1531 struct intel_crtc_state *pipe_config,
1532 struct drm_connector_state *conn_state);
1533 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1537 void intel_lvds_init(struct drm_device *dev);
1538 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1539 bool intel_is_dual_link_lvds(struct drm_device *dev);
1543 int intel_connector_update_modes(struct drm_connector *connector,
1545 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1546 void intel_attach_force_audio_property(struct drm_connector *connector);
1547 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1548 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1551 /* intel_overlay.c */
1552 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1553 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1554 int intel_overlay_switch_off(struct intel_overlay *overlay);
1555 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1556 struct drm_file *file_priv);
1557 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1558 struct drm_file *file_priv);
1559 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1563 int intel_panel_init(struct intel_panel *panel,
1564 struct drm_display_mode *fixed_mode,
1565 struct drm_display_mode *downclock_mode);
1566 void intel_panel_fini(struct intel_panel *panel);
1567 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1568 struct drm_display_mode *adjusted_mode);
1569 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1570 struct intel_crtc_state *pipe_config,
1572 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1573 struct intel_crtc_state *pipe_config,
1575 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1576 u32 level, u32 max);
1577 int intel_panel_setup_backlight(struct drm_connector *connector,
1579 void intel_panel_enable_backlight(struct intel_connector *connector);
1580 void intel_panel_disable_backlight(struct intel_connector *connector);
1581 void intel_panel_destroy_backlight(struct drm_connector *connector);
1582 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1583 extern struct drm_display_mode *intel_find_panel_downclock(
1584 struct drm_device *dev,
1585 struct drm_display_mode *fixed_mode,
1586 struct drm_connector *connector);
1588 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1589 int intel_backlight_device_register(struct intel_connector *connector);
1590 void intel_backlight_device_unregister(struct intel_connector *connector);
1591 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1592 static int intel_backlight_device_register(struct intel_connector *connector)
1596 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1599 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1603 void intel_psr_enable(struct intel_dp *intel_dp);
1604 void intel_psr_disable(struct intel_dp *intel_dp);
1605 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1606 unsigned frontbuffer_bits);
1607 void intel_psr_flush(struct drm_i915_private *dev_priv,
1608 unsigned frontbuffer_bits,
1609 enum fb_op_origin origin);
1610 void intel_psr_init(struct drm_device *dev);
1611 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1612 unsigned frontbuffer_bits);
1614 /* intel_runtime_pm.c */
1615 int intel_power_domains_init(struct drm_i915_private *);
1616 void intel_power_domains_fini(struct drm_i915_private *);
1617 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1618 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1619 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1620 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1621 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1623 intel_display_power_domain_str(enum intel_display_power_domain domain);
1625 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1626 enum intel_display_power_domain domain);
1627 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1628 enum intel_display_power_domain domain);
1629 void intel_display_power_get(struct drm_i915_private *dev_priv,
1630 enum intel_display_power_domain domain);
1631 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1632 enum intel_display_power_domain domain);
1633 void intel_display_power_put(struct drm_i915_private *dev_priv,
1634 enum intel_display_power_domain domain);
1637 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1639 WARN_ONCE(dev_priv->pm.suspended,
1640 "Device suspended during HW access\n");
1644 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1646 assert_rpm_device_not_suspended(dev_priv);
1647 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1648 * too much noise. */
1649 if (!atomic_read(&dev_priv->pm.wakeref_count))
1650 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1654 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1655 * @dev_priv: i915 device instance
1657 * This function disable asserts that check if we hold an RPM wakelock
1658 * reference, while keeping the device-not-suspended checks still enabled.
1659 * It's meant to be used only in special circumstances where our rule about
1660 * the wakelock refcount wrt. the device power state doesn't hold. According
1661 * to this rule at any point where we access the HW or want to keep the HW in
1662 * an active state we must hold an RPM wakelock reference acquired via one of
1663 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1664 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1665 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1666 * users should avoid using this function.
1668 * Any calls to this function must have a symmetric call to
1669 * enable_rpm_wakeref_asserts().
1672 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1674 atomic_inc(&dev_priv->pm.wakeref_count);
1678 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1679 * @dev_priv: i915 device instance
1681 * This function re-enables the RPM assert checks after disabling them with
1682 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1683 * circumstances otherwise its use should be avoided.
1685 * Any calls to this function must have a symmetric call to
1686 * disable_rpm_wakeref_asserts().
1689 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1691 atomic_dec(&dev_priv->pm.wakeref_count);
1694 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1695 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1696 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1697 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1699 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1701 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1702 bool override, unsigned int mask);
1703 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1704 enum dpio_channel ch, bool override);
1708 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1709 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1710 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1711 void intel_update_watermarks(struct intel_crtc *crtc);
1712 void intel_init_pm(struct drm_i915_private *dev_priv);
1713 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1714 void intel_pm_setup(struct drm_device *dev);
1715 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1716 void intel_gpu_ips_teardown(void);
1717 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1718 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1719 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1720 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1721 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1722 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1723 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1724 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1725 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1726 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1727 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1728 struct intel_rps_client *rps,
1729 unsigned long submitted);
1730 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1731 void vlv_wm_get_hw_state(struct drm_device *dev);
1732 void ilk_wm_get_hw_state(struct drm_device *dev);
1733 void skl_wm_get_hw_state(struct drm_device *dev);
1734 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1735 struct skl_ddb_allocation *ddb /* out */);
1736 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1737 struct skl_pipe_wm *out);
1738 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1739 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1740 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1741 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1742 const struct skl_wm_level *l2);
1743 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1744 const struct skl_ddb_entry *ddb,
1746 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1747 bool ilk_disable_lp_wm(struct drm_device *dev);
1748 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1749 static inline int intel_enable_rc6(void)
1751 return i915.enable_rc6;
1755 bool intel_sdvo_init(struct drm_device *dev,
1756 i915_reg_t reg, enum port port);
1759 /* intel_sprite.c */
1760 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1762 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1763 enum pipe pipe, int plane);
1764 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1765 struct drm_file *file_priv);
1766 void intel_pipe_update_start(struct intel_crtc *crtc);
1767 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1770 void intel_tv_init(struct drm_device *dev);
1772 /* intel_atomic.c */
1773 int intel_connector_atomic_get_property(struct drm_connector *connector,
1774 const struct drm_connector_state *state,
1775 struct drm_property *property,
1777 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1778 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1779 struct drm_crtc_state *state);
1780 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1781 void intel_atomic_state_clear(struct drm_atomic_state *);
1782 struct intel_shared_dpll_config *
1783 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1785 static inline struct intel_crtc_state *
1786 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1787 struct intel_crtc *crtc)
1789 struct drm_crtc_state *crtc_state;
1790 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1791 if (IS_ERR(crtc_state))
1792 return ERR_CAST(crtc_state);
1794 return to_intel_crtc_state(crtc_state);
1797 static inline struct intel_plane_state *
1798 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1799 struct intel_plane *plane)
1801 struct drm_plane_state *plane_state;
1803 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1805 return to_intel_plane_state(plane_state);
1808 int intel_atomic_setup_scalers(struct drm_device *dev,
1809 struct intel_crtc *intel_crtc,
1810 struct intel_crtc_state *crtc_state);
1812 /* intel_atomic_plane.c */
1813 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1814 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1815 void intel_plane_destroy_state(struct drm_plane *plane,
1816 struct drm_plane_state *state);
1817 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1818 int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
1819 struct intel_plane_state *intel_state);
1822 void intel_color_init(struct drm_crtc *crtc);
1823 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1824 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1825 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1827 /* intel_lspcon.c */
1828 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1829 void lspcon_resume(struct intel_lspcon *lspcon);
1830 #endif /* __INTEL_DRV_H__ */