2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
41 * _wait_for - magic (register) wait macro
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
48 #define _wait_for(COND, MS, W) ({ \
49 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
52 if (time_after(jiffies, timeout__)) { \
57 if ((W) && drm_can_sleep()) { \
58 usleep_range((W)*1000, (W)*2000); \
66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
69 DIV_ROUND_UP((US), 1000), 0)
71 #define KHz(x) (1000 * (x))
72 #define MHz(x) KHz(1000 * (x))
75 * Display related stuff
78 /* store information about an Ixxx DVO */
79 /* The i830->i865 use multiple DVOs with multiple i2cs */
80 /* the i915, i945 have a single sDVO i2c bus - which is different */
82 /* maximum connectors per crtcs in the mode set */
84 /* Maximum cursor sizes */
85 #define GEN2_CURSOR_WIDTH 64
86 #define GEN2_CURSOR_HEIGHT 64
87 #define MAX_CURSOR_WIDTH 256
88 #define MAX_CURSOR_HEIGHT 256
90 #define INTEL_I2C_BUS_DVO 1
91 #define INTEL_I2C_BUS_SDVO 2
93 /* these are outputs from the chip - integrated only
94 external chips are via DVO or SDVO output */
95 enum intel_output_type {
96 INTEL_OUTPUT_UNUSED = 0,
97 INTEL_OUTPUT_ANALOG = 1,
99 INTEL_OUTPUT_SDVO = 3,
100 INTEL_OUTPUT_LVDS = 4,
101 INTEL_OUTPUT_TVOUT = 5,
102 INTEL_OUTPUT_HDMI = 6,
103 INTEL_OUTPUT_DISPLAYPORT = 7,
104 INTEL_OUTPUT_EDP = 8,
105 INTEL_OUTPUT_DSI = 9,
106 INTEL_OUTPUT_UNKNOWN = 10,
107 INTEL_OUTPUT_DP_MST = 11,
110 #define INTEL_DVO_CHIP_NONE 0
111 #define INTEL_DVO_CHIP_LVDS 1
112 #define INTEL_DVO_CHIP_TMDS 2
113 #define INTEL_DVO_CHIP_TVOUT 4
115 #define INTEL_DSI_VIDEO_MODE 0
116 #define INTEL_DSI_COMMAND_MODE 1
118 struct intel_framebuffer {
119 struct drm_framebuffer base;
120 struct drm_i915_gem_object *obj;
124 struct drm_fb_helper helper;
125 struct intel_framebuffer *fb;
129 struct intel_encoder {
130 struct drm_encoder base;
132 enum intel_output_type type;
133 unsigned int cloneable;
134 void (*hot_plug)(struct intel_encoder *);
135 bool (*compute_config)(struct intel_encoder *,
136 struct intel_crtc_state *);
137 void (*pre_pll_enable)(struct intel_encoder *);
138 void (*pre_enable)(struct intel_encoder *);
139 void (*enable)(struct intel_encoder *);
140 void (*mode_set)(struct intel_encoder *intel_encoder);
141 void (*disable)(struct intel_encoder *);
142 void (*post_disable)(struct intel_encoder *);
143 void (*post_pll_disable)(struct intel_encoder *);
144 /* Read out the current hw state of this connector, returning true if
145 * the encoder is active. If the encoder is enabled it also set the pipe
146 * it is connected to in the pipe parameter. */
147 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
148 /* Reconstructs the equivalent mode flags for the current hardware
149 * state. This must be called _after_ display->get_pipe_config has
150 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
151 * be set correctly before calling this function. */
152 void (*get_config)(struct intel_encoder *,
153 struct intel_crtc_state *pipe_config);
155 * Called during system suspend after all pending requests for the
156 * encoder are flushed (for example for DP AUX transactions) and
157 * device interrupts are disabled.
159 void (*suspend)(struct intel_encoder *);
161 enum hpd_pin hpd_pin;
165 struct drm_display_mode *fixed_mode;
166 struct drm_display_mode *downclock_mode;
176 bool combination_mode; /* gen 2/4 only */
180 bool util_pin_active_low; /* bxt+ */
181 u8 controller; /* bxt+ only */
182 struct pwm_device *pwm;
184 struct backlight_device *device;
186 /* Connector and platform specific backlight functions */
187 int (*setup)(struct intel_connector *connector, enum pipe pipe);
188 uint32_t (*get)(struct intel_connector *connector);
189 void (*set)(struct intel_connector *connector, uint32_t level);
190 void (*disable)(struct intel_connector *connector);
191 void (*enable)(struct intel_connector *connector);
192 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
194 void (*power)(struct intel_connector *, bool enable);
198 struct intel_connector {
199 struct drm_connector base;
201 * The fixed encoder this connector is connected to.
203 struct intel_encoder *encoder;
205 /* Reads out the current hw, returning true if the connector is enabled
206 * and active (i.e. dpms ON state). */
207 bool (*get_hw_state)(struct intel_connector *);
210 * Removes all interfaces through which the connector is accessible
211 * - like sysfs, debugfs entries -, so that no new operations can be
212 * started on the connector. Also makes sure all currently pending
213 * operations finish before returing.
215 void (*unregister)(struct intel_connector *);
217 /* Panel info for eDP and LVDS */
218 struct intel_panel panel;
220 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
222 struct edid *detect_edid;
224 /* since POLL and HPD connectors may use the same HPD line keep the native
225 state of connector->polled in case hotplug storm detection changes it */
228 void *port; /* store this opaque as its illegal to dereference it */
230 struct intel_dp *mst_port;
233 typedef struct dpll {
245 struct intel_atomic_state {
246 struct drm_atomic_state base;
251 * Calculated device cdclk, can be different from cdclk
252 * only when all crtc's are DPMS off.
254 unsigned int dev_cdclk;
256 bool dpll_set, modeset;
258 unsigned int active_crtcs;
259 unsigned int min_pixclk[I915_MAX_PIPES];
261 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
262 struct intel_wm_config wm_config;
265 struct intel_plane_state {
266 struct drm_plane_state base;
269 struct drm_rect clip;
274 * = -1 : not using a scaler
275 * >= 0 : using a scalers
277 * plane requiring a scaler:
278 * - During check_plane, its bit is set in
279 * crtc_state->scaler_state.scaler_users by calling helper function
280 * update_scaler_plane.
281 * - scaler_id indicates the scaler it got assigned.
283 * plane doesn't require a scaler:
284 * - this can happen when scaling is no more required or plane simply
286 * - During check_plane, corresponding bit is reset in
287 * crtc_state->scaler_state.scaler_users by calling helper function
288 * update_scaler_plane.
292 struct drm_intel_sprite_colorkey ckey;
294 /* async flip related structures */
295 struct drm_i915_gem_request *wait_req;
298 struct intel_initial_plane_config {
299 struct intel_framebuffer *fb;
305 #define SKL_MIN_SRC_W 8
306 #define SKL_MAX_SRC_W 4096
307 #define SKL_MIN_SRC_H 8
308 #define SKL_MAX_SRC_H 4096
309 #define SKL_MIN_DST_W 8
310 #define SKL_MAX_DST_W 4096
311 #define SKL_MIN_DST_H 8
312 #define SKL_MAX_DST_H 4096
314 struct intel_scaler {
319 struct intel_crtc_scaler_state {
320 #define SKL_NUM_SCALERS 2
321 struct intel_scaler scalers[SKL_NUM_SCALERS];
324 * scaler_users: keeps track of users requesting scalers on this crtc.
326 * If a bit is set, a user is using a scaler.
327 * Here user can be a plane or crtc as defined below:
328 * bits 0-30 - plane (bit position is index from drm_plane_index)
331 * Instead of creating a new index to cover planes and crtc, using
332 * existing drm_plane_index for planes which is well less than 31
333 * planes and bit 31 for crtc. This should be fine to cover all
336 * intel_atomic_setup_scalers will setup available scalers to users
337 * requesting scalers. It will gracefully fail if request exceeds
340 #define SKL_CRTC_INDEX 31
341 unsigned scaler_users;
343 /* scaler used by crtc for panel fitting purpose */
347 /* drm_mode->private_flags */
348 #define I915_MODE_FLAG_INHERITED 1
350 struct intel_pipe_wm {
351 struct intel_wm_level wm[5];
355 bool sprites_enabled;
360 struct skl_wm_level wm[8];
361 struct skl_wm_level trans_wm;
365 struct intel_crtc_state {
366 struct drm_crtc_state base;
369 * quirks - bitfield with hw state readout quirks
371 * For various reasons the hw state readout code might not be able to
372 * completely faithfully read out the current state. These cases are
373 * tracked with quirk flags so that fastboot and state checker can act
376 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
377 unsigned long quirks;
379 bool update_pipe; /* can a fast modeset be performed? */
381 bool wm_changed; /* watermarks are updated */
383 /* Pipe source size (ie. panel fitter input size)
384 * All planes will be positioned inside this space,
385 * and get clipped at the edges. */
386 int pipe_src_w, pipe_src_h;
388 /* Whether to set up the PCH/FDI. Note that we never allow sharing
389 * between pch encoders and cpu encoders. */
390 bool has_pch_encoder;
392 /* Are we sending infoframes on the attached port */
395 /* CPU Transcoder for the pipe. Currently this can only differ from the
396 * pipe on Haswell (where we have a special eDP transcoder). */
397 enum transcoder cpu_transcoder;
400 * Use reduced/limited/broadcast rbg range, compressing from the full
401 * range fed into the crtcs.
403 bool limited_color_range;
405 /* DP has a bunch of special case unfortunately, so mark the pipe
409 /* DSI has special cases */
410 bool has_dsi_encoder;
412 /* Whether we should send NULL infoframes. Required for audio. */
415 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
416 * has_dp_encoder is set. */
420 * Enable dithering, used when the selected pipe bpp doesn't match the
425 /* Controls for the clock computation, to override various stages. */
428 /* SDVO TV has a bunch of special case. To make multifunction encoders
429 * work correctly, we need to track this at runtime.*/
433 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
434 * required. This is set in the 2nd loop of calling encoder's
435 * ->compute_config if the first pick doesn't work out.
439 /* Settings for the intel dpll used on pretty much everything but
443 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
444 enum intel_dpll_id shared_dpll;
447 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
448 * - enum skl_dpll on SKL
450 uint32_t ddi_pll_sel;
452 /* Actual register state of the dpll, for shared dpll cross-checking. */
453 struct intel_dpll_hw_state dpll_hw_state;
456 struct intel_link_m_n dp_m_n;
458 /* m2_n2 for eDP downclock */
459 struct intel_link_m_n dp_m2_n2;
463 * Frequence the dpll for the port should run at. Differs from the
464 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
465 * already multiplied by pixel_multiplier.
469 /* Used by SDVO (and if we ever fix it, HDMI). */
470 unsigned pixel_multiplier;
474 /* Panel fitter controls for gen2-gen4 + VLV */
478 u32 lvds_border_bits;
481 /* Panel fitter placement and size for Ironlake+ */
489 /* FDI configuration, only valid if has_pch_encoder is set. */
491 struct intel_link_m_n fdi_m_n;
497 bool dp_encoder_is_mst;
500 struct intel_crtc_scaler_state scaler_state;
502 /* w/a for waiting 2 vblanks during crtc enable */
503 enum pipe hsw_workaround_pipe;
505 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
510 * optimal watermarks, programmed post-vblank when this state
514 struct intel_pipe_wm ilk;
515 struct skl_pipe_wm skl;
520 struct vlv_wm_state {
521 struct vlv_pipe_wm wm[3];
522 struct vlv_sr_wm sr[3];
523 uint8_t num_active_planes;
529 struct intel_mmio_flip {
530 struct work_struct work;
531 struct drm_i915_private *i915;
532 struct drm_i915_gem_request *req;
533 struct intel_crtc *crtc;
534 unsigned int rotation;
538 * Tracking of operations that need to be performed at the beginning/end of an
539 * atomic commit, outside the atomic section where interrupts are disabled.
540 * These are generally operations that grab mutexes or might otherwise sleep
541 * and thus can't be run with interrupts disabled.
543 struct intel_crtc_atomic_commit {
544 /* Sleepable operations to perform before commit */
547 bool pre_disable_primary;
549 /* Sleepable operations to perform after commit */
553 bool post_enable_primary;
554 unsigned update_sprite_watermarks;
558 struct drm_crtc base;
561 u8 lut_r[256], lut_g[256], lut_b[256];
563 * Whether the crtc and the connected output pipeline is active. Implies
564 * that crtc->enabled is set, i.e. the current mode configuration has
565 * some outputs connected to this crtc.
568 unsigned long enabled_power_domains;
570 struct intel_overlay *overlay;
571 struct intel_unpin_work *unpin_work;
573 atomic_t unpin_work_count;
575 /* Display surface base address adjustement for pageflips. Note that on
576 * gen4+ this only adjusts up to a tile, offsets within a tile are
577 * handled in the hw itself (with the TILEOFF register). */
578 unsigned long dspaddr_offset;
582 uint32_t cursor_addr;
583 uint32_t cursor_cntl;
584 uint32_t cursor_size;
585 uint32_t cursor_base;
587 struct intel_crtc_state *config;
589 /* reset counter value when the last flip was submitted */
590 unsigned int reset_counter;
592 /* Access to these should be protected by dev_priv->irq_lock. */
593 bool cpu_fifo_underrun_disabled;
594 bool pch_fifo_underrun_disabled;
596 /* per-pipe watermark state */
598 /* watermarks currently being used */
600 struct intel_pipe_wm ilk;
601 struct skl_pipe_wm skl;
603 /* allow CxSR on this pipe */
610 unsigned start_vbl_count;
611 ktime_t start_vbl_time;
612 int min_vbl, max_vbl;
616 struct intel_crtc_atomic_commit atomic;
618 /* scalers available on this crtc */
621 struct vlv_wm_state wm_state;
624 struct intel_plane_wm_parameters {
625 uint32_t horiz_pixels;
626 uint32_t vert_pixels;
628 * For packed pixel formats:
629 * bytes_per_pixel - holds bytes per pixel
630 * For planar pixel formats:
631 * bytes_per_pixel - holds bytes per pixel for uv-plane
632 * y_bytes_per_pixel - holds bytes per pixel for y-plane
634 uint8_t bytes_per_pixel;
635 uint8_t y_bytes_per_pixel;
639 unsigned int rotation;
644 struct drm_plane base;
649 uint32_t frontbuffer_bit;
651 /* Since we need to change the watermarks before/after
652 * enabling/disabling the planes, we need to store the parameters here
653 * as the other pieces of the struct may not reflect the values we want
654 * for the watermark calculations. Currently only Haswell uses this.
656 struct intel_plane_wm_parameters wm;
659 * NOTE: Do not place new plane state fields here (e.g., when adding
660 * new plane properties). New runtime state should now be placed in
661 * the intel_plane_state structure and accessed via plane_state.
664 void (*update_plane)(struct drm_plane *plane,
665 const struct intel_crtc_state *crtc_state,
666 const struct intel_plane_state *plane_state);
667 void (*disable_plane)(struct drm_plane *plane,
668 struct drm_crtc *crtc);
669 int (*check_plane)(struct drm_plane *plane,
670 struct intel_crtc_state *crtc_state,
671 struct intel_plane_state *state);
674 struct intel_watermark_params {
675 unsigned long fifo_size;
676 unsigned long max_wm;
677 unsigned long default_wm;
678 unsigned long guard_size;
679 unsigned long cacheline_size;
682 struct cxsr_latency {
685 unsigned long fsb_freq;
686 unsigned long mem_freq;
687 unsigned long display_sr;
688 unsigned long display_hpll_disable;
689 unsigned long cursor_sr;
690 unsigned long cursor_hpll_disable;
693 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
694 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
695 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
696 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
697 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
698 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
699 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
700 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
701 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
706 bool limited_color_range;
707 bool color_range_auto;
710 enum hdmi_force_audio force_audio;
711 bool rgb_quant_range_selectable;
712 enum hdmi_picture_aspect aspect_ratio;
713 struct intel_connector *attached_connector;
714 void (*write_infoframe)(struct drm_encoder *encoder,
715 enum hdmi_infoframe_type type,
716 const void *frame, ssize_t len);
717 void (*set_infoframes)(struct drm_encoder *encoder,
719 const struct drm_display_mode *adjusted_mode);
720 bool (*infoframe_enabled)(struct drm_encoder *encoder,
721 const struct intel_crtc_state *pipe_config);
724 struct intel_dp_mst_encoder;
725 #define DP_MAX_DOWNSTREAM_PORTS 0x10
729 * When platform provides two set of M_N registers for dp, we can
730 * program them and switch between them incase of DRRS.
731 * But When only one such register is provided, we have to program the
732 * required divider value on that registers itself based on the DRRS state.
734 * M1_N1 : Program dp_m_n on M1_N1 registers
735 * dp_m2_n2 on M2_N2 registers (If supported)
737 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
738 * M2_N2 registers are not supported
742 /* Sets the m1_n1 and m2_n2 */
748 i915_reg_t output_reg;
749 i915_reg_t aux_ch_ctl_reg;
750 i915_reg_t aux_ch_data_reg[5];
755 enum hdmi_force_audio force_audio;
756 bool limited_color_range;
757 bool color_range_auto;
758 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
759 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
760 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
761 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
762 uint8_t num_sink_rates;
763 int sink_rates[DP_MAX_SUPPORTED_RATES];
764 struct drm_dp_aux aux;
765 uint8_t train_set[4];
766 int panel_power_up_delay;
767 int panel_power_down_delay;
768 int panel_power_cycle_delay;
769 int backlight_on_delay;
770 int backlight_off_delay;
771 struct delayed_work panel_vdd_work;
773 unsigned long last_power_cycle;
774 unsigned long last_power_on;
775 unsigned long last_backlight_off;
777 struct notifier_block edp_notifier;
780 * Pipe whose power sequencer is currently locked into
781 * this port. Only relevant on VLV/CHV.
784 struct edp_power_seq pps_delays;
786 bool can_mst; /* this port supports mst */
788 int active_mst_links;
789 /* connector directly attached - won't be use for modeset in mst world */
790 struct intel_connector *attached_connector;
792 /* mst connector list */
793 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
794 struct drm_dp_mst_topology_mgr mst_mgr;
796 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
798 * This function returns the value we have to program the AUX_CTL
799 * register with to kick off an AUX transaction.
801 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
804 uint32_t aux_clock_divider);
806 /* This is called before a link training is starterd */
807 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
809 bool train_set_valid;
811 /* Displayport compliance testing */
812 unsigned long compliance_test_type;
813 unsigned long compliance_test_data;
814 bool compliance_test_active;
817 struct intel_digital_port {
818 struct intel_encoder base;
822 struct intel_hdmi hdmi;
823 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
824 bool release_cl2_override;
826 /* for communication with audio component; protected by av_mutex */
827 const struct drm_connector *audio_connector;
830 struct intel_dp_mst_encoder {
831 struct intel_encoder base;
833 struct intel_digital_port *primary;
834 void *port; /* store this opaque as its illegal to dereference it */
837 static inline enum dpio_channel
838 vlv_dport_to_channel(struct intel_digital_port *dport)
840 switch (dport->port) {
851 static inline enum dpio_phy
852 vlv_dport_to_phy(struct intel_digital_port *dport)
854 switch (dport->port) {
865 static inline enum dpio_channel
866 vlv_pipe_to_channel(enum pipe pipe)
879 static inline struct drm_crtc *
880 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
882 struct drm_i915_private *dev_priv = dev->dev_private;
883 return dev_priv->pipe_to_crtc_mapping[pipe];
886 static inline struct drm_crtc *
887 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
889 struct drm_i915_private *dev_priv = dev->dev_private;
890 return dev_priv->plane_to_crtc_mapping[plane];
893 struct intel_unpin_work {
894 struct work_struct work;
895 struct drm_crtc *crtc;
896 struct drm_framebuffer *old_fb;
897 struct drm_i915_gem_object *pending_flip_obj;
898 struct drm_pending_vblank_event *event;
900 #define INTEL_FLIP_INACTIVE 0
901 #define INTEL_FLIP_PENDING 1
902 #define INTEL_FLIP_COMPLETE 2
905 struct drm_i915_gem_request *flip_queued_req;
906 u32 flip_queued_vblank;
907 u32 flip_ready_vblank;
908 bool enable_stall_check;
911 struct intel_load_detect_pipe {
912 struct drm_framebuffer *release_fb;
913 bool load_detect_temp;
917 static inline struct intel_encoder *
918 intel_attached_encoder(struct drm_connector *connector)
920 return to_intel_connector(connector)->encoder;
923 static inline struct intel_digital_port *
924 enc_to_dig_port(struct drm_encoder *encoder)
926 return container_of(encoder, struct intel_digital_port, base.base);
929 static inline struct intel_dp_mst_encoder *
930 enc_to_mst(struct drm_encoder *encoder)
932 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
935 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
937 return &enc_to_dig_port(encoder)->dp;
940 static inline struct intel_digital_port *
941 dp_to_dig_port(struct intel_dp *intel_dp)
943 return container_of(intel_dp, struct intel_digital_port, dp);
946 static inline struct intel_digital_port *
947 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
949 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
953 * Returns the number of planes for this pipe, ie the number of sprites + 1
954 * (primary plane). This doesn't count the cursor plane then.
956 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
958 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
961 /* intel_fifo_underrun.c */
962 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
963 enum pipe pipe, bool enable);
964 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
965 enum transcoder pch_transcoder,
967 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
969 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
970 enum transcoder pch_transcoder);
971 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
972 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
975 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
976 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
977 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
978 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
979 void gen6_reset_rps_interrupts(struct drm_device *dev);
980 void gen6_enable_rps_interrupts(struct drm_device *dev);
981 void gen6_disable_rps_interrupts(struct drm_device *dev);
982 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
983 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
984 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
985 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
988 * We only use drm_irq_uninstall() at unload and VT switch, so
989 * this is the only thing we need to check.
991 return dev_priv->pm.irqs_enabled;
994 int intel_get_crtc_scanline(struct intel_crtc *crtc);
995 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
996 unsigned int pipe_mask);
999 void intel_crt_init(struct drm_device *dev);
1003 void intel_ddi_clk_select(struct intel_encoder *encoder,
1004 const struct intel_crtc_state *pipe_config);
1005 void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
1006 void hsw_fdi_link_train(struct drm_crtc *crtc);
1007 void intel_ddi_init(struct drm_device *dev, enum port port);
1008 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1009 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1010 void intel_ddi_pll_init(struct drm_device *dev);
1011 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1012 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1013 enum transcoder cpu_transcoder);
1014 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1015 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1016 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1017 struct intel_crtc_state *crtc_state);
1018 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1019 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1020 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1021 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1022 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1023 struct intel_crtc *intel_crtc);
1024 void intel_ddi_get_config(struct intel_encoder *encoder,
1025 struct intel_crtc_state *pipe_config);
1026 struct intel_encoder *
1027 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1029 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1030 void intel_ddi_clock_get(struct intel_encoder *encoder,
1031 struct intel_crtc_state *pipe_config);
1032 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1033 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1035 /* intel_frontbuffer.c */
1036 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1037 enum fb_op_origin origin);
1038 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1039 unsigned frontbuffer_bits);
1040 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1041 unsigned frontbuffer_bits);
1042 void intel_frontbuffer_flip(struct drm_device *dev,
1043 unsigned frontbuffer_bits);
1044 unsigned int intel_fb_align_height(struct drm_device *dev,
1045 unsigned int height,
1046 uint32_t pixel_format,
1047 uint64_t fb_format_modifier);
1048 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1049 enum fb_op_origin origin);
1050 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1051 uint64_t fb_modifier, uint32_t pixel_format);
1054 void intel_init_audio(struct drm_device *dev);
1055 void intel_audio_codec_enable(struct intel_encoder *encoder);
1056 void intel_audio_codec_disable(struct intel_encoder *encoder);
1057 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1058 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1060 /* intel_display.c */
1061 extern const struct drm_plane_funcs intel_plane_funcs;
1062 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1063 int intel_pch_rawclk(struct drm_device *dev);
1064 int intel_hrawclk(struct drm_device *dev);
1065 void intel_mark_busy(struct drm_device *dev);
1066 void intel_mark_idle(struct drm_device *dev);
1067 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1068 int intel_display_suspend(struct drm_device *dev);
1069 void intel_encoder_destroy(struct drm_encoder *encoder);
1070 int intel_connector_init(struct intel_connector *);
1071 struct intel_connector *intel_connector_alloc(void);
1072 bool intel_connector_get_hw_state(struct intel_connector *connector);
1073 void intel_connector_attach_encoder(struct intel_connector *connector,
1074 struct intel_encoder *encoder);
1075 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1076 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1077 struct drm_crtc *crtc);
1078 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1079 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1080 struct drm_file *file_priv);
1081 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1083 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1085 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1087 drm_wait_one_vblank(dev, pipe);
1090 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1092 const struct intel_crtc *crtc =
1093 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1096 intel_wait_for_vblank(dev, pipe);
1098 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1099 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1100 struct intel_digital_port *dport,
1101 unsigned int expected_mask);
1102 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1103 struct drm_display_mode *mode,
1104 struct intel_load_detect_pipe *old,
1105 struct drm_modeset_acquire_ctx *ctx);
1106 void intel_release_load_detect_pipe(struct drm_connector *connector,
1107 struct intel_load_detect_pipe *old,
1108 struct drm_modeset_acquire_ctx *ctx);
1109 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1110 struct drm_framebuffer *fb,
1111 const struct drm_plane_state *plane_state);
1112 struct drm_framebuffer *
1113 __intel_framebuffer_create(struct drm_device *dev,
1114 struct drm_mode_fb_cmd2 *mode_cmd,
1115 struct drm_i915_gem_object *obj);
1116 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1117 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1118 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1119 void intel_check_page_flip(struct drm_device *dev, int pipe);
1120 int intel_prepare_plane_fb(struct drm_plane *plane,
1121 const struct drm_plane_state *new_state);
1122 void intel_cleanup_plane_fb(struct drm_plane *plane,
1123 const struct drm_plane_state *old_state);
1124 int intel_plane_atomic_get_property(struct drm_plane *plane,
1125 const struct drm_plane_state *state,
1126 struct drm_property *property,
1128 int intel_plane_atomic_set_property(struct drm_plane *plane,
1129 struct drm_plane_state *state,
1130 struct drm_property *property,
1132 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1133 struct drm_plane_state *plane_state);
1135 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1136 uint64_t fb_modifier, unsigned int cpp);
1139 intel_rotation_90_or_270(unsigned int rotation)
1141 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1144 void intel_create_rotation_property(struct drm_device *dev,
1145 struct intel_plane *plane);
1147 /* shared dpll functions */
1148 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1149 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1150 struct intel_shared_dpll *pll,
1152 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1153 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1154 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1155 struct intel_crtc_state *state);
1157 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1158 const struct dpll *dpll);
1159 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1161 /* modesetting asserts */
1162 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1164 void assert_pll(struct drm_i915_private *dev_priv,
1165 enum pipe pipe, bool state);
1166 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1167 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1168 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1169 enum pipe pipe, bool state);
1170 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1171 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1172 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1173 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1174 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1175 unsigned long intel_compute_tile_offset(struct drm_i915_private *dev_priv,
1177 uint64_t fb_modifier,
1179 unsigned int pitch);
1180 void intel_prepare_reset(struct drm_device *dev);
1181 void intel_finish_reset(struct drm_device *dev);
1182 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1183 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1184 void broxton_init_cdclk(struct drm_device *dev);
1185 void broxton_uninit_cdclk(struct drm_device *dev);
1186 void broxton_ddi_phy_init(struct drm_device *dev);
1187 void broxton_ddi_phy_uninit(struct drm_device *dev);
1188 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1189 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1190 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1191 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
1192 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1193 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1194 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1195 void intel_dp_get_m_n(struct intel_crtc *crtc,
1196 struct intel_crtc_state *pipe_config);
1197 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1198 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1200 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1202 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1203 intel_clock_t *best_clock);
1204 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1206 bool intel_crtc_active(struct drm_crtc *crtc);
1207 void hsw_enable_ips(struct intel_crtc *crtc);
1208 void hsw_disable_ips(struct intel_crtc *crtc);
1209 enum intel_display_power_domain
1210 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1211 enum intel_display_power_domain
1212 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1213 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1214 struct intel_crtc_state *pipe_config);
1215 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1217 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1218 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1220 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1221 struct drm_i915_gem_object *obj,
1222 unsigned int plane);
1224 u32 skl_plane_ctl_format(uint32_t pixel_format);
1225 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1226 u32 skl_plane_ctl_rotation(unsigned int rotation);
1229 void intel_csr_ucode_init(struct drm_i915_private *);
1230 void intel_csr_load_program(struct drm_i915_private *);
1231 void intel_csr_ucode_fini(struct drm_i915_private *);
1234 void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1235 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1236 struct intel_connector *intel_connector);
1237 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1238 const struct intel_crtc_state *pipe_config);
1239 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1240 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1241 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1242 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1243 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1244 bool intel_dp_compute_config(struct intel_encoder *encoder,
1245 struct intel_crtc_state *pipe_config);
1246 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1247 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1249 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1250 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1251 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1252 void intel_edp_panel_on(struct intel_dp *intel_dp);
1253 void intel_edp_panel_off(struct intel_dp *intel_dp);
1254 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1255 void intel_dp_mst_suspend(struct drm_device *dev);
1256 void intel_dp_mst_resume(struct drm_device *dev);
1257 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1258 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1259 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1260 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1261 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1262 void intel_plane_destroy(struct drm_plane *plane);
1263 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1264 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1265 void intel_edp_drrs_invalidate(struct drm_device *dev,
1266 unsigned frontbuffer_bits);
1267 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1268 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1269 struct intel_digital_port *port);
1270 void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
1273 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1274 uint8_t dp_train_pat);
1276 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1277 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1279 intel_dp_voltage_max(struct intel_dp *intel_dp);
1281 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1282 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1283 uint8_t *link_bw, uint8_t *rate_select);
1284 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1286 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1288 /* intel_dp_mst.c */
1289 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1290 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1292 void intel_dsi_init(struct drm_device *dev);
1296 void intel_dvo_init(struct drm_device *dev);
1299 /* legacy fbdev emulation in intel_fbdev.c */
1300 #ifdef CONFIG_DRM_FBDEV_EMULATION
1301 extern int intel_fbdev_init(struct drm_device *dev);
1302 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1303 extern void intel_fbdev_fini(struct drm_device *dev);
1304 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1305 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1306 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1308 static inline int intel_fbdev_init(struct drm_device *dev)
1313 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1317 static inline void intel_fbdev_fini(struct drm_device *dev)
1321 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1325 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1331 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1332 void intel_fbc_deactivate(struct intel_crtc *crtc);
1333 void intel_fbc_update(struct intel_crtc *crtc);
1334 void intel_fbc_init(struct drm_i915_private *dev_priv);
1335 void intel_fbc_enable(struct intel_crtc *crtc);
1336 void intel_fbc_disable(struct drm_i915_private *dev_priv);
1337 void intel_fbc_disable_crtc(struct intel_crtc *crtc);
1338 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1339 unsigned int frontbuffer_bits,
1340 enum fb_op_origin origin);
1341 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1342 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1343 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1346 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1347 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1348 struct intel_connector *intel_connector);
1349 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1350 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1351 struct intel_crtc_state *pipe_config);
1355 void intel_lvds_init(struct drm_device *dev);
1356 bool intel_is_dual_link_lvds(struct drm_device *dev);
1360 int intel_connector_update_modes(struct drm_connector *connector,
1362 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1363 void intel_attach_force_audio_property(struct drm_connector *connector);
1364 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1365 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1368 /* intel_overlay.c */
1369 void intel_setup_overlay(struct drm_device *dev);
1370 void intel_cleanup_overlay(struct drm_device *dev);
1371 int intel_overlay_switch_off(struct intel_overlay *overlay);
1372 int intel_overlay_put_image(struct drm_device *dev, void *data,
1373 struct drm_file *file_priv);
1374 int intel_overlay_attrs(struct drm_device *dev, void *data,
1375 struct drm_file *file_priv);
1376 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1380 int intel_panel_init(struct intel_panel *panel,
1381 struct drm_display_mode *fixed_mode,
1382 struct drm_display_mode *downclock_mode);
1383 void intel_panel_fini(struct intel_panel *panel);
1384 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1385 struct drm_display_mode *adjusted_mode);
1386 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1387 struct intel_crtc_state *pipe_config,
1389 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1390 struct intel_crtc_state *pipe_config,
1392 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1393 u32 level, u32 max);
1394 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1395 void intel_panel_enable_backlight(struct intel_connector *connector);
1396 void intel_panel_disable_backlight(struct intel_connector *connector);
1397 void intel_panel_destroy_backlight(struct drm_connector *connector);
1398 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1399 extern struct drm_display_mode *intel_find_panel_downclock(
1400 struct drm_device *dev,
1401 struct drm_display_mode *fixed_mode,
1402 struct drm_connector *connector);
1403 void intel_backlight_register(struct drm_device *dev);
1404 void intel_backlight_unregister(struct drm_device *dev);
1408 void intel_psr_enable(struct intel_dp *intel_dp);
1409 void intel_psr_disable(struct intel_dp *intel_dp);
1410 void intel_psr_invalidate(struct drm_device *dev,
1411 unsigned frontbuffer_bits);
1412 void intel_psr_flush(struct drm_device *dev,
1413 unsigned frontbuffer_bits,
1414 enum fb_op_origin origin);
1415 void intel_psr_init(struct drm_device *dev);
1416 void intel_psr_single_frame_update(struct drm_device *dev,
1417 unsigned frontbuffer_bits);
1419 /* intel_runtime_pm.c */
1420 int intel_power_domains_init(struct drm_i915_private *);
1421 void intel_power_domains_fini(struct drm_i915_private *);
1422 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1423 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1424 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
1425 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
1426 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1428 intel_display_power_domain_str(enum intel_display_power_domain domain);
1430 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1431 enum intel_display_power_domain domain);
1432 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1433 enum intel_display_power_domain domain);
1434 void intel_display_power_get(struct drm_i915_private *dev_priv,
1435 enum intel_display_power_domain domain);
1436 void intel_display_power_put(struct drm_i915_private *dev_priv,
1437 enum intel_display_power_domain domain);
1440 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1442 WARN_ONCE(dev_priv->pm.suspended,
1443 "Device suspended during HW access\n");
1447 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1449 assert_rpm_device_not_suspended(dev_priv);
1450 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1451 * too much noise. */
1452 if (!atomic_read(&dev_priv->pm.wakeref_count))
1453 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1457 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1459 int seq = atomic_read(&dev_priv->pm.atomic_seq);
1461 assert_rpm_wakelock_held(dev_priv);
1467 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1469 WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1470 "HW access outside of RPM atomic section\n");
1474 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1475 * @dev_priv: i915 device instance
1477 * This function disable asserts that check if we hold an RPM wakelock
1478 * reference, while keeping the device-not-suspended checks still enabled.
1479 * It's meant to be used only in special circumstances where our rule about
1480 * the wakelock refcount wrt. the device power state doesn't hold. According
1481 * to this rule at any point where we access the HW or want to keep the HW in
1482 * an active state we must hold an RPM wakelock reference acquired via one of
1483 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1484 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1485 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1486 * users should avoid using this function.
1488 * Any calls to this function must have a symmetric call to
1489 * enable_rpm_wakeref_asserts().
1492 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1494 atomic_inc(&dev_priv->pm.wakeref_count);
1498 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1499 * @dev_priv: i915 device instance
1501 * This function re-enables the RPM assert checks after disabling them with
1502 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1503 * circumstances otherwise its use should be avoided.
1505 * Any calls to this function must have a symmetric call to
1506 * disable_rpm_wakeref_asserts().
1509 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1511 atomic_dec(&dev_priv->pm.wakeref_count);
1514 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1515 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1516 disable_rpm_wakeref_asserts(dev_priv)
1518 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1519 enable_rpm_wakeref_asserts(dev_priv)
1521 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1522 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1523 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1525 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1527 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1528 bool override, unsigned int mask);
1529 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1530 enum dpio_channel ch, bool override);
1534 void intel_init_clock_gating(struct drm_device *dev);
1535 void intel_suspend_hw(struct drm_device *dev);
1536 int ilk_wm_max_level(const struct drm_device *dev);
1537 void intel_update_watermarks(struct drm_crtc *crtc);
1538 void intel_init_pm(struct drm_device *dev);
1539 void intel_pm_setup(struct drm_device *dev);
1540 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1541 void intel_gpu_ips_teardown(void);
1542 void intel_init_gt_powersave(struct drm_device *dev);
1543 void intel_cleanup_gt_powersave(struct drm_device *dev);
1544 void intel_enable_gt_powersave(struct drm_device *dev);
1545 void intel_disable_gt_powersave(struct drm_device *dev);
1546 void intel_suspend_gt_powersave(struct drm_device *dev);
1547 void intel_reset_gt_powersave(struct drm_device *dev);
1548 void gen6_update_ring_freq(struct drm_device *dev);
1549 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1550 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1551 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1552 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1553 struct intel_rps_client *rps,
1554 unsigned long submitted);
1555 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1556 struct drm_i915_gem_request *req);
1557 void vlv_wm_get_hw_state(struct drm_device *dev);
1558 void ilk_wm_get_hw_state(struct drm_device *dev);
1559 void skl_wm_get_hw_state(struct drm_device *dev);
1560 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1561 struct skl_ddb_allocation *ddb /* out */);
1562 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1565 bool intel_sdvo_init(struct drm_device *dev,
1566 i915_reg_t reg, enum port port);
1569 /* intel_sprite.c */
1570 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1571 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1572 struct drm_file *file_priv);
1573 void intel_pipe_update_start(struct intel_crtc *crtc);
1574 void intel_pipe_update_end(struct intel_crtc *crtc);
1577 void intel_tv_init(struct drm_device *dev);
1579 /* intel_atomic.c */
1580 int intel_connector_atomic_get_property(struct drm_connector *connector,
1581 const struct drm_connector_state *state,
1582 struct drm_property *property,
1584 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1585 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1586 struct drm_crtc_state *state);
1587 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1588 void intel_atomic_state_clear(struct drm_atomic_state *);
1589 struct intel_shared_dpll_config *
1590 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1592 static inline struct intel_crtc_state *
1593 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1594 struct intel_crtc *crtc)
1596 struct drm_crtc_state *crtc_state;
1597 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1598 if (IS_ERR(crtc_state))
1599 return ERR_CAST(crtc_state);
1601 return to_intel_crtc_state(crtc_state);
1603 int intel_atomic_setup_scalers(struct drm_device *dev,
1604 struct intel_crtc *intel_crtc,
1605 struct intel_crtc_state *crtc_state);
1607 /* intel_atomic_plane.c */
1608 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1609 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1610 void intel_plane_destroy_state(struct drm_plane *plane,
1611 struct drm_plane_state *state);
1612 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1614 #endif /* __INTEL_DRV_H__ */