drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_dual_mode_helper.h>
  37 #include <drm/drm_dp_mst_helper.h>
  38 #include <drm/drm_rect.h>
  39 #include <drm/drm_atomic.h>
  40
  41 /**
  42  * _wait_for - magic (register) wait macro
  43  *
  44  * Does the right thing for modeset paths when run under kdgb or similar atomic
  45  * contexts. Note that it's important that we check the condition again after
  46  * having timed out, since the timeout could be due to preemption or similar and
  47  * we've never had a chance to check the condition before the timeout.
  48  *
  49  * TODO: When modesetting has fully transitioned to atomic, the below
  50  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  51  * added.
  52  */
  53 #define _wait_for(COND, US, W) ({ \
  54         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  55         int ret__ = 0;                                                  \
  56         while (!(COND)) {                                               \
  57                 if (time_after(jiffies, timeout__)) {                   \
  58                         if (!(COND))                                    \
  59                                 ret__ = -ETIMEDOUT;                     \
  60                         break;                                          \
  61                 }                                                       \
  62                 if ((W) && drm_can_sleep()) {                           \
  63                         usleep_range((W), (W)*2);                       \
  64                 } else {                                                \
  65                         cpu_relax();                                    \
  66                 }                                                       \
  67         }                                                               \
  68         ret__;                                                          \
  69 })
  70
  71 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  72
  73 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  74 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  75 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  76 #else
  77 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  78 #endif
  79
  80 #define _wait_for_atomic(COND, US, ATOMIC) \
  81 ({ \
  82         int cpu, ret, timeout = (US) * 1000; \
  83         u64 base; \
  84         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  85         BUILD_BUG_ON((US) > 50000); \
  86         if (!(ATOMIC)) { \
  87                 preempt_disable(); \
  88                 cpu = smp_processor_id(); \
  89         } \
  90         base = local_clock(); \
  91         for (;;) { \
  92                 u64 now = local_clock(); \
  93                 if (!(ATOMIC)) \
  94                         preempt_enable(); \
  95                 if (COND) { \
  96                         ret = 0; \
  97                         break; \
  98                 } \
  99                 if (now - base >= timeout) { \
 100                         ret = -ETIMEDOUT; \
 101                         break; \
 102                 } \
 103                 cpu_relax(); \
 104                 if (!(ATOMIC)) { \
 105                         preempt_disable(); \
 106                         if (unlikely(cpu != smp_processor_id())) { \
 107                                 timeout -= now - base; \
 108                                 cpu = smp_processor_id(); \
 109                                 base = local_clock(); \
 110                         } \
 111                 } \
 112         } \
 113         ret; \
 114 })
 115
 116 #define wait_for_us(COND, US) \
 117 ({ \
 118         int ret__; \
 119         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 120         if ((US) > 10) \
 121                 ret__ = _wait_for((COND), (US), 10); \
 122         else \
 123                 ret__ = _wait_for_atomic((COND), (US), 0); \
 124         ret__; \
 125 })
 126
 127 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 128 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 129
 130 #define KHz(x) (1000 * (x))
 131 #define MHz(x) KHz(1000 * (x))
 132
 133 /*
 134  * Display related stuff
 135  */
 136
 137 /* store information about an Ixxx DVO */
 138 /* The i830->i865 use multiple DVOs with multiple i2cs */
 139 /* the i915, i945 have a single sDVO i2c bus - which is different */
 140 #define MAX_OUTPUTS 6
 141 /* maximum connectors per crtcs in the mode set */
 142
 143 /* Maximum cursor sizes */
 144 #define GEN2_CURSOR_WIDTH 64
 145 #define GEN2_CURSOR_HEIGHT 64
 146 #define MAX_CURSOR_WIDTH 256
 147 #define MAX_CURSOR_HEIGHT 256
 148
 149 #define INTEL_I2C_BUS_DVO 1
 150 #define INTEL_I2C_BUS_SDVO 2
 151
 152 /* these are outputs from the chip - integrated only
 153    external chips are via DVO or SDVO output */
 154 enum intel_output_type {
 155         INTEL_OUTPUT_UNUSED = 0,
 156         INTEL_OUTPUT_ANALOG = 1,
 157         INTEL_OUTPUT_DVO = 2,
 158         INTEL_OUTPUT_SDVO = 3,
 159         INTEL_OUTPUT_LVDS = 4,
 160         INTEL_OUTPUT_TVOUT = 5,
 161         INTEL_OUTPUT_HDMI = 6,
 162         INTEL_OUTPUT_DP = 7,
 163         INTEL_OUTPUT_EDP = 8,
 164         INTEL_OUTPUT_DSI = 9,
 165         INTEL_OUTPUT_UNKNOWN = 10,
 166         INTEL_OUTPUT_DP_MST = 11,
 167 };
 168
 169 #define INTEL_DVO_CHIP_NONE 0
 170 #define INTEL_DVO_CHIP_LVDS 1
 171 #define INTEL_DVO_CHIP_TMDS 2
 172 #define INTEL_DVO_CHIP_TVOUT 4
 173
 174 #define INTEL_DSI_VIDEO_MODE    0
 175 #define INTEL_DSI_COMMAND_MODE  1
 176
 177 struct intel_framebuffer {
 178         struct drm_framebuffer base;
 179         struct drm_i915_gem_object *obj;
 180         struct intel_rotation_info rot_info;
 181
 182         /* for each plane in the normal GTT view */
 183         struct {
 184                 unsigned int x, y;
 185         } normal[2];
 186         /* for each plane in the rotated GTT view */
 187         struct {
 188                 unsigned int x, y;
 189                 unsigned int pitch; /* pixels */
 190         } rotated[2];
 191 };
 192
 193 struct intel_fbdev {
 194         struct drm_fb_helper helper;
 195         struct intel_framebuffer *fb;
 196         async_cookie_t cookie;
 197         int preferred_bpp;
 198 };
 199
 200 struct intel_encoder {
 201         struct drm_encoder base;
 202
 203         enum intel_output_type type;
 204         unsigned int cloneable;
 205         void (*hot_plug)(struct intel_encoder *);
 206         bool (*compute_config)(struct intel_encoder *,
 207                                struct intel_crtc_state *);
 208         void (*pre_pll_enable)(struct intel_encoder *);
 209         void (*pre_enable)(struct intel_encoder *);
 210         void (*enable)(struct intel_encoder *);
 211         void (*mode_set)(struct intel_encoder *intel_encoder);
 212         void (*disable)(struct intel_encoder *);
 213         void (*post_disable)(struct intel_encoder *);
 214         void (*post_pll_disable)(struct intel_encoder *);
 215         /* Read out the current hw state of this connector, returning true if
 216          * the encoder is active. If the encoder is enabled it also set the pipe
 217          * it is connected to in the pipe parameter. */
 218         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 219         /* Reconstructs the equivalent mode flags for the current hardware
 220          * state. This must be called _after_ display->get_pipe_config has
 221          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 222          * be set correctly before calling this function. */
 223         void (*get_config)(struct intel_encoder *,
 224                            struct intel_crtc_state *pipe_config);
 225         /*
 226          * Called during system suspend after all pending requests for the
 227          * encoder are flushed (for example for DP AUX transactions) and
 228          * device interrupts are disabled.
 229          */
 230         void (*suspend)(struct intel_encoder *);
 231         int crtc_mask;
 232         enum hpd_pin hpd_pin;
 233 };
 234
 235 struct intel_panel {
 236         struct drm_display_mode *fixed_mode;
 237         struct drm_display_mode *downclock_mode;
 238         int fitting_mode;
 239
 240         /* backlight */
 241         struct {
 242                 bool present;
 243                 u32 level;
 244                 u32 min;
 245                 u32 max;
 246                 bool enabled;
 247                 bool combination_mode;  /* gen 2/4 only */
 248                 bool active_low_pwm;
 249
 250                 /* PWM chip */
 251                 bool util_pin_active_low;       /* bxt+ */
 252                 u8 controller;          /* bxt+ only */
 253                 struct pwm_device *pwm;
 254
 255                 struct backlight_device *device;
 256
 257                 /* Connector and platform specific backlight functions */
 258                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 259                 uint32_t (*get)(struct intel_connector *connector);
 260                 void (*set)(struct intel_connector *connector, uint32_t level);
 261                 void (*disable)(struct intel_connector *connector);
 262                 void (*enable)(struct intel_connector *connector);
 263                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 264                                       uint32_t hz);
 265                 void (*power)(struct intel_connector *, bool enable);
 266         } backlight;
 267 };
 268
 269 struct intel_connector {
 270         struct drm_connector base;
 271         /*
 272          * The fixed encoder this connector is connected to.
 273          */
 274         struct intel_encoder *encoder;
 275
 276         /* Reads out the current hw, returning true if the connector is enabled
 277          * and active (i.e. dpms ON state). */
 278         bool (*get_hw_state)(struct intel_connector *);
 279
 280         /* Panel info for eDP and LVDS */
 281         struct intel_panel panel;
 282
 283         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 284         struct edid *edid;
 285         struct edid *detect_edid;
 286
 287         /* since POLL and HPD connectors may use the same HPD line keep the native
 288            state of connector->polled in case hotplug storm detection changes it */
 289         u8 polled;
 290
 291         void *port; /* store this opaque as its illegal to dereference it */
 292
 293         struct intel_dp *mst_port;
 294 };
 295
 296 struct dpll {
 297         /* given values */
 298         int n;
 299         int m1, m2;
 300         int p1, p2;
 301         /* derived values */
 302         int     dot;
 303         int     vco;
 304         int     m;
 305         int     p;
 306 };
 307
 308 struct intel_atomic_state {
 309         struct drm_atomic_state base;
 310
 311         unsigned int cdclk;
 312
 313         /*
 314          * Calculated device cdclk, can be different from cdclk
 315          * only when all crtc's are DPMS off.
 316          */
 317         unsigned int dev_cdclk;
 318
 319         bool dpll_set, modeset;
 320
 321         /*
 322          * Does this transaction change the pipes that are active?  This mask
 323          * tracks which CRTC's have changed their active state at the end of
 324          * the transaction (not counting the temporary disable during modesets).
 325          * This mask should only be non-zero when intel_state->modeset is true,
 326          * but the converse is not necessarily true; simply changing a mode may
 327          * not flip the final active status of any CRTC's
 328          */
 329         unsigned int active_pipe_changes;
 330
 331         unsigned int active_crtcs;
 332         unsigned int min_pixclk[I915_MAX_PIPES];
 333
 334         /* SKL/KBL Only */
 335         unsigned int cdclk_pll_vco;
 336
 337         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 338
 339         /*
 340          * Current watermarks can't be trusted during hardware readout, so
 341          * don't bother calculating intermediate watermarks.
 342          */
 343         bool skip_intermediate_wm;
 344
 345         /* Gen9+ only */
 346         struct skl_wm_values wm_results;
 347 };
 348
 349 struct intel_plane_state {
 350         struct drm_plane_state base;
 351         struct drm_rect src;
 352         struct drm_rect dst;
 353         struct drm_rect clip;
 354         bool visible;
 355
 356         struct {
 357                 u32 offset;
 358                 int x, y;
 359         } main;
 360
 361         /*
 362          * scaler_id
 363          *    = -1 : not using a scaler
 364          *    >=  0 : using a scalers
 365          *
 366          * plane requiring a scaler:
 367          *   - During check_plane, its bit is set in
 368          *     crtc_state->scaler_state.scaler_users by calling helper function
 369          *     update_scaler_plane.
 370          *   - scaler_id indicates the scaler it got assigned.
 371          *
 372          * plane doesn't require a scaler:
 373          *   - this can happen when scaling is no more required or plane simply
 374          *     got disabled.
 375          *   - During check_plane, corresponding bit is reset in
 376          *     crtc_state->scaler_state.scaler_users by calling helper function
 377          *     update_scaler_plane.
 378          */
 379         int scaler_id;
 380
 381         struct drm_intel_sprite_colorkey ckey;
 382
 383         /* async flip related structures */
 384         struct drm_i915_gem_request *wait_req;
 385 };
 386
 387 struct intel_initial_plane_config {
 388         struct intel_framebuffer *fb;
 389         unsigned int tiling;
 390         int size;
 391         u32 base;
 392 };
 393
 394 #define SKL_MIN_SRC_W 8
 395 #define SKL_MAX_SRC_W 4096
 396 #define SKL_MIN_SRC_H 8
 397 #define SKL_MAX_SRC_H 4096
 398 #define SKL_MIN_DST_W 8
 399 #define SKL_MAX_DST_W 4096
 400 #define SKL_MIN_DST_H 8
 401 #define SKL_MAX_DST_H 4096
 402
 403 struct intel_scaler {
 404         int in_use;
 405         uint32_t mode;
 406 };
 407
 408 struct intel_crtc_scaler_state {
 409 #define SKL_NUM_SCALERS 2
 410         struct intel_scaler scalers[SKL_NUM_SCALERS];
 411
 412         /*
 413          * scaler_users: keeps track of users requesting scalers on this crtc.
 414          *
 415          *     If a bit is set, a user is using a scaler.
 416          *     Here user can be a plane or crtc as defined below:
 417          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 418          *       bit 31    - crtc
 419          *
 420          * Instead of creating a new index to cover planes and crtc, using
 421          * existing drm_plane_index for planes which is well less than 31
 422          * planes and bit 31 for crtc. This should be fine to cover all
 423          * our platforms.
 424          *
 425          * intel_atomic_setup_scalers will setup available scalers to users
 426          * requesting scalers. It will gracefully fail if request exceeds
 427          * avilability.
 428          */
 429 #define SKL_CRTC_INDEX 31
 430         unsigned scaler_users;
 431
 432         /* scaler used by crtc for panel fitting purpose */
 433         int scaler_id;
 434 };
 435
 436 /* drm_mode->private_flags */
 437 #define I915_MODE_FLAG_INHERITED 1
 438
 439 struct intel_pipe_wm {
 440         struct intel_wm_level wm[5];
 441         struct intel_wm_level raw_wm[5];
 442         uint32_t linetime;
 443         bool fbc_wm_enabled;
 444         bool pipe_enabled;
 445         bool sprites_enabled;
 446         bool sprites_scaled;
 447 };
 448
 449 struct skl_pipe_wm {
 450         struct skl_wm_level wm[8];
 451         struct skl_wm_level trans_wm;
 452         uint32_t linetime;
 453 };
 454
 455 struct intel_crtc_wm_state {
 456         union {
 457                 struct {
 458                         /*
 459                          * Intermediate watermarks; these can be
 460                          * programmed immediately since they satisfy
 461                          * both the current configuration we're
 462                          * switching away from and the new
 463                          * configuration we're switching to.
 464                          */
 465                         struct intel_pipe_wm intermediate;
 466
 467                         /*
 468                          * Optimal watermarks, programmed post-vblank
 469                          * when this state is committed.
 470                          */
 471                         struct intel_pipe_wm optimal;
 472                 } ilk;
 473
 474                 struct {
 475                         /* gen9+ only needs 1-step wm programming */
 476                         struct skl_pipe_wm optimal;
 477
 478                         /* cached plane data rate */
 479                         unsigned plane_data_rate[I915_MAX_PLANES];
 480                         unsigned plane_y_data_rate[I915_MAX_PLANES];
 481
 482                         /* minimum block allocation */
 483                         uint16_t minimum_blocks[I915_MAX_PLANES];
 484                         uint16_t minimum_y_blocks[I915_MAX_PLANES];
 485                 } skl;
 486         };
 487
 488         /*
 489          * Platforms with two-step watermark programming will need to
 490          * update watermark programming post-vblank to switch from the
 491          * safe intermediate watermarks to the optimal final
 492          * watermarks.
 493          */
 494         bool need_postvbl_update;
 495 };
 496
 497 struct intel_crtc_state {
 498         struct drm_crtc_state base;
 499
 500         /**
 501          * quirks - bitfield with hw state readout quirks
 502          *
 503          * For various reasons the hw state readout code might not be able to
 504          * completely faithfully read out the current state. These cases are
 505          * tracked with quirk flags so that fastboot and state checker can act
 506          * accordingly.
 507          */
 508 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 509         unsigned long quirks;
 510
 511         unsigned fb_bits; /* framebuffers to flip */
 512         bool update_pipe; /* can a fast modeset be performed? */
 513         bool disable_cxsr;
 514         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 515         bool fb_changed; /* fb on any of the planes is changed */
 516
 517         /* Pipe source size (ie. panel fitter input size)
 518          * All planes will be positioned inside this space,
 519          * and get clipped at the edges. */
 520         int pipe_src_w, pipe_src_h;
 521
 522         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 523          * between pch encoders and cpu encoders. */
 524         bool has_pch_encoder;
 525
 526         /* Are we sending infoframes on the attached port */
 527         bool has_infoframe;
 528
 529         /* CPU Transcoder for the pipe. Currently this can only differ from the
 530          * pipe on Haswell and later (where we have a special eDP transcoder)
 531          * and Broxton (where we have special DSI transcoders). */
 532         enum transcoder cpu_transcoder;
 533
 534         /*
 535          * Use reduced/limited/broadcast rbg range, compressing from the full
 536          * range fed into the crtcs.
 537          */
 538         bool limited_color_range;
 539
 540         /* Bitmask of encoder types (enum intel_output_type)
 541          * driven by the pipe.
 542          */
 543         unsigned int output_types;
 544
 545         /* Whether we should send NULL infoframes. Required for audio. */
 546         bool has_hdmi_sink;
 547
 548         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 549          * has_dp_encoder is set. */
 550         bool has_audio;
 551
 552         /*
 553          * Enable dithering, used when the selected pipe bpp doesn't match the
 554          * plane bpp.
 555          */
 556         bool dither;
 557
 558         /* Controls for the clock computation, to override various stages. */
 559         bool clock_set;
 560
 561         /* SDVO TV has a bunch of special case. To make multifunction encoders
 562          * work correctly, we need to track this at runtime.*/
 563         bool sdvo_tv_clock;
 564
 565         /*
 566          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 567          * required. This is set in the 2nd loop of calling encoder's
 568          * ->compute_config if the first pick doesn't work out.
 569          */
 570         bool bw_constrained;
 571
 572         /* Settings for the intel dpll used on pretty much everything but
 573          * haswell. */
 574         struct dpll dpll;
 575
 576         /* Selected dpll when shared or NULL. */
 577         struct intel_shared_dpll *shared_dpll;
 578
 579         /*
 580          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 581          * - enum skl_dpll on SKL
 582          */
 583         uint32_t ddi_pll_sel;
 584
 585         /* Actual register state of the dpll, for shared dpll cross-checking. */
 586         struct intel_dpll_hw_state dpll_hw_state;
 587
 588         /* DSI PLL registers */
 589         struct {
 590                 u32 ctrl, div;
 591         } dsi_pll;
 592
 593         int pipe_bpp;
 594         struct intel_link_m_n dp_m_n;
 595
 596         /* m2_n2 for eDP downclock */
 597         struct intel_link_m_n dp_m2_n2;
 598         bool has_drrs;
 599
 600         /*
 601          * Frequence the dpll for the port should run at. Differs from the
 602          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 603          * already multiplied by pixel_multiplier.
 604          */
 605         int port_clock;
 606
 607         /* Used by SDVO (and if we ever fix it, HDMI). */
 608         unsigned pixel_multiplier;
 609
 610         uint8_t lane_count;
 611
 612         /*
 613          * Used by platforms having DP/HDMI PHY with programmable lane
 614          * latency optimization.
 615          */
 616         uint8_t lane_lat_optim_mask;
 617
 618         /* Panel fitter controls for gen2-gen4 + VLV */
 619         struct {
 620                 u32 control;
 621                 u32 pgm_ratios;
 622                 u32 lvds_border_bits;
 623         } gmch_pfit;
 624
 625         /* Panel fitter placement and size for Ironlake+ */
 626         struct {
 627                 u32 pos;
 628                 u32 size;
 629                 bool enabled;
 630                 bool force_thru;
 631         } pch_pfit;
 632
 633         /* FDI configuration, only valid if has_pch_encoder is set. */
 634         int fdi_lanes;
 635         struct intel_link_m_n fdi_m_n;
 636
 637         bool ips_enabled;
 638
 639         bool enable_fbc;
 640
 641         bool double_wide;
 642
 643         bool dp_encoder_is_mst;
 644         int pbn;
 645
 646         struct intel_crtc_scaler_state scaler_state;
 647
 648         /* w/a for waiting 2 vblanks during crtc enable */
 649         enum pipe hsw_workaround_pipe;
 650
 651         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 652         bool disable_lp_wm;
 653
 654         struct intel_crtc_wm_state wm;
 655
 656         /* Gamma mode programmed on the pipe */
 657         uint32_t gamma_mode;
 658 };
 659
 660 struct vlv_wm_state {
 661         struct vlv_pipe_wm wm[3];
 662         struct vlv_sr_wm sr[3];
 663         uint8_t num_active_planes;
 664         uint8_t num_levels;
 665         uint8_t level;
 666         bool cxsr;
 667 };
 668
 669 struct intel_crtc {
 670         struct drm_crtc base;
 671         enum pipe pipe;
 672         enum plane plane;
 673         u8 lut_r[256], lut_g[256], lut_b[256];
 674         /*
 675          * Whether the crtc and the connected output pipeline is active. Implies
 676          * that crtc->enabled is set, i.e. the current mode configuration has
 677          * some outputs connected to this crtc.
 678          */
 679         bool active;
 680         unsigned long enabled_power_domains;
 681         bool lowfreq_avail;
 682         struct intel_overlay *overlay;
 683         struct intel_flip_work *flip_work;
 684
 685         atomic_t unpin_work_count;
 686
 687         /* Display surface base address adjustement for pageflips. Note that on
 688          * gen4+ this only adjusts up to a tile, offsets within a tile are
 689          * handled in the hw itself (with the TILEOFF register). */
 690         u32 dspaddr_offset;
 691         int adjusted_x;
 692         int adjusted_y;
 693
 694         uint32_t cursor_addr;
 695         uint32_t cursor_cntl;
 696         uint32_t cursor_size;
 697         uint32_t cursor_base;
 698
 699         struct intel_crtc_state *config;
 700
 701         /* reset counter value when the last flip was submitted */
 702         unsigned int reset_counter;
 703
 704         /* Access to these should be protected by dev_priv->irq_lock. */
 705         bool cpu_fifo_underrun_disabled;
 706         bool pch_fifo_underrun_disabled;
 707
 708         /* per-pipe watermark state */
 709         struct {
 710                 /* watermarks currently being used  */
 711                 union {
 712                         struct intel_pipe_wm ilk;
 713                         struct skl_pipe_wm skl;
 714                 } active;
 715
 716                 /* allow CxSR on this pipe */
 717                 bool cxsr_allowed;
 718         } wm;
 719
 720         int scanline_offset;
 721
 722         struct {
 723                 unsigned start_vbl_count;
 724                 ktime_t start_vbl_time;
 725                 int min_vbl, max_vbl;
 726                 int scanline_start;
 727         } debug;
 728
 729         /* scalers available on this crtc */
 730         int num_scalers;
 731
 732         struct vlv_wm_state wm_state;
 733 };
 734
 735 struct intel_plane_wm_parameters {
 736         uint32_t horiz_pixels;
 737         uint32_t vert_pixels;
 738         /*
 739          *   For packed pixel formats:
 740          *     bytes_per_pixel - holds bytes per pixel
 741          *   For planar pixel formats:
 742          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 743          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 744          */
 745         uint8_t bytes_per_pixel;
 746         uint8_t y_bytes_per_pixel;
 747         bool enabled;
 748         bool scaled;
 749         u64 tiling;
 750         unsigned int rotation;
 751         uint16_t fifo_size;
 752 };
 753
 754 struct intel_plane {
 755         struct drm_plane base;
 756         int plane;
 757         enum pipe pipe;
 758         bool can_scale;
 759         int max_downscale;
 760         uint32_t frontbuffer_bit;
 761
 762         /* Since we need to change the watermarks before/after
 763          * enabling/disabling the planes, we need to store the parameters here
 764          * as the other pieces of the struct may not reflect the values we want
 765          * for the watermark calculations. Currently only Haswell uses this.
 766          */
 767         struct intel_plane_wm_parameters wm;
 768
 769         /*
 770          * NOTE: Do not place new plane state fields here (e.g., when adding
 771          * new plane properties).  New runtime state should now be placed in
 772          * the intel_plane_state structure and accessed via plane_state.
 773          */
 774
 775         void (*update_plane)(struct drm_plane *plane,
 776                              const struct intel_crtc_state *crtc_state,
 777                              const struct intel_plane_state *plane_state);
 778         void (*disable_plane)(struct drm_plane *plane,
 779                               struct drm_crtc *crtc);
 780         int (*check_plane)(struct drm_plane *plane,
 781                            struct intel_crtc_state *crtc_state,
 782                            struct intel_plane_state *state);
 783 };
 784
 785 struct intel_watermark_params {
 786         unsigned long fifo_size;
 787         unsigned long max_wm;
 788         unsigned long default_wm;
 789         unsigned long guard_size;
 790         unsigned long cacheline_size;
 791 };
 792
 793 struct cxsr_latency {
 794         int is_desktop;
 795         int is_ddr3;
 796         unsigned long fsb_freq;
 797         unsigned long mem_freq;
 798         unsigned long display_sr;
 799         unsigned long display_hpll_disable;
 800         unsigned long cursor_sr;
 801         unsigned long cursor_hpll_disable;
 802 };
 803
 804 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 805 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 806 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 807 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 808 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 809 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 810 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 811 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 812 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 813
 814 struct intel_hdmi {
 815         i915_reg_t hdmi_reg;
 816         int ddc_bus;
 817         struct {
 818                 enum drm_dp_dual_mode_type type;
 819                 int max_tmds_clock;
 820         } dp_dual_mode;
 821         bool limited_color_range;
 822         bool color_range_auto;
 823         bool has_hdmi_sink;
 824         bool has_audio;
 825         enum hdmi_force_audio force_audio;
 826         bool rgb_quant_range_selectable;
 827         enum hdmi_picture_aspect aspect_ratio;
 828         struct intel_connector *attached_connector;
 829         void (*write_infoframe)(struct drm_encoder *encoder,
 830                                 enum hdmi_infoframe_type type,
 831                                 const void *frame, ssize_t len);
 832         void (*set_infoframes)(struct drm_encoder *encoder,
 833                                bool enable,
 834                                const struct drm_display_mode *adjusted_mode);
 835         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 836                                   const struct intel_crtc_state *pipe_config);
 837 };
 838
 839 struct intel_dp_mst_encoder;
 840 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 841
 842 /*
 843  * enum link_m_n_set:
 844  *      When platform provides two set of M_N registers for dp, we can
 845  *      program them and switch between them incase of DRRS.
 846  *      But When only one such register is provided, we have to program the
 847  *      required divider value on that registers itself based on the DRRS state.
 848  *
 849  * M1_N1        : Program dp_m_n on M1_N1 registers
 850  *                        dp_m2_n2 on M2_N2 registers (If supported)
 851  *
 852  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 853  *                        M2_N2 registers are not supported
 854  */
 855
 856 enum link_m_n_set {
 857         /* Sets the m1_n1 and m2_n2 */
 858         M1_N1 = 0,
 859         M2_N2
 860 };
 861
 862 struct intel_dp {
 863         i915_reg_t output_reg;
 864         i915_reg_t aux_ch_ctl_reg;
 865         i915_reg_t aux_ch_data_reg[5];
 866         uint32_t DP;
 867         int link_rate;
 868         uint8_t lane_count;
 869         uint8_t sink_count;
 870         bool link_mst;
 871         bool has_audio;
 872         bool detect_done;
 873         enum hdmi_force_audio force_audio;
 874         bool limited_color_range;
 875         bool color_range_auto;
 876         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 877         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 878         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 879         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 880         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 881         uint8_t num_sink_rates;
 882         int sink_rates[DP_MAX_SUPPORTED_RATES];
 883         struct drm_dp_aux aux;
 884         uint8_t train_set[4];
 885         int panel_power_up_delay;
 886         int panel_power_down_delay;
 887         int panel_power_cycle_delay;
 888         int backlight_on_delay;
 889         int backlight_off_delay;
 890         struct delayed_work panel_vdd_work;
 891         bool want_panel_vdd;
 892         unsigned long last_power_on;
 893         unsigned long last_backlight_off;
 894         ktime_t panel_power_off_time;
 895
 896         struct notifier_block edp_notifier;
 897
 898         /*
 899          * Pipe whose power sequencer is currently locked into
 900          * this port. Only relevant on VLV/CHV.
 901          */
 902         enum pipe pps_pipe;
 903         /*
 904          * Set if the sequencer may be reset due to a power transition,
 905          * requiring a reinitialization. Only relevant on BXT.
 906          */
 907         bool pps_reset;
 908         struct edp_power_seq pps_delays;
 909
 910         bool can_mst; /* this port supports mst */
 911         bool is_mst;
 912         int active_mst_links;
 913         /* connector directly attached - won't be use for modeset in mst world */
 914         struct intel_connector *attached_connector;
 915
 916         /* mst connector list */
 917         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 918         struct drm_dp_mst_topology_mgr mst_mgr;
 919
 920         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 921         /*
 922          * This function returns the value we have to program the AUX_CTL
 923          * register with to kick off an AUX transaction.
 924          */
 925         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 926                                      bool has_aux_irq,
 927                                      int send_bytes,
 928                                      uint32_t aux_clock_divider);
 929
 930         /* This is called before a link training is starterd */
 931         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 932
 933         /* Displayport compliance testing */
 934         unsigned long compliance_test_type;
 935         unsigned long compliance_test_data;
 936         bool compliance_test_active;
 937 };
 938
 939 struct intel_digital_port {
 940         struct intel_encoder base;
 941         enum port port;
 942         u32 saved_port_bits;
 943         struct intel_dp dp;
 944         struct intel_hdmi hdmi;
 945         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 946         bool release_cl2_override;
 947         uint8_t max_lanes;
 948         /* for communication with audio component; protected by av_mutex */
 949         const struct drm_connector *audio_connector;
 950 };
 951
 952 struct intel_dp_mst_encoder {
 953         struct intel_encoder base;
 954         enum pipe pipe;
 955         struct intel_digital_port *primary;
 956         struct intel_connector *connector;
 957 };
 958
 959 static inline enum dpio_channel
 960 vlv_dport_to_channel(struct intel_digital_port *dport)
 961 {
 962         switch (dport->port) {
 963         case PORT_B:
 964         case PORT_D:
 965                 return DPIO_CH0;
 966         case PORT_C:
 967                 return DPIO_CH1;
 968         default:
 969                 BUG();
 970         }
 971 }
 972
 973 static inline enum dpio_phy
 974 vlv_dport_to_phy(struct intel_digital_port *dport)
 975 {
 976         switch (dport->port) {
 977         case PORT_B:
 978         case PORT_C:
 979                 return DPIO_PHY0;
 980         case PORT_D:
 981                 return DPIO_PHY1;
 982         default:
 983                 BUG();
 984         }
 985 }
 986
 987 static inline enum dpio_channel
 988 vlv_pipe_to_channel(enum pipe pipe)
 989 {
 990         switch (pipe) {
 991         case PIPE_A:
 992         case PIPE_C:
 993                 return DPIO_CH0;
 994         case PIPE_B:
 995                 return DPIO_CH1;
 996         default:
 997                 BUG();
 998         }
 999 }
1000
1001 static inline struct drm_crtc *
1002 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
1003 {
1004         struct drm_i915_private *dev_priv = to_i915(dev);
1005         return dev_priv->pipe_to_crtc_mapping[pipe];
1006 }
1007
1008 static inline struct drm_crtc *
1009 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
1010 {
1011         struct drm_i915_private *dev_priv = to_i915(dev);
1012         return dev_priv->plane_to_crtc_mapping[plane];
1013 }
1014
1015 struct intel_flip_work {
1016         struct work_struct unpin_work;
1017         struct work_struct mmio_work;
1018
1019         struct drm_crtc *crtc;
1020         struct drm_framebuffer *old_fb;
1021         struct drm_i915_gem_object *pending_flip_obj;
1022         struct drm_pending_vblank_event *event;
1023         atomic_t pending;
1024         u32 flip_count;
1025         u32 gtt_offset;
1026         struct drm_i915_gem_request *flip_queued_req;
1027         u32 flip_queued_vblank;
1028         u32 flip_ready_vblank;
1029         unsigned int rotation;
1030 };
1031
1032 struct intel_load_detect_pipe {
1033         struct drm_atomic_state *restore_state;
1034 };
1035
1036 static inline struct intel_encoder *
1037 intel_attached_encoder(struct drm_connector *connector)
1038 {
1039         return to_intel_connector(connector)->encoder;
1040 }
1041
1042 static inline struct intel_digital_port *
1043 enc_to_dig_port(struct drm_encoder *encoder)
1044 {
1045         return container_of(encoder, struct intel_digital_port, base.base);
1046 }
1047
1048 static inline struct intel_dp_mst_encoder *
1049 enc_to_mst(struct drm_encoder *encoder)
1050 {
1051         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1052 }
1053
1054 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1055 {
1056         return &enc_to_dig_port(encoder)->dp;
1057 }
1058
1059 static inline struct intel_digital_port *
1060 dp_to_dig_port(struct intel_dp *intel_dp)
1061 {
1062         return container_of(intel_dp, struct intel_digital_port, dp);
1063 }
1064
1065 static inline struct intel_digital_port *
1066 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1067 {
1068         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1069 }
1070
1071 /*
1072  * Returns the number of planes for this pipe, ie the number of sprites + 1
1073  * (primary plane). This doesn't count the cursor plane then.
1074  */
1075 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1076 {
1077         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1078 }
1079
1080 /* intel_fifo_underrun.c */
1081 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1082                                            enum pipe pipe, bool enable);
1083 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1084                                            enum transcoder pch_transcoder,
1085                                            bool enable);
1086 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1087                                          enum pipe pipe);
1088 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1089                                          enum transcoder pch_transcoder);
1090 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1091 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1092
1093 /* i915_irq.c */
1094 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1095 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1096 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1097 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1098 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1099 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1100 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1101 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1102 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1103 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1104 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1105 {
1106         /*
1107          * We only use drm_irq_uninstall() at unload and VT switch, so
1108          * this is the only thing we need to check.
1109          */
1110         return dev_priv->pm.irqs_enabled;
1111 }
1112
1113 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1114 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1115                                      unsigned int pipe_mask);
1116 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1117                                      unsigned int pipe_mask);
1118
1119 /* intel_crt.c */
1120 void intel_crt_init(struct drm_device *dev);
1121 void intel_crt_reset(struct drm_encoder *encoder);
1122
1123 /* intel_ddi.c */
1124 void intel_ddi_clk_select(struct intel_encoder *encoder,
1125                           const struct intel_crtc_state *pipe_config);
1126 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1127 void hsw_fdi_link_train(struct drm_crtc *crtc);
1128 void intel_ddi_init(struct drm_device *dev, enum port port);
1129 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1130 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1131 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1132 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1133                                        enum transcoder cpu_transcoder);
1134 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1135 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1136 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1137                           struct intel_crtc_state *crtc_state);
1138 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1139 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1140 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1141 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1142 void intel_ddi_get_config(struct intel_encoder *encoder,
1143                           struct intel_crtc_state *pipe_config);
1144 struct intel_encoder *
1145 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1146
1147 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1148 void intel_ddi_clock_get(struct intel_encoder *encoder,
1149                          struct intel_crtc_state *pipe_config);
1150 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1151 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1152
1153 unsigned int intel_fb_align_height(struct drm_device *dev,
1154                                    unsigned int height,
1155                                    uint32_t pixel_format,
1156                                    uint64_t fb_format_modifier);
1157 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1158                               uint64_t fb_modifier, uint32_t pixel_format);
1159
1160 /* intel_audio.c */
1161 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1162 void intel_audio_codec_enable(struct intel_encoder *encoder);
1163 void intel_audio_codec_disable(struct intel_encoder *encoder);
1164 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1165 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1166
1167 /* intel_display.c */
1168 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1169 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1170 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1171                       const char *name, u32 reg, int ref_freq);
1172 extern const struct drm_plane_funcs intel_plane_funcs;
1173 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1174 unsigned int intel_fb_xy_to_linear(int x, int y,
1175                                    const struct intel_plane_state *state,
1176                                    int plane);
1177 void intel_add_fb_offsets(int *x, int *y,
1178                           const struct intel_plane_state *state, int plane);
1179 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1180 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1181 void intel_mark_busy(struct drm_i915_private *dev_priv);
1182 void intel_mark_idle(struct drm_i915_private *dev_priv);
1183 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1184 int intel_display_suspend(struct drm_device *dev);
1185 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1186 void intel_encoder_destroy(struct drm_encoder *encoder);
1187 int intel_connector_init(struct intel_connector *);
1188 struct intel_connector *intel_connector_alloc(void);
1189 bool intel_connector_get_hw_state(struct intel_connector *connector);
1190 void intel_connector_attach_encoder(struct intel_connector *connector,
1191                                     struct intel_encoder *encoder);
1192 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1193                                              struct drm_crtc *crtc);
1194 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1195 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1196                                 struct drm_file *file_priv);
1197 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1198                                              enum pipe pipe);
1199 static inline bool
1200 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1201                     enum intel_output_type type)
1202 {
1203         return crtc_state->output_types & (1 << type);
1204 }
1205 static inline bool
1206 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1207 {
1208         return crtc_state->output_types &
1209                 ((1 << INTEL_OUTPUT_DP) |
1210                  (1 << INTEL_OUTPUT_DP_MST) |
1211                  (1 << INTEL_OUTPUT_EDP));
1212 }
1213 static inline void
1214 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1215 {
1216         drm_wait_one_vblank(dev, pipe);
1217 }
1218 static inline void
1219 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1220 {
1221         const struct intel_crtc *crtc =
1222                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1223
1224         if (crtc->active)
1225                 intel_wait_for_vblank(dev, pipe);
1226 }
1227
1228 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1229
1230 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1231 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1232                          struct intel_digital_port *dport,
1233                          unsigned int expected_mask);
1234 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1235                                 struct drm_display_mode *mode,
1236                                 struct intel_load_detect_pipe *old,
1237                                 struct drm_modeset_acquire_ctx *ctx);
1238 void intel_release_load_detect_pipe(struct drm_connector *connector,
1239                                     struct intel_load_detect_pipe *old,
1240                                     struct drm_modeset_acquire_ctx *ctx);
1241 int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1242                                unsigned int rotation);
1243 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1244 struct drm_framebuffer *
1245 __intel_framebuffer_create(struct drm_device *dev,
1246                            struct drm_mode_fb_cmd2 *mode_cmd,
1247                            struct drm_i915_gem_object *obj);
1248 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1249 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1250 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1251 int intel_prepare_plane_fb(struct drm_plane *plane,
1252                            const struct drm_plane_state *new_state);
1253 void intel_cleanup_plane_fb(struct drm_plane *plane,
1254                             const struct drm_plane_state *old_state);
1255 int intel_plane_atomic_get_property(struct drm_plane *plane,
1256                                     const struct drm_plane_state *state,
1257                                     struct drm_property *property,
1258                                     uint64_t *val);
1259 int intel_plane_atomic_set_property(struct drm_plane *plane,
1260                                     struct drm_plane_state *state,
1261                                     struct drm_property *property,
1262                                     uint64_t val);
1263 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1264                                     struct drm_plane_state *plane_state);
1265
1266 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1267                                uint64_t fb_modifier, unsigned int cpp);
1268
1269 static inline bool
1270 intel_rotation_90_or_270(unsigned int rotation)
1271 {
1272         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1273 }
1274
1275 void intel_create_rotation_property(struct drm_device *dev,
1276                                         struct intel_plane *plane);
1277
1278 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1279                                     enum pipe pipe);
1280
1281 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1282                      const struct dpll *dpll);
1283 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1284 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1285
1286 /* modesetting asserts */
1287 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1288                            enum pipe pipe);
1289 void assert_pll(struct drm_i915_private *dev_priv,
1290                 enum pipe pipe, bool state);
1291 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1292 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1293 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1294 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1295 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1296 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1297                        enum pipe pipe, bool state);
1298 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1299 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1300 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1301 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1302 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1303 u32 intel_compute_tile_offset(int *x, int *y,
1304                               const struct intel_plane_state *state, int plane);
1305 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1306 void intel_finish_reset(struct drm_i915_private *dev_priv);
1307 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1308 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1309 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1310 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1311 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1312 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1313 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1314                             enum dpio_phy phy);
1315 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1316                               enum dpio_phy phy);
1317 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1318 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1319 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1320 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1321 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1322 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1323 unsigned int skl_cdclk_get_vco(unsigned int freq);
1324 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1325 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1326 void intel_dp_get_m_n(struct intel_crtc *crtc,
1327                       struct intel_crtc_state *pipe_config);
1328 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1329 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1330 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1331                         struct dpll *best_clock);
1332 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1333
1334 bool intel_crtc_active(struct drm_crtc *crtc);
1335 void hsw_enable_ips(struct intel_crtc *crtc);
1336 void hsw_disable_ips(struct intel_crtc *crtc);
1337 enum intel_display_power_domain
1338 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1339 enum intel_display_power_domain
1340 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1341 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1342                                  struct intel_crtc_state *pipe_config);
1343
1344 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1345 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1346
1347 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, unsigned int rotation);
1348
1349 u32 skl_plane_ctl_format(uint32_t pixel_format);
1350 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1351 u32 skl_plane_ctl_rotation(unsigned int rotation);
1352 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1353                      unsigned int rotation);
1354 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1355
1356 /* intel_csr.c */
1357 void intel_csr_ucode_init(struct drm_i915_private *);
1358 void intel_csr_load_program(struct drm_i915_private *);
1359 void intel_csr_ucode_fini(struct drm_i915_private *);
1360 void intel_csr_ucode_suspend(struct drm_i915_private *);
1361 void intel_csr_ucode_resume(struct drm_i915_private *);
1362
1363 /* intel_dp.c */
1364 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1365 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1366                              struct intel_connector *intel_connector);
1367 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1368                               const struct intel_crtc_state *pipe_config);
1369 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1370 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1371 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1372 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1373 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1374 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1375 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1376 bool intel_dp_compute_config(struct intel_encoder *encoder,
1377                              struct intel_crtc_state *pipe_config);
1378 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1379 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1380                                   bool long_hpd);
1381 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1382 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1383 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1384 void intel_edp_panel_on(struct intel_dp *intel_dp);
1385 void intel_edp_panel_off(struct intel_dp *intel_dp);
1386 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1387 void intel_dp_mst_suspend(struct drm_device *dev);
1388 void intel_dp_mst_resume(struct drm_device *dev);
1389 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1390 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1391 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1392 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1393 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1394 void intel_plane_destroy(struct drm_plane *plane);
1395 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1396 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1397 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1398                                unsigned int frontbuffer_bits);
1399 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1400                           unsigned int frontbuffer_bits);
1401 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1402                                   struct intel_digital_port *port);
1403
1404 void
1405 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1406                                        uint8_t dp_train_pat);
1407 void
1408 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1409 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1410 uint8_t
1411 intel_dp_voltage_max(struct intel_dp *intel_dp);
1412 uint8_t
1413 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1414 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1415                            uint8_t *link_bw, uint8_t *rate_select);
1416 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1417 bool
1418 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1419
1420 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1421 {
1422         return ~((1 << lane_count) - 1) & 0xf;
1423 }
1424
1425 /* intel_dp_aux_backlight.c */
1426 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1427
1428 /* intel_dp_mst.c */
1429 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1430 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1431 /* intel_dsi.c */
1432 void intel_dsi_init(struct drm_device *dev);
1433
1434 /* intel_dsi_dcs_backlight.c */
1435 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1436
1437 /* intel_dvo.c */
1438 void intel_dvo_init(struct drm_device *dev);
1439 /* intel_hotplug.c */
1440 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1441
1442
1443 /* legacy fbdev emulation in intel_fbdev.c */
1444 #ifdef CONFIG_DRM_FBDEV_EMULATION
1445 extern int intel_fbdev_init(struct drm_device *dev);
1446 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1447 extern void intel_fbdev_fini(struct drm_device *dev);
1448 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1449 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1450 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1451 #else
1452 static inline int intel_fbdev_init(struct drm_device *dev)
1453 {
1454         return 0;
1455 }
1456
1457 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1458 {
1459 }
1460
1461 static inline void intel_fbdev_fini(struct drm_device *dev)
1462 {
1463 }
1464
1465 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1466 {
1467 }
1468
1469 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1470 {
1471 }
1472 #endif
1473
1474 /* intel_fbc.c */
1475 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1476                            struct drm_atomic_state *state);
1477 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1478 void intel_fbc_pre_update(struct intel_crtc *crtc,
1479                           struct intel_crtc_state *crtc_state,
1480                           struct intel_plane_state *plane_state);
1481 void intel_fbc_post_update(struct intel_crtc *crtc);
1482 void intel_fbc_init(struct drm_i915_private *dev_priv);
1483 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1484 void intel_fbc_enable(struct intel_crtc *crtc,
1485                       struct intel_crtc_state *crtc_state,
1486                       struct intel_plane_state *plane_state);
1487 void intel_fbc_disable(struct intel_crtc *crtc);
1488 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1489 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1490                           unsigned int frontbuffer_bits,
1491                           enum fb_op_origin origin);
1492 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1493                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1494 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1495
1496 /* intel_hdmi.c */
1497 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1498 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1499                                struct intel_connector *intel_connector);
1500 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1501 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1502                                struct intel_crtc_state *pipe_config);
1503 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1504
1505
1506 /* intel_lvds.c */
1507 void intel_lvds_init(struct drm_device *dev);
1508 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1509 bool intel_is_dual_link_lvds(struct drm_device *dev);
1510
1511
1512 /* intel_modes.c */
1513 int intel_connector_update_modes(struct drm_connector *connector,
1514                                  struct edid *edid);
1515 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1516 void intel_attach_force_audio_property(struct drm_connector *connector);
1517 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1518 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1519
1520
1521 /* intel_overlay.c */
1522 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1523 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1524 int intel_overlay_switch_off(struct intel_overlay *overlay);
1525 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1526                                   struct drm_file *file_priv);
1527 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1528                               struct drm_file *file_priv);
1529 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1530
1531
1532 /* intel_panel.c */
1533 int intel_panel_init(struct intel_panel *panel,
1534                      struct drm_display_mode *fixed_mode,
1535                      struct drm_display_mode *downclock_mode);
1536 void intel_panel_fini(struct intel_panel *panel);
1537 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1538                             struct drm_display_mode *adjusted_mode);
1539 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1540                              struct intel_crtc_state *pipe_config,
1541                              int fitting_mode);
1542 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1543                               struct intel_crtc_state *pipe_config,
1544                               int fitting_mode);
1545 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1546                                     u32 level, u32 max);
1547 int intel_panel_setup_backlight(struct drm_connector *connector,
1548                                 enum pipe pipe);
1549 void intel_panel_enable_backlight(struct intel_connector *connector);
1550 void intel_panel_disable_backlight(struct intel_connector *connector);
1551 void intel_panel_destroy_backlight(struct drm_connector *connector);
1552 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1553 extern struct drm_display_mode *intel_find_panel_downclock(
1554                                 struct drm_device *dev,
1555                                 struct drm_display_mode *fixed_mode,
1556                                 struct drm_connector *connector);
1557
1558 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1559 int intel_backlight_device_register(struct intel_connector *connector);
1560 void intel_backlight_device_unregister(struct intel_connector *connector);
1561 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1562 static int intel_backlight_device_register(struct intel_connector *connector)
1563 {
1564         return 0;
1565 }
1566 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1567 {
1568 }
1569 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1570
1571
1572 /* intel_psr.c */
1573 void intel_psr_enable(struct intel_dp *intel_dp);
1574 void intel_psr_disable(struct intel_dp *intel_dp);
1575 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1576                           unsigned frontbuffer_bits);
1577 void intel_psr_flush(struct drm_i915_private *dev_priv,
1578                      unsigned frontbuffer_bits,
1579                      enum fb_op_origin origin);
1580 void intel_psr_init(struct drm_device *dev);
1581 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1582                                    unsigned frontbuffer_bits);
1583
1584 /* intel_runtime_pm.c */
1585 int intel_power_domains_init(struct drm_i915_private *);
1586 void intel_power_domains_fini(struct drm_i915_private *);
1587 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1588 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1589 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1590 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1591 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1592 const char *
1593 intel_display_power_domain_str(enum intel_display_power_domain domain);
1594
1595 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1596                                     enum intel_display_power_domain domain);
1597 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1598                                       enum intel_display_power_domain domain);
1599 void intel_display_power_get(struct drm_i915_private *dev_priv,
1600                              enum intel_display_power_domain domain);
1601 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1602                                         enum intel_display_power_domain domain);
1603 void intel_display_power_put(struct drm_i915_private *dev_priv,
1604                              enum intel_display_power_domain domain);
1605
1606 static inline void
1607 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1608 {
1609         WARN_ONCE(dev_priv->pm.suspended,
1610                   "Device suspended during HW access\n");
1611 }
1612
1613 static inline void
1614 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1615 {
1616         assert_rpm_device_not_suspended(dev_priv);
1617         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1618          * too much noise. */
1619         if (!atomic_read(&dev_priv->pm.wakeref_count))
1620                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1621 }
1622
1623 static inline int
1624 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1625 {
1626         int seq = atomic_read(&dev_priv->pm.atomic_seq);
1627
1628         assert_rpm_wakelock_held(dev_priv);
1629
1630         return seq;
1631 }
1632
1633 static inline void
1634 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1635 {
1636         WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1637                   "HW access outside of RPM atomic section\n");
1638 }
1639
1640 /**
1641  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1642  * @dev_priv: i915 device instance
1643  *
1644  * This function disable asserts that check if we hold an RPM wakelock
1645  * reference, while keeping the device-not-suspended checks still enabled.
1646  * It's meant to be used only in special circumstances where our rule about
1647  * the wakelock refcount wrt. the device power state doesn't hold. According
1648  * to this rule at any point where we access the HW or want to keep the HW in
1649  * an active state we must hold an RPM wakelock reference acquired via one of
1650  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1651  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1652  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1653  * users should avoid using this function.
1654  *
1655  * Any calls to this function must have a symmetric call to
1656  * enable_rpm_wakeref_asserts().
1657  */
1658 static inline void
1659 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1660 {
1661         atomic_inc(&dev_priv->pm.wakeref_count);
1662 }
1663
1664 /**
1665  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1666  * @dev_priv: i915 device instance
1667  *
1668  * This function re-enables the RPM assert checks after disabling them with
1669  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1670  * circumstances otherwise its use should be avoided.
1671  *
1672  * Any calls to this function must have a symmetric call to
1673  * disable_rpm_wakeref_asserts().
1674  */
1675 static inline void
1676 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1677 {
1678         atomic_dec(&dev_priv->pm.wakeref_count);
1679 }
1680
1681 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1682 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1683 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1684 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1685
1686 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1687
1688 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1689                              bool override, unsigned int mask);
1690 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1691                           enum dpio_channel ch, bool override);
1692
1693
1694 /* intel_pm.c */
1695 void intel_init_clock_gating(struct drm_device *dev);
1696 void intel_suspend_hw(struct drm_device *dev);
1697 int ilk_wm_max_level(const struct drm_device *dev);
1698 void intel_update_watermarks(struct drm_crtc *crtc);
1699 void intel_init_pm(struct drm_device *dev);
1700 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1701 void intel_pm_setup(struct drm_device *dev);
1702 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1703 void intel_gpu_ips_teardown(void);
1704 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1705 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1706 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1707 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1708 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1709 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1710 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1711 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1712 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1713 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1714 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1715                     struct intel_rps_client *rps,
1716                     unsigned long submitted);
1717 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1718 void vlv_wm_get_hw_state(struct drm_device *dev);
1719 void ilk_wm_get_hw_state(struct drm_device *dev);
1720 void skl_wm_get_hw_state(struct drm_device *dev);
1721 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1722                           struct skl_ddb_allocation *ddb /* out */);
1723 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1724 bool ilk_disable_lp_wm(struct drm_device *dev);
1725 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1726 static inline int intel_enable_rc6(void)
1727 {
1728         return i915.enable_rc6;
1729 }
1730
1731 /* intel_sdvo.c */
1732 bool intel_sdvo_init(struct drm_device *dev,
1733                      i915_reg_t reg, enum port port);
1734
1735
1736 /* intel_sprite.c */
1737 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1738 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1739                               struct drm_file *file_priv);
1740 void intel_pipe_update_start(struct intel_crtc *crtc);
1741 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1742
1743 /* intel_tv.c */
1744 void intel_tv_init(struct drm_device *dev);
1745
1746 /* intel_atomic.c */
1747 int intel_connector_atomic_get_property(struct drm_connector *connector,
1748                                         const struct drm_connector_state *state,
1749                                         struct drm_property *property,
1750                                         uint64_t *val);
1751 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1752 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1753                                struct drm_crtc_state *state);
1754 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1755 void intel_atomic_state_clear(struct drm_atomic_state *);
1756 struct intel_shared_dpll_config *
1757 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1758
1759 static inline struct intel_crtc_state *
1760 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1761                             struct intel_crtc *crtc)
1762 {
1763         struct drm_crtc_state *crtc_state;
1764         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1765         if (IS_ERR(crtc_state))
1766                 return ERR_CAST(crtc_state);
1767
1768         return to_intel_crtc_state(crtc_state);
1769 }
1770
1771 static inline struct intel_plane_state *
1772 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1773                                       struct intel_plane *plane)
1774 {
1775         struct drm_plane_state *plane_state;
1776
1777         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1778
1779         return to_intel_plane_state(plane_state);
1780 }
1781
1782 int intel_atomic_setup_scalers(struct drm_device *dev,
1783         struct intel_crtc *intel_crtc,
1784         struct intel_crtc_state *crtc_state);
1785
1786 /* intel_atomic_plane.c */
1787 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1788 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1789 void intel_plane_destroy_state(struct drm_plane *plane,
1790                                struct drm_plane_state *state);
1791 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1792
1793 /* intel_color.c */
1794 void intel_color_init(struct drm_crtc *crtc);
1795 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1796 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1797 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1798
1799 #endif /* __INTEL_DRV_H__ */