2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
32 #include "drm_crtc_helper.h"
33 #include "drm_fb_helper.h"
35 #define _wait_for(COND, MS, W) ({ \
36 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
39 if (time_after(jiffies, timeout__)) { \
43 if (W && drm_can_sleep()) msleep(W); \
48 #define wait_for_atomic_us(COND, US) ({ \
49 int i, ret__ = -ETIMEDOUT; \
50 for (i = 0; i < (US); i++) { \
60 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
61 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
63 #define KHz(x) (1000*x)
64 #define MHz(x) KHz(1000*x)
67 * Display related stuff
70 /* store information about an Ixxx DVO */
71 /* The i830->i865 use multiple DVOs with multiple i2cs */
72 /* the i915, i945 have a single sDVO i2c bus - which is different */
74 /* maximum connectors per crtcs in the mode set */
75 #define INTELFB_CONN_LIMIT 4
77 #define INTEL_I2C_BUS_DVO 1
78 #define INTEL_I2C_BUS_SDVO 2
80 /* these are outputs from the chip - integrated only
81 external chips are via DVO or SDVO output */
82 #define INTEL_OUTPUT_UNUSED 0
83 #define INTEL_OUTPUT_ANALOG 1
84 #define INTEL_OUTPUT_DVO 2
85 #define INTEL_OUTPUT_SDVO 3
86 #define INTEL_OUTPUT_LVDS 4
87 #define INTEL_OUTPUT_TVOUT 5
88 #define INTEL_OUTPUT_HDMI 6
89 #define INTEL_OUTPUT_DISPLAYPORT 7
90 #define INTEL_OUTPUT_EDP 8
92 /* Intel Pipe Clone Bit */
93 #define INTEL_HDMIB_CLONE_BIT 1
94 #define INTEL_HDMIC_CLONE_BIT 2
95 #define INTEL_HDMID_CLONE_BIT 3
96 #define INTEL_HDMIE_CLONE_BIT 4
97 #define INTEL_HDMIF_CLONE_BIT 5
98 #define INTEL_SDVO_NON_TV_CLONE_BIT 6
99 #define INTEL_SDVO_TV_CLONE_BIT 7
100 #define INTEL_SDVO_LVDS_CLONE_BIT 8
101 #define INTEL_ANALOG_CLONE_BIT 9
102 #define INTEL_TV_CLONE_BIT 10
103 #define INTEL_DP_B_CLONE_BIT 11
104 #define INTEL_DP_C_CLONE_BIT 12
105 #define INTEL_DP_D_CLONE_BIT 13
106 #define INTEL_LVDS_CLONE_BIT 14
107 #define INTEL_DVO_TMDS_CLONE_BIT 15
108 #define INTEL_DVO_LVDS_CLONE_BIT 16
109 #define INTEL_EDP_CLONE_BIT 17
111 #define INTEL_DVO_CHIP_NONE 0
112 #define INTEL_DVO_CHIP_LVDS 1
113 #define INTEL_DVO_CHIP_TMDS 2
114 #define INTEL_DVO_CHIP_TVOUT 4
116 /* drm_display_mode->private_flags */
117 #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
118 #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
119 #define INTEL_MODE_DP_FORCE_6BPC (0x10)
122 intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
125 mode->clock *= multiplier;
126 mode->private_flags |= multiplier;
130 intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
132 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
135 struct intel_framebuffer {
136 struct drm_framebuffer base;
137 struct drm_i915_gem_object *obj;
141 struct drm_fb_helper helper;
142 struct intel_framebuffer ifb;
143 struct list_head fbdev_list;
144 struct drm_display_mode *our_mode;
147 struct intel_encoder {
148 struct drm_encoder base;
151 void (*hot_plug)(struct intel_encoder *);
156 struct intel_connector {
157 struct drm_connector base;
158 struct intel_encoder *encoder;
162 struct drm_crtc base;
165 u8 lut_r[256], lut_g[256], lut_b[256];
167 bool active; /* is the crtc on? independent of the dpms mode */
168 bool busy; /* is scanout buffer being updated frequently? */
169 struct timer_list idle_timer;
171 struct intel_overlay *overlay;
172 struct intel_unpin_work *unpin_work;
175 struct drm_i915_gem_object *cursor_bo;
176 uint32_t cursor_addr;
177 int16_t cursor_x, cursor_y;
178 int16_t cursor_width, cursor_height;
182 bool no_pll; /* tertiary pipe for IVB */
187 struct drm_plane base;
189 struct drm_i915_gem_object *obj;
190 bool primary_disabled;
192 u32 lut_r[1024], lut_g[1024], lut_b[1024];
193 void (*update_plane)(struct drm_plane *plane,
194 struct drm_framebuffer *fb,
195 struct drm_i915_gem_object *obj,
196 int crtc_x, int crtc_y,
197 unsigned int crtc_w, unsigned int crtc_h,
198 uint32_t x, uint32_t y,
199 uint32_t src_w, uint32_t src_h);
200 void (*disable_plane)(struct drm_plane *plane);
201 int (*update_colorkey)(struct drm_plane *plane,
202 struct drm_intel_sprite_colorkey *key);
203 void (*get_colorkey)(struct drm_plane *plane,
204 struct drm_intel_sprite_colorkey *key);
207 struct intel_watermark_params {
208 unsigned long fifo_size;
209 unsigned long max_wm;
210 unsigned long default_wm;
211 unsigned long guard_size;
212 unsigned long cacheline_size;
215 struct cxsr_latency {
218 unsigned long fsb_freq;
219 unsigned long mem_freq;
220 unsigned long display_sr;
221 unsigned long display_hpll_disable;
222 unsigned long cursor_sr;
223 unsigned long cursor_hpll_disable;
226 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
227 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
228 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
229 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
230 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
232 #define DIP_HEADER_SIZE 5
234 #define DIP_TYPE_AVI 0x82
235 #define DIP_VERSION_AVI 0x2
236 #define DIP_LEN_AVI 13
238 #define DIP_TYPE_SPD 0x83
239 #define DIP_VERSION_SPD 0x1
240 #define DIP_LEN_SPD 25
241 #define DIP_SPD_UNKNOWN 0
242 #define DIP_SPD_DSTB 0x1
243 #define DIP_SPD_DVDP 0x2
244 #define DIP_SPD_DVHS 0x3
245 #define DIP_SPD_HDDVR 0x4
246 #define DIP_SPD_DVC 0x5
247 #define DIP_SPD_DSC 0x6
248 #define DIP_SPD_VCD 0x7
249 #define DIP_SPD_GAME 0x8
250 #define DIP_SPD_PC 0x9
251 #define DIP_SPD_BD 0xa
252 #define DIP_SPD_SCD 0xb
254 struct dip_infoframe {
255 uint8_t type; /* HB0 */
256 uint8_t ver; /* HB1 */
257 uint8_t len; /* HB2 - body len, not including checksum */
258 uint8_t ecc; /* Header ECC */
259 uint8_t checksum; /* PB0 */
262 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
264 /* PB2 - C 7:6, M 5:4, R 3:0 */
266 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
273 uint16_t top_bar_end;
274 uint16_t bottom_bar_start;
275 uint16_t left_bar_end;
276 uint16_t right_bar_start;
284 } __attribute__ ((packed)) body;
285 } __attribute__((packed));
287 static inline struct drm_crtc *
288 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
290 struct drm_i915_private *dev_priv = dev->dev_private;
291 return dev_priv->pipe_to_crtc_mapping[pipe];
294 static inline struct drm_crtc *
295 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 return dev_priv->plane_to_crtc_mapping[plane];
301 struct intel_unpin_work {
302 struct work_struct work;
303 struct drm_device *dev;
304 struct drm_i915_gem_object *old_fb_obj;
305 struct drm_i915_gem_object *pending_flip_obj;
306 struct drm_pending_vblank_event *event;
308 bool enable_stall_check;
311 struct intel_fbc_work {
312 struct delayed_work work;
313 struct drm_crtc *crtc;
314 struct drm_framebuffer *fb;
318 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
319 extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus);
321 extern void intel_attach_force_audio_property(struct drm_connector *connector);
322 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
324 extern void intel_crt_init(struct drm_device *dev);
325 extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
326 void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
327 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
329 extern void intel_dvo_init(struct drm_device *dev);
330 extern void intel_tv_init(struct drm_device *dev);
331 extern void intel_mark_busy(struct drm_device *dev,
332 struct drm_i915_gem_object *obj);
333 extern bool intel_lvds_init(struct drm_device *dev);
334 extern void intel_dp_init(struct drm_device *dev, int dp_reg);
336 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
337 struct drm_display_mode *adjusted_mode);
338 extern bool intel_dpd_is_edp(struct drm_device *dev);
339 extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
340 extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
341 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
342 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
346 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
347 struct drm_display_mode *adjusted_mode);
348 extern void intel_pch_panel_fitting(struct drm_device *dev,
350 struct drm_display_mode *mode,
351 struct drm_display_mode *adjusted_mode);
352 extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
353 extern u32 intel_panel_get_backlight(struct drm_device *dev);
354 extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
355 extern int intel_panel_setup_backlight(struct drm_device *dev);
356 extern void intel_panel_enable_backlight(struct drm_device *dev);
357 extern void intel_panel_disable_backlight(struct drm_device *dev);
358 extern void intel_panel_destroy_backlight(struct drm_device *dev);
359 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
361 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
362 extern void intel_encoder_prepare(struct drm_encoder *encoder);
363 extern void intel_encoder_commit(struct drm_encoder *encoder);
364 extern void intel_encoder_destroy(struct drm_encoder *encoder);
366 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
368 return to_intel_connector(connector)->encoder;
371 extern void intel_connector_attach_encoder(struct intel_connector *connector,
372 struct intel_encoder *encoder);
373 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
375 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
376 struct drm_crtc *crtc);
377 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
378 struct drm_file *file_priv);
379 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
380 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
382 struct intel_load_detect_pipe {
383 struct drm_framebuffer *release_fb;
384 bool load_detect_temp;
387 extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
388 struct drm_connector *connector,
389 struct drm_display_mode *mode,
390 struct intel_load_detect_pipe *old);
391 extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
392 struct drm_connector *connector,
393 struct intel_load_detect_pipe *old);
395 extern void intelfb_restore(void);
396 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
397 u16 blue, int regno);
398 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
399 u16 *blue, int regno);
400 extern void intel_enable_clock_gating(struct drm_device *dev);
401 extern void ironlake_disable_rc6(struct drm_device *dev);
402 extern void ironlake_enable_drps(struct drm_device *dev);
403 extern void ironlake_disable_drps(struct drm_device *dev);
404 extern void gen6_enable_rps(struct drm_i915_private *dev_priv);
405 extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
406 extern void gen6_disable_rps(struct drm_device *dev);
407 extern void intel_init_emon(struct drm_device *dev);
409 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
410 struct drm_i915_gem_object *obj,
411 struct intel_ring_buffer *pipelined);
412 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
414 extern int intel_framebuffer_init(struct drm_device *dev,
415 struct intel_framebuffer *ifb,
416 struct drm_mode_fb_cmd2 *mode_cmd,
417 struct drm_i915_gem_object *obj);
418 extern int intel_fbdev_init(struct drm_device *dev);
419 extern void intel_fbdev_fini(struct drm_device *dev);
420 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
421 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
422 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
423 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
425 extern void intel_setup_overlay(struct drm_device *dev);
426 extern void intel_cleanup_overlay(struct drm_device *dev);
427 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
428 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
429 struct drm_file *file_priv);
430 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
431 struct drm_file *file_priv);
433 extern void intel_fb_output_poll_changed(struct drm_device *dev);
434 extern void intel_fb_restore_mode(struct drm_device *dev);
436 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
438 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
439 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
441 extern void intel_init_clock_gating(struct drm_device *dev);
442 extern void intel_write_eld(struct drm_encoder *encoder,
443 struct drm_display_mode *mode);
444 extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
446 /* For use by IVB LP watermark workaround in intel_sprite.c */
447 extern void intel_update_watermarks(struct drm_device *dev);
448 extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
449 uint32_t sprite_width,
452 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
453 struct drm_file *file_priv);
454 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
455 struct drm_file *file_priv);
457 extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
459 /* Power-related functions, located in intel_pm.c */
461 extern void i8xx_disable_fbc(struct drm_device *dev);
462 extern void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
463 extern bool i8xx_fbc_enabled(struct drm_device *dev);
464 extern void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
465 extern void g4x_disable_fbc(struct drm_device *dev);
466 extern bool g4x_fbc_enabled(struct drm_device *dev);
467 extern void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
468 extern void ironlake_disable_fbc(struct drm_device *dev);
469 extern bool ironlake_fbc_enabled(struct drm_device *dev);
470 extern bool intel_fbc_enabled(struct drm_device *dev);
471 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
472 extern void intel_update_fbc(struct drm_device *dev);
475 extern void pineview_update_wm(struct drm_device *dev);
476 extern void valleyview_update_wm(struct drm_device *dev);
477 extern void g4x_update_wm(struct drm_device *dev);
478 extern void i965_update_wm(struct drm_device *dev);
479 extern void i9xx_update_wm(struct drm_device *dev);
480 extern void i830_update_wm(struct drm_device *dev);
481 extern void ironlake_update_wm(struct drm_device *dev);
482 extern void sandybridge_update_wm(struct drm_device *dev);
483 extern void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
484 uint32_t sprite_width, int pixel_size);
485 extern const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
489 extern void pineview_disable_cxsr(struct drm_device *dev);
490 extern int i9xx_get_fifo_size(struct drm_device *dev, int plane);
491 extern int i85x_get_fifo_size(struct drm_device *dev, int plane);
492 extern int i845_get_fifo_size(struct drm_device *dev, int plane);
493 extern int i830_get_fifo_size(struct drm_device *dev, int plane);
496 extern void ironlake_init_clock_gating(struct drm_device *dev);
497 extern void gen6_init_clock_gating(struct drm_device *dev);
498 extern void ivybridge_init_clock_gating(struct drm_device *dev);
499 extern void valleyview_init_clock_gating(struct drm_device *dev);
500 extern void g4x_init_clock_gating(struct drm_device *dev);
501 extern void crestline_init_clock_gating(struct drm_device *dev);
502 extern void broadwater_init_clock_gating(struct drm_device *dev);
503 extern void gen3_init_clock_gating(struct drm_device *dev);
504 extern void i85x_init_clock_gating(struct drm_device *dev);
505 extern void i830_init_clock_gating(struct drm_device *dev);
506 extern void ibx_init_clock_gating(struct drm_device *dev);
507 extern void cpt_init_clock_gating(struct drm_device *dev);
509 #endif /* __INTEL_DRV_H__ */