2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_dual_mode_helper.h>
37 #include <drm/drm_dp_mst_helper.h>
38 #include <drm/drm_rect.h>
39 #include <drm/drm_atomic.h>
42 * _wait_for - magic (register) wait macro
44 * Does the right thing for modeset paths when run under kdgb or similar atomic
45 * contexts. Note that it's important that we check the condition again after
46 * having timed out, since the timeout could be due to preemption or similar and
47 * we've never had a chance to check the condition before the timeout.
49 * TODO: When modesetting has fully transitioned to atomic, the below
50 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
53 #define _wait_for(COND, US, W) ({ \
54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
57 if (time_after(jiffies, timeout__)) { \
62 if ((W) && drm_can_sleep()) { \
63 usleep_range((W), (W)*2); \
71 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
72 #define wait_for_us(COND, US) _wait_for((COND), (US), 1)
74 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
75 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
76 # define _WAIT_FOR_ATOMIC_CHECK WARN_ON_ONCE(!in_atomic())
78 # define _WAIT_FOR_ATOMIC_CHECK do { } while (0)
81 #define _wait_for_atomic(COND, US) ({ \
82 unsigned long end__; \
84 _WAIT_FOR_ATOMIC_CHECK; \
85 BUILD_BUG_ON((US) > 50000); \
86 end__ = (local_clock() >> 10) + (US) + 1; \
88 if (time_after((unsigned long)(local_clock() >> 10), end__)) { \
89 /* Unlike the regular wait_for(), this atomic variant \
90 * cannot be preempted (and we'll just ignore the issue\
91 * of irq interruptions) and so we know that no time \
92 * has passed since the last check of COND and can \
93 * immediately report the timeout. \
103 #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000)
104 #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US))
106 #define KHz(x) (1000 * (x))
107 #define MHz(x) KHz(1000 * (x))
110 * Display related stuff
113 /* store information about an Ixxx DVO */
114 /* The i830->i865 use multiple DVOs with multiple i2cs */
115 /* the i915, i945 have a single sDVO i2c bus - which is different */
116 #define MAX_OUTPUTS 6
117 /* maximum connectors per crtcs in the mode set */
119 /* Maximum cursor sizes */
120 #define GEN2_CURSOR_WIDTH 64
121 #define GEN2_CURSOR_HEIGHT 64
122 #define MAX_CURSOR_WIDTH 256
123 #define MAX_CURSOR_HEIGHT 256
125 #define INTEL_I2C_BUS_DVO 1
126 #define INTEL_I2C_BUS_SDVO 2
128 /* these are outputs from the chip - integrated only
129 external chips are via DVO or SDVO output */
130 enum intel_output_type {
131 INTEL_OUTPUT_UNUSED = 0,
132 INTEL_OUTPUT_ANALOG = 1,
133 INTEL_OUTPUT_DVO = 2,
134 INTEL_OUTPUT_SDVO = 3,
135 INTEL_OUTPUT_LVDS = 4,
136 INTEL_OUTPUT_TVOUT = 5,
137 INTEL_OUTPUT_HDMI = 6,
138 INTEL_OUTPUT_DISPLAYPORT = 7,
139 INTEL_OUTPUT_EDP = 8,
140 INTEL_OUTPUT_DSI = 9,
141 INTEL_OUTPUT_UNKNOWN = 10,
142 INTEL_OUTPUT_DP_MST = 11,
145 #define INTEL_DVO_CHIP_NONE 0
146 #define INTEL_DVO_CHIP_LVDS 1
147 #define INTEL_DVO_CHIP_TMDS 2
148 #define INTEL_DVO_CHIP_TVOUT 4
150 #define INTEL_DSI_VIDEO_MODE 0
151 #define INTEL_DSI_COMMAND_MODE 1
153 struct intel_framebuffer {
154 struct drm_framebuffer base;
155 struct drm_i915_gem_object *obj;
156 struct intel_rotation_info rot_info;
160 struct drm_fb_helper helper;
161 struct intel_framebuffer *fb;
165 struct intel_encoder {
166 struct drm_encoder base;
168 enum intel_output_type type;
169 unsigned int cloneable;
170 void (*hot_plug)(struct intel_encoder *);
171 bool (*compute_config)(struct intel_encoder *,
172 struct intel_crtc_state *);
173 void (*pre_pll_enable)(struct intel_encoder *);
174 void (*pre_enable)(struct intel_encoder *);
175 void (*enable)(struct intel_encoder *);
176 void (*mode_set)(struct intel_encoder *intel_encoder);
177 void (*disable)(struct intel_encoder *);
178 void (*post_disable)(struct intel_encoder *);
179 void (*post_pll_disable)(struct intel_encoder *);
180 /* Read out the current hw state of this connector, returning true if
181 * the encoder is active. If the encoder is enabled it also set the pipe
182 * it is connected to in the pipe parameter. */
183 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
184 /* Reconstructs the equivalent mode flags for the current hardware
185 * state. This must be called _after_ display->get_pipe_config has
186 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
187 * be set correctly before calling this function. */
188 void (*get_config)(struct intel_encoder *,
189 struct intel_crtc_state *pipe_config);
191 * Called during system suspend after all pending requests for the
192 * encoder are flushed (for example for DP AUX transactions) and
193 * device interrupts are disabled.
195 void (*suspend)(struct intel_encoder *);
197 enum hpd_pin hpd_pin;
201 struct drm_display_mode *fixed_mode;
202 struct drm_display_mode *downclock_mode;
212 bool combination_mode; /* gen 2/4 only */
216 bool util_pin_active_low; /* bxt+ */
217 u8 controller; /* bxt+ only */
218 struct pwm_device *pwm;
220 struct backlight_device *device;
222 /* Connector and platform specific backlight functions */
223 int (*setup)(struct intel_connector *connector, enum pipe pipe);
224 uint32_t (*get)(struct intel_connector *connector);
225 void (*set)(struct intel_connector *connector, uint32_t level);
226 void (*disable)(struct intel_connector *connector);
227 void (*enable)(struct intel_connector *connector);
228 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
230 void (*power)(struct intel_connector *, bool enable);
234 struct intel_connector {
235 struct drm_connector base;
237 * The fixed encoder this connector is connected to.
239 struct intel_encoder *encoder;
241 /* Reads out the current hw, returning true if the connector is enabled
242 * and active (i.e. dpms ON state). */
243 bool (*get_hw_state)(struct intel_connector *);
246 * Removes all interfaces through which the connector is accessible
247 * - like sysfs, debugfs entries -, so that no new operations can be
248 * started on the connector. Also makes sure all currently pending
249 * operations finish before returing.
251 void (*unregister)(struct intel_connector *);
253 /* Panel info for eDP and LVDS */
254 struct intel_panel panel;
256 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
258 struct edid *detect_edid;
260 /* since POLL and HPD connectors may use the same HPD line keep the native
261 state of connector->polled in case hotplug storm detection changes it */
264 void *port; /* store this opaque as its illegal to dereference it */
266 struct intel_dp *mst_port;
269 typedef struct dpll {
281 struct intel_atomic_state {
282 struct drm_atomic_state base;
287 * Calculated device cdclk, can be different from cdclk
288 * only when all crtc's are DPMS off.
290 unsigned int dev_cdclk;
292 bool dpll_set, modeset;
294 unsigned int active_crtcs;
295 unsigned int min_pixclk[I915_MAX_PIPES];
297 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
298 struct intel_wm_config wm_config;
301 * Current watermarks can't be trusted during hardware readout, so
302 * don't bother calculating intermediate watermarks.
304 bool skip_intermediate_wm;
307 struct intel_plane_state {
308 struct drm_plane_state base;
311 struct drm_rect clip;
316 * = -1 : not using a scaler
317 * >= 0 : using a scalers
319 * plane requiring a scaler:
320 * - During check_plane, its bit is set in
321 * crtc_state->scaler_state.scaler_users by calling helper function
322 * update_scaler_plane.
323 * - scaler_id indicates the scaler it got assigned.
325 * plane doesn't require a scaler:
326 * - this can happen when scaling is no more required or plane simply
328 * - During check_plane, corresponding bit is reset in
329 * crtc_state->scaler_state.scaler_users by calling helper function
330 * update_scaler_plane.
334 struct drm_intel_sprite_colorkey ckey;
336 /* async flip related structures */
337 struct drm_i915_gem_request *wait_req;
340 struct intel_initial_plane_config {
341 struct intel_framebuffer *fb;
347 #define SKL_MIN_SRC_W 8
348 #define SKL_MAX_SRC_W 4096
349 #define SKL_MIN_SRC_H 8
350 #define SKL_MAX_SRC_H 4096
351 #define SKL_MIN_DST_W 8
352 #define SKL_MAX_DST_W 4096
353 #define SKL_MIN_DST_H 8
354 #define SKL_MAX_DST_H 4096
356 struct intel_scaler {
361 struct intel_crtc_scaler_state {
362 #define SKL_NUM_SCALERS 2
363 struct intel_scaler scalers[SKL_NUM_SCALERS];
366 * scaler_users: keeps track of users requesting scalers on this crtc.
368 * If a bit is set, a user is using a scaler.
369 * Here user can be a plane or crtc as defined below:
370 * bits 0-30 - plane (bit position is index from drm_plane_index)
373 * Instead of creating a new index to cover planes and crtc, using
374 * existing drm_plane_index for planes which is well less than 31
375 * planes and bit 31 for crtc. This should be fine to cover all
378 * intel_atomic_setup_scalers will setup available scalers to users
379 * requesting scalers. It will gracefully fail if request exceeds
382 #define SKL_CRTC_INDEX 31
383 unsigned scaler_users;
385 /* scaler used by crtc for panel fitting purpose */
389 /* drm_mode->private_flags */
390 #define I915_MODE_FLAG_INHERITED 1
392 struct intel_pipe_wm {
393 struct intel_wm_level wm[5];
394 struct intel_wm_level raw_wm[5];
398 bool sprites_enabled;
403 struct skl_wm_level wm[8];
404 struct skl_wm_level trans_wm;
408 struct intel_crtc_state {
409 struct drm_crtc_state base;
412 * quirks - bitfield with hw state readout quirks
414 * For various reasons the hw state readout code might not be able to
415 * completely faithfully read out the current state. These cases are
416 * tracked with quirk flags so that fastboot and state checker can act
419 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
420 unsigned long quirks;
422 unsigned fb_bits; /* framebuffers to flip */
423 bool update_pipe; /* can a fast modeset be performed? */
425 bool update_wm_pre, update_wm_post; /* watermarks are updated */
426 bool fb_changed; /* fb on any of the planes is changed */
428 /* Pipe source size (ie. panel fitter input size)
429 * All planes will be positioned inside this space,
430 * and get clipped at the edges. */
431 int pipe_src_w, pipe_src_h;
433 /* Whether to set up the PCH/FDI. Note that we never allow sharing
434 * between pch encoders and cpu encoders. */
435 bool has_pch_encoder;
437 /* Are we sending infoframes on the attached port */
440 /* CPU Transcoder for the pipe. Currently this can only differ from the
441 * pipe on Haswell and later (where we have a special eDP transcoder)
442 * and Broxton (where we have special DSI transcoders). */
443 enum transcoder cpu_transcoder;
446 * Use reduced/limited/broadcast rbg range, compressing from the full
447 * range fed into the crtcs.
449 bool limited_color_range;
451 /* DP has a bunch of special case unfortunately, so mark the pipe
455 /* DSI has special cases */
456 bool has_dsi_encoder;
458 /* Whether we should send NULL infoframes. Required for audio. */
461 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
462 * has_dp_encoder is set. */
466 * Enable dithering, used when the selected pipe bpp doesn't match the
471 /* Controls for the clock computation, to override various stages. */
474 /* SDVO TV has a bunch of special case. To make multifunction encoders
475 * work correctly, we need to track this at runtime.*/
479 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
480 * required. This is set in the 2nd loop of calling encoder's
481 * ->compute_config if the first pick doesn't work out.
485 /* Settings for the intel dpll used on pretty much everything but
489 /* Selected dpll when shared or NULL. */
490 struct intel_shared_dpll *shared_dpll;
493 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
494 * - enum skl_dpll on SKL
496 uint32_t ddi_pll_sel;
498 /* Actual register state of the dpll, for shared dpll cross-checking. */
499 struct intel_dpll_hw_state dpll_hw_state;
501 /* DSI PLL registers */
507 struct intel_link_m_n dp_m_n;
509 /* m2_n2 for eDP downclock */
510 struct intel_link_m_n dp_m2_n2;
514 * Frequence the dpll for the port should run at. Differs from the
515 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
516 * already multiplied by pixel_multiplier.
520 /* Used by SDVO (and if we ever fix it, HDMI). */
521 unsigned pixel_multiplier;
525 /* Panel fitter controls for gen2-gen4 + VLV */
529 u32 lvds_border_bits;
532 /* Panel fitter placement and size for Ironlake+ */
540 /* FDI configuration, only valid if has_pch_encoder is set. */
542 struct intel_link_m_n fdi_m_n;
550 bool dp_encoder_is_mst;
553 struct intel_crtc_scaler_state scaler_state;
555 /* w/a for waiting 2 vblanks during crtc enable */
556 enum pipe hsw_workaround_pipe;
558 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
563 * Optimal watermarks, programmed post-vblank when this state
567 struct intel_pipe_wm ilk;
568 struct skl_pipe_wm skl;
572 * Intermediate watermarks; these can be programmed immediately
573 * since they satisfy both the current configuration we're
574 * switching away from and the new configuration we're switching
577 struct intel_pipe_wm intermediate;
580 * Platforms with two-step watermark programming will need to
581 * update watermark programming post-vblank to switch from the
582 * safe intermediate watermarks to the optimal final
585 bool need_postvbl_update;
588 /* Gamma mode programmed on the pipe */
592 struct vlv_wm_state {
593 struct vlv_pipe_wm wm[3];
594 struct vlv_sr_wm sr[3];
595 uint8_t num_active_planes;
601 struct intel_mmio_flip {
602 struct work_struct work;
603 struct drm_i915_private *i915;
604 struct drm_i915_gem_request *req;
605 struct intel_crtc *crtc;
606 unsigned int rotation;
610 struct drm_crtc base;
613 u8 lut_r[256], lut_g[256], lut_b[256];
615 * Whether the crtc and the connected output pipeline is active. Implies
616 * that crtc->enabled is set, i.e. the current mode configuration has
617 * some outputs connected to this crtc.
620 unsigned long enabled_power_domains;
622 struct intel_overlay *overlay;
623 struct intel_unpin_work *unpin_work;
625 atomic_t unpin_work_count;
627 /* Display surface base address adjustement for pageflips. Note that on
628 * gen4+ this only adjusts up to a tile, offsets within a tile are
629 * handled in the hw itself (with the TILEOFF register). */
634 uint32_t cursor_addr;
635 uint32_t cursor_cntl;
636 uint32_t cursor_size;
637 uint32_t cursor_base;
639 struct intel_crtc_state *config;
641 /* reset counter value when the last flip was submitted */
642 unsigned int reset_counter;
644 /* Access to these should be protected by dev_priv->irq_lock. */
645 bool cpu_fifo_underrun_disabled;
646 bool pch_fifo_underrun_disabled;
648 /* per-pipe watermark state */
650 /* watermarks currently being used */
652 struct intel_pipe_wm ilk;
653 struct skl_pipe_wm skl;
656 /* allow CxSR on this pipe */
663 unsigned start_vbl_count;
664 ktime_t start_vbl_time;
665 int min_vbl, max_vbl;
669 /* scalers available on this crtc */
672 struct vlv_wm_state wm_state;
675 struct intel_plane_wm_parameters {
676 uint32_t horiz_pixels;
677 uint32_t vert_pixels;
679 * For packed pixel formats:
680 * bytes_per_pixel - holds bytes per pixel
681 * For planar pixel formats:
682 * bytes_per_pixel - holds bytes per pixel for uv-plane
683 * y_bytes_per_pixel - holds bytes per pixel for y-plane
685 uint8_t bytes_per_pixel;
686 uint8_t y_bytes_per_pixel;
690 unsigned int rotation;
695 struct drm_plane base;
700 uint32_t frontbuffer_bit;
702 /* Since we need to change the watermarks before/after
703 * enabling/disabling the planes, we need to store the parameters here
704 * as the other pieces of the struct may not reflect the values we want
705 * for the watermark calculations. Currently only Haswell uses this.
707 struct intel_plane_wm_parameters wm;
710 * NOTE: Do not place new plane state fields here (e.g., when adding
711 * new plane properties). New runtime state should now be placed in
712 * the intel_plane_state structure and accessed via plane_state.
715 void (*update_plane)(struct drm_plane *plane,
716 const struct intel_crtc_state *crtc_state,
717 const struct intel_plane_state *plane_state);
718 void (*disable_plane)(struct drm_plane *plane,
719 struct drm_crtc *crtc);
720 int (*check_plane)(struct drm_plane *plane,
721 struct intel_crtc_state *crtc_state,
722 struct intel_plane_state *state);
725 struct intel_watermark_params {
726 unsigned long fifo_size;
727 unsigned long max_wm;
728 unsigned long default_wm;
729 unsigned long guard_size;
730 unsigned long cacheline_size;
733 struct cxsr_latency {
736 unsigned long fsb_freq;
737 unsigned long mem_freq;
738 unsigned long display_sr;
739 unsigned long display_hpll_disable;
740 unsigned long cursor_sr;
741 unsigned long cursor_hpll_disable;
744 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
745 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
746 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
747 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
748 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
749 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
750 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
751 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
752 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
758 enum drm_dp_dual_mode_type type;
761 bool limited_color_range;
762 bool color_range_auto;
765 enum hdmi_force_audio force_audio;
766 bool rgb_quant_range_selectable;
767 enum hdmi_picture_aspect aspect_ratio;
768 struct intel_connector *attached_connector;
769 void (*write_infoframe)(struct drm_encoder *encoder,
770 enum hdmi_infoframe_type type,
771 const void *frame, ssize_t len);
772 void (*set_infoframes)(struct drm_encoder *encoder,
774 const struct drm_display_mode *adjusted_mode);
775 bool (*infoframe_enabled)(struct drm_encoder *encoder,
776 const struct intel_crtc_state *pipe_config);
779 struct intel_dp_mst_encoder;
780 #define DP_MAX_DOWNSTREAM_PORTS 0x10
784 * When platform provides two set of M_N registers for dp, we can
785 * program them and switch between them incase of DRRS.
786 * But When only one such register is provided, we have to program the
787 * required divider value on that registers itself based on the DRRS state.
789 * M1_N1 : Program dp_m_n on M1_N1 registers
790 * dp_m2_n2 on M2_N2 registers (If supported)
792 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
793 * M2_N2 registers are not supported
797 /* Sets the m1_n1 and m2_n2 */
803 i915_reg_t output_reg;
804 i915_reg_t aux_ch_ctl_reg;
805 i915_reg_t aux_ch_data_reg[5];
812 enum hdmi_force_audio force_audio;
813 bool limited_color_range;
814 bool color_range_auto;
815 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
816 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
817 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
818 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
819 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
820 uint8_t num_sink_rates;
821 int sink_rates[DP_MAX_SUPPORTED_RATES];
822 struct drm_dp_aux aux;
823 uint8_t train_set[4];
824 int panel_power_up_delay;
825 int panel_power_down_delay;
826 int panel_power_cycle_delay;
827 int backlight_on_delay;
828 int backlight_off_delay;
829 struct delayed_work panel_vdd_work;
831 unsigned long last_power_on;
832 unsigned long last_backlight_off;
833 ktime_t panel_power_off_time;
835 struct notifier_block edp_notifier;
838 * Pipe whose power sequencer is currently locked into
839 * this port. Only relevant on VLV/CHV.
842 struct edp_power_seq pps_delays;
844 bool can_mst; /* this port supports mst */
846 int active_mst_links;
847 /* connector directly attached - won't be use for modeset in mst world */
848 struct intel_connector *attached_connector;
850 /* mst connector list */
851 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
852 struct drm_dp_mst_topology_mgr mst_mgr;
854 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
856 * This function returns the value we have to program the AUX_CTL
857 * register with to kick off an AUX transaction.
859 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
862 uint32_t aux_clock_divider);
864 /* This is called before a link training is starterd */
865 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
867 bool train_set_valid;
869 /* Displayport compliance testing */
870 unsigned long compliance_test_type;
871 unsigned long compliance_test_data;
872 bool compliance_test_active;
875 struct intel_digital_port {
876 struct intel_encoder base;
880 struct intel_hdmi hdmi;
881 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
882 bool release_cl2_override;
884 /* for communication with audio component; protected by av_mutex */
885 const struct drm_connector *audio_connector;
888 struct intel_dp_mst_encoder {
889 struct intel_encoder base;
891 struct intel_digital_port *primary;
892 void *port; /* store this opaque as its illegal to dereference it */
895 static inline enum dpio_channel
896 vlv_dport_to_channel(struct intel_digital_port *dport)
898 switch (dport->port) {
909 static inline enum dpio_phy
910 vlv_dport_to_phy(struct intel_digital_port *dport)
912 switch (dport->port) {
923 static inline enum dpio_channel
924 vlv_pipe_to_channel(enum pipe pipe)
937 static inline struct drm_crtc *
938 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 return dev_priv->pipe_to_crtc_mapping[pipe];
944 static inline struct drm_crtc *
945 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
947 struct drm_i915_private *dev_priv = dev->dev_private;
948 return dev_priv->plane_to_crtc_mapping[plane];
951 struct intel_unpin_work {
952 struct work_struct work;
953 struct drm_crtc *crtc;
954 struct drm_framebuffer *old_fb;
955 struct drm_i915_gem_object *pending_flip_obj;
956 struct drm_pending_vblank_event *event;
958 #define INTEL_FLIP_INACTIVE 0
959 #define INTEL_FLIP_PENDING 1
960 #define INTEL_FLIP_COMPLETE 2
963 struct drm_i915_gem_request *flip_queued_req;
964 u32 flip_queued_vblank;
965 u32 flip_ready_vblank;
966 bool enable_stall_check;
969 struct intel_load_detect_pipe {
970 struct drm_atomic_state *restore_state;
973 static inline struct intel_encoder *
974 intel_attached_encoder(struct drm_connector *connector)
976 return to_intel_connector(connector)->encoder;
979 static inline struct intel_digital_port *
980 enc_to_dig_port(struct drm_encoder *encoder)
982 return container_of(encoder, struct intel_digital_port, base.base);
985 static inline struct intel_dp_mst_encoder *
986 enc_to_mst(struct drm_encoder *encoder)
988 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
991 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
993 return &enc_to_dig_port(encoder)->dp;
996 static inline struct intel_digital_port *
997 dp_to_dig_port(struct intel_dp *intel_dp)
999 return container_of(intel_dp, struct intel_digital_port, dp);
1002 static inline struct intel_digital_port *
1003 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1005 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1009 * Returns the number of planes for this pipe, ie the number of sprites + 1
1010 * (primary plane). This doesn't count the cursor plane then.
1012 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1014 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1017 /* intel_fifo_underrun.c */
1018 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1019 enum pipe pipe, bool enable);
1020 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1021 enum transcoder pch_transcoder,
1023 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1025 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1026 enum transcoder pch_transcoder);
1027 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1028 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1031 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1032 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1033 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1034 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1035 void gen6_reset_rps_interrupts(struct drm_device *dev);
1036 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1037 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1038 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1039 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1040 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1041 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1044 * We only use drm_irq_uninstall() at unload and VT switch, so
1045 * this is the only thing we need to check.
1047 return dev_priv->pm.irqs_enabled;
1050 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1051 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1052 unsigned int pipe_mask);
1053 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1054 unsigned int pipe_mask);
1057 void intel_crt_init(struct drm_device *dev);
1061 void intel_ddi_clk_select(struct intel_encoder *encoder,
1062 const struct intel_crtc_state *pipe_config);
1063 void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
1064 void hsw_fdi_link_train(struct drm_crtc *crtc);
1065 void intel_ddi_init(struct drm_device *dev, enum port port);
1066 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1067 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1068 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1069 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1070 enum transcoder cpu_transcoder);
1071 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1072 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1073 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1074 struct intel_crtc_state *crtc_state);
1075 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1076 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1077 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1078 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1079 void intel_ddi_get_config(struct intel_encoder *encoder,
1080 struct intel_crtc_state *pipe_config);
1081 struct intel_encoder *
1082 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1084 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1085 void intel_ddi_clock_get(struct intel_encoder *encoder,
1086 struct intel_crtc_state *pipe_config);
1087 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1088 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1090 /* intel_frontbuffer.c */
1091 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1092 enum fb_op_origin origin);
1093 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1094 unsigned frontbuffer_bits);
1095 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1096 unsigned frontbuffer_bits);
1097 void intel_frontbuffer_flip(struct drm_device *dev,
1098 unsigned frontbuffer_bits);
1099 unsigned int intel_fb_align_height(struct drm_device *dev,
1100 unsigned int height,
1101 uint32_t pixel_format,
1102 uint64_t fb_format_modifier);
1103 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1104 enum fb_op_origin origin);
1105 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1106 uint64_t fb_modifier, uint32_t pixel_format);
1109 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1110 void intel_audio_codec_enable(struct intel_encoder *encoder);
1111 void intel_audio_codec_disable(struct intel_encoder *encoder);
1112 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1113 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1115 /* intel_display.c */
1116 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1117 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1118 const char *name, u32 reg, int ref_freq);
1119 extern const struct drm_plane_funcs intel_plane_funcs;
1120 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1121 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1122 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1123 void intel_mark_busy(struct drm_i915_private *dev_priv);
1124 void intel_mark_idle(struct drm_i915_private *dev_priv);
1125 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1126 int intel_display_suspend(struct drm_device *dev);
1127 void intel_encoder_destroy(struct drm_encoder *encoder);
1128 int intel_connector_init(struct intel_connector *);
1129 struct intel_connector *intel_connector_alloc(void);
1130 bool intel_connector_get_hw_state(struct intel_connector *connector);
1131 void intel_connector_attach_encoder(struct intel_connector *connector,
1132 struct intel_encoder *encoder);
1133 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1134 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1135 struct drm_crtc *crtc);
1136 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1137 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1138 struct drm_file *file_priv);
1139 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1141 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1143 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1145 drm_wait_one_vblank(dev, pipe);
1148 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1150 const struct intel_crtc *crtc =
1151 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1154 intel_wait_for_vblank(dev, pipe);
1156 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1157 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1158 struct intel_digital_port *dport,
1159 unsigned int expected_mask);
1160 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1161 struct drm_display_mode *mode,
1162 struct intel_load_detect_pipe *old,
1163 struct drm_modeset_acquire_ctx *ctx);
1164 void intel_release_load_detect_pipe(struct drm_connector *connector,
1165 struct intel_load_detect_pipe *old,
1166 struct drm_modeset_acquire_ctx *ctx);
1167 int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1168 unsigned int rotation);
1169 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1170 struct drm_framebuffer *
1171 __intel_framebuffer_create(struct drm_device *dev,
1172 struct drm_mode_fb_cmd2 *mode_cmd,
1173 struct drm_i915_gem_object *obj);
1174 void intel_prepare_page_flip(struct drm_i915_private *dev_priv, int plane);
1175 void intel_finish_page_flip(struct drm_i915_private *dev_priv, int pipe);
1176 void intel_finish_page_flip_plane(struct drm_i915_private *dev_priv, int plane);
1177 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1178 int intel_prepare_plane_fb(struct drm_plane *plane,
1179 const struct drm_plane_state *new_state);
1180 void intel_cleanup_plane_fb(struct drm_plane *plane,
1181 const struct drm_plane_state *old_state);
1182 int intel_plane_atomic_get_property(struct drm_plane *plane,
1183 const struct drm_plane_state *state,
1184 struct drm_property *property,
1186 int intel_plane_atomic_set_property(struct drm_plane *plane,
1187 struct drm_plane_state *state,
1188 struct drm_property *property,
1190 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1191 struct drm_plane_state *plane_state);
1193 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1194 uint64_t fb_modifier, unsigned int cpp);
1197 intel_rotation_90_or_270(unsigned int rotation)
1199 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1202 void intel_create_rotation_property(struct drm_device *dev,
1203 struct intel_plane *plane);
1205 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1208 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1209 const struct dpll *dpll);
1210 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1211 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1213 /* modesetting asserts */
1214 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1216 void assert_pll(struct drm_i915_private *dev_priv,
1217 enum pipe pipe, bool state);
1218 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1219 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1220 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1221 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1222 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1223 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1224 enum pipe pipe, bool state);
1225 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1226 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1227 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1228 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1229 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1230 u32 intel_compute_tile_offset(int *x, int *y,
1231 const struct drm_framebuffer *fb, int plane,
1233 unsigned int rotation);
1234 void intel_prepare_reset(struct drm_device *dev);
1235 void intel_finish_reset(struct drm_device *dev);
1236 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1237 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1238 void broxton_init_cdclk(struct drm_i915_private *dev_priv);
1239 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);
1240 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv);
1241 void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);
1242 void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);
1243 void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv);
1244 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1245 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1246 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1247 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1248 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1249 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
1250 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1251 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1252 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1253 void intel_dp_get_m_n(struct intel_crtc *crtc,
1254 struct intel_crtc_state *pipe_config);
1255 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1256 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1257 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1258 intel_clock_t *best_clock);
1259 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1261 bool intel_crtc_active(struct drm_crtc *crtc);
1262 void hsw_enable_ips(struct intel_crtc *crtc);
1263 void hsw_disable_ips(struct intel_crtc *crtc);
1264 enum intel_display_power_domain
1265 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1266 enum intel_display_power_domain
1267 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1268 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1269 struct intel_crtc_state *pipe_config);
1271 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1272 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1274 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1275 struct drm_i915_gem_object *obj,
1276 unsigned int plane);
1278 u32 skl_plane_ctl_format(uint32_t pixel_format);
1279 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1280 u32 skl_plane_ctl_rotation(unsigned int rotation);
1283 void intel_csr_ucode_init(struct drm_i915_private *);
1284 void intel_csr_load_program(struct drm_i915_private *);
1285 void intel_csr_ucode_fini(struct drm_i915_private *);
1286 void intel_csr_ucode_suspend(struct drm_i915_private *);
1287 void intel_csr_ucode_resume(struct drm_i915_private *);
1290 void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1291 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1292 struct intel_connector *intel_connector);
1293 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1294 const struct intel_crtc_state *pipe_config);
1295 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1296 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1297 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1298 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1299 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1300 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1301 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1302 bool intel_dp_compute_config(struct intel_encoder *encoder,
1303 struct intel_crtc_state *pipe_config);
1304 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1305 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1307 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1308 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1309 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1310 void intel_edp_panel_on(struct intel_dp *intel_dp);
1311 void intel_edp_panel_off(struct intel_dp *intel_dp);
1312 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1313 void intel_dp_mst_suspend(struct drm_device *dev);
1314 void intel_dp_mst_resume(struct drm_device *dev);
1315 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1316 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1317 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1318 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1319 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1320 void intel_plane_destroy(struct drm_plane *plane);
1321 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1322 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1323 void intel_edp_drrs_invalidate(struct drm_device *dev,
1324 unsigned frontbuffer_bits);
1325 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1326 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1327 struct intel_digital_port *port);
1330 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1331 uint8_t dp_train_pat);
1333 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1334 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1336 intel_dp_voltage_max(struct intel_dp *intel_dp);
1338 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1339 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1340 uint8_t *link_bw, uint8_t *rate_select);
1341 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1343 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1345 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1347 return ~((1 << lane_count) - 1) & 0xf;
1350 /* intel_dp_aux_backlight.c */
1351 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1353 /* intel_dp_mst.c */
1354 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1355 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1357 void intel_dsi_init(struct drm_device *dev);
1361 void intel_dvo_init(struct drm_device *dev);
1364 /* legacy fbdev emulation in intel_fbdev.c */
1365 #ifdef CONFIG_DRM_FBDEV_EMULATION
1366 extern int intel_fbdev_init(struct drm_device *dev);
1367 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1368 extern void intel_fbdev_fini(struct drm_device *dev);
1369 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1370 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1371 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1373 static inline int intel_fbdev_init(struct drm_device *dev)
1378 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1382 static inline void intel_fbdev_fini(struct drm_device *dev)
1386 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1390 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1396 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1397 struct drm_atomic_state *state);
1398 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1399 void intel_fbc_pre_update(struct intel_crtc *crtc);
1400 void intel_fbc_post_update(struct intel_crtc *crtc);
1401 void intel_fbc_init(struct drm_i915_private *dev_priv);
1402 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1403 void intel_fbc_enable(struct intel_crtc *crtc);
1404 void intel_fbc_disable(struct intel_crtc *crtc);
1405 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1406 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1407 unsigned int frontbuffer_bits,
1408 enum fb_op_origin origin);
1409 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1410 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1411 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1414 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1415 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1416 struct intel_connector *intel_connector);
1417 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1418 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1419 struct intel_crtc_state *pipe_config);
1420 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1424 void intel_lvds_init(struct drm_device *dev);
1425 bool intel_is_dual_link_lvds(struct drm_device *dev);
1429 int intel_connector_update_modes(struct drm_connector *connector,
1431 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1432 void intel_attach_force_audio_property(struct drm_connector *connector);
1433 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1434 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1437 /* intel_overlay.c */
1438 void intel_setup_overlay(struct drm_device *dev);
1439 void intel_cleanup_overlay(struct drm_device *dev);
1440 int intel_overlay_switch_off(struct intel_overlay *overlay);
1441 int intel_overlay_put_image(struct drm_device *dev, void *data,
1442 struct drm_file *file_priv);
1443 int intel_overlay_attrs(struct drm_device *dev, void *data,
1444 struct drm_file *file_priv);
1445 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1449 int intel_panel_init(struct intel_panel *panel,
1450 struct drm_display_mode *fixed_mode,
1451 struct drm_display_mode *downclock_mode);
1452 void intel_panel_fini(struct intel_panel *panel);
1453 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1454 struct drm_display_mode *adjusted_mode);
1455 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1456 struct intel_crtc_state *pipe_config,
1458 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1459 struct intel_crtc_state *pipe_config,
1461 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1462 u32 level, u32 max);
1463 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1464 void intel_panel_enable_backlight(struct intel_connector *connector);
1465 void intel_panel_disable_backlight(struct intel_connector *connector);
1466 void intel_panel_destroy_backlight(struct drm_connector *connector);
1467 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1468 extern struct drm_display_mode *intel_find_panel_downclock(
1469 struct drm_device *dev,
1470 struct drm_display_mode *fixed_mode,
1471 struct drm_connector *connector);
1472 void intel_backlight_register(struct drm_device *dev);
1473 void intel_backlight_unregister(struct drm_device *dev);
1477 void intel_psr_enable(struct intel_dp *intel_dp);
1478 void intel_psr_disable(struct intel_dp *intel_dp);
1479 void intel_psr_invalidate(struct drm_device *dev,
1480 unsigned frontbuffer_bits);
1481 void intel_psr_flush(struct drm_device *dev,
1482 unsigned frontbuffer_bits,
1483 enum fb_op_origin origin);
1484 void intel_psr_init(struct drm_device *dev);
1485 void intel_psr_single_frame_update(struct drm_device *dev,
1486 unsigned frontbuffer_bits);
1488 /* intel_runtime_pm.c */
1489 int intel_power_domains_init(struct drm_i915_private *);
1490 void intel_power_domains_fini(struct drm_i915_private *);
1491 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1492 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1493 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1494 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1495 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1497 intel_display_power_domain_str(enum intel_display_power_domain domain);
1499 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1500 enum intel_display_power_domain domain);
1501 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1502 enum intel_display_power_domain domain);
1503 void intel_display_power_get(struct drm_i915_private *dev_priv,
1504 enum intel_display_power_domain domain);
1505 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1506 enum intel_display_power_domain domain);
1507 void intel_display_power_put(struct drm_i915_private *dev_priv,
1508 enum intel_display_power_domain domain);
1511 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1513 WARN_ONCE(dev_priv->pm.suspended,
1514 "Device suspended during HW access\n");
1518 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1520 assert_rpm_device_not_suspended(dev_priv);
1521 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1522 * too much noise. */
1523 if (!atomic_read(&dev_priv->pm.wakeref_count))
1524 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1528 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1530 int seq = atomic_read(&dev_priv->pm.atomic_seq);
1532 assert_rpm_wakelock_held(dev_priv);
1538 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1540 WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1541 "HW access outside of RPM atomic section\n");
1545 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1546 * @dev_priv: i915 device instance
1548 * This function disable asserts that check if we hold an RPM wakelock
1549 * reference, while keeping the device-not-suspended checks still enabled.
1550 * It's meant to be used only in special circumstances where our rule about
1551 * the wakelock refcount wrt. the device power state doesn't hold. According
1552 * to this rule at any point where we access the HW or want to keep the HW in
1553 * an active state we must hold an RPM wakelock reference acquired via one of
1554 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1555 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1556 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1557 * users should avoid using this function.
1559 * Any calls to this function must have a symmetric call to
1560 * enable_rpm_wakeref_asserts().
1563 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1565 atomic_inc(&dev_priv->pm.wakeref_count);
1569 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1570 * @dev_priv: i915 device instance
1572 * This function re-enables the RPM assert checks after disabling them with
1573 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1574 * circumstances otherwise its use should be avoided.
1576 * Any calls to this function must have a symmetric call to
1577 * disable_rpm_wakeref_asserts().
1580 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1582 atomic_dec(&dev_priv->pm.wakeref_count);
1585 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1586 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1587 disable_rpm_wakeref_asserts(dev_priv)
1589 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1590 enable_rpm_wakeref_asserts(dev_priv)
1592 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1593 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1594 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1595 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1597 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1599 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1600 bool override, unsigned int mask);
1601 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1602 enum dpio_channel ch, bool override);
1606 void intel_init_clock_gating(struct drm_device *dev);
1607 void intel_suspend_hw(struct drm_device *dev);
1608 int ilk_wm_max_level(const struct drm_device *dev);
1609 void intel_update_watermarks(struct drm_crtc *crtc);
1610 void intel_init_pm(struct drm_device *dev);
1611 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1612 void intel_pm_setup(struct drm_device *dev);
1613 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1614 void intel_gpu_ips_teardown(void);
1615 void intel_init_gt_powersave(struct drm_device *dev);
1616 void intel_cleanup_gt_powersave(struct drm_device *dev);
1617 void intel_enable_gt_powersave(struct drm_device *dev);
1618 void intel_disable_gt_powersave(struct drm_device *dev);
1619 void intel_suspend_gt_powersave(struct drm_device *dev);
1620 void intel_reset_gt_powersave(struct drm_device *dev);
1621 void gen6_update_ring_freq(struct drm_device *dev);
1622 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1623 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1624 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1625 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1626 struct intel_rps_client *rps,
1627 unsigned long submitted);
1628 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1629 void vlv_wm_get_hw_state(struct drm_device *dev);
1630 void ilk_wm_get_hw_state(struct drm_device *dev);
1631 void skl_wm_get_hw_state(struct drm_device *dev);
1632 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1633 struct skl_ddb_allocation *ddb /* out */);
1634 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1635 bool ilk_disable_lp_wm(struct drm_device *dev);
1636 int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6);
1639 bool intel_sdvo_init(struct drm_device *dev,
1640 i915_reg_t reg, enum port port);
1643 /* intel_sprite.c */
1644 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1645 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1646 struct drm_file *file_priv);
1647 void intel_pipe_update_start(struct intel_crtc *crtc);
1648 void intel_pipe_update_end(struct intel_crtc *crtc);
1651 void intel_tv_init(struct drm_device *dev);
1653 /* intel_atomic.c */
1654 int intel_connector_atomic_get_property(struct drm_connector *connector,
1655 const struct drm_connector_state *state,
1656 struct drm_property *property,
1658 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1659 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1660 struct drm_crtc_state *state);
1661 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1662 void intel_atomic_state_clear(struct drm_atomic_state *);
1663 struct intel_shared_dpll_config *
1664 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1666 static inline struct intel_crtc_state *
1667 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1668 struct intel_crtc *crtc)
1670 struct drm_crtc_state *crtc_state;
1671 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1672 if (IS_ERR(crtc_state))
1673 return ERR_CAST(crtc_state);
1675 return to_intel_crtc_state(crtc_state);
1678 static inline struct intel_plane_state *
1679 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1680 struct intel_plane *plane)
1682 struct drm_plane_state *plane_state;
1684 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1686 return to_intel_plane_state(plane_state);
1689 int intel_atomic_setup_scalers(struct drm_device *dev,
1690 struct intel_crtc *intel_crtc,
1691 struct intel_crtc_state *crtc_state);
1693 /* intel_atomic_plane.c */
1694 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1695 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1696 void intel_plane_destroy_state(struct drm_plane *plane,
1697 struct drm_plane_state *state);
1698 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1701 void intel_color_init(struct drm_crtc *crtc);
1702 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1703 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1704 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1706 #endif /* __INTEL_DRV_H__ */