2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
41 * _wait_for - magic (register) wait macro
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
48 * TODO: When modesetting has fully transitioned to atomic, the below
49 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
52 #define _wait_for(COND, US, W) ({ \
53 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
56 if (time_after(jiffies, timeout__)) { \
61 if ((W) && drm_can_sleep()) { \
62 usleep_range((W), (W)*2); \
70 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
71 #define wait_for_us(COND, US) _wait_for((COND), (US), 1)
73 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
74 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
75 # define _WAIT_FOR_ATOMIC_CHECK WARN_ON_ONCE(!in_atomic())
77 # define _WAIT_FOR_ATOMIC_CHECK do { } while (0)
80 #define _wait_for_atomic(COND, US) ({ \
81 unsigned long end__; \
83 _WAIT_FOR_ATOMIC_CHECK; \
84 BUILD_BUG_ON((US) > 50000); \
85 end__ = (local_clock() >> 10) + (US) + 1; \
87 if (time_after((unsigned long)(local_clock() >> 10), end__)) { \
88 /* Unlike the regular wait_for(), this atomic variant \
89 * cannot be preempted (and we'll just ignore the issue\
90 * of irq interruptions) and so we know that no time \
91 * has passed since the last check of COND and can \
92 * immediately report the timeout. \
102 #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000)
103 #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US))
105 #define KHz(x) (1000 * (x))
106 #define MHz(x) KHz(1000 * (x))
109 * Display related stuff
112 /* store information about an Ixxx DVO */
113 /* The i830->i865 use multiple DVOs with multiple i2cs */
114 /* the i915, i945 have a single sDVO i2c bus - which is different */
115 #define MAX_OUTPUTS 6
116 /* maximum connectors per crtcs in the mode set */
118 /* Maximum cursor sizes */
119 #define GEN2_CURSOR_WIDTH 64
120 #define GEN2_CURSOR_HEIGHT 64
121 #define MAX_CURSOR_WIDTH 256
122 #define MAX_CURSOR_HEIGHT 256
124 #define INTEL_I2C_BUS_DVO 1
125 #define INTEL_I2C_BUS_SDVO 2
127 /* these are outputs from the chip - integrated only
128 external chips are via DVO or SDVO output */
129 enum intel_output_type {
130 INTEL_OUTPUT_UNUSED = 0,
131 INTEL_OUTPUT_ANALOG = 1,
132 INTEL_OUTPUT_DVO = 2,
133 INTEL_OUTPUT_SDVO = 3,
134 INTEL_OUTPUT_LVDS = 4,
135 INTEL_OUTPUT_TVOUT = 5,
136 INTEL_OUTPUT_HDMI = 6,
137 INTEL_OUTPUT_DISPLAYPORT = 7,
138 INTEL_OUTPUT_EDP = 8,
139 INTEL_OUTPUT_DSI = 9,
140 INTEL_OUTPUT_UNKNOWN = 10,
141 INTEL_OUTPUT_DP_MST = 11,
144 #define INTEL_DVO_CHIP_NONE 0
145 #define INTEL_DVO_CHIP_LVDS 1
146 #define INTEL_DVO_CHIP_TMDS 2
147 #define INTEL_DVO_CHIP_TVOUT 4
149 #define INTEL_DSI_VIDEO_MODE 0
150 #define INTEL_DSI_COMMAND_MODE 1
152 struct intel_framebuffer {
153 struct drm_framebuffer base;
154 struct drm_i915_gem_object *obj;
155 struct intel_rotation_info rot_info;
159 struct drm_fb_helper helper;
160 struct intel_framebuffer *fb;
164 struct intel_encoder {
165 struct drm_encoder base;
167 enum intel_output_type type;
168 unsigned int cloneable;
169 void (*hot_plug)(struct intel_encoder *);
170 bool (*compute_config)(struct intel_encoder *,
171 struct intel_crtc_state *);
172 void (*pre_pll_enable)(struct intel_encoder *);
173 void (*pre_enable)(struct intel_encoder *);
174 void (*enable)(struct intel_encoder *);
175 void (*mode_set)(struct intel_encoder *intel_encoder);
176 void (*disable)(struct intel_encoder *);
177 void (*post_disable)(struct intel_encoder *);
178 void (*post_pll_disable)(struct intel_encoder *);
179 /* Read out the current hw state of this connector, returning true if
180 * the encoder is active. If the encoder is enabled it also set the pipe
181 * it is connected to in the pipe parameter. */
182 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
183 /* Reconstructs the equivalent mode flags for the current hardware
184 * state. This must be called _after_ display->get_pipe_config has
185 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
186 * be set correctly before calling this function. */
187 void (*get_config)(struct intel_encoder *,
188 struct intel_crtc_state *pipe_config);
190 * Called during system suspend after all pending requests for the
191 * encoder are flushed (for example for DP AUX transactions) and
192 * device interrupts are disabled.
194 void (*suspend)(struct intel_encoder *);
196 enum hpd_pin hpd_pin;
200 struct drm_display_mode *fixed_mode;
201 struct drm_display_mode *downclock_mode;
211 bool combination_mode; /* gen 2/4 only */
215 bool util_pin_active_low; /* bxt+ */
216 u8 controller; /* bxt+ only */
217 struct pwm_device *pwm;
219 struct backlight_device *device;
221 /* Connector and platform specific backlight functions */
222 int (*setup)(struct intel_connector *connector, enum pipe pipe);
223 uint32_t (*get)(struct intel_connector *connector);
224 void (*set)(struct intel_connector *connector, uint32_t level);
225 void (*disable)(struct intel_connector *connector);
226 void (*enable)(struct intel_connector *connector);
227 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
229 void (*power)(struct intel_connector *, bool enable);
233 struct intel_connector {
234 struct drm_connector base;
236 * The fixed encoder this connector is connected to.
238 struct intel_encoder *encoder;
240 /* Reads out the current hw, returning true if the connector is enabled
241 * and active (i.e. dpms ON state). */
242 bool (*get_hw_state)(struct intel_connector *);
245 * Removes all interfaces through which the connector is accessible
246 * - like sysfs, debugfs entries -, so that no new operations can be
247 * started on the connector. Also makes sure all currently pending
248 * operations finish before returing.
250 void (*unregister)(struct intel_connector *);
252 /* Panel info for eDP and LVDS */
253 struct intel_panel panel;
255 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
257 struct edid *detect_edid;
259 /* since POLL and HPD connectors may use the same HPD line keep the native
260 state of connector->polled in case hotplug storm detection changes it */
263 void *port; /* store this opaque as its illegal to dereference it */
265 struct intel_dp *mst_port;
268 typedef struct dpll {
280 struct intel_atomic_state {
281 struct drm_atomic_state base;
286 * Calculated device cdclk, can be different from cdclk
287 * only when all crtc's are DPMS off.
289 unsigned int dev_cdclk;
291 bool dpll_set, modeset;
293 unsigned int active_crtcs;
294 unsigned int min_pixclk[I915_MAX_PIPES];
296 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
297 struct intel_wm_config wm_config;
300 * Current watermarks can't be trusted during hardware readout, so
301 * don't bother calculating intermediate watermarks.
303 bool skip_intermediate_wm;
306 struct intel_plane_state {
307 struct drm_plane_state base;
310 struct drm_rect clip;
315 * = -1 : not using a scaler
316 * >= 0 : using a scalers
318 * plane requiring a scaler:
319 * - During check_plane, its bit is set in
320 * crtc_state->scaler_state.scaler_users by calling helper function
321 * update_scaler_plane.
322 * - scaler_id indicates the scaler it got assigned.
324 * plane doesn't require a scaler:
325 * - this can happen when scaling is no more required or plane simply
327 * - During check_plane, corresponding bit is reset in
328 * crtc_state->scaler_state.scaler_users by calling helper function
329 * update_scaler_plane.
333 struct drm_intel_sprite_colorkey ckey;
335 /* async flip related structures */
336 struct drm_i915_gem_request *wait_req;
339 struct intel_initial_plane_config {
340 struct intel_framebuffer *fb;
346 #define SKL_MIN_SRC_W 8
347 #define SKL_MAX_SRC_W 4096
348 #define SKL_MIN_SRC_H 8
349 #define SKL_MAX_SRC_H 4096
350 #define SKL_MIN_DST_W 8
351 #define SKL_MAX_DST_W 4096
352 #define SKL_MIN_DST_H 8
353 #define SKL_MAX_DST_H 4096
355 struct intel_scaler {
360 struct intel_crtc_scaler_state {
361 #define SKL_NUM_SCALERS 2
362 struct intel_scaler scalers[SKL_NUM_SCALERS];
365 * scaler_users: keeps track of users requesting scalers on this crtc.
367 * If a bit is set, a user is using a scaler.
368 * Here user can be a plane or crtc as defined below:
369 * bits 0-30 - plane (bit position is index from drm_plane_index)
372 * Instead of creating a new index to cover planes and crtc, using
373 * existing drm_plane_index for planes which is well less than 31
374 * planes and bit 31 for crtc. This should be fine to cover all
377 * intel_atomic_setup_scalers will setup available scalers to users
378 * requesting scalers. It will gracefully fail if request exceeds
381 #define SKL_CRTC_INDEX 31
382 unsigned scaler_users;
384 /* scaler used by crtc for panel fitting purpose */
388 /* drm_mode->private_flags */
389 #define I915_MODE_FLAG_INHERITED 1
391 struct intel_pipe_wm {
392 struct intel_wm_level wm[5];
393 struct intel_wm_level raw_wm[5];
397 bool sprites_enabled;
402 struct skl_wm_level wm[8];
403 struct skl_wm_level trans_wm;
407 struct intel_crtc_state {
408 struct drm_crtc_state base;
411 * quirks - bitfield with hw state readout quirks
413 * For various reasons the hw state readout code might not be able to
414 * completely faithfully read out the current state. These cases are
415 * tracked with quirk flags so that fastboot and state checker can act
418 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
419 unsigned long quirks;
421 unsigned fb_bits; /* framebuffers to flip */
422 bool update_pipe; /* can a fast modeset be performed? */
424 bool update_wm_pre, update_wm_post; /* watermarks are updated */
425 bool fb_changed; /* fb on any of the planes is changed */
427 /* Pipe source size (ie. panel fitter input size)
428 * All planes will be positioned inside this space,
429 * and get clipped at the edges. */
430 int pipe_src_w, pipe_src_h;
432 /* Whether to set up the PCH/FDI. Note that we never allow sharing
433 * between pch encoders and cpu encoders. */
434 bool has_pch_encoder;
436 /* Are we sending infoframes on the attached port */
439 /* CPU Transcoder for the pipe. Currently this can only differ from the
440 * pipe on Haswell and later (where we have a special eDP transcoder)
441 * and Broxton (where we have special DSI transcoders). */
442 enum transcoder cpu_transcoder;
445 * Use reduced/limited/broadcast rbg range, compressing from the full
446 * range fed into the crtcs.
448 bool limited_color_range;
450 /* DP has a bunch of special case unfortunately, so mark the pipe
454 /* DSI has special cases */
455 bool has_dsi_encoder;
457 /* Whether we should send NULL infoframes. Required for audio. */
460 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
461 * has_dp_encoder is set. */
465 * Enable dithering, used when the selected pipe bpp doesn't match the
470 /* Controls for the clock computation, to override various stages. */
473 /* SDVO TV has a bunch of special case. To make multifunction encoders
474 * work correctly, we need to track this at runtime.*/
478 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
479 * required. This is set in the 2nd loop of calling encoder's
480 * ->compute_config if the first pick doesn't work out.
484 /* Settings for the intel dpll used on pretty much everything but
488 /* Selected dpll when shared or NULL. */
489 struct intel_shared_dpll *shared_dpll;
492 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
493 * - enum skl_dpll on SKL
495 uint32_t ddi_pll_sel;
497 /* Actual register state of the dpll, for shared dpll cross-checking. */
498 struct intel_dpll_hw_state dpll_hw_state;
501 struct intel_link_m_n dp_m_n;
503 /* m2_n2 for eDP downclock */
504 struct intel_link_m_n dp_m2_n2;
508 * Frequence the dpll for the port should run at. Differs from the
509 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
510 * already multiplied by pixel_multiplier.
514 /* Used by SDVO (and if we ever fix it, HDMI). */
515 unsigned pixel_multiplier;
519 /* Panel fitter controls for gen2-gen4 + VLV */
523 u32 lvds_border_bits;
526 /* Panel fitter placement and size for Ironlake+ */
534 /* FDI configuration, only valid if has_pch_encoder is set. */
536 struct intel_link_m_n fdi_m_n;
544 bool dp_encoder_is_mst;
547 struct intel_crtc_scaler_state scaler_state;
549 /* w/a for waiting 2 vblanks during crtc enable */
550 enum pipe hsw_workaround_pipe;
552 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
557 * Optimal watermarks, programmed post-vblank when this state
561 struct intel_pipe_wm ilk;
562 struct skl_pipe_wm skl;
566 * Intermediate watermarks; these can be programmed immediately
567 * since they satisfy both the current configuration we're
568 * switching away from and the new configuration we're switching
571 struct intel_pipe_wm intermediate;
574 * Platforms with two-step watermark programming will need to
575 * update watermark programming post-vblank to switch from the
576 * safe intermediate watermarks to the optimal final
579 bool need_postvbl_update;
582 /* Gamma mode programmed on the pipe */
586 struct vlv_wm_state {
587 struct vlv_pipe_wm wm[3];
588 struct vlv_sr_wm sr[3];
589 uint8_t num_active_planes;
595 struct intel_mmio_flip {
596 struct work_struct work;
597 struct drm_i915_private *i915;
598 struct drm_i915_gem_request *req;
599 struct intel_crtc *crtc;
600 unsigned int rotation;
604 struct drm_crtc base;
607 u8 lut_r[256], lut_g[256], lut_b[256];
609 * Whether the crtc and the connected output pipeline is active. Implies
610 * that crtc->enabled is set, i.e. the current mode configuration has
611 * some outputs connected to this crtc.
614 unsigned long enabled_power_domains;
616 struct intel_overlay *overlay;
617 struct intel_unpin_work *unpin_work;
619 atomic_t unpin_work_count;
621 /* Display surface base address adjustement for pageflips. Note that on
622 * gen4+ this only adjusts up to a tile, offsets within a tile are
623 * handled in the hw itself (with the TILEOFF register). */
628 uint32_t cursor_addr;
629 uint32_t cursor_cntl;
630 uint32_t cursor_size;
631 uint32_t cursor_base;
633 struct intel_crtc_state *config;
635 /* reset counter value when the last flip was submitted */
636 unsigned int reset_counter;
638 /* Access to these should be protected by dev_priv->irq_lock. */
639 bool cpu_fifo_underrun_disabled;
640 bool pch_fifo_underrun_disabled;
642 /* per-pipe watermark state */
644 /* watermarks currently being used */
646 struct intel_pipe_wm ilk;
647 struct skl_pipe_wm skl;
650 /* allow CxSR on this pipe */
657 unsigned start_vbl_count;
658 ktime_t start_vbl_time;
659 int min_vbl, max_vbl;
663 /* scalers available on this crtc */
666 struct vlv_wm_state wm_state;
669 struct intel_plane_wm_parameters {
670 uint32_t horiz_pixels;
671 uint32_t vert_pixels;
673 * For packed pixel formats:
674 * bytes_per_pixel - holds bytes per pixel
675 * For planar pixel formats:
676 * bytes_per_pixel - holds bytes per pixel for uv-plane
677 * y_bytes_per_pixel - holds bytes per pixel for y-plane
679 uint8_t bytes_per_pixel;
680 uint8_t y_bytes_per_pixel;
684 unsigned int rotation;
689 struct drm_plane base;
694 uint32_t frontbuffer_bit;
696 /* Since we need to change the watermarks before/after
697 * enabling/disabling the planes, we need to store the parameters here
698 * as the other pieces of the struct may not reflect the values we want
699 * for the watermark calculations. Currently only Haswell uses this.
701 struct intel_plane_wm_parameters wm;
704 * NOTE: Do not place new plane state fields here (e.g., when adding
705 * new plane properties). New runtime state should now be placed in
706 * the intel_plane_state structure and accessed via plane_state.
709 void (*update_plane)(struct drm_plane *plane,
710 const struct intel_crtc_state *crtc_state,
711 const struct intel_plane_state *plane_state);
712 void (*disable_plane)(struct drm_plane *plane,
713 struct drm_crtc *crtc);
714 int (*check_plane)(struct drm_plane *plane,
715 struct intel_crtc_state *crtc_state,
716 struct intel_plane_state *state);
719 struct intel_watermark_params {
720 unsigned long fifo_size;
721 unsigned long max_wm;
722 unsigned long default_wm;
723 unsigned long guard_size;
724 unsigned long cacheline_size;
727 struct cxsr_latency {
730 unsigned long fsb_freq;
731 unsigned long mem_freq;
732 unsigned long display_sr;
733 unsigned long display_hpll_disable;
734 unsigned long cursor_sr;
735 unsigned long cursor_hpll_disable;
738 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
739 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
740 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
741 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
742 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
743 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
744 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
745 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
746 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
751 bool limited_color_range;
752 bool color_range_auto;
755 enum hdmi_force_audio force_audio;
756 bool rgb_quant_range_selectable;
757 enum hdmi_picture_aspect aspect_ratio;
758 struct intel_connector *attached_connector;
759 void (*write_infoframe)(struct drm_encoder *encoder,
760 enum hdmi_infoframe_type type,
761 const void *frame, ssize_t len);
762 void (*set_infoframes)(struct drm_encoder *encoder,
764 const struct drm_display_mode *adjusted_mode);
765 bool (*infoframe_enabled)(struct drm_encoder *encoder,
766 const struct intel_crtc_state *pipe_config);
769 struct intel_dp_mst_encoder;
770 #define DP_MAX_DOWNSTREAM_PORTS 0x10
774 * When platform provides two set of M_N registers for dp, we can
775 * program them and switch between them incase of DRRS.
776 * But When only one such register is provided, we have to program the
777 * required divider value on that registers itself based on the DRRS state.
779 * M1_N1 : Program dp_m_n on M1_N1 registers
780 * dp_m2_n2 on M2_N2 registers (If supported)
782 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
783 * M2_N2 registers are not supported
787 /* Sets the m1_n1 and m2_n2 */
793 i915_reg_t output_reg;
794 i915_reg_t aux_ch_ctl_reg;
795 i915_reg_t aux_ch_data_reg[5];
800 enum hdmi_force_audio force_audio;
801 bool limited_color_range;
802 bool color_range_auto;
803 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
804 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
805 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
806 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
807 uint8_t num_sink_rates;
808 int sink_rates[DP_MAX_SUPPORTED_RATES];
809 struct drm_dp_aux aux;
810 uint8_t train_set[4];
811 int panel_power_up_delay;
812 int panel_power_down_delay;
813 int panel_power_cycle_delay;
814 int backlight_on_delay;
815 int backlight_off_delay;
816 struct delayed_work panel_vdd_work;
818 unsigned long last_power_on;
819 unsigned long last_backlight_off;
820 ktime_t panel_power_off_time;
822 struct notifier_block edp_notifier;
825 * Pipe whose power sequencer is currently locked into
826 * this port. Only relevant on VLV/CHV.
829 struct edp_power_seq pps_delays;
831 bool can_mst; /* this port supports mst */
833 int active_mst_links;
834 /* connector directly attached - won't be use for modeset in mst world */
835 struct intel_connector *attached_connector;
837 /* mst connector list */
838 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
839 struct drm_dp_mst_topology_mgr mst_mgr;
841 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
843 * This function returns the value we have to program the AUX_CTL
844 * register with to kick off an AUX transaction.
846 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
849 uint32_t aux_clock_divider);
851 /* This is called before a link training is starterd */
852 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
854 bool train_set_valid;
856 /* Displayport compliance testing */
857 unsigned long compliance_test_type;
858 unsigned long compliance_test_data;
859 bool compliance_test_active;
862 struct intel_digital_port {
863 struct intel_encoder base;
867 struct intel_hdmi hdmi;
868 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
869 bool release_cl2_override;
871 /* for communication with audio component; protected by av_mutex */
872 const struct drm_connector *audio_connector;
875 struct intel_dp_mst_encoder {
876 struct intel_encoder base;
878 struct intel_digital_port *primary;
879 void *port; /* store this opaque as its illegal to dereference it */
882 static inline enum dpio_channel
883 vlv_dport_to_channel(struct intel_digital_port *dport)
885 switch (dport->port) {
896 static inline enum dpio_phy
897 vlv_dport_to_phy(struct intel_digital_port *dport)
899 switch (dport->port) {
910 static inline enum dpio_channel
911 vlv_pipe_to_channel(enum pipe pipe)
924 static inline struct drm_crtc *
925 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
927 struct drm_i915_private *dev_priv = dev->dev_private;
928 return dev_priv->pipe_to_crtc_mapping[pipe];
931 static inline struct drm_crtc *
932 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
934 struct drm_i915_private *dev_priv = dev->dev_private;
935 return dev_priv->plane_to_crtc_mapping[plane];
938 struct intel_unpin_work {
939 struct work_struct work;
940 struct drm_crtc *crtc;
941 struct drm_framebuffer *old_fb;
942 struct drm_i915_gem_object *pending_flip_obj;
943 struct drm_pending_vblank_event *event;
945 #define INTEL_FLIP_INACTIVE 0
946 #define INTEL_FLIP_PENDING 1
947 #define INTEL_FLIP_COMPLETE 2
950 struct drm_i915_gem_request *flip_queued_req;
951 u32 flip_queued_vblank;
952 u32 flip_ready_vblank;
953 bool enable_stall_check;
956 struct intel_load_detect_pipe {
957 struct drm_atomic_state *restore_state;
960 static inline struct intel_encoder *
961 intel_attached_encoder(struct drm_connector *connector)
963 return to_intel_connector(connector)->encoder;
966 static inline struct intel_digital_port *
967 enc_to_dig_port(struct drm_encoder *encoder)
969 return container_of(encoder, struct intel_digital_port, base.base);
972 static inline struct intel_dp_mst_encoder *
973 enc_to_mst(struct drm_encoder *encoder)
975 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
978 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
980 return &enc_to_dig_port(encoder)->dp;
983 static inline struct intel_digital_port *
984 dp_to_dig_port(struct intel_dp *intel_dp)
986 return container_of(intel_dp, struct intel_digital_port, dp);
989 static inline struct intel_digital_port *
990 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
992 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
996 * Returns the number of planes for this pipe, ie the number of sprites + 1
997 * (primary plane). This doesn't count the cursor plane then.
999 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1001 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1004 /* intel_fifo_underrun.c */
1005 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1006 enum pipe pipe, bool enable);
1007 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1008 enum transcoder pch_transcoder,
1010 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1012 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1013 enum transcoder pch_transcoder);
1014 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1015 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1018 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1019 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1020 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1021 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1022 void gen6_reset_rps_interrupts(struct drm_device *dev);
1023 void gen6_enable_rps_interrupts(struct drm_device *dev);
1024 void gen6_disable_rps_interrupts(struct drm_device *dev);
1025 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1026 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1027 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1028 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1031 * We only use drm_irq_uninstall() at unload and VT switch, so
1032 * this is the only thing we need to check.
1034 return dev_priv->pm.irqs_enabled;
1037 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1038 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1039 unsigned int pipe_mask);
1040 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1041 unsigned int pipe_mask);
1044 void intel_crt_init(struct drm_device *dev);
1048 void intel_ddi_clk_select(struct intel_encoder *encoder,
1049 const struct intel_crtc_state *pipe_config);
1050 void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
1051 void hsw_fdi_link_train(struct drm_crtc *crtc);
1052 void intel_ddi_init(struct drm_device *dev, enum port port);
1053 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1054 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1055 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1056 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1057 enum transcoder cpu_transcoder);
1058 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1059 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1060 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1061 struct intel_crtc_state *crtc_state);
1062 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1063 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1064 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1065 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1066 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1067 struct intel_crtc *intel_crtc);
1068 void intel_ddi_get_config(struct intel_encoder *encoder,
1069 struct intel_crtc_state *pipe_config);
1070 struct intel_encoder *
1071 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1073 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1074 void intel_ddi_clock_get(struct intel_encoder *encoder,
1075 struct intel_crtc_state *pipe_config);
1076 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1077 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1079 /* intel_frontbuffer.c */
1080 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1081 enum fb_op_origin origin);
1082 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1083 unsigned frontbuffer_bits);
1084 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1085 unsigned frontbuffer_bits);
1086 void intel_frontbuffer_flip(struct drm_device *dev,
1087 unsigned frontbuffer_bits);
1088 unsigned int intel_fb_align_height(struct drm_device *dev,
1089 unsigned int height,
1090 uint32_t pixel_format,
1091 uint64_t fb_format_modifier);
1092 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1093 enum fb_op_origin origin);
1094 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1095 uint64_t fb_modifier, uint32_t pixel_format);
1098 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1099 void intel_audio_codec_enable(struct intel_encoder *encoder);
1100 void intel_audio_codec_disable(struct intel_encoder *encoder);
1101 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1102 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1104 /* intel_display.c */
1105 extern const struct drm_plane_funcs intel_plane_funcs;
1106 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1107 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1108 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1109 void intel_mark_busy(struct drm_device *dev);
1110 void intel_mark_idle(struct drm_device *dev);
1111 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1112 int intel_display_suspend(struct drm_device *dev);
1113 void intel_encoder_destroy(struct drm_encoder *encoder);
1114 int intel_connector_init(struct intel_connector *);
1115 struct intel_connector *intel_connector_alloc(void);
1116 bool intel_connector_get_hw_state(struct intel_connector *connector);
1117 void intel_connector_attach_encoder(struct intel_connector *connector,
1118 struct intel_encoder *encoder);
1119 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1120 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1121 struct drm_crtc *crtc);
1122 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1123 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1124 struct drm_file *file_priv);
1125 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1127 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1129 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1131 drm_wait_one_vblank(dev, pipe);
1134 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1136 const struct intel_crtc *crtc =
1137 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1140 intel_wait_for_vblank(dev, pipe);
1142 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1143 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1144 struct intel_digital_port *dport,
1145 unsigned int expected_mask);
1146 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1147 struct drm_display_mode *mode,
1148 struct intel_load_detect_pipe *old,
1149 struct drm_modeset_acquire_ctx *ctx);
1150 void intel_release_load_detect_pipe(struct drm_connector *connector,
1151 struct intel_load_detect_pipe *old,
1152 struct drm_modeset_acquire_ctx *ctx);
1153 int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1154 unsigned int rotation);
1155 struct drm_framebuffer *
1156 __intel_framebuffer_create(struct drm_device *dev,
1157 struct drm_mode_fb_cmd2 *mode_cmd,
1158 struct drm_i915_gem_object *obj);
1159 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1160 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1161 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1162 void intel_check_page_flip(struct drm_device *dev, int pipe);
1163 int intel_prepare_plane_fb(struct drm_plane *plane,
1164 const struct drm_plane_state *new_state);
1165 void intel_cleanup_plane_fb(struct drm_plane *plane,
1166 const struct drm_plane_state *old_state);
1167 int intel_plane_atomic_get_property(struct drm_plane *plane,
1168 const struct drm_plane_state *state,
1169 struct drm_property *property,
1171 int intel_plane_atomic_set_property(struct drm_plane *plane,
1172 struct drm_plane_state *state,
1173 struct drm_property *property,
1175 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1176 struct drm_plane_state *plane_state);
1178 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1179 uint64_t fb_modifier, unsigned int cpp);
1182 intel_rotation_90_or_270(unsigned int rotation)
1184 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1187 void intel_create_rotation_property(struct drm_device *dev,
1188 struct intel_plane *plane);
1190 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1193 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1194 const struct dpll *dpll);
1195 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1196 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1198 /* modesetting asserts */
1199 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1201 void assert_pll(struct drm_i915_private *dev_priv,
1202 enum pipe pipe, bool state);
1203 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1204 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1205 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1206 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1207 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1208 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1209 enum pipe pipe, bool state);
1210 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1211 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1212 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1213 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1214 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1215 u32 intel_compute_tile_offset(int *x, int *y,
1216 const struct drm_framebuffer *fb, int plane,
1218 unsigned int rotation);
1219 void intel_prepare_reset(struct drm_device *dev);
1220 void intel_finish_reset(struct drm_device *dev);
1221 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1222 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1223 void broxton_init_cdclk(struct drm_device *dev);
1224 void broxton_uninit_cdclk(struct drm_device *dev);
1225 void broxton_ddi_phy_init(struct drm_device *dev);
1226 void broxton_ddi_phy_uninit(struct drm_device *dev);
1227 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1228 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1229 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1230 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
1231 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1232 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1233 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1234 void intel_dp_get_m_n(struct intel_crtc *crtc,
1235 struct intel_crtc_state *pipe_config);
1236 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1237 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1238 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1239 intel_clock_t *best_clock);
1240 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1242 bool intel_crtc_active(struct drm_crtc *crtc);
1243 void hsw_enable_ips(struct intel_crtc *crtc);
1244 void hsw_disable_ips(struct intel_crtc *crtc);
1245 enum intel_display_power_domain
1246 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1247 enum intel_display_power_domain
1248 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1249 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1250 struct intel_crtc_state *pipe_config);
1252 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1253 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1255 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1256 struct drm_i915_gem_object *obj,
1257 unsigned int plane);
1259 u32 skl_plane_ctl_format(uint32_t pixel_format);
1260 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1261 u32 skl_plane_ctl_rotation(unsigned int rotation);
1264 void intel_csr_ucode_init(struct drm_i915_private *);
1265 void intel_csr_load_program(struct drm_i915_private *);
1266 void intel_csr_ucode_fini(struct drm_i915_private *);
1269 void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1270 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1271 struct intel_connector *intel_connector);
1272 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1273 const struct intel_crtc_state *pipe_config);
1274 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1275 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1276 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1277 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1278 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1279 bool intel_dp_compute_config(struct intel_encoder *encoder,
1280 struct intel_crtc_state *pipe_config);
1281 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1282 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1284 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1285 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1286 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1287 void intel_edp_panel_on(struct intel_dp *intel_dp);
1288 void intel_edp_panel_off(struct intel_dp *intel_dp);
1289 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1290 void intel_dp_mst_suspend(struct drm_device *dev);
1291 void intel_dp_mst_resume(struct drm_device *dev);
1292 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1293 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1294 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1295 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1296 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1297 void intel_plane_destroy(struct drm_plane *plane);
1298 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1299 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1300 void intel_edp_drrs_invalidate(struct drm_device *dev,
1301 unsigned frontbuffer_bits);
1302 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1303 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1304 struct intel_digital_port *port);
1307 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1308 uint8_t dp_train_pat);
1310 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1311 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1313 intel_dp_voltage_max(struct intel_dp *intel_dp);
1315 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1316 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1317 uint8_t *link_bw, uint8_t *rate_select);
1318 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1320 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1322 /* intel_dp_mst.c */
1323 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1324 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1326 void intel_dsi_init(struct drm_device *dev);
1330 void intel_dvo_init(struct drm_device *dev);
1333 /* legacy fbdev emulation in intel_fbdev.c */
1334 #ifdef CONFIG_DRM_FBDEV_EMULATION
1335 extern int intel_fbdev_init(struct drm_device *dev);
1336 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1337 extern void intel_fbdev_fini(struct drm_device *dev);
1338 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1339 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1340 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1342 static inline int intel_fbdev_init(struct drm_device *dev)
1347 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1351 static inline void intel_fbdev_fini(struct drm_device *dev)
1355 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1359 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1365 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1366 struct drm_atomic_state *state);
1367 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1368 void intel_fbc_pre_update(struct intel_crtc *crtc);
1369 void intel_fbc_post_update(struct intel_crtc *crtc);
1370 void intel_fbc_init(struct drm_i915_private *dev_priv);
1371 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1372 void intel_fbc_enable(struct intel_crtc *crtc);
1373 void intel_fbc_disable(struct intel_crtc *crtc);
1374 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1375 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1376 unsigned int frontbuffer_bits,
1377 enum fb_op_origin origin);
1378 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1379 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1380 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1383 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1384 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1385 struct intel_connector *intel_connector);
1386 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1387 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1388 struct intel_crtc_state *pipe_config);
1392 void intel_lvds_init(struct drm_device *dev);
1393 bool intel_is_dual_link_lvds(struct drm_device *dev);
1397 int intel_connector_update_modes(struct drm_connector *connector,
1399 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1400 void intel_attach_force_audio_property(struct drm_connector *connector);
1401 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1402 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1405 /* intel_overlay.c */
1406 void intel_setup_overlay(struct drm_device *dev);
1407 void intel_cleanup_overlay(struct drm_device *dev);
1408 int intel_overlay_switch_off(struct intel_overlay *overlay);
1409 int intel_overlay_put_image(struct drm_device *dev, void *data,
1410 struct drm_file *file_priv);
1411 int intel_overlay_attrs(struct drm_device *dev, void *data,
1412 struct drm_file *file_priv);
1413 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1417 int intel_panel_init(struct intel_panel *panel,
1418 struct drm_display_mode *fixed_mode,
1419 struct drm_display_mode *downclock_mode);
1420 void intel_panel_fini(struct intel_panel *panel);
1421 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1422 struct drm_display_mode *adjusted_mode);
1423 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1424 struct intel_crtc_state *pipe_config,
1426 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1427 struct intel_crtc_state *pipe_config,
1429 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1430 u32 level, u32 max);
1431 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1432 void intel_panel_enable_backlight(struct intel_connector *connector);
1433 void intel_panel_disable_backlight(struct intel_connector *connector);
1434 void intel_panel_destroy_backlight(struct drm_connector *connector);
1435 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1436 extern struct drm_display_mode *intel_find_panel_downclock(
1437 struct drm_device *dev,
1438 struct drm_display_mode *fixed_mode,
1439 struct drm_connector *connector);
1440 void intel_backlight_register(struct drm_device *dev);
1441 void intel_backlight_unregister(struct drm_device *dev);
1445 void intel_psr_enable(struct intel_dp *intel_dp);
1446 void intel_psr_disable(struct intel_dp *intel_dp);
1447 void intel_psr_invalidate(struct drm_device *dev,
1448 unsigned frontbuffer_bits);
1449 void intel_psr_flush(struct drm_device *dev,
1450 unsigned frontbuffer_bits,
1451 enum fb_op_origin origin);
1452 void intel_psr_init(struct drm_device *dev);
1453 void intel_psr_single_frame_update(struct drm_device *dev,
1454 unsigned frontbuffer_bits);
1456 /* intel_runtime_pm.c */
1457 int intel_power_domains_init(struct drm_i915_private *);
1458 void intel_power_domains_fini(struct drm_i915_private *);
1459 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1460 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1461 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
1462 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
1463 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1465 intel_display_power_domain_str(enum intel_display_power_domain domain);
1467 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1468 enum intel_display_power_domain domain);
1469 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1470 enum intel_display_power_domain domain);
1471 void intel_display_power_get(struct drm_i915_private *dev_priv,
1472 enum intel_display_power_domain domain);
1473 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1474 enum intel_display_power_domain domain);
1475 void intel_display_power_put(struct drm_i915_private *dev_priv,
1476 enum intel_display_power_domain domain);
1479 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1481 WARN_ONCE(dev_priv->pm.suspended,
1482 "Device suspended during HW access\n");
1486 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1488 assert_rpm_device_not_suspended(dev_priv);
1489 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1490 * too much noise. */
1491 if (!atomic_read(&dev_priv->pm.wakeref_count))
1492 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1496 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1498 int seq = atomic_read(&dev_priv->pm.atomic_seq);
1500 assert_rpm_wakelock_held(dev_priv);
1506 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1508 WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1509 "HW access outside of RPM atomic section\n");
1513 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1514 * @dev_priv: i915 device instance
1516 * This function disable asserts that check if we hold an RPM wakelock
1517 * reference, while keeping the device-not-suspended checks still enabled.
1518 * It's meant to be used only in special circumstances where our rule about
1519 * the wakelock refcount wrt. the device power state doesn't hold. According
1520 * to this rule at any point where we access the HW or want to keep the HW in
1521 * an active state we must hold an RPM wakelock reference acquired via one of
1522 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1523 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1524 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1525 * users should avoid using this function.
1527 * Any calls to this function must have a symmetric call to
1528 * enable_rpm_wakeref_asserts().
1531 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1533 atomic_inc(&dev_priv->pm.wakeref_count);
1537 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1538 * @dev_priv: i915 device instance
1540 * This function re-enables the RPM assert checks after disabling them with
1541 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1542 * circumstances otherwise its use should be avoided.
1544 * Any calls to this function must have a symmetric call to
1545 * disable_rpm_wakeref_asserts().
1548 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1550 atomic_dec(&dev_priv->pm.wakeref_count);
1553 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1554 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1555 disable_rpm_wakeref_asserts(dev_priv)
1557 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1558 enable_rpm_wakeref_asserts(dev_priv)
1560 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1561 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1562 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1563 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1565 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1567 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1568 bool override, unsigned int mask);
1569 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1570 enum dpio_channel ch, bool override);
1574 void intel_init_clock_gating(struct drm_device *dev);
1575 void intel_suspend_hw(struct drm_device *dev);
1576 int ilk_wm_max_level(const struct drm_device *dev);
1577 void intel_update_watermarks(struct drm_crtc *crtc);
1578 void intel_init_pm(struct drm_device *dev);
1579 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1580 void intel_pm_setup(struct drm_device *dev);
1581 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1582 void intel_gpu_ips_teardown(void);
1583 void intel_init_gt_powersave(struct drm_device *dev);
1584 void intel_cleanup_gt_powersave(struct drm_device *dev);
1585 void intel_enable_gt_powersave(struct drm_device *dev);
1586 void intel_disable_gt_powersave(struct drm_device *dev);
1587 void intel_suspend_gt_powersave(struct drm_device *dev);
1588 void intel_reset_gt_powersave(struct drm_device *dev);
1589 void gen6_update_ring_freq(struct drm_device *dev);
1590 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1591 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1592 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1593 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1594 struct intel_rps_client *rps,
1595 unsigned long submitted);
1596 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1597 struct drm_i915_gem_request *req);
1598 void vlv_wm_get_hw_state(struct drm_device *dev);
1599 void ilk_wm_get_hw_state(struct drm_device *dev);
1600 void skl_wm_get_hw_state(struct drm_device *dev);
1601 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1602 struct skl_ddb_allocation *ddb /* out */);
1603 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1604 bool ilk_disable_lp_wm(struct drm_device *dev);
1605 int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6);
1608 bool intel_sdvo_init(struct drm_device *dev,
1609 i915_reg_t reg, enum port port);
1612 /* intel_sprite.c */
1613 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1614 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1615 struct drm_file *file_priv);
1616 void intel_pipe_update_start(struct intel_crtc *crtc);
1617 void intel_pipe_update_end(struct intel_crtc *crtc);
1620 void intel_tv_init(struct drm_device *dev);
1622 /* intel_atomic.c */
1623 int intel_connector_atomic_get_property(struct drm_connector *connector,
1624 const struct drm_connector_state *state,
1625 struct drm_property *property,
1627 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1628 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1629 struct drm_crtc_state *state);
1630 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1631 void intel_atomic_state_clear(struct drm_atomic_state *);
1632 struct intel_shared_dpll_config *
1633 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1635 static inline struct intel_crtc_state *
1636 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1637 struct intel_crtc *crtc)
1639 struct drm_crtc_state *crtc_state;
1640 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1641 if (IS_ERR(crtc_state))
1642 return ERR_CAST(crtc_state);
1644 return to_intel_crtc_state(crtc_state);
1647 static inline struct intel_plane_state *
1648 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1649 struct intel_plane *plane)
1651 struct drm_plane_state *plane_state;
1653 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1655 return to_intel_plane_state(plane_state);
1658 int intel_atomic_setup_scalers(struct drm_device *dev,
1659 struct intel_crtc *intel_crtc,
1660 struct intel_crtc_state *crtc_state);
1662 /* intel_atomic_plane.c */
1663 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1664 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1665 void intel_plane_destroy_state(struct drm_plane *plane,
1666 struct drm_plane_state *state);
1667 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1670 void intel_color_init(struct drm_crtc *crtc);
1671 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1672 void intel_color_set_csc(struct drm_crtc *crtc);
1673 void intel_color_load_luts(struct drm_crtc *crtc);
1675 #endif /* __INTEL_DRV_H__ */