2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
41 * _wait_for - magic (register) wait macro
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
48 #define _wait_for(COND, MS, W) ({ \
49 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
52 if (time_after(jiffies, timeout__)) { \
57 if ((W) && drm_can_sleep()) { \
58 usleep_range((W)*1000, (W)*2000); \
66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
69 DIV_ROUND_UP((US), 1000), 0)
71 #define KHz(x) (1000 * (x))
72 #define MHz(x) KHz(1000 * (x))
75 * Display related stuff
78 /* store information about an Ixxx DVO */
79 /* The i830->i865 use multiple DVOs with multiple i2cs */
80 /* the i915, i945 have a single sDVO i2c bus - which is different */
82 /* maximum connectors per crtcs in the mode set */
84 /* Maximum cursor sizes */
85 #define GEN2_CURSOR_WIDTH 64
86 #define GEN2_CURSOR_HEIGHT 64
87 #define MAX_CURSOR_WIDTH 256
88 #define MAX_CURSOR_HEIGHT 256
90 #define INTEL_I2C_BUS_DVO 1
91 #define INTEL_I2C_BUS_SDVO 2
93 /* these are outputs from the chip - integrated only
94 external chips are via DVO or SDVO output */
95 enum intel_output_type {
96 INTEL_OUTPUT_UNUSED = 0,
97 INTEL_OUTPUT_ANALOG = 1,
99 INTEL_OUTPUT_SDVO = 3,
100 INTEL_OUTPUT_LVDS = 4,
101 INTEL_OUTPUT_TVOUT = 5,
102 INTEL_OUTPUT_HDMI = 6,
103 INTEL_OUTPUT_DISPLAYPORT = 7,
104 INTEL_OUTPUT_EDP = 8,
105 INTEL_OUTPUT_DSI = 9,
106 INTEL_OUTPUT_UNKNOWN = 10,
107 INTEL_OUTPUT_DP_MST = 11,
110 #define INTEL_DVO_CHIP_NONE 0
111 #define INTEL_DVO_CHIP_LVDS 1
112 #define INTEL_DVO_CHIP_TMDS 2
113 #define INTEL_DVO_CHIP_TVOUT 4
115 #define INTEL_DSI_VIDEO_MODE 0
116 #define INTEL_DSI_COMMAND_MODE 1
118 struct intel_framebuffer {
119 struct drm_framebuffer base;
120 struct drm_i915_gem_object *obj;
124 struct drm_fb_helper helper;
125 struct intel_framebuffer *fb;
129 struct intel_encoder {
130 struct drm_encoder base;
132 enum intel_output_type type;
133 unsigned int cloneable;
134 void (*hot_plug)(struct intel_encoder *);
135 bool (*compute_config)(struct intel_encoder *,
136 struct intel_crtc_state *);
137 void (*pre_pll_enable)(struct intel_encoder *);
138 void (*pre_enable)(struct intel_encoder *);
139 void (*enable)(struct intel_encoder *);
140 void (*mode_set)(struct intel_encoder *intel_encoder);
141 void (*disable)(struct intel_encoder *);
142 void (*post_disable)(struct intel_encoder *);
143 void (*post_pll_disable)(struct intel_encoder *);
144 /* Read out the current hw state of this connector, returning true if
145 * the encoder is active. If the encoder is enabled it also set the pipe
146 * it is connected to in the pipe parameter. */
147 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
148 /* Reconstructs the equivalent mode flags for the current hardware
149 * state. This must be called _after_ display->get_pipe_config has
150 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
151 * be set correctly before calling this function. */
152 void (*get_config)(struct intel_encoder *,
153 struct intel_crtc_state *pipe_config);
155 * Called during system suspend after all pending requests for the
156 * encoder are flushed (for example for DP AUX transactions) and
157 * device interrupts are disabled.
159 void (*suspend)(struct intel_encoder *);
161 enum hpd_pin hpd_pin;
165 struct drm_display_mode *fixed_mode;
166 struct drm_display_mode *downclock_mode;
176 bool combination_mode; /* gen 2/4 only */
180 bool util_pin_active_low; /* bxt+ */
181 u8 controller; /* bxt+ only */
182 struct pwm_device *pwm;
184 struct backlight_device *device;
186 /* Connector and platform specific backlight functions */
187 int (*setup)(struct intel_connector *connector, enum pipe pipe);
188 uint32_t (*get)(struct intel_connector *connector);
189 void (*set)(struct intel_connector *connector, uint32_t level);
190 void (*disable)(struct intel_connector *connector);
191 void (*enable)(struct intel_connector *connector);
192 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
194 void (*power)(struct intel_connector *, bool enable);
198 struct intel_connector {
199 struct drm_connector base;
201 * The fixed encoder this connector is connected to.
203 struct intel_encoder *encoder;
205 /* Reads out the current hw, returning true if the connector is enabled
206 * and active (i.e. dpms ON state). */
207 bool (*get_hw_state)(struct intel_connector *);
210 * Removes all interfaces through which the connector is accessible
211 * - like sysfs, debugfs entries -, so that no new operations can be
212 * started on the connector. Also makes sure all currently pending
213 * operations finish before returing.
215 void (*unregister)(struct intel_connector *);
217 /* Panel info for eDP and LVDS */
218 struct intel_panel panel;
220 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
222 struct edid *detect_edid;
224 /* since POLL and HPD connectors may use the same HPD line keep the native
225 state of connector->polled in case hotplug storm detection changes it */
228 void *port; /* store this opaque as its illegal to dereference it */
230 struct intel_dp *mst_port;
233 typedef struct dpll {
245 struct intel_atomic_state {
246 struct drm_atomic_state base;
250 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
253 struct intel_plane_state {
254 struct drm_plane_state base;
257 struct drm_rect clip;
262 * = -1 : not using a scaler
263 * >= 0 : using a scalers
265 * plane requiring a scaler:
266 * - During check_plane, its bit is set in
267 * crtc_state->scaler_state.scaler_users by calling helper function
268 * update_scaler_plane.
269 * - scaler_id indicates the scaler it got assigned.
271 * plane doesn't require a scaler:
272 * - this can happen when scaling is no more required or plane simply
274 * - During check_plane, corresponding bit is reset in
275 * crtc_state->scaler_state.scaler_users by calling helper function
276 * update_scaler_plane.
280 struct drm_intel_sprite_colorkey ckey;
283 struct intel_initial_plane_config {
284 struct intel_framebuffer *fb;
290 #define SKL_MIN_SRC_W 8
291 #define SKL_MAX_SRC_W 4096
292 #define SKL_MIN_SRC_H 8
293 #define SKL_MAX_SRC_H 4096
294 #define SKL_MIN_DST_W 8
295 #define SKL_MAX_DST_W 4096
296 #define SKL_MIN_DST_H 8
297 #define SKL_MAX_DST_H 4096
299 struct intel_scaler {
304 struct intel_crtc_scaler_state {
305 #define SKL_NUM_SCALERS 2
306 struct intel_scaler scalers[SKL_NUM_SCALERS];
309 * scaler_users: keeps track of users requesting scalers on this crtc.
311 * If a bit is set, a user is using a scaler.
312 * Here user can be a plane or crtc as defined below:
313 * bits 0-30 - plane (bit position is index from drm_plane_index)
316 * Instead of creating a new index to cover planes and crtc, using
317 * existing drm_plane_index for planes which is well less than 31
318 * planes and bit 31 for crtc. This should be fine to cover all
321 * intel_atomic_setup_scalers will setup available scalers to users
322 * requesting scalers. It will gracefully fail if request exceeds
325 #define SKL_CRTC_INDEX 31
326 unsigned scaler_users;
328 /* scaler used by crtc for panel fitting purpose */
332 /* drm_mode->private_flags */
333 #define I915_MODE_FLAG_INHERITED 1
335 struct intel_crtc_state {
336 struct drm_crtc_state base;
339 * quirks - bitfield with hw state readout quirks
341 * For various reasons the hw state readout code might not be able to
342 * completely faithfully read out the current state. These cases are
343 * tracked with quirk flags so that fastboot and state checker can act
346 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
347 unsigned long quirks;
351 /* Pipe source size (ie. panel fitter input size)
352 * All planes will be positioned inside this space,
353 * and get clipped at the edges. */
354 int pipe_src_w, pipe_src_h;
356 /* Whether to set up the PCH/FDI. Note that we never allow sharing
357 * between pch encoders and cpu encoders. */
358 bool has_pch_encoder;
360 /* Are we sending infoframes on the attached port */
363 /* CPU Transcoder for the pipe. Currently this can only differ from the
364 * pipe on Haswell (where we have a special eDP transcoder). */
365 enum transcoder cpu_transcoder;
368 * Use reduced/limited/broadcast rbg range, compressing from the full
369 * range fed into the crtcs.
371 bool limited_color_range;
373 /* DP has a bunch of special case unfortunately, so mark the pipe
377 /* Whether we should send NULL infoframes. Required for audio. */
380 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
381 * has_dp_encoder is set. */
385 * Enable dithering, used when the selected pipe bpp doesn't match the
390 /* Controls for the clock computation, to override various stages. */
393 /* SDVO TV has a bunch of special case. To make multifunction encoders
394 * work correctly, we need to track this at runtime.*/
398 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
399 * required. This is set in the 2nd loop of calling encoder's
400 * ->compute_config if the first pick doesn't work out.
404 /* Settings for the intel dpll used on pretty much everything but
408 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
409 enum intel_dpll_id shared_dpll;
412 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
413 * - enum skl_dpll on SKL
415 uint32_t ddi_pll_sel;
417 /* Actual register state of the dpll, for shared dpll cross-checking. */
418 struct intel_dpll_hw_state dpll_hw_state;
421 struct intel_link_m_n dp_m_n;
423 /* m2_n2 for eDP downclock */
424 struct intel_link_m_n dp_m2_n2;
428 * Frequence the dpll for the port should run at. Differs from the
429 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
430 * already multiplied by pixel_multiplier.
434 /* Used by SDVO (and if we ever fix it, HDMI). */
435 unsigned pixel_multiplier;
439 /* Panel fitter controls for gen2-gen4 + VLV */
443 u32 lvds_border_bits;
446 /* Panel fitter placement and size for Ironlake+ */
454 /* FDI configuration, only valid if has_pch_encoder is set. */
456 struct intel_link_m_n fdi_m_n;
462 bool dp_encoder_is_mst;
465 struct intel_crtc_scaler_state scaler_state;
467 /* w/a for waiting 2 vblanks during crtc enable */
468 enum pipe hsw_workaround_pipe;
471 struct vlv_wm_state {
472 struct vlv_pipe_wm wm[3];
473 struct vlv_sr_wm sr[3];
474 uint8_t num_active_planes;
480 struct intel_pipe_wm {
481 struct intel_wm_level wm[5];
485 bool sprites_enabled;
489 struct intel_mmio_flip {
490 struct work_struct work;
491 struct drm_i915_private *i915;
492 struct drm_i915_gem_request *req;
493 struct intel_crtc *crtc;
497 struct skl_wm_level wm[8];
498 struct skl_wm_level trans_wm;
503 * Tracking of operations that need to be performed at the beginning/end of an
504 * atomic commit, outside the atomic section where interrupts are disabled.
505 * These are generally operations that grab mutexes or might otherwise sleep
506 * and thus can't be run with interrupts disabled.
508 struct intel_crtc_atomic_commit {
509 /* Sleepable operations to perform before commit */
514 bool pre_disable_primary;
515 bool update_wm_pre, update_wm_post;
516 unsigned disabled_planes;
518 /* Sleepable operations to perform after commit */
522 bool post_enable_primary;
523 unsigned update_sprite_watermarks;
527 struct drm_crtc base;
530 u8 lut_r[256], lut_g[256], lut_b[256];
532 * Whether the crtc and the connected output pipeline is active. Implies
533 * that crtc->enabled is set, i.e. the current mode configuration has
534 * some outputs connected to this crtc.
537 unsigned long enabled_power_domains;
539 struct intel_overlay *overlay;
540 struct intel_unpin_work *unpin_work;
542 atomic_t unpin_work_count;
544 /* Display surface base address adjustement for pageflips. Note that on
545 * gen4+ this only adjusts up to a tile, offsets within a tile are
546 * handled in the hw itself (with the TILEOFF register). */
547 unsigned long dspaddr_offset;
551 struct drm_i915_gem_object *cursor_bo;
552 uint32_t cursor_addr;
553 uint32_t cursor_cntl;
554 uint32_t cursor_size;
555 uint32_t cursor_base;
557 struct intel_crtc_state *config;
559 /* reset counter value when the last flip was submitted */
560 unsigned int reset_counter;
562 /* Access to these should be protected by dev_priv->irq_lock. */
563 bool cpu_fifo_underrun_disabled;
564 bool pch_fifo_underrun_disabled;
566 /* per-pipe watermark state */
568 /* watermarks currently being used */
569 struct intel_pipe_wm active;
570 /* SKL wm values currently in use */
571 struct skl_pipe_wm skl_active;
572 /* allow CxSR on this pipe */
579 unsigned start_vbl_count;
580 ktime_t start_vbl_time;
581 int min_vbl, max_vbl;
585 struct intel_crtc_atomic_commit atomic;
587 /* scalers available on this crtc */
590 struct vlv_wm_state wm_state;
593 struct intel_plane_wm_parameters {
594 uint32_t horiz_pixels;
595 uint32_t vert_pixels;
597 * For packed pixel formats:
598 * bytes_per_pixel - holds bytes per pixel
599 * For planar pixel formats:
600 * bytes_per_pixel - holds bytes per pixel for uv-plane
601 * y_bytes_per_pixel - holds bytes per pixel for y-plane
603 uint8_t bytes_per_pixel;
604 uint8_t y_bytes_per_pixel;
608 unsigned int rotation;
613 struct drm_plane base;
618 uint32_t frontbuffer_bit;
620 /* Since we need to change the watermarks before/after
621 * enabling/disabling the planes, we need to store the parameters here
622 * as the other pieces of the struct may not reflect the values we want
623 * for the watermark calculations. Currently only Haswell uses this.
625 struct intel_plane_wm_parameters wm;
628 * NOTE: Do not place new plane state fields here (e.g., when adding
629 * new plane properties). New runtime state should now be placed in
630 * the intel_plane_state structure and accessed via drm_plane->state.
633 void (*update_plane)(struct drm_plane *plane,
634 struct drm_crtc *crtc,
635 struct drm_framebuffer *fb,
636 int crtc_x, int crtc_y,
637 unsigned int crtc_w, unsigned int crtc_h,
638 uint32_t x, uint32_t y,
639 uint32_t src_w, uint32_t src_h);
640 void (*disable_plane)(struct drm_plane *plane,
641 struct drm_crtc *crtc);
642 int (*check_plane)(struct drm_plane *plane,
643 struct intel_crtc_state *crtc_state,
644 struct intel_plane_state *state);
645 void (*commit_plane)(struct drm_plane *plane,
646 struct intel_plane_state *state);
649 struct intel_watermark_params {
650 unsigned long fifo_size;
651 unsigned long max_wm;
652 unsigned long default_wm;
653 unsigned long guard_size;
654 unsigned long cacheline_size;
657 struct cxsr_latency {
660 unsigned long fsb_freq;
661 unsigned long mem_freq;
662 unsigned long display_sr;
663 unsigned long display_hpll_disable;
664 unsigned long cursor_sr;
665 unsigned long cursor_hpll_disable;
668 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
669 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
670 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
671 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
672 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
673 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
674 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
675 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
676 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
681 bool limited_color_range;
682 bool color_range_auto;
685 enum hdmi_force_audio force_audio;
686 bool rgb_quant_range_selectable;
687 enum hdmi_picture_aspect aspect_ratio;
688 struct intel_connector *attached_connector;
689 void (*write_infoframe)(struct drm_encoder *encoder,
690 enum hdmi_infoframe_type type,
691 const void *frame, ssize_t len);
692 void (*set_infoframes)(struct drm_encoder *encoder,
694 const struct drm_display_mode *adjusted_mode);
695 bool (*infoframe_enabled)(struct drm_encoder *encoder);
698 struct intel_dp_mst_encoder;
699 #define DP_MAX_DOWNSTREAM_PORTS 0x10
703 * When platform provides two set of M_N registers for dp, we can
704 * program them and switch between them incase of DRRS.
705 * But When only one such register is provided, we have to program the
706 * required divider value on that registers itself based on the DRRS state.
708 * M1_N1 : Program dp_m_n on M1_N1 registers
709 * dp_m2_n2 on M2_N2 registers (If supported)
711 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
712 * M2_N2 registers are not supported
716 /* Sets the m1_n1 and m2_n2 */
729 uint32_t aux_ch_ctl_reg;
734 enum hdmi_force_audio force_audio;
735 bool limited_color_range;
736 bool color_range_auto;
737 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
738 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
739 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
740 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
741 uint8_t num_sink_rates;
742 int sink_rates[DP_MAX_SUPPORTED_RATES];
743 struct sink_crc sink_crc;
744 struct drm_dp_aux aux;
745 uint8_t train_set[4];
746 int panel_power_up_delay;
747 int panel_power_down_delay;
748 int panel_power_cycle_delay;
749 int backlight_on_delay;
750 int backlight_off_delay;
751 struct delayed_work panel_vdd_work;
753 unsigned long last_power_cycle;
754 unsigned long last_power_on;
755 unsigned long last_backlight_off;
757 struct notifier_block edp_notifier;
760 * Pipe whose power sequencer is currently locked into
761 * this port. Only relevant on VLV/CHV.
764 struct edp_power_seq pps_delays;
766 bool can_mst; /* this port supports mst */
768 int active_mst_links;
769 /* connector directly attached - won't be use for modeset in mst world */
770 struct intel_connector *attached_connector;
772 /* mst connector list */
773 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
774 struct drm_dp_mst_topology_mgr mst_mgr;
776 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
778 * This function returns the value we have to program the AUX_CTL
779 * register with to kick off an AUX transaction.
781 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
784 uint32_t aux_clock_divider);
785 bool train_set_valid;
787 /* Displayport compliance testing */
788 unsigned long compliance_test_type;
789 unsigned long compliance_test_data;
790 bool compliance_test_active;
793 struct intel_digital_port {
794 struct intel_encoder base;
798 struct intel_hdmi hdmi;
799 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
800 bool release_cl2_override;
803 struct intel_dp_mst_encoder {
804 struct intel_encoder base;
806 struct intel_digital_port *primary;
807 void *port; /* store this opaque as its illegal to dereference it */
810 static inline enum dpio_channel
811 vlv_dport_to_channel(struct intel_digital_port *dport)
813 switch (dport->port) {
824 static inline enum dpio_phy
825 vlv_dport_to_phy(struct intel_digital_port *dport)
827 switch (dport->port) {
838 static inline enum dpio_channel
839 vlv_pipe_to_channel(enum pipe pipe)
852 static inline struct drm_crtc *
853 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
855 struct drm_i915_private *dev_priv = dev->dev_private;
856 return dev_priv->pipe_to_crtc_mapping[pipe];
859 static inline struct drm_crtc *
860 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
862 struct drm_i915_private *dev_priv = dev->dev_private;
863 return dev_priv->plane_to_crtc_mapping[plane];
866 struct intel_unpin_work {
867 struct work_struct work;
868 struct drm_crtc *crtc;
869 struct drm_framebuffer *old_fb;
870 struct drm_i915_gem_object *pending_flip_obj;
871 struct drm_pending_vblank_event *event;
873 #define INTEL_FLIP_INACTIVE 0
874 #define INTEL_FLIP_PENDING 1
875 #define INTEL_FLIP_COMPLETE 2
878 struct drm_i915_gem_request *flip_queued_req;
879 u32 flip_queued_vblank;
880 u32 flip_ready_vblank;
881 bool enable_stall_check;
884 struct intel_load_detect_pipe {
885 struct drm_framebuffer *release_fb;
886 bool load_detect_temp;
890 static inline struct intel_encoder *
891 intel_attached_encoder(struct drm_connector *connector)
893 return to_intel_connector(connector)->encoder;
896 static inline struct intel_digital_port *
897 enc_to_dig_port(struct drm_encoder *encoder)
899 return container_of(encoder, struct intel_digital_port, base.base);
902 static inline struct intel_dp_mst_encoder *
903 enc_to_mst(struct drm_encoder *encoder)
905 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
908 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
910 return &enc_to_dig_port(encoder)->dp;
913 static inline struct intel_digital_port *
914 dp_to_dig_port(struct intel_dp *intel_dp)
916 return container_of(intel_dp, struct intel_digital_port, dp);
919 static inline struct intel_digital_port *
920 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
922 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
926 * Returns the number of planes for this pipe, ie the number of sprites + 1
927 * (primary plane). This doesn't count the cursor plane then.
929 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
931 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
934 /* intel_fifo_underrun.c */
935 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
936 enum pipe pipe, bool enable);
937 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
938 enum transcoder pch_transcoder,
940 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
942 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
943 enum transcoder pch_transcoder);
944 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
947 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
948 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
949 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
950 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
951 void gen6_reset_rps_interrupts(struct drm_device *dev);
952 void gen6_enable_rps_interrupts(struct drm_device *dev);
953 void gen6_disable_rps_interrupts(struct drm_device *dev);
954 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
955 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
956 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
957 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
960 * We only use drm_irq_uninstall() at unload and VT switch, so
961 * this is the only thing we need to check.
963 return dev_priv->pm.irqs_enabled;
966 int intel_get_crtc_scanline(struct intel_crtc *crtc);
967 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
968 unsigned int pipe_mask);
971 void intel_crt_init(struct drm_device *dev);
975 void intel_prepare_ddi(struct drm_device *dev);
976 void hsw_fdi_link_train(struct drm_crtc *crtc);
977 void intel_ddi_init(struct drm_device *dev, enum port port);
978 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
979 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
980 void intel_ddi_pll_init(struct drm_device *dev);
981 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
982 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
983 enum transcoder cpu_transcoder);
984 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
985 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
986 bool intel_ddi_pll_select(struct intel_crtc *crtc,
987 struct intel_crtc_state *crtc_state);
988 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
989 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
990 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
991 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
992 void intel_ddi_get_config(struct intel_encoder *encoder,
993 struct intel_crtc_state *pipe_config);
994 struct intel_encoder *
995 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
997 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
998 void intel_ddi_clock_get(struct intel_encoder *encoder,
999 struct intel_crtc_state *pipe_config);
1000 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1001 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1003 /* intel_frontbuffer.c */
1004 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1005 enum fb_op_origin origin);
1006 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1007 unsigned frontbuffer_bits);
1008 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1009 unsigned frontbuffer_bits);
1010 void intel_frontbuffer_flip(struct drm_device *dev,
1011 unsigned frontbuffer_bits);
1012 unsigned int intel_fb_align_height(struct drm_device *dev,
1013 unsigned int height,
1014 uint32_t pixel_format,
1015 uint64_t fb_format_modifier);
1016 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1017 enum fb_op_origin origin);
1018 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
1019 uint32_t pixel_format);
1022 void intel_init_audio(struct drm_device *dev);
1023 void intel_audio_codec_enable(struct intel_encoder *encoder);
1024 void intel_audio_codec_disable(struct intel_encoder *encoder);
1025 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1026 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1028 /* intel_display.c */
1029 extern const struct drm_plane_funcs intel_plane_funcs;
1030 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1031 int intel_pch_rawclk(struct drm_device *dev);
1032 int intel_hrawclk(struct drm_device *dev);
1033 void intel_mark_busy(struct drm_device *dev);
1034 void intel_mark_idle(struct drm_device *dev);
1035 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1036 int intel_display_suspend(struct drm_device *dev);
1037 void intel_encoder_destroy(struct drm_encoder *encoder);
1038 int intel_connector_init(struct intel_connector *);
1039 struct intel_connector *intel_connector_alloc(void);
1040 bool intel_connector_get_hw_state(struct intel_connector *connector);
1041 void intel_connector_attach_encoder(struct intel_connector *connector,
1042 struct intel_encoder *encoder);
1043 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1044 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1045 struct drm_crtc *crtc);
1046 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1047 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1048 struct drm_file *file_priv);
1049 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1051 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1053 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1055 drm_wait_one_vblank(dev, pipe);
1057 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1058 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1059 struct intel_digital_port *dport,
1060 unsigned int expected_mask);
1061 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1062 struct drm_display_mode *mode,
1063 struct intel_load_detect_pipe *old,
1064 struct drm_modeset_acquire_ctx *ctx);
1065 void intel_release_load_detect_pipe(struct drm_connector *connector,
1066 struct intel_load_detect_pipe *old,
1067 struct drm_modeset_acquire_ctx *ctx);
1068 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1069 struct drm_framebuffer *fb,
1070 const struct drm_plane_state *plane_state,
1071 struct intel_engine_cs *pipelined,
1072 struct drm_i915_gem_request **pipelined_request);
1073 struct drm_framebuffer *
1074 __intel_framebuffer_create(struct drm_device *dev,
1075 struct drm_mode_fb_cmd2 *mode_cmd,
1076 struct drm_i915_gem_object *obj);
1077 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1078 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1079 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1080 void intel_check_page_flip(struct drm_device *dev, int pipe);
1081 int intel_prepare_plane_fb(struct drm_plane *plane,
1082 const struct drm_plane_state *new_state);
1083 void intel_cleanup_plane_fb(struct drm_plane *plane,
1084 const struct drm_plane_state *old_state);
1085 int intel_plane_atomic_get_property(struct drm_plane *plane,
1086 const struct drm_plane_state *state,
1087 struct drm_property *property,
1089 int intel_plane_atomic_set_property(struct drm_plane *plane,
1090 struct drm_plane_state *state,
1091 struct drm_property *property,
1093 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1094 struct drm_plane_state *plane_state);
1097 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1098 uint64_t fb_format_modifier, unsigned int plane);
1101 intel_rotation_90_or_270(unsigned int rotation)
1103 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1106 void intel_create_rotation_property(struct drm_device *dev,
1107 struct intel_plane *plane);
1109 /* shared dpll functions */
1110 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1111 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1112 struct intel_shared_dpll *pll,
1114 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1115 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1116 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1117 struct intel_crtc_state *state);
1119 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1120 const struct dpll *dpll);
1121 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1123 /* modesetting asserts */
1124 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1126 void assert_pll(struct drm_i915_private *dev_priv,
1127 enum pipe pipe, bool state);
1128 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1129 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1130 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1131 enum pipe pipe, bool state);
1132 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1133 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1134 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1135 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1136 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1137 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
1139 unsigned int tiling_mode,
1141 unsigned int pitch);
1142 void intel_prepare_reset(struct drm_device *dev);
1143 void intel_finish_reset(struct drm_device *dev);
1144 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1145 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1146 void broxton_init_cdclk(struct drm_device *dev);
1147 void broxton_uninit_cdclk(struct drm_device *dev);
1148 void broxton_ddi_phy_init(struct drm_device *dev);
1149 void broxton_ddi_phy_uninit(struct drm_device *dev);
1150 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1151 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1152 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1153 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1154 void intel_dp_get_m_n(struct intel_crtc *crtc,
1155 struct intel_crtc_state *pipe_config);
1156 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1157 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1159 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1161 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1162 intel_clock_t *best_clock);
1163 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1165 bool intel_crtc_active(struct drm_crtc *crtc);
1166 void hsw_enable_ips(struct intel_crtc *crtc);
1167 void hsw_disable_ips(struct intel_crtc *crtc);
1168 enum intel_display_power_domain
1169 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1170 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1171 struct intel_crtc_state *pipe_config);
1172 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1173 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1175 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1176 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1178 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1179 struct drm_i915_gem_object *obj,
1180 unsigned int plane);
1182 u32 skl_plane_ctl_format(uint32_t pixel_format);
1183 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1184 u32 skl_plane_ctl_rotation(unsigned int rotation);
1187 void intel_csr_ucode_init(struct drm_device *dev);
1188 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1189 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1190 enum csr_state state);
1191 void intel_csr_load_program(struct drm_device *dev);
1192 void intel_csr_ucode_fini(struct drm_device *dev);
1193 void assert_csr_loaded(struct drm_i915_private *dev_priv);
1196 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1197 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1198 struct intel_connector *intel_connector);
1199 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1200 const struct intel_crtc_state *pipe_config);
1201 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1202 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1203 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1204 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1205 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1206 bool intel_dp_compute_config(struct intel_encoder *encoder,
1207 struct intel_crtc_state *pipe_config);
1208 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1209 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1211 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1212 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1213 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1214 void intel_edp_panel_on(struct intel_dp *intel_dp);
1215 void intel_edp_panel_off(struct intel_dp *intel_dp);
1216 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1217 void intel_dp_mst_suspend(struct drm_device *dev);
1218 void intel_dp_mst_resume(struct drm_device *dev);
1219 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1220 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1221 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1222 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1223 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1224 void intel_plane_destroy(struct drm_plane *plane);
1225 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1226 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1227 void intel_edp_drrs_invalidate(struct drm_device *dev,
1228 unsigned frontbuffer_bits);
1229 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1230 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1231 struct intel_digital_port *port);
1232 void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
1234 /* intel_dp_mst.c */
1235 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1236 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1238 void intel_dsi_init(struct drm_device *dev);
1242 void intel_dvo_init(struct drm_device *dev);
1245 /* legacy fbdev emulation in intel_fbdev.c */
1246 #ifdef CONFIG_DRM_FBDEV_EMULATION
1247 extern int intel_fbdev_init(struct drm_device *dev);
1248 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1249 extern void intel_fbdev_fini(struct drm_device *dev);
1250 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1251 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1252 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1254 static inline int intel_fbdev_init(struct drm_device *dev)
1259 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1263 static inline void intel_fbdev_fini(struct drm_device *dev)
1267 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1271 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1277 bool intel_fbc_enabled(struct drm_i915_private *dev_priv);
1278 void intel_fbc_update(struct drm_i915_private *dev_priv);
1279 void intel_fbc_init(struct drm_i915_private *dev_priv);
1280 void intel_fbc_disable(struct drm_i915_private *dev_priv);
1281 void intel_fbc_disable_crtc(struct intel_crtc *crtc);
1282 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1283 unsigned int frontbuffer_bits,
1284 enum fb_op_origin origin);
1285 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1286 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1287 const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
1288 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1291 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1292 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1293 struct intel_connector *intel_connector);
1294 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1295 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1296 struct intel_crtc_state *pipe_config);
1300 void intel_lvds_init(struct drm_device *dev);
1301 bool intel_is_dual_link_lvds(struct drm_device *dev);
1305 int intel_connector_update_modes(struct drm_connector *connector,
1307 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1308 void intel_attach_force_audio_property(struct drm_connector *connector);
1309 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1310 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1313 /* intel_overlay.c */
1314 void intel_setup_overlay(struct drm_device *dev);
1315 void intel_cleanup_overlay(struct drm_device *dev);
1316 int intel_overlay_switch_off(struct intel_overlay *overlay);
1317 int intel_overlay_put_image(struct drm_device *dev, void *data,
1318 struct drm_file *file_priv);
1319 int intel_overlay_attrs(struct drm_device *dev, void *data,
1320 struct drm_file *file_priv);
1321 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1325 int intel_panel_init(struct intel_panel *panel,
1326 struct drm_display_mode *fixed_mode,
1327 struct drm_display_mode *downclock_mode);
1328 void intel_panel_fini(struct intel_panel *panel);
1329 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1330 struct drm_display_mode *adjusted_mode);
1331 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1332 struct intel_crtc_state *pipe_config,
1334 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1335 struct intel_crtc_state *pipe_config,
1337 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1338 u32 level, u32 max);
1339 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1340 void intel_panel_enable_backlight(struct intel_connector *connector);
1341 void intel_panel_disable_backlight(struct intel_connector *connector);
1342 void intel_panel_destroy_backlight(struct drm_connector *connector);
1343 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1344 extern struct drm_display_mode *intel_find_panel_downclock(
1345 struct drm_device *dev,
1346 struct drm_display_mode *fixed_mode,
1347 struct drm_connector *connector);
1348 void intel_backlight_register(struct drm_device *dev);
1349 void intel_backlight_unregister(struct drm_device *dev);
1353 void intel_psr_enable(struct intel_dp *intel_dp);
1354 void intel_psr_disable(struct intel_dp *intel_dp);
1355 void intel_psr_invalidate(struct drm_device *dev,
1356 unsigned frontbuffer_bits);
1357 void intel_psr_flush(struct drm_device *dev,
1358 unsigned frontbuffer_bits,
1359 enum fb_op_origin origin);
1360 void intel_psr_init(struct drm_device *dev);
1361 void intel_psr_single_frame_update(struct drm_device *dev,
1362 unsigned frontbuffer_bits);
1364 /* intel_runtime_pm.c */
1365 int intel_power_domains_init(struct drm_i915_private *);
1366 void intel_power_domains_fini(struct drm_i915_private *);
1367 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1368 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1370 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1371 enum intel_display_power_domain domain);
1372 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1373 enum intel_display_power_domain domain);
1374 void intel_display_power_get(struct drm_i915_private *dev_priv,
1375 enum intel_display_power_domain domain);
1376 void intel_display_power_put(struct drm_i915_private *dev_priv,
1377 enum intel_display_power_domain domain);
1378 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1379 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1380 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1381 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1382 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1384 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1386 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1387 bool override, unsigned int mask);
1388 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1389 enum dpio_channel ch, bool override);
1393 void intel_init_clock_gating(struct drm_device *dev);
1394 void intel_suspend_hw(struct drm_device *dev);
1395 int ilk_wm_max_level(const struct drm_device *dev);
1396 void intel_update_watermarks(struct drm_crtc *crtc);
1397 void intel_update_sprite_watermarks(struct drm_plane *plane,
1398 struct drm_crtc *crtc,
1399 uint32_t sprite_width,
1400 uint32_t sprite_height,
1402 bool enabled, bool scaled);
1403 void intel_init_pm(struct drm_device *dev);
1404 void intel_pm_setup(struct drm_device *dev);
1405 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1406 void intel_gpu_ips_teardown(void);
1407 void intel_init_gt_powersave(struct drm_device *dev);
1408 void intel_cleanup_gt_powersave(struct drm_device *dev);
1409 void intel_enable_gt_powersave(struct drm_device *dev);
1410 void intel_disable_gt_powersave(struct drm_device *dev);
1411 void intel_suspend_gt_powersave(struct drm_device *dev);
1412 void intel_reset_gt_powersave(struct drm_device *dev);
1413 void gen6_update_ring_freq(struct drm_device *dev);
1414 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1415 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1416 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1417 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1418 struct intel_rps_client *rps,
1419 unsigned long submitted);
1420 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1421 struct drm_i915_gem_request *req);
1422 void vlv_wm_get_hw_state(struct drm_device *dev);
1423 void ilk_wm_get_hw_state(struct drm_device *dev);
1424 void skl_wm_get_hw_state(struct drm_device *dev);
1425 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1426 struct skl_ddb_allocation *ddb /* out */);
1427 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1430 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1433 /* intel_sprite.c */
1434 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1435 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1436 struct drm_file *file_priv);
1437 void intel_pipe_update_start(struct intel_crtc *crtc);
1438 void intel_pipe_update_end(struct intel_crtc *crtc);
1441 void intel_tv_init(struct drm_device *dev);
1443 /* intel_atomic.c */
1444 int intel_connector_atomic_get_property(struct drm_connector *connector,
1445 const struct drm_connector_state *state,
1446 struct drm_property *property,
1448 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1449 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1450 struct drm_crtc_state *state);
1451 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1452 void intel_atomic_state_clear(struct drm_atomic_state *);
1453 struct intel_shared_dpll_config *
1454 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1456 static inline struct intel_crtc_state *
1457 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1458 struct intel_crtc *crtc)
1460 struct drm_crtc_state *crtc_state;
1461 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1462 if (IS_ERR(crtc_state))
1463 return ERR_CAST(crtc_state);
1465 return to_intel_crtc_state(crtc_state);
1467 int intel_atomic_setup_scalers(struct drm_device *dev,
1468 struct intel_crtc *intel_crtc,
1469 struct intel_crtc_state *crtc_state);
1471 /* intel_atomic_plane.c */
1472 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1473 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1474 void intel_plane_destroy_state(struct drm_plane *plane,
1475 struct drm_plane_state *state);
1476 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1478 #endif /* __INTEL_DRV_H__ */