2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_dual_mode_helper.h>
37 #include <drm/drm_dp_mst_helper.h>
38 #include <drm/drm_rect.h>
39 #include <drm/drm_atomic.h>
42 * _wait_for - magic (register) wait macro
44 * Does the right thing for modeset paths when run under kdgb or similar atomic
45 * contexts. Note that it's important that we check the condition again after
46 * having timed out, since the timeout could be due to preemption or similar and
47 * we've never had a chance to check the condition before the timeout.
49 * TODO: When modesetting has fully transitioned to atomic, the below
50 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
53 #define _wait_for(COND, US, W) ({ \
54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
57 bool expired__ = time_after(jiffies, timeout__); \
66 if ((W) && drm_can_sleep()) { \
67 usleep_range((W), (W)*2); \
75 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
77 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
78 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
79 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
84 #define _wait_for_atomic(COND, US, ATOMIC) \
86 int cpu, ret, timeout = (US) * 1000; \
88 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
89 BUILD_BUG_ON((US) > 50000); \
92 cpu = smp_processor_id(); \
94 base = local_clock(); \
96 u64 now = local_clock(); \
103 if (now - base >= timeout) { \
110 if (unlikely(cpu != smp_processor_id())) { \
111 timeout -= now - base; \
112 cpu = smp_processor_id(); \
113 base = local_clock(); \
120 #define wait_for_us(COND, US) \
123 BUILD_BUG_ON(!__builtin_constant_p(US)); \
125 ret__ = _wait_for((COND), (US), 10); \
127 ret__ = _wait_for_atomic((COND), (US), 0); \
131 #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000, 1)
132 #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US), 1)
134 #define KHz(x) (1000 * (x))
135 #define MHz(x) KHz(1000 * (x))
138 * Display related stuff
141 /* store information about an Ixxx DVO */
142 /* The i830->i865 use multiple DVOs with multiple i2cs */
143 /* the i915, i945 have a single sDVO i2c bus - which is different */
144 #define MAX_OUTPUTS 6
145 /* maximum connectors per crtcs in the mode set */
147 /* Maximum cursor sizes */
148 #define GEN2_CURSOR_WIDTH 64
149 #define GEN2_CURSOR_HEIGHT 64
150 #define MAX_CURSOR_WIDTH 256
151 #define MAX_CURSOR_HEIGHT 256
153 #define INTEL_I2C_BUS_DVO 1
154 #define INTEL_I2C_BUS_SDVO 2
156 /* these are outputs from the chip - integrated only
157 external chips are via DVO or SDVO output */
158 enum intel_output_type {
159 INTEL_OUTPUT_UNUSED = 0,
160 INTEL_OUTPUT_ANALOG = 1,
161 INTEL_OUTPUT_DVO = 2,
162 INTEL_OUTPUT_SDVO = 3,
163 INTEL_OUTPUT_LVDS = 4,
164 INTEL_OUTPUT_TVOUT = 5,
165 INTEL_OUTPUT_HDMI = 6,
167 INTEL_OUTPUT_EDP = 8,
168 INTEL_OUTPUT_DSI = 9,
169 INTEL_OUTPUT_UNKNOWN = 10,
170 INTEL_OUTPUT_DP_MST = 11,
173 #define INTEL_DVO_CHIP_NONE 0
174 #define INTEL_DVO_CHIP_LVDS 1
175 #define INTEL_DVO_CHIP_TMDS 2
176 #define INTEL_DVO_CHIP_TVOUT 4
178 #define INTEL_DSI_VIDEO_MODE 0
179 #define INTEL_DSI_COMMAND_MODE 1
181 struct intel_framebuffer {
182 struct drm_framebuffer base;
183 struct drm_i915_gem_object *obj;
184 struct intel_rotation_info rot_info;
186 /* for each plane in the normal GTT view */
190 /* for each plane in the rotated GTT view */
193 unsigned int pitch; /* pixels */
198 struct drm_fb_helper helper;
199 struct intel_framebuffer *fb;
200 struct i915_vma *vma;
201 async_cookie_t cookie;
205 struct intel_encoder {
206 struct drm_encoder base;
208 enum intel_output_type type;
209 unsigned int cloneable;
210 void (*hot_plug)(struct intel_encoder *);
211 bool (*compute_config)(struct intel_encoder *,
212 struct intel_crtc_state *,
213 struct drm_connector_state *);
214 void (*pre_pll_enable)(struct intel_encoder *,
215 struct intel_crtc_state *,
216 struct drm_connector_state *);
217 void (*pre_enable)(struct intel_encoder *,
218 struct intel_crtc_state *,
219 struct drm_connector_state *);
220 void (*enable)(struct intel_encoder *,
221 struct intel_crtc_state *,
222 struct drm_connector_state *);
223 void (*disable)(struct intel_encoder *,
224 struct intel_crtc_state *,
225 struct drm_connector_state *);
226 void (*post_disable)(struct intel_encoder *,
227 struct intel_crtc_state *,
228 struct drm_connector_state *);
229 void (*post_pll_disable)(struct intel_encoder *,
230 struct intel_crtc_state *,
231 struct drm_connector_state *);
232 /* Read out the current hw state of this connector, returning true if
233 * the encoder is active. If the encoder is enabled it also set the pipe
234 * it is connected to in the pipe parameter. */
235 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
236 /* Reconstructs the equivalent mode flags for the current hardware
237 * state. This must be called _after_ display->get_pipe_config has
238 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
239 * be set correctly before calling this function. */
240 void (*get_config)(struct intel_encoder *,
241 struct intel_crtc_state *pipe_config);
243 * Called during system suspend after all pending requests for the
244 * encoder are flushed (for example for DP AUX transactions) and
245 * device interrupts are disabled.
247 void (*suspend)(struct intel_encoder *);
249 enum hpd_pin hpd_pin;
253 struct drm_display_mode *fixed_mode;
254 struct drm_display_mode *downclock_mode;
264 bool combination_mode; /* gen 2/4 only */
268 bool util_pin_active_low; /* bxt+ */
269 u8 controller; /* bxt+ only */
270 struct pwm_device *pwm;
272 struct backlight_device *device;
274 /* Connector and platform specific backlight functions */
275 int (*setup)(struct intel_connector *connector, enum pipe pipe);
276 uint32_t (*get)(struct intel_connector *connector);
277 void (*set)(struct intel_connector *connector, uint32_t level);
278 void (*disable)(struct intel_connector *connector);
279 void (*enable)(struct intel_connector *connector);
280 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
282 void (*power)(struct intel_connector *, bool enable);
286 struct intel_connector {
287 struct drm_connector base;
289 * The fixed encoder this connector is connected to.
291 struct intel_encoder *encoder;
293 /* Reads out the current hw, returning true if the connector is enabled
294 * and active (i.e. dpms ON state). */
295 bool (*get_hw_state)(struct intel_connector *);
297 /* Panel info for eDP and LVDS */
298 struct intel_panel panel;
300 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
302 struct edid *detect_edid;
304 /* since POLL and HPD connectors may use the same HPD line keep the native
305 state of connector->polled in case hotplug storm detection changes it */
308 void *port; /* store this opaque as its illegal to dereference it */
310 struct intel_dp *mst_port;
325 struct intel_atomic_state {
326 struct drm_atomic_state base;
331 * Calculated device cdclk, can be different from cdclk
332 * only when all crtc's are DPMS off.
334 unsigned int dev_cdclk;
336 bool dpll_set, modeset;
339 * Does this transaction change the pipes that are active? This mask
340 * tracks which CRTC's have changed their active state at the end of
341 * the transaction (not counting the temporary disable during modesets).
342 * This mask should only be non-zero when intel_state->modeset is true,
343 * but the converse is not necessarily true; simply changing a mode may
344 * not flip the final active status of any CRTC's
346 unsigned int active_pipe_changes;
348 unsigned int active_crtcs;
349 unsigned int min_pixclk[I915_MAX_PIPES];
352 unsigned int cdclk_pll_vco;
354 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
357 * Current watermarks can't be trusted during hardware readout, so
358 * don't bother calculating intermediate watermarks.
360 bool skip_intermediate_wm;
363 struct skl_wm_values wm_results;
366 struct intel_plane_state {
367 struct drm_plane_state base;
368 struct drm_rect clip;
381 * = -1 : not using a scaler
382 * >= 0 : using a scalers
384 * plane requiring a scaler:
385 * - During check_plane, its bit is set in
386 * crtc_state->scaler_state.scaler_users by calling helper function
387 * update_scaler_plane.
388 * - scaler_id indicates the scaler it got assigned.
390 * plane doesn't require a scaler:
391 * - this can happen when scaling is no more required or plane simply
393 * - During check_plane, corresponding bit is reset in
394 * crtc_state->scaler_state.scaler_users by calling helper function
395 * update_scaler_plane.
399 struct drm_intel_sprite_colorkey ckey;
401 /* async flip related structures */
402 struct drm_i915_gem_request *wait_req;
405 struct intel_initial_plane_config {
406 struct intel_framebuffer *fb;
412 #define SKL_MIN_SRC_W 8
413 #define SKL_MAX_SRC_W 4096
414 #define SKL_MIN_SRC_H 8
415 #define SKL_MAX_SRC_H 4096
416 #define SKL_MIN_DST_W 8
417 #define SKL_MAX_DST_W 4096
418 #define SKL_MIN_DST_H 8
419 #define SKL_MAX_DST_H 4096
421 struct intel_scaler {
426 struct intel_crtc_scaler_state {
427 #define SKL_NUM_SCALERS 2
428 struct intel_scaler scalers[SKL_NUM_SCALERS];
431 * scaler_users: keeps track of users requesting scalers on this crtc.
433 * If a bit is set, a user is using a scaler.
434 * Here user can be a plane or crtc as defined below:
435 * bits 0-30 - plane (bit position is index from drm_plane_index)
438 * Instead of creating a new index to cover planes and crtc, using
439 * existing drm_plane_index for planes which is well less than 31
440 * planes and bit 31 for crtc. This should be fine to cover all
443 * intel_atomic_setup_scalers will setup available scalers to users
444 * requesting scalers. It will gracefully fail if request exceeds
447 #define SKL_CRTC_INDEX 31
448 unsigned scaler_users;
450 /* scaler used by crtc for panel fitting purpose */
454 /* drm_mode->private_flags */
455 #define I915_MODE_FLAG_INHERITED 1
457 struct intel_pipe_wm {
458 struct intel_wm_level wm[5];
459 struct intel_wm_level raw_wm[5];
463 bool sprites_enabled;
468 struct skl_wm_level wm[8];
469 struct skl_wm_level trans_wm;
473 struct intel_crtc_wm_state {
477 * Intermediate watermarks; these can be
478 * programmed immediately since they satisfy
479 * both the current configuration we're
480 * switching away from and the new
481 * configuration we're switching to.
483 struct intel_pipe_wm intermediate;
486 * Optimal watermarks, programmed post-vblank
487 * when this state is committed.
489 struct intel_pipe_wm optimal;
493 /* gen9+ only needs 1-step wm programming */
494 struct skl_pipe_wm optimal;
496 /* cached plane data rate */
497 unsigned plane_data_rate[I915_MAX_PLANES];
498 unsigned plane_y_data_rate[I915_MAX_PLANES];
500 /* minimum block allocation */
501 uint16_t minimum_blocks[I915_MAX_PLANES];
502 uint16_t minimum_y_blocks[I915_MAX_PLANES];
507 * Platforms with two-step watermark programming will need to
508 * update watermark programming post-vblank to switch from the
509 * safe intermediate watermarks to the optimal final
512 bool need_postvbl_update;
515 struct intel_crtc_state {
516 struct drm_crtc_state base;
519 * quirks - bitfield with hw state readout quirks
521 * For various reasons the hw state readout code might not be able to
522 * completely faithfully read out the current state. These cases are
523 * tracked with quirk flags so that fastboot and state checker can act
526 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
527 unsigned long quirks;
529 unsigned fb_bits; /* framebuffers to flip */
530 bool update_pipe; /* can a fast modeset be performed? */
532 bool update_wm_pre, update_wm_post; /* watermarks are updated */
533 bool fb_changed; /* fb on any of the planes is changed */
535 /* Pipe source size (ie. panel fitter input size)
536 * All planes will be positioned inside this space,
537 * and get clipped at the edges. */
538 int pipe_src_w, pipe_src_h;
540 /* Whether to set up the PCH/FDI. Note that we never allow sharing
541 * between pch encoders and cpu encoders. */
542 bool has_pch_encoder;
544 /* Are we sending infoframes on the attached port */
547 /* CPU Transcoder for the pipe. Currently this can only differ from the
548 * pipe on Haswell and later (where we have a special eDP transcoder)
549 * and Broxton (where we have special DSI transcoders). */
550 enum transcoder cpu_transcoder;
553 * Use reduced/limited/broadcast rbg range, compressing from the full
554 * range fed into the crtcs.
556 bool limited_color_range;
558 /* Bitmask of encoder types (enum intel_output_type)
559 * driven by the pipe.
561 unsigned int output_types;
563 /* Whether we should send NULL infoframes. Required for audio. */
566 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
567 * has_dp_encoder is set. */
571 * Enable dithering, used when the selected pipe bpp doesn't match the
576 /* Controls for the clock computation, to override various stages. */
579 /* SDVO TV has a bunch of special case. To make multifunction encoders
580 * work correctly, we need to track this at runtime.*/
584 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
585 * required. This is set in the 2nd loop of calling encoder's
586 * ->compute_config if the first pick doesn't work out.
590 /* Settings for the intel dpll used on pretty much everything but
594 /* Selected dpll when shared or NULL. */
595 struct intel_shared_dpll *shared_dpll;
597 /* Actual register state of the dpll, for shared dpll cross-checking. */
598 struct intel_dpll_hw_state dpll_hw_state;
600 /* DSI PLL registers */
606 struct intel_link_m_n dp_m_n;
608 /* m2_n2 for eDP downclock */
609 struct intel_link_m_n dp_m2_n2;
613 * Frequence the dpll for the port should run at. Differs from the
614 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
615 * already multiplied by pixel_multiplier.
619 /* Used by SDVO (and if we ever fix it, HDMI). */
620 unsigned pixel_multiplier;
625 * Used by platforms having DP/HDMI PHY with programmable lane
626 * latency optimization.
628 uint8_t lane_lat_optim_mask;
630 /* Panel fitter controls for gen2-gen4 + VLV */
634 u32 lvds_border_bits;
637 /* Panel fitter placement and size for Ironlake+ */
645 /* FDI configuration, only valid if has_pch_encoder is set. */
647 struct intel_link_m_n fdi_m_n;
655 bool dp_encoder_is_mst;
658 struct intel_crtc_scaler_state scaler_state;
660 /* w/a for waiting 2 vblanks during crtc enable */
661 enum pipe hsw_workaround_pipe;
663 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
666 struct intel_crtc_wm_state wm;
668 /* Gamma mode programmed on the pipe */
672 struct vlv_wm_state {
673 struct vlv_pipe_wm wm[3];
674 struct vlv_sr_wm sr[3];
675 uint8_t num_active_planes;
682 struct drm_crtc base;
685 u8 lut_r[256], lut_g[256], lut_b[256];
687 * Whether the crtc and the connected output pipeline is active. Implies
688 * that crtc->enabled is set, i.e. the current mode configuration has
689 * some outputs connected to this crtc.
692 unsigned long enabled_power_domains;
694 struct intel_overlay *overlay;
695 struct intel_flip_work *flip_work;
697 atomic_t unpin_work_count;
699 /* Display surface base address adjustement for pageflips. Note that on
700 * gen4+ this only adjusts up to a tile, offsets within a tile are
701 * handled in the hw itself (with the TILEOFF register). */
706 uint32_t cursor_addr;
707 uint32_t cursor_cntl;
708 uint32_t cursor_size;
709 uint32_t cursor_base;
711 struct intel_crtc_state *config;
713 /* global reset count when the last flip was submitted */
714 unsigned int reset_count;
716 /* Access to these should be protected by dev_priv->irq_lock. */
717 bool cpu_fifo_underrun_disabled;
718 bool pch_fifo_underrun_disabled;
720 /* per-pipe watermark state */
722 /* watermarks currently being used */
724 struct intel_pipe_wm ilk;
725 struct skl_pipe_wm skl;
728 /* allow CxSR on this pipe */
735 unsigned start_vbl_count;
736 ktime_t start_vbl_time;
737 int min_vbl, max_vbl;
741 /* scalers available on this crtc */
744 struct vlv_wm_state wm_state;
747 struct intel_plane_wm_parameters {
748 uint32_t horiz_pixels;
749 uint32_t vert_pixels;
751 * For packed pixel formats:
752 * bytes_per_pixel - holds bytes per pixel
753 * For planar pixel formats:
754 * bytes_per_pixel - holds bytes per pixel for uv-plane
755 * y_bytes_per_pixel - holds bytes per pixel for y-plane
757 uint8_t bytes_per_pixel;
758 uint8_t y_bytes_per_pixel;
762 unsigned int rotation;
767 struct drm_plane base;
772 uint32_t frontbuffer_bit;
774 /* Since we need to change the watermarks before/after
775 * enabling/disabling the planes, we need to store the parameters here
776 * as the other pieces of the struct may not reflect the values we want
777 * for the watermark calculations. Currently only Haswell uses this.
779 struct intel_plane_wm_parameters wm;
782 * NOTE: Do not place new plane state fields here (e.g., when adding
783 * new plane properties). New runtime state should now be placed in
784 * the intel_plane_state structure and accessed via plane_state.
787 void (*update_plane)(struct drm_plane *plane,
788 const struct intel_crtc_state *crtc_state,
789 const struct intel_plane_state *plane_state);
790 void (*disable_plane)(struct drm_plane *plane,
791 struct drm_crtc *crtc);
792 int (*check_plane)(struct drm_plane *plane,
793 struct intel_crtc_state *crtc_state,
794 struct intel_plane_state *state);
797 struct intel_watermark_params {
798 unsigned long fifo_size;
799 unsigned long max_wm;
800 unsigned long default_wm;
801 unsigned long guard_size;
802 unsigned long cacheline_size;
805 struct cxsr_latency {
808 unsigned long fsb_freq;
809 unsigned long mem_freq;
810 unsigned long display_sr;
811 unsigned long display_hpll_disable;
812 unsigned long cursor_sr;
813 unsigned long cursor_hpll_disable;
816 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
817 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
818 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
819 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
820 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
821 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
822 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
823 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
824 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
830 enum drm_dp_dual_mode_type type;
833 bool limited_color_range;
834 bool color_range_auto;
837 enum hdmi_force_audio force_audio;
838 bool rgb_quant_range_selectable;
839 enum hdmi_picture_aspect aspect_ratio;
840 struct intel_connector *attached_connector;
841 void (*write_infoframe)(struct drm_encoder *encoder,
842 enum hdmi_infoframe_type type,
843 const void *frame, ssize_t len);
844 void (*set_infoframes)(struct drm_encoder *encoder,
846 const struct drm_display_mode *adjusted_mode);
847 bool (*infoframe_enabled)(struct drm_encoder *encoder,
848 const struct intel_crtc_state *pipe_config);
851 struct intel_dp_mst_encoder;
852 #define DP_MAX_DOWNSTREAM_PORTS 0x10
856 * When platform provides two set of M_N registers for dp, we can
857 * program them and switch between them incase of DRRS.
858 * But When only one such register is provided, we have to program the
859 * required divider value on that registers itself based on the DRRS state.
861 * M1_N1 : Program dp_m_n on M1_N1 registers
862 * dp_m2_n2 on M2_N2 registers (If supported)
864 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
865 * M2_N2 registers are not supported
869 /* Sets the m1_n1 and m2_n2 */
875 i915_reg_t output_reg;
876 i915_reg_t aux_ch_ctl_reg;
877 i915_reg_t aux_ch_data_reg[5];
885 bool channel_eq_status;
886 enum hdmi_force_audio force_audio;
887 bool limited_color_range;
888 bool color_range_auto;
889 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
890 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
891 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
892 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
893 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
894 uint8_t num_sink_rates;
895 int sink_rates[DP_MAX_SUPPORTED_RATES];
896 struct drm_dp_aux aux;
897 uint8_t train_set[4];
898 int panel_power_up_delay;
899 int panel_power_down_delay;
900 int panel_power_cycle_delay;
901 int backlight_on_delay;
902 int backlight_off_delay;
903 struct delayed_work panel_vdd_work;
905 unsigned long last_power_on;
906 unsigned long last_backlight_off;
907 ktime_t panel_power_off_time;
909 struct notifier_block edp_notifier;
912 * Pipe whose power sequencer is currently locked into
913 * this port. Only relevant on VLV/CHV.
917 * Set if the sequencer may be reset due to a power transition,
918 * requiring a reinitialization. Only relevant on BXT.
921 struct edp_power_seq pps_delays;
923 bool can_mst; /* this port supports mst */
925 int active_mst_links;
926 /* connector directly attached - won't be use for modeset in mst world */
927 struct intel_connector *attached_connector;
929 /* mst connector list */
930 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
931 struct drm_dp_mst_topology_mgr mst_mgr;
933 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
935 * This function returns the value we have to program the AUX_CTL
936 * register with to kick off an AUX transaction.
938 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
941 uint32_t aux_clock_divider);
943 /* This is called before a link training is starterd */
944 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
946 /* Displayport compliance testing */
947 unsigned long compliance_test_type;
948 unsigned long compliance_test_data;
949 bool compliance_test_active;
952 struct intel_digital_port {
953 struct intel_encoder base;
957 struct intel_hdmi hdmi;
958 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
959 bool release_cl2_override;
961 /* for communication with audio component; protected by av_mutex */
962 const struct drm_connector *audio_connector;
965 struct intel_dp_mst_encoder {
966 struct intel_encoder base;
968 struct intel_digital_port *primary;
969 struct intel_connector *connector;
972 static inline enum dpio_channel
973 vlv_dport_to_channel(struct intel_digital_port *dport)
975 switch (dport->port) {
986 static inline enum dpio_phy
987 vlv_dport_to_phy(struct intel_digital_port *dport)
989 switch (dport->port) {
1000 static inline enum dpio_channel
1001 vlv_pipe_to_channel(enum pipe pipe)
1014 static inline struct drm_crtc *
1015 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
1017 struct drm_i915_private *dev_priv = to_i915(dev);
1018 return dev_priv->pipe_to_crtc_mapping[pipe];
1021 static inline struct drm_crtc *
1022 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
1024 struct drm_i915_private *dev_priv = to_i915(dev);
1025 return dev_priv->plane_to_crtc_mapping[plane];
1028 struct intel_flip_work {
1029 struct work_struct unpin_work;
1030 struct work_struct mmio_work;
1032 struct drm_crtc *crtc;
1033 struct drm_framebuffer *old_fb;
1034 struct drm_i915_gem_object *pending_flip_obj;
1035 struct drm_pending_vblank_event *event;
1039 struct drm_i915_gem_request *flip_queued_req;
1040 u32 flip_queued_vblank;
1041 u32 flip_ready_vblank;
1042 unsigned int rotation;
1045 struct intel_load_detect_pipe {
1046 struct drm_atomic_state *restore_state;
1049 static inline struct intel_encoder *
1050 intel_attached_encoder(struct drm_connector *connector)
1052 return to_intel_connector(connector)->encoder;
1055 static inline struct intel_digital_port *
1056 enc_to_dig_port(struct drm_encoder *encoder)
1058 return container_of(encoder, struct intel_digital_port, base.base);
1061 static inline struct intel_dp_mst_encoder *
1062 enc_to_mst(struct drm_encoder *encoder)
1064 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1067 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1069 return &enc_to_dig_port(encoder)->dp;
1072 static inline struct intel_digital_port *
1073 dp_to_dig_port(struct intel_dp *intel_dp)
1075 return container_of(intel_dp, struct intel_digital_port, dp);
1078 static inline struct intel_digital_port *
1079 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1081 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1085 * Returns the number of planes for this pipe, ie the number of sprites + 1
1086 * (primary plane). This doesn't count the cursor plane then.
1088 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1090 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1093 /* intel_fifo_underrun.c */
1094 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool enable);
1096 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1097 enum transcoder pch_transcoder,
1099 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1101 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1102 enum transcoder pch_transcoder);
1103 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1104 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1107 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1108 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1109 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1110 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1111 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1112 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1113 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1114 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1115 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1116 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1117 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1120 * We only use drm_irq_uninstall() at unload and VT switch, so
1121 * this is the only thing we need to check.
1123 return dev_priv->pm.irqs_enabled;
1126 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1127 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1128 unsigned int pipe_mask);
1129 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1130 unsigned int pipe_mask);
1133 void intel_crt_init(struct drm_device *dev);
1134 void intel_crt_reset(struct drm_encoder *encoder);
1137 void intel_ddi_clk_select(struct intel_encoder *encoder,
1138 struct intel_shared_dpll *pll);
1139 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1140 struct intel_crtc_state *old_crtc_state,
1141 struct drm_connector_state *old_conn_state);
1142 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1143 void hsw_fdi_link_train(struct drm_crtc *crtc);
1144 void intel_ddi_init(struct drm_device *dev, enum port port);
1145 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1146 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1147 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1148 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1149 enum transcoder cpu_transcoder);
1150 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1151 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1152 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1153 struct intel_crtc_state *crtc_state);
1154 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1155 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1156 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1157 void intel_ddi_get_config(struct intel_encoder *encoder,
1158 struct intel_crtc_state *pipe_config);
1159 struct intel_encoder *
1160 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1162 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1163 void intel_ddi_clock_get(struct intel_encoder *encoder,
1164 struct intel_crtc_state *pipe_config);
1165 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1166 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1167 struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
1169 unsigned int intel_fb_align_height(struct drm_device *dev,
1170 unsigned int height,
1171 uint32_t pixel_format,
1172 uint64_t fb_format_modifier);
1173 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1174 uint64_t fb_modifier, uint32_t pixel_format);
1177 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1178 void intel_audio_codec_enable(struct intel_encoder *encoder);
1179 void intel_audio_codec_disable(struct intel_encoder *encoder);
1180 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1181 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1183 /* intel_display.c */
1184 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1185 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1186 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1187 const char *name, u32 reg, int ref_freq);
1188 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1189 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1190 extern const struct drm_plane_funcs intel_plane_funcs;
1191 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1192 unsigned int intel_fb_xy_to_linear(int x, int y,
1193 const struct intel_plane_state *state,
1195 void intel_add_fb_offsets(int *x, int *y,
1196 const struct intel_plane_state *state, int plane);
1197 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1198 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1199 void intel_mark_busy(struct drm_i915_private *dev_priv);
1200 void intel_mark_idle(struct drm_i915_private *dev_priv);
1201 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1202 int intel_display_suspend(struct drm_device *dev);
1203 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1204 void intel_encoder_destroy(struct drm_encoder *encoder);
1205 int intel_connector_init(struct intel_connector *);
1206 struct intel_connector *intel_connector_alloc(void);
1207 bool intel_connector_get_hw_state(struct intel_connector *connector);
1208 void intel_connector_attach_encoder(struct intel_connector *connector,
1209 struct intel_encoder *encoder);
1210 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1211 struct drm_crtc *crtc);
1212 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1213 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1214 struct drm_file *file_priv);
1215 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1218 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1219 enum intel_output_type type)
1221 return crtc_state->output_types & (1 << type);
1224 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1226 return crtc_state->output_types &
1227 ((1 << INTEL_OUTPUT_DP) |
1228 (1 << INTEL_OUTPUT_DP_MST) |
1229 (1 << INTEL_OUTPUT_EDP));
1232 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1234 drm_wait_one_vblank(dev, pipe);
1237 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1239 const struct intel_crtc *crtc =
1240 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1243 intel_wait_for_vblank(dev, pipe);
1246 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1248 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1249 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1250 struct intel_digital_port *dport,
1251 unsigned int expected_mask);
1252 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1253 struct drm_display_mode *mode,
1254 struct intel_load_detect_pipe *old,
1255 struct drm_modeset_acquire_ctx *ctx);
1256 void intel_release_load_detect_pipe(struct drm_connector *connector,
1257 struct intel_load_detect_pipe *old,
1258 struct drm_modeset_acquire_ctx *ctx);
1260 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1261 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1262 struct drm_framebuffer *
1263 __intel_framebuffer_create(struct drm_device *dev,
1264 struct drm_mode_fb_cmd2 *mode_cmd,
1265 struct drm_i915_gem_object *obj);
1266 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1267 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1268 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1269 int intel_prepare_plane_fb(struct drm_plane *plane,
1270 struct drm_plane_state *new_state);
1271 void intel_cleanup_plane_fb(struct drm_plane *plane,
1272 struct drm_plane_state *old_state);
1273 int intel_plane_atomic_get_property(struct drm_plane *plane,
1274 const struct drm_plane_state *state,
1275 struct drm_property *property,
1277 int intel_plane_atomic_set_property(struct drm_plane *plane,
1278 struct drm_plane_state *state,
1279 struct drm_property *property,
1281 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1282 struct drm_plane_state *plane_state);
1284 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1285 uint64_t fb_modifier, unsigned int cpp);
1287 void intel_create_rotation_property(struct drm_device *dev,
1288 struct intel_plane *plane);
1290 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1293 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1294 const struct dpll *dpll);
1295 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1296 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1298 /* modesetting asserts */
1299 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1301 void assert_pll(struct drm_i915_private *dev_priv,
1302 enum pipe pipe, bool state);
1303 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1304 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1305 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1306 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1307 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1308 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1309 enum pipe pipe, bool state);
1310 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1311 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1312 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1313 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1314 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1315 u32 intel_compute_tile_offset(int *x, int *y,
1316 const struct intel_plane_state *state, int plane);
1317 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1318 void intel_finish_reset(struct drm_i915_private *dev_priv);
1319 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1320 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1321 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1322 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1323 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1324 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1325 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1327 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1329 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1330 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1331 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1332 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1333 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1334 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1335 unsigned int skl_cdclk_get_vco(unsigned int freq);
1336 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1337 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1338 void intel_dp_get_m_n(struct intel_crtc *crtc,
1339 struct intel_crtc_state *pipe_config);
1340 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1341 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1342 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1343 struct dpll *best_clock);
1344 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1346 bool intel_crtc_active(struct drm_crtc *crtc);
1347 void hsw_enable_ips(struct intel_crtc *crtc);
1348 void hsw_disable_ips(struct intel_crtc *crtc);
1349 enum intel_display_power_domain
1350 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1351 enum intel_display_power_domain
1352 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1353 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1354 struct intel_crtc_state *pipe_config);
1356 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1357 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1359 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, unsigned int rotation);
1361 u32 skl_plane_ctl_format(uint32_t pixel_format);
1362 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1363 u32 skl_plane_ctl_rotation(unsigned int rotation);
1364 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1365 unsigned int rotation);
1366 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1369 void intel_csr_ucode_init(struct drm_i915_private *);
1370 void intel_csr_load_program(struct drm_i915_private *);
1371 void intel_csr_ucode_fini(struct drm_i915_private *);
1372 void intel_csr_ucode_suspend(struct drm_i915_private *);
1373 void intel_csr_ucode_resume(struct drm_i915_private *);
1376 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1377 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1378 struct intel_connector *intel_connector);
1379 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1380 int link_rate, uint8_t lane_count,
1382 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1383 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1384 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1385 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1386 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1387 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1388 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1389 bool intel_dp_compute_config(struct intel_encoder *encoder,
1390 struct intel_crtc_state *pipe_config,
1391 struct drm_connector_state *conn_state);
1392 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1393 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1395 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1396 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1397 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1398 void intel_edp_panel_on(struct intel_dp *intel_dp);
1399 void intel_edp_panel_off(struct intel_dp *intel_dp);
1400 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1401 void intel_dp_mst_suspend(struct drm_device *dev);
1402 void intel_dp_mst_resume(struct drm_device *dev);
1403 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1404 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1405 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1406 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1407 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1408 void intel_plane_destroy(struct drm_plane *plane);
1409 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1410 struct intel_crtc_state *crtc_state);
1411 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1412 struct intel_crtc_state *crtc_state);
1413 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1414 unsigned int frontbuffer_bits);
1415 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1416 unsigned int frontbuffer_bits);
1419 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1420 uint8_t dp_train_pat);
1422 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1423 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1425 intel_dp_voltage_max(struct intel_dp *intel_dp);
1427 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1428 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1429 uint8_t *link_bw, uint8_t *rate_select);
1430 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1432 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1434 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1436 return ~((1 << lane_count) - 1) & 0xf;
1439 /* intel_dp_aux_backlight.c */
1440 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1442 /* intel_dp_mst.c */
1443 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1444 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1446 void intel_dsi_init(struct drm_device *dev);
1448 /* intel_dsi_dcs_backlight.c */
1449 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1452 void intel_dvo_init(struct drm_device *dev);
1453 /* intel_hotplug.c */
1454 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1457 /* legacy fbdev emulation in intel_fbdev.c */
1458 #ifdef CONFIG_DRM_FBDEV_EMULATION
1459 extern int intel_fbdev_init(struct drm_device *dev);
1460 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1461 extern void intel_fbdev_fini(struct drm_device *dev);
1462 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1463 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1464 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1466 static inline int intel_fbdev_init(struct drm_device *dev)
1471 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1475 static inline void intel_fbdev_fini(struct drm_device *dev)
1479 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1483 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1489 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1490 struct drm_atomic_state *state);
1491 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1492 void intel_fbc_pre_update(struct intel_crtc *crtc,
1493 struct intel_crtc_state *crtc_state,
1494 struct intel_plane_state *plane_state);
1495 void intel_fbc_post_update(struct intel_crtc *crtc);
1496 void intel_fbc_init(struct drm_i915_private *dev_priv);
1497 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1498 void intel_fbc_enable(struct intel_crtc *crtc,
1499 struct intel_crtc_state *crtc_state,
1500 struct intel_plane_state *plane_state);
1501 void intel_fbc_disable(struct intel_crtc *crtc);
1502 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1503 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1504 unsigned int frontbuffer_bits,
1505 enum fb_op_origin origin);
1506 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1507 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1508 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1511 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1512 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1513 struct intel_connector *intel_connector);
1514 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1515 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1516 struct intel_crtc_state *pipe_config,
1517 struct drm_connector_state *conn_state);
1518 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1522 void intel_lvds_init(struct drm_device *dev);
1523 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1524 bool intel_is_dual_link_lvds(struct drm_device *dev);
1528 int intel_connector_update_modes(struct drm_connector *connector,
1530 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1531 void intel_attach_force_audio_property(struct drm_connector *connector);
1532 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1533 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1536 /* intel_overlay.c */
1537 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1538 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1539 int intel_overlay_switch_off(struct intel_overlay *overlay);
1540 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1541 struct drm_file *file_priv);
1542 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1543 struct drm_file *file_priv);
1544 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1548 int intel_panel_init(struct intel_panel *panel,
1549 struct drm_display_mode *fixed_mode,
1550 struct drm_display_mode *downclock_mode);
1551 void intel_panel_fini(struct intel_panel *panel);
1552 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1553 struct drm_display_mode *adjusted_mode);
1554 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1555 struct intel_crtc_state *pipe_config,
1557 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1558 struct intel_crtc_state *pipe_config,
1560 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1561 u32 level, u32 max);
1562 int intel_panel_setup_backlight(struct drm_connector *connector,
1564 void intel_panel_enable_backlight(struct intel_connector *connector);
1565 void intel_panel_disable_backlight(struct intel_connector *connector);
1566 void intel_panel_destroy_backlight(struct drm_connector *connector);
1567 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1568 extern struct drm_display_mode *intel_find_panel_downclock(
1569 struct drm_device *dev,
1570 struct drm_display_mode *fixed_mode,
1571 struct drm_connector *connector);
1573 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1574 int intel_backlight_device_register(struct intel_connector *connector);
1575 void intel_backlight_device_unregister(struct intel_connector *connector);
1576 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1577 static int intel_backlight_device_register(struct intel_connector *connector)
1581 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1584 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1588 void intel_psr_enable(struct intel_dp *intel_dp);
1589 void intel_psr_disable(struct intel_dp *intel_dp);
1590 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1591 unsigned frontbuffer_bits);
1592 void intel_psr_flush(struct drm_i915_private *dev_priv,
1593 unsigned frontbuffer_bits,
1594 enum fb_op_origin origin);
1595 void intel_psr_init(struct drm_device *dev);
1596 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1597 unsigned frontbuffer_bits);
1599 /* intel_runtime_pm.c */
1600 int intel_power_domains_init(struct drm_i915_private *);
1601 void intel_power_domains_fini(struct drm_i915_private *);
1602 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1603 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1604 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1605 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1606 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1608 intel_display_power_domain_str(enum intel_display_power_domain domain);
1610 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1611 enum intel_display_power_domain domain);
1612 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1613 enum intel_display_power_domain domain);
1614 void intel_display_power_get(struct drm_i915_private *dev_priv,
1615 enum intel_display_power_domain domain);
1616 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1617 enum intel_display_power_domain domain);
1618 void intel_display_power_put(struct drm_i915_private *dev_priv,
1619 enum intel_display_power_domain domain);
1622 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1624 WARN_ONCE(dev_priv->pm.suspended,
1625 "Device suspended during HW access\n");
1629 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1631 assert_rpm_device_not_suspended(dev_priv);
1632 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1633 * too much noise. */
1634 if (!atomic_read(&dev_priv->pm.wakeref_count))
1635 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1639 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1641 int seq = atomic_read(&dev_priv->pm.atomic_seq);
1643 assert_rpm_wakelock_held(dev_priv);
1649 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1651 WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1652 "HW access outside of RPM atomic section\n");
1656 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1657 * @dev_priv: i915 device instance
1659 * This function disable asserts that check if we hold an RPM wakelock
1660 * reference, while keeping the device-not-suspended checks still enabled.
1661 * It's meant to be used only in special circumstances where our rule about
1662 * the wakelock refcount wrt. the device power state doesn't hold. According
1663 * to this rule at any point where we access the HW or want to keep the HW in
1664 * an active state we must hold an RPM wakelock reference acquired via one of
1665 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1666 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1667 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1668 * users should avoid using this function.
1670 * Any calls to this function must have a symmetric call to
1671 * enable_rpm_wakeref_asserts().
1674 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1676 atomic_inc(&dev_priv->pm.wakeref_count);
1680 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1681 * @dev_priv: i915 device instance
1683 * This function re-enables the RPM assert checks after disabling them with
1684 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1685 * circumstances otherwise its use should be avoided.
1687 * Any calls to this function must have a symmetric call to
1688 * disable_rpm_wakeref_asserts().
1691 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1693 atomic_dec(&dev_priv->pm.wakeref_count);
1696 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1697 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1698 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1699 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1701 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1703 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1704 bool override, unsigned int mask);
1705 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1706 enum dpio_channel ch, bool override);
1710 void intel_init_clock_gating(struct drm_device *dev);
1711 void intel_suspend_hw(struct drm_device *dev);
1712 int ilk_wm_max_level(const struct drm_device *dev);
1713 void intel_update_watermarks(struct drm_crtc *crtc);
1714 void intel_init_pm(struct drm_device *dev);
1715 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1716 void intel_pm_setup(struct drm_device *dev);
1717 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1718 void intel_gpu_ips_teardown(void);
1719 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1720 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1721 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1722 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1723 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1724 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1725 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1726 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1727 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1728 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1729 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1730 struct intel_rps_client *rps,
1731 unsigned long submitted);
1732 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1733 void vlv_wm_get_hw_state(struct drm_device *dev);
1734 void ilk_wm_get_hw_state(struct drm_device *dev);
1735 void skl_wm_get_hw_state(struct drm_device *dev);
1736 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1737 struct skl_ddb_allocation *ddb /* out */);
1738 bool skl_can_enable_sagv(struct drm_atomic_state *state);
1739 int skl_enable_sagv(struct drm_i915_private *dev_priv);
1740 int skl_disable_sagv(struct drm_i915_private *dev_priv);
1741 bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
1742 const struct skl_ddb_allocation *new,
1744 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
1745 const struct skl_ddb_allocation *old,
1746 const struct skl_ddb_allocation *new,
1748 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
1749 const struct skl_wm_values *wm);
1750 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
1751 const struct skl_wm_values *wm,
1753 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1754 bool ilk_disable_lp_wm(struct drm_device *dev);
1755 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1756 static inline int intel_enable_rc6(void)
1758 return i915.enable_rc6;
1762 bool intel_sdvo_init(struct drm_device *dev,
1763 i915_reg_t reg, enum port port);
1766 /* intel_sprite.c */
1767 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1769 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1770 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1771 struct drm_file *file_priv);
1772 void intel_pipe_update_start(struct intel_crtc *crtc);
1773 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1776 void intel_tv_init(struct drm_device *dev);
1778 /* intel_atomic.c */
1779 int intel_connector_atomic_get_property(struct drm_connector *connector,
1780 const struct drm_connector_state *state,
1781 struct drm_property *property,
1783 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1784 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1785 struct drm_crtc_state *state);
1786 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1787 void intel_atomic_state_clear(struct drm_atomic_state *);
1788 struct intel_shared_dpll_config *
1789 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1791 static inline struct intel_crtc_state *
1792 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1793 struct intel_crtc *crtc)
1795 struct drm_crtc_state *crtc_state;
1796 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1797 if (IS_ERR(crtc_state))
1798 return ERR_CAST(crtc_state);
1800 return to_intel_crtc_state(crtc_state);
1803 static inline struct intel_plane_state *
1804 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1805 struct intel_plane *plane)
1807 struct drm_plane_state *plane_state;
1809 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1811 return to_intel_plane_state(plane_state);
1814 int intel_atomic_setup_scalers(struct drm_device *dev,
1815 struct intel_crtc *intel_crtc,
1816 struct intel_crtc_state *crtc_state);
1818 /* intel_atomic_plane.c */
1819 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1820 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1821 void intel_plane_destroy_state(struct drm_plane *plane,
1822 struct drm_plane_state *state);
1823 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1826 void intel_color_init(struct drm_crtc *crtc);
1827 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1828 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1829 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1831 #endif /* __INTEL_DRV_H__ */