drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <drm/drm_mipi_dsi.h>
  32 #include <linux/slab.h>
  33 #include <linux/gpio/consumer.h>
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36 #include "intel_dsi.h"
  37
  38 /* return pixels in terms of txbyteclkhs */
  39 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  40                        u16 burst_mode_ratio)
  41 {
  42         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  43                                          8 * 100), lane_count);
  44 }
  45
  46 /* return pixels equvalent to txbyteclkhs */
  47 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  48                         u16 burst_mode_ratio)
  49 {
  50         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  51                                                 (bpp * burst_mode_ratio));
  52 }
  53
  54 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  55 {
  56         /* It just so happens the VBT matches register contents. */
  57         switch (fmt) {
  58         case VID_MODE_FORMAT_RGB888:
  59                 return MIPI_DSI_FMT_RGB888;
  60         case VID_MODE_FORMAT_RGB666:
  61                 return MIPI_DSI_FMT_RGB666;
  62         case VID_MODE_FORMAT_RGB666_PACKED:
  63                 return MIPI_DSI_FMT_RGB666_PACKED;
  64         case VID_MODE_FORMAT_RGB565:
  65                 return MIPI_DSI_FMT_RGB565;
  66         default:
  67                 MISSING_CASE(fmt);
  68                 return MIPI_DSI_FMT_RGB666;
  69         }
  70 }
  71
  72 void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  73 {
  74         struct drm_encoder *encoder = &intel_dsi->base.base;
  75         struct drm_device *dev = encoder->dev;
  76         struct drm_i915_private *dev_priv = to_i915(dev);
  77         u32 mask;
  78
  79         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  80                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  81
  82         if (intel_wait_for_register(dev_priv,
  83                                     MIPI_GEN_FIFO_STAT(port), mask, mask,
  84                                     100))
  85                 DRM_ERROR("DPI FIFOs are not empty\n");
  86 }
  87
  88 static void write_data(struct drm_i915_private *dev_priv,
  89                        i915_reg_t reg,
  90                        const u8 *data, u32 len)
  91 {
  92         u32 i, j;
  93
  94         for (i = 0; i < len; i += 4) {
  95                 u32 val = 0;
  96
  97                 for (j = 0; j < min_t(u32, len - i, 4); j++)
  98                         val |= *data++ << 8 * j;
  99
 100                 I915_WRITE(reg, val);
 101         }
 102 }
 103
 104 static void read_data(struct drm_i915_private *dev_priv,
 105                       i915_reg_t reg,
 106                       u8 *data, u32 len)
 107 {
 108         u32 i, j;
 109
 110         for (i = 0; i < len; i += 4) {
 111                 u32 val = I915_READ(reg);
 112
 113                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 114                         *data++ = val >> 8 * j;
 115         }
 116 }
 117
 118 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 119                                        const struct mipi_dsi_msg *msg)
 120 {
 121         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 122         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 123         struct drm_i915_private *dev_priv = to_i915(dev);
 124         enum port port = intel_dsi_host->port;
 125         struct mipi_dsi_packet packet;
 126         ssize_t ret;
 127         const u8 *header, *data;
 128         i915_reg_t data_reg, ctrl_reg;
 129         u32 data_mask, ctrl_mask;
 130
 131         ret = mipi_dsi_create_packet(&packet, msg);
 132         if (ret < 0)
 133                 return ret;
 134
 135         header = packet.header;
 136         data = packet.payload;
 137
 138         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 139                 data_reg = MIPI_LP_GEN_DATA(port);
 140                 data_mask = LP_DATA_FIFO_FULL;
 141                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 142                 ctrl_mask = LP_CTRL_FIFO_FULL;
 143         } else {
 144                 data_reg = MIPI_HS_GEN_DATA(port);
 145                 data_mask = HS_DATA_FIFO_FULL;
 146                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 147                 ctrl_mask = HS_CTRL_FIFO_FULL;
 148         }
 149
 150         /* note: this is never true for reads */
 151         if (packet.payload_length) {
 152                 if (intel_wait_for_register(dev_priv,
 153                                             MIPI_GEN_FIFO_STAT(port),
 154                                             data_mask, 0,
 155                                             50))
 156                         DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 157
 158                 write_data(dev_priv, data_reg, packet.payload,
 159                            packet.payload_length);
 160         }
 161
 162         if (msg->rx_len) {
 163                 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 164         }
 165
 166         if (intel_wait_for_register(dev_priv,
 167                                     MIPI_GEN_FIFO_STAT(port),
 168                                     ctrl_mask, 0,
 169                                     50)) {
 170                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 171         }
 172
 173         I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
 174
 175         /* ->rx_len is set only for reads */
 176         if (msg->rx_len) {
 177                 data_mask = GEN_READ_DATA_AVAIL;
 178                 if (intel_wait_for_register(dev_priv,
 179                                             MIPI_INTR_STAT(port),
 180                                             data_mask, data_mask,
 181                                             50))
 182                         DRM_ERROR("Timeout waiting for read data.\n");
 183
 184                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 185         }
 186
 187         /* XXX: fix for reads and writes */
 188         return 4 + packet.payload_length;
 189 }
 190
 191 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 192                                  struct mipi_dsi_device *dsi)
 193 {
 194         return 0;
 195 }
 196
 197 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 198                                  struct mipi_dsi_device *dsi)
 199 {
 200         return 0;
 201 }
 202
 203 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 204         .attach = intel_dsi_host_attach,
 205         .detach = intel_dsi_host_detach,
 206         .transfer = intel_dsi_host_transfer,
 207 };
 208
 209 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
 210                                                   enum port port)
 211 {
 212         struct intel_dsi_host *host;
 213         struct mipi_dsi_device *device;
 214
 215         host = kzalloc(sizeof(*host), GFP_KERNEL);
 216         if (!host)
 217                 return NULL;
 218
 219         host->base.ops = &intel_dsi_host_ops;
 220         host->intel_dsi = intel_dsi;
 221         host->port = port;
 222
 223         /*
 224          * We should call mipi_dsi_host_register(&host->base) here, but we don't
 225          * have a host->dev, and we don't have OF stuff either. So just use the
 226          * dsi framework as a library and hope for the best. Create the dsi
 227          * devices by ourselves here too. Need to be careful though, because we
 228          * don't initialize any of the driver model devices here.
 229          */
 230         device = kzalloc(sizeof(*device), GFP_KERNEL);
 231         if (!device) {
 232                 kfree(host);
 233                 return NULL;
 234         }
 235
 236         device->host = &host->base;
 237         host->device = device;
 238
 239         return host;
 240 }
 241
 242 /*
 243  * send a video mode command
 244  *
 245  * XXX: commands with data in MIPI_DPI_DATA?
 246  */
 247 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 248                         enum port port)
 249 {
 250         struct drm_encoder *encoder = &intel_dsi->base.base;
 251         struct drm_device *dev = encoder->dev;
 252         struct drm_i915_private *dev_priv = to_i915(dev);
 253         u32 mask;
 254
 255         /* XXX: pipe, hs */
 256         if (hs)
 257                 cmd &= ~DPI_LP_MODE;
 258         else
 259                 cmd |= DPI_LP_MODE;
 260
 261         /* clear bit */
 262         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 263
 264         /* XXX: old code skips write if control unchanged */
 265         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 266                 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
 267
 268         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 269
 270         mask = SPL_PKT_SENT_INTERRUPT;
 271         if (intel_wait_for_register(dev_priv,
 272                                     MIPI_INTR_STAT(port), mask, mask,
 273                                     100))
 274                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 275
 276         return 0;
 277 }
 278
 279 static void band_gap_reset(struct drm_i915_private *dev_priv)
 280 {
 281         mutex_lock(&dev_priv->sb_lock);
 282
 283         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 284         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 285         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 286         udelay(150);
 287         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 288         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 289
 290         mutex_unlock(&dev_priv->sb_lock);
 291 }
 292
 293 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
 294 {
 295         return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
 296 }
 297
 298 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
 299 {
 300         return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
 301 }
 302
 303 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 304                                      struct intel_crtc_state *pipe_config,
 305                                      struct drm_connector_state *conn_state)
 306 {
 307         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 308         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 309                                                    base);
 310         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 311         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 312         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 313         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 314         int ret;
 315
 316         DRM_DEBUG_KMS("\n");
 317
 318         if (fixed_mode) {
 319                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 320
 321                 if (HAS_GMCH_DISPLAY(dev_priv))
 322                         intel_gmch_panel_fitting(crtc, pipe_config,
 323                                                  intel_connector->panel.fitting_mode);
 324                 else
 325                         intel_pch_panel_fitting(crtc, pipe_config,
 326                                                 intel_connector->panel.fitting_mode);
 327         }
 328
 329         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 330         adjusted_mode->flags = 0;
 331
 332         if (IS_GEN9_LP(dev_priv)) {
 333                 /* Dual link goes to DSI transcoder A. */
 334                 if (intel_dsi->ports == BIT(PORT_C))
 335                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 336                 else
 337                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 338         }
 339
 340         ret = intel_compute_dsi_pll(encoder, pipe_config);
 341         if (ret)
 342                 return false;
 343
 344         pipe_config->clock_set = true;
 345
 346         return true;
 347 }
 348
 349 static void glk_dsi_device_ready(struct intel_encoder *encoder)
 350 {
 351         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 352         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 353         enum port port;
 354         u32 tmp, val;
 355
 356         /* Set the MIPI mode
 357          * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
 358          * Power ON MIPI IO first and then write into IO reset and LP wake bits
 359          */
 360         for_each_dsi_port(port, intel_dsi->ports) {
 361                 tmp = I915_READ(MIPI_CTRL(port));
 362                 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
 363         }
 364
 365         /* Put the IO into reset */
 366         tmp = I915_READ(MIPI_CTRL(PORT_A));
 367         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 368         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 369
 370         /* Program LP Wake */
 371         for_each_dsi_port(port, intel_dsi->ports) {
 372                 tmp = I915_READ(MIPI_CTRL(port));
 373                 tmp |= GLK_LP_WAKE;
 374                 I915_WRITE(MIPI_CTRL(port), tmp);
 375         }
 376
 377         /* Wait for Pwr ACK */
 378         for_each_dsi_port(port, intel_dsi->ports) {
 379                 if (intel_wait_for_register(dev_priv,
 380                                 MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
 381                                 GLK_MIPIIO_PORT_POWERED, 20))
 382                         DRM_ERROR("MIPIO port is powergated\n");
 383         }
 384
 385         /* Wait for MIPI PHY status bit to set */
 386         for_each_dsi_port(port, intel_dsi->ports) {
 387                 if (intel_wait_for_register(dev_priv,
 388                                 MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
 389                                 GLK_PHY_STATUS_PORT_READY, 20))
 390                         DRM_ERROR("PHY is not ON\n");
 391         }
 392
 393         /* Get IO out of reset */
 394         tmp = I915_READ(MIPI_CTRL(PORT_A));
 395         I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED);
 396
 397         /* Get IO out of Low power state*/
 398         for_each_dsi_port(port, intel_dsi->ports) {
 399                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
 400                         val = I915_READ(MIPI_DEVICE_READY(port));
 401                         val &= ~ULPS_STATE_MASK;
 402                         val |= DEVICE_READY;
 403                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 404                         usleep_range(10, 15);
 405                 }
 406
 407                 /* Enter ULPS */
 408                 val = I915_READ(MIPI_DEVICE_READY(port));
 409                 val &= ~ULPS_STATE_MASK;
 410                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 411                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 412
 413                 /* Wait for ULPS Not active */
 414                 if (intel_wait_for_register(dev_priv,
 415                                 MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
 416                                 GLK_ULPS_NOT_ACTIVE, 20))
 417                         DRM_ERROR("ULPS is still active\n");
 418
 419                 /* Exit ULPS */
 420                 val = I915_READ(MIPI_DEVICE_READY(port));
 421                 val &= ~ULPS_STATE_MASK;
 422                 val |= (ULPS_STATE_EXIT | DEVICE_READY);
 423                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 424
 425                 /* Enter Normal Mode */
 426                 val = I915_READ(MIPI_DEVICE_READY(port));
 427                 val &= ~ULPS_STATE_MASK;
 428                 val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
 429                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 430
 431                 tmp = I915_READ(MIPI_CTRL(port));
 432                 tmp &= ~GLK_LP_WAKE;
 433                 I915_WRITE(MIPI_CTRL(port), tmp);
 434         }
 435
 436         /* Wait for Stop state */
 437         for_each_dsi_port(port, intel_dsi->ports) {
 438                 if (intel_wait_for_register(dev_priv,
 439                                 MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
 440                                 GLK_DATA_LANE_STOP_STATE, 20))
 441                         DRM_ERROR("Date lane not in STOP state\n");
 442         }
 443
 444         /* Wait for AFE LATCH */
 445         for_each_dsi_port(port, intel_dsi->ports) {
 446                 if (intel_wait_for_register(dev_priv,
 447                                 BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
 448                                 AFE_LATCHOUT, 20))
 449                         DRM_ERROR("D-PHY not entering LP-11 state\n");
 450         }
 451 }
 452
 453 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 454 {
 455         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 456         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 457         enum port port;
 458         u32 val;
 459
 460         DRM_DEBUG_KMS("\n");
 461
 462         /* Enable MIPI PHY transparent latch */
 463         for_each_dsi_port(port, intel_dsi->ports) {
 464                 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
 465                 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
 466                 usleep_range(2000, 2500);
 467         }
 468
 469         /* Clear ULPS and set device ready */
 470         for_each_dsi_port(port, intel_dsi->ports) {
 471                 val = I915_READ(MIPI_DEVICE_READY(port));
 472                 val &= ~ULPS_STATE_MASK;
 473                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 474                 usleep_range(2000, 2500);
 475                 val |= DEVICE_READY;
 476                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 477         }
 478 }
 479
 480 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 481 {
 482         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 483         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 484         enum port port;
 485         u32 val;
 486
 487         DRM_DEBUG_KMS("\n");
 488
 489         mutex_lock(&dev_priv->sb_lock);
 490         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 491          * needed everytime after power gate */
 492         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 493         mutex_unlock(&dev_priv->sb_lock);
 494
 495         /* bandgap reset is needed after everytime we do power gate */
 496         band_gap_reset(dev_priv);
 497
 498         for_each_dsi_port(port, intel_dsi->ports) {
 499
 500                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 501                 usleep_range(2500, 3000);
 502
 503                 /* Enable MIPI PHY transparent latch
 504                  * Common bit for both MIPI Port A & MIPI Port C
 505                  * No similar bit in MIPI Port C reg
 506                  */
 507                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 508                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 509                 usleep_range(1000, 1500);
 510
 511                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 512                 usleep_range(2500, 3000);
 513
 514                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 515                 usleep_range(2500, 3000);
 516         }
 517 }
 518
 519 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 520 {
 521         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 522
 523         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 524                 vlv_dsi_device_ready(encoder);
 525         else if (IS_BROXTON(dev_priv))
 526                 bxt_dsi_device_ready(encoder);
 527         else if (IS_GEMINILAKE(dev_priv))
 528                 glk_dsi_device_ready(encoder);
 529 }
 530
 531 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 532 {
 533         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 534         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 535         enum port port;
 536         u32 val;
 537
 538         /* Enter ULPS */
 539         for_each_dsi_port(port, intel_dsi->ports) {
 540                 val = I915_READ(MIPI_DEVICE_READY(port));
 541                 val &= ~ULPS_STATE_MASK;
 542                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 543                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 544         }
 545
 546         /* Wait for MIPI PHY status bit to unset */
 547         for_each_dsi_port(port, intel_dsi->ports) {
 548                 if (intel_wait_for_register(dev_priv,
 549                                             MIPI_CTRL(port),
 550                                             GLK_PHY_STATUS_PORT_READY, 0, 20))
 551                         DRM_ERROR("PHY is not turning OFF\n");
 552         }
 553
 554         /* Wait for Pwr ACK bit to unset */
 555         for_each_dsi_port(port, intel_dsi->ports) {
 556                 if (intel_wait_for_register(dev_priv,
 557                                             MIPI_CTRL(port),
 558                                             GLK_MIPIIO_PORT_POWERED, 0, 20))
 559                         DRM_ERROR("MIPI IO Port is not powergated\n");
 560         }
 561 }
 562
 563 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
 564 {
 565         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 566         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 567         enum port port;
 568         u32 tmp;
 569
 570         /* Put the IO into reset */
 571         tmp = I915_READ(MIPI_CTRL(PORT_A));
 572         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 573         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 574
 575         /* Wait for MIPI PHY status bit to unset */
 576         for_each_dsi_port(port, intel_dsi->ports) {
 577                 if (intel_wait_for_register(dev_priv,
 578                                             MIPI_CTRL(port),
 579                                             GLK_PHY_STATUS_PORT_READY, 0, 20))
 580                         DRM_ERROR("PHY is not turning OFF\n");
 581         }
 582
 583         /* Clear MIPI mode */
 584         for_each_dsi_port(port, intel_dsi->ports) {
 585                 tmp = I915_READ(MIPI_CTRL(port));
 586                 tmp &= ~GLK_MIPIIO_ENABLE;
 587                 I915_WRITE(MIPI_CTRL(port), tmp);
 588         }
 589 }
 590
 591 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
 592 {
 593         glk_dsi_enter_low_power_mode(encoder);
 594         glk_dsi_disable_mipi_io(encoder);
 595 }
 596
 597 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 598 {
 599         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 600         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 601         enum port port;
 602
 603         DRM_DEBUG_KMS("\n");
 604         for_each_dsi_port(port, intel_dsi->ports) {
 605                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 606                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 607                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 608                 u32 val;
 609
 610                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 611                                                         ULPS_STATE_ENTER);
 612                 usleep_range(2000, 2500);
 613
 614                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 615                                                         ULPS_STATE_EXIT);
 616                 usleep_range(2000, 2500);
 617
 618                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 619                                                         ULPS_STATE_ENTER);
 620                 usleep_range(2000, 2500);
 621
 622                 /*
 623                  * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
 624                  * Port A only. MIPI Port C has no similar bit for checking.
 625                  */
 626                 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
 627                     intel_wait_for_register(dev_priv,
 628                                             port_ctrl, AFE_LATCHOUT, 0,
 629                                             30))
 630                         DRM_ERROR("DSI LP not going Low\n");
 631
 632                 /* Disable MIPI PHY transparent latch */
 633                 val = I915_READ(port_ctrl);
 634                 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
 635                 usleep_range(1000, 1500);
 636
 637                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 638                 usleep_range(2000, 2500);
 639         }
 640 }
 641
 642 static void intel_dsi_port_enable(struct intel_encoder *encoder)
 643 {
 644         struct drm_device *dev = encoder->base.dev;
 645         struct drm_i915_private *dev_priv = to_i915(dev);
 646         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 647         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 648         enum port port;
 649
 650         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 651                 u32 temp;
 652                 if (IS_GEN9_LP(dev_priv)) {
 653                         for_each_dsi_port(port, intel_dsi->ports) {
 654                                 temp = I915_READ(MIPI_CTRL(port));
 655                                 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
 656                                         intel_dsi->pixel_overlap <<
 657                                         BXT_PIXEL_OVERLAP_CNT_SHIFT;
 658                                 I915_WRITE(MIPI_CTRL(port), temp);
 659                         }
 660                 } else {
 661                         temp = I915_READ(VLV_CHICKEN_3);
 662                         temp &= ~PIXEL_OVERLAP_CNT_MASK |
 663                                         intel_dsi->pixel_overlap <<
 664                                         PIXEL_OVERLAP_CNT_SHIFT;
 665                         I915_WRITE(VLV_CHICKEN_3, temp);
 666                 }
 667         }
 668
 669         for_each_dsi_port(port, intel_dsi->ports) {
 670                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 671                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 672                 u32 temp;
 673
 674                 temp = I915_READ(port_ctrl);
 675
 676                 temp &= ~LANE_CONFIGURATION_MASK;
 677                 temp &= ~DUAL_LINK_MODE_MASK;
 678
 679                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 680                         temp |= (intel_dsi->dual_link - 1)
 681                                                 << DUAL_LINK_MODE_SHIFT;
 682                         if (IS_BROXTON(dev_priv))
 683                                 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
 684                         else
 685                                 temp |= intel_crtc->pipe ?
 686                                         LANE_CONFIGURATION_DUAL_LINK_B :
 687                                         LANE_CONFIGURATION_DUAL_LINK_A;
 688                 }
 689                 /* assert ip_tg_enable signal */
 690                 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
 691                 POSTING_READ(port_ctrl);
 692         }
 693 }
 694
 695 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 696 {
 697         struct drm_device *dev = encoder->base.dev;
 698         struct drm_i915_private *dev_priv = to_i915(dev);
 699         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 700         enum port port;
 701
 702         for_each_dsi_port(port, intel_dsi->ports) {
 703                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 704                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 705                 u32 temp;
 706
 707                 /* de-assert ip_tg_enable signal */
 708                 temp = I915_READ(port_ctrl);
 709                 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
 710                 POSTING_READ(port_ctrl);
 711         }
 712 }
 713
 714 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 715                               struct intel_crtc_state *pipe_config);
 716 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 717
 718 static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
 719 {
 720         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 721
 722         /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
 723         if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
 724                 return;
 725
 726         msleep(msec);
 727 }
 728
 729 /*
 730  * Panel enable/disable sequences from the VBT spec.
 731  *
 732  * Note the spec has AssertReset / DeassertReset swapped from their
 733  * usual naming. We use the normal names to avoid confusion (so below
 734  * they are swapped compared to the spec).
 735  *
 736  * Steps starting with MIPI refer to VBT sequences, note that for v2
 737  * VBTs several steps which have a VBT in v2 are expected to be handled
 738  * directly by the driver, by directly driving gpios for example.
 739  *
 740  * v2 video mode seq         v3 video mode seq         command mode seq
 741  * - power on                - MIPIPanelPowerOn        - power on
 742  * - wait t1+t2                                        - wait t1+t2
 743  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
 744  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
 745  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
 746  *                                                     - MIPITearOn
 747  *                                                     - MIPIDisplayOn
 748  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
 749  * - MIPIDisplayOn           - MIPIDisplayOn
 750  * - wait t5                                           - wait t5
 751  * - backlight on            - MIPIBacklightOn         - backlight on
 752  * ...                       ...                       ... issue mem cmds ...
 753  * - backlight off           - MIPIBacklightOff        - backlight off
 754  * - wait t6                                           - wait t6
 755  * - MIPIDisplayOff
 756  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
 757  *                                                     - MIPITearOff
 758  *                           - MIPIDisplayOff          - MIPIDisplayOff
 759  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
 760  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
 761  * - wait t3                                           - wait t3
 762  * - power off               - MIPIPanelPowerOff       - power off
 763  * - wait t4                                           - wait t4
 764  */
 765
 766 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 767                                  struct intel_crtc_state *pipe_config,
 768                                  struct drm_connector_state *conn_state)
 769 {
 770         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 771         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 772         enum port port;
 773         u32 val;
 774
 775         DRM_DEBUG_KMS("\n");
 776
 777         /*
 778          * The BIOS may leave the PLL in a wonky state where it doesn't
 779          * lock. It needs to be fully powered down to fix it.
 780          */
 781         intel_disable_dsi_pll(encoder);
 782         intel_enable_dsi_pll(encoder, pipe_config);
 783
 784         if (IS_BROXTON(dev_priv)) {
 785                 /* Add MIPI IO reset programming for modeset */
 786                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 787                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 788                                         val | MIPIO_RST_CTRL);
 789
 790                 /* Power up DSI regulator */
 791                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 792                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0);
 793         }
 794
 795         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 796                 u32 val;
 797
 798                 /* Disable DPOunit clock gating, can stall pipe */
 799                 val = I915_READ(DSPCLK_GATE_D);
 800                 val |= DPOUNIT_CLOCK_GATE_DISABLE;
 801                 I915_WRITE(DSPCLK_GATE_D, val);
 802         }
 803
 804         intel_dsi_prepare(encoder, pipe_config);
 805
 806         /* Power on, try both CRC pmic gpio and VBT */
 807         if (intel_dsi->gpio_panel)
 808                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
 809         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 810         intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 811
 812         /* Deassert reset */
 813         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 814
 815         /* Put device in ready state (LP-11) */
 816         intel_dsi_device_ready(encoder);
 817
 818         /* Send initialization commands in LP mode */
 819         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 820
 821         /* Enable port in pre-enable phase itself because as per hw team
 822          * recommendation, port should be enabled befor plane & pipe */
 823         if (is_cmd_mode(intel_dsi)) {
 824                 for_each_dsi_port(port, intel_dsi->ports)
 825                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 826                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
 827                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 828         } else {
 829                 msleep(20); /* XXX */
 830                 for_each_dsi_port(port, intel_dsi->ports)
 831                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 832                 intel_dsi_msleep(intel_dsi, 100);
 833
 834                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 835
 836                 intel_dsi_port_enable(encoder);
 837         }
 838
 839         intel_panel_enable_backlight(intel_dsi->attached_connector);
 840         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 841 }
 842
 843 static void intel_dsi_enable_nop(struct intel_encoder *encoder,
 844                                  struct intel_crtc_state *pipe_config,
 845                                  struct drm_connector_state *conn_state)
 846 {
 847         DRM_DEBUG_KMS("\n");
 848
 849         /* for DSI port enable has to be done before pipe
 850          * and plane enable, so port enable is done in
 851          * pre_enable phase itself unlike other encoders
 852          */
 853 }
 854
 855 static void intel_dsi_pre_disable(struct intel_encoder *encoder,
 856                                   struct intel_crtc_state *old_crtc_state,
 857                                   struct drm_connector_state *old_conn_state)
 858 {
 859         struct drm_device *dev = encoder->base.dev;
 860         struct drm_i915_private *dev_priv = dev->dev_private;
 861         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 862         enum port port;
 863
 864         DRM_DEBUG_KMS("\n");
 865
 866         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
 867         intel_panel_disable_backlight(intel_dsi->attached_connector);
 868
 869         /*
 870          * Disable Device ready before the port shutdown in order
 871          * to avoid split screen
 872          */
 873         if (IS_BROXTON(dev_priv)) {
 874                 for_each_dsi_port(port, intel_dsi->ports)
 875                         I915_WRITE(MIPI_DEVICE_READY(port), 0);
 876         }
 877
 878         /*
 879          * According to the spec we should send SHUTDOWN before
 880          * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
 881          * has shown that the v3 sequence works for v2 VBTs too
 882          */
 883         if (is_vid_mode(intel_dsi)) {
 884                 /* Send Shutdown command to the panel in LP mode */
 885                 for_each_dsi_port(port, intel_dsi->ports)
 886                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 887                 msleep(10);
 888         }
 889 }
 890
 891 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 892 {
 893         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 894
 895         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
 896             IS_BROXTON(dev_priv))
 897                 vlv_dsi_clear_device_ready(encoder);
 898         else if (IS_GEMINILAKE(dev_priv))
 899                 glk_dsi_clear_device_ready(encoder);
 900 }
 901
 902 static void intel_dsi_post_disable(struct intel_encoder *encoder,
 903                                    struct intel_crtc_state *pipe_config,
 904                                    struct drm_connector_state *conn_state)
 905 {
 906         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 907         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 908         enum port port;
 909         u32 val;
 910
 911         DRM_DEBUG_KMS("\n");
 912
 913         if (is_vid_mode(intel_dsi)) {
 914                 for_each_dsi_port(port, intel_dsi->ports)
 915                         wait_for_dsi_fifo_empty(intel_dsi, port);
 916
 917                 intel_dsi_port_disable(encoder);
 918                 usleep_range(2000, 5000);
 919         }
 920
 921         intel_dsi_unprepare(encoder);
 922
 923         /*
 924          * if disable packets are sent before sending shutdown packet then in
 925          * some next enable sequence send turn on packet error is observed
 926          */
 927         if (is_cmd_mode(intel_dsi))
 928                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
 929         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 930
 931         /* Transition to LP-00 */
 932         intel_dsi_clear_device_ready(encoder);
 933
 934         if (IS_BROXTON(dev_priv)) {
 935                 /* Power down DSI regulator to save power */
 936                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 937                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT);
 938
 939                 /* Add MIPI IO reset programming for modeset */
 940                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 941                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 942                                 val & ~MIPIO_RST_CTRL);
 943         }
 944
 945         intel_disable_dsi_pll(encoder);
 946
 947         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 948                 u32 val;
 949
 950                 val = I915_READ(DSPCLK_GATE_D);
 951                 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 952                 I915_WRITE(DSPCLK_GATE_D, val);
 953         }
 954
 955         /* Assert reset */
 956         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
 957
 958         /* Power off, try both CRC pmic gpio and VBT */
 959         intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
 960         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
 961         if (intel_dsi->gpio_panel)
 962                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
 963
 964         /*
 965          * FIXME As we do with eDP, just make a note of the time here
 966          * and perform the wait before the next panel power on.
 967          */
 968         intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
 969 }
 970
 971 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 972                                    enum pipe *pipe)
 973 {
 974         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 975         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 976         enum port port;
 977         bool active = false;
 978
 979         DRM_DEBUG_KMS("\n");
 980
 981         if (!intel_display_power_get_if_enabled(dev_priv,
 982                                                 encoder->power_domain))
 983                 return false;
 984
 985         /*
 986          * On Broxton the PLL needs to be enabled with a valid divider
 987          * configuration, otherwise accessing DSI registers will hang the
 988          * machine. See BSpec North Display Engine registers/MIPI[BXT].
 989          */
 990         if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
 991                 goto out_put_power;
 992
 993         /* XXX: this only works for one DSI output */
 994         for_each_dsi_port(port, intel_dsi->ports) {
 995                 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
 996                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 997                 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
 998
 999                 /*
1000                  * Due to some hardware limitations on VLV/CHV, the DPI enable
1001                  * bit in port C control register does not get set. As a
1002                  * workaround, check pipe B conf instead.
1003                  */
1004                 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1005                     port == PORT_C)
1006                         enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1007
1008                 /* Try command mode if video mode not enabled */
1009                 if (!enabled) {
1010                         u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
1011                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
1012                 }
1013
1014                 if (!enabled)
1015                         continue;
1016
1017                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
1018                         continue;
1019
1020                 if (IS_GEN9_LP(dev_priv)) {
1021                         u32 tmp = I915_READ(MIPI_CTRL(port));
1022                         tmp &= BXT_PIPE_SELECT_MASK;
1023                         tmp >>= BXT_PIPE_SELECT_SHIFT;
1024
1025                         if (WARN_ON(tmp > PIPE_C))
1026                                 continue;
1027
1028                         *pipe = tmp;
1029                 } else {
1030                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1031                 }
1032
1033                 active = true;
1034                 break;
1035         }
1036
1037 out_put_power:
1038         intel_display_power_put(dev_priv, encoder->power_domain);
1039
1040         return active;
1041 }
1042
1043 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1044                                  struct intel_crtc_state *pipe_config)
1045 {
1046         struct drm_device *dev = encoder->base.dev;
1047         struct drm_i915_private *dev_priv = to_i915(dev);
1048         struct drm_display_mode *adjusted_mode =
1049                                         &pipe_config->base.adjusted_mode;
1050         struct drm_display_mode *adjusted_mode_sw;
1051         struct intel_crtc *intel_crtc;
1052         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1053         unsigned int lane_count = intel_dsi->lane_count;
1054         unsigned int bpp, fmt;
1055         enum port port;
1056         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1057         u16 hfp_sw, hsync_sw, hbp_sw;
1058         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1059                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
1060
1061         /* FIXME: hw readout should not depend on SW state */
1062         intel_crtc = to_intel_crtc(encoder->base.crtc);
1063         adjusted_mode_sw = &intel_crtc->config->base.adjusted_mode;
1064
1065         /*
1066          * Atleast one port is active as encoder->get_config called only if
1067          * encoder->get_hw_state() returns true.
1068          */
1069         for_each_dsi_port(port, intel_dsi->ports) {
1070                 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1071                         break;
1072         }
1073
1074         fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1075         pipe_config->pipe_bpp =
1076                         mipi_dsi_pixel_format_to_bpp(
1077                                 pixel_format_from_register_bits(fmt));
1078         bpp = pipe_config->pipe_bpp;
1079
1080         /* In terms of pixels */
1081         adjusted_mode->crtc_hdisplay =
1082                                 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
1083         adjusted_mode->crtc_vdisplay =
1084                                 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
1085         adjusted_mode->crtc_vtotal =
1086                                 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
1087
1088         hactive = adjusted_mode->crtc_hdisplay;
1089         hfp = I915_READ(MIPI_HFP_COUNT(port));
1090
1091         /*
1092          * Meaningful for video mode non-burst sync pulse mode only,
1093          * can be zero for non-burst sync events and burst modes
1094          */
1095         hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
1096         hbp = I915_READ(MIPI_HBP_COUNT(port));
1097
1098         /* harizontal values are in terms of high speed byte clock */
1099         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1100                                                 intel_dsi->burst_mode_ratio);
1101         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1102                                                 intel_dsi->burst_mode_ratio);
1103         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1104                                                 intel_dsi->burst_mode_ratio);
1105
1106         if (intel_dsi->dual_link) {
1107                 hfp *= 2;
1108                 hsync *= 2;
1109                 hbp *= 2;
1110         }
1111
1112         /* vertical values are in terms of lines */
1113         vfp = I915_READ(MIPI_VFP_COUNT(port));
1114         vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
1115         vbp = I915_READ(MIPI_VBP_COUNT(port));
1116
1117         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1118         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1119         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1120         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1121         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1122
1123         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1124         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1125         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1126         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1127
1128         /*
1129          * In BXT DSI there is no regs programmed with few horizontal timings
1130          * in Pixels but txbyteclkhs.. So retrieval process adds some
1131          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1132          * Actually here for the given adjusted_mode, we are calculating the
1133          * value programmed to the port and then back to the horizontal timing
1134          * param in pixels. This is the expected value, including roundup errors
1135          * And if that is same as retrieved value from port, then
1136          * (HW state) adjusted_mode's horizontal timings are corrected to
1137          * match with SW state to nullify the errors.
1138          */
1139         /* Calculating the value programmed to the Port register */
1140         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1141                                         adjusted_mode_sw->crtc_hdisplay;
1142         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1143                                         adjusted_mode_sw->crtc_hsync_start;
1144         hbp_sw = adjusted_mode_sw->crtc_htotal -
1145                                         adjusted_mode_sw->crtc_hsync_end;
1146
1147         if (intel_dsi->dual_link) {
1148                 hfp_sw /= 2;
1149                 hsync_sw /= 2;
1150                 hbp_sw /= 2;
1151         }
1152
1153         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1154                                                 intel_dsi->burst_mode_ratio);
1155         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1156                             intel_dsi->burst_mode_ratio);
1157         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1158                                                 intel_dsi->burst_mode_ratio);
1159
1160         /* Reverse calculating the adjusted mode parameters from port reg vals*/
1161         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1162                                                 intel_dsi->burst_mode_ratio);
1163         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1164                                                 intel_dsi->burst_mode_ratio);
1165         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1166                                                 intel_dsi->burst_mode_ratio);
1167
1168         if (intel_dsi->dual_link) {
1169                 hfp_sw *= 2;
1170                 hsync_sw *= 2;
1171                 hbp_sw *= 2;
1172         }
1173
1174         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1175                                                         hsync_sw + hbp_sw;
1176         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1177         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1178         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1179         crtc_hblank_end_sw = crtc_htotal_sw;
1180
1181         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1182                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1183
1184         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1185                 adjusted_mode->crtc_hsync_start =
1186                                         adjusted_mode_sw->crtc_hsync_start;
1187
1188         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1189                 adjusted_mode->crtc_hsync_end =
1190                                         adjusted_mode_sw->crtc_hsync_end;
1191
1192         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1193                 adjusted_mode->crtc_hblank_start =
1194                                         adjusted_mode_sw->crtc_hblank_start;
1195
1196         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1197                 adjusted_mode->crtc_hblank_end =
1198                                         adjusted_mode_sw->crtc_hblank_end;
1199 }
1200
1201 static void intel_dsi_get_config(struct intel_encoder *encoder,
1202                                  struct intel_crtc_state *pipe_config)
1203 {
1204         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1205         u32 pclk;
1206         DRM_DEBUG_KMS("\n");
1207
1208         if (IS_GEN9_LP(dev_priv))
1209                 bxt_dsi_get_pipe_config(encoder, pipe_config);
1210
1211         pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
1212                                   pipe_config);
1213         if (!pclk)
1214                 return;
1215
1216         pipe_config->base.adjusted_mode.crtc_clock = pclk;
1217         pipe_config->port_clock = pclk;
1218 }
1219
1220 static enum drm_mode_status
1221 intel_dsi_mode_valid(struct drm_connector *connector,
1222                      struct drm_display_mode *mode)
1223 {
1224         struct intel_connector *intel_connector = to_intel_connector(connector);
1225         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
1226         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1227
1228         DRM_DEBUG_KMS("\n");
1229
1230         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
1231                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
1232                 return MODE_NO_DBLESCAN;
1233         }
1234
1235         if (fixed_mode) {
1236                 if (mode->hdisplay > fixed_mode->hdisplay)
1237                         return MODE_PANEL;
1238                 if (mode->vdisplay > fixed_mode->vdisplay)
1239                         return MODE_PANEL;
1240                 if (fixed_mode->clock > max_dotclk)
1241                         return MODE_CLOCK_HIGH;
1242         }
1243
1244         return MODE_OK;
1245 }
1246
1247 /* return txclkesc cycles in terms of divider and duration in us */
1248 static u16 txclkesc(u32 divider, unsigned int us)
1249 {
1250         switch (divider) {
1251         case ESCAPE_CLOCK_DIVIDER_1:
1252         default:
1253                 return 20 * us;
1254         case ESCAPE_CLOCK_DIVIDER_2:
1255                 return 10 * us;
1256         case ESCAPE_CLOCK_DIVIDER_4:
1257                 return 5 * us;
1258         }
1259 }
1260
1261 static void set_dsi_timings(struct drm_encoder *encoder,
1262                             const struct drm_display_mode *adjusted_mode)
1263 {
1264         struct drm_device *dev = encoder->dev;
1265         struct drm_i915_private *dev_priv = to_i915(dev);
1266         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1267         enum port port;
1268         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1269         unsigned int lane_count = intel_dsi->lane_count;
1270
1271         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1272
1273         hactive = adjusted_mode->crtc_hdisplay;
1274         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1275         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1276         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1277
1278         if (intel_dsi->dual_link) {
1279                 hactive /= 2;
1280                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1281                         hactive += intel_dsi->pixel_overlap;
1282                 hfp /= 2;
1283                 hsync /= 2;
1284                 hbp /= 2;
1285         }
1286
1287         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1288         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1289         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1290
1291         /* horizontal values are in terms of high speed byte clock */
1292         hactive = txbyteclkhs(hactive, bpp, lane_count,
1293                               intel_dsi->burst_mode_ratio);
1294         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1295         hsync = txbyteclkhs(hsync, bpp, lane_count,
1296                             intel_dsi->burst_mode_ratio);
1297         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1298
1299         for_each_dsi_port(port, intel_dsi->ports) {
1300                 if (IS_GEN9_LP(dev_priv)) {
1301                         /*
1302                          * Program hdisplay and vdisplay on MIPI transcoder.
1303                          * This is different from calculated hactive and
1304                          * vactive, as they are calculated per channel basis,
1305                          * whereas these values should be based on resolution.
1306                          */
1307                         I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1308                                    adjusted_mode->crtc_hdisplay);
1309                         I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1310                                    adjusted_mode->crtc_vdisplay);
1311                         I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1312                                    adjusted_mode->crtc_vtotal);
1313                 }
1314
1315                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1316                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
1317
1318                 /* meaningful for video mode non-burst sync pulse mode only,
1319                  * can be zero for non-burst sync events and burst modes */
1320                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1321                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
1322
1323                 /* vertical values are in terms of lines */
1324                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1325                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1326                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1327         }
1328 }
1329
1330 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1331 {
1332         switch (fmt) {
1333         case MIPI_DSI_FMT_RGB888:
1334                 return VID_MODE_FORMAT_RGB888;
1335         case MIPI_DSI_FMT_RGB666:
1336                 return VID_MODE_FORMAT_RGB666;
1337         case MIPI_DSI_FMT_RGB666_PACKED:
1338                 return VID_MODE_FORMAT_RGB666_PACKED;
1339         case MIPI_DSI_FMT_RGB565:
1340                 return VID_MODE_FORMAT_RGB565;
1341         default:
1342                 MISSING_CASE(fmt);
1343                 return VID_MODE_FORMAT_RGB666;
1344         }
1345 }
1346
1347 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1348                               struct intel_crtc_state *pipe_config)
1349 {
1350         struct drm_encoder *encoder = &intel_encoder->base;
1351         struct drm_device *dev = encoder->dev;
1352         struct drm_i915_private *dev_priv = to_i915(dev);
1353         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1354         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1355         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1356         enum port port;
1357         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1358         u32 val, tmp;
1359         u16 mode_hdisplay;
1360
1361         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
1362
1363         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1364
1365         if (intel_dsi->dual_link) {
1366                 mode_hdisplay /= 2;
1367                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1368                         mode_hdisplay += intel_dsi->pixel_overlap;
1369         }
1370
1371         for_each_dsi_port(port, intel_dsi->ports) {
1372                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1373                         /*
1374                          * escape clock divider, 20MHz, shared for A and C.
1375                          * device ready must be off when doing this! txclkesc?
1376                          */
1377                         tmp = I915_READ(MIPI_CTRL(PORT_A));
1378                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1379                         I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1380                                         ESCAPE_CLOCK_DIVIDER_1);
1381
1382                         /* read request priority is per pipe */
1383                         tmp = I915_READ(MIPI_CTRL(port));
1384                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1385                         I915_WRITE(MIPI_CTRL(port), tmp |
1386                                         READ_REQUEST_PRIORITY_HIGH);
1387                 } else if (IS_GEN9_LP(dev_priv)) {
1388                         enum pipe pipe = intel_crtc->pipe;
1389
1390                         tmp = I915_READ(MIPI_CTRL(port));
1391                         tmp &= ~BXT_PIPE_SELECT_MASK;
1392
1393                         tmp |= BXT_PIPE_SELECT(pipe);
1394                         I915_WRITE(MIPI_CTRL(port), tmp);
1395                 }
1396
1397                 /* XXX: why here, why like this? handling in irq handler?! */
1398                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1399                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1400
1401                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1402
1403                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
1404                         adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
1405                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1406         }
1407
1408         set_dsi_timings(encoder, adjusted_mode);
1409
1410         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1411         if (is_cmd_mode(intel_dsi)) {
1412                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1413                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1414         } else {
1415                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1416                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1417         }
1418
1419         tmp = 0;
1420         if (intel_dsi->eotp_pkt == 0)
1421                 tmp |= EOT_DISABLE;
1422         if (intel_dsi->clock_stop)
1423                 tmp |= CLOCKSTOP;
1424
1425         if (IS_GEN9_LP(dev_priv)) {
1426                 tmp |= BXT_DPHY_DEFEATURE_EN;
1427                 if (!is_cmd_mode(intel_dsi))
1428                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1429         }
1430
1431         for_each_dsi_port(port, intel_dsi->ports) {
1432                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1433
1434                 /* timeouts for recovery. one frame IIUC. if counter expires,
1435                  * EOT and stop state. */
1436
1437                 /*
1438                  * In burst mode, value greater than one DPI line Time in byte
1439                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1440                  * said value is recommended.
1441                  *
1442                  * In non-burst mode, Value greater than one DPI frame time in
1443                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1444                  * said value is recommended.
1445                  *
1446                  * In DBI only mode, value greater than one DBI frame time in
1447                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1448                  * said value is recommended.
1449                  */
1450
1451                 if (is_vid_mode(intel_dsi) &&
1452                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1453                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1454                                 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
1455                                             intel_dsi->lane_count,
1456                                             intel_dsi->burst_mode_ratio) + 1);
1457                 } else {
1458                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1459                                 txbyteclkhs(adjusted_mode->crtc_vtotal *
1460                                             adjusted_mode->crtc_htotal,
1461                                             bpp, intel_dsi->lane_count,
1462                                             intel_dsi->burst_mode_ratio) + 1);
1463                 }
1464                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1465                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1466                                                 intel_dsi->turn_arnd_val);
1467                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1468                                                 intel_dsi->rst_timer_val);
1469
1470                 /* dphy stuff */
1471
1472                 /* in terms of low power clock */
1473                 I915_WRITE(MIPI_INIT_COUNT(port),
1474                                 txclkesc(intel_dsi->escape_clk_div, 100));
1475
1476                 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
1477                         /*
1478                          * BXT spec says write MIPI_INIT_COUNT for
1479                          * both the ports, even if only one is
1480                          * getting used. So write the other port
1481                          * if not in dual link mode.
1482                          */
1483                         I915_WRITE(MIPI_INIT_COUNT(port ==
1484                                                 PORT_A ? PORT_C : PORT_A),
1485                                         intel_dsi->init_count);
1486                 }
1487
1488                 /* recovery disables */
1489                 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1490
1491                 /* in terms of low power clock */
1492                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1493
1494                 /* in terms of txbyteclkhs. actual high to low switch +
1495                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1496                  *
1497                  * XXX: write MIPI_STOP_STATE_STALL?
1498                  */
1499                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1500                                                 intel_dsi->hs_to_lp_count);
1501
1502                 /* XXX: low power clock equivalence in terms of byte clock.
1503                  * the number of byte clocks occupied in one low power clock.
1504                  * based on txbyteclkhs and txclkesc.
1505                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1506                  * ) / 105.???
1507                  */
1508                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1509
1510                 if (IS_GEMINILAKE(dev_priv)) {
1511                         I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
1512                                         intel_dsi->lp_byte_clk);
1513                         /* Shadow of DPHY reg */
1514                         I915_WRITE(MIPI_CLK_LANE_TIMING(port),
1515                                         intel_dsi->dphy_reg);
1516                 }
1517
1518                 /* the bw essential for transmitting 16 long packets containing
1519                  * 252 bytes meant for dcs write memory command is programmed in
1520                  * this register in terms of byte clocks. based on dsi transfer
1521                  * rate and the number of lanes configured the time taken to
1522                  * transmit 16 long packets in a dsi stream varies. */
1523                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1524
1525                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1526                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1527                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1528
1529                 if (is_vid_mode(intel_dsi))
1530                         /* Some panels might have resolution which is not a
1531                          * multiple of 64 like 1366 x 768. Enable RANDOM
1532                          * resolution support for such panels by default */
1533                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1534                                 intel_dsi->video_frmt_cfg_bits |
1535                                 intel_dsi->video_mode_format |
1536                                 IP_TG_CONFIG |
1537                                 RANDOM_DPI_DISPLAY_RESOLUTION);
1538         }
1539 }
1540
1541 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1542 {
1543         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1544         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1545         enum port port;
1546         u32 val;
1547
1548         if (!IS_GEMINILAKE(dev_priv)) {
1549                 for_each_dsi_port(port, intel_dsi->ports) {
1550                         /* Panel commands can be sent when clock is in LP11 */
1551                         I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
1552
1553                         intel_dsi_reset_clocks(encoder, port);
1554                         I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
1555
1556                         val = I915_READ(MIPI_DSI_FUNC_PRG(port));
1557                         val &= ~VID_MODE_FORMAT_MASK;
1558                         I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1559
1560                         I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
1561                 }
1562         }
1563 }
1564
1565 static int intel_dsi_get_modes(struct drm_connector *connector)
1566 {
1567         struct intel_connector *intel_connector = to_intel_connector(connector);
1568         struct drm_display_mode *mode;
1569
1570         DRM_DEBUG_KMS("\n");
1571
1572         if (!intel_connector->panel.fixed_mode) {
1573                 DRM_DEBUG_KMS("no fixed mode\n");
1574                 return 0;
1575         }
1576
1577         mode = drm_mode_duplicate(connector->dev,
1578                                   intel_connector->panel.fixed_mode);
1579         if (!mode) {
1580                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1581                 return 0;
1582         }
1583
1584         drm_mode_probed_add(connector, mode);
1585         return 1;
1586 }
1587
1588 static int intel_dsi_set_property(struct drm_connector *connector,
1589                                   struct drm_property *property,
1590                                   uint64_t val)
1591 {
1592         struct drm_device *dev = connector->dev;
1593         struct intel_connector *intel_connector = to_intel_connector(connector);
1594         struct drm_crtc *crtc;
1595         int ret;
1596
1597         ret = drm_object_property_set_value(&connector->base, property, val);
1598         if (ret)
1599                 return ret;
1600
1601         if (property == dev->mode_config.scaling_mode_property) {
1602                 if (val == DRM_MODE_SCALE_NONE) {
1603                         DRM_DEBUG_KMS("no scaling not supported\n");
1604                         return -EINVAL;
1605                 }
1606                 if (HAS_GMCH_DISPLAY(to_i915(dev)) &&
1607                     val == DRM_MODE_SCALE_CENTER) {
1608                         DRM_DEBUG_KMS("centering not supported\n");
1609                         return -EINVAL;
1610                 }
1611
1612                 if (intel_connector->panel.fitting_mode == val)
1613                         return 0;
1614
1615                 intel_connector->panel.fitting_mode = val;
1616         }
1617
1618         crtc = connector->state->crtc;
1619         if (crtc && crtc->state->enable) {
1620                 /*
1621                  * If the CRTC is enabled, the display will be changed
1622                  * according to the new panel fitting mode.
1623                  */
1624                 intel_crtc_restore_mode(crtc);
1625         }
1626
1627         return 0;
1628 }
1629
1630 static void intel_dsi_connector_destroy(struct drm_connector *connector)
1631 {
1632         struct intel_connector *intel_connector = to_intel_connector(connector);
1633
1634         DRM_DEBUG_KMS("\n");
1635         intel_panel_fini(&intel_connector->panel);
1636         drm_connector_cleanup(connector);
1637         kfree(connector);
1638 }
1639
1640 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1641 {
1642         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1643
1644         /* dispose of the gpios */
1645         if (intel_dsi->gpio_panel)
1646                 gpiod_put(intel_dsi->gpio_panel);
1647
1648         intel_encoder_destroy(encoder);
1649 }
1650
1651 static const struct drm_encoder_funcs intel_dsi_funcs = {
1652         .destroy = intel_dsi_encoder_destroy,
1653 };
1654
1655 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1656         .get_modes = intel_dsi_get_modes,
1657         .mode_valid = intel_dsi_mode_valid,
1658 };
1659
1660 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1661         .dpms = drm_atomic_helper_connector_dpms,
1662         .late_register = intel_connector_register,
1663         .early_unregister = intel_connector_unregister,
1664         .destroy = intel_dsi_connector_destroy,
1665         .fill_modes = drm_helper_probe_single_connector_modes,
1666         .set_property = intel_dsi_set_property,
1667         .atomic_get_property = intel_connector_atomic_get_property,
1668         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1669         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1670 };
1671
1672 static void intel_dsi_add_properties(struct intel_connector *connector)
1673 {
1674         struct drm_device *dev = connector->base.dev;
1675
1676         if (connector->panel.fixed_mode) {
1677                 drm_mode_create_scaling_mode_property(dev);
1678                 drm_object_attach_property(&connector->base.base,
1679                                            dev->mode_config.scaling_mode_property,
1680                                            DRM_MODE_SCALE_ASPECT);
1681                 connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
1682         }
1683 }
1684
1685 void intel_dsi_init(struct drm_i915_private *dev_priv)
1686 {
1687         struct drm_device *dev = &dev_priv->drm;
1688         struct intel_dsi *intel_dsi;
1689         struct intel_encoder *intel_encoder;
1690         struct drm_encoder *encoder;
1691         struct intel_connector *intel_connector;
1692         struct drm_connector *connector;
1693         struct drm_display_mode *scan, *fixed_mode = NULL;
1694         enum port port;
1695
1696         DRM_DEBUG_KMS("\n");
1697
1698         /* There is no detection method for MIPI so rely on VBT */
1699         if (!intel_bios_is_dsi_present(dev_priv, &port))
1700                 return;
1701
1702         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1703                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1704         } else if (IS_GEN9_LP(dev_priv)) {
1705                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1706         } else {
1707                 DRM_ERROR("Unsupported Mipi device to reg base");
1708                 return;
1709         }
1710
1711         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1712         if (!intel_dsi)
1713                 return;
1714
1715         intel_connector = intel_connector_alloc();
1716         if (!intel_connector) {
1717                 kfree(intel_dsi);
1718                 return;
1719         }
1720
1721         intel_encoder = &intel_dsi->base;
1722         encoder = &intel_encoder->base;
1723         intel_dsi->attached_connector = intel_connector;
1724
1725         connector = &intel_connector->base;
1726
1727         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1728                          "DSI %c", port_name(port));
1729
1730         intel_encoder->compute_config = intel_dsi_compute_config;
1731         intel_encoder->pre_enable = intel_dsi_pre_enable;
1732         intel_encoder->enable = intel_dsi_enable_nop;
1733         intel_encoder->disable = intel_dsi_pre_disable;
1734         intel_encoder->post_disable = intel_dsi_post_disable;
1735         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1736         intel_encoder->get_config = intel_dsi_get_config;
1737
1738         intel_connector->get_hw_state = intel_connector_get_hw_state;
1739
1740         intel_encoder->port = port;
1741
1742         /*
1743          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1744          * port C. BXT isn't limited like this.
1745          */
1746         if (IS_GEN9_LP(dev_priv))
1747                 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1748         else if (port == PORT_A)
1749                 intel_encoder->crtc_mask = BIT(PIPE_A);
1750         else
1751                 intel_encoder->crtc_mask = BIT(PIPE_B);
1752
1753         if (dev_priv->vbt.dsi.config->dual_link) {
1754                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1755
1756                 switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
1757                 case DL_DCS_PORT_A:
1758                         intel_dsi->dcs_backlight_ports = BIT(PORT_A);
1759                         break;
1760                 case DL_DCS_PORT_C:
1761                         intel_dsi->dcs_backlight_ports = BIT(PORT_C);
1762                         break;
1763                 default:
1764                 case DL_DCS_PORT_A_AND_C:
1765                         intel_dsi->dcs_backlight_ports = BIT(PORT_A) | BIT(PORT_C);
1766                         break;
1767                 }
1768
1769                 switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
1770                 case DL_DCS_PORT_A:
1771                         intel_dsi->dcs_cabc_ports = BIT(PORT_A);
1772                         break;
1773                 case DL_DCS_PORT_C:
1774                         intel_dsi->dcs_cabc_ports = BIT(PORT_C);
1775                         break;
1776                 default:
1777                 case DL_DCS_PORT_A_AND_C:
1778                         intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C);
1779                         break;
1780                 }
1781         } else {
1782                 intel_dsi->ports = BIT(port);
1783                 intel_dsi->dcs_backlight_ports = BIT(port);
1784                 intel_dsi->dcs_cabc_ports = BIT(port);
1785         }
1786
1787         if (!dev_priv->vbt.dsi.config->cabc_supported)
1788                 intel_dsi->dcs_cabc_ports = 0;
1789
1790         /* Create a DSI host (and a device) for each port. */
1791         for_each_dsi_port(port, intel_dsi->ports) {
1792                 struct intel_dsi_host *host;
1793
1794                 host = intel_dsi_host_init(intel_dsi, port);
1795                 if (!host)
1796                         goto err;
1797
1798                 intel_dsi->dsi_hosts[port] = host;
1799         }
1800
1801         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1802                 DRM_DEBUG_KMS("no device found\n");
1803                 goto err;
1804         }
1805
1806         /*
1807          * In case of BYT with CRC PMIC, we need to use GPIO for
1808          * Panel control.
1809          */
1810         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1811             (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) {
1812                 intel_dsi->gpio_panel =
1813                         gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1814
1815                 if (IS_ERR(intel_dsi->gpio_panel)) {
1816                         DRM_ERROR("Failed to own gpio for panel control\n");
1817                         intel_dsi->gpio_panel = NULL;
1818                 }
1819         }
1820
1821         intel_encoder->type = INTEL_OUTPUT_DSI;
1822         intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1823         intel_encoder->cloneable = 0;
1824         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1825                            DRM_MODE_CONNECTOR_DSI);
1826
1827         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1828
1829         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1830         connector->interlace_allowed = false;
1831         connector->doublescan_allowed = false;
1832
1833         intel_connector_attach_encoder(intel_connector, intel_encoder);
1834
1835         mutex_lock(&dev->mode_config.mutex);
1836         intel_dsi_vbt_get_modes(intel_dsi);
1837         list_for_each_entry(scan, &connector->probed_modes, head) {
1838                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1839                         fixed_mode = drm_mode_duplicate(dev, scan);
1840                         break;
1841                 }
1842         }
1843         mutex_unlock(&dev->mode_config.mutex);
1844
1845         if (!fixed_mode) {
1846                 DRM_DEBUG_KMS("no fixed mode\n");
1847                 goto err;
1848         }
1849
1850         connector->display_info.width_mm = fixed_mode->width_mm;
1851         connector->display_info.height_mm = fixed_mode->height_mm;
1852
1853         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1854         intel_panel_setup_backlight(connector, INVALID_PIPE);
1855
1856         intel_dsi_add_properties(intel_connector);
1857
1858         return;
1859
1860 err:
1861         drm_encoder_cleanup(&intel_encoder->base);
1862         kfree(intel_dsi);
1863         kfree(intel_connector);
1864 }