drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <drm/drm_panel.h>
  32 #include <drm/drm_mipi_dsi.h>
  33 #include <linux/slab.h>
  34 #include <linux/gpio/consumer.h>
  35 #include "i915_drv.h"
  36 #include "intel_drv.h"
  37 #include "intel_dsi.h"
  38
  39 static const struct {
  40         u16 panel_id;
  41         struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
  42 } intel_dsi_drivers[] = {
  43         {
  44                 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
  45                 .init = vbt_panel_init,
  46         },
  47 };
  48
  49 /* return pixels in terms of txbyteclkhs */
  50 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  51                        u16 burst_mode_ratio)
  52 {
  53         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  54                                          8 * 100), lane_count);
  55 }
  56
  57 /* return pixels equvalent to txbyteclkhs */
  58 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  59                         u16 burst_mode_ratio)
  60 {
  61         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  62                                                 (bpp * burst_mode_ratio));
  63 }
  64
  65 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  66 {
  67         /* It just so happens the VBT matches register contents. */
  68         switch (fmt) {
  69         case VID_MODE_FORMAT_RGB888:
  70                 return MIPI_DSI_FMT_RGB888;
  71         case VID_MODE_FORMAT_RGB666:
  72                 return MIPI_DSI_FMT_RGB666;
  73         case VID_MODE_FORMAT_RGB666_PACKED:
  74                 return MIPI_DSI_FMT_RGB666_PACKED;
  75         case VID_MODE_FORMAT_RGB565:
  76                 return MIPI_DSI_FMT_RGB565;
  77         default:
  78                 MISSING_CASE(fmt);
  79                 return MIPI_DSI_FMT_RGB666;
  80         }
  81 }
  82
  83 static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  84 {
  85         struct drm_encoder *encoder = &intel_dsi->base.base;
  86         struct drm_device *dev = encoder->dev;
  87         struct drm_i915_private *dev_priv = to_i915(dev);
  88         u32 mask;
  89
  90         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  91                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  92
  93         if (intel_wait_for_register(dev_priv,
  94                                     MIPI_GEN_FIFO_STAT(port), mask, mask,
  95                                     100))
  96                 DRM_ERROR("DPI FIFOs are not empty\n");
  97 }
  98
  99 static void write_data(struct drm_i915_private *dev_priv,
 100                        i915_reg_t reg,
 101                        const u8 *data, u32 len)
 102 {
 103         u32 i, j;
 104
 105         for (i = 0; i < len; i += 4) {
 106                 u32 val = 0;
 107
 108                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 109                         val |= *data++ << 8 * j;
 110
 111                 I915_WRITE(reg, val);
 112         }
 113 }
 114
 115 static void read_data(struct drm_i915_private *dev_priv,
 116                       i915_reg_t reg,
 117                       u8 *data, u32 len)
 118 {
 119         u32 i, j;
 120
 121         for (i = 0; i < len; i += 4) {
 122                 u32 val = I915_READ(reg);
 123
 124                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 125                         *data++ = val >> 8 * j;
 126         }
 127 }
 128
 129 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 130                                        const struct mipi_dsi_msg *msg)
 131 {
 132         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 133         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 134         struct drm_i915_private *dev_priv = to_i915(dev);
 135         enum port port = intel_dsi_host->port;
 136         struct mipi_dsi_packet packet;
 137         ssize_t ret;
 138         const u8 *header, *data;
 139         i915_reg_t data_reg, ctrl_reg;
 140         u32 data_mask, ctrl_mask;
 141
 142         ret = mipi_dsi_create_packet(&packet, msg);
 143         if (ret < 0)
 144                 return ret;
 145
 146         header = packet.header;
 147         data = packet.payload;
 148
 149         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 150                 data_reg = MIPI_LP_GEN_DATA(port);
 151                 data_mask = LP_DATA_FIFO_FULL;
 152                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 153                 ctrl_mask = LP_CTRL_FIFO_FULL;
 154         } else {
 155                 data_reg = MIPI_HS_GEN_DATA(port);
 156                 data_mask = HS_DATA_FIFO_FULL;
 157                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 158                 ctrl_mask = HS_CTRL_FIFO_FULL;
 159         }
 160
 161         /* note: this is never true for reads */
 162         if (packet.payload_length) {
 163                 if (intel_wait_for_register(dev_priv,
 164                                             MIPI_GEN_FIFO_STAT(port),
 165                                             data_mask, 0,
 166                                             50))
 167                         DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 168
 169                 write_data(dev_priv, data_reg, packet.payload,
 170                            packet.payload_length);
 171         }
 172
 173         if (msg->rx_len) {
 174                 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 175         }
 176
 177         if (intel_wait_for_register(dev_priv,
 178                                     MIPI_GEN_FIFO_STAT(port),
 179                                     ctrl_mask, 0,
 180                                     50)) {
 181                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 182         }
 183
 184         I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
 185
 186         /* ->rx_len is set only for reads */
 187         if (msg->rx_len) {
 188                 data_mask = GEN_READ_DATA_AVAIL;
 189                 if (intel_wait_for_register(dev_priv,
 190                                             MIPI_INTR_STAT(port),
 191                                             data_mask, data_mask,
 192                                             50))
 193                         DRM_ERROR("Timeout waiting for read data.\n");
 194
 195                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 196         }
 197
 198         /* XXX: fix for reads and writes */
 199         return 4 + packet.payload_length;
 200 }
 201
 202 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 203                                  struct mipi_dsi_device *dsi)
 204 {
 205         return 0;
 206 }
 207
 208 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 209                                  struct mipi_dsi_device *dsi)
 210 {
 211         return 0;
 212 }
 213
 214 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 215         .attach = intel_dsi_host_attach,
 216         .detach = intel_dsi_host_detach,
 217         .transfer = intel_dsi_host_transfer,
 218 };
 219
 220 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
 221                                                   enum port port)
 222 {
 223         struct intel_dsi_host *host;
 224         struct mipi_dsi_device *device;
 225
 226         host = kzalloc(sizeof(*host), GFP_KERNEL);
 227         if (!host)
 228                 return NULL;
 229
 230         host->base.ops = &intel_dsi_host_ops;
 231         host->intel_dsi = intel_dsi;
 232         host->port = port;
 233
 234         /*
 235          * We should call mipi_dsi_host_register(&host->base) here, but we don't
 236          * have a host->dev, and we don't have OF stuff either. So just use the
 237          * dsi framework as a library and hope for the best. Create the dsi
 238          * devices by ourselves here too. Need to be careful though, because we
 239          * don't initialize any of the driver model devices here.
 240          */
 241         device = kzalloc(sizeof(*device), GFP_KERNEL);
 242         if (!device) {
 243                 kfree(host);
 244                 return NULL;
 245         }
 246
 247         device->host = &host->base;
 248         host->device = device;
 249
 250         return host;
 251 }
 252
 253 /*
 254  * send a video mode command
 255  *
 256  * XXX: commands with data in MIPI_DPI_DATA?
 257  */
 258 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 259                         enum port port)
 260 {
 261         struct drm_encoder *encoder = &intel_dsi->base.base;
 262         struct drm_device *dev = encoder->dev;
 263         struct drm_i915_private *dev_priv = to_i915(dev);
 264         u32 mask;
 265
 266         /* XXX: pipe, hs */
 267         if (hs)
 268                 cmd &= ~DPI_LP_MODE;
 269         else
 270                 cmd |= DPI_LP_MODE;
 271
 272         /* clear bit */
 273         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 274
 275         /* XXX: old code skips write if control unchanged */
 276         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 277                 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
 278
 279         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 280
 281         mask = SPL_PKT_SENT_INTERRUPT;
 282         if (intel_wait_for_register(dev_priv,
 283                                     MIPI_INTR_STAT(port), mask, mask,
 284                                     100))
 285                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 286
 287         return 0;
 288 }
 289
 290 static void band_gap_reset(struct drm_i915_private *dev_priv)
 291 {
 292         mutex_lock(&dev_priv->sb_lock);
 293
 294         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 295         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 296         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 297         udelay(150);
 298         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 299         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 300
 301         mutex_unlock(&dev_priv->sb_lock);
 302 }
 303
 304 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
 305 {
 306         return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
 307 }
 308
 309 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
 310 {
 311         return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
 312 }
 313
 314 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 315                                      struct intel_crtc_state *pipe_config,
 316                                      struct drm_connector_state *conn_state)
 317 {
 318         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 319         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 320                                                    base);
 321         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 322         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 323         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 324         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 325         int ret;
 326
 327         DRM_DEBUG_KMS("\n");
 328
 329         if (fixed_mode) {
 330                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 331
 332                 if (HAS_GMCH_DISPLAY(dev_priv))
 333                         intel_gmch_panel_fitting(crtc, pipe_config,
 334                                                  intel_connector->panel.fitting_mode);
 335                 else
 336                         intel_pch_panel_fitting(crtc, pipe_config,
 337                                                 intel_connector->panel.fitting_mode);
 338         }
 339
 340         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 341         adjusted_mode->flags = 0;
 342
 343         if (IS_BROXTON(dev_priv)) {
 344                 /* Dual link goes to DSI transcoder A. */
 345                 if (intel_dsi->ports == BIT(PORT_C))
 346                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 347                 else
 348                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 349         }
 350
 351         ret = intel_compute_dsi_pll(encoder, pipe_config);
 352         if (ret)
 353                 return false;
 354
 355         pipe_config->clock_set = true;
 356
 357         return true;
 358 }
 359
 360 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 361 {
 362         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 363         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 364         enum port port;
 365         u32 val;
 366
 367         DRM_DEBUG_KMS("\n");
 368
 369         /* Exit Low power state in 4 steps*/
 370         for_each_dsi_port(port, intel_dsi->ports) {
 371
 372                 /* 1. Enable MIPI PHY transparent latch */
 373                 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
 374                 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
 375                 usleep_range(2000, 2500);
 376
 377                 /* 2. Enter ULPS */
 378                 val = I915_READ(MIPI_DEVICE_READY(port));
 379                 val &= ~ULPS_STATE_MASK;
 380                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 381                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 382                 usleep_range(2, 3);
 383
 384                 /* 3. Exit ULPS */
 385                 val = I915_READ(MIPI_DEVICE_READY(port));
 386                 val &= ~ULPS_STATE_MASK;
 387                 val |= (ULPS_STATE_EXIT | DEVICE_READY);
 388                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 389                 usleep_range(1000, 1500);
 390
 391                 /* Clear ULPS and set device ready */
 392                 val = I915_READ(MIPI_DEVICE_READY(port));
 393                 val &= ~ULPS_STATE_MASK;
 394                 val |= DEVICE_READY;
 395                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 396         }
 397 }
 398
 399 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 400 {
 401         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 402         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 403         enum port port;
 404         u32 val;
 405
 406         DRM_DEBUG_KMS("\n");
 407
 408         mutex_lock(&dev_priv->sb_lock);
 409         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 410          * needed everytime after power gate */
 411         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 412         mutex_unlock(&dev_priv->sb_lock);
 413
 414         /* bandgap reset is needed after everytime we do power gate */
 415         band_gap_reset(dev_priv);
 416
 417         for_each_dsi_port(port, intel_dsi->ports) {
 418
 419                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 420                 usleep_range(2500, 3000);
 421
 422                 /* Enable MIPI PHY transparent latch
 423                  * Common bit for both MIPI Port A & MIPI Port C
 424                  * No similar bit in MIPI Port C reg
 425                  */
 426                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 427                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 428                 usleep_range(1000, 1500);
 429
 430                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 431                 usleep_range(2500, 3000);
 432
 433                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 434                 usleep_range(2500, 3000);
 435         }
 436 }
 437
 438 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 439 {
 440         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 441
 442         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 443                 vlv_dsi_device_ready(encoder);
 444         else if (IS_BROXTON(dev_priv))
 445                 bxt_dsi_device_ready(encoder);
 446 }
 447
 448 static void intel_dsi_port_enable(struct intel_encoder *encoder)
 449 {
 450         struct drm_device *dev = encoder->base.dev;
 451         struct drm_i915_private *dev_priv = to_i915(dev);
 452         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 453         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 454         enum port port;
 455
 456         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 457                 u32 temp;
 458
 459                 temp = I915_READ(VLV_CHICKEN_3);
 460                 temp &= ~PIXEL_OVERLAP_CNT_MASK |
 461                                         intel_dsi->pixel_overlap <<
 462                                         PIXEL_OVERLAP_CNT_SHIFT;
 463                 I915_WRITE(VLV_CHICKEN_3, temp);
 464         }
 465
 466         for_each_dsi_port(port, intel_dsi->ports) {
 467                 i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
 468                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 469                 u32 temp;
 470
 471                 temp = I915_READ(port_ctrl);
 472
 473                 temp &= ~LANE_CONFIGURATION_MASK;
 474                 temp &= ~DUAL_LINK_MODE_MASK;
 475
 476                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 477                         temp |= (intel_dsi->dual_link - 1)
 478                                                 << DUAL_LINK_MODE_SHIFT;
 479                         temp |= intel_crtc->pipe ?
 480                                         LANE_CONFIGURATION_DUAL_LINK_B :
 481                                         LANE_CONFIGURATION_DUAL_LINK_A;
 482                 }
 483                 /* assert ip_tg_enable signal */
 484                 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
 485                 POSTING_READ(port_ctrl);
 486         }
 487 }
 488
 489 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 490 {
 491         struct drm_device *dev = encoder->base.dev;
 492         struct drm_i915_private *dev_priv = to_i915(dev);
 493         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 494         enum port port;
 495
 496         for_each_dsi_port(port, intel_dsi->ports) {
 497                 i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
 498                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 499                 u32 temp;
 500
 501                 /* de-assert ip_tg_enable signal */
 502                 temp = I915_READ(port_ctrl);
 503                 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
 504                 POSTING_READ(port_ctrl);
 505         }
 506 }
 507
 508 static void intel_dsi_enable(struct intel_encoder *encoder)
 509 {
 510         struct drm_device *dev = encoder->base.dev;
 511         struct drm_i915_private *dev_priv = to_i915(dev);
 512         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 513         enum port port;
 514
 515         DRM_DEBUG_KMS("\n");
 516
 517         if (is_cmd_mode(intel_dsi)) {
 518                 for_each_dsi_port(port, intel_dsi->ports)
 519                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 520         } else {
 521                 msleep(20); /* XXX */
 522                 for_each_dsi_port(port, intel_dsi->ports)
 523                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 524                 msleep(100);
 525
 526                 drm_panel_enable(intel_dsi->panel);
 527
 528                 for_each_dsi_port(port, intel_dsi->ports)
 529                         wait_for_dsi_fifo_empty(intel_dsi, port);
 530
 531                 intel_dsi_port_enable(encoder);
 532         }
 533
 534         intel_panel_enable_backlight(intel_dsi->attached_connector);
 535 }
 536
 537 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 538                               struct intel_crtc_state *pipe_config);
 539
 540 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 541                                  struct intel_crtc_state *pipe_config,
 542                                  struct drm_connector_state *conn_state)
 543 {
 544         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 545         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 546         enum port port;
 547
 548         DRM_DEBUG_KMS("\n");
 549
 550         /*
 551          * The BIOS may leave the PLL in a wonky state where it doesn't
 552          * lock. It needs to be fully powered down to fix it.
 553          */
 554         intel_disable_dsi_pll(encoder);
 555         intel_enable_dsi_pll(encoder, pipe_config);
 556
 557         intel_dsi_prepare(encoder, pipe_config);
 558
 559         /* Panel Enable over CRC PMIC */
 560         if (intel_dsi->gpio_panel)
 561                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
 562
 563         msleep(intel_dsi->panel_on_delay);
 564
 565         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 566                 u32 val;
 567
 568                 /* Disable DPOunit clock gating, can stall pipe */
 569                 val = I915_READ(DSPCLK_GATE_D);
 570                 val |= DPOUNIT_CLOCK_GATE_DISABLE;
 571                 I915_WRITE(DSPCLK_GATE_D, val);
 572         }
 573
 574         /* put device in ready state */
 575         intel_dsi_device_ready(encoder);
 576
 577         drm_panel_prepare(intel_dsi->panel);
 578
 579         for_each_dsi_port(port, intel_dsi->ports)
 580                 wait_for_dsi_fifo_empty(intel_dsi, port);
 581
 582         /* Enable port in pre-enable phase itself because as per hw team
 583          * recommendation, port should be enabled befor plane & pipe */
 584         intel_dsi_enable(encoder);
 585 }
 586
 587 static void intel_dsi_enable_nop(struct intel_encoder *encoder,
 588                                  struct intel_crtc_state *pipe_config,
 589                                  struct drm_connector_state *conn_state)
 590 {
 591         DRM_DEBUG_KMS("\n");
 592
 593         /* for DSI port enable has to be done before pipe
 594          * and plane enable, so port enable is done in
 595          * pre_enable phase itself unlike other encoders
 596          */
 597 }
 598
 599 static void intel_dsi_pre_disable(struct intel_encoder *encoder,
 600                                   struct intel_crtc_state *old_crtc_state,
 601                                   struct drm_connector_state *old_conn_state)
 602 {
 603         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 604         enum port port;
 605
 606         DRM_DEBUG_KMS("\n");
 607
 608         intel_panel_disable_backlight(intel_dsi->attached_connector);
 609
 610         if (is_vid_mode(intel_dsi)) {
 611                 /* Send Shutdown command to the panel in LP mode */
 612                 for_each_dsi_port(port, intel_dsi->ports)
 613                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 614                 msleep(10);
 615         }
 616 }
 617
 618 static void intel_dsi_disable(struct intel_encoder *encoder)
 619 {
 620         struct drm_device *dev = encoder->base.dev;
 621         struct drm_i915_private *dev_priv = to_i915(dev);
 622         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 623         enum port port;
 624         u32 temp;
 625
 626         DRM_DEBUG_KMS("\n");
 627
 628         if (is_vid_mode(intel_dsi)) {
 629                 for_each_dsi_port(port, intel_dsi->ports)
 630                         wait_for_dsi_fifo_empty(intel_dsi, port);
 631
 632                 intel_dsi_port_disable(encoder);
 633                 msleep(2);
 634         }
 635
 636         for_each_dsi_port(port, intel_dsi->ports) {
 637                 /* Panel commands can be sent when clock is in LP11 */
 638                 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
 639
 640                 intel_dsi_reset_clocks(encoder, port);
 641                 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 642
 643                 temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
 644                 temp &= ~VID_MODE_FORMAT_MASK;
 645                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
 646
 647                 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
 648         }
 649         /* if disable packets are sent before sending shutdown packet then in
 650          * some next enable sequence send turn on packet error is observed */
 651         drm_panel_disable(intel_dsi->panel);
 652
 653         for_each_dsi_port(port, intel_dsi->ports)
 654                 wait_for_dsi_fifo_empty(intel_dsi, port);
 655 }
 656
 657 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 658 {
 659         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 660         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 661         enum port port;
 662
 663         DRM_DEBUG_KMS("\n");
 664         for_each_dsi_port(port, intel_dsi->ports) {
 665                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 666                 i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
 667                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 668                 u32 val;
 669
 670                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 671                                                         ULPS_STATE_ENTER);
 672                 usleep_range(2000, 2500);
 673
 674                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 675                                                         ULPS_STATE_EXIT);
 676                 usleep_range(2000, 2500);
 677
 678                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 679                                                         ULPS_STATE_ENTER);
 680                 usleep_range(2000, 2500);
 681
 682                 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
 683                  * only. MIPI Port C has no similar bit for checking
 684                  */
 685                 if (intel_wait_for_register(dev_priv,
 686                                             port_ctrl, AFE_LATCHOUT, 0,
 687                                             30))
 688                         DRM_ERROR("DSI LP not going Low\n");
 689
 690                 /* Disable MIPI PHY transparent latch */
 691                 val = I915_READ(port_ctrl);
 692                 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
 693                 usleep_range(1000, 1500);
 694
 695                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 696                 usleep_range(2000, 2500);
 697         }
 698
 699         intel_disable_dsi_pll(encoder);
 700 }
 701
 702 static void intel_dsi_post_disable(struct intel_encoder *encoder,
 703                                    struct intel_crtc_state *pipe_config,
 704                                    struct drm_connector_state *conn_state)
 705 {
 706         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 707         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 708
 709         DRM_DEBUG_KMS("\n");
 710
 711         intel_dsi_disable(encoder);
 712
 713         intel_dsi_clear_device_ready(encoder);
 714
 715         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 716                 u32 val;
 717
 718                 val = I915_READ(DSPCLK_GATE_D);
 719                 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 720                 I915_WRITE(DSPCLK_GATE_D, val);
 721         }
 722
 723         drm_panel_unprepare(intel_dsi->panel);
 724
 725         msleep(intel_dsi->panel_off_delay);
 726
 727         /* Panel Disable over CRC PMIC */
 728         if (intel_dsi->gpio_panel)
 729                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
 730
 731         /*
 732          * FIXME As we do with eDP, just make a note of the time here
 733          * and perform the wait before the next panel power on.
 734          */
 735         msleep(intel_dsi->panel_pwr_cycle_delay);
 736 }
 737
 738 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 739                                    enum pipe *pipe)
 740 {
 741         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 742         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 743         enum intel_display_power_domain power_domain;
 744         enum port port;
 745         bool active = false;
 746
 747         DRM_DEBUG_KMS("\n");
 748
 749         power_domain = intel_display_port_power_domain(encoder);
 750         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 751                 return false;
 752
 753         /*
 754          * On Broxton the PLL needs to be enabled with a valid divider
 755          * configuration, otherwise accessing DSI registers will hang the
 756          * machine. See BSpec North Display Engine registers/MIPI[BXT].
 757          */
 758         if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
 759                 goto out_put_power;
 760
 761         /* XXX: this only works for one DSI output */
 762         for_each_dsi_port(port, intel_dsi->ports) {
 763                 i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
 764                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 765                 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
 766
 767                 /*
 768                  * Due to some hardware limitations on VLV/CHV, the DPI enable
 769                  * bit in port C control register does not get set. As a
 770                  * workaround, check pipe B conf instead.
 771                  */
 772                 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 773                     port == PORT_C)
 774                         enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
 775
 776                 /* Try command mode if video mode not enabled */
 777                 if (!enabled) {
 778                         u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
 779                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
 780                 }
 781
 782                 if (!enabled)
 783                         continue;
 784
 785                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
 786                         continue;
 787
 788                 if (IS_BROXTON(dev_priv)) {
 789                         u32 tmp = I915_READ(MIPI_CTRL(port));
 790                         tmp &= BXT_PIPE_SELECT_MASK;
 791                         tmp >>= BXT_PIPE_SELECT_SHIFT;
 792
 793                         if (WARN_ON(tmp > PIPE_C))
 794                                 continue;
 795
 796                         *pipe = tmp;
 797                 } else {
 798                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
 799                 }
 800
 801                 active = true;
 802                 break;
 803         }
 804
 805 out_put_power:
 806         intel_display_power_put(dev_priv, power_domain);
 807
 808         return active;
 809 }
 810
 811 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
 812                                  struct intel_crtc_state *pipe_config)
 813 {
 814         struct drm_device *dev = encoder->base.dev;
 815         struct drm_i915_private *dev_priv = to_i915(dev);
 816         struct drm_display_mode *adjusted_mode =
 817                                         &pipe_config->base.adjusted_mode;
 818         struct drm_display_mode *adjusted_mode_sw;
 819         struct intel_crtc *intel_crtc;
 820         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 821         unsigned int lane_count = intel_dsi->lane_count;
 822         unsigned int bpp, fmt;
 823         enum port port;
 824         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 825         u16 hfp_sw, hsync_sw, hbp_sw;
 826         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
 827                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
 828
 829         /* FIXME: hw readout should not depend on SW state */
 830         intel_crtc = to_intel_crtc(encoder->base.crtc);
 831         adjusted_mode_sw = &intel_crtc->config->base.adjusted_mode;
 832
 833         /*
 834          * Atleast one port is active as encoder->get_config called only if
 835          * encoder->get_hw_state() returns true.
 836          */
 837         for_each_dsi_port(port, intel_dsi->ports) {
 838                 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
 839                         break;
 840         }
 841
 842         fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
 843         pipe_config->pipe_bpp =
 844                         mipi_dsi_pixel_format_to_bpp(
 845                                 pixel_format_from_register_bits(fmt));
 846         bpp = pipe_config->pipe_bpp;
 847
 848         /* In terms of pixels */
 849         adjusted_mode->crtc_hdisplay =
 850                                 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
 851         adjusted_mode->crtc_vdisplay =
 852                                 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
 853         adjusted_mode->crtc_vtotal =
 854                                 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
 855
 856         hactive = adjusted_mode->crtc_hdisplay;
 857         hfp = I915_READ(MIPI_HFP_COUNT(port));
 858
 859         /*
 860          * Meaningful for video mode non-burst sync pulse mode only,
 861          * can be zero for non-burst sync events and burst modes
 862          */
 863         hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
 864         hbp = I915_READ(MIPI_HBP_COUNT(port));
 865
 866         /* harizontal values are in terms of high speed byte clock */
 867         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
 868                                                 intel_dsi->burst_mode_ratio);
 869         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
 870                                                 intel_dsi->burst_mode_ratio);
 871         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
 872                                                 intel_dsi->burst_mode_ratio);
 873
 874         if (intel_dsi->dual_link) {
 875                 hfp *= 2;
 876                 hsync *= 2;
 877                 hbp *= 2;
 878         }
 879
 880         /* vertical values are in terms of lines */
 881         vfp = I915_READ(MIPI_VFP_COUNT(port));
 882         vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
 883         vbp = I915_READ(MIPI_VBP_COUNT(port));
 884
 885         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
 886         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
 887         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
 888         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
 889         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
 890
 891         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
 892         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
 893         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
 894         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
 895
 896         /*
 897          * In BXT DSI there is no regs programmed with few horizontal timings
 898          * in Pixels but txbyteclkhs.. So retrieval process adds some
 899          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
 900          * Actually here for the given adjusted_mode, we are calculating the
 901          * value programmed to the port and then back to the horizontal timing
 902          * param in pixels. This is the expected value, including roundup errors
 903          * And if that is same as retrieved value from port, then
 904          * (HW state) adjusted_mode's horizontal timings are corrected to
 905          * match with SW state to nullify the errors.
 906          */
 907         /* Calculating the value programmed to the Port register */
 908         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
 909                                         adjusted_mode_sw->crtc_hdisplay;
 910         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
 911                                         adjusted_mode_sw->crtc_hsync_start;
 912         hbp_sw = adjusted_mode_sw->crtc_htotal -
 913                                         adjusted_mode_sw->crtc_hsync_end;
 914
 915         if (intel_dsi->dual_link) {
 916                 hfp_sw /= 2;
 917                 hsync_sw /= 2;
 918                 hbp_sw /= 2;
 919         }
 920
 921         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
 922                                                 intel_dsi->burst_mode_ratio);
 923         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
 924                             intel_dsi->burst_mode_ratio);
 925         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
 926                                                 intel_dsi->burst_mode_ratio);
 927
 928         /* Reverse calculating the adjusted mode parameters from port reg vals*/
 929         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
 930                                                 intel_dsi->burst_mode_ratio);
 931         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
 932                                                 intel_dsi->burst_mode_ratio);
 933         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
 934                                                 intel_dsi->burst_mode_ratio);
 935
 936         if (intel_dsi->dual_link) {
 937                 hfp_sw *= 2;
 938                 hsync_sw *= 2;
 939                 hbp_sw *= 2;
 940         }
 941
 942         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
 943                                                         hsync_sw + hbp_sw;
 944         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
 945         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
 946         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
 947         crtc_hblank_end_sw = crtc_htotal_sw;
 948
 949         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
 950                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
 951
 952         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
 953                 adjusted_mode->crtc_hsync_start =
 954                                         adjusted_mode_sw->crtc_hsync_start;
 955
 956         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
 957                 adjusted_mode->crtc_hsync_end =
 958                                         adjusted_mode_sw->crtc_hsync_end;
 959
 960         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
 961                 adjusted_mode->crtc_hblank_start =
 962                                         adjusted_mode_sw->crtc_hblank_start;
 963
 964         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
 965                 adjusted_mode->crtc_hblank_end =
 966                                         adjusted_mode_sw->crtc_hblank_end;
 967 }
 968
 969 static void intel_dsi_get_config(struct intel_encoder *encoder,
 970                                  struct intel_crtc_state *pipe_config)
 971 {
 972         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 973         u32 pclk;
 974         DRM_DEBUG_KMS("\n");
 975
 976         if (IS_BROXTON(dev_priv))
 977                 bxt_dsi_get_pipe_config(encoder, pipe_config);
 978
 979         pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
 980                                   pipe_config);
 981         if (!pclk)
 982                 return;
 983
 984         pipe_config->base.adjusted_mode.crtc_clock = pclk;
 985         pipe_config->port_clock = pclk;
 986 }
 987
 988 static enum drm_mode_status
 989 intel_dsi_mode_valid(struct drm_connector *connector,
 990                      struct drm_display_mode *mode)
 991 {
 992         struct intel_connector *intel_connector = to_intel_connector(connector);
 993         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 994         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 995
 996         DRM_DEBUG_KMS("\n");
 997
 998         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 999                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
1000                 return MODE_NO_DBLESCAN;
1001         }
1002
1003         if (fixed_mode) {
1004                 if (mode->hdisplay > fixed_mode->hdisplay)
1005                         return MODE_PANEL;
1006                 if (mode->vdisplay > fixed_mode->vdisplay)
1007                         return MODE_PANEL;
1008                 if (fixed_mode->clock > max_dotclk)
1009                         return MODE_CLOCK_HIGH;
1010         }
1011
1012         return MODE_OK;
1013 }
1014
1015 /* return txclkesc cycles in terms of divider and duration in us */
1016 static u16 txclkesc(u32 divider, unsigned int us)
1017 {
1018         switch (divider) {
1019         case ESCAPE_CLOCK_DIVIDER_1:
1020         default:
1021                 return 20 * us;
1022         case ESCAPE_CLOCK_DIVIDER_2:
1023                 return 10 * us;
1024         case ESCAPE_CLOCK_DIVIDER_4:
1025                 return 5 * us;
1026         }
1027 }
1028
1029 static void set_dsi_timings(struct drm_encoder *encoder,
1030                             const struct drm_display_mode *adjusted_mode)
1031 {
1032         struct drm_device *dev = encoder->dev;
1033         struct drm_i915_private *dev_priv = to_i915(dev);
1034         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1035         enum port port;
1036         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1037         unsigned int lane_count = intel_dsi->lane_count;
1038
1039         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1040
1041         hactive = adjusted_mode->crtc_hdisplay;
1042         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1043         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1044         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1045
1046         if (intel_dsi->dual_link) {
1047                 hactive /= 2;
1048                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1049                         hactive += intel_dsi->pixel_overlap;
1050                 hfp /= 2;
1051                 hsync /= 2;
1052                 hbp /= 2;
1053         }
1054
1055         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1056         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1057         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1058
1059         /* horizontal values are in terms of high speed byte clock */
1060         hactive = txbyteclkhs(hactive, bpp, lane_count,
1061                               intel_dsi->burst_mode_ratio);
1062         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1063         hsync = txbyteclkhs(hsync, bpp, lane_count,
1064                             intel_dsi->burst_mode_ratio);
1065         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1066
1067         for_each_dsi_port(port, intel_dsi->ports) {
1068                 if (IS_BROXTON(dev_priv)) {
1069                         /*
1070                          * Program hdisplay and vdisplay on MIPI transcoder.
1071                          * This is different from calculated hactive and
1072                          * vactive, as they are calculated per channel basis,
1073                          * whereas these values should be based on resolution.
1074                          */
1075                         I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1076                                    adjusted_mode->crtc_hdisplay);
1077                         I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1078                                    adjusted_mode->crtc_vdisplay);
1079                         I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1080                                    adjusted_mode->crtc_vtotal);
1081                 }
1082
1083                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1084                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
1085
1086                 /* meaningful for video mode non-burst sync pulse mode only,
1087                  * can be zero for non-burst sync events and burst modes */
1088                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1089                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
1090
1091                 /* vertical values are in terms of lines */
1092                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1093                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1094                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1095         }
1096 }
1097
1098 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1099 {
1100         switch (fmt) {
1101         case MIPI_DSI_FMT_RGB888:
1102                 return VID_MODE_FORMAT_RGB888;
1103         case MIPI_DSI_FMT_RGB666:
1104                 return VID_MODE_FORMAT_RGB666;
1105         case MIPI_DSI_FMT_RGB666_PACKED:
1106                 return VID_MODE_FORMAT_RGB666_PACKED;
1107         case MIPI_DSI_FMT_RGB565:
1108                 return VID_MODE_FORMAT_RGB565;
1109         default:
1110                 MISSING_CASE(fmt);
1111                 return VID_MODE_FORMAT_RGB666;
1112         }
1113 }
1114
1115 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1116                               struct intel_crtc_state *pipe_config)
1117 {
1118         struct drm_encoder *encoder = &intel_encoder->base;
1119         struct drm_device *dev = encoder->dev;
1120         struct drm_i915_private *dev_priv = to_i915(dev);
1121         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1122         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1123         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1124         enum port port;
1125         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1126         u32 val, tmp;
1127         u16 mode_hdisplay;
1128
1129         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
1130
1131         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1132
1133         if (intel_dsi->dual_link) {
1134                 mode_hdisplay /= 2;
1135                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1136                         mode_hdisplay += intel_dsi->pixel_overlap;
1137         }
1138
1139         for_each_dsi_port(port, intel_dsi->ports) {
1140                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1141                         /*
1142                          * escape clock divider, 20MHz, shared for A and C.
1143                          * device ready must be off when doing this! txclkesc?
1144                          */
1145                         tmp = I915_READ(MIPI_CTRL(PORT_A));
1146                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1147                         I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1148                                         ESCAPE_CLOCK_DIVIDER_1);
1149
1150                         /* read request priority is per pipe */
1151                         tmp = I915_READ(MIPI_CTRL(port));
1152                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1153                         I915_WRITE(MIPI_CTRL(port), tmp |
1154                                         READ_REQUEST_PRIORITY_HIGH);
1155                 } else if (IS_BROXTON(dev_priv)) {
1156                         enum pipe pipe = intel_crtc->pipe;
1157
1158                         tmp = I915_READ(MIPI_CTRL(port));
1159                         tmp &= ~BXT_PIPE_SELECT_MASK;
1160
1161                         tmp |= BXT_PIPE_SELECT(pipe);
1162                         I915_WRITE(MIPI_CTRL(port), tmp);
1163                 }
1164
1165                 /* XXX: why here, why like this? handling in irq handler?! */
1166                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1167                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1168
1169                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1170
1171                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
1172                         adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
1173                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1174         }
1175
1176         set_dsi_timings(encoder, adjusted_mode);
1177
1178         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1179         if (is_cmd_mode(intel_dsi)) {
1180                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1181                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1182         } else {
1183                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1184                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1185         }
1186
1187         tmp = 0;
1188         if (intel_dsi->eotp_pkt == 0)
1189                 tmp |= EOT_DISABLE;
1190         if (intel_dsi->clock_stop)
1191                 tmp |= CLOCKSTOP;
1192
1193         if (IS_BROXTON(dev_priv)) {
1194                 tmp |= BXT_DPHY_DEFEATURE_EN;
1195                 if (!is_cmd_mode(intel_dsi))
1196                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1197         }
1198
1199         for_each_dsi_port(port, intel_dsi->ports) {
1200                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1201
1202                 /* timeouts for recovery. one frame IIUC. if counter expires,
1203                  * EOT and stop state. */
1204
1205                 /*
1206                  * In burst mode, value greater than one DPI line Time in byte
1207                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1208                  * said value is recommended.
1209                  *
1210                  * In non-burst mode, Value greater than one DPI frame time in
1211                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1212                  * said value is recommended.
1213                  *
1214                  * In DBI only mode, value greater than one DBI frame time in
1215                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1216                  * said value is recommended.
1217                  */
1218
1219                 if (is_vid_mode(intel_dsi) &&
1220                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1221                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1222                                 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
1223                                             intel_dsi->lane_count,
1224                                             intel_dsi->burst_mode_ratio) + 1);
1225                 } else {
1226                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1227                                 txbyteclkhs(adjusted_mode->crtc_vtotal *
1228                                             adjusted_mode->crtc_htotal,
1229                                             bpp, intel_dsi->lane_count,
1230                                             intel_dsi->burst_mode_ratio) + 1);
1231                 }
1232                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1233                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1234                                                 intel_dsi->turn_arnd_val);
1235                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1236                                                 intel_dsi->rst_timer_val);
1237
1238                 /* dphy stuff */
1239
1240                 /* in terms of low power clock */
1241                 I915_WRITE(MIPI_INIT_COUNT(port),
1242                                 txclkesc(intel_dsi->escape_clk_div, 100));
1243
1244                 if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
1245                         /*
1246                          * BXT spec says write MIPI_INIT_COUNT for
1247                          * both the ports, even if only one is
1248                          * getting used. So write the other port
1249                          * if not in dual link mode.
1250                          */
1251                         I915_WRITE(MIPI_INIT_COUNT(port ==
1252                                                 PORT_A ? PORT_C : PORT_A),
1253                                         intel_dsi->init_count);
1254                 }
1255
1256                 /* recovery disables */
1257                 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1258
1259                 /* in terms of low power clock */
1260                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1261
1262                 /* in terms of txbyteclkhs. actual high to low switch +
1263                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1264                  *
1265                  * XXX: write MIPI_STOP_STATE_STALL?
1266                  */
1267                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1268                                                 intel_dsi->hs_to_lp_count);
1269
1270                 /* XXX: low power clock equivalence in terms of byte clock.
1271                  * the number of byte clocks occupied in one low power clock.
1272                  * based on txbyteclkhs and txclkesc.
1273                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1274                  * ) / 105.???
1275                  */
1276                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1277
1278                 /* the bw essential for transmitting 16 long packets containing
1279                  * 252 bytes meant for dcs write memory command is programmed in
1280                  * this register in terms of byte clocks. based on dsi transfer
1281                  * rate and the number of lanes configured the time taken to
1282                  * transmit 16 long packets in a dsi stream varies. */
1283                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1284
1285                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1286                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1287                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1288
1289                 if (is_vid_mode(intel_dsi))
1290                         /* Some panels might have resolution which is not a
1291                          * multiple of 64 like 1366 x 768. Enable RANDOM
1292                          * resolution support for such panels by default */
1293                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1294                                 intel_dsi->video_frmt_cfg_bits |
1295                                 intel_dsi->video_mode_format |
1296                                 IP_TG_CONFIG |
1297                                 RANDOM_DPI_DISPLAY_RESOLUTION);
1298         }
1299 }
1300
1301 static int intel_dsi_get_modes(struct drm_connector *connector)
1302 {
1303         struct intel_connector *intel_connector = to_intel_connector(connector);
1304         struct drm_display_mode *mode;
1305
1306         DRM_DEBUG_KMS("\n");
1307
1308         if (!intel_connector->panel.fixed_mode) {
1309                 DRM_DEBUG_KMS("no fixed mode\n");
1310                 return 0;
1311         }
1312
1313         mode = drm_mode_duplicate(connector->dev,
1314                                   intel_connector->panel.fixed_mode);
1315         if (!mode) {
1316                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1317                 return 0;
1318         }
1319
1320         drm_mode_probed_add(connector, mode);
1321         return 1;
1322 }
1323
1324 static int intel_dsi_set_property(struct drm_connector *connector,
1325                                   struct drm_property *property,
1326                                   uint64_t val)
1327 {
1328         struct drm_device *dev = connector->dev;
1329         struct intel_connector *intel_connector = to_intel_connector(connector);
1330         struct drm_crtc *crtc;
1331         int ret;
1332
1333         ret = drm_object_property_set_value(&connector->base, property, val);
1334         if (ret)
1335                 return ret;
1336
1337         if (property == dev->mode_config.scaling_mode_property) {
1338                 if (val == DRM_MODE_SCALE_NONE) {
1339                         DRM_DEBUG_KMS("no scaling not supported\n");
1340                         return -EINVAL;
1341                 }
1342                 if (HAS_GMCH_DISPLAY(to_i915(dev)) &&
1343                     val == DRM_MODE_SCALE_CENTER) {
1344                         DRM_DEBUG_KMS("centering not supported\n");
1345                         return -EINVAL;
1346                 }
1347
1348                 if (intel_connector->panel.fitting_mode == val)
1349                         return 0;
1350
1351                 intel_connector->panel.fitting_mode = val;
1352         }
1353
1354         crtc = connector->state->crtc;
1355         if (crtc && crtc->state->enable) {
1356                 /*
1357                  * If the CRTC is enabled, the display will be changed
1358                  * according to the new panel fitting mode.
1359                  */
1360                 intel_crtc_restore_mode(crtc);
1361         }
1362
1363         return 0;
1364 }
1365
1366 static void intel_dsi_connector_destroy(struct drm_connector *connector)
1367 {
1368         struct intel_connector *intel_connector = to_intel_connector(connector);
1369
1370         DRM_DEBUG_KMS("\n");
1371         intel_panel_fini(&intel_connector->panel);
1372         drm_connector_cleanup(connector);
1373         kfree(connector);
1374 }
1375
1376 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1377 {
1378         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1379
1380         if (intel_dsi->panel) {
1381                 drm_panel_detach(intel_dsi->panel);
1382                 /* XXX: Logically this call belongs in the panel driver. */
1383                 drm_panel_remove(intel_dsi->panel);
1384         }
1385
1386         /* dispose of the gpios */
1387         if (intel_dsi->gpio_panel)
1388                 gpiod_put(intel_dsi->gpio_panel);
1389
1390         intel_encoder_destroy(encoder);
1391 }
1392
1393 static const struct drm_encoder_funcs intel_dsi_funcs = {
1394         .destroy = intel_dsi_encoder_destroy,
1395 };
1396
1397 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1398         .get_modes = intel_dsi_get_modes,
1399         .mode_valid = intel_dsi_mode_valid,
1400 };
1401
1402 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1403         .dpms = drm_atomic_helper_connector_dpms,
1404         .late_register = intel_connector_register,
1405         .early_unregister = intel_connector_unregister,
1406         .destroy = intel_dsi_connector_destroy,
1407         .fill_modes = drm_helper_probe_single_connector_modes,
1408         .set_property = intel_dsi_set_property,
1409         .atomic_get_property = intel_connector_atomic_get_property,
1410         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1411         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1412 };
1413
1414 static void intel_dsi_add_properties(struct intel_connector *connector)
1415 {
1416         struct drm_device *dev = connector->base.dev;
1417
1418         if (connector->panel.fixed_mode) {
1419                 drm_mode_create_scaling_mode_property(dev);
1420                 drm_object_attach_property(&connector->base.base,
1421                                            dev->mode_config.scaling_mode_property,
1422                                            DRM_MODE_SCALE_ASPECT);
1423                 connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
1424         }
1425 }
1426
1427 void intel_dsi_init(struct drm_device *dev)
1428 {
1429         struct intel_dsi *intel_dsi;
1430         struct intel_encoder *intel_encoder;
1431         struct drm_encoder *encoder;
1432         struct intel_connector *intel_connector;
1433         struct drm_connector *connector;
1434         struct drm_display_mode *scan, *fixed_mode = NULL;
1435         struct drm_i915_private *dev_priv = to_i915(dev);
1436         enum port port;
1437         unsigned int i;
1438
1439         DRM_DEBUG_KMS("\n");
1440
1441         /* There is no detection method for MIPI so rely on VBT */
1442         if (!intel_bios_is_dsi_present(dev_priv, &port))
1443                 return;
1444
1445         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1446                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1447         } else if (IS_BROXTON(dev_priv)) {
1448                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1449         } else {
1450                 DRM_ERROR("Unsupported Mipi device to reg base");
1451                 return;
1452         }
1453
1454         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1455         if (!intel_dsi)
1456                 return;
1457
1458         intel_connector = intel_connector_alloc();
1459         if (!intel_connector) {
1460                 kfree(intel_dsi);
1461                 return;
1462         }
1463
1464         intel_encoder = &intel_dsi->base;
1465         encoder = &intel_encoder->base;
1466         intel_dsi->attached_connector = intel_connector;
1467
1468         connector = &intel_connector->base;
1469
1470         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1471                          "DSI %c", port_name(port));
1472
1473         intel_encoder->compute_config = intel_dsi_compute_config;
1474         intel_encoder->pre_enable = intel_dsi_pre_enable;
1475         intel_encoder->enable = intel_dsi_enable_nop;
1476         intel_encoder->disable = intel_dsi_pre_disable;
1477         intel_encoder->post_disable = intel_dsi_post_disable;
1478         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1479         intel_encoder->get_config = intel_dsi_get_config;
1480
1481         intel_connector->get_hw_state = intel_connector_get_hw_state;
1482
1483         intel_encoder->port = port;
1484         /*
1485          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1486          * port C. BXT isn't limited like this.
1487          */
1488         if (IS_BROXTON(dev_priv))
1489                 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1490         else if (port == PORT_A)
1491                 intel_encoder->crtc_mask = BIT(PIPE_A);
1492         else
1493                 intel_encoder->crtc_mask = BIT(PIPE_B);
1494
1495         if (dev_priv->vbt.dsi.config->dual_link) {
1496                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1497
1498                 switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
1499                 case DL_DCS_PORT_A:
1500                         intel_dsi->dcs_backlight_ports = BIT(PORT_A);
1501                         break;
1502                 case DL_DCS_PORT_C:
1503                         intel_dsi->dcs_backlight_ports = BIT(PORT_C);
1504                         break;
1505                 default:
1506                 case DL_DCS_PORT_A_AND_C:
1507                         intel_dsi->dcs_backlight_ports = BIT(PORT_A) | BIT(PORT_C);
1508                         break;
1509                 }
1510
1511                 switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
1512                 case DL_DCS_PORT_A:
1513                         intel_dsi->dcs_cabc_ports = BIT(PORT_A);
1514                         break;
1515                 case DL_DCS_PORT_C:
1516                         intel_dsi->dcs_cabc_ports = BIT(PORT_C);
1517                         break;
1518                 default:
1519                 case DL_DCS_PORT_A_AND_C:
1520                         intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C);
1521                         break;
1522                 }
1523         } else {
1524                 intel_dsi->ports = BIT(port);
1525                 intel_dsi->dcs_backlight_ports = BIT(port);
1526                 intel_dsi->dcs_cabc_ports = BIT(port);
1527         }
1528
1529         if (!dev_priv->vbt.dsi.config->cabc_supported)
1530                 intel_dsi->dcs_cabc_ports = 0;
1531
1532         /* Create a DSI host (and a device) for each port. */
1533         for_each_dsi_port(port, intel_dsi->ports) {
1534                 struct intel_dsi_host *host;
1535
1536                 host = intel_dsi_host_init(intel_dsi, port);
1537                 if (!host)
1538                         goto err;
1539
1540                 intel_dsi->dsi_hosts[port] = host;
1541         }
1542
1543         for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) {
1544                 intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi,
1545                                                              intel_dsi_drivers[i].panel_id);
1546                 if (intel_dsi->panel)
1547                         break;
1548         }
1549
1550         if (!intel_dsi->panel) {
1551                 DRM_DEBUG_KMS("no device found\n");
1552                 goto err;
1553         }
1554
1555         /*
1556          * In case of BYT with CRC PMIC, we need to use GPIO for
1557          * Panel control.
1558          */
1559         if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
1560                 intel_dsi->gpio_panel =
1561                         gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1562
1563                 if (IS_ERR(intel_dsi->gpio_panel)) {
1564                         DRM_ERROR("Failed to own gpio for panel control\n");
1565                         intel_dsi->gpio_panel = NULL;
1566                 }
1567         }
1568
1569         intel_encoder->type = INTEL_OUTPUT_DSI;
1570         intel_encoder->cloneable = 0;
1571         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1572                            DRM_MODE_CONNECTOR_DSI);
1573
1574         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1575
1576         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1577         connector->interlace_allowed = false;
1578         connector->doublescan_allowed = false;
1579
1580         intel_connector_attach_encoder(intel_connector, intel_encoder);
1581
1582         drm_panel_attach(intel_dsi->panel, connector);
1583
1584         mutex_lock(&dev->mode_config.mutex);
1585         drm_panel_get_modes(intel_dsi->panel);
1586         list_for_each_entry(scan, &connector->probed_modes, head) {
1587                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1588                         fixed_mode = drm_mode_duplicate(dev, scan);
1589                         break;
1590                 }
1591         }
1592         mutex_unlock(&dev->mode_config.mutex);
1593
1594         if (!fixed_mode) {
1595                 DRM_DEBUG_KMS("no fixed mode\n");
1596                 goto err;
1597         }
1598
1599         connector->display_info.width_mm = fixed_mode->width_mm;
1600         connector->display_info.height_mm = fixed_mode->height_mm;
1601
1602         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1603         intel_panel_setup_backlight(connector, INVALID_PIPE);
1604
1605         intel_dsi_add_properties(intel_connector);
1606
1607         return;
1608
1609 err:
1610         drm_encoder_cleanup(&intel_encoder->base);
1611         kfree(intel_dsi);
1612         kfree(intel_connector);
1613 }