drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <drm/drm_panel.h>
  32 #include <drm/drm_mipi_dsi.h>
  33 #include <linux/slab.h>
  34 #include <linux/gpio/consumer.h>
  35 #include "i915_drv.h"
  36 #include "intel_drv.h"
  37 #include "intel_dsi.h"
  38
  39 static const struct {
  40         u16 panel_id;
  41         struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
  42 } intel_dsi_drivers[] = {
  43         {
  44                 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
  45                 .init = vbt_panel_init,
  46         },
  47 };
  48
  49 /* return pixels in terms of txbyteclkhs */
  50 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  51                        u16 burst_mode_ratio)
  52 {
  53         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  54                                          8 * 100), lane_count);
  55 }
  56
  57 /* return pixels equvalent to txbyteclkhs */
  58 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  59                         u16 burst_mode_ratio)
  60 {
  61         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  62                                                 (bpp * burst_mode_ratio));
  63 }
  64
  65 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  66 {
  67         /* It just so happens the VBT matches register contents. */
  68         switch (fmt) {
  69         case VID_MODE_FORMAT_RGB888:
  70                 return MIPI_DSI_FMT_RGB888;
  71         case VID_MODE_FORMAT_RGB666:
  72                 return MIPI_DSI_FMT_RGB666;
  73         case VID_MODE_FORMAT_RGB666_PACKED:
  74                 return MIPI_DSI_FMT_RGB666_PACKED;
  75         case VID_MODE_FORMAT_RGB565:
  76                 return MIPI_DSI_FMT_RGB565;
  77         default:
  78                 MISSING_CASE(fmt);
  79                 return MIPI_DSI_FMT_RGB666;
  80         }
  81 }
  82
  83 void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  84 {
  85         struct drm_encoder *encoder = &intel_dsi->base.base;
  86         struct drm_device *dev = encoder->dev;
  87         struct drm_i915_private *dev_priv = to_i915(dev);
  88         u32 mask;
  89
  90         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  91                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  92
  93         if (intel_wait_for_register(dev_priv,
  94                                     MIPI_GEN_FIFO_STAT(port), mask, mask,
  95                                     100))
  96                 DRM_ERROR("DPI FIFOs are not empty\n");
  97 }
  98
  99 static void write_data(struct drm_i915_private *dev_priv,
 100                        i915_reg_t reg,
 101                        const u8 *data, u32 len)
 102 {
 103         u32 i, j;
 104
 105         for (i = 0; i < len; i += 4) {
 106                 u32 val = 0;
 107
 108                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 109                         val |= *data++ << 8 * j;
 110
 111                 I915_WRITE(reg, val);
 112         }
 113 }
 114
 115 static void read_data(struct drm_i915_private *dev_priv,
 116                       i915_reg_t reg,
 117                       u8 *data, u32 len)
 118 {
 119         u32 i, j;
 120
 121         for (i = 0; i < len; i += 4) {
 122                 u32 val = I915_READ(reg);
 123
 124                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 125                         *data++ = val >> 8 * j;
 126         }
 127 }
 128
 129 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 130                                        const struct mipi_dsi_msg *msg)
 131 {
 132         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 133         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 134         struct drm_i915_private *dev_priv = to_i915(dev);
 135         enum port port = intel_dsi_host->port;
 136         struct mipi_dsi_packet packet;
 137         ssize_t ret;
 138         const u8 *header, *data;
 139         i915_reg_t data_reg, ctrl_reg;
 140         u32 data_mask, ctrl_mask;
 141
 142         ret = mipi_dsi_create_packet(&packet, msg);
 143         if (ret < 0)
 144                 return ret;
 145
 146         header = packet.header;
 147         data = packet.payload;
 148
 149         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 150                 data_reg = MIPI_LP_GEN_DATA(port);
 151                 data_mask = LP_DATA_FIFO_FULL;
 152                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 153                 ctrl_mask = LP_CTRL_FIFO_FULL;
 154         } else {
 155                 data_reg = MIPI_HS_GEN_DATA(port);
 156                 data_mask = HS_DATA_FIFO_FULL;
 157                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 158                 ctrl_mask = HS_CTRL_FIFO_FULL;
 159         }
 160
 161         /* note: this is never true for reads */
 162         if (packet.payload_length) {
 163                 if (intel_wait_for_register(dev_priv,
 164                                             MIPI_GEN_FIFO_STAT(port),
 165                                             data_mask, 0,
 166                                             50))
 167                         DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 168
 169                 write_data(dev_priv, data_reg, packet.payload,
 170                            packet.payload_length);
 171         }
 172
 173         if (msg->rx_len) {
 174                 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 175         }
 176
 177         if (intel_wait_for_register(dev_priv,
 178                                     MIPI_GEN_FIFO_STAT(port),
 179                                     ctrl_mask, 0,
 180                                     50)) {
 181                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 182         }
 183
 184         I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
 185
 186         /* ->rx_len is set only for reads */
 187         if (msg->rx_len) {
 188                 data_mask = GEN_READ_DATA_AVAIL;
 189                 if (intel_wait_for_register(dev_priv,
 190                                             MIPI_INTR_STAT(port),
 191                                             data_mask, data_mask,
 192                                             50))
 193                         DRM_ERROR("Timeout waiting for read data.\n");
 194
 195                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 196         }
 197
 198         /* XXX: fix for reads and writes */
 199         return 4 + packet.payload_length;
 200 }
 201
 202 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 203                                  struct mipi_dsi_device *dsi)
 204 {
 205         return 0;
 206 }
 207
 208 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 209                                  struct mipi_dsi_device *dsi)
 210 {
 211         return 0;
 212 }
 213
 214 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 215         .attach = intel_dsi_host_attach,
 216         .detach = intel_dsi_host_detach,
 217         .transfer = intel_dsi_host_transfer,
 218 };
 219
 220 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
 221                                                   enum port port)
 222 {
 223         struct intel_dsi_host *host;
 224         struct mipi_dsi_device *device;
 225
 226         host = kzalloc(sizeof(*host), GFP_KERNEL);
 227         if (!host)
 228                 return NULL;
 229
 230         host->base.ops = &intel_dsi_host_ops;
 231         host->intel_dsi = intel_dsi;
 232         host->port = port;
 233
 234         /*
 235          * We should call mipi_dsi_host_register(&host->base) here, but we don't
 236          * have a host->dev, and we don't have OF stuff either. So just use the
 237          * dsi framework as a library and hope for the best. Create the dsi
 238          * devices by ourselves here too. Need to be careful though, because we
 239          * don't initialize any of the driver model devices here.
 240          */
 241         device = kzalloc(sizeof(*device), GFP_KERNEL);
 242         if (!device) {
 243                 kfree(host);
 244                 return NULL;
 245         }
 246
 247         device->host = &host->base;
 248         host->device = device;
 249
 250         return host;
 251 }
 252
 253 /*
 254  * send a video mode command
 255  *
 256  * XXX: commands with data in MIPI_DPI_DATA?
 257  */
 258 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 259                         enum port port)
 260 {
 261         struct drm_encoder *encoder = &intel_dsi->base.base;
 262         struct drm_device *dev = encoder->dev;
 263         struct drm_i915_private *dev_priv = to_i915(dev);
 264         u32 mask;
 265
 266         /* XXX: pipe, hs */
 267         if (hs)
 268                 cmd &= ~DPI_LP_MODE;
 269         else
 270                 cmd |= DPI_LP_MODE;
 271
 272         /* clear bit */
 273         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 274
 275         /* XXX: old code skips write if control unchanged */
 276         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 277                 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
 278
 279         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 280
 281         mask = SPL_PKT_SENT_INTERRUPT;
 282         if (intel_wait_for_register(dev_priv,
 283                                     MIPI_INTR_STAT(port), mask, mask,
 284                                     100))
 285                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 286
 287         return 0;
 288 }
 289
 290 static void band_gap_reset(struct drm_i915_private *dev_priv)
 291 {
 292         mutex_lock(&dev_priv->sb_lock);
 293
 294         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 295         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 296         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 297         udelay(150);
 298         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 299         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 300
 301         mutex_unlock(&dev_priv->sb_lock);
 302 }
 303
 304 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
 305 {
 306         return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
 307 }
 308
 309 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
 310 {
 311         return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
 312 }
 313
 314 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 315                                      struct intel_crtc_state *pipe_config,
 316                                      struct drm_connector_state *conn_state)
 317 {
 318         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 319         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 320                                                    base);
 321         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 322         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 323         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 324         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 325         int ret;
 326
 327         DRM_DEBUG_KMS("\n");
 328
 329         if (fixed_mode) {
 330                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 331
 332                 if (HAS_GMCH_DISPLAY(dev_priv))
 333                         intel_gmch_panel_fitting(crtc, pipe_config,
 334                                                  intel_connector->panel.fitting_mode);
 335                 else
 336                         intel_pch_panel_fitting(crtc, pipe_config,
 337                                                 intel_connector->panel.fitting_mode);
 338         }
 339
 340         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 341         adjusted_mode->flags = 0;
 342
 343         if (IS_GEN9_LP(dev_priv)) {
 344                 /* Dual link goes to DSI transcoder A. */
 345                 if (intel_dsi->ports == BIT(PORT_C))
 346                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 347                 else
 348                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 349         }
 350
 351         ret = intel_compute_dsi_pll(encoder, pipe_config);
 352         if (ret)
 353                 return false;
 354
 355         pipe_config->clock_set = true;
 356
 357         return true;
 358 }
 359
 360 static void glk_dsi_device_ready(struct intel_encoder *encoder)
 361 {
 362         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 363         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 364         enum port port;
 365         u32 tmp, val;
 366
 367         /* Set the MIPI mode
 368          * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
 369          * Power ON MIPI IO first and then write into IO reset and LP wake bits
 370          */
 371         for_each_dsi_port(port, intel_dsi->ports) {
 372                 tmp = I915_READ(MIPI_CTRL(port));
 373                 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
 374         }
 375
 376         /* Put the IO into reset */
 377         tmp = I915_READ(MIPI_CTRL(PORT_A));
 378         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 379         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 380
 381         /* Program LP Wake */
 382         for_each_dsi_port(port, intel_dsi->ports) {
 383                 tmp = I915_READ(MIPI_CTRL(port));
 384                 tmp |= GLK_LP_WAKE;
 385                 I915_WRITE(MIPI_CTRL(port), tmp);
 386         }
 387
 388         /* Wait for Pwr ACK */
 389         for_each_dsi_port(port, intel_dsi->ports) {
 390                 if (intel_wait_for_register(dev_priv,
 391                                 MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
 392                                 GLK_MIPIIO_PORT_POWERED, 20))
 393                         DRM_ERROR("MIPIO port is powergated\n");
 394         }
 395
 396         /* Wait for MIPI PHY status bit to set */
 397         for_each_dsi_port(port, intel_dsi->ports) {
 398                 if (intel_wait_for_register(dev_priv,
 399                                 MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
 400                                 GLK_PHY_STATUS_PORT_READY, 20))
 401                         DRM_ERROR("PHY is not ON\n");
 402         }
 403
 404         /* Get IO out of reset */
 405         tmp = I915_READ(MIPI_CTRL(PORT_A));
 406         I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED);
 407
 408         /* Get IO out of Low power state*/
 409         for_each_dsi_port(port, intel_dsi->ports) {
 410                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
 411                         val = I915_READ(MIPI_DEVICE_READY(port));
 412                         val &= ~ULPS_STATE_MASK;
 413                         val |= DEVICE_READY;
 414                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 415                         usleep_range(10, 15);
 416                 }
 417
 418                 /* Enter ULPS */
 419                 val = I915_READ(MIPI_DEVICE_READY(port));
 420                 val &= ~ULPS_STATE_MASK;
 421                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 422                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 423
 424                 /* Wait for ULPS Not active */
 425                 if (intel_wait_for_register(dev_priv,
 426                                 MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
 427                                 GLK_ULPS_NOT_ACTIVE, 20))
 428
 429                 /* Exit ULPS */
 430                 val = I915_READ(MIPI_DEVICE_READY(port));
 431                 val &= ~ULPS_STATE_MASK;
 432                 val |= (ULPS_STATE_EXIT | DEVICE_READY);
 433                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 434
 435                 /* Enter Normal Mode */
 436                 val = I915_READ(MIPI_DEVICE_READY(port));
 437                 val &= ~ULPS_STATE_MASK;
 438                 val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
 439                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 440
 441                 tmp = I915_READ(MIPI_CTRL(port));
 442                 tmp &= ~GLK_LP_WAKE;
 443                 I915_WRITE(MIPI_CTRL(port), tmp);
 444         }
 445
 446         /* Wait for Stop state */
 447         for_each_dsi_port(port, intel_dsi->ports) {
 448                 if (intel_wait_for_register(dev_priv,
 449                                 MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
 450                                 GLK_DATA_LANE_STOP_STATE, 20))
 451                         DRM_ERROR("Date lane not in STOP state\n");
 452         }
 453
 454         /* Wait for AFE LATCH */
 455         for_each_dsi_port(port, intel_dsi->ports) {
 456                 if (intel_wait_for_register(dev_priv,
 457                                 BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
 458                                 AFE_LATCHOUT, 20))
 459                         DRM_ERROR("D-PHY not entering LP-11 state\n");
 460         }
 461 }
 462
 463 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 464 {
 465         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 466         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 467         enum port port;
 468         u32 val;
 469
 470         DRM_DEBUG_KMS("\n");
 471
 472         /* Enable MIPI PHY transparent latch */
 473         for_each_dsi_port(port, intel_dsi->ports) {
 474                 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
 475                 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
 476                 usleep_range(2000, 2500);
 477         }
 478
 479         /* Clear ULPS and set device ready */
 480         for_each_dsi_port(port, intel_dsi->ports) {
 481                 val = I915_READ(MIPI_DEVICE_READY(port));
 482                 val &= ~ULPS_STATE_MASK;
 483                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 484                 usleep_range(2000, 2500);
 485                 val |= DEVICE_READY;
 486                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 487         }
 488 }
 489
 490 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 491 {
 492         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 493         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 494         enum port port;
 495         u32 val;
 496
 497         DRM_DEBUG_KMS("\n");
 498
 499         mutex_lock(&dev_priv->sb_lock);
 500         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 501          * needed everytime after power gate */
 502         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 503         mutex_unlock(&dev_priv->sb_lock);
 504
 505         /* bandgap reset is needed after everytime we do power gate */
 506         band_gap_reset(dev_priv);
 507
 508         for_each_dsi_port(port, intel_dsi->ports) {
 509
 510                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 511                 usleep_range(2500, 3000);
 512
 513                 /* Enable MIPI PHY transparent latch
 514                  * Common bit for both MIPI Port A & MIPI Port C
 515                  * No similar bit in MIPI Port C reg
 516                  */
 517                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 518                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 519                 usleep_range(1000, 1500);
 520
 521                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 522                 usleep_range(2500, 3000);
 523
 524                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 525                 usleep_range(2500, 3000);
 526         }
 527 }
 528
 529 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 530 {
 531         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 532
 533         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 534                 vlv_dsi_device_ready(encoder);
 535         else if (IS_BROXTON(dev_priv))
 536                 bxt_dsi_device_ready(encoder);
 537         else if (IS_GEMINILAKE(dev_priv))
 538                 glk_dsi_device_ready(encoder);
 539 }
 540
 541 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 542 {
 543         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 544         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 545         enum port port;
 546         u32 val;
 547
 548         /* Enter ULPS */
 549         for_each_dsi_port(port, intel_dsi->ports) {
 550                 val = I915_READ(MIPI_DEVICE_READY(port));
 551                 val &= ~ULPS_STATE_MASK;
 552                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 553                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 554         }
 555
 556         /* Wait for MIPI PHY status bit to unset */
 557         for_each_dsi_port(port, intel_dsi->ports) {
 558                 if (intel_wait_for_register(dev_priv,
 559                                             MIPI_CTRL(port),
 560                                             GLK_PHY_STATUS_PORT_READY, 0, 20))
 561                         DRM_ERROR("PHY is not turning OFF\n");
 562         }
 563
 564         /* Wait for Pwr ACK bit to unset */
 565         for_each_dsi_port(port, intel_dsi->ports) {
 566                 if (intel_wait_for_register(dev_priv,
 567                                             MIPI_CTRL(port),
 568                                             GLK_MIPIIO_PORT_POWERED, 0, 20))
 569                         DRM_ERROR("MIPI IO Port is not powergated\n");
 570         }
 571 }
 572
 573 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
 574 {
 575         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 576         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 577         enum port port;
 578         u32 tmp;
 579
 580         /* Put the IO into reset */
 581         tmp = I915_READ(MIPI_CTRL(PORT_A));
 582         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 583         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 584
 585         /* Wait for MIPI PHY status bit to unset */
 586         for_each_dsi_port(port, intel_dsi->ports) {
 587                 if (intel_wait_for_register(dev_priv,
 588                                             MIPI_CTRL(port),
 589                                             GLK_PHY_STATUS_PORT_READY, 0, 20))
 590                         DRM_ERROR("PHY is not turning OFF\n");
 591         }
 592
 593         /* Clear MIPI mode */
 594         for_each_dsi_port(port, intel_dsi->ports) {
 595                 tmp = I915_READ(MIPI_CTRL(port));
 596                 tmp &= ~GLK_MIPIIO_ENABLE;
 597                 I915_WRITE(MIPI_CTRL(port), tmp);
 598         }
 599 }
 600
 601 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
 602 {
 603         glk_dsi_enter_low_power_mode(encoder);
 604         glk_dsi_disable_mipi_io(encoder);
 605 }
 606
 607 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 608 {
 609         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 610         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 611         enum port port;
 612
 613         DRM_DEBUG_KMS("\n");
 614         for_each_dsi_port(port, intel_dsi->ports) {
 615                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 616                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 617                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 618                 u32 val;
 619
 620                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 621                                                         ULPS_STATE_ENTER);
 622                 usleep_range(2000, 2500);
 623
 624                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 625                                                         ULPS_STATE_EXIT);
 626                 usleep_range(2000, 2500);
 627
 628                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 629                                                         ULPS_STATE_ENTER);
 630                 usleep_range(2000, 2500);
 631
 632                 /*
 633                  * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
 634                  * Port A only. MIPI Port C has no similar bit for checking.
 635                  */
 636                 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
 637                     intel_wait_for_register(dev_priv,
 638                                             port_ctrl, AFE_LATCHOUT, 0,
 639                                             30))
 640                         DRM_ERROR("DSI LP not going Low\n");
 641
 642                 /* Disable MIPI PHY transparent latch */
 643                 val = I915_READ(port_ctrl);
 644                 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
 645                 usleep_range(1000, 1500);
 646
 647                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 648                 usleep_range(2000, 2500);
 649         }
 650 }
 651
 652 static void intel_dsi_port_enable(struct intel_encoder *encoder)
 653 {
 654         struct drm_device *dev = encoder->base.dev;
 655         struct drm_i915_private *dev_priv = to_i915(dev);
 656         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 657         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 658         enum port port;
 659
 660         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 661                 u32 temp;
 662                 if (IS_GEN9_LP(dev_priv)) {
 663                         for_each_dsi_port(port, intel_dsi->ports) {
 664                                 temp = I915_READ(MIPI_CTRL(port));
 665                                 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
 666                                         intel_dsi->pixel_overlap <<
 667                                         BXT_PIXEL_OVERLAP_CNT_SHIFT;
 668                                 I915_WRITE(MIPI_CTRL(port), temp);
 669                         }
 670                 } else {
 671                         temp = I915_READ(VLV_CHICKEN_3);
 672                         temp &= ~PIXEL_OVERLAP_CNT_MASK |
 673                                         intel_dsi->pixel_overlap <<
 674                                         PIXEL_OVERLAP_CNT_SHIFT;
 675                         I915_WRITE(VLV_CHICKEN_3, temp);
 676                 }
 677         }
 678
 679         for_each_dsi_port(port, intel_dsi->ports) {
 680                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 681                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 682                 u32 temp;
 683
 684                 temp = I915_READ(port_ctrl);
 685
 686                 temp &= ~LANE_CONFIGURATION_MASK;
 687                 temp &= ~DUAL_LINK_MODE_MASK;
 688
 689                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 690                         temp |= (intel_dsi->dual_link - 1)
 691                                                 << DUAL_LINK_MODE_SHIFT;
 692                         if (IS_BROXTON(dev_priv))
 693                                 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
 694                         else
 695                                 temp |= intel_crtc->pipe ?
 696                                         LANE_CONFIGURATION_DUAL_LINK_B :
 697                                         LANE_CONFIGURATION_DUAL_LINK_A;
 698                 }
 699                 /* assert ip_tg_enable signal */
 700                 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
 701                 POSTING_READ(port_ctrl);
 702         }
 703 }
 704
 705 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 706 {
 707         struct drm_device *dev = encoder->base.dev;
 708         struct drm_i915_private *dev_priv = to_i915(dev);
 709         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 710         enum port port;
 711
 712         for_each_dsi_port(port, intel_dsi->ports) {
 713                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 714                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 715                 u32 temp;
 716
 717                 /* de-assert ip_tg_enable signal */
 718                 temp = I915_READ(port_ctrl);
 719                 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
 720                 POSTING_READ(port_ctrl);
 721         }
 722 }
 723
 724 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 725                               struct intel_crtc_state *pipe_config);
 726 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 727
 728 /*
 729  * Panel enable/disable sequences from the VBT spec.
 730  *
 731  * Note the spec has AssertReset / DeassertReset swapped from their
 732  * usual naming. We use the normal names to avoid confusion (so below
 733  * they are swapped compared to the spec).
 734  *
 735  * Steps starting with MIPI refer to VBT sequences, note that for v2
 736  * VBTs several steps which have a VBT in v2 are expected to be handled
 737  * directly by the driver, by directly driving gpios for example.
 738  *
 739  * v2 video mode seq         v3 video mode seq         command mode seq
 740  * - power on                - MIPIPanelPowerOn        - power on
 741  * - wait t1+t2                                        - wait t1+t2
 742  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
 743  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
 744  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
 745  *                                                     - MIPITearOn
 746  *                                                     - MIPIDisplayOn
 747  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
 748  * - MIPIDisplayOn           - MIPIDisplayOn
 749  * - wait t5                                           - wait t5
 750  * - backlight on            - MIPIBacklightOn         - backlight on
 751  * ...                       ...                       ... issue mem cmds ...
 752  * - backlight off           - MIPIBacklightOff        - backlight off
 753  * - wait t6                                           - wait t6
 754  * - MIPIDisplayOff
 755  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
 756  *                                                     - MIPITearOff
 757  *                           - MIPIDisplayOff          - MIPIDisplayOff
 758  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
 759  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
 760  * - wait t3                                           - wait t3
 761  * - power off               - MIPIPanelPowerOff       - power off
 762  * - wait t4                                           - wait t4
 763  */
 764
 765 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 766                                  struct intel_crtc_state *pipe_config,
 767                                  struct drm_connector_state *conn_state)
 768 {
 769         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 770         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 771         enum port port;
 772         u32 val;
 773
 774         DRM_DEBUG_KMS("\n");
 775
 776         /*
 777          * The BIOS may leave the PLL in a wonky state where it doesn't
 778          * lock. It needs to be fully powered down to fix it.
 779          */
 780         intel_disable_dsi_pll(encoder);
 781         intel_enable_dsi_pll(encoder, pipe_config);
 782
 783         if (IS_BROXTON(dev_priv)) {
 784                 /* Add MIPI IO reset programming for modeset */
 785                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 786                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 787                                         val | MIPIO_RST_CTRL);
 788
 789                 /* Power up DSI regulator */
 790                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 791                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0);
 792         }
 793
 794         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 795                 u32 val;
 796
 797                 /* Disable DPOunit clock gating, can stall pipe */
 798                 val = I915_READ(DSPCLK_GATE_D);
 799                 val |= DPOUNIT_CLOCK_GATE_DISABLE;
 800                 I915_WRITE(DSPCLK_GATE_D, val);
 801         }
 802
 803         intel_dsi_prepare(encoder, pipe_config);
 804
 805         /* Power on, try both CRC pmic gpio and VBT */
 806         if (intel_dsi->gpio_panel)
 807                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
 808         intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 809         msleep(intel_dsi->panel_on_delay);
 810
 811         /* Deassert reset */
 812         intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 813
 814         /* Put device in ready state (LP-11) */
 815         intel_dsi_device_ready(encoder);
 816
 817         /* Send initialization commands in LP mode */
 818         intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 819
 820         /* Enable port in pre-enable phase itself because as per hw team
 821          * recommendation, port should be enabled befor plane & pipe */
 822         if (is_cmd_mode(intel_dsi)) {
 823                 for_each_dsi_port(port, intel_dsi->ports)
 824                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 825                 intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
 826                 intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 827         } else {
 828                 msleep(20); /* XXX */
 829                 for_each_dsi_port(port, intel_dsi->ports)
 830                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 831                 msleep(100);
 832
 833                 intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 834
 835                 intel_dsi_port_enable(encoder);
 836         }
 837
 838         intel_panel_enable_backlight(intel_dsi->attached_connector);
 839         intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 840 }
 841
 842 static void intel_dsi_enable_nop(struct intel_encoder *encoder,
 843                                  struct intel_crtc_state *pipe_config,
 844                                  struct drm_connector_state *conn_state)
 845 {
 846         DRM_DEBUG_KMS("\n");
 847
 848         /* for DSI port enable has to be done before pipe
 849          * and plane enable, so port enable is done in
 850          * pre_enable phase itself unlike other encoders
 851          */
 852 }
 853
 854 static void intel_dsi_pre_disable(struct intel_encoder *encoder,
 855                                   struct intel_crtc_state *old_crtc_state,
 856                                   struct drm_connector_state *old_conn_state)
 857 {
 858         struct drm_device *dev = encoder->base.dev;
 859         struct drm_i915_private *dev_priv = dev->dev_private;
 860         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 861         enum port port;
 862
 863         DRM_DEBUG_KMS("\n");
 864
 865         intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
 866         intel_panel_disable_backlight(intel_dsi->attached_connector);
 867
 868         /*
 869          * Disable Device ready before the port shutdown in order
 870          * to avoid split screen
 871          */
 872         if (IS_BROXTON(dev_priv)) {
 873                 for_each_dsi_port(port, intel_dsi->ports)
 874                         I915_WRITE(MIPI_DEVICE_READY(port), 0);
 875         }
 876
 877         /*
 878          * According to the spec we should send SHUTDOWN before
 879          * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
 880          * has shown that the v3 sequence works for v2 VBTs too
 881          */
 882         if (is_vid_mode(intel_dsi)) {
 883                 /* Send Shutdown command to the panel in LP mode */
 884                 for_each_dsi_port(port, intel_dsi->ports)
 885                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 886                 msleep(10);
 887         }
 888 }
 889
 890 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 891 {
 892         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 893
 894         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
 895             IS_BROXTON(dev_priv))
 896                 vlv_dsi_clear_device_ready(encoder);
 897         else if (IS_GEMINILAKE(dev_priv))
 898                 glk_dsi_clear_device_ready(encoder);
 899 }
 900
 901 static void intel_dsi_post_disable(struct intel_encoder *encoder,
 902                                    struct intel_crtc_state *pipe_config,
 903                                    struct drm_connector_state *conn_state)
 904 {
 905         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 906         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 907         enum port port;
 908         u32 val;
 909
 910         DRM_DEBUG_KMS("\n");
 911
 912         if (is_vid_mode(intel_dsi)) {
 913                 for_each_dsi_port(port, intel_dsi->ports)
 914                         wait_for_dsi_fifo_empty(intel_dsi, port);
 915
 916                 intel_dsi_port_disable(encoder);
 917                 usleep_range(2000, 5000);
 918         }
 919
 920         intel_dsi_unprepare(encoder);
 921
 922         /*
 923          * if disable packets are sent before sending shutdown packet then in
 924          * some next enable sequence send turn on packet error is observed
 925          */
 926         if (is_cmd_mode(intel_dsi))
 927                 intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
 928         intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 929
 930         /* Transition to LP-00 */
 931         intel_dsi_clear_device_ready(encoder);
 932
 933         if (IS_BROXTON(dev_priv)) {
 934                 /* Power down DSI regulator to save power */
 935                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 936                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT);
 937
 938                 /* Add MIPI IO reset programming for modeset */
 939                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 940                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 941                                 val & ~MIPIO_RST_CTRL);
 942         }
 943
 944         intel_disable_dsi_pll(encoder);
 945
 946         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 947                 u32 val;
 948
 949                 val = I915_READ(DSPCLK_GATE_D);
 950                 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 951                 I915_WRITE(DSPCLK_GATE_D, val);
 952         }
 953
 954         /* Assert reset */
 955         intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
 956
 957         /* Power off, try both CRC pmic gpio and VBT */
 958         msleep(intel_dsi->panel_off_delay);
 959         intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
 960         if (intel_dsi->gpio_panel)
 961                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
 962
 963         /*
 964          * FIXME As we do with eDP, just make a note of the time here
 965          * and perform the wait before the next panel power on.
 966          */
 967         msleep(intel_dsi->panel_pwr_cycle_delay);
 968 }
 969
 970 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 971                                    enum pipe *pipe)
 972 {
 973         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 974         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 975         enum port port;
 976         bool active = false;
 977
 978         DRM_DEBUG_KMS("\n");
 979
 980         if (!intel_display_power_get_if_enabled(dev_priv,
 981                                                 encoder->power_domain))
 982                 return false;
 983
 984         /*
 985          * On Broxton the PLL needs to be enabled with a valid divider
 986          * configuration, otherwise accessing DSI registers will hang the
 987          * machine. See BSpec North Display Engine registers/MIPI[BXT].
 988          */
 989         if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
 990                 goto out_put_power;
 991
 992         /* XXX: this only works for one DSI output */
 993         for_each_dsi_port(port, intel_dsi->ports) {
 994                 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
 995                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 996                 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
 997
 998                 /*
 999                  * Due to some hardware limitations on VLV/CHV, the DPI enable
1000                  * bit in port C control register does not get set. As a
1001                  * workaround, check pipe B conf instead.
1002                  */
1003                 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1004                     port == PORT_C)
1005                         enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1006
1007                 /* Try command mode if video mode not enabled */
1008                 if (!enabled) {
1009                         u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
1010                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
1011                 }
1012
1013                 if (!enabled)
1014                         continue;
1015
1016                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
1017                         continue;
1018
1019                 if (IS_GEN9_LP(dev_priv)) {
1020                         u32 tmp = I915_READ(MIPI_CTRL(port));
1021                         tmp &= BXT_PIPE_SELECT_MASK;
1022                         tmp >>= BXT_PIPE_SELECT_SHIFT;
1023
1024                         if (WARN_ON(tmp > PIPE_C))
1025                                 continue;
1026
1027                         *pipe = tmp;
1028                 } else {
1029                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1030                 }
1031
1032                 active = true;
1033                 break;
1034         }
1035
1036 out_put_power:
1037         intel_display_power_put(dev_priv, encoder->power_domain);
1038
1039         return active;
1040 }
1041
1042 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1043                                  struct intel_crtc_state *pipe_config)
1044 {
1045         struct drm_device *dev = encoder->base.dev;
1046         struct drm_i915_private *dev_priv = to_i915(dev);
1047         struct drm_display_mode *adjusted_mode =
1048                                         &pipe_config->base.adjusted_mode;
1049         struct drm_display_mode *adjusted_mode_sw;
1050         struct intel_crtc *intel_crtc;
1051         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1052         unsigned int lane_count = intel_dsi->lane_count;
1053         unsigned int bpp, fmt;
1054         enum port port;
1055         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1056         u16 hfp_sw, hsync_sw, hbp_sw;
1057         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1058                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
1059
1060         /* FIXME: hw readout should not depend on SW state */
1061         intel_crtc = to_intel_crtc(encoder->base.crtc);
1062         adjusted_mode_sw = &intel_crtc->config->base.adjusted_mode;
1063
1064         /*
1065          * Atleast one port is active as encoder->get_config called only if
1066          * encoder->get_hw_state() returns true.
1067          */
1068         for_each_dsi_port(port, intel_dsi->ports) {
1069                 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1070                         break;
1071         }
1072
1073         fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1074         pipe_config->pipe_bpp =
1075                         mipi_dsi_pixel_format_to_bpp(
1076                                 pixel_format_from_register_bits(fmt));
1077         bpp = pipe_config->pipe_bpp;
1078
1079         /* In terms of pixels */
1080         adjusted_mode->crtc_hdisplay =
1081                                 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
1082         adjusted_mode->crtc_vdisplay =
1083                                 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
1084         adjusted_mode->crtc_vtotal =
1085                                 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
1086
1087         hactive = adjusted_mode->crtc_hdisplay;
1088         hfp = I915_READ(MIPI_HFP_COUNT(port));
1089
1090         /*
1091          * Meaningful for video mode non-burst sync pulse mode only,
1092          * can be zero for non-burst sync events and burst modes
1093          */
1094         hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
1095         hbp = I915_READ(MIPI_HBP_COUNT(port));
1096
1097         /* harizontal values are in terms of high speed byte clock */
1098         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1099                                                 intel_dsi->burst_mode_ratio);
1100         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1101                                                 intel_dsi->burst_mode_ratio);
1102         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1103                                                 intel_dsi->burst_mode_ratio);
1104
1105         if (intel_dsi->dual_link) {
1106                 hfp *= 2;
1107                 hsync *= 2;
1108                 hbp *= 2;
1109         }
1110
1111         /* vertical values are in terms of lines */
1112         vfp = I915_READ(MIPI_VFP_COUNT(port));
1113         vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
1114         vbp = I915_READ(MIPI_VBP_COUNT(port));
1115
1116         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1117         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1118         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1119         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1120         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1121
1122         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1123         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1124         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1125         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1126
1127         /*
1128          * In BXT DSI there is no regs programmed with few horizontal timings
1129          * in Pixels but txbyteclkhs.. So retrieval process adds some
1130          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1131          * Actually here for the given adjusted_mode, we are calculating the
1132          * value programmed to the port and then back to the horizontal timing
1133          * param in pixels. This is the expected value, including roundup errors
1134          * And if that is same as retrieved value from port, then
1135          * (HW state) adjusted_mode's horizontal timings are corrected to
1136          * match with SW state to nullify the errors.
1137          */
1138         /* Calculating the value programmed to the Port register */
1139         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1140                                         adjusted_mode_sw->crtc_hdisplay;
1141         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1142                                         adjusted_mode_sw->crtc_hsync_start;
1143         hbp_sw = adjusted_mode_sw->crtc_htotal -
1144                                         adjusted_mode_sw->crtc_hsync_end;
1145
1146         if (intel_dsi->dual_link) {
1147                 hfp_sw /= 2;
1148                 hsync_sw /= 2;
1149                 hbp_sw /= 2;
1150         }
1151
1152         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1153                                                 intel_dsi->burst_mode_ratio);
1154         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1155                             intel_dsi->burst_mode_ratio);
1156         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1157                                                 intel_dsi->burst_mode_ratio);
1158
1159         /* Reverse calculating the adjusted mode parameters from port reg vals*/
1160         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1161                                                 intel_dsi->burst_mode_ratio);
1162         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1163                                                 intel_dsi->burst_mode_ratio);
1164         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1165                                                 intel_dsi->burst_mode_ratio);
1166
1167         if (intel_dsi->dual_link) {
1168                 hfp_sw *= 2;
1169                 hsync_sw *= 2;
1170                 hbp_sw *= 2;
1171         }
1172
1173         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1174                                                         hsync_sw + hbp_sw;
1175         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1176         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1177         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1178         crtc_hblank_end_sw = crtc_htotal_sw;
1179
1180         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1181                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1182
1183         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1184                 adjusted_mode->crtc_hsync_start =
1185                                         adjusted_mode_sw->crtc_hsync_start;
1186
1187         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1188                 adjusted_mode->crtc_hsync_end =
1189                                         adjusted_mode_sw->crtc_hsync_end;
1190
1191         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1192                 adjusted_mode->crtc_hblank_start =
1193                                         adjusted_mode_sw->crtc_hblank_start;
1194
1195         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1196                 adjusted_mode->crtc_hblank_end =
1197                                         adjusted_mode_sw->crtc_hblank_end;
1198 }
1199
1200 static void intel_dsi_get_config(struct intel_encoder *encoder,
1201                                  struct intel_crtc_state *pipe_config)
1202 {
1203         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1204         u32 pclk;
1205         DRM_DEBUG_KMS("\n");
1206
1207         if (IS_GEN9_LP(dev_priv))
1208                 bxt_dsi_get_pipe_config(encoder, pipe_config);
1209
1210         pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
1211                                   pipe_config);
1212         if (!pclk)
1213                 return;
1214
1215         pipe_config->base.adjusted_mode.crtc_clock = pclk;
1216         pipe_config->port_clock = pclk;
1217 }
1218
1219 static enum drm_mode_status
1220 intel_dsi_mode_valid(struct drm_connector *connector,
1221                      struct drm_display_mode *mode)
1222 {
1223         struct intel_connector *intel_connector = to_intel_connector(connector);
1224         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
1225         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1226
1227         DRM_DEBUG_KMS("\n");
1228
1229         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
1230                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
1231                 return MODE_NO_DBLESCAN;
1232         }
1233
1234         if (fixed_mode) {
1235                 if (mode->hdisplay > fixed_mode->hdisplay)
1236                         return MODE_PANEL;
1237                 if (mode->vdisplay > fixed_mode->vdisplay)
1238                         return MODE_PANEL;
1239                 if (fixed_mode->clock > max_dotclk)
1240                         return MODE_CLOCK_HIGH;
1241         }
1242
1243         return MODE_OK;
1244 }
1245
1246 /* return txclkesc cycles in terms of divider and duration in us */
1247 static u16 txclkesc(u32 divider, unsigned int us)
1248 {
1249         switch (divider) {
1250         case ESCAPE_CLOCK_DIVIDER_1:
1251         default:
1252                 return 20 * us;
1253         case ESCAPE_CLOCK_DIVIDER_2:
1254                 return 10 * us;
1255         case ESCAPE_CLOCK_DIVIDER_4:
1256                 return 5 * us;
1257         }
1258 }
1259
1260 static void set_dsi_timings(struct drm_encoder *encoder,
1261                             const struct drm_display_mode *adjusted_mode)
1262 {
1263         struct drm_device *dev = encoder->dev;
1264         struct drm_i915_private *dev_priv = to_i915(dev);
1265         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1266         enum port port;
1267         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1268         unsigned int lane_count = intel_dsi->lane_count;
1269
1270         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1271
1272         hactive = adjusted_mode->crtc_hdisplay;
1273         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1274         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1275         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1276
1277         if (intel_dsi->dual_link) {
1278                 hactive /= 2;
1279                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1280                         hactive += intel_dsi->pixel_overlap;
1281                 hfp /= 2;
1282                 hsync /= 2;
1283                 hbp /= 2;
1284         }
1285
1286         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1287         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1288         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1289
1290         /* horizontal values are in terms of high speed byte clock */
1291         hactive = txbyteclkhs(hactive, bpp, lane_count,
1292                               intel_dsi->burst_mode_ratio);
1293         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1294         hsync = txbyteclkhs(hsync, bpp, lane_count,
1295                             intel_dsi->burst_mode_ratio);
1296         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1297
1298         for_each_dsi_port(port, intel_dsi->ports) {
1299                 if (IS_GEN9_LP(dev_priv)) {
1300                         /*
1301                          * Program hdisplay and vdisplay on MIPI transcoder.
1302                          * This is different from calculated hactive and
1303                          * vactive, as they are calculated per channel basis,
1304                          * whereas these values should be based on resolution.
1305                          */
1306                         I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1307                                    adjusted_mode->crtc_hdisplay);
1308                         I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1309                                    adjusted_mode->crtc_vdisplay);
1310                         I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1311                                    adjusted_mode->crtc_vtotal);
1312                 }
1313
1314                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1315                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
1316
1317                 /* meaningful for video mode non-burst sync pulse mode only,
1318                  * can be zero for non-burst sync events and burst modes */
1319                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1320                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
1321
1322                 /* vertical values are in terms of lines */
1323                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1324                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1325                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1326         }
1327 }
1328
1329 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1330 {
1331         switch (fmt) {
1332         case MIPI_DSI_FMT_RGB888:
1333                 return VID_MODE_FORMAT_RGB888;
1334         case MIPI_DSI_FMT_RGB666:
1335                 return VID_MODE_FORMAT_RGB666;
1336         case MIPI_DSI_FMT_RGB666_PACKED:
1337                 return VID_MODE_FORMAT_RGB666_PACKED;
1338         case MIPI_DSI_FMT_RGB565:
1339                 return VID_MODE_FORMAT_RGB565;
1340         default:
1341                 MISSING_CASE(fmt);
1342                 return VID_MODE_FORMAT_RGB666;
1343         }
1344 }
1345
1346 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1347                               struct intel_crtc_state *pipe_config)
1348 {
1349         struct drm_encoder *encoder = &intel_encoder->base;
1350         struct drm_device *dev = encoder->dev;
1351         struct drm_i915_private *dev_priv = to_i915(dev);
1352         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1353         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1354         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1355         enum port port;
1356         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1357         u32 val, tmp;
1358         u16 mode_hdisplay;
1359
1360         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
1361
1362         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1363
1364         if (intel_dsi->dual_link) {
1365                 mode_hdisplay /= 2;
1366                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1367                         mode_hdisplay += intel_dsi->pixel_overlap;
1368         }
1369
1370         for_each_dsi_port(port, intel_dsi->ports) {
1371                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1372                         /*
1373                          * escape clock divider, 20MHz, shared for A and C.
1374                          * device ready must be off when doing this! txclkesc?
1375                          */
1376                         tmp = I915_READ(MIPI_CTRL(PORT_A));
1377                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1378                         I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1379                                         ESCAPE_CLOCK_DIVIDER_1);
1380
1381                         /* read request priority is per pipe */
1382                         tmp = I915_READ(MIPI_CTRL(port));
1383                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1384                         I915_WRITE(MIPI_CTRL(port), tmp |
1385                                         READ_REQUEST_PRIORITY_HIGH);
1386                 } else if (IS_GEN9_LP(dev_priv)) {
1387                         enum pipe pipe = intel_crtc->pipe;
1388
1389                         tmp = I915_READ(MIPI_CTRL(port));
1390                         tmp &= ~BXT_PIPE_SELECT_MASK;
1391
1392                         tmp |= BXT_PIPE_SELECT(pipe);
1393                         I915_WRITE(MIPI_CTRL(port), tmp);
1394                 }
1395
1396                 /* XXX: why here, why like this? handling in irq handler?! */
1397                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1398                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1399
1400                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1401
1402                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
1403                         adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
1404                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1405         }
1406
1407         set_dsi_timings(encoder, adjusted_mode);
1408
1409         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1410         if (is_cmd_mode(intel_dsi)) {
1411                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1412                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1413         } else {
1414                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1415                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1416         }
1417
1418         tmp = 0;
1419         if (intel_dsi->eotp_pkt == 0)
1420                 tmp |= EOT_DISABLE;
1421         if (intel_dsi->clock_stop)
1422                 tmp |= CLOCKSTOP;
1423
1424         if (IS_GEN9_LP(dev_priv)) {
1425                 tmp |= BXT_DPHY_DEFEATURE_EN;
1426                 if (!is_cmd_mode(intel_dsi))
1427                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1428         }
1429
1430         for_each_dsi_port(port, intel_dsi->ports) {
1431                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1432
1433                 /* timeouts for recovery. one frame IIUC. if counter expires,
1434                  * EOT and stop state. */
1435
1436                 /*
1437                  * In burst mode, value greater than one DPI line Time in byte
1438                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1439                  * said value is recommended.
1440                  *
1441                  * In non-burst mode, Value greater than one DPI frame time in
1442                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1443                  * said value is recommended.
1444                  *
1445                  * In DBI only mode, value greater than one DBI frame time in
1446                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1447                  * said value is recommended.
1448                  */
1449
1450                 if (is_vid_mode(intel_dsi) &&
1451                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1452                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1453                                 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
1454                                             intel_dsi->lane_count,
1455                                             intel_dsi->burst_mode_ratio) + 1);
1456                 } else {
1457                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1458                                 txbyteclkhs(adjusted_mode->crtc_vtotal *
1459                                             adjusted_mode->crtc_htotal,
1460                                             bpp, intel_dsi->lane_count,
1461                                             intel_dsi->burst_mode_ratio) + 1);
1462                 }
1463                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1464                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1465                                                 intel_dsi->turn_arnd_val);
1466                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1467                                                 intel_dsi->rst_timer_val);
1468
1469                 /* dphy stuff */
1470
1471                 /* in terms of low power clock */
1472                 I915_WRITE(MIPI_INIT_COUNT(port),
1473                                 txclkesc(intel_dsi->escape_clk_div, 100));
1474
1475                 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
1476                         /*
1477                          * BXT spec says write MIPI_INIT_COUNT for
1478                          * both the ports, even if only one is
1479                          * getting used. So write the other port
1480                          * if not in dual link mode.
1481                          */
1482                         I915_WRITE(MIPI_INIT_COUNT(port ==
1483                                                 PORT_A ? PORT_C : PORT_A),
1484                                         intel_dsi->init_count);
1485                 }
1486
1487                 /* recovery disables */
1488                 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1489
1490                 /* in terms of low power clock */
1491                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1492
1493                 /* in terms of txbyteclkhs. actual high to low switch +
1494                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1495                  *
1496                  * XXX: write MIPI_STOP_STATE_STALL?
1497                  */
1498                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1499                                                 intel_dsi->hs_to_lp_count);
1500
1501                 /* XXX: low power clock equivalence in terms of byte clock.
1502                  * the number of byte clocks occupied in one low power clock.
1503                  * based on txbyteclkhs and txclkesc.
1504                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1505                  * ) / 105.???
1506                  */
1507                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1508
1509                 if (IS_GEMINILAKE(dev_priv)) {
1510                         I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
1511                                         intel_dsi->lp_byte_clk);
1512                         /* Shadow of DPHY reg */
1513                         I915_WRITE(MIPI_CLK_LANE_TIMING(port),
1514                                         intel_dsi->dphy_reg);
1515                 }
1516
1517                 /* the bw essential for transmitting 16 long packets containing
1518                  * 252 bytes meant for dcs write memory command is programmed in
1519                  * this register in terms of byte clocks. based on dsi transfer
1520                  * rate and the number of lanes configured the time taken to
1521                  * transmit 16 long packets in a dsi stream varies. */
1522                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1523
1524                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1525                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1526                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1527
1528                 if (is_vid_mode(intel_dsi))
1529                         /* Some panels might have resolution which is not a
1530                          * multiple of 64 like 1366 x 768. Enable RANDOM
1531                          * resolution support for such panels by default */
1532                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1533                                 intel_dsi->video_frmt_cfg_bits |
1534                                 intel_dsi->video_mode_format |
1535                                 IP_TG_CONFIG |
1536                                 RANDOM_DPI_DISPLAY_RESOLUTION);
1537         }
1538 }
1539
1540 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1541 {
1542         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1543         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1544         enum port port;
1545         u32 val;
1546
1547         if (!IS_GEMINILAKE(dev_priv)) {
1548                 for_each_dsi_port(port, intel_dsi->ports) {
1549                         /* Panel commands can be sent when clock is in LP11 */
1550                         I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
1551
1552                         intel_dsi_reset_clocks(encoder, port);
1553                         I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
1554
1555                         val = I915_READ(MIPI_DSI_FUNC_PRG(port));
1556                         val &= ~VID_MODE_FORMAT_MASK;
1557                         I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1558
1559                         I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
1560                 }
1561         }
1562 }
1563
1564 static int intel_dsi_get_modes(struct drm_connector *connector)
1565 {
1566         struct intel_connector *intel_connector = to_intel_connector(connector);
1567         struct drm_display_mode *mode;
1568
1569         DRM_DEBUG_KMS("\n");
1570
1571         if (!intel_connector->panel.fixed_mode) {
1572                 DRM_DEBUG_KMS("no fixed mode\n");
1573                 return 0;
1574         }
1575
1576         mode = drm_mode_duplicate(connector->dev,
1577                                   intel_connector->panel.fixed_mode);
1578         if (!mode) {
1579                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1580                 return 0;
1581         }
1582
1583         drm_mode_probed_add(connector, mode);
1584         return 1;
1585 }
1586
1587 static int intel_dsi_set_property(struct drm_connector *connector,
1588                                   struct drm_property *property,
1589                                   uint64_t val)
1590 {
1591         struct drm_device *dev = connector->dev;
1592         struct intel_connector *intel_connector = to_intel_connector(connector);
1593         struct drm_crtc *crtc;
1594         int ret;
1595
1596         ret = drm_object_property_set_value(&connector->base, property, val);
1597         if (ret)
1598                 return ret;
1599
1600         if (property == dev->mode_config.scaling_mode_property) {
1601                 if (val == DRM_MODE_SCALE_NONE) {
1602                         DRM_DEBUG_KMS("no scaling not supported\n");
1603                         return -EINVAL;
1604                 }
1605                 if (HAS_GMCH_DISPLAY(to_i915(dev)) &&
1606                     val == DRM_MODE_SCALE_CENTER) {
1607                         DRM_DEBUG_KMS("centering not supported\n");
1608                         return -EINVAL;
1609                 }
1610
1611                 if (intel_connector->panel.fitting_mode == val)
1612                         return 0;
1613
1614                 intel_connector->panel.fitting_mode = val;
1615         }
1616
1617         crtc = connector->state->crtc;
1618         if (crtc && crtc->state->enable) {
1619                 /*
1620                  * If the CRTC is enabled, the display will be changed
1621                  * according to the new panel fitting mode.
1622                  */
1623                 intel_crtc_restore_mode(crtc);
1624         }
1625
1626         return 0;
1627 }
1628
1629 static void intel_dsi_connector_destroy(struct drm_connector *connector)
1630 {
1631         struct intel_connector *intel_connector = to_intel_connector(connector);
1632
1633         DRM_DEBUG_KMS("\n");
1634         intel_panel_fini(&intel_connector->panel);
1635         drm_connector_cleanup(connector);
1636         kfree(connector);
1637 }
1638
1639 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1640 {
1641         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1642
1643         if (intel_dsi->panel) {
1644                 drm_panel_detach(intel_dsi->panel);
1645                 /* XXX: Logically this call belongs in the panel driver. */
1646                 drm_panel_remove(intel_dsi->panel);
1647         }
1648
1649         /* dispose of the gpios */
1650         if (intel_dsi->gpio_panel)
1651                 gpiod_put(intel_dsi->gpio_panel);
1652
1653         intel_encoder_destroy(encoder);
1654 }
1655
1656 static const struct drm_encoder_funcs intel_dsi_funcs = {
1657         .destroy = intel_dsi_encoder_destroy,
1658 };
1659
1660 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1661         .get_modes = intel_dsi_get_modes,
1662         .mode_valid = intel_dsi_mode_valid,
1663 };
1664
1665 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1666         .dpms = drm_atomic_helper_connector_dpms,
1667         .late_register = intel_connector_register,
1668         .early_unregister = intel_connector_unregister,
1669         .destroy = intel_dsi_connector_destroy,
1670         .fill_modes = drm_helper_probe_single_connector_modes,
1671         .set_property = intel_dsi_set_property,
1672         .atomic_get_property = intel_connector_atomic_get_property,
1673         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1674         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1675 };
1676
1677 static void intel_dsi_add_properties(struct intel_connector *connector)
1678 {
1679         struct drm_device *dev = connector->base.dev;
1680
1681         if (connector->panel.fixed_mode) {
1682                 drm_mode_create_scaling_mode_property(dev);
1683                 drm_object_attach_property(&connector->base.base,
1684                                            dev->mode_config.scaling_mode_property,
1685                                            DRM_MODE_SCALE_ASPECT);
1686                 connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
1687         }
1688 }
1689
1690 void intel_dsi_init(struct drm_i915_private *dev_priv)
1691 {
1692         struct drm_device *dev = &dev_priv->drm;
1693         struct intel_dsi *intel_dsi;
1694         struct intel_encoder *intel_encoder;
1695         struct drm_encoder *encoder;
1696         struct intel_connector *intel_connector;
1697         struct drm_connector *connector;
1698         struct drm_display_mode *scan, *fixed_mode = NULL;
1699         enum port port;
1700         unsigned int i;
1701
1702         DRM_DEBUG_KMS("\n");
1703
1704         /* There is no detection method for MIPI so rely on VBT */
1705         if (!intel_bios_is_dsi_present(dev_priv, &port))
1706                 return;
1707
1708         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1709                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1710         } else if (IS_GEN9_LP(dev_priv)) {
1711                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1712         } else {
1713                 DRM_ERROR("Unsupported Mipi device to reg base");
1714                 return;
1715         }
1716
1717         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1718         if (!intel_dsi)
1719                 return;
1720
1721         intel_connector = intel_connector_alloc();
1722         if (!intel_connector) {
1723                 kfree(intel_dsi);
1724                 return;
1725         }
1726
1727         intel_encoder = &intel_dsi->base;
1728         encoder = &intel_encoder->base;
1729         intel_dsi->attached_connector = intel_connector;
1730
1731         connector = &intel_connector->base;
1732
1733         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1734                          "DSI %c", port_name(port));
1735
1736         intel_encoder->compute_config = intel_dsi_compute_config;
1737         intel_encoder->pre_enable = intel_dsi_pre_enable;
1738         intel_encoder->enable = intel_dsi_enable_nop;
1739         intel_encoder->disable = intel_dsi_pre_disable;
1740         intel_encoder->post_disable = intel_dsi_post_disable;
1741         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1742         intel_encoder->get_config = intel_dsi_get_config;
1743
1744         intel_connector->get_hw_state = intel_connector_get_hw_state;
1745
1746         intel_encoder->port = port;
1747
1748         /*
1749          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1750          * port C. BXT isn't limited like this.
1751          */
1752         if (IS_GEN9_LP(dev_priv))
1753                 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1754         else if (port == PORT_A)
1755                 intel_encoder->crtc_mask = BIT(PIPE_A);
1756         else
1757                 intel_encoder->crtc_mask = BIT(PIPE_B);
1758
1759         if (dev_priv->vbt.dsi.config->dual_link) {
1760                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1761
1762                 switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
1763                 case DL_DCS_PORT_A:
1764                         intel_dsi->dcs_backlight_ports = BIT(PORT_A);
1765                         break;
1766                 case DL_DCS_PORT_C:
1767                         intel_dsi->dcs_backlight_ports = BIT(PORT_C);
1768                         break;
1769                 default:
1770                 case DL_DCS_PORT_A_AND_C:
1771                         intel_dsi->dcs_backlight_ports = BIT(PORT_A) | BIT(PORT_C);
1772                         break;
1773                 }
1774
1775                 switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
1776                 case DL_DCS_PORT_A:
1777                         intel_dsi->dcs_cabc_ports = BIT(PORT_A);
1778                         break;
1779                 case DL_DCS_PORT_C:
1780                         intel_dsi->dcs_cabc_ports = BIT(PORT_C);
1781                         break;
1782                 default:
1783                 case DL_DCS_PORT_A_AND_C:
1784                         intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C);
1785                         break;
1786                 }
1787         } else {
1788                 intel_dsi->ports = BIT(port);
1789                 intel_dsi->dcs_backlight_ports = BIT(port);
1790                 intel_dsi->dcs_cabc_ports = BIT(port);
1791         }
1792
1793         if (!dev_priv->vbt.dsi.config->cabc_supported)
1794                 intel_dsi->dcs_cabc_ports = 0;
1795
1796         /* Create a DSI host (and a device) for each port. */
1797         for_each_dsi_port(port, intel_dsi->ports) {
1798                 struct intel_dsi_host *host;
1799
1800                 host = intel_dsi_host_init(intel_dsi, port);
1801                 if (!host)
1802                         goto err;
1803
1804                 intel_dsi->dsi_hosts[port] = host;
1805         }
1806
1807         for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) {
1808                 intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi,
1809                                                              intel_dsi_drivers[i].panel_id);
1810                 if (intel_dsi->panel)
1811                         break;
1812         }
1813
1814         if (!intel_dsi->panel) {
1815                 DRM_DEBUG_KMS("no device found\n");
1816                 goto err;
1817         }
1818
1819         /*
1820          * In case of BYT with CRC PMIC, we need to use GPIO for
1821          * Panel control.
1822          */
1823         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1824             (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) {
1825                 intel_dsi->gpio_panel =
1826                         gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1827
1828                 if (IS_ERR(intel_dsi->gpio_panel)) {
1829                         DRM_ERROR("Failed to own gpio for panel control\n");
1830                         intel_dsi->gpio_panel = NULL;
1831                 }
1832         }
1833
1834         intel_encoder->type = INTEL_OUTPUT_DSI;
1835         intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1836         intel_encoder->cloneable = 0;
1837         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1838                            DRM_MODE_CONNECTOR_DSI);
1839
1840         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1841
1842         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1843         connector->interlace_allowed = false;
1844         connector->doublescan_allowed = false;
1845
1846         intel_connector_attach_encoder(intel_connector, intel_encoder);
1847
1848         drm_panel_attach(intel_dsi->panel, connector);
1849
1850         mutex_lock(&dev->mode_config.mutex);
1851         drm_panel_get_modes(intel_dsi->panel);
1852         list_for_each_entry(scan, &connector->probed_modes, head) {
1853                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1854                         fixed_mode = drm_mode_duplicate(dev, scan);
1855                         break;
1856                 }
1857         }
1858         mutex_unlock(&dev->mode_config.mutex);
1859
1860         if (!fixed_mode) {
1861                 DRM_DEBUG_KMS("no fixed mode\n");
1862                 goto err;
1863         }
1864
1865         connector->display_info.width_mm = fixed_mode->width_mm;
1866         connector->display_info.height_mm = fixed_mode->height_mm;
1867
1868         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1869         intel_panel_setup_backlight(connector, INVALID_PIPE);
1870
1871         intel_dsi_add_properties(intel_connector);
1872
1873         return;
1874
1875 err:
1876         drm_encoder_cleanup(&intel_encoder->base);
1877         kfree(intel_dsi);
1878         kfree(intel_connector);
1879 }