drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <drm/drm_panel.h>
  32 #include <drm/drm_mipi_dsi.h>
  33 #include <linux/slab.h>
  34 #include <linux/gpio/consumer.h>
  35 #include "i915_drv.h"
  36 #include "intel_drv.h"
  37 #include "intel_dsi.h"
  38
  39 static const struct {
  40         u16 panel_id;
  41         struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
  42 } intel_dsi_drivers[] = {
  43         {
  44                 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
  45                 .init = vbt_panel_init,
  46         },
  47 };
  48
  49 static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  50 {
  51         struct drm_encoder *encoder = &intel_dsi->base.base;
  52         struct drm_device *dev = encoder->dev;
  53         struct drm_i915_private *dev_priv = dev->dev_private;
  54         u32 mask;
  55
  56         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  57                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  58
  59         if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100))
  60                 DRM_ERROR("DPI FIFOs are not empty\n");
  61 }
  62
  63 static void write_data(struct drm_i915_private *dev_priv, u32 reg,
  64                        const u8 *data, u32 len)
  65 {
  66         u32 i, j;
  67
  68         for (i = 0; i < len; i += 4) {
  69                 u32 val = 0;
  70
  71                 for (j = 0; j < min_t(u32, len - i, 4); j++)
  72                         val |= *data++ << 8 * j;
  73
  74                 I915_WRITE(reg, val);
  75         }
  76 }
  77
  78 static void read_data(struct drm_i915_private *dev_priv, u32 reg,
  79                       u8 *data, u32 len)
  80 {
  81         u32 i, j;
  82
  83         for (i = 0; i < len; i += 4) {
  84                 u32 val = I915_READ(reg);
  85
  86                 for (j = 0; j < min_t(u32, len - i, 4); j++)
  87                         *data++ = val >> 8 * j;
  88         }
  89 }
  90
  91 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
  92                                        const struct mipi_dsi_msg *msg)
  93 {
  94         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
  95         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
  96         struct drm_i915_private *dev_priv = dev->dev_private;
  97         enum port port = intel_dsi_host->port;
  98         struct mipi_dsi_packet packet;
  99         ssize_t ret;
 100         const u8 *header, *data;
 101         u32 data_reg, data_mask, ctrl_reg, ctrl_mask;
 102
 103         ret = mipi_dsi_create_packet(&packet, msg);
 104         if (ret < 0)
 105                 return ret;
 106
 107         header = packet.header;
 108         data = packet.payload;
 109
 110         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 111                 data_reg = MIPI_LP_GEN_DATA(port);
 112                 data_mask = LP_DATA_FIFO_FULL;
 113                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 114                 ctrl_mask = LP_CTRL_FIFO_FULL;
 115         } else {
 116                 data_reg = MIPI_HS_GEN_DATA(port);
 117                 data_mask = HS_DATA_FIFO_FULL;
 118                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 119                 ctrl_mask = HS_CTRL_FIFO_FULL;
 120         }
 121
 122         /* note: this is never true for reads */
 123         if (packet.payload_length) {
 124
 125                 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50))
 126                         DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 127
 128                 write_data(dev_priv, data_reg, packet.payload,
 129                            packet.payload_length);
 130         }
 131
 132         if (msg->rx_len) {
 133                 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 134         }
 135
 136         if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) {
 137                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 138         }
 139
 140         I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
 141
 142         /* ->rx_len is set only for reads */
 143         if (msg->rx_len) {
 144                 data_mask = GEN_READ_DATA_AVAIL;
 145                 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50))
 146                         DRM_ERROR("Timeout waiting for read data.\n");
 147
 148                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 149         }
 150
 151         /* XXX: fix for reads and writes */
 152         return 4 + packet.payload_length;
 153 }
 154
 155 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 156                                  struct mipi_dsi_device *dsi)
 157 {
 158         return 0;
 159 }
 160
 161 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 162                                  struct mipi_dsi_device *dsi)
 163 {
 164         return 0;
 165 }
 166
 167 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 168         .attach = intel_dsi_host_attach,
 169         .detach = intel_dsi_host_detach,
 170         .transfer = intel_dsi_host_transfer,
 171 };
 172
 173 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
 174                                                   enum port port)
 175 {
 176         struct intel_dsi_host *host;
 177         struct mipi_dsi_device *device;
 178
 179         host = kzalloc(sizeof(*host), GFP_KERNEL);
 180         if (!host)
 181                 return NULL;
 182
 183         host->base.ops = &intel_dsi_host_ops;
 184         host->intel_dsi = intel_dsi;
 185         host->port = port;
 186
 187         /*
 188          * We should call mipi_dsi_host_register(&host->base) here, but we don't
 189          * have a host->dev, and we don't have OF stuff either. So just use the
 190          * dsi framework as a library and hope for the best. Create the dsi
 191          * devices by ourselves here too. Need to be careful though, because we
 192          * don't initialize any of the driver model devices here.
 193          */
 194         device = kzalloc(sizeof(*device), GFP_KERNEL);
 195         if (!device) {
 196                 kfree(host);
 197                 return NULL;
 198         }
 199
 200         device->host = &host->base;
 201         host->device = device;
 202
 203         return host;
 204 }
 205
 206 /*
 207  * send a video mode command
 208  *
 209  * XXX: commands with data in MIPI_DPI_DATA?
 210  */
 211 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 212                         enum port port)
 213 {
 214         struct drm_encoder *encoder = &intel_dsi->base.base;
 215         struct drm_device *dev = encoder->dev;
 216         struct drm_i915_private *dev_priv = dev->dev_private;
 217         u32 mask;
 218
 219         /* XXX: pipe, hs */
 220         if (hs)
 221                 cmd &= ~DPI_LP_MODE;
 222         else
 223                 cmd |= DPI_LP_MODE;
 224
 225         /* clear bit */
 226         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 227
 228         /* XXX: old code skips write if control unchanged */
 229         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 230                 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
 231
 232         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 233
 234         mask = SPL_PKT_SENT_INTERRUPT;
 235         if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
 236                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 237
 238         return 0;
 239 }
 240
 241 static void band_gap_reset(struct drm_i915_private *dev_priv)
 242 {
 243         mutex_lock(&dev_priv->sb_lock);
 244
 245         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 246         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 247         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 248         udelay(150);
 249         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 250         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 251
 252         mutex_unlock(&dev_priv->sb_lock);
 253 }
 254
 255 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
 256 {
 257         return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
 258 }
 259
 260 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
 261 {
 262         return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
 263 }
 264
 265 static void intel_dsi_hot_plug(struct intel_encoder *encoder)
 266 {
 267         DRM_DEBUG_KMS("\n");
 268 }
 269
 270 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 271                                      struct intel_crtc_state *config)
 272 {
 273         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 274                                                    base);
 275         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 276         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 277         struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode;
 278
 279         DRM_DEBUG_KMS("\n");
 280
 281         if (fixed_mode)
 282                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 283
 284         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 285         adjusted_mode->flags = 0;
 286
 287         return true;
 288 }
 289
 290 static void intel_dsi_port_enable(struct intel_encoder *encoder)
 291 {
 292         struct drm_device *dev = encoder->base.dev;
 293         struct drm_i915_private *dev_priv = dev->dev_private;
 294         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 295         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 296         enum port port;
 297         u32 temp;
 298
 299         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 300                 temp = I915_READ(VLV_CHICKEN_3);
 301                 temp &= ~PIXEL_OVERLAP_CNT_MASK |
 302                                         intel_dsi->pixel_overlap <<
 303                                         PIXEL_OVERLAP_CNT_SHIFT;
 304                 I915_WRITE(VLV_CHICKEN_3, temp);
 305         }
 306
 307         for_each_dsi_port(port, intel_dsi->ports) {
 308                 temp = I915_READ(MIPI_PORT_CTRL(port));
 309                 temp &= ~LANE_CONFIGURATION_MASK;
 310                 temp &= ~DUAL_LINK_MODE_MASK;
 311
 312                 if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
 313                         temp |= (intel_dsi->dual_link - 1)
 314                                                 << DUAL_LINK_MODE_SHIFT;
 315                         temp |= intel_crtc->pipe ?
 316                                         LANE_CONFIGURATION_DUAL_LINK_B :
 317                                         LANE_CONFIGURATION_DUAL_LINK_A;
 318                 }
 319                 /* assert ip_tg_enable signal */
 320                 I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
 321                 POSTING_READ(MIPI_PORT_CTRL(port));
 322         }
 323 }
 324
 325 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 326 {
 327         struct drm_device *dev = encoder->base.dev;
 328         struct drm_i915_private *dev_priv = dev->dev_private;
 329         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 330         enum port port;
 331         u32 temp;
 332
 333         for_each_dsi_port(port, intel_dsi->ports) {
 334                 /* de-assert ip_tg_enable signal */
 335                 temp = I915_READ(MIPI_PORT_CTRL(port));
 336                 I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
 337                 POSTING_READ(MIPI_PORT_CTRL(port));
 338         }
 339 }
 340
 341 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 342 {
 343         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 344         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 345         enum port port;
 346         u32 val;
 347
 348         DRM_DEBUG_KMS("\n");
 349
 350         mutex_lock(&dev_priv->sb_lock);
 351         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 352          * needed everytime after power gate */
 353         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 354         mutex_unlock(&dev_priv->sb_lock);
 355
 356         /* bandgap reset is needed after everytime we do power gate */
 357         band_gap_reset(dev_priv);
 358
 359         for_each_dsi_port(port, intel_dsi->ports) {
 360
 361                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 362                 usleep_range(2500, 3000);
 363
 364                 /* Enable MIPI PHY transparent latch
 365                  * Common bit for both MIPI Port A & MIPI Port C
 366                  * No similar bit in MIPI Port C reg
 367                  */
 368                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 369                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 370                 usleep_range(1000, 1500);
 371
 372                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 373                 usleep_range(2500, 3000);
 374
 375                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 376                 usleep_range(2500, 3000);
 377         }
 378 }
 379
 380 static void intel_dsi_enable(struct intel_encoder *encoder)
 381 {
 382         struct drm_device *dev = encoder->base.dev;
 383         struct drm_i915_private *dev_priv = dev->dev_private;
 384         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 385         enum port port;
 386
 387         DRM_DEBUG_KMS("\n");
 388
 389         if (is_cmd_mode(intel_dsi)) {
 390                 for_each_dsi_port(port, intel_dsi->ports)
 391                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 392         } else {
 393                 msleep(20); /* XXX */
 394                 for_each_dsi_port(port, intel_dsi->ports)
 395                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 396                 msleep(100);
 397
 398                 drm_panel_enable(intel_dsi->panel);
 399
 400                 for_each_dsi_port(port, intel_dsi->ports)
 401                         wait_for_dsi_fifo_empty(intel_dsi, port);
 402
 403                 intel_dsi_port_enable(encoder);
 404         }
 405
 406         intel_panel_enable_backlight(intel_dsi->attached_connector);
 407 }
 408
 409 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 410 {
 411         struct drm_device *dev = encoder->base.dev;
 412         struct drm_i915_private *dev_priv = dev->dev_private;
 413         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 414         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 415         enum pipe pipe = intel_crtc->pipe;
 416         enum port port;
 417         u32 tmp;
 418
 419         DRM_DEBUG_KMS("\n");
 420
 421         /* Panel Enable over CRC PMIC */
 422         if (intel_dsi->gpio_panel)
 423                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
 424
 425         msleep(intel_dsi->panel_on_delay);
 426
 427         /* Disable DPOunit clock gating, can stall pipe
 428          * and we need DPLL REFA always enabled */
 429         tmp = I915_READ(DPLL(pipe));
 430         tmp |= DPLL_REFA_CLK_ENABLE_VLV;
 431         I915_WRITE(DPLL(pipe), tmp);
 432
 433         /* update the hw state for DPLL */
 434         intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
 435                 DPLL_REFA_CLK_ENABLE_VLV;
 436
 437         tmp = I915_READ(DSPCLK_GATE_D);
 438         tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
 439         I915_WRITE(DSPCLK_GATE_D, tmp);
 440
 441         /* put device in ready state */
 442         intel_dsi_device_ready(encoder);
 443
 444         drm_panel_prepare(intel_dsi->panel);
 445
 446         for_each_dsi_port(port, intel_dsi->ports)
 447                 wait_for_dsi_fifo_empty(intel_dsi, port);
 448
 449         /* Enable port in pre-enable phase itself because as per hw team
 450          * recommendation, port should be enabled befor plane & pipe */
 451         intel_dsi_enable(encoder);
 452 }
 453
 454 static void intel_dsi_enable_nop(struct intel_encoder *encoder)
 455 {
 456         DRM_DEBUG_KMS("\n");
 457
 458         /* for DSI port enable has to be done before pipe
 459          * and plane enable, so port enable is done in
 460          * pre_enable phase itself unlike other encoders
 461          */
 462 }
 463
 464 static void intel_dsi_pre_disable(struct intel_encoder *encoder)
 465 {
 466         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 467         enum port port;
 468
 469         DRM_DEBUG_KMS("\n");
 470
 471         intel_panel_disable_backlight(intel_dsi->attached_connector);
 472
 473         if (is_vid_mode(intel_dsi)) {
 474                 /* Send Shutdown command to the panel in LP mode */
 475                 for_each_dsi_port(port, intel_dsi->ports)
 476                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 477                 msleep(10);
 478         }
 479 }
 480
 481 static void intel_dsi_disable(struct intel_encoder *encoder)
 482 {
 483         struct drm_device *dev = encoder->base.dev;
 484         struct drm_i915_private *dev_priv = dev->dev_private;
 485         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 486         enum port port;
 487         u32 temp;
 488
 489         DRM_DEBUG_KMS("\n");
 490
 491         if (is_vid_mode(intel_dsi)) {
 492                 for_each_dsi_port(port, intel_dsi->ports)
 493                         wait_for_dsi_fifo_empty(intel_dsi, port);
 494
 495                 intel_dsi_port_disable(encoder);
 496                 msleep(2);
 497         }
 498
 499         for_each_dsi_port(port, intel_dsi->ports) {
 500                 /* Panel commands can be sent when clock is in LP11 */
 501                 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
 502
 503                 temp = I915_READ(MIPI_CTRL(port));
 504                 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 505                 I915_WRITE(MIPI_CTRL(port), temp |
 506                            intel_dsi->escape_clk_div <<
 507                            ESCAPE_CLOCK_DIVIDER_SHIFT);
 508
 509                 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 510
 511                 temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
 512                 temp &= ~VID_MODE_FORMAT_MASK;
 513                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
 514
 515                 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
 516         }
 517         /* if disable packets are sent before sending shutdown packet then in
 518          * some next enable sequence send turn on packet error is observed */
 519         drm_panel_disable(intel_dsi->panel);
 520
 521         for_each_dsi_port(port, intel_dsi->ports)
 522                 wait_for_dsi_fifo_empty(intel_dsi, port);
 523 }
 524
 525 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 526 {
 527         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 528         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 529         enum port port;
 530         u32 val;
 531
 532         DRM_DEBUG_KMS("\n");
 533         for_each_dsi_port(port, intel_dsi->ports) {
 534
 535                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 536                                                         ULPS_STATE_ENTER);
 537                 usleep_range(2000, 2500);
 538
 539                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 540                                                         ULPS_STATE_EXIT);
 541                 usleep_range(2000, 2500);
 542
 543                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 544                                                         ULPS_STATE_ENTER);
 545                 usleep_range(2000, 2500);
 546
 547                 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
 548                  * only. MIPI Port C has no similar bit for checking
 549                  */
 550                 if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT)
 551                                                         == 0x00000), 30))
 552                         DRM_ERROR("DSI LP not going Low\n");
 553
 554                 /* Disable MIPI PHY transparent latch
 555                  * Common bit for both MIPI Port A & MIPI Port C
 556                  */
 557                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 558                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD);
 559                 usleep_range(1000, 1500);
 560
 561                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 562                 usleep_range(2000, 2500);
 563         }
 564
 565         vlv_disable_dsi_pll(encoder);
 566 }
 567
 568 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 569 {
 570         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 571         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 572         u32 val;
 573
 574         DRM_DEBUG_KMS("\n");
 575
 576         intel_dsi_disable(encoder);
 577
 578         intel_dsi_clear_device_ready(encoder);
 579
 580         val = I915_READ(DSPCLK_GATE_D);
 581         val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 582         I915_WRITE(DSPCLK_GATE_D, val);
 583
 584         drm_panel_unprepare(intel_dsi->panel);
 585
 586         msleep(intel_dsi->panel_off_delay);
 587         msleep(intel_dsi->panel_pwr_cycle_delay);
 588
 589         /* Panel Disable over CRC PMIC */
 590         if (intel_dsi->gpio_panel)
 591                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
 592 }
 593
 594 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 595                                    enum pipe *pipe)
 596 {
 597         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 598         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 599         struct drm_device *dev = encoder->base.dev;
 600         enum intel_display_power_domain power_domain;
 601         u32 dpi_enabled, func;
 602         enum port port;
 603
 604         DRM_DEBUG_KMS("\n");
 605
 606         power_domain = intel_display_port_power_domain(encoder);
 607         if (!intel_display_power_is_enabled(dev_priv, power_domain))
 608                 return false;
 609
 610         /* XXX: this only works for one DSI output */
 611         for_each_dsi_port(port, intel_dsi->ports) {
 612                 func = I915_READ(MIPI_DSI_FUNC_PRG(port));
 613                 dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) &
 614                                                         DPI_ENABLE;
 615
 616                 /* Due to some hardware limitations on BYT, MIPI Port C DPI
 617                  * Enable bit does not get set. To check whether DSI Port C
 618                  * was enabled in BIOS, check the Pipe B enable bit
 619                  */
 620                 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 621                     (port == PORT_C))
 622                         dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
 623                                                         PIPECONF_ENABLE;
 624
 625                 if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) {
 626                         if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) {
 627                                 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
 628                                 return true;
 629                         }
 630                 }
 631         }
 632
 633         return false;
 634 }
 635
 636 static void intel_dsi_get_config(struct intel_encoder *encoder,
 637                                  struct intel_crtc_state *pipe_config)
 638 {
 639         u32 pclk;
 640         DRM_DEBUG_KMS("\n");
 641
 642         /*
 643          * DPLL_MD is not used in case of DSI, reading will get some default value
 644          * set dpll_md = 0
 645          */
 646         pipe_config->dpll_hw_state.dpll_md = 0;
 647
 648         pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
 649         if (!pclk)
 650                 return;
 651
 652         pipe_config->base.adjusted_mode.crtc_clock = pclk;
 653         pipe_config->port_clock = pclk;
 654 }
 655
 656 static enum drm_mode_status
 657 intel_dsi_mode_valid(struct drm_connector *connector,
 658                      struct drm_display_mode *mode)
 659 {
 660         struct intel_connector *intel_connector = to_intel_connector(connector);
 661         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 662
 663         DRM_DEBUG_KMS("\n");
 664
 665         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 666                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
 667                 return MODE_NO_DBLESCAN;
 668         }
 669
 670         if (fixed_mode) {
 671                 if (mode->hdisplay > fixed_mode->hdisplay)
 672                         return MODE_PANEL;
 673                 if (mode->vdisplay > fixed_mode->vdisplay)
 674                         return MODE_PANEL;
 675         }
 676
 677         return MODE_OK;
 678 }
 679
 680 /* return txclkesc cycles in terms of divider and duration in us */
 681 static u16 txclkesc(u32 divider, unsigned int us)
 682 {
 683         switch (divider) {
 684         case ESCAPE_CLOCK_DIVIDER_1:
 685         default:
 686                 return 20 * us;
 687         case ESCAPE_CLOCK_DIVIDER_2:
 688                 return 10 * us;
 689         case ESCAPE_CLOCK_DIVIDER_4:
 690                 return 5 * us;
 691         }
 692 }
 693
 694 /* return pixels in terms of txbyteclkhs */
 695 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
 696                        u16 burst_mode_ratio)
 697 {
 698         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
 699                                          8 * 100), lane_count);
 700 }
 701
 702 static void set_dsi_timings(struct drm_encoder *encoder,
 703                             const struct drm_display_mode *mode)
 704 {
 705         struct drm_device *dev = encoder->dev;
 706         struct drm_i915_private *dev_priv = dev->dev_private;
 707         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 708         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 709         enum port port;
 710         unsigned int bpp = intel_crtc->config->pipe_bpp;
 711         unsigned int lane_count = intel_dsi->lane_count;
 712
 713         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 714
 715         hactive = mode->hdisplay;
 716         hfp = mode->hsync_start - mode->hdisplay;
 717         hsync = mode->hsync_end - mode->hsync_start;
 718         hbp = mode->htotal - mode->hsync_end;
 719
 720         if (intel_dsi->dual_link) {
 721                 hactive /= 2;
 722                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 723                         hactive += intel_dsi->pixel_overlap;
 724                 hfp /= 2;
 725                 hsync /= 2;
 726                 hbp /= 2;
 727         }
 728
 729         vfp = mode->vsync_start - mode->vdisplay;
 730         vsync = mode->vsync_end - mode->vsync_start;
 731         vbp = mode->vtotal - mode->vsync_end;
 732
 733         /* horizontal values are in terms of high speed byte clock */
 734         hactive = txbyteclkhs(hactive, bpp, lane_count,
 735                               intel_dsi->burst_mode_ratio);
 736         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 737         hsync = txbyteclkhs(hsync, bpp, lane_count,
 738                             intel_dsi->burst_mode_ratio);
 739         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 740
 741         for_each_dsi_port(port, intel_dsi->ports) {
 742                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
 743                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
 744
 745                 /* meaningful for video mode non-burst sync pulse mode only,
 746                  * can be zero for non-burst sync events and burst modes */
 747                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
 748                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
 749
 750                 /* vertical values are in terms of lines */
 751                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
 752                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
 753                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
 754         }
 755 }
 756
 757 static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 758 {
 759         struct drm_encoder *encoder = &intel_encoder->base;
 760         struct drm_device *dev = encoder->dev;
 761         struct drm_i915_private *dev_priv = dev->dev_private;
 762         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 763         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 764         struct drm_display_mode *adjusted_mode =
 765                 &intel_crtc->config->base.adjusted_mode;
 766         enum port port;
 767         unsigned int bpp = intel_crtc->config->pipe_bpp;
 768         u32 val, tmp;
 769         u16 mode_hdisplay;
 770
 771         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
 772
 773         mode_hdisplay = adjusted_mode->hdisplay;
 774
 775         if (intel_dsi->dual_link) {
 776                 mode_hdisplay /= 2;
 777                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 778                         mode_hdisplay += intel_dsi->pixel_overlap;
 779         }
 780
 781         for_each_dsi_port(port, intel_dsi->ports) {
 782                 /* escape clock divider, 20MHz, shared for A and C.
 783                  * device ready must be off when doing this! txclkesc? */
 784                 tmp = I915_READ(MIPI_CTRL(PORT_A));
 785                 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 786                 I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
 787
 788                 /* read request priority is per pipe */
 789                 tmp = I915_READ(MIPI_CTRL(port));
 790                 tmp &= ~READ_REQUEST_PRIORITY_MASK;
 791                 I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
 792
 793                 /* XXX: why here, why like this? handling in irq handler?! */
 794                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
 795                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
 796
 797                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
 798
 799                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
 800                         adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
 801                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
 802         }
 803
 804         set_dsi_timings(encoder, adjusted_mode);
 805
 806         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
 807         if (is_cmd_mode(intel_dsi)) {
 808                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
 809                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
 810         } else {
 811                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
 812
 813                 /* XXX: cross-check bpp vs. pixel format? */
 814                 val |= intel_dsi->pixel_format;
 815         }
 816
 817         tmp = 0;
 818         if (intel_dsi->eotp_pkt == 0)
 819                 tmp |= EOT_DISABLE;
 820         if (intel_dsi->clock_stop)
 821                 tmp |= CLOCKSTOP;
 822
 823         for_each_dsi_port(port, intel_dsi->ports) {
 824                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
 825
 826                 /* timeouts for recovery. one frame IIUC. if counter expires,
 827                  * EOT and stop state. */
 828
 829                 /*
 830                  * In burst mode, value greater than one DPI line Time in byte
 831                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
 832                  * said value is recommended.
 833                  *
 834                  * In non-burst mode, Value greater than one DPI frame time in
 835                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
 836                  * said value is recommended.
 837                  *
 838                  * In DBI only mode, value greater than one DBI frame time in
 839                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
 840                  * said value is recommended.
 841                  */
 842
 843                 if (is_vid_mode(intel_dsi) &&
 844                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 845                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
 846                                 txbyteclkhs(adjusted_mode->htotal, bpp,
 847                                         intel_dsi->lane_count,
 848                                         intel_dsi->burst_mode_ratio) + 1);
 849                 } else {
 850                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
 851                                 txbyteclkhs(adjusted_mode->vtotal *
 852                                         adjusted_mode->htotal,
 853                                         bpp, intel_dsi->lane_count,
 854                                         intel_dsi->burst_mode_ratio) + 1);
 855                 }
 856                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
 857                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
 858                                                 intel_dsi->turn_arnd_val);
 859                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
 860                                                 intel_dsi->rst_timer_val);
 861
 862                 /* dphy stuff */
 863
 864                 /* in terms of low power clock */
 865                 I915_WRITE(MIPI_INIT_COUNT(port),
 866                                 txclkesc(intel_dsi->escape_clk_div, 100));
 867
 868
 869                 /* recovery disables */
 870                 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
 871
 872                 /* in terms of low power clock */
 873                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
 874
 875                 /* in terms of txbyteclkhs. actual high to low switch +
 876                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
 877                  *
 878                  * XXX: write MIPI_STOP_STATE_STALL?
 879                  */
 880                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
 881                                                 intel_dsi->hs_to_lp_count);
 882
 883                 /* XXX: low power clock equivalence in terms of byte clock.
 884                  * the number of byte clocks occupied in one low power clock.
 885                  * based on txbyteclkhs and txclkesc.
 886                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
 887                  * ) / 105.???
 888                  */
 889                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
 890
 891                 /* the bw essential for transmitting 16 long packets containing
 892                  * 252 bytes meant for dcs write memory command is programmed in
 893                  * this register in terms of byte clocks. based on dsi transfer
 894                  * rate and the number of lanes configured the time taken to
 895                  * transmit 16 long packets in a dsi stream varies. */
 896                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
 897
 898                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
 899                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
 900                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
 901
 902                 if (is_vid_mode(intel_dsi))
 903                         /* Some panels might have resolution which is not a
 904                          * multiple of 64 like 1366 x 768. Enable RANDOM
 905                          * resolution support for such panels by default */
 906                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
 907                                 intel_dsi->video_frmt_cfg_bits |
 908                                 intel_dsi->video_mode_format |
 909                                 IP_TG_CONFIG |
 910                                 RANDOM_DPI_DISPLAY_RESOLUTION);
 911         }
 912 }
 913
 914 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
 915 {
 916         DRM_DEBUG_KMS("\n");
 917
 918         intel_dsi_prepare(encoder);
 919
 920         vlv_enable_dsi_pll(encoder);
 921 }
 922
 923 static enum drm_connector_status
 924 intel_dsi_detect(struct drm_connector *connector, bool force)
 925 {
 926         return connector_status_connected;
 927 }
 928
 929 static int intel_dsi_get_modes(struct drm_connector *connector)
 930 {
 931         struct intel_connector *intel_connector = to_intel_connector(connector);
 932         struct drm_display_mode *mode;
 933
 934         DRM_DEBUG_KMS("\n");
 935
 936         if (!intel_connector->panel.fixed_mode) {
 937                 DRM_DEBUG_KMS("no fixed mode\n");
 938                 return 0;
 939         }
 940
 941         mode = drm_mode_duplicate(connector->dev,
 942                                   intel_connector->panel.fixed_mode);
 943         if (!mode) {
 944                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
 945                 return 0;
 946         }
 947
 948         drm_mode_probed_add(connector, mode);
 949         return 1;
 950 }
 951
 952 static void intel_dsi_connector_destroy(struct drm_connector *connector)
 953 {
 954         struct intel_connector *intel_connector = to_intel_connector(connector);
 955
 956         DRM_DEBUG_KMS("\n");
 957         intel_panel_fini(&intel_connector->panel);
 958         drm_connector_cleanup(connector);
 959         kfree(connector);
 960 }
 961
 962 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
 963 {
 964         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 965
 966         if (intel_dsi->panel) {
 967                 drm_panel_detach(intel_dsi->panel);
 968                 /* XXX: Logically this call belongs in the panel driver. */
 969                 drm_panel_remove(intel_dsi->panel);
 970         }
 971
 972         /* dispose of the gpios */
 973         if (intel_dsi->gpio_panel)
 974                 gpiod_put(intel_dsi->gpio_panel);
 975
 976         intel_encoder_destroy(encoder);
 977 }
 978
 979 static const struct drm_encoder_funcs intel_dsi_funcs = {
 980         .destroy = intel_dsi_encoder_destroy,
 981 };
 982
 983 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
 984         .get_modes = intel_dsi_get_modes,
 985         .mode_valid = intel_dsi_mode_valid,
 986         .best_encoder = intel_best_encoder,
 987 };
 988
 989 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
 990         .dpms = intel_connector_dpms,
 991         .detect = intel_dsi_detect,
 992         .destroy = intel_dsi_connector_destroy,
 993         .fill_modes = drm_helper_probe_single_connector_modes,
 994         .atomic_get_property = intel_connector_atomic_get_property,
 995         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 996         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 997 };
 998
 999 void intel_dsi_init(struct drm_device *dev)
1000 {
1001         struct intel_dsi *intel_dsi;
1002         struct intel_encoder *intel_encoder;
1003         struct drm_encoder *encoder;
1004         struct intel_connector *intel_connector;
1005         struct drm_connector *connector;
1006         struct drm_display_mode *scan, *fixed_mode = NULL;
1007         struct drm_i915_private *dev_priv = dev->dev_private;
1008         enum port port;
1009         unsigned int i;
1010
1011         DRM_DEBUG_KMS("\n");
1012
1013         /* There is no detection method for MIPI so rely on VBT */
1014         if (!dev_priv->vbt.has_mipi)
1015                 return;
1016
1017         if (IS_VALLEYVIEW(dev)) {
1018                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1019         } else {
1020                 DRM_ERROR("Unsupported Mipi device to reg base");
1021                 return;
1022         }
1023
1024         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1025         if (!intel_dsi)
1026                 return;
1027
1028         intel_connector = intel_connector_alloc();
1029         if (!intel_connector) {
1030                 kfree(intel_dsi);
1031                 return;
1032         }
1033
1034         intel_encoder = &intel_dsi->base;
1035         encoder = &intel_encoder->base;
1036         intel_dsi->attached_connector = intel_connector;
1037
1038         connector = &intel_connector->base;
1039
1040         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
1041
1042         /* XXX: very likely not all of these are needed */
1043         intel_encoder->hot_plug = intel_dsi_hot_plug;
1044         intel_encoder->compute_config = intel_dsi_compute_config;
1045         intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
1046         intel_encoder->pre_enable = intel_dsi_pre_enable;
1047         intel_encoder->enable = intel_dsi_enable_nop;
1048         intel_encoder->disable = intel_dsi_pre_disable;
1049         intel_encoder->post_disable = intel_dsi_post_disable;
1050         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1051         intel_encoder->get_config = intel_dsi_get_config;
1052
1053         intel_connector->get_hw_state = intel_connector_get_hw_state;
1054         intel_connector->unregister = intel_connector_unregister;
1055
1056         /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
1057         if (dev_priv->vbt.dsi.config->dual_link) {
1058                 /* XXX: does dual link work on either pipe? */
1059                 intel_encoder->crtc_mask = (1 << PIPE_A);
1060                 intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
1061         } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) {
1062                 intel_encoder->crtc_mask = (1 << PIPE_A);
1063                 intel_dsi->ports = (1 << PORT_A);
1064         } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) {
1065                 intel_encoder->crtc_mask = (1 << PIPE_B);
1066                 intel_dsi->ports = (1 << PORT_C);
1067         }
1068
1069         /* Create a DSI host (and a device) for each port. */
1070         for_each_dsi_port(port, intel_dsi->ports) {
1071                 struct intel_dsi_host *host;
1072
1073                 host = intel_dsi_host_init(intel_dsi, port);
1074                 if (!host)
1075                         goto err;
1076
1077                 intel_dsi->dsi_hosts[port] = host;
1078         }
1079
1080         for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) {
1081                 intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi,
1082                                                              intel_dsi_drivers[i].panel_id);
1083                 if (intel_dsi->panel)
1084                         break;
1085         }
1086
1087         if (!intel_dsi->panel) {
1088                 DRM_DEBUG_KMS("no device found\n");
1089                 goto err;
1090         }
1091
1092         /*
1093          * In case of BYT with CRC PMIC, we need to use GPIO for
1094          * Panel control.
1095          */
1096         if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
1097                 intel_dsi->gpio_panel =
1098                         gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1099
1100                 if (IS_ERR(intel_dsi->gpio_panel)) {
1101                         DRM_ERROR("Failed to own gpio for panel control\n");
1102                         intel_dsi->gpio_panel = NULL;
1103                 }
1104         }
1105
1106         intel_encoder->type = INTEL_OUTPUT_DSI;
1107         intel_encoder->cloneable = 0;
1108         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1109                            DRM_MODE_CONNECTOR_DSI);
1110
1111         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1112
1113         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1114         connector->interlace_allowed = false;
1115         connector->doublescan_allowed = false;
1116
1117         intel_connector_attach_encoder(intel_connector, intel_encoder);
1118
1119         drm_connector_register(connector);
1120
1121         drm_panel_attach(intel_dsi->panel, connector);
1122
1123         mutex_lock(&dev->mode_config.mutex);
1124         drm_panel_get_modes(intel_dsi->panel);
1125         list_for_each_entry(scan, &connector->probed_modes, head) {
1126                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1127                         fixed_mode = drm_mode_duplicate(dev, scan);
1128                         break;
1129                 }
1130         }
1131         mutex_unlock(&dev->mode_config.mutex);
1132
1133         if (!fixed_mode) {
1134                 DRM_DEBUG_KMS("no fixed mode\n");
1135                 goto err;
1136         }
1137
1138         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1139         intel_panel_setup_backlight(connector, INVALID_PIPE);
1140
1141         return;
1142
1143 err:
1144         drm_encoder_cleanup(&intel_encoder->base);
1145         kfree(intel_dsi);
1146         kfree(intel_connector);
1147 }