2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_ringbuffer.h"
27 #include "intel_lrc.h"
29 static const struct engine_info {
32 enum intel_engine_hw_id hw_id;
35 int (*init_legacy)(struct intel_engine_cs *engine);
36 int (*init_execlists)(struct intel_engine_cs *engine);
39 .name = "render ring",
40 .exec_id = I915_EXEC_RENDER,
42 .mmio_base = RENDER_RING_BASE,
43 .irq_shift = GEN8_RCS_IRQ_SHIFT,
44 .init_execlists = logical_render_ring_init,
45 .init_legacy = intel_init_render_ring_buffer,
48 .name = "blitter ring",
49 .exec_id = I915_EXEC_BLT,
51 .mmio_base = BLT_RING_BASE,
52 .irq_shift = GEN8_BCS_IRQ_SHIFT,
53 .init_execlists = logical_xcs_ring_init,
54 .init_legacy = intel_init_blt_ring_buffer,
58 .exec_id = I915_EXEC_BSD,
60 .mmio_base = GEN6_BSD_RING_BASE,
61 .irq_shift = GEN8_VCS1_IRQ_SHIFT,
62 .init_execlists = logical_xcs_ring_init,
63 .init_legacy = intel_init_bsd_ring_buffer,
67 .exec_id = I915_EXEC_BSD,
69 .mmio_base = GEN8_BSD2_RING_BASE,
70 .irq_shift = GEN8_VCS2_IRQ_SHIFT,
71 .init_execlists = logical_xcs_ring_init,
72 .init_legacy = intel_init_bsd2_ring_buffer,
75 .name = "video enhancement ring",
76 .exec_id = I915_EXEC_VEBOX,
78 .mmio_base = VEBOX_RING_BASE,
79 .irq_shift = GEN8_VECS_IRQ_SHIFT,
80 .init_execlists = logical_xcs_ring_init,
81 .init_legacy = intel_init_vebox_ring_buffer,
86 intel_engine_setup(struct drm_i915_private *dev_priv,
87 enum intel_engine_id id)
89 const struct engine_info *info = &intel_engines[id];
90 struct intel_engine_cs *engine;
92 GEM_BUG_ON(dev_priv->engine[id]);
93 engine = kzalloc(sizeof(*engine), GFP_KERNEL);
98 engine->i915 = dev_priv;
99 engine->name = info->name;
100 engine->exec_id = info->exec_id;
101 engine->hw_id = engine->guc_id = info->hw_id;
102 engine->mmio_base = info->mmio_base;
103 engine->irq_shift = info->irq_shift;
105 /* Nothing to do here, execute in order of dependencies */
106 engine->schedule = NULL;
108 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
110 dev_priv->engine[id] = engine;
115 * intel_engines_init() - allocate, populate and init the Engine Command Streamers
116 * @dev_priv: i915 device private
118 * Return: non-zero if the initialization failed.
120 int intel_engines_init(struct drm_i915_private *dev_priv)
122 struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
123 unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask;
124 unsigned int mask = 0;
125 int (*init)(struct intel_engine_cs *engine);
126 struct intel_engine_cs *engine;
127 enum intel_engine_id id;
131 WARN_ON(ring_mask == 0);
133 GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
135 for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
136 if (!HAS_ENGINE(dev_priv, i))
139 if (i915.enable_execlists)
140 init = intel_engines[i].init_execlists;
142 init = intel_engines[i].init_legacy;
147 ret = intel_engine_setup(dev_priv, i);
151 ret = init(dev_priv->engine[i]);
155 mask |= ENGINE_MASK(i);
159 * Catch failures to update intel_engines table when the new engines
160 * are added to the driver by a warning and disabling the forgotten
163 if (WARN_ON(mask != ring_mask))
164 device_info->ring_mask = mask;
166 device_info->num_rings = hweight32(mask);
171 for_each_engine(engine, dev_priv, id) {
172 if (i915.enable_execlists)
173 intel_logical_ring_cleanup(engine);
175 intel_engine_cleanup(engine);
181 void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno)
183 struct drm_i915_private *dev_priv = engine->i915;
185 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
186 * so long as the semaphore value in the register/page is greater
187 * than the sync value), so whenever we reset the seqno,
188 * so long as we reset the tracking semaphore value to 0, it will
189 * always be before the next request's seqno. If we don't reset
190 * the semaphore value, then when the seqno moves backwards all
191 * future waits will complete instantly (causing rendering corruption).
193 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
194 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
195 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
196 if (HAS_VEBOX(dev_priv))
197 I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
199 if (dev_priv->semaphore) {
200 struct page *page = i915_vma_first_page(dev_priv->semaphore);
203 /* Semaphores are in noncoherent memory, flush to be safe */
204 semaphores = kmap(page);
205 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
206 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
207 drm_clflush_virt_range(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
208 I915_NUM_ENGINES * gen8_semaphore_seqno_size);
212 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
213 if (engine->irq_seqno_barrier)
214 engine->irq_seqno_barrier(engine);
216 GEM_BUG_ON(i915_gem_active_isset(&engine->timeline->last_request));
217 engine->timeline->last_submitted_seqno = seqno;
219 engine->hangcheck.seqno = seqno;
221 /* After manually advancing the seqno, fake the interrupt in case
222 * there are any waiters for that seqno.
224 intel_engine_wakeup(engine);
227 static void intel_engine_init_timeline(struct intel_engine_cs *engine)
229 engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id];
233 * intel_engines_setup_common - setup engine state not requiring hw access
234 * @engine: Engine to setup.
236 * Initializes @engine@ structure members shared between legacy and execlists
237 * submission modes which do not require hardware access.
239 * Typically done early in the submission mode specific engine setup stage.
241 void intel_engine_setup_common(struct intel_engine_cs *engine)
243 engine->execlist_queue = RB_ROOT;
244 engine->execlist_first = NULL;
246 intel_engine_init_timeline(engine);
247 intel_engine_init_hangcheck(engine);
248 i915_gem_batch_pool_init(engine, &engine->batch_pool);
250 intel_engine_init_cmd_parser(engine);
253 int intel_engine_create_scratch(struct intel_engine_cs *engine, int size)
255 struct drm_i915_gem_object *obj;
256 struct i915_vma *vma;
259 WARN_ON(engine->scratch);
261 obj = i915_gem_object_create_stolen(engine->i915, size);
263 obj = i915_gem_object_create_internal(engine->i915, size);
265 DRM_ERROR("Failed to allocate scratch page\n");
269 vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
275 ret = i915_vma_pin(vma, 0, 4096, PIN_GLOBAL | PIN_HIGH);
279 engine->scratch = vma;
280 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
281 engine->name, i915_ggtt_offset(vma));
285 i915_gem_object_put(obj);
289 static void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
291 i915_vma_unpin_and_release(&engine->scratch);
295 * intel_engines_init_common - initialize cengine state which might require hw access
296 * @engine: Engine to initialize.
298 * Initializes @engine@ structure members shared between legacy and execlists
299 * submission modes which do require hardware access.
301 * Typcally done at later stages of submission mode specific engine setup.
303 * Returns zero on success or an error code on failure.
305 int intel_engine_init_common(struct intel_engine_cs *engine)
309 /* We may need to do things with the shrinker which
310 * require us to immediately switch back to the default
311 * context. This can cause a problem as pinning the
312 * default context also requires GTT space which may not
313 * be available. To avoid this we always pin the default
316 ret = engine->context_pin(engine, engine->i915->kernel_context);
320 ret = intel_engine_init_breadcrumbs(engine);
324 ret = i915_gem_render_state_init(engine);
331 engine->context_unpin(engine, engine->i915->kernel_context);
336 * intel_engines_cleanup_common - cleans up the engine state created by
337 * the common initiailizers.
338 * @engine: Engine to cleanup.
340 * This cleans up everything created by the common helpers.
342 void intel_engine_cleanup_common(struct intel_engine_cs *engine)
344 intel_engine_cleanup_scratch(engine);
346 i915_gem_render_state_fini(engine);
347 intel_engine_fini_breadcrumbs(engine);
348 intel_engine_cleanup_cmd_parser(engine);
349 i915_gem_batch_pool_fini(&engine->batch_pool);
351 engine->context_unpin(engine, engine->i915->kernel_context);
354 u64 intel_engine_get_active_head(struct intel_engine_cs *engine)
356 struct drm_i915_private *dev_priv = engine->i915;
359 if (INTEL_GEN(dev_priv) >= 8)
360 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
361 RING_ACTHD_UDW(engine->mmio_base));
362 else if (INTEL_GEN(dev_priv) >= 4)
363 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
365 acthd = I915_READ(ACTHD);
370 u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine)
372 struct drm_i915_private *dev_priv = engine->i915;
375 if (INTEL_GEN(dev_priv) >= 8)
376 bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base),
377 RING_BBADDR_UDW(engine->mmio_base));
379 bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
384 const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
387 case I915_CACHE_NONE: return " uncached";
388 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
389 case I915_CACHE_L3_LLC: return " L3+LLC";
390 case I915_CACHE_WT: return " WT";
395 static inline uint32_t
396 read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
397 int subslice, i915_reg_t reg)
401 enum forcewake_domains fw_domains;
403 fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
405 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
407 FW_REG_READ | FW_REG_WRITE);
409 spin_lock_irq(&dev_priv->uncore.lock);
410 intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
412 mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
414 * The HW expects the slice and sublice selectors to be reset to 0
415 * after reading out the registers.
417 WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
418 mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
419 mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
420 I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
422 ret = I915_READ_FW(reg);
424 mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
425 I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
427 intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
428 spin_unlock_irq(&dev_priv->uncore.lock);
433 /* NB: please notice the memset */
434 void intel_engine_get_instdone(struct intel_engine_cs *engine,
435 struct intel_instdone *instdone)
437 struct drm_i915_private *dev_priv = engine->i915;
438 u32 mmio_base = engine->mmio_base;
442 memset(instdone, 0, sizeof(*instdone));
444 switch (INTEL_GEN(dev_priv)) {
446 instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
448 if (engine->id != RCS)
451 instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
452 for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
453 instdone->sampler[slice][subslice] =
454 read_subslice_reg(dev_priv, slice, subslice,
455 GEN7_SAMPLER_INSTDONE);
456 instdone->row[slice][subslice] =
457 read_subslice_reg(dev_priv, slice, subslice,
462 instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
464 if (engine->id != RCS)
467 instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
468 instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE);
469 instdone->row[0][0] = I915_READ(GEN7_ROW_INSTDONE);
475 instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
477 if (engine->id == RCS)
478 /* HACK: Using the wrong struct member */
479 instdone->slice_common = I915_READ(GEN4_INSTDONE1);
483 instdone->instdone = I915_READ(GEN2_INSTDONE);