drivers/gpu/drm/i915/intel_guc_loader.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Vinit Azad <vinit.azad@intel.com>
  25  *    Ben Widawsky <ben@bwidawsk.net>
  26  *    Dave Gordon <david.s.gordon@intel.com>
  27  *    Alex Dai <yu.dai@intel.com>
  28  */
  29 #include <linux/firmware.h>
  30 #include "i915_drv.h"
  31 #include "intel_guc.h"
  32
  33 /**
  34  * DOC: GuC-specific firmware loader
  35  *
  36  * intel_guc:
  37  * Top level structure of guc. It handles firmware loading and manages client
  38  * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
  39  * ExecList submission.
  40  *
  41  * Firmware versioning:
  42  * The firmware build process will generate a version header file with major and
  43  * minor version defined. The versions are built into CSS header of firmware.
  44  * i915 kernel driver set the minimal firmware version required per platform.
  45  * The firmware installation package will install (symbolic link) proper version
  46  * of firmware.
  47  *
  48  * GuC address space:
  49  * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
  50  * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
  51  * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
  52  * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
  53  *
  54  * Firmware log:
  55  * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
  56  * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
  57  * i915_guc_load_status will print out firmware loading status and scratch
  58  * registers value.
  59  *
  60  */
  61
  62 #define I915_SKL_GUC_UCODE "i915/skl_guc_ver6_1.bin"
  63 MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
  64
  65 #define I915_BXT_GUC_UCODE "i915/bxt_guc_ver8_7.bin"
  66 MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
  67
  68 /* User-friendly representation of an enum */
  69 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
  70 {
  71         switch (status) {
  72         case GUC_FIRMWARE_FAIL:
  73                 return "FAIL";
  74         case GUC_FIRMWARE_NONE:
  75                 return "NONE";
  76         case GUC_FIRMWARE_PENDING:
  77                 return "PENDING";
  78         case GUC_FIRMWARE_SUCCESS:
  79                 return "SUCCESS";
  80         default:
  81                 return "UNKNOWN!";
  82         }
  83 };
  84
  85 static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
  86 {
  87         struct intel_engine_cs *engine;
  88         int irqs;
  89
  90         /* tell all command streamers NOT to forward interrupts or vblank to GuC */
  91         irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
  92         irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
  93         for_each_engine(engine, dev_priv)
  94                 I915_WRITE(RING_MODE_GEN7(engine), irqs);
  95
  96         /* route all GT interrupts to the host */
  97         I915_WRITE(GUC_BCS_RCS_IER, 0);
  98         I915_WRITE(GUC_VCS2_VCS1_IER, 0);
  99         I915_WRITE(GUC_WD_VECS_IER, 0);
 100 }
 101
 102 static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 103 {
 104         struct intel_engine_cs *engine;
 105         int irqs;
 106         u32 tmp;
 107
 108         /* tell all command streamers to forward interrupts (but not vblank) to GuC */
 109         irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
 110         for_each_engine(engine, dev_priv)
 111                 I915_WRITE(RING_MODE_GEN7(engine), irqs);
 112
 113         /* route USER_INTERRUPT to Host, all others are sent to GuC. */
 114         irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
 115                GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
 116         /* These three registers have the same bit definitions */
 117         I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
 118         I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
 119         I915_WRITE(GUC_WD_VECS_IER, ~irqs);
 120
 121         /*
 122          * If GuC has routed PM interrupts to itself, don't keep it.
 123          * and keep other interrupts those are unmasked by GuC.
 124         */
 125         tmp = I915_READ(GEN6_PMINTRMSK);
 126         if (tmp & GEN8_PMINTR_REDIRECT_TO_NON_DISP) {
 127                 dev_priv->rps.pm_intr_keep |= ~(tmp & ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
 128                 dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
 129         }
 130 }
 131
 132 static u32 get_gttype(struct drm_i915_private *dev_priv)
 133 {
 134         /* XXX: GT type based on PCI device ID? field seems unused by fw */
 135         return 0;
 136 }
 137
 138 static u32 get_core_family(struct drm_i915_private *dev_priv)
 139 {
 140         switch (INTEL_INFO(dev_priv)->gen) {
 141         case 9:
 142                 return GFXCORE_FAMILY_GEN9;
 143
 144         default:
 145                 DRM_ERROR("GUC: unsupported core family\n");
 146                 return GFXCORE_FAMILY_UNKNOWN;
 147         }
 148 }
 149
 150 static void set_guc_init_params(struct drm_i915_private *dev_priv)
 151 {
 152         struct intel_guc *guc = &dev_priv->guc;
 153         u32 params[GUC_CTL_MAX_DWORDS];
 154         int i;
 155
 156         memset(&params, 0, sizeof(params));
 157
 158         params[GUC_CTL_DEVICE_INFO] |=
 159                 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
 160                 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
 161
 162         /*
 163          * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
 164          * second. This ARAR is calculated by:
 165          * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
 166          */
 167         params[GUC_CTL_ARAT_HIGH] = 0;
 168         params[GUC_CTL_ARAT_LOW] = 100000000;
 169
 170         params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
 171
 172         params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 173                         GUC_CTL_VCS2_ENABLED;
 174
 175         if (i915.guc_log_level >= 0) {
 176                 params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
 177                 params[GUC_CTL_DEBUG] =
 178                         i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
 179         }
 180
 181         if (guc->ads_obj) {
 182                 u32 ads = (u32)i915_gem_obj_ggtt_offset(guc->ads_obj)
 183                                 >> PAGE_SHIFT;
 184                 params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
 185                 params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
 186         }
 187
 188         /* If GuC submission is enabled, set up additional parameters here */
 189         if (i915.enable_guc_submission) {
 190                 u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj);
 191                 u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
 192
 193                 pgs >>= PAGE_SHIFT;
 194                 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
 195                         (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
 196
 197                 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
 198
 199                 /* Unmask this bit to enable the GuC's internal scheduler */
 200                 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
 201         }
 202
 203         I915_WRITE(SOFT_SCRATCH(0), 0);
 204
 205         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 206                 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
 207 }
 208
 209 /*
 210  * Read the GuC status register (GUC_STATUS) and store it in the
 211  * specified location; then return a boolean indicating whether
 212  * the value matches either of two values representing completion
 213  * of the GuC boot process.
 214  *
 215  * This is used for polling the GuC status in a wait_for()
 216  * loop below.
 217  */
 218 static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
 219                                       u32 *status)
 220 {
 221         u32 val = I915_READ(GUC_STATUS);
 222         u32 uk_val = val & GS_UKERNEL_MASK;
 223         *status = val;
 224         return (uk_val == GS_UKERNEL_READY ||
 225                 ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
 226 }
 227
 228 /*
 229  * Transfer the firmware image to RAM for execution by the microcontroller.
 230  *
 231  * Architecturally, the DMA engine is bidirectional, and can potentially even
 232  * transfer between GTT locations. This functionality is left out of the API
 233  * for now as there is no need for it.
 234  *
 235  * Note that GuC needs the CSS header plus uKernel code to be copied by the
 236  * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
 237  */
 238 static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
 239 {
 240         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 241         struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
 242         unsigned long offset;
 243         struct sg_table *sg = fw_obj->pages;
 244         u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
 245         int i, ret = 0;
 246
 247         /* where RSA signature starts */
 248         offset = guc_fw->rsa_offset;
 249
 250         /* Copy RSA signature from the fw image to HW for verification */
 251         sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
 252         for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
 253                 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
 254
 255         /* The header plus uCode will be copied to WOPCM via DMA, excluding any
 256          * other components */
 257         I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
 258
 259         /* Set the source address for the new blob */
 260         offset = i915_gem_obj_ggtt_offset(fw_obj) + guc_fw->header_offset;
 261         I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 262         I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 263
 264         /*
 265          * Set the DMA destination. Current uCode expects the code to be
 266          * loaded at 8k; locations below this are used for the stack.
 267          */
 268         I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
 269         I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 270
 271         /* Finally start the DMA */
 272         I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
 273
 274         /*
 275          * Wait for the DMA to complete & the GuC to start up.
 276          * NB: Docs recommend not using the interrupt for completion.
 277          * Measurements indicate this should take no more than 20ms, so a
 278          * timeout here indicates that the GuC has failed and is unusable.
 279          * (Higher levels of the driver will attempt to fall back to
 280          * execlist mode if this happens.)
 281          */
 282         ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
 283
 284         DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
 285                         I915_READ(DMA_CTRL), status);
 286
 287         if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
 288                 DRM_ERROR("GuC firmware signature verification failed\n");
 289                 ret = -ENOEXEC;
 290         }
 291
 292         DRM_DEBUG_DRIVER("returning %d\n", ret);
 293
 294         return ret;
 295 }
 296
 297 static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
 298 {
 299         u32 wopcm_size = GUC_WOPCM_TOP;
 300
 301         /* On BXT, the top of WOPCM is reserved for RC6 context */
 302         if (IS_BROXTON(dev_priv))
 303                 wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
 304
 305         return wopcm_size;
 306 }
 307
 308 /*
 309  * Load the GuC firmware blob into the MinuteIA.
 310  */
 311 static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 312 {
 313         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 314         struct drm_device *dev = dev_priv->dev;
 315         int ret;
 316
 317         ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
 318         if (ret) {
 319                 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
 320                 return ret;
 321         }
 322
 323         ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
 324         if (ret) {
 325                 DRM_DEBUG_DRIVER("pin failed %d\n", ret);
 326                 return ret;
 327         }
 328
 329         /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
 330         I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 331
 332         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 333
 334         /* init WOPCM */
 335         I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
 336         I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
 337
 338         /* Enable MIA caching. GuC clock gating is disabled. */
 339         I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 340
 341         /* WaDisableMinuteIaClockGating:skl,bxt */
 342         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 343             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 344                 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
 345                                               ~GUC_ENABLE_MIA_CLOCK_GATING));
 346         }
 347
 348         /* WaC6DisallowByGfxPause*/
 349         I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
 350
 351         if (IS_BROXTON(dev))
 352                 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 353         else
 354                 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 355
 356         if (IS_GEN9(dev)) {
 357                 /* DOP Clock Gating Enable for GuC clocks */
 358                 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
 359                                             I915_READ(GEN7_MISCCPCTL)));
 360
 361                 /* allows for 5us before GT can go to RC6 */
 362                 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
 363         }
 364
 365         set_guc_init_params(dev_priv);
 366
 367         ret = guc_ucode_xfer_dma(dev_priv);
 368
 369         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 370
 371         /*
 372          * We keep the object pages for reuse during resume. But we can unpin it
 373          * now that DMA has completed, so it doesn't continue to take up space.
 374          */
 375         i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
 376
 377         return ret;
 378 }
 379
 380 static int i915_reset_guc(struct drm_i915_private *dev_priv)
 381 {
 382         int ret;
 383         u32 guc_status;
 384
 385         ret = intel_guc_reset(dev_priv);
 386         if (ret) {
 387                 DRM_ERROR("GuC reset failed, ret = %d\n", ret);
 388                 return ret;
 389         }
 390
 391         guc_status = I915_READ(GUC_STATUS);
 392         WARN(!(guc_status & GS_MIA_IN_RESET),
 393              "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status);
 394
 395         return ret;
 396 }
 397
 398 /**
 399  * intel_guc_setup() - finish preparing the GuC for activity
 400  * @dev:        drm device
 401  *
 402  * Called from gem_init_hw() during driver loading and also after a GPU reset.
 403  *
 404  * The main action required here it to load the GuC uCode into the device.
 405  * The firmware image should have already been fetched into memory by the
 406  * earlier call to intel_guc_init(), so here we need only check that worked,
 407  * and then transfer the image to the h/w.
 408  *
 409  * Return:      non-zero code on error
 410  */
 411 int intel_guc_setup(struct drm_device *dev)
 412 {
 413         struct drm_i915_private *dev_priv = dev->dev_private;
 414         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 415         const char *fw_path = guc_fw->guc_fw_path;
 416         int retries, ret, err;
 417
 418         DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
 419                 fw_path,
 420                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 421                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 422
 423         /* Loading forbidden, or no firmware to load? */
 424         if (!i915.enable_guc_loading) {
 425                 err = 0;
 426                 goto fail;
 427         } else if (fw_path == NULL) {
 428                 /* Device is known to have no uCode (e.g. no GuC) */
 429                 err = -ENXIO;
 430                 goto fail;
 431         } else if (*fw_path == '\0') {
 432                 /* Device has a GuC but we don't know what f/w to load? */
 433                 DRM_INFO("No GuC firmware known for this platform\n");
 434                 err = -ENODEV;
 435                 goto fail;
 436         }
 437
 438         /* Fetch failed, or already fetched but failed to load? */
 439         if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
 440                 err = -EIO;
 441                 goto fail;
 442         } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
 443                 err = -ENOEXEC;
 444                 goto fail;
 445         }
 446
 447         direct_interrupts_to_host(dev_priv);
 448
 449         guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
 450
 451         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 452                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 453                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 454
 455         err = i915_guc_submission_init(dev_priv);
 456         if (err)
 457                 goto fail;
 458
 459         /*
 460          * WaEnableuKernelHeaderValidFix:skl,bxt
 461          * For BXT, this is only upto B0 but below WA is required for later
 462          * steppings also so this is extended as well.
 463          */
 464         /* WaEnableGuCBootHashCheckNotSet:skl,bxt */
 465         for (retries = 3; ; ) {
 466                 /*
 467                  * Always reset the GuC just before (re)loading, so
 468                  * that the state and timing are fairly predictable
 469                  */
 470                 err = i915_reset_guc(dev_priv);
 471                 if (err) {
 472                         DRM_ERROR("GuC reset failed: %d\n", err);
 473                         goto fail;
 474                 }
 475
 476                 err = guc_ucode_xfer(dev_priv);
 477                 if (!err)
 478                         break;
 479
 480                 if (--retries == 0)
 481                         goto fail;
 482
 483                 DRM_INFO("GuC fw load failed: %d; will reset and "
 484                          "retry %d more time(s)\n", err, retries);
 485         }
 486
 487         guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
 488
 489         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 490                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 491                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 492
 493         if (i915.enable_guc_submission) {
 494                 err = i915_guc_submission_enable(dev_priv);
 495                 if (err)
 496                         goto fail;
 497                 direct_interrupts_to_guc(dev_priv);
 498         }
 499
 500         return 0;
 501
 502 fail:
 503         if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
 504                 guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
 505
 506         direct_interrupts_to_host(dev_priv);
 507         i915_guc_submission_disable(dev_priv);
 508         i915_guc_submission_fini(dev_priv);
 509
 510         /*
 511          * We've failed to load the firmware :(
 512          *
 513          * Decide whether to disable GuC submission and fall back to
 514          * execlist mode, and whether to hide the error by returning
 515          * zero or to return -EIO, which the caller will treat as a
 516          * nonfatal error (i.e. it doesn't prevent driver load, but
 517          * marks the GPU as wedged until reset).
 518          */
 519         if (i915.enable_guc_loading > 1) {
 520                 ret = -EIO;
 521         } else if (i915.enable_guc_submission > 1) {
 522                 ret = -EIO;
 523         } else {
 524                 ret = 0;
 525         }
 526
 527         if (err == 0 && !HAS_GUC_UCODE(dev))
 528                 ;       /* Don't mention the GuC! */
 529         else if (err == 0)
 530                 DRM_INFO("GuC firmware load skipped\n");
 531         else if (ret != -EIO)
 532                 DRM_INFO("GuC firmware load failed: %d\n", err);
 533         else
 534                 DRM_ERROR("GuC firmware load failed: %d\n", err);
 535
 536         if (i915.enable_guc_submission) {
 537                 if (fw_path == NULL)
 538                         DRM_INFO("GuC submission without firmware not supported\n");
 539                 if (ret == 0)
 540                         DRM_INFO("Falling back from GuC submission to execlist mode\n");
 541                 else
 542                         DRM_ERROR("GuC init failed: %d\n", ret);
 543         }
 544         i915.enable_guc_submission = 0;
 545
 546         return ret;
 547 }
 548
 549 static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
 550 {
 551         struct drm_i915_gem_object *obj;
 552         const struct firmware *fw;
 553         struct guc_css_header *css;
 554         size_t size;
 555         int err;
 556
 557         DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
 558                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
 559
 560         err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
 561         if (err)
 562                 goto fail;
 563         if (!fw)
 564                 goto fail;
 565
 566         DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
 567                 guc_fw->guc_fw_path, fw);
 568
 569         /* Check the size of the blob before examining buffer contents */
 570         if (fw->size < sizeof(struct guc_css_header)) {
 571                 DRM_ERROR("Firmware header is missing\n");
 572                 goto fail;
 573         }
 574
 575         css = (struct guc_css_header *)fw->data;
 576
 577         /* Firmware bits always start from header */
 578         guc_fw->header_offset = 0;
 579         guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
 580                 css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
 581
 582         if (guc_fw->header_size != sizeof(struct guc_css_header)) {
 583                 DRM_ERROR("CSS header definition mismatch\n");
 584                 goto fail;
 585         }
 586
 587         /* then, uCode */
 588         guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
 589         guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
 590
 591         /* now RSA */
 592         if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
 593                 DRM_ERROR("RSA key size is bad\n");
 594                 goto fail;
 595         }
 596         guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
 597         guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
 598
 599         /* At least, it should have header, uCode and RSA. Size of all three. */
 600         size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
 601         if (fw->size < size) {
 602                 DRM_ERROR("Missing firmware components\n");
 603                 goto fail;
 604         }
 605
 606         /* Header and uCode will be loaded to WOPCM. Size of the two. */
 607         size = guc_fw->header_size + guc_fw->ucode_size;
 608         if (size > guc_wopcm_size(dev->dev_private)) {
 609                 DRM_ERROR("Firmware is too large to fit in WOPCM\n");
 610                 goto fail;
 611         }
 612
 613         /*
 614          * The GuC firmware image has the version number embedded at a well-known
 615          * offset within the firmware blob; note that major / minor version are
 616          * TWO bytes each (i.e. u16), although all pointers and offsets are defined
 617          * in terms of bytes (u8).
 618          */
 619         guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
 620         guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
 621
 622         if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
 623             guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
 624                 DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
 625                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
 626                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
 627                 err = -ENOEXEC;
 628                 goto fail;
 629         }
 630
 631         DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
 632                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
 633                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
 634
 635         mutex_lock(&dev->struct_mutex);
 636         obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
 637         mutex_unlock(&dev->struct_mutex);
 638         if (IS_ERR_OR_NULL(obj)) {
 639                 err = obj ? PTR_ERR(obj) : -ENOMEM;
 640                 goto fail;
 641         }
 642
 643         guc_fw->guc_fw_obj = obj;
 644         guc_fw->guc_fw_size = fw->size;
 645
 646         DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
 647                         guc_fw->guc_fw_obj);
 648
 649         release_firmware(fw);
 650         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
 651         return;
 652
 653 fail:
 654         DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
 655                 err, fw, guc_fw->guc_fw_obj);
 656         DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
 657                   guc_fw->guc_fw_path, err);
 658
 659         mutex_lock(&dev->struct_mutex);
 660         obj = guc_fw->guc_fw_obj;
 661         if (obj)
 662                 drm_gem_object_unreference(&obj->base);
 663         guc_fw->guc_fw_obj = NULL;
 664         mutex_unlock(&dev->struct_mutex);
 665
 666         release_firmware(fw);           /* OK even if fw is NULL */
 667         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
 668 }
 669
 670 /**
 671  * intel_guc_init() - define parameters and fetch firmware
 672  * @dev:        drm device
 673  *
 674  * Called early during driver load, but after GEM is initialised.
 675  *
 676  * The firmware will be transferred to the GuC's memory later,
 677  * when intel_guc_setup() is called.
 678  */
 679 void intel_guc_init(struct drm_device *dev)
 680 {
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 683         const char *fw_path;
 684
 685         /* A negative value means "use platform default" */
 686         if (i915.enable_guc_loading < 0)
 687                 i915.enable_guc_loading = HAS_GUC_UCODE(dev);
 688         if (i915.enable_guc_submission < 0)
 689                 i915.enable_guc_submission = HAS_GUC_SCHED(dev);
 690
 691         if (!HAS_GUC_UCODE(dev)) {
 692                 fw_path = NULL;
 693         } else if (IS_SKYLAKE(dev)) {
 694                 fw_path = I915_SKL_GUC_UCODE;
 695                 guc_fw->guc_fw_major_wanted = 6;
 696                 guc_fw->guc_fw_minor_wanted = 1;
 697         } else if (IS_BROXTON(dev)) {
 698                 fw_path = I915_BXT_GUC_UCODE;
 699                 guc_fw->guc_fw_major_wanted = 8;
 700                 guc_fw->guc_fw_minor_wanted = 7;
 701         } else {
 702                 fw_path = "";   /* unknown device */
 703         }
 704
 705         guc_fw->guc_dev = dev;
 706         guc_fw->guc_fw_path = fw_path;
 707         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 708         guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
 709
 710         /* Early (and silent) return if GuC loading is disabled */
 711         if (!i915.enable_guc_loading)
 712                 return;
 713         if (fw_path == NULL)
 714                 return;
 715         if (*fw_path == '\0')
 716                 return;
 717
 718         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
 719         DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
 720         guc_fw_fetch(dev, guc_fw);
 721         /* status must now be FAIL or SUCCESS */
 722 }
 723
 724 /**
 725  * intel_guc_fini() - clean up all allocated resources
 726  * @dev:        drm device
 727  */
 728 void intel_guc_fini(struct drm_device *dev)
 729 {
 730         struct drm_i915_private *dev_priv = dev->dev_private;
 731         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 732
 733         mutex_lock(&dev->struct_mutex);
 734         direct_interrupts_to_host(dev_priv);
 735         i915_guc_submission_disable(dev_priv);
 736         i915_guc_submission_fini(dev_priv);
 737
 738         if (guc_fw->guc_fw_obj)
 739                 drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
 740         guc_fw->guc_fw_obj = NULL;
 741         mutex_unlock(&dev->struct_mutex);
 742
 743         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 744 }