2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Vinit Azad <vinit.azad@intel.com>
25 * Ben Widawsky <ben@bwidawsk.net>
26 * Dave Gordon <david.s.gordon@intel.com>
27 * Alex Dai <yu.dai@intel.com>
29 #include <linux/firmware.h>
31 #include "intel_guc.h"
37 * Top level structure of guc. It handles firmware loading and manages client
38 * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
39 * ExecList submission.
41 * Firmware versioning:
42 * The firmware build process will generate a version header file with major and
43 * minor version defined. The versions are built into CSS header of firmware.
44 * i915 kernel driver set the minimal firmware version required per platform.
45 * The firmware installation package will install (symbolic link) proper version
49 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
50 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
51 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
52 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
55 * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
56 * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
57 * i915_guc_load_status will print out firmware loading status and scratch
62 #define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin"
63 MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
65 /* User-friendly representation of an enum */
66 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
69 case GUC_FIRMWARE_FAIL:
71 case GUC_FIRMWARE_NONE:
73 case GUC_FIRMWARE_PENDING:
75 case GUC_FIRMWARE_SUCCESS:
82 static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
84 struct intel_engine_cs *ring;
87 /* tell all command streamers NOT to forward interrupts and vblank to GuC */
88 irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
89 irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
90 for_each_ring(ring, dev_priv, i)
91 I915_WRITE(RING_MODE_GEN7(ring), irqs);
93 /* tell DE to send nothing to GuC */
94 I915_WRITE(DE_GUCRMR, ~0);
96 /* route all GT interrupts to the host */
97 I915_WRITE(GUC_BCS_RCS_IER, 0);
98 I915_WRITE(GUC_VCS2_VCS1_IER, 0);
99 I915_WRITE(GUC_WD_VECS_IER, 0);
102 static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
104 struct intel_engine_cs *ring;
107 /* tell all command streamers to forward interrupts and vblank to GuC */
108 irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_ALWAYS);
109 irqs |= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
110 for_each_ring(ring, dev_priv, i)
111 I915_WRITE(RING_MODE_GEN7(ring), irqs);
113 /* tell DE to send (all) flip_done to GuC */
114 irqs = DERRMR_PIPEA_PRI_FLIP_DONE | DERRMR_PIPEA_SPR_FLIP_DONE |
115 DERRMR_PIPEB_PRI_FLIP_DONE | DERRMR_PIPEB_SPR_FLIP_DONE |
116 DERRMR_PIPEC_PRI_FLIP_DONE | DERRMR_PIPEC_SPR_FLIP_DONE;
117 /* Unmasked bits will cause GuC response message to be sent */
118 I915_WRITE(DE_GUCRMR, ~irqs);
120 /* route USER_INTERRUPT to Host, all others are sent to GuC. */
121 irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
122 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
123 /* These three registers have the same bit definitions */
124 I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
125 I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
126 I915_WRITE(GUC_WD_VECS_IER, ~irqs);
129 static u32 get_gttype(struct drm_i915_private *dev_priv)
131 /* XXX: GT type based on PCI device ID? field seems unused by fw */
135 static u32 get_core_family(struct drm_i915_private *dev_priv)
137 switch (INTEL_INFO(dev_priv)->gen) {
139 return GFXCORE_FAMILY_GEN9;
142 DRM_ERROR("GUC: unsupported core family\n");
143 return GFXCORE_FAMILY_UNKNOWN;
147 static void set_guc_init_params(struct drm_i915_private *dev_priv)
149 struct intel_guc *guc = &dev_priv->guc;
150 u32 params[GUC_CTL_MAX_DWORDS];
153 memset(¶ms, 0, sizeof(params));
155 params[GUC_CTL_DEVICE_INFO] |=
156 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
157 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
160 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
161 * second. This ARAR is calculated by:
162 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
164 params[GUC_CTL_ARAT_HIGH] = 0;
165 params[GUC_CTL_ARAT_LOW] = 100000000;
167 params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
169 params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
170 GUC_CTL_VCS2_ENABLED;
172 if (i915.guc_log_level >= 0) {
173 params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
174 params[GUC_CTL_DEBUG] =
175 i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
178 /* If GuC submission is enabled, set up additional parameters here */
179 if (i915.enable_guc_submission) {
180 u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj);
181 u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
184 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
185 (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
187 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
189 /* Unmask this bit to enable the GuC's internal scheduler */
190 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
193 I915_WRITE(SOFT_SCRATCH(0), 0);
195 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
196 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
200 * Read the GuC status register (GUC_STATUS) and store it in the
201 * specified location; then return a boolean indicating whether
202 * the value matches either of two values representing completion
203 * of the GuC boot process.
205 * This is used for polling the GuC status in a wait_for_atomic()
208 static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
211 u32 val = I915_READ(GUC_STATUS);
213 return ((val & GS_UKERNEL_MASK) == GS_UKERNEL_READY ||
214 (val & GS_UKERNEL_MASK) == GS_UKERNEL_LAPIC_DONE);
218 * Transfer the firmware image to RAM for execution by the microcontroller.
220 * GuC Firmware layout:
221 * +-------------------------------+ ----
222 * | CSS header | 128B
223 * | contains major/minor version |
224 * +-------------------------------+ ----
226 * +-------------------------------+ ----
227 * | RSA signature | 256B
228 * +-------------------------------+ ----
230 * Architecturally, the DMA engine is bidirectional, and can potentially even
231 * transfer between GTT locations. This functionality is left out of the API
232 * for now as there is no need for it.
234 * Note that GuC needs the CSS header plus uKernel code to be copied by the
235 * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
238 #define UOS_CSS_HEADER_OFFSET 0
239 #define UOS_VER_MINOR_OFFSET 0x44
240 #define UOS_VER_MAJOR_OFFSET 0x46
241 #define UOS_CSS_HEADER_SIZE 0x80
242 #define UOS_RSA_SIG_SIZE 0x100
244 static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
246 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
247 struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
248 unsigned long offset;
249 struct sg_table *sg = fw_obj->pages;
250 u32 status, ucode_size, rsa[UOS_RSA_SIG_SIZE / sizeof(u32)];
253 /* uCode size, also is where RSA signature starts */
254 offset = ucode_size = guc_fw->guc_fw_size - UOS_RSA_SIG_SIZE;
255 I915_WRITE(DMA_COPY_SIZE, ucode_size);
257 /* Copy RSA signature from the fw image to HW for verification */
258 sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, UOS_RSA_SIG_SIZE, offset);
259 for (i = 0; i < UOS_RSA_SIG_SIZE / sizeof(u32); i++)
260 I915_WRITE(UOS_RSA_SCRATCH_0 + i * sizeof(u32), rsa[i]);
262 /* Set the source address for the new blob */
263 offset = i915_gem_obj_ggtt_offset(fw_obj);
264 I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
265 I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
268 * Set the DMA destination. Current uCode expects the code to be
269 * loaded at 8k; locations below this are used for the stack.
271 I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
272 I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
274 /* Finally start the DMA */
275 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
278 * Spin-wait for the DMA to complete & the GuC to start up.
279 * NB: Docs recommend not using the interrupt for completion.
280 * Measurements indicate this should take no more than 20ms, so a
281 * timeout here indicates that the GuC has failed and is unusable.
282 * (Higher levels of the driver will attempt to fall back to
283 * execlist mode if this happens.)
285 ret = wait_for_atomic(guc_ucode_response(dev_priv, &status), 100);
287 DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
288 I915_READ(DMA_CTRL), status);
290 if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
291 DRM_ERROR("GuC firmware signature verification failed\n");
295 DRM_DEBUG_DRIVER("returning %d\n", ret);
301 * Load the GuC firmware blob into the MinuteIA.
303 static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
305 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
306 struct drm_device *dev = dev_priv->dev;
309 ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
311 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
315 ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
317 DRM_DEBUG_DRIVER("pin failed %d\n", ret);
321 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
322 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
324 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
327 I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
328 I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
330 /* Enable MIA caching. GuC clock gating is disabled. */
331 I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
333 /* WaDisableMinuteIaClockGating:skl,bxt */
334 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
335 (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) {
336 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
337 ~GUC_ENABLE_MIA_CLOCK_GATING));
340 /* WaC6DisallowByGfxPause*/
341 I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
344 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
346 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
349 /* DOP Clock Gating Enable for GuC clocks */
350 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
351 I915_READ(GEN7_MISCCPCTL)));
353 /* allows for 5us before GT can go to RC6 */
354 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
357 set_guc_init_params(dev_priv);
359 ret = guc_ucode_xfer_dma(dev_priv);
361 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
364 * We keep the object pages for reuse during resume. But we can unpin it
365 * now that DMA has completed, so it doesn't continue to take up space.
367 i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
373 * intel_guc_ucode_load() - load GuC uCode into the device
376 * Called from gem_init_hw() during driver loading and also after a GPU reset.
378 * The firmware image should have already been fetched into memory by the
379 * earlier call to intel_guc_ucode_init(), so here we need only check that
380 * is succeeded, and then transfer the image to the h/w.
382 * Return: non-zero code on error
384 int intel_guc_ucode_load(struct drm_device *dev)
386 struct drm_i915_private *dev_priv = dev->dev_private;
387 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
390 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
391 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
392 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
394 direct_interrupts_to_host(dev_priv);
395 i915_guc_submission_disable(dev);
397 if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_NONE)
400 if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS &&
401 guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL)
404 guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
406 DRM_DEBUG_DRIVER("GuC fw fetch status %s\n",
407 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
409 switch (guc_fw->guc_fw_fetch_status) {
410 case GUC_FIRMWARE_FAIL:
411 /* something went wrong :( */
415 case GUC_FIRMWARE_NONE:
416 case GUC_FIRMWARE_PENDING:
419 WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n",
421 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
422 guc_fw->guc_fw_fetch_status);
426 case GUC_FIRMWARE_SUCCESS:
430 err = i915_guc_submission_init(dev);
434 err = guc_ucode_xfer(dev_priv);
438 guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
440 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
441 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
442 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
444 if (i915.enable_guc_submission) {
445 err = i915_guc_submission_enable(dev);
448 direct_interrupts_to_guc(dev_priv);
454 if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
455 guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
457 direct_interrupts_to_host(dev_priv);
458 i915_guc_submission_disable(dev);
463 static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
465 struct drm_i915_gem_object *obj;
466 const struct firmware *fw;
467 const u8 *css_header;
468 const size_t minsize = UOS_CSS_HEADER_SIZE + UOS_RSA_SIG_SIZE;
469 const size_t maxsize = GUC_WOPCM_SIZE_VALUE + UOS_RSA_SIG_SIZE
470 - 0x8000; /* 32k reserved (8K stack + 24k context) */
473 DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
474 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
476 err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
482 DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
483 guc_fw->guc_fw_path, fw);
484 DRM_DEBUG_DRIVER("firmware file size %zu (minimum %zu, maximum %zu)\n",
485 fw->size, minsize, maxsize);
487 /* Check the size of the blob befoe examining buffer contents */
488 if (fw->size < minsize || fw->size > maxsize)
492 * The GuC firmware image has the version number embedded at a well-known
493 * offset within the firmware blob; note that major / minor version are
494 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
495 * in terms of bytes (u8).
497 css_header = fw->data + UOS_CSS_HEADER_OFFSET;
498 guc_fw->guc_fw_major_found = *(u16 *)(css_header + UOS_VER_MAJOR_OFFSET);
499 guc_fw->guc_fw_minor_found = *(u16 *)(css_header + UOS_VER_MINOR_OFFSET);
501 if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
502 guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
503 DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
504 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
505 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
510 DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
511 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
512 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
514 obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
515 if (IS_ERR_OR_NULL(obj)) {
516 err = obj ? PTR_ERR(obj) : -ENOMEM;
520 guc_fw->guc_fw_obj = obj;
521 guc_fw->guc_fw_size = fw->size;
523 DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
526 release_firmware(fw);
527 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
531 DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
532 err, fw, guc_fw->guc_fw_obj);
533 DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
534 guc_fw->guc_fw_path, err);
536 obj = guc_fw->guc_fw_obj;
538 drm_gem_object_unreference(&obj->base);
539 guc_fw->guc_fw_obj = NULL;
541 release_firmware(fw); /* OK even if fw is NULL */
542 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
546 * intel_guc_ucode_init() - define parameters and fetch firmware
549 * Called early during driver load, but after GEM is initialised.
550 * The device struct_mutex must be held by the caller, as we're
551 * going to allocate a GEM object to hold the firmware image.
553 * The firmware will be transferred to the GuC's memory later,
554 * when intel_guc_ucode_load() is called.
556 void intel_guc_ucode_init(struct drm_device *dev)
558 struct drm_i915_private *dev_priv = dev->dev_private;
559 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
562 if (!HAS_GUC_SCHED(dev))
563 i915.enable_guc_submission = false;
565 if (!HAS_GUC_UCODE(dev)) {
567 } else if (IS_SKYLAKE(dev)) {
568 fw_path = I915_SKL_GUC_UCODE;
569 guc_fw->guc_fw_major_wanted = 4;
570 guc_fw->guc_fw_minor_wanted = 3;
572 i915.enable_guc_submission = false;
573 fw_path = ""; /* unknown device */
576 guc_fw->guc_dev = dev;
577 guc_fw->guc_fw_path = fw_path;
578 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
579 guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
584 if (*fw_path == '\0') {
585 DRM_ERROR("No GuC firmware known for this platform\n");
586 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
590 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
591 DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
592 guc_fw_fetch(dev, guc_fw);
593 /* status must now be FAIL or SUCCESS */
597 * intel_guc_ucode_fini() - clean up all allocated resources
600 void intel_guc_ucode_fini(struct drm_device *dev)
602 struct drm_i915_private *dev_priv = dev->dev_private;
603 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
605 direct_interrupts_to_host(dev_priv);
606 i915_guc_submission_fini(dev);
608 if (guc_fw->guc_fw_obj)
609 drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
610 guc_fw->guc_fw_obj = NULL;
612 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;