2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Vinit Azad <vinit.azad@intel.com>
25 * Ben Widawsky <ben@bwidawsk.net>
26 * Dave Gordon <david.s.gordon@intel.com>
27 * Alex Dai <yu.dai@intel.com>
29 #include <linux/firmware.h>
31 #include "intel_guc.h"
34 * DOC: GuC-specific firmware loader
37 * Top level structure of guc. It handles firmware loading and manages client
38 * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
39 * ExecList submission.
41 * Firmware versioning:
42 * The firmware build process will generate a version header file with major and
43 * minor version defined. The versions are built into CSS header of firmware.
44 * i915 kernel driver set the minimal firmware version required per platform.
45 * The firmware installation package will install (symbolic link) proper version
49 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
50 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
51 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
52 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
55 * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
56 * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
57 * i915_guc_load_status will print out firmware loading status and scratch
62 #define SKL_FW_MAJOR 6
63 #define SKL_FW_MINOR 1
65 #define BXT_FW_MAJOR 8
66 #define BXT_FW_MINOR 7
68 #define KBL_FW_MAJOR 9
69 #define KBL_FW_MINOR 14
71 #define GUC_FW_PATH(platform, major, minor) \
72 "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"
74 #define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
75 MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
77 #define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
78 MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
80 #define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
81 MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
83 /* User-friendly representation of an enum */
84 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
87 case GUC_FIRMWARE_FAIL:
89 case GUC_FIRMWARE_NONE:
91 case GUC_FIRMWARE_PENDING:
93 case GUC_FIRMWARE_SUCCESS:
100 static void guc_interrupts_release(struct drm_i915_private *dev_priv)
102 struct intel_engine_cs *engine;
105 /* tell all command streamers NOT to forward interrupts or vblank to GuC */
106 irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
107 irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
108 for_each_engine(engine, dev_priv)
109 I915_WRITE(RING_MODE_GEN7(engine), irqs);
111 /* route all GT interrupts to the host */
112 I915_WRITE(GUC_BCS_RCS_IER, 0);
113 I915_WRITE(GUC_VCS2_VCS1_IER, 0);
114 I915_WRITE(GUC_WD_VECS_IER, 0);
117 static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
119 struct intel_engine_cs *engine;
123 /* tell all command streamers to forward interrupts (but not vblank) to GuC */
124 irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
125 for_each_engine(engine, dev_priv)
126 I915_WRITE(RING_MODE_GEN7(engine), irqs);
128 /* route USER_INTERRUPT to Host, all others are sent to GuC. */
129 irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
130 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
131 /* These three registers have the same bit definitions */
132 I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
133 I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
134 I915_WRITE(GUC_WD_VECS_IER, ~irqs);
137 * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
138 * (unmasked) PM interrupts to the GuC. All other bits of this
139 * register *disable* generation of a specific interrupt.
141 * 'pm_intr_keep' indicates bits that are NOT to be set when
142 * writing to the PM interrupt mask register, i.e. interrupts
143 * that must not be disabled.
145 * If the GuC is handling these interrupts, then we must not let
146 * the PM code disable ANY interrupt that the GuC is expecting.
147 * So for each ENABLED (0) bit in this register, we must SET the
148 * bit in pm_intr_keep so that it's left enabled for the GuC.
150 * OTOH the REDIRECT_TO_GUC bit is initially SET in pm_intr_keep
151 * (so interrupts go to the DISPLAY unit at first); but here we
152 * need to CLEAR that bit, which will result in the register bit
155 tmp = I915_READ(GEN6_PMINTRMSK);
156 if (tmp & GEN8_PMINTR_REDIRECT_TO_GUC) {
157 dev_priv->rps.pm_intr_keep |= ~tmp;
158 dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_GUC;
162 static u32 get_gttype(struct drm_i915_private *dev_priv)
164 /* XXX: GT type based on PCI device ID? field seems unused by fw */
168 static u32 get_core_family(struct drm_i915_private *dev_priv)
170 u32 gen = INTEL_GEN(dev_priv);
174 return GFXCORE_FAMILY_GEN9;
177 WARN(1, "GEN%d does not support GuC operation!\n", gen);
178 return GFXCORE_FAMILY_UNKNOWN;
183 * Initialise the GuC parameter block before starting the firmware
184 * transfer. These parameters are read by the firmware on startup
185 * and cannot be changed thereafter.
187 static void guc_params_init(struct drm_i915_private *dev_priv)
189 struct intel_guc *guc = &dev_priv->guc;
190 u32 params[GUC_CTL_MAX_DWORDS];
193 memset(¶ms, 0, sizeof(params));
195 params[GUC_CTL_DEVICE_INFO] |=
196 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
197 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
200 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
201 * second. This ARAR is calculated by:
202 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
204 params[GUC_CTL_ARAT_HIGH] = 0;
205 params[GUC_CTL_ARAT_LOW] = 100000000;
207 params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
209 params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
210 GUC_CTL_VCS2_ENABLED;
212 if (i915.guc_log_level >= 0) {
213 params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
214 params[GUC_CTL_DEBUG] =
215 i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
219 u32 ads = i915_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
220 params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
221 params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
224 /* If GuC submission is enabled, set up additional parameters here */
225 if (i915.enable_guc_submission) {
226 u32 pgs = i915_ggtt_offset(dev_priv->guc.ctx_pool_vma);
227 u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
230 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
231 (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
233 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
235 /* Unmask this bit to enable the GuC's internal scheduler */
236 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
239 I915_WRITE(SOFT_SCRATCH(0), 0);
241 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
242 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
246 * Read the GuC status register (GUC_STATUS) and store it in the
247 * specified location; then return a boolean indicating whether
248 * the value matches either of two values representing completion
249 * of the GuC boot process.
251 * This is used for polling the GuC status in a wait_for()
254 static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
257 u32 val = I915_READ(GUC_STATUS);
258 u32 uk_val = val & GS_UKERNEL_MASK;
260 return (uk_val == GS_UKERNEL_READY ||
261 ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
265 * Transfer the firmware image to RAM for execution by the microcontroller.
267 * Architecturally, the DMA engine is bidirectional, and can potentially even
268 * transfer between GTT locations. This functionality is left out of the API
269 * for now as there is no need for it.
271 * Note that GuC needs the CSS header plus uKernel code to be copied by the
272 * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
274 static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
275 struct i915_vma *vma)
277 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
278 unsigned long offset;
279 struct sg_table *sg = vma->pages;
280 u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
283 /* where RSA signature starts */
284 offset = guc_fw->rsa_offset;
286 /* Copy RSA signature from the fw image to HW for verification */
287 sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
288 for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
289 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
291 /* The header plus uCode will be copied to WOPCM via DMA, excluding any
292 * other components */
293 I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
295 /* Set the source address for the new blob */
296 offset = i915_ggtt_offset(vma) + guc_fw->header_offset;
297 I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
298 I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
301 * Set the DMA destination. Current uCode expects the code to be
302 * loaded at 8k; locations below this are used for the stack.
304 I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
305 I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
307 /* Finally start the DMA */
308 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
311 * Wait for the DMA to complete & the GuC to start up.
312 * NB: Docs recommend not using the interrupt for completion.
313 * Measurements indicate this should take no more than 20ms, so a
314 * timeout here indicates that the GuC has failed and is unusable.
315 * (Higher levels of the driver will attempt to fall back to
316 * execlist mode if this happens.)
318 ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
320 DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
321 I915_READ(DMA_CTRL), status);
323 if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
324 DRM_ERROR("GuC firmware signature verification failed\n");
328 DRM_DEBUG_DRIVER("returning %d\n", ret);
333 static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
335 u32 wopcm_size = GUC_WOPCM_TOP;
337 /* On BXT, the top of WOPCM is reserved for RC6 context */
338 if (IS_BROXTON(dev_priv))
339 wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
345 * Load the GuC firmware blob into the MinuteIA.
347 static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
349 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
350 struct drm_device *dev = &dev_priv->drm;
351 struct i915_vma *vma;
354 ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
356 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
360 vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
362 DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
366 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
367 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
369 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
372 I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
373 I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
375 /* Enable MIA caching. GuC clock gating is disabled. */
376 I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
378 /* WaDisableMinuteIaClockGating:bxt */
379 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
380 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
381 ~GUC_ENABLE_MIA_CLOCK_GATING));
384 /* WaC6DisallowByGfxPause:bxt */
385 if (IS_BXT_REVID(dev, 0, BXT_REVID_B0))
386 I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
389 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
391 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
394 /* DOP Clock Gating Enable for GuC clocks */
395 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
396 I915_READ(GEN7_MISCCPCTL)));
398 /* allows for 5us (in 10ns units) before GT can go to RC6 */
399 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
402 guc_params_init(dev_priv);
404 ret = guc_ucode_xfer_dma(dev_priv, vma);
406 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
409 * We keep the object pages for reuse during resume. But we can unpin it
410 * now that DMA has completed, so it doesn't continue to take up space.
417 static int guc_hw_reset(struct drm_i915_private *dev_priv)
422 ret = intel_guc_reset(dev_priv);
424 DRM_ERROR("GuC reset failed, ret = %d\n", ret);
428 guc_status = I915_READ(GUC_STATUS);
429 WARN(!(guc_status & GS_MIA_IN_RESET),
430 "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status);
436 * intel_guc_setup() - finish preparing the GuC for activity
439 * Called from gem_init_hw() during driver loading and also after a GPU reset.
441 * The main action required here it to load the GuC uCode into the device.
442 * The firmware image should have already been fetched into memory by the
443 * earlier call to intel_guc_init(), so here we need only check that worked,
444 * and then transfer the image to the h/w.
446 * Return: non-zero code on error
448 int intel_guc_setup(struct drm_device *dev)
450 struct drm_i915_private *dev_priv = to_i915(dev);
451 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
452 const char *fw_path = guc_fw->guc_fw_path;
453 int retries, ret, err;
455 DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
457 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
458 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
460 /* Loading forbidden, or no firmware to load? */
461 if (!i915.enable_guc_loading) {
464 } else if (fw_path == NULL) {
465 /* Device is known to have no uCode (e.g. no GuC) */
468 } else if (*fw_path == '\0') {
469 /* Device has a GuC but we don't know what f/w to load? */
470 WARN(1, "No GuC firmware known for this platform!\n");
475 /* Fetch failed, or already fetched but failed to load? */
476 if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
479 } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
484 guc_interrupts_release(dev_priv);
486 guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
488 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
489 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
490 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
492 err = i915_guc_submission_init(dev_priv);
497 * WaEnableuKernelHeaderValidFix:skl,bxt
498 * For BXT, this is only upto B0 but below WA is required for later
499 * steppings also so this is extended as well.
501 /* WaEnableGuCBootHashCheckNotSet:skl,bxt */
502 for (retries = 3; ; ) {
504 * Always reset the GuC just before (re)loading, so
505 * that the state and timing are fairly predictable
507 err = guc_hw_reset(dev_priv);
511 err = guc_ucode_xfer(dev_priv);
518 DRM_INFO("GuC fw load failed: %d; will reset and "
519 "retry %d more time(s)\n", err, retries);
522 guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
524 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
525 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
526 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
528 if (i915.enable_guc_submission) {
529 err = i915_guc_submission_enable(dev_priv);
532 guc_interrupts_capture(dev_priv);
538 if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
539 guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
541 guc_interrupts_release(dev_priv);
542 i915_guc_submission_disable(dev_priv);
543 i915_guc_submission_fini(dev_priv);
546 * We've failed to load the firmware :(
548 * Decide whether to disable GuC submission and fall back to
549 * execlist mode, and whether to hide the error by returning
550 * zero or to return -EIO, which the caller will treat as a
551 * nonfatal error (i.e. it doesn't prevent driver load, but
552 * marks the GPU as wedged until reset).
554 if (i915.enable_guc_loading > 1) {
556 } else if (i915.enable_guc_submission > 1) {
562 if (err == 0 && !HAS_GUC_UCODE(dev))
563 ; /* Don't mention the GuC! */
565 DRM_INFO("GuC firmware load skipped\n");
566 else if (ret != -EIO)
567 DRM_NOTE("GuC firmware load failed: %d\n", err);
569 DRM_WARN("GuC firmware load failed: %d\n", err);
571 if (i915.enable_guc_submission) {
573 DRM_INFO("GuC submission without firmware not supported\n");
575 DRM_NOTE("Falling back from GuC submission to execlist mode\n");
577 DRM_ERROR("GuC init failed: %d\n", ret);
579 i915.enable_guc_submission = 0;
584 static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
586 struct pci_dev *pdev = dev->pdev;
587 struct drm_i915_gem_object *obj;
588 const struct firmware *fw;
589 struct guc_css_header *css;
593 DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
594 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
596 err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev);
602 DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
603 guc_fw->guc_fw_path, fw);
605 /* Check the size of the blob before examining buffer contents */
606 if (fw->size < sizeof(struct guc_css_header)) {
607 DRM_NOTE("Firmware header is missing\n");
611 css = (struct guc_css_header *)fw->data;
613 /* Firmware bits always start from header */
614 guc_fw->header_offset = 0;
615 guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
616 css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
618 if (guc_fw->header_size != sizeof(struct guc_css_header)) {
619 DRM_NOTE("CSS header definition mismatch\n");
624 guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
625 guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
628 if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
629 DRM_NOTE("RSA key size is bad\n");
632 guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
633 guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
635 /* At least, it should have header, uCode and RSA. Size of all three. */
636 size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
637 if (fw->size < size) {
638 DRM_NOTE("Missing firmware components\n");
642 /* Header and uCode will be loaded to WOPCM. Size of the two. */
643 size = guc_fw->header_size + guc_fw->ucode_size;
644 if (size > guc_wopcm_size(to_i915(dev))) {
645 DRM_NOTE("Firmware is too large to fit in WOPCM\n");
650 * The GuC firmware image has the version number embedded at a well-known
651 * offset within the firmware blob; note that major / minor version are
652 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
653 * in terms of bytes (u8).
655 guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
656 guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
658 if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
659 guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
660 DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n",
661 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
662 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
667 DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
668 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
669 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
671 mutex_lock(&dev->struct_mutex);
672 obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
673 mutex_unlock(&dev->struct_mutex);
674 if (IS_ERR_OR_NULL(obj)) {
675 err = obj ? PTR_ERR(obj) : -ENOMEM;
679 guc_fw->guc_fw_obj = obj;
680 guc_fw->guc_fw_size = fw->size;
682 DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
685 release_firmware(fw);
686 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
690 DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n",
691 guc_fw->guc_fw_path, err);
692 DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
693 err, fw, guc_fw->guc_fw_obj);
695 mutex_lock(&dev->struct_mutex);
696 obj = guc_fw->guc_fw_obj;
698 i915_gem_object_put(obj);
699 guc_fw->guc_fw_obj = NULL;
700 mutex_unlock(&dev->struct_mutex);
702 release_firmware(fw); /* OK even if fw is NULL */
703 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
707 * intel_guc_init() - define parameters and fetch firmware
710 * Called early during driver load, but after GEM is initialised.
712 * The firmware will be transferred to the GuC's memory later,
713 * when intel_guc_setup() is called.
715 void intel_guc_init(struct drm_device *dev)
717 struct drm_i915_private *dev_priv = to_i915(dev);
718 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
721 /* A negative value means "use platform default" */
722 if (i915.enable_guc_loading < 0)
723 i915.enable_guc_loading = HAS_GUC_UCODE(dev);
724 if (i915.enable_guc_submission < 0)
725 i915.enable_guc_submission = HAS_GUC_SCHED(dev);
727 if (!HAS_GUC_UCODE(dev)) {
729 } else if (IS_SKYLAKE(dev)) {
730 fw_path = I915_SKL_GUC_UCODE;
731 guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
732 guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
733 } else if (IS_BROXTON(dev)) {
734 fw_path = I915_BXT_GUC_UCODE;
735 guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
736 guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
737 } else if (IS_KABYLAKE(dev)) {
738 fw_path = I915_KBL_GUC_UCODE;
739 guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
740 guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
742 fw_path = ""; /* unknown device */
745 guc_fw->guc_dev = dev;
746 guc_fw->guc_fw_path = fw_path;
747 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
748 guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
750 /* Early (and silent) return if GuC loading is disabled */
751 if (!i915.enable_guc_loading)
755 if (*fw_path == '\0')
758 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
759 DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
760 guc_fw_fetch(dev, guc_fw);
761 /* status must now be FAIL or SUCCESS */
765 * intel_guc_fini() - clean up all allocated resources
768 void intel_guc_fini(struct drm_device *dev)
770 struct drm_i915_private *dev_priv = to_i915(dev);
771 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
773 mutex_lock(&dev->struct_mutex);
774 guc_interrupts_release(dev_priv);
775 i915_guc_submission_disable(dev_priv);
776 i915_guc_submission_fini(dev_priv);
778 if (guc_fw->guc_fw_obj)
779 i915_gem_object_put(guc_fw->guc_fw_obj);
780 guc_fw->guc_fw_obj = NULL;
781 mutex_unlock(&dev->struct_mutex);
783 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;