drivers/gpu/drm/i915/intel_guc_loader.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Vinit Azad <vinit.azad@intel.com>
  25  *    Ben Widawsky <ben@bwidawsk.net>
  26  *    Dave Gordon <david.s.gordon@intel.com>
  27  *    Alex Dai <yu.dai@intel.com>
  28  */
  29 #include <linux/firmware.h>
  30 #include "i915_drv.h"
  31 #include "intel_guc.h"
  32
  33 /**
  34  * DOC: GuC-specific firmware loader
  35  *
  36  * intel_guc:
  37  * Top level structure of guc. It handles firmware loading and manages client
  38  * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
  39  * ExecList submission.
  40  *
  41  * Firmware versioning:
  42  * The firmware build process will generate a version header file with major and
  43  * minor version defined. The versions are built into CSS header of firmware.
  44  * i915 kernel driver set the minimal firmware version required per platform.
  45  * The firmware installation package will install (symbolic link) proper version
  46  * of firmware.
  47  *
  48  * GuC address space:
  49  * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
  50  * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
  51  * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
  52  * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
  53  *
  54  * Firmware log:
  55  * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
  56  * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
  57  * i915_guc_load_status will print out firmware loading status and scratch
  58  * registers value.
  59  *
  60  */
  61
  62 #define I915_SKL_GUC_UCODE "i915/skl_guc_ver6_1.bin"
  63 MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
  64
  65 #define I915_BXT_GUC_UCODE "i915/bxt_guc_ver8_7.bin"
  66 MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
  67
  68 /* User-friendly representation of an enum */
  69 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
  70 {
  71         switch (status) {
  72         case GUC_FIRMWARE_FAIL:
  73                 return "FAIL";
  74         case GUC_FIRMWARE_NONE:
  75                 return "NONE";
  76         case GUC_FIRMWARE_PENDING:
  77                 return "PENDING";
  78         case GUC_FIRMWARE_SUCCESS:
  79                 return "SUCCESS";
  80         default:
  81                 return "UNKNOWN!";
  82         }
  83 };
  84
  85 static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
  86 {
  87         struct intel_engine_cs *engine;
  88         int irqs;
  89
  90         /* tell all command streamers NOT to forward interrupts and vblank to GuC */
  91         irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
  92         irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
  93         for_each_engine(engine, dev_priv)
  94                 I915_WRITE(RING_MODE_GEN7(engine), irqs);
  95
  96         /* route all GT interrupts to the host */
  97         I915_WRITE(GUC_BCS_RCS_IER, 0);
  98         I915_WRITE(GUC_VCS2_VCS1_IER, 0);
  99         I915_WRITE(GUC_WD_VECS_IER, 0);
 100 }
 101
 102 static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 103 {
 104         struct intel_engine_cs *engine;
 105         int irqs;
 106         u32 tmp;
 107
 108         /* tell all command streamers to forward interrupts and vblank to GuC */
 109         irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_ALWAYS);
 110         irqs |= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
 111         for_each_engine(engine, dev_priv)
 112                 I915_WRITE(RING_MODE_GEN7(engine), irqs);
 113
 114         /* route USER_INTERRUPT to Host, all others are sent to GuC. */
 115         irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
 116                GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
 117         /* These three registers have the same bit definitions */
 118         I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
 119         I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
 120         I915_WRITE(GUC_WD_VECS_IER, ~irqs);
 121
 122         /*
 123          * If GuC has routed PM interrupts to itself, don't keep it.
 124          * and keep other interrupts those are unmasked by GuC.
 125         */
 126         tmp = I915_READ(GEN6_PMINTRMSK);
 127         if (tmp & GEN8_PMINTR_REDIRECT_TO_NON_DISP) {
 128                 dev_priv->rps.pm_intr_keep |= ~(tmp & ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
 129                 dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
 130         }
 131 }
 132
 133 static u32 get_gttype(struct drm_i915_private *dev_priv)
 134 {
 135         /* XXX: GT type based on PCI device ID? field seems unused by fw */
 136         return 0;
 137 }
 138
 139 static u32 get_core_family(struct drm_i915_private *dev_priv)
 140 {
 141         switch (INTEL_INFO(dev_priv)->gen) {
 142         case 9:
 143                 return GFXCORE_FAMILY_GEN9;
 144
 145         default:
 146                 DRM_ERROR("GUC: unsupported core family\n");
 147                 return GFXCORE_FAMILY_UNKNOWN;
 148         }
 149 }
 150
 151 static void set_guc_init_params(struct drm_i915_private *dev_priv)
 152 {
 153         struct intel_guc *guc = &dev_priv->guc;
 154         u32 params[GUC_CTL_MAX_DWORDS];
 155         int i;
 156
 157         memset(&params, 0, sizeof(params));
 158
 159         params[GUC_CTL_DEVICE_INFO] |=
 160                 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
 161                 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
 162
 163         /*
 164          * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
 165          * second. This ARAR is calculated by:
 166          * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
 167          */
 168         params[GUC_CTL_ARAT_HIGH] = 0;
 169         params[GUC_CTL_ARAT_LOW] = 100000000;
 170
 171         params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
 172
 173         params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 174                         GUC_CTL_VCS2_ENABLED;
 175
 176         if (i915.guc_log_level >= 0) {
 177                 params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
 178                 params[GUC_CTL_DEBUG] =
 179                         i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
 180         }
 181
 182         if (guc->ads_obj) {
 183                 u32 ads = (u32)i915_gem_obj_ggtt_offset(guc->ads_obj)
 184                                 >> PAGE_SHIFT;
 185                 params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
 186                 params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
 187         }
 188
 189         /* If GuC submission is enabled, set up additional parameters here */
 190         if (i915.enable_guc_submission) {
 191                 u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj);
 192                 u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
 193
 194                 pgs >>= PAGE_SHIFT;
 195                 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
 196                         (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
 197
 198                 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
 199
 200                 /* Unmask this bit to enable the GuC's internal scheduler */
 201                 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
 202         }
 203
 204         I915_WRITE(SOFT_SCRATCH(0), 0);
 205
 206         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 207                 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
 208 }
 209
 210 /*
 211  * Read the GuC status register (GUC_STATUS) and store it in the
 212  * specified location; then return a boolean indicating whether
 213  * the value matches either of two values representing completion
 214  * of the GuC boot process.
 215  *
 216  * This is used for polling the GuC status in a wait_for()
 217  * loop below.
 218  */
 219 static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
 220                                       u32 *status)
 221 {
 222         u32 val = I915_READ(GUC_STATUS);
 223         u32 uk_val = val & GS_UKERNEL_MASK;
 224         *status = val;
 225         return (uk_val == GS_UKERNEL_READY ||
 226                 ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
 227 }
 228
 229 /*
 230  * Transfer the firmware image to RAM for execution by the microcontroller.
 231  *
 232  * Architecturally, the DMA engine is bidirectional, and can potentially even
 233  * transfer between GTT locations. This functionality is left out of the API
 234  * for now as there is no need for it.
 235  *
 236  * Note that GuC needs the CSS header plus uKernel code to be copied by the
 237  * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
 238  */
 239 static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
 240 {
 241         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 242         struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
 243         unsigned long offset;
 244         struct sg_table *sg = fw_obj->pages;
 245         u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
 246         int i, ret = 0;
 247
 248         /* where RSA signature starts */
 249         offset = guc_fw->rsa_offset;
 250
 251         /* Copy RSA signature from the fw image to HW for verification */
 252         sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
 253         for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
 254                 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
 255
 256         /* The header plus uCode will be copied to WOPCM via DMA, excluding any
 257          * other components */
 258         I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
 259
 260         /* Set the source address for the new blob */
 261         offset = i915_gem_obj_ggtt_offset(fw_obj) + guc_fw->header_offset;
 262         I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 263         I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 264
 265         /*
 266          * Set the DMA destination. Current uCode expects the code to be
 267          * loaded at 8k; locations below this are used for the stack.
 268          */
 269         I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
 270         I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 271
 272         /* Finally start the DMA */
 273         I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
 274
 275         /*
 276          * Wait for the DMA to complete & the GuC to start up.
 277          * NB: Docs recommend not using the interrupt for completion.
 278          * Measurements indicate this should take no more than 20ms, so a
 279          * timeout here indicates that the GuC has failed and is unusable.
 280          * (Higher levels of the driver will attempt to fall back to
 281          * execlist mode if this happens.)
 282          */
 283         ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
 284
 285         DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
 286                         I915_READ(DMA_CTRL), status);
 287
 288         if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
 289                 DRM_ERROR("GuC firmware signature verification failed\n");
 290                 ret = -ENOEXEC;
 291         }
 292
 293         DRM_DEBUG_DRIVER("returning %d\n", ret);
 294
 295         return ret;
 296 }
 297
 298 static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
 299 {
 300         u32 wopcm_size = GUC_WOPCM_TOP;
 301
 302         /* On BXT, the top of WOPCM is reserved for RC6 context */
 303         if (IS_BROXTON(dev_priv))
 304                 wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
 305
 306         return wopcm_size;
 307 }
 308
 309 /*
 310  * Load the GuC firmware blob into the MinuteIA.
 311  */
 312 static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 313 {
 314         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 315         struct drm_device *dev = dev_priv->dev;
 316         int ret;
 317
 318         ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
 319         if (ret) {
 320                 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
 321                 return ret;
 322         }
 323
 324         ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
 325         if (ret) {
 326                 DRM_DEBUG_DRIVER("pin failed %d\n", ret);
 327                 return ret;
 328         }
 329
 330         /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
 331         I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 332
 333         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 334
 335         /* init WOPCM */
 336         I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
 337         I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
 338
 339         /* Enable MIA caching. GuC clock gating is disabled. */
 340         I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 341
 342         /* WaDisableMinuteIaClockGating:skl,bxt */
 343         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 344             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 345                 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
 346                                               ~GUC_ENABLE_MIA_CLOCK_GATING));
 347         }
 348
 349         /* WaC6DisallowByGfxPause*/
 350         I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
 351
 352         if (IS_BROXTON(dev))
 353                 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 354         else
 355                 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 356
 357         if (IS_GEN9(dev)) {
 358                 /* DOP Clock Gating Enable for GuC clocks */
 359                 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
 360                                             I915_READ(GEN7_MISCCPCTL)));
 361
 362                 /* allows for 5us before GT can go to RC6 */
 363                 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
 364         }
 365
 366         set_guc_init_params(dev_priv);
 367
 368         ret = guc_ucode_xfer_dma(dev_priv);
 369
 370         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 371
 372         /*
 373          * We keep the object pages for reuse during resume. But we can unpin it
 374          * now that DMA has completed, so it doesn't continue to take up space.
 375          */
 376         i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
 377
 378         return ret;
 379 }
 380
 381 static int i915_reset_guc(struct drm_i915_private *dev_priv)
 382 {
 383         int ret;
 384         u32 guc_status;
 385
 386         ret = intel_guc_reset(dev_priv);
 387         if (ret) {
 388                 DRM_ERROR("GuC reset failed, ret = %d\n", ret);
 389                 return ret;
 390         }
 391
 392         guc_status = I915_READ(GUC_STATUS);
 393         WARN(!(guc_status & GS_MIA_IN_RESET),
 394              "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status);
 395
 396         return ret;
 397 }
 398
 399 /**
 400  * intel_guc_setup() - finish preparing the GuC for activity
 401  * @dev:        drm device
 402  *
 403  * Called from gem_init_hw() during driver loading and also after a GPU reset.
 404  *
 405  * The main action required here it to load the GuC uCode into the device.
 406  * The firmware image should have already been fetched into memory by the
 407  * earlier call to intel_guc_init(), so here we need only check that worked,
 408  * and then transfer the image to the h/w.
 409  *
 410  * Return:      non-zero code on error
 411  */
 412 int intel_guc_setup(struct drm_device *dev)
 413 {
 414         struct drm_i915_private *dev_priv = dev->dev_private;
 415         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 416         const char *fw_path = guc_fw->guc_fw_path;
 417         int retries, ret, err;
 418
 419         DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
 420                 fw_path,
 421                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 422                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 423
 424         /* Loading forbidden, or no firmware to load? */
 425         if (!i915.enable_guc_loading) {
 426                 err = 0;
 427                 goto fail;
 428         } else if (fw_path == NULL || *fw_path == '\0') {
 429                 if (*fw_path == '\0')
 430                         DRM_INFO("No GuC firmware known for this platform\n");
 431                 err = -ENODEV;
 432                 goto fail;
 433         }
 434
 435         /* Fetch failed, or already fetched but failed to load? */
 436         if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
 437                 err = -EIO;
 438                 goto fail;
 439         } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
 440                 err = -ENOEXEC;
 441                 goto fail;
 442         }
 443
 444         direct_interrupts_to_host(dev_priv);
 445
 446         guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
 447
 448         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 449                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 450                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 451
 452         err = i915_guc_submission_init(dev);
 453         if (err)
 454                 goto fail;
 455
 456         /*
 457          * WaEnableuKernelHeaderValidFix:skl,bxt
 458          * For BXT, this is only upto B0 but below WA is required for later
 459          * steppings also so this is extended as well.
 460          */
 461         /* WaEnableGuCBootHashCheckNotSet:skl,bxt */
 462         for (retries = 3; ; ) {
 463                 /*
 464                  * Always reset the GuC just before (re)loading, so
 465                  * that the state and timing are fairly predictable
 466                  */
 467                 err = i915_reset_guc(dev_priv);
 468                 if (err) {
 469                         DRM_ERROR("GuC reset failed: %d\n", err);
 470                         goto fail;
 471                 }
 472
 473                 err = guc_ucode_xfer(dev_priv);
 474                 if (!err)
 475                         break;
 476
 477                 if (--retries == 0)
 478                         goto fail;
 479
 480                 DRM_INFO("GuC fw load failed: %d; will reset and "
 481                          "retry %d more time(s)\n", err, retries);
 482         }
 483
 484         guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
 485
 486         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 487                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 488                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 489
 490         if (i915.enable_guc_submission) {
 491                 /* The execbuf_client will be recreated. Release it first. */
 492                 i915_guc_submission_disable(dev);
 493
 494                 err = i915_guc_submission_enable(dev);
 495                 if (err)
 496                         goto fail;
 497                 direct_interrupts_to_guc(dev_priv);
 498         }
 499
 500         return 0;
 501
 502 fail:
 503         if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
 504                 guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
 505
 506         direct_interrupts_to_host(dev_priv);
 507         i915_guc_submission_disable(dev);
 508         i915_guc_submission_fini(dev);
 509
 510         /*
 511          * We've failed to load the firmware :(
 512          *
 513          * Decide whether to disable GuC submission and fall back to
 514          * execlist mode, and whether to hide the error by returning
 515          * zero or to return -EIO, which the caller will treat as a
 516          * nonfatal error (i.e. it doesn't prevent driver load, but
 517          * marks the GPU as wedged until reset).
 518          */
 519         if (i915.enable_guc_loading > 1) {
 520                 ret = -EIO;
 521         } else if (i915.enable_guc_submission > 1) {
 522                 ret = -EIO;
 523         } else {
 524                 ret = 0;
 525         }
 526
 527         if (err == 0)
 528                 DRM_INFO("GuC firmware load skipped\n");
 529         else if (ret == -EIO)
 530                 DRM_ERROR("GuC firmware load failed: %d\n", err);
 531         else
 532                 DRM_INFO("GuC firmware load failed: %d\n", err);
 533
 534         if (i915.enable_guc_submission) {
 535                 if (fw_path == NULL)
 536                         DRM_INFO("GuC submission without firmware not supported\n");
 537                 if (ret == 0)
 538                         DRM_INFO("Falling back to execlist mode\n");
 539                 else
 540                         DRM_ERROR("GuC init failed: %d\n", ret);
 541         }
 542         i915.enable_guc_submission = 0;
 543
 544         return ret;
 545 }
 546
 547 static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
 548 {
 549         struct drm_i915_gem_object *obj;
 550         const struct firmware *fw;
 551         struct guc_css_header *css;
 552         size_t size;
 553         int err;
 554
 555         DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
 556                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
 557
 558         err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
 559         if (err)
 560                 goto fail;
 561         if (!fw)
 562                 goto fail;
 563
 564         DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
 565                 guc_fw->guc_fw_path, fw);
 566
 567         /* Check the size of the blob before examining buffer contents */
 568         if (fw->size < sizeof(struct guc_css_header)) {
 569                 DRM_ERROR("Firmware header is missing\n");
 570                 goto fail;
 571         }
 572
 573         css = (struct guc_css_header *)fw->data;
 574
 575         /* Firmware bits always start from header */
 576         guc_fw->header_offset = 0;
 577         guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
 578                 css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
 579
 580         if (guc_fw->header_size != sizeof(struct guc_css_header)) {
 581                 DRM_ERROR("CSS header definition mismatch\n");
 582                 goto fail;
 583         }
 584
 585         /* then, uCode */
 586         guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
 587         guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
 588
 589         /* now RSA */
 590         if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
 591                 DRM_ERROR("RSA key size is bad\n");
 592                 goto fail;
 593         }
 594         guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
 595         guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
 596
 597         /* At least, it should have header, uCode and RSA. Size of all three. */
 598         size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
 599         if (fw->size < size) {
 600                 DRM_ERROR("Missing firmware components\n");
 601                 goto fail;
 602         }
 603
 604         /* Header and uCode will be loaded to WOPCM. Size of the two. */
 605         size = guc_fw->header_size + guc_fw->ucode_size;
 606         if (size > guc_wopcm_size(dev->dev_private)) {
 607                 DRM_ERROR("Firmware is too large to fit in WOPCM\n");
 608                 goto fail;
 609         }
 610
 611         /*
 612          * The GuC firmware image has the version number embedded at a well-known
 613          * offset within the firmware blob; note that major / minor version are
 614          * TWO bytes each (i.e. u16), although all pointers and offsets are defined
 615          * in terms of bytes (u8).
 616          */
 617         guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
 618         guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
 619
 620         if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
 621             guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
 622                 DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
 623                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
 624                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
 625                 err = -ENOEXEC;
 626                 goto fail;
 627         }
 628
 629         DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
 630                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
 631                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
 632
 633         mutex_lock(&dev->struct_mutex);
 634         obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
 635         mutex_unlock(&dev->struct_mutex);
 636         if (IS_ERR_OR_NULL(obj)) {
 637                 err = obj ? PTR_ERR(obj) : -ENOMEM;
 638                 goto fail;
 639         }
 640
 641         guc_fw->guc_fw_obj = obj;
 642         guc_fw->guc_fw_size = fw->size;
 643
 644         DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
 645                         guc_fw->guc_fw_obj);
 646
 647         release_firmware(fw);
 648         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
 649         return;
 650
 651 fail:
 652         DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
 653                 err, fw, guc_fw->guc_fw_obj);
 654         DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
 655                   guc_fw->guc_fw_path, err);
 656
 657         mutex_lock(&dev->struct_mutex);
 658         obj = guc_fw->guc_fw_obj;
 659         if (obj)
 660                 drm_gem_object_unreference(&obj->base);
 661         guc_fw->guc_fw_obj = NULL;
 662         mutex_unlock(&dev->struct_mutex);
 663
 664         release_firmware(fw);           /* OK even if fw is NULL */
 665         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
 666 }
 667
 668 /**
 669  * intel_guc_init() - define parameters and fetch firmware
 670  * @dev:        drm device
 671  *
 672  * Called early during driver load, but after GEM is initialised.
 673  *
 674  * The firmware will be transferred to the GuC's memory later,
 675  * when intel_guc_setup() is called.
 676  */
 677 void intel_guc_init(struct drm_device *dev)
 678 {
 679         struct drm_i915_private *dev_priv = dev->dev_private;
 680         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 681         const char *fw_path;
 682
 683         /* A negative value means "use platform default" */
 684         if (i915.enable_guc_loading < 0)
 685                 i915.enable_guc_loading = HAS_GUC_UCODE(dev);
 686         if (i915.enable_guc_submission < 0)
 687                 i915.enable_guc_submission = HAS_GUC_SCHED(dev);
 688
 689         if (!HAS_GUC_UCODE(dev)) {
 690                 fw_path = NULL;
 691         } else if (IS_SKYLAKE(dev)) {
 692                 fw_path = I915_SKL_GUC_UCODE;
 693                 guc_fw->guc_fw_major_wanted = 6;
 694                 guc_fw->guc_fw_minor_wanted = 1;
 695         } else if (IS_BROXTON(dev)) {
 696                 fw_path = I915_BXT_GUC_UCODE;
 697                 guc_fw->guc_fw_major_wanted = 8;
 698                 guc_fw->guc_fw_minor_wanted = 7;
 699         } else {
 700                 fw_path = "";   /* unknown device */
 701         }
 702
 703         guc_fw->guc_dev = dev;
 704         guc_fw->guc_fw_path = fw_path;
 705         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 706         guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
 707
 708         /* Early (and silent) return if GuC loading is disabled */
 709         if (!i915.enable_guc_loading)
 710                 return;
 711         if (fw_path == NULL)
 712                 return;
 713         if (*fw_path == '\0')
 714                 return;
 715
 716         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
 717         DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
 718         guc_fw_fetch(dev, guc_fw);
 719         /* status must now be FAIL or SUCCESS */
 720 }
 721
 722 /**
 723  * intel_guc_fini() - clean up all allocated resources
 724  * @dev:        drm device
 725  */
 726 void intel_guc_fini(struct drm_device *dev)
 727 {
 728         struct drm_i915_private *dev_priv = dev->dev_private;
 729         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 730
 731         mutex_lock(&dev->struct_mutex);
 732         direct_interrupts_to_host(dev_priv);
 733         i915_guc_submission_disable(dev);
 734         i915_guc_submission_fini(dev);
 735
 736         if (guc_fw->guc_fw_obj)
 737                 drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
 738         guc_fw->guc_fw_obj = NULL;
 739         mutex_unlock(&dev->struct_mutex);
 740
 741         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 742 }