2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Vinit Azad <vinit.azad@intel.com>
25 * Ben Widawsky <ben@bwidawsk.net>
26 * Dave Gordon <david.s.gordon@intel.com>
27 * Alex Dai <yu.dai@intel.com>
29 #include <linux/firmware.h>
31 #include "intel_guc.h"
34 * DOC: GuC-specific firmware loader
37 * Top level structure of guc. It handles firmware loading and manages client
38 * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
39 * ExecList submission.
41 * Firmware versioning:
42 * The firmware build process will generate a version header file with major and
43 * minor version defined. The versions are built into CSS header of firmware.
44 * i915 kernel driver set the minimal firmware version required per platform.
45 * The firmware installation package will install (symbolic link) proper version
49 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
50 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
51 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
52 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
55 * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
56 * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
57 * i915_guc_load_status will print out firmware loading status and scratch
62 #define I915_SKL_GUC_UCODE "i915/skl_guc_ver6_1.bin"
63 MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
65 #define I915_BXT_GUC_UCODE "i915/bxt_guc_ver8_7.bin"
66 MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
68 /* User-friendly representation of an enum */
69 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
72 case GUC_FIRMWARE_FAIL:
74 case GUC_FIRMWARE_NONE:
76 case GUC_FIRMWARE_PENDING:
78 case GUC_FIRMWARE_SUCCESS:
85 static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
87 struct intel_engine_cs *engine;
90 /* tell all command streamers NOT to forward interrupts and vblank to GuC */
91 irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
92 irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
93 for_each_engine(engine, dev_priv)
94 I915_WRITE(RING_MODE_GEN7(engine), irqs);
96 /* route all GT interrupts to the host */
97 I915_WRITE(GUC_BCS_RCS_IER, 0);
98 I915_WRITE(GUC_VCS2_VCS1_IER, 0);
99 I915_WRITE(GUC_WD_VECS_IER, 0);
102 static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
104 struct intel_engine_cs *engine;
107 /* tell all command streamers to forward interrupts and vblank to GuC */
108 irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_ALWAYS);
109 irqs |= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
110 for_each_engine(engine, dev_priv)
111 I915_WRITE(RING_MODE_GEN7(engine), irqs);
113 /* route USER_INTERRUPT to Host, all others are sent to GuC. */
114 irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
115 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
116 /* These three registers have the same bit definitions */
117 I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
118 I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
119 I915_WRITE(GUC_WD_VECS_IER, ~irqs);
122 static u32 get_gttype(struct drm_i915_private *dev_priv)
124 /* XXX: GT type based on PCI device ID? field seems unused by fw */
128 static u32 get_core_family(struct drm_i915_private *dev_priv)
130 switch (INTEL_INFO(dev_priv)->gen) {
132 return GFXCORE_FAMILY_GEN9;
135 DRM_ERROR("GUC: unsupported core family\n");
136 return GFXCORE_FAMILY_UNKNOWN;
140 static void set_guc_init_params(struct drm_i915_private *dev_priv)
142 struct intel_guc *guc = &dev_priv->guc;
143 u32 params[GUC_CTL_MAX_DWORDS];
146 memset(¶ms, 0, sizeof(params));
148 params[GUC_CTL_DEVICE_INFO] |=
149 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
150 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
153 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
154 * second. This ARAR is calculated by:
155 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
157 params[GUC_CTL_ARAT_HIGH] = 0;
158 params[GUC_CTL_ARAT_LOW] = 100000000;
160 params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
162 params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
163 GUC_CTL_VCS2_ENABLED;
165 if (i915.guc_log_level >= 0) {
166 params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
167 params[GUC_CTL_DEBUG] =
168 i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
172 u32 ads = (u32)i915_gem_obj_ggtt_offset(guc->ads_obj)
174 params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
175 params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
178 /* If GuC submission is enabled, set up additional parameters here */
179 if (i915.enable_guc_submission) {
180 u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj);
181 u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
184 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
185 (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
187 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
189 /* Unmask this bit to enable the GuC's internal scheduler */
190 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
193 I915_WRITE(SOFT_SCRATCH(0), 0);
195 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
196 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
200 * Read the GuC status register (GUC_STATUS) and store it in the
201 * specified location; then return a boolean indicating whether
202 * the value matches either of two values representing completion
203 * of the GuC boot process.
205 * This is used for polling the GuC status in a wait_for()
208 static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
211 u32 val = I915_READ(GUC_STATUS);
212 u32 uk_val = val & GS_UKERNEL_MASK;
214 return (uk_val == GS_UKERNEL_READY ||
215 ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
219 * Transfer the firmware image to RAM for execution by the microcontroller.
221 * Architecturally, the DMA engine is bidirectional, and can potentially even
222 * transfer between GTT locations. This functionality is left out of the API
223 * for now as there is no need for it.
225 * Note that GuC needs the CSS header plus uKernel code to be copied by the
226 * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
228 static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
230 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
231 struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
232 unsigned long offset;
233 struct sg_table *sg = fw_obj->pages;
234 u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
237 /* where RSA signature starts */
238 offset = guc_fw->rsa_offset;
240 /* Copy RSA signature from the fw image to HW for verification */
241 sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
242 for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
243 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
245 /* The header plus uCode will be copied to WOPCM via DMA, excluding any
246 * other components */
247 I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
249 /* Set the source address for the new blob */
250 offset = i915_gem_obj_ggtt_offset(fw_obj) + guc_fw->header_offset;
251 I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
252 I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
255 * Set the DMA destination. Current uCode expects the code to be
256 * loaded at 8k; locations below this are used for the stack.
258 I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
259 I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
261 /* Finally start the DMA */
262 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
265 * Wait for the DMA to complete & the GuC to start up.
266 * NB: Docs recommend not using the interrupt for completion.
267 * Measurements indicate this should take no more than 20ms, so a
268 * timeout here indicates that the GuC has failed and is unusable.
269 * (Higher levels of the driver will attempt to fall back to
270 * execlist mode if this happens.)
272 ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
274 DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
275 I915_READ(DMA_CTRL), status);
277 if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
278 DRM_ERROR("GuC firmware signature verification failed\n");
282 DRM_DEBUG_DRIVER("returning %d\n", ret);
287 static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
289 u32 wopcm_size = GUC_WOPCM_TOP;
291 /* On BXT, the top of WOPCM is reserved for RC6 context */
292 if (IS_BROXTON(dev_priv))
293 wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
299 * Load the GuC firmware blob into the MinuteIA.
301 static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
303 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
304 struct drm_device *dev = dev_priv->dev;
307 ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
309 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
313 ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
315 DRM_DEBUG_DRIVER("pin failed %d\n", ret);
319 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
320 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
322 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
325 I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
326 I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
328 /* Enable MIA caching. GuC clock gating is disabled. */
329 I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
331 /* WaDisableMinuteIaClockGating:skl,bxt */
332 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
333 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
334 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
335 ~GUC_ENABLE_MIA_CLOCK_GATING));
338 /* WaC6DisallowByGfxPause*/
339 I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
342 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
344 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
347 /* DOP Clock Gating Enable for GuC clocks */
348 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
349 I915_READ(GEN7_MISCCPCTL)));
351 /* allows for 5us before GT can go to RC6 */
352 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
355 set_guc_init_params(dev_priv);
357 ret = guc_ucode_xfer_dma(dev_priv);
359 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
362 * We keep the object pages for reuse during resume. But we can unpin it
363 * now that DMA has completed, so it doesn't continue to take up space.
365 i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
370 static int i915_reset_guc(struct drm_i915_private *dev_priv)
375 ret = intel_guc_reset(dev_priv);
377 DRM_ERROR("GuC reset failed, ret = %d\n", ret);
381 guc_status = I915_READ(GUC_STATUS);
382 WARN(!(guc_status & GS_MIA_IN_RESET),
383 "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status);
389 * intel_guc_ucode_load() - load GuC uCode into the device
392 * Called from gem_init_hw() during driver loading and also after a GPU reset.
394 * The firmware image should have already been fetched into memory by the
395 * earlier call to intel_guc_ucode_init(), so here we need only check that
396 * is succeeded, and then transfer the image to the h/w.
398 * Return: non-zero code on error
400 int intel_guc_ucode_load(struct drm_device *dev)
402 struct drm_i915_private *dev_priv = dev->dev_private;
403 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
404 int retries, err = 0;
406 if (!i915.enable_guc_submission)
409 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
410 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
411 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
413 direct_interrupts_to_host(dev_priv);
415 if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_NONE)
418 if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS &&
419 guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL)
422 guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
424 DRM_DEBUG_DRIVER("GuC fw fetch status %s\n",
425 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
427 switch (guc_fw->guc_fw_fetch_status) {
428 case GUC_FIRMWARE_FAIL:
429 /* something went wrong :( */
433 case GUC_FIRMWARE_NONE:
434 case GUC_FIRMWARE_PENDING:
437 WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n",
439 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
440 guc_fw->guc_fw_fetch_status);
444 case GUC_FIRMWARE_SUCCESS:
448 err = i915_guc_submission_init(dev);
453 * WaEnableuKernelHeaderValidFix:skl,bxt
454 * For BXT, this is only upto B0 but below WA is required for later
455 * steppings also so this is extended as well.
457 /* WaEnableGuCBootHashCheckNotSet:skl,bxt */
458 for (retries = 3; ; ) {
460 * Always reset the GuC just before (re)loading, so
461 * that the state and timing are fairly predictable
463 err = i915_reset_guc(dev_priv);
465 DRM_ERROR("GuC reset failed, err %d\n", err);
469 err = guc_ucode_xfer(dev_priv);
476 DRM_INFO("GuC fw load failed, err %d; will reset and "
477 "retry %d more time(s)\n", err, retries);
480 guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
482 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
483 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
484 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
486 if (i915.enable_guc_submission) {
487 /* The execbuf_client will be recreated. Release it first. */
488 i915_guc_submission_disable(dev);
490 err = i915_guc_submission_enable(dev);
493 direct_interrupts_to_guc(dev_priv);
499 DRM_ERROR("GuC firmware load failed, err %d\n", err);
500 if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
501 guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
503 direct_interrupts_to_host(dev_priv);
504 i915_guc_submission_disable(dev);
505 i915_guc_submission_fini(dev);
510 static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
512 struct drm_i915_gem_object *obj;
513 const struct firmware *fw;
514 struct guc_css_header *css;
518 DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
519 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
521 err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
527 DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
528 guc_fw->guc_fw_path, fw);
530 /* Check the size of the blob before examining buffer contents */
531 if (fw->size < sizeof(struct guc_css_header)) {
532 DRM_ERROR("Firmware header is missing\n");
536 css = (struct guc_css_header *)fw->data;
538 /* Firmware bits always start from header */
539 guc_fw->header_offset = 0;
540 guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
541 css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
543 if (guc_fw->header_size != sizeof(struct guc_css_header)) {
544 DRM_ERROR("CSS header definition mismatch\n");
549 guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
550 guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
553 if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
554 DRM_ERROR("RSA key size is bad\n");
557 guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
558 guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
560 /* At least, it should have header, uCode and RSA. Size of all three. */
561 size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
562 if (fw->size < size) {
563 DRM_ERROR("Missing firmware components\n");
567 /* Header and uCode will be loaded to WOPCM. Size of the two. */
568 size = guc_fw->header_size + guc_fw->ucode_size;
569 if (size > guc_wopcm_size(dev->dev_private)) {
570 DRM_ERROR("Firmware is too large to fit in WOPCM\n");
575 * The GuC firmware image has the version number embedded at a well-known
576 * offset within the firmware blob; note that major / minor version are
577 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
578 * in terms of bytes (u8).
580 guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
581 guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
583 if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
584 guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
585 DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
586 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
587 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
592 DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
593 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
594 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
596 mutex_lock(&dev->struct_mutex);
597 obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
598 mutex_unlock(&dev->struct_mutex);
599 if (IS_ERR_OR_NULL(obj)) {
600 err = obj ? PTR_ERR(obj) : -ENOMEM;
604 guc_fw->guc_fw_obj = obj;
605 guc_fw->guc_fw_size = fw->size;
607 DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
610 release_firmware(fw);
611 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
615 DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
616 err, fw, guc_fw->guc_fw_obj);
617 DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
618 guc_fw->guc_fw_path, err);
620 mutex_lock(&dev->struct_mutex);
621 obj = guc_fw->guc_fw_obj;
623 drm_gem_object_unreference(&obj->base);
624 guc_fw->guc_fw_obj = NULL;
625 mutex_unlock(&dev->struct_mutex);
627 release_firmware(fw); /* OK even if fw is NULL */
628 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
632 * intel_guc_ucode_init() - define parameters and fetch firmware
635 * Called early during driver load, but after GEM is initialised.
637 * The firmware will be transferred to the GuC's memory later,
638 * when intel_guc_ucode_load() is called.
640 void intel_guc_ucode_init(struct drm_device *dev)
642 struct drm_i915_private *dev_priv = dev->dev_private;
643 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
646 if (!HAS_GUC_SCHED(dev))
647 i915.enable_guc_submission = false;
649 if (!HAS_GUC_UCODE(dev)) {
651 } else if (IS_SKYLAKE(dev)) {
652 fw_path = I915_SKL_GUC_UCODE;
653 guc_fw->guc_fw_major_wanted = 6;
654 guc_fw->guc_fw_minor_wanted = 1;
655 } else if (IS_BROXTON(dev)) {
656 fw_path = I915_BXT_GUC_UCODE;
657 guc_fw->guc_fw_major_wanted = 8;
658 guc_fw->guc_fw_minor_wanted = 7;
660 i915.enable_guc_submission = false;
661 fw_path = ""; /* unknown device */
664 if (!i915.enable_guc_submission)
667 guc_fw->guc_dev = dev;
668 guc_fw->guc_fw_path = fw_path;
669 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
670 guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
675 if (*fw_path == '\0') {
676 DRM_ERROR("No GuC firmware known for this platform\n");
677 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
681 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
682 DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
683 guc_fw_fetch(dev, guc_fw);
684 /* status must now be FAIL or SUCCESS */
688 * intel_guc_ucode_fini() - clean up all allocated resources
691 void intel_guc_ucode_fini(struct drm_device *dev)
693 struct drm_i915_private *dev_priv = dev->dev_private;
694 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
696 mutex_lock(&dev->struct_mutex);
697 direct_interrupts_to_host(dev_priv);
698 i915_guc_submission_disable(dev);
699 i915_guc_submission_fini(dev);
701 if (guc_fw->guc_fw_obj)
702 drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
703 guc_fw->guc_fw_obj = NULL;
704 mutex_unlock(&dev->struct_mutex);
706 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;