drivers/gpu/drm/i915/intel_guc_loader.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Vinit Azad <vinit.azad@intel.com>
  25  *    Ben Widawsky <ben@bwidawsk.net>
  26  *    Dave Gordon <david.s.gordon@intel.com>
  27  *    Alex Dai <yu.dai@intel.com>
  28  */
  29 #include <linux/firmware.h>
  30 #include "i915_drv.h"
  31 #include "intel_guc.h"
  32
  33 /**
  34  * DOC: GuC-specific firmware loader
  35  *
  36  * intel_guc:
  37  * Top level structure of guc. It handles firmware loading and manages client
  38  * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
  39  * ExecList submission.
  40  *
  41  * Firmware versioning:
  42  * The firmware build process will generate a version header file with major and
  43  * minor version defined. The versions are built into CSS header of firmware.
  44  * i915 kernel driver set the minimal firmware version required per platform.
  45  * The firmware installation package will install (symbolic link) proper version
  46  * of firmware.
  47  *
  48  * GuC address space:
  49  * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
  50  * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
  51  * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
  52  * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
  53  *
  54  * Firmware log:
  55  * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
  56  * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
  57  * i915_guc_load_status will print out firmware loading status and scratch
  58  * registers value.
  59  *
  60  */
  61
  62 #define I915_SKL_GUC_UCODE "i915/skl_guc_ver6_1.bin"
  63 MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
  64
  65 #define I915_BXT_GUC_UCODE "i915/bxt_guc_ver8_7.bin"
  66 MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
  67
  68 /* User-friendly representation of an enum */
  69 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
  70 {
  71         switch (status) {
  72         case GUC_FIRMWARE_FAIL:
  73                 return "FAIL";
  74         case GUC_FIRMWARE_NONE:
  75                 return "NONE";
  76         case GUC_FIRMWARE_PENDING:
  77                 return "PENDING";
  78         case GUC_FIRMWARE_SUCCESS:
  79                 return "SUCCESS";
  80         default:
  81                 return "UNKNOWN!";
  82         }
  83 };
  84
  85 static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
  86 {
  87         struct intel_engine_cs *engine;
  88         int irqs;
  89
  90         /* tell all command streamers NOT to forward interrupts and vblank to GuC */
  91         irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
  92         irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
  93         for_each_engine(engine, dev_priv)
  94                 I915_WRITE(RING_MODE_GEN7(engine), irqs);
  95
  96         /* route all GT interrupts to the host */
  97         I915_WRITE(GUC_BCS_RCS_IER, 0);
  98         I915_WRITE(GUC_VCS2_VCS1_IER, 0);
  99         I915_WRITE(GUC_WD_VECS_IER, 0);
 100 }
 101
 102 static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 103 {
 104         struct intel_engine_cs *engine;
 105         int irqs;
 106
 107         /* tell all command streamers to forward interrupts and vblank to GuC */
 108         irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_ALWAYS);
 109         irqs |= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
 110         for_each_engine(engine, dev_priv)
 111                 I915_WRITE(RING_MODE_GEN7(engine), irqs);
 112
 113         /* route USER_INTERRUPT to Host, all others are sent to GuC. */
 114         irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
 115                GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
 116         /* These three registers have the same bit definitions */
 117         I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
 118         I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
 119         I915_WRITE(GUC_WD_VECS_IER, ~irqs);
 120 }
 121
 122 static u32 get_gttype(struct drm_i915_private *dev_priv)
 123 {
 124         /* XXX: GT type based on PCI device ID? field seems unused by fw */
 125         return 0;
 126 }
 127
 128 static u32 get_core_family(struct drm_i915_private *dev_priv)
 129 {
 130         switch (INTEL_INFO(dev_priv)->gen) {
 131         case 9:
 132                 return GFXCORE_FAMILY_GEN9;
 133
 134         default:
 135                 DRM_ERROR("GUC: unsupported core family\n");
 136                 return GFXCORE_FAMILY_UNKNOWN;
 137         }
 138 }
 139
 140 static void set_guc_init_params(struct drm_i915_private *dev_priv)
 141 {
 142         struct intel_guc *guc = &dev_priv->guc;
 143         u32 params[GUC_CTL_MAX_DWORDS];
 144         int i;
 145
 146         memset(&params, 0, sizeof(params));
 147
 148         params[GUC_CTL_DEVICE_INFO] |=
 149                 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
 150                 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
 151
 152         /*
 153          * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
 154          * second. This ARAR is calculated by:
 155          * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
 156          */
 157         params[GUC_CTL_ARAT_HIGH] = 0;
 158         params[GUC_CTL_ARAT_LOW] = 100000000;
 159
 160         params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
 161
 162         params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 163                         GUC_CTL_VCS2_ENABLED;
 164
 165         if (i915.guc_log_level >= 0) {
 166                 params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
 167                 params[GUC_CTL_DEBUG] =
 168                         i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
 169         }
 170
 171         if (guc->ads_obj) {
 172                 u32 ads = (u32)i915_gem_obj_ggtt_offset(guc->ads_obj)
 173                                 >> PAGE_SHIFT;
 174                 params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
 175                 params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
 176         }
 177
 178         /* If GuC submission is enabled, set up additional parameters here */
 179         if (i915.enable_guc_submission) {
 180                 u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj);
 181                 u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
 182
 183                 pgs >>= PAGE_SHIFT;
 184                 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
 185                         (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
 186
 187                 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
 188
 189                 /* Unmask this bit to enable the GuC's internal scheduler */
 190                 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
 191         }
 192
 193         I915_WRITE(SOFT_SCRATCH(0), 0);
 194
 195         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 196                 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
 197 }
 198
 199 /*
 200  * Read the GuC status register (GUC_STATUS) and store it in the
 201  * specified location; then return a boolean indicating whether
 202  * the value matches either of two values representing completion
 203  * of the GuC boot process.
 204  *
 205  * This is used for polling the GuC status in a wait_for()
 206  * loop below.
 207  */
 208 static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
 209                                       u32 *status)
 210 {
 211         u32 val = I915_READ(GUC_STATUS);
 212         u32 uk_val = val & GS_UKERNEL_MASK;
 213         *status = val;
 214         return (uk_val == GS_UKERNEL_READY ||
 215                 ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
 216 }
 217
 218 /*
 219  * Transfer the firmware image to RAM for execution by the microcontroller.
 220  *
 221  * Architecturally, the DMA engine is bidirectional, and can potentially even
 222  * transfer between GTT locations. This functionality is left out of the API
 223  * for now as there is no need for it.
 224  *
 225  * Note that GuC needs the CSS header plus uKernel code to be copied by the
 226  * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
 227  */
 228 static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
 229 {
 230         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 231         struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
 232         unsigned long offset;
 233         struct sg_table *sg = fw_obj->pages;
 234         u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
 235         int i, ret = 0;
 236
 237         /* where RSA signature starts */
 238         offset = guc_fw->rsa_offset;
 239
 240         /* Copy RSA signature from the fw image to HW for verification */
 241         sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
 242         for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
 243                 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
 244
 245         /* The header plus uCode will be copied to WOPCM via DMA, excluding any
 246          * other components */
 247         I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
 248
 249         /* Set the source address for the new blob */
 250         offset = i915_gem_obj_ggtt_offset(fw_obj) + guc_fw->header_offset;
 251         I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 252         I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 253
 254         /*
 255          * Set the DMA destination. Current uCode expects the code to be
 256          * loaded at 8k; locations below this are used for the stack.
 257          */
 258         I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
 259         I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 260
 261         /* Finally start the DMA */
 262         I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
 263
 264         /*
 265          * Wait for the DMA to complete & the GuC to start up.
 266          * NB: Docs recommend not using the interrupt for completion.
 267          * Measurements indicate this should take no more than 20ms, so a
 268          * timeout here indicates that the GuC has failed and is unusable.
 269          * (Higher levels of the driver will attempt to fall back to
 270          * execlist mode if this happens.)
 271          */
 272         ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
 273
 274         DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
 275                         I915_READ(DMA_CTRL), status);
 276
 277         if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
 278                 DRM_ERROR("GuC firmware signature verification failed\n");
 279                 ret = -ENOEXEC;
 280         }
 281
 282         DRM_DEBUG_DRIVER("returning %d\n", ret);
 283
 284         return ret;
 285 }
 286
 287 static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
 288 {
 289         u32 wopcm_size = GUC_WOPCM_TOP;
 290
 291         /* On BXT, the top of WOPCM is reserved for RC6 context */
 292         if (IS_BROXTON(dev_priv))
 293                 wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
 294
 295         return wopcm_size;
 296 }
 297
 298 /*
 299  * Load the GuC firmware blob into the MinuteIA.
 300  */
 301 static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 302 {
 303         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 304         struct drm_device *dev = dev_priv->dev;
 305         int ret;
 306
 307         ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
 308         if (ret) {
 309                 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
 310                 return ret;
 311         }
 312
 313         ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
 314         if (ret) {
 315                 DRM_DEBUG_DRIVER("pin failed %d\n", ret);
 316                 return ret;
 317         }
 318
 319         /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
 320         I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 321
 322         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 323
 324         /* init WOPCM */
 325         I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
 326         I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
 327
 328         /* Enable MIA caching. GuC clock gating is disabled. */
 329         I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 330
 331         /* WaDisableMinuteIaClockGating:skl,bxt */
 332         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 333             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 334                 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
 335                                               ~GUC_ENABLE_MIA_CLOCK_GATING));
 336         }
 337
 338         /* WaC6DisallowByGfxPause*/
 339         I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
 340
 341         if (IS_BROXTON(dev))
 342                 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 343         else
 344                 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 345
 346         if (IS_GEN9(dev)) {
 347                 /* DOP Clock Gating Enable for GuC clocks */
 348                 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
 349                                             I915_READ(GEN7_MISCCPCTL)));
 350
 351                 /* allows for 5us before GT can go to RC6 */
 352                 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
 353         }
 354
 355         set_guc_init_params(dev_priv);
 356
 357         ret = guc_ucode_xfer_dma(dev_priv);
 358
 359         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 360
 361         /*
 362          * We keep the object pages for reuse during resume. But we can unpin it
 363          * now that DMA has completed, so it doesn't continue to take up space.
 364          */
 365         i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
 366
 367         return ret;
 368 }
 369
 370 static int i915_reset_guc(struct drm_i915_private *dev_priv)
 371 {
 372         int ret;
 373         u32 guc_status;
 374
 375         ret = intel_guc_reset(dev_priv);
 376         if (ret) {
 377                 DRM_ERROR("GuC reset failed, ret = %d\n", ret);
 378                 return ret;
 379         }
 380
 381         guc_status = I915_READ(GUC_STATUS);
 382         WARN(!(guc_status & GS_MIA_IN_RESET),
 383              "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status);
 384
 385         return ret;
 386 }
 387
 388 /**
 389  * intel_guc_setup() - finish preparing the GuC for activity
 390  * @dev:        drm device
 391  *
 392  * Called from gem_init_hw() during driver loading and also after a GPU reset.
 393  *
 394  * The main action required here it to load the GuC uCode into the device.
 395  * The firmware image should have already been fetched into memory by the
 396  * earlier call to intel_guc_init(), so here we need only check that worked,
 397  * and then transfer the image to the h/w.
 398  *
 399  * Return:      non-zero code on error
 400  */
 401 int intel_guc_setup(struct drm_device *dev)
 402 {
 403         struct drm_i915_private *dev_priv = dev->dev_private;
 404         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 405         const char *fw_path = guc_fw->guc_fw_path;
 406         int retries, ret, err;
 407
 408         DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
 409                 fw_path,
 410                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 411                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 412
 413         /* Loading forbidden, or no firmware to load? */
 414         if (!i915.enable_guc_loading) {
 415                 err = 0;
 416                 goto fail;
 417         } else if (fw_path == NULL || *fw_path == '\0') {
 418                 if (*fw_path == '\0')
 419                         DRM_INFO("No GuC firmware known for this platform\n");
 420                 err = -ENODEV;
 421                 goto fail;
 422         }
 423
 424         /* Fetch failed, or already fetched but failed to load? */
 425         if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
 426                 err = -EIO;
 427                 goto fail;
 428         } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
 429                 err = -ENOEXEC;
 430                 goto fail;
 431         }
 432
 433         direct_interrupts_to_host(dev_priv);
 434
 435         guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
 436
 437         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 438                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 439                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 440
 441         err = i915_guc_submission_init(dev);
 442         if (err)
 443                 goto fail;
 444
 445         /*
 446          * WaEnableuKernelHeaderValidFix:skl,bxt
 447          * For BXT, this is only upto B0 but below WA is required for later
 448          * steppings also so this is extended as well.
 449          */
 450         /* WaEnableGuCBootHashCheckNotSet:skl,bxt */
 451         for (retries = 3; ; ) {
 452                 /*
 453                  * Always reset the GuC just before (re)loading, so
 454                  * that the state and timing are fairly predictable
 455                  */
 456                 err = i915_reset_guc(dev_priv);
 457                 if (err) {
 458                         DRM_ERROR("GuC reset failed: %d\n", err);
 459                         goto fail;
 460                 }
 461
 462                 err = guc_ucode_xfer(dev_priv);
 463                 if (!err)
 464                         break;
 465
 466                 if (--retries == 0)
 467                         goto fail;
 468
 469                 DRM_INFO("GuC fw load failed: %d; will reset and "
 470                          "retry %d more time(s)\n", err, retries);
 471         }
 472
 473         guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
 474
 475         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 476                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 477                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 478
 479         if (i915.enable_guc_submission) {
 480                 /* The execbuf_client will be recreated. Release it first. */
 481                 i915_guc_submission_disable(dev);
 482
 483                 err = i915_guc_submission_enable(dev);
 484                 if (err)
 485                         goto fail;
 486                 direct_interrupts_to_guc(dev_priv);
 487         }
 488
 489         return 0;
 490
 491 fail:
 492         if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
 493                 guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
 494
 495         direct_interrupts_to_host(dev_priv);
 496         i915_guc_submission_disable(dev);
 497         i915_guc_submission_fini(dev);
 498
 499         /*
 500          * We've failed to load the firmware :(
 501          *
 502          * Decide whether to disable GuC submission and fall back to
 503          * execlist mode, and whether to hide the error by returning
 504          * zero or to return -EIO, which the caller will treat as a
 505          * nonfatal error (i.e. it doesn't prevent driver load, but
 506          * marks the GPU as wedged until reset).
 507          */
 508         if (i915.enable_guc_loading > 1) {
 509                 ret = -EIO;
 510         } else if (i915.enable_guc_submission > 1) {
 511                 ret = -EIO;
 512         } else {
 513                 ret = 0;
 514         }
 515
 516         if (err == 0)
 517                 DRM_INFO("GuC firmware load skipped\n");
 518         else if (ret == -EIO)
 519                 DRM_ERROR("GuC firmware load failed: %d\n", err);
 520         else
 521                 DRM_INFO("GuC firmware load failed: %d\n", err);
 522
 523         if (i915.enable_guc_submission) {
 524                 if (fw_path == NULL)
 525                         DRM_INFO("GuC submission without firmware not supported\n");
 526                 if (ret == 0)
 527                         DRM_INFO("Falling back to execlist mode\n");
 528                 else
 529                         DRM_ERROR("GuC init failed: %d\n", ret);
 530         }
 531         i915.enable_guc_submission = 0;
 532
 533         return ret;
 534 }
 535
 536 static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
 537 {
 538         struct drm_i915_gem_object *obj;
 539         const struct firmware *fw;
 540         struct guc_css_header *css;
 541         size_t size;
 542         int err;
 543
 544         DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
 545                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
 546
 547         err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
 548         if (err)
 549                 goto fail;
 550         if (!fw)
 551                 goto fail;
 552
 553         DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
 554                 guc_fw->guc_fw_path, fw);
 555
 556         /* Check the size of the blob before examining buffer contents */
 557         if (fw->size < sizeof(struct guc_css_header)) {
 558                 DRM_ERROR("Firmware header is missing\n");
 559                 goto fail;
 560         }
 561
 562         css = (struct guc_css_header *)fw->data;
 563
 564         /* Firmware bits always start from header */
 565         guc_fw->header_offset = 0;
 566         guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
 567                 css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
 568
 569         if (guc_fw->header_size != sizeof(struct guc_css_header)) {
 570                 DRM_ERROR("CSS header definition mismatch\n");
 571                 goto fail;
 572         }
 573
 574         /* then, uCode */
 575         guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
 576         guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
 577
 578         /* now RSA */
 579         if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
 580                 DRM_ERROR("RSA key size is bad\n");
 581                 goto fail;
 582         }
 583         guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
 584         guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
 585
 586         /* At least, it should have header, uCode and RSA. Size of all three. */
 587         size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
 588         if (fw->size < size) {
 589                 DRM_ERROR("Missing firmware components\n");
 590                 goto fail;
 591         }
 592
 593         /* Header and uCode will be loaded to WOPCM. Size of the two. */
 594         size = guc_fw->header_size + guc_fw->ucode_size;
 595         if (size > guc_wopcm_size(dev->dev_private)) {
 596                 DRM_ERROR("Firmware is too large to fit in WOPCM\n");
 597                 goto fail;
 598         }
 599
 600         /*
 601          * The GuC firmware image has the version number embedded at a well-known
 602          * offset within the firmware blob; note that major / minor version are
 603          * TWO bytes each (i.e. u16), although all pointers and offsets are defined
 604          * in terms of bytes (u8).
 605          */
 606         guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
 607         guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
 608
 609         if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
 610             guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
 611                 DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
 612                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
 613                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
 614                 err = -ENOEXEC;
 615                 goto fail;
 616         }
 617
 618         DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
 619                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
 620                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
 621
 622         mutex_lock(&dev->struct_mutex);
 623         obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
 624         mutex_unlock(&dev->struct_mutex);
 625         if (IS_ERR_OR_NULL(obj)) {
 626                 err = obj ? PTR_ERR(obj) : -ENOMEM;
 627                 goto fail;
 628         }
 629
 630         guc_fw->guc_fw_obj = obj;
 631         guc_fw->guc_fw_size = fw->size;
 632
 633         DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
 634                         guc_fw->guc_fw_obj);
 635
 636         release_firmware(fw);
 637         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
 638         return;
 639
 640 fail:
 641         DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
 642                 err, fw, guc_fw->guc_fw_obj);
 643         DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
 644                   guc_fw->guc_fw_path, err);
 645
 646         mutex_lock(&dev->struct_mutex);
 647         obj = guc_fw->guc_fw_obj;
 648         if (obj)
 649                 drm_gem_object_unreference(&obj->base);
 650         guc_fw->guc_fw_obj = NULL;
 651         mutex_unlock(&dev->struct_mutex);
 652
 653         release_firmware(fw);           /* OK even if fw is NULL */
 654         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
 655 }
 656
 657 /**
 658  * intel_guc_init() - define parameters and fetch firmware
 659  * @dev:        drm device
 660  *
 661  * Called early during driver load, but after GEM is initialised.
 662  *
 663  * The firmware will be transferred to the GuC's memory later,
 664  * when intel_guc_setup() is called.
 665  */
 666 void intel_guc_init(struct drm_device *dev)
 667 {
 668         struct drm_i915_private *dev_priv = dev->dev_private;
 669         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 670         const char *fw_path;
 671
 672         /* A negative value means "use platform default" */
 673         if (i915.enable_guc_loading < 0)
 674                 i915.enable_guc_loading = HAS_GUC_UCODE(dev);
 675         if (i915.enable_guc_submission < 0)
 676                 i915.enable_guc_submission = HAS_GUC_SCHED(dev);
 677
 678         if (!HAS_GUC_UCODE(dev)) {
 679                 fw_path = NULL;
 680         } else if (IS_SKYLAKE(dev)) {
 681                 fw_path = I915_SKL_GUC_UCODE;
 682                 guc_fw->guc_fw_major_wanted = 6;
 683                 guc_fw->guc_fw_minor_wanted = 1;
 684         } else if (IS_BROXTON(dev)) {
 685                 fw_path = I915_BXT_GUC_UCODE;
 686                 guc_fw->guc_fw_major_wanted = 8;
 687                 guc_fw->guc_fw_minor_wanted = 7;
 688         } else {
 689                 fw_path = "";   /* unknown device */
 690         }
 691
 692         guc_fw->guc_dev = dev;
 693         guc_fw->guc_fw_path = fw_path;
 694         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 695         guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
 696
 697         /* Early (and silent) return if GuC loading is disabled */
 698         if (!i915.enable_guc_loading)
 699                 return;
 700         if (fw_path == NULL)
 701                 return;
 702         if (*fw_path == '\0')
 703                 return;
 704
 705         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
 706         DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
 707         guc_fw_fetch(dev, guc_fw);
 708         /* status must now be FAIL or SUCCESS */
 709 }
 710
 711 /**
 712  * intel_guc_fini() - clean up all allocated resources
 713  * @dev:        drm device
 714  */
 715 void intel_guc_fini(struct drm_device *dev)
 716 {
 717         struct drm_i915_private *dev_priv = dev->dev_private;
 718         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 719
 720         mutex_lock(&dev->struct_mutex);
 721         direct_interrupts_to_host(dev_priv);
 722         i915_guc_submission_disable(dev);
 723         i915_guc_submission_fini(dev);
 724
 725         if (guc_fw->guc_fw_obj)
 726                 drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
 727         guc_fw->guc_fw_obj = NULL;
 728         mutex_unlock(&dev->struct_mutex);
 729
 730         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 731 }