drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include <drm/intel_lpe_audio.h>
  40 #include "i915_drv.h"
  41
  42 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  43 {
  44         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  45 }
  46
  47 static void
  48 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  49 {
  50         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  51         struct drm_i915_private *dev_priv = to_i915(dev);
  52         uint32_t enabled_bits;
  53
  54         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  55
  56         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  57              "HDMI port enabled, expecting disabled\n");
  58 }
  59
  60 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  61 {
  62         struct intel_digital_port *intel_dig_port =
  63                 container_of(encoder, struct intel_digital_port, base.base);
  64         return &intel_dig_port->hdmi;
  65 }
  66
  67 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  68 {
  69         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  70 }
  71
  72 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  73 {
  74         switch (type) {
  75         case HDMI_INFOFRAME_TYPE_AVI:
  76                 return VIDEO_DIP_SELECT_AVI;
  77         case HDMI_INFOFRAME_TYPE_SPD:
  78                 return VIDEO_DIP_SELECT_SPD;
  79         case HDMI_INFOFRAME_TYPE_VENDOR:
  80                 return VIDEO_DIP_SELECT_VENDOR;
  81         default:
  82                 MISSING_CASE(type);
  83                 return 0;
  84         }
  85 }
  86
  87 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  88 {
  89         switch (type) {
  90         case HDMI_INFOFRAME_TYPE_AVI:
  91                 return VIDEO_DIP_ENABLE_AVI;
  92         case HDMI_INFOFRAME_TYPE_SPD:
  93                 return VIDEO_DIP_ENABLE_SPD;
  94         case HDMI_INFOFRAME_TYPE_VENDOR:
  95                 return VIDEO_DIP_ENABLE_VENDOR;
  96         default:
  97                 MISSING_CASE(type);
  98                 return 0;
  99         }
 100 }
 101
 102 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 103 {
 104         switch (type) {
 105         case HDMI_INFOFRAME_TYPE_AVI:
 106                 return VIDEO_DIP_ENABLE_AVI_HSW;
 107         case HDMI_INFOFRAME_TYPE_SPD:
 108                 return VIDEO_DIP_ENABLE_SPD_HSW;
 109         case HDMI_INFOFRAME_TYPE_VENDOR:
 110                 return VIDEO_DIP_ENABLE_VS_HSW;
 111         default:
 112                 MISSING_CASE(type);
 113                 return 0;
 114         }
 115 }
 116
 117 static i915_reg_t
 118 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 119                  enum transcoder cpu_transcoder,
 120                  enum hdmi_infoframe_type type,
 121                  int i)
 122 {
 123         switch (type) {
 124         case HDMI_INFOFRAME_TYPE_AVI:
 125                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 126         case HDMI_INFOFRAME_TYPE_SPD:
 127                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 128         case HDMI_INFOFRAME_TYPE_VENDOR:
 129                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 130         default:
 131                 MISSING_CASE(type);
 132                 return INVALID_MMIO_REG;
 133         }
 134 }
 135
 136 static void g4x_write_infoframe(struct drm_encoder *encoder,
 137                                 enum hdmi_infoframe_type type,
 138                                 const void *frame, ssize_t len)
 139 {
 140         const uint32_t *data = frame;
 141         struct drm_device *dev = encoder->dev;
 142         struct drm_i915_private *dev_priv = to_i915(dev);
 143         u32 val = I915_READ(VIDEO_DIP_CTL);
 144         int i;
 145
 146         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 147
 148         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 149         val |= g4x_infoframe_index(type);
 150
 151         val &= ~g4x_infoframe_enable(type);
 152
 153         I915_WRITE(VIDEO_DIP_CTL, val);
 154
 155         mmiowb();
 156         for (i = 0; i < len; i += 4) {
 157                 I915_WRITE(VIDEO_DIP_DATA, *data);
 158                 data++;
 159         }
 160         /* Write every possible data byte to force correct ECC calculation. */
 161         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 162                 I915_WRITE(VIDEO_DIP_DATA, 0);
 163         mmiowb();
 164
 165         val |= g4x_infoframe_enable(type);
 166         val &= ~VIDEO_DIP_FREQ_MASK;
 167         val |= VIDEO_DIP_FREQ_VSYNC;
 168
 169         I915_WRITE(VIDEO_DIP_CTL, val);
 170         POSTING_READ(VIDEO_DIP_CTL);
 171 }
 172
 173 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
 174                                   const struct intel_crtc_state *pipe_config)
 175 {
 176         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 177         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 178         u32 val = I915_READ(VIDEO_DIP_CTL);
 179
 180         if ((val & VIDEO_DIP_ENABLE) == 0)
 181                 return false;
 182
 183         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 184                 return false;
 185
 186         return val & (VIDEO_DIP_ENABLE_AVI |
 187                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 188 }
 189
 190 static void ibx_write_infoframe(struct drm_encoder *encoder,
 191                                 enum hdmi_infoframe_type type,
 192                                 const void *frame, ssize_t len)
 193 {
 194         const uint32_t *data = frame;
 195         struct drm_device *dev = encoder->dev;
 196         struct drm_i915_private *dev_priv = to_i915(dev);
 197         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 198         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 199         u32 val = I915_READ(reg);
 200         int i;
 201
 202         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 203
 204         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 205         val |= g4x_infoframe_index(type);
 206
 207         val &= ~g4x_infoframe_enable(type);
 208
 209         I915_WRITE(reg, val);
 210
 211         mmiowb();
 212         for (i = 0; i < len; i += 4) {
 213                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 214                 data++;
 215         }
 216         /* Write every possible data byte to force correct ECC calculation. */
 217         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 218                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 219         mmiowb();
 220
 221         val |= g4x_infoframe_enable(type);
 222         val &= ~VIDEO_DIP_FREQ_MASK;
 223         val |= VIDEO_DIP_FREQ_VSYNC;
 224
 225         I915_WRITE(reg, val);
 226         POSTING_READ(reg);
 227 }
 228
 229 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
 230                                   const struct intel_crtc_state *pipe_config)
 231 {
 232         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 233         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 234         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 235         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 236         u32 val = I915_READ(reg);
 237
 238         if ((val & VIDEO_DIP_ENABLE) == 0)
 239                 return false;
 240
 241         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 242                 return false;
 243
 244         return val & (VIDEO_DIP_ENABLE_AVI |
 245                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 246                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 247 }
 248
 249 static void cpt_write_infoframe(struct drm_encoder *encoder,
 250                                 enum hdmi_infoframe_type type,
 251                                 const void *frame, ssize_t len)
 252 {
 253         const uint32_t *data = frame;
 254         struct drm_device *dev = encoder->dev;
 255         struct drm_i915_private *dev_priv = to_i915(dev);
 256         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 257         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 258         u32 val = I915_READ(reg);
 259         int i;
 260
 261         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 262
 263         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 264         val |= g4x_infoframe_index(type);
 265
 266         /* The DIP control register spec says that we need to update the AVI
 267          * infoframe without clearing its enable bit */
 268         if (type != HDMI_INFOFRAME_TYPE_AVI)
 269                 val &= ~g4x_infoframe_enable(type);
 270
 271         I915_WRITE(reg, val);
 272
 273         mmiowb();
 274         for (i = 0; i < len; i += 4) {
 275                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 276                 data++;
 277         }
 278         /* Write every possible data byte to force correct ECC calculation. */
 279         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 280                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 281         mmiowb();
 282
 283         val |= g4x_infoframe_enable(type);
 284         val &= ~VIDEO_DIP_FREQ_MASK;
 285         val |= VIDEO_DIP_FREQ_VSYNC;
 286
 287         I915_WRITE(reg, val);
 288         POSTING_READ(reg);
 289 }
 290
 291 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
 292                                   const struct intel_crtc_state *pipe_config)
 293 {
 294         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 295         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 296         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 297
 298         if ((val & VIDEO_DIP_ENABLE) == 0)
 299                 return false;
 300
 301         return val & (VIDEO_DIP_ENABLE_AVI |
 302                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 303                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 304 }
 305
 306 static void vlv_write_infoframe(struct drm_encoder *encoder,
 307                                 enum hdmi_infoframe_type type,
 308                                 const void *frame, ssize_t len)
 309 {
 310         const uint32_t *data = frame;
 311         struct drm_device *dev = encoder->dev;
 312         struct drm_i915_private *dev_priv = to_i915(dev);
 313         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 314         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 315         u32 val = I915_READ(reg);
 316         int i;
 317
 318         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 319
 320         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 321         val |= g4x_infoframe_index(type);
 322
 323         val &= ~g4x_infoframe_enable(type);
 324
 325         I915_WRITE(reg, val);
 326
 327         mmiowb();
 328         for (i = 0; i < len; i += 4) {
 329                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 330                 data++;
 331         }
 332         /* Write every possible data byte to force correct ECC calculation. */
 333         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 334                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 335         mmiowb();
 336
 337         val |= g4x_infoframe_enable(type);
 338         val &= ~VIDEO_DIP_FREQ_MASK;
 339         val |= VIDEO_DIP_FREQ_VSYNC;
 340
 341         I915_WRITE(reg, val);
 342         POSTING_READ(reg);
 343 }
 344
 345 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
 346                                   const struct intel_crtc_state *pipe_config)
 347 {
 348         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 349         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 350         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 351         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 352
 353         if ((val & VIDEO_DIP_ENABLE) == 0)
 354                 return false;
 355
 356         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 357                 return false;
 358
 359         return val & (VIDEO_DIP_ENABLE_AVI |
 360                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 361                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 362 }
 363
 364 static void hsw_write_infoframe(struct drm_encoder *encoder,
 365                                 enum hdmi_infoframe_type type,
 366                                 const void *frame, ssize_t len)
 367 {
 368         const uint32_t *data = frame;
 369         struct drm_device *dev = encoder->dev;
 370         struct drm_i915_private *dev_priv = to_i915(dev);
 371         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 372         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
 373         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 374         i915_reg_t data_reg;
 375         int i;
 376         u32 val = I915_READ(ctl_reg);
 377
 378         data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
 379
 380         val &= ~hsw_infoframe_enable(type);
 381         I915_WRITE(ctl_reg, val);
 382
 383         mmiowb();
 384         for (i = 0; i < len; i += 4) {
 385                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 386                                             type, i >> 2), *data);
 387                 data++;
 388         }
 389         /* Write every possible data byte to force correct ECC calculation. */
 390         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 391                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 392                                             type, i >> 2), 0);
 393         mmiowb();
 394
 395         val |= hsw_infoframe_enable(type);
 396         I915_WRITE(ctl_reg, val);
 397         POSTING_READ(ctl_reg);
 398 }
 399
 400 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
 401                                   const struct intel_crtc_state *pipe_config)
 402 {
 403         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 404         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 405
 406         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 407                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 408                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 409 }
 410
 411 /*
 412  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 413  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 414  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 415  * used for both technologies.
 416  *
 417  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 418  * DW1:       DB3       | DB2 | DB1 | DB0
 419  * DW2:       DB7       | DB6 | DB5 | DB4
 420  * DW3: ...
 421  *
 422  * (HB is Header Byte, DB is Data Byte)
 423  *
 424  * The hdmi pack() functions don't know about that hardware specific hole so we
 425  * trick them by giving an offset into the buffer and moving back the header
 426  * bytes by one.
 427  */
 428 static void intel_write_infoframe(struct drm_encoder *encoder,
 429                                   union hdmi_infoframe *frame)
 430 {
 431         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 432         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 433         ssize_t len;
 434
 435         /* see comment above for the reason for this offset */
 436         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 437         if (len < 0)
 438                 return;
 439
 440         /* Insert the 'hole' (see big comment above) at position 3 */
 441         buffer[0] = buffer[1];
 442         buffer[1] = buffer[2];
 443         buffer[2] = buffer[3];
 444         buffer[3] = 0;
 445         len++;
 446
 447         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 448 }
 449
 450 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 451                                          const struct drm_display_mode *adjusted_mode)
 452 {
 453         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 454         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 455         union hdmi_infoframe frame;
 456         int ret;
 457
 458         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 459                                                        adjusted_mode);
 460         if (ret < 0) {
 461                 DRM_ERROR("couldn't fill AVI infoframe\n");
 462                 return;
 463         }
 464
 465         if (intel_hdmi->rgb_quant_range_selectable) {
 466                 if (intel_crtc->config->limited_color_range)
 467                         frame.avi.quantization_range =
 468                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 469                 else
 470                         frame.avi.quantization_range =
 471                                 HDMI_QUANTIZATION_RANGE_FULL;
 472         }
 473
 474         intel_write_infoframe(encoder, &frame);
 475 }
 476
 477 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 478 {
 479         union hdmi_infoframe frame;
 480         int ret;
 481
 482         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 483         if (ret < 0) {
 484                 DRM_ERROR("couldn't fill SPD infoframe\n");
 485                 return;
 486         }
 487
 488         frame.spd.sdi = HDMI_SPD_SDI_PC;
 489
 490         intel_write_infoframe(encoder, &frame);
 491 }
 492
 493 static void
 494 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 495                               const struct drm_display_mode *adjusted_mode)
 496 {
 497         union hdmi_infoframe frame;
 498         int ret;
 499
 500         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 501                                                           adjusted_mode);
 502         if (ret < 0)
 503                 return;
 504
 505         intel_write_infoframe(encoder, &frame);
 506 }
 507
 508 static void g4x_set_infoframes(struct drm_encoder *encoder,
 509                                bool enable,
 510                                const struct drm_display_mode *adjusted_mode)
 511 {
 512         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 513         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 514         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 515         i915_reg_t reg = VIDEO_DIP_CTL;
 516         u32 val = I915_READ(reg);
 517         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 518
 519         assert_hdmi_port_disabled(intel_hdmi);
 520
 521         /* If the registers were not initialized yet, they might be zeroes,
 522          * which means we're selecting the AVI DIP and we're setting its
 523          * frequency to once. This seems to really confuse the HW and make
 524          * things stop working (the register spec says the AVI always needs to
 525          * be sent every VSync). So here we avoid writing to the register more
 526          * than we need and also explicitly select the AVI DIP and explicitly
 527          * set its frequency to every VSync. Avoiding to write it twice seems to
 528          * be enough to solve the problem, but being defensive shouldn't hurt us
 529          * either. */
 530         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 531
 532         if (!enable) {
 533                 if (!(val & VIDEO_DIP_ENABLE))
 534                         return;
 535                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 536                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 537                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 538                         return;
 539                 }
 540                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 541                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 542                 I915_WRITE(reg, val);
 543                 POSTING_READ(reg);
 544                 return;
 545         }
 546
 547         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 548                 if (val & VIDEO_DIP_ENABLE) {
 549                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 550                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 551                         return;
 552                 }
 553                 val &= ~VIDEO_DIP_PORT_MASK;
 554                 val |= port;
 555         }
 556
 557         val |= VIDEO_DIP_ENABLE;
 558         val &= ~(VIDEO_DIP_ENABLE_AVI |
 559                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 560
 561         I915_WRITE(reg, val);
 562         POSTING_READ(reg);
 563
 564         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 565         intel_hdmi_set_spd_infoframe(encoder);
 566         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 567 }
 568
 569 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
 570 {
 571         struct drm_device *dev = encoder->dev;
 572         struct drm_connector *connector;
 573
 574         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 575
 576         /*
 577          * HDMI cloning is only supported on g4x which doesn't
 578          * support deep color or GCP infoframes anyway so no
 579          * need to worry about multiple HDMI sinks here.
 580          */
 581         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 582                 if (connector->encoder == encoder)
 583                         return connector->display_info.bpc > 8;
 584
 585         return false;
 586 }
 587
 588 /*
 589  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 590  *
 591  * From HDMI specification 1.4a:
 592  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 593  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 594  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 595  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 596  *   phase of 0
 597  */
 598 static bool gcp_default_phase_possible(int pipe_bpp,
 599                                        const struct drm_display_mode *mode)
 600 {
 601         unsigned int pixels_per_group;
 602
 603         switch (pipe_bpp) {
 604         case 30:
 605                 /* 4 pixels in 5 clocks */
 606                 pixels_per_group = 4;
 607                 break;
 608         case 36:
 609                 /* 2 pixels in 3 clocks */
 610                 pixels_per_group = 2;
 611                 break;
 612         case 48:
 613                 /* 1 pixel in 2 clocks */
 614                 pixels_per_group = 1;
 615                 break;
 616         default:
 617                 /* phase information not relevant for 8bpc */
 618                 return false;
 619         }
 620
 621         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 622                 mode->crtc_htotal % pixels_per_group == 0 &&
 623                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 624                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 625                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 626                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 627                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 628                  mode->crtc_htotal/2 % pixels_per_group == 0);
 629 }
 630
 631 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
 632 {
 633         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 634         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 635         i915_reg_t reg;
 636         u32 val = 0;
 637
 638         if (HAS_DDI(dev_priv))
 639                 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
 640         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 641                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 642         else if (HAS_PCH_SPLIT(dev_priv))
 643                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 644         else
 645                 return false;
 646
 647         /* Indicate color depth whenever the sink supports deep color */
 648         if (hdmi_sink_is_deep_color(encoder))
 649                 val |= GCP_COLOR_INDICATION;
 650
 651         /* Enable default_phase whenever the display mode is suitably aligned */
 652         if (gcp_default_phase_possible(crtc->config->pipe_bpp,
 653                                        &crtc->config->base.adjusted_mode))
 654                 val |= GCP_DEFAULT_PHASE_ENABLE;
 655
 656         I915_WRITE(reg, val);
 657
 658         return val != 0;
 659 }
 660
 661 static void ibx_set_infoframes(struct drm_encoder *encoder,
 662                                bool enable,
 663                                const struct drm_display_mode *adjusted_mode)
 664 {
 665         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 666         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 667         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 668         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 669         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 670         u32 val = I915_READ(reg);
 671         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 672
 673         assert_hdmi_port_disabled(intel_hdmi);
 674
 675         /* See the big comment in g4x_set_infoframes() */
 676         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 677
 678         if (!enable) {
 679                 if (!(val & VIDEO_DIP_ENABLE))
 680                         return;
 681                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 682                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 683                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 684                 I915_WRITE(reg, val);
 685                 POSTING_READ(reg);
 686                 return;
 687         }
 688
 689         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 690                 WARN(val & VIDEO_DIP_ENABLE,
 691                      "DIP already enabled on port %c\n",
 692                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 693                 val &= ~VIDEO_DIP_PORT_MASK;
 694                 val |= port;
 695         }
 696
 697         val |= VIDEO_DIP_ENABLE;
 698         val &= ~(VIDEO_DIP_ENABLE_AVI |
 699                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 700                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 701
 702         if (intel_hdmi_set_gcp_infoframe(encoder))
 703                 val |= VIDEO_DIP_ENABLE_GCP;
 704
 705         I915_WRITE(reg, val);
 706         POSTING_READ(reg);
 707
 708         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 709         intel_hdmi_set_spd_infoframe(encoder);
 710         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 711 }
 712
 713 static void cpt_set_infoframes(struct drm_encoder *encoder,
 714                                bool enable,
 715                                const struct drm_display_mode *adjusted_mode)
 716 {
 717         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 718         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 719         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 720         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 721         u32 val = I915_READ(reg);
 722
 723         assert_hdmi_port_disabled(intel_hdmi);
 724
 725         /* See the big comment in g4x_set_infoframes() */
 726         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 727
 728         if (!enable) {
 729                 if (!(val & VIDEO_DIP_ENABLE))
 730                         return;
 731                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 732                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 733                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 734                 I915_WRITE(reg, val);
 735                 POSTING_READ(reg);
 736                 return;
 737         }
 738
 739         /* Set both together, unset both together: see the spec. */
 740         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 741         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 742                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 743
 744         if (intel_hdmi_set_gcp_infoframe(encoder))
 745                 val |= VIDEO_DIP_ENABLE_GCP;
 746
 747         I915_WRITE(reg, val);
 748         POSTING_READ(reg);
 749
 750         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 751         intel_hdmi_set_spd_infoframe(encoder);
 752         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 753 }
 754
 755 static void vlv_set_infoframes(struct drm_encoder *encoder,
 756                                bool enable,
 757                                const struct drm_display_mode *adjusted_mode)
 758 {
 759         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 760         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 761         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 762         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 763         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 764         u32 val = I915_READ(reg);
 765         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 766
 767         assert_hdmi_port_disabled(intel_hdmi);
 768
 769         /* See the big comment in g4x_set_infoframes() */
 770         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 771
 772         if (!enable) {
 773                 if (!(val & VIDEO_DIP_ENABLE))
 774                         return;
 775                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 776                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 777                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 778                 I915_WRITE(reg, val);
 779                 POSTING_READ(reg);
 780                 return;
 781         }
 782
 783         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 784                 WARN(val & VIDEO_DIP_ENABLE,
 785                      "DIP already enabled on port %c\n",
 786                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 787                 val &= ~VIDEO_DIP_PORT_MASK;
 788                 val |= port;
 789         }
 790
 791         val |= VIDEO_DIP_ENABLE;
 792         val &= ~(VIDEO_DIP_ENABLE_AVI |
 793                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 794                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 795
 796         if (intel_hdmi_set_gcp_infoframe(encoder))
 797                 val |= VIDEO_DIP_ENABLE_GCP;
 798
 799         I915_WRITE(reg, val);
 800         POSTING_READ(reg);
 801
 802         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 803         intel_hdmi_set_spd_infoframe(encoder);
 804         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 805 }
 806
 807 static void hsw_set_infoframes(struct drm_encoder *encoder,
 808                                bool enable,
 809                                const struct drm_display_mode *adjusted_mode)
 810 {
 811         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 812         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 813         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 814         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 815         u32 val = I915_READ(reg);
 816
 817         assert_hdmi_port_disabled(intel_hdmi);
 818
 819         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 820                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 821                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 822
 823         if (!enable) {
 824                 I915_WRITE(reg, val);
 825                 POSTING_READ(reg);
 826                 return;
 827         }
 828
 829         if (intel_hdmi_set_gcp_infoframe(encoder))
 830                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
 831
 832         I915_WRITE(reg, val);
 833         POSTING_READ(reg);
 834
 835         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 836         intel_hdmi_set_spd_infoframe(encoder);
 837         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 838 }
 839
 840 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
 841 {
 842         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
 843         struct i2c_adapter *adapter =
 844                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
 845
 846         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
 847                 return;
 848
 849         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
 850                       enable ? "Enabling" : "Disabling");
 851
 852         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
 853                                          adapter, enable);
 854 }
 855
 856 static void intel_hdmi_prepare(struct intel_encoder *encoder)
 857 {
 858         struct drm_device *dev = encoder->base.dev;
 859         struct drm_i915_private *dev_priv = to_i915(dev);
 860         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 861         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 862         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 863         u32 hdmi_val;
 864
 865         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
 866
 867         hdmi_val = SDVO_ENCODING_HDMI;
 868         if (!HAS_PCH_SPLIT(dev_priv) && crtc->config->limited_color_range)
 869                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
 870         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 871                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 872         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 873                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 874
 875         if (crtc->config->pipe_bpp > 24)
 876                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 877         else
 878                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 879
 880         if (crtc->config->has_hdmi_sink)
 881                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 882
 883         if (HAS_PCH_CPT(dev_priv))
 884                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 885         else if (IS_CHERRYVIEW(dev_priv))
 886                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 887         else
 888                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 889
 890         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 891         POSTING_READ(intel_hdmi->hdmi_reg);
 892 }
 893
 894 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 895                                     enum pipe *pipe)
 896 {
 897         struct drm_device *dev = encoder->base.dev;
 898         struct drm_i915_private *dev_priv = to_i915(dev);
 899         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 900         enum intel_display_power_domain power_domain;
 901         u32 tmp;
 902         bool ret;
 903
 904         power_domain = intel_display_port_power_domain(encoder);
 905         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 906                 return false;
 907
 908         ret = false;
 909
 910         tmp = I915_READ(intel_hdmi->hdmi_reg);
 911
 912         if (!(tmp & SDVO_ENABLE))
 913                 goto out;
 914
 915         if (HAS_PCH_CPT(dev_priv))
 916                 *pipe = PORT_TO_PIPE_CPT(tmp);
 917         else if (IS_CHERRYVIEW(dev_priv))
 918                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 919         else
 920                 *pipe = PORT_TO_PIPE(tmp);
 921
 922         ret = true;
 923
 924 out:
 925         intel_display_power_put(dev_priv, power_domain);
 926
 927         return ret;
 928 }
 929
 930 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 931                                   struct intel_crtc_state *pipe_config)
 932 {
 933         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 934         struct drm_device *dev = encoder->base.dev;
 935         struct drm_i915_private *dev_priv = to_i915(dev);
 936         u32 tmp, flags = 0;
 937         int dotclock;
 938
 939         tmp = I915_READ(intel_hdmi->hdmi_reg);
 940
 941         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 942                 flags |= DRM_MODE_FLAG_PHSYNC;
 943         else
 944                 flags |= DRM_MODE_FLAG_NHSYNC;
 945
 946         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 947                 flags |= DRM_MODE_FLAG_PVSYNC;
 948         else
 949                 flags |= DRM_MODE_FLAG_NVSYNC;
 950
 951         if (tmp & HDMI_MODE_SELECT_HDMI)
 952                 pipe_config->has_hdmi_sink = true;
 953
 954         if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
 955                 pipe_config->has_infoframe = true;
 956
 957         if (tmp & SDVO_AUDIO_ENABLE)
 958                 pipe_config->has_audio = true;
 959
 960         if (!HAS_PCH_SPLIT(dev_priv) &&
 961             tmp & HDMI_COLOR_RANGE_16_235)
 962                 pipe_config->limited_color_range = true;
 963
 964         pipe_config->base.adjusted_mode.flags |= flags;
 965
 966         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 967                 dotclock = pipe_config->port_clock * 2 / 3;
 968         else
 969                 dotclock = pipe_config->port_clock;
 970
 971         if (pipe_config->pixel_multiplier)
 972                 dotclock /= pipe_config->pixel_multiplier;
 973
 974         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 975
 976         pipe_config->lane_count = 4;
 977 }
 978
 979 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
 980                                     struct intel_crtc_state *pipe_config,
 981                                     struct drm_connector_state *conn_state)
 982 {
 983         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 984
 985         WARN_ON(!crtc->config->has_hdmi_sink);
 986         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 987                          pipe_name(crtc->pipe));
 988         intel_audio_codec_enable(encoder, pipe_config, conn_state);
 989 }
 990
 991 static void g4x_enable_hdmi(struct intel_encoder *encoder,
 992                             struct intel_crtc_state *pipe_config,
 993                             struct drm_connector_state *conn_state)
 994 {
 995         struct drm_device *dev = encoder->base.dev;
 996         struct drm_i915_private *dev_priv = to_i915(dev);
 997         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 998         u32 temp;
 999
1000         temp = I915_READ(intel_hdmi->hdmi_reg);
1001
1002         temp |= SDVO_ENABLE;
1003         if (pipe_config->has_audio)
1004                 temp |= SDVO_AUDIO_ENABLE;
1005
1006         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1007         POSTING_READ(intel_hdmi->hdmi_reg);
1008
1009         if (pipe_config->has_audio)
1010                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1011 }
1012
1013 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1014                             struct intel_crtc_state *pipe_config,
1015                             struct drm_connector_state *conn_state)
1016 {
1017         struct drm_device *dev = encoder->base.dev;
1018         struct drm_i915_private *dev_priv = to_i915(dev);
1019         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1020         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1021         u32 temp;
1022
1023         temp = I915_READ(intel_hdmi->hdmi_reg);
1024
1025         temp |= SDVO_ENABLE;
1026         if (crtc->config->has_audio)
1027                 temp |= SDVO_AUDIO_ENABLE;
1028
1029         /*
1030          * HW workaround, need to write this twice for issue
1031          * that may result in first write getting masked.
1032          */
1033         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1034         POSTING_READ(intel_hdmi->hdmi_reg);
1035         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1036         POSTING_READ(intel_hdmi->hdmi_reg);
1037
1038         /*
1039          * HW workaround, need to toggle enable bit off and on
1040          * for 12bpc with pixel repeat.
1041          *
1042          * FIXME: BSpec says this should be done at the end of
1043          * of the modeset sequence, so not sure if this isn't too soon.
1044          */
1045         if (pipe_config->pipe_bpp > 24 &&
1046             pipe_config->pixel_multiplier > 1) {
1047                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1048                 POSTING_READ(intel_hdmi->hdmi_reg);
1049
1050                 /*
1051                  * HW workaround, need to write this twice for issue
1052                  * that may result in first write getting masked.
1053                  */
1054                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1055                 POSTING_READ(intel_hdmi->hdmi_reg);
1056                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1057                 POSTING_READ(intel_hdmi->hdmi_reg);
1058         }
1059
1060         if (pipe_config->has_audio)
1061                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1062 }
1063
1064 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1065                             struct intel_crtc_state *pipe_config,
1066                             struct drm_connector_state *conn_state)
1067 {
1068         struct drm_device *dev = encoder->base.dev;
1069         struct drm_i915_private *dev_priv = to_i915(dev);
1070         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1071         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1072         enum pipe pipe = crtc->pipe;
1073         u32 temp;
1074
1075         temp = I915_READ(intel_hdmi->hdmi_reg);
1076
1077         temp |= SDVO_ENABLE;
1078         if (pipe_config->has_audio)
1079                 temp |= SDVO_AUDIO_ENABLE;
1080
1081         /*
1082          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1083          *
1084          * The procedure for 12bpc is as follows:
1085          * 1. disable HDMI clock gating
1086          * 2. enable HDMI with 8bpc
1087          * 3. enable HDMI with 12bpc
1088          * 4. enable HDMI clock gating
1089          */
1090
1091         if (pipe_config->pipe_bpp > 24) {
1092                 I915_WRITE(TRANS_CHICKEN1(pipe),
1093                            I915_READ(TRANS_CHICKEN1(pipe)) |
1094                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1095
1096                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1097                 temp |= SDVO_COLOR_FORMAT_8bpc;
1098         }
1099
1100         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1101         POSTING_READ(intel_hdmi->hdmi_reg);
1102
1103         if (pipe_config->pipe_bpp > 24) {
1104                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1105                 temp |= HDMI_COLOR_FORMAT_12bpc;
1106
1107                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1108                 POSTING_READ(intel_hdmi->hdmi_reg);
1109
1110                 I915_WRITE(TRANS_CHICKEN1(pipe),
1111                            I915_READ(TRANS_CHICKEN1(pipe)) &
1112                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1113         }
1114
1115         if (pipe_config->has_audio)
1116                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1117 }
1118
1119 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1120                             struct intel_crtc_state *pipe_config,
1121                             struct drm_connector_state *conn_state)
1122 {
1123 }
1124
1125 static void intel_disable_hdmi(struct intel_encoder *encoder,
1126                                struct intel_crtc_state *old_crtc_state,
1127                                struct drm_connector_state *old_conn_state)
1128 {
1129         struct drm_device *dev = encoder->base.dev;
1130         struct drm_i915_private *dev_priv = to_i915(dev);
1131         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1132         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1133         u32 temp;
1134
1135         temp = I915_READ(intel_hdmi->hdmi_reg);
1136
1137         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1138         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1139         POSTING_READ(intel_hdmi->hdmi_reg);
1140
1141         /*
1142          * HW workaround for IBX, we need to move the port
1143          * to transcoder A after disabling it to allow the
1144          * matching DP port to be enabled on transcoder A.
1145          */
1146         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1147                 /*
1148                  * We get CPU/PCH FIFO underruns on the other pipe when
1149                  * doing the workaround. Sweep them under the rug.
1150                  */
1151                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1152                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1153
1154                 temp &= ~SDVO_PIPE_B_SELECT;
1155                 temp |= SDVO_ENABLE;
1156                 /*
1157                  * HW workaround, need to write this twice for issue
1158                  * that may result in first write getting masked.
1159                  */
1160                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1161                 POSTING_READ(intel_hdmi->hdmi_reg);
1162                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1163                 POSTING_READ(intel_hdmi->hdmi_reg);
1164
1165                 temp &= ~SDVO_ENABLE;
1166                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1167                 POSTING_READ(intel_hdmi->hdmi_reg);
1168
1169                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1170                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1171                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1172         }
1173
1174         intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1175
1176         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1177 }
1178
1179 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1180                              struct intel_crtc_state *old_crtc_state,
1181                              struct drm_connector_state *old_conn_state)
1182 {
1183         if (old_crtc_state->has_audio)
1184                 intel_audio_codec_disable(encoder);
1185
1186         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1187 }
1188
1189 static void pch_disable_hdmi(struct intel_encoder *encoder,
1190                              struct intel_crtc_state *old_crtc_state,
1191                              struct drm_connector_state *old_conn_state)
1192 {
1193         if (old_crtc_state->has_audio)
1194                 intel_audio_codec_disable(encoder);
1195 }
1196
1197 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1198                                   struct intel_crtc_state *old_crtc_state,
1199                                   struct drm_connector_state *old_conn_state)
1200 {
1201         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1202 }
1203
1204 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
1205 {
1206         if (IS_G4X(dev_priv))
1207                 return 165000;
1208         else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
1209                 return 300000;
1210         else
1211                 return 225000;
1212 }
1213
1214 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1215                                  bool respect_downstream_limits)
1216 {
1217         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1218         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
1219
1220         if (respect_downstream_limits) {
1221                 struct intel_connector *connector = hdmi->attached_connector;
1222                 const struct drm_display_info *info = &connector->base.display_info;
1223
1224                 if (hdmi->dp_dual_mode.max_tmds_clock)
1225                         max_tmds_clock = min(max_tmds_clock,
1226                                              hdmi->dp_dual_mode.max_tmds_clock);
1227
1228                 if (info->max_tmds_clock)
1229                         max_tmds_clock = min(max_tmds_clock,
1230                                              info->max_tmds_clock);
1231                 else if (!hdmi->has_hdmi_sink)
1232                         max_tmds_clock = min(max_tmds_clock, 165000);
1233         }
1234
1235         return max_tmds_clock;
1236 }
1237
1238 static enum drm_mode_status
1239 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1240                       int clock, bool respect_downstream_limits)
1241 {
1242         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1243
1244         if (clock < 25000)
1245                 return MODE_CLOCK_LOW;
1246         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits))
1247                 return MODE_CLOCK_HIGH;
1248
1249         /* BXT DPLL can't generate 223-240 MHz */
1250         if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
1251                 return MODE_CLOCK_RANGE;
1252
1253         /* CHV DPLL can't generate 216-240 MHz */
1254         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1255                 return MODE_CLOCK_RANGE;
1256
1257         return MODE_OK;
1258 }
1259
1260 static enum drm_mode_status
1261 intel_hdmi_mode_valid(struct drm_connector *connector,
1262                       struct drm_display_mode *mode)
1263 {
1264         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1265         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1266         struct drm_i915_private *dev_priv = to_i915(dev);
1267         enum drm_mode_status status;
1268         int clock;
1269         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1270
1271         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1272                 return MODE_NO_DBLESCAN;
1273
1274         clock = mode->clock;
1275
1276         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1277                 clock *= 2;
1278
1279         if (clock > max_dotclk)
1280                 return MODE_CLOCK_HIGH;
1281
1282         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1283                 clock *= 2;
1284
1285         /* check if we can do 8bpc */
1286         status = hdmi_port_clock_valid(hdmi, clock, true);
1287
1288         /* if we can't do 8bpc we may still be able to do 12bpc */
1289         if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK)
1290                 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1291
1292         return status;
1293 }
1294
1295 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1296 {
1297         struct drm_device *dev = crtc_state->base.crtc->dev;
1298
1299         if (HAS_GMCH_DISPLAY(to_i915(dev)))
1300                 return false;
1301
1302         /*
1303          * HDMI 12bpc affects the clocks, so it's only possible
1304          * when not cloning with other encoder types.
1305          */
1306         return crtc_state->output_types == 1 << INTEL_OUTPUT_HDMI;
1307 }
1308
1309 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1310                                struct intel_crtc_state *pipe_config,
1311                                struct drm_connector_state *conn_state)
1312 {
1313         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1314         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1315         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1316         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1317         int clock_12bpc = clock_8bpc * 3 / 2;
1318         int desired_bpp;
1319
1320         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1321
1322         if (pipe_config->has_hdmi_sink)
1323                 pipe_config->has_infoframe = true;
1324
1325         if (intel_hdmi->color_range_auto) {
1326                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1327                 pipe_config->limited_color_range =
1328                         pipe_config->has_hdmi_sink &&
1329                         drm_match_cea_mode(adjusted_mode) > 1;
1330         } else {
1331                 pipe_config->limited_color_range =
1332                         intel_hdmi->limited_color_range;
1333         }
1334
1335         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1336                 pipe_config->pixel_multiplier = 2;
1337                 clock_8bpc *= 2;
1338                 clock_12bpc *= 2;
1339         }
1340
1341         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1342                 pipe_config->has_pch_encoder = true;
1343
1344         if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1345                 pipe_config->has_audio = true;
1346
1347         /*
1348          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1349          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1350          * outputs. We also need to check that the higher clock still fits
1351          * within limits.
1352          */
1353         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1354             hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK &&
1355             hdmi_12bpc_possible(pipe_config)) {
1356                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1357                 desired_bpp = 12*3;
1358
1359                 /* Need to adjust the port link by 1.5x for 12bpc. */
1360                 pipe_config->port_clock = clock_12bpc;
1361         } else {
1362                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1363                 desired_bpp = 8*3;
1364
1365                 pipe_config->port_clock = clock_8bpc;
1366         }
1367
1368         if (!pipe_config->bw_constrained) {
1369                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1370                 pipe_config->pipe_bpp = desired_bpp;
1371         }
1372
1373         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1374                                   false) != MODE_OK) {
1375                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1376                 return false;
1377         }
1378
1379         /* Set user selected PAR to incoming mode's member */
1380         adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1381
1382         pipe_config->lane_count = 4;
1383
1384         return true;
1385 }
1386
1387 static void
1388 intel_hdmi_unset_edid(struct drm_connector *connector)
1389 {
1390         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1391
1392         intel_hdmi->has_hdmi_sink = false;
1393         intel_hdmi->has_audio = false;
1394         intel_hdmi->rgb_quant_range_selectable = false;
1395
1396         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1397         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1398
1399         kfree(to_intel_connector(connector)->detect_edid);
1400         to_intel_connector(connector)->detect_edid = NULL;
1401 }
1402
1403 static void
1404 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1405 {
1406         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1407         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1408         enum port port = hdmi_to_dig_port(hdmi)->port;
1409         struct i2c_adapter *adapter =
1410                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1411         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1412
1413         /*
1414          * Type 1 DVI adaptors are not required to implement any
1415          * registers, so we can't always detect their presence.
1416          * Ideally we should be able to check the state of the
1417          * CONFIG1 pin, but no such luck on our hardware.
1418          *
1419          * The only method left to us is to check the VBT to see
1420          * if the port is a dual mode capable DP port. But let's
1421          * only do that when we sucesfully read the EDID, to avoid
1422          * confusing log messages about DP dual mode adaptors when
1423          * there's nothing connected to the port.
1424          */
1425         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1426                 if (has_edid &&
1427                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1428                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1429                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1430                 } else {
1431                         type = DRM_DP_DUAL_MODE_NONE;
1432                 }
1433         }
1434
1435         if (type == DRM_DP_DUAL_MODE_NONE)
1436                 return;
1437
1438         hdmi->dp_dual_mode.type = type;
1439         hdmi->dp_dual_mode.max_tmds_clock =
1440                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1441
1442         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1443                       drm_dp_get_dual_mode_type_name(type),
1444                       hdmi->dp_dual_mode.max_tmds_clock);
1445 }
1446
1447 static bool
1448 intel_hdmi_set_edid(struct drm_connector *connector)
1449 {
1450         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1451         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1452         struct edid *edid;
1453         bool connected = false;
1454
1455         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1456
1457         edid = drm_get_edid(connector,
1458                             intel_gmbus_get_adapter(dev_priv,
1459                             intel_hdmi->ddc_bus));
1460
1461         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1462
1463         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1464
1465         to_intel_connector(connector)->detect_edid = edid;
1466         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1467                 intel_hdmi->rgb_quant_range_selectable =
1468                         drm_rgb_quant_range_selectable(edid);
1469
1470                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1471                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1472                         intel_hdmi->has_audio =
1473                                 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1474
1475                 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1476                         intel_hdmi->has_hdmi_sink =
1477                                 drm_detect_hdmi_monitor(edid);
1478
1479                 connected = true;
1480         }
1481
1482         return connected;
1483 }
1484
1485 static enum drm_connector_status
1486 intel_hdmi_detect(struct drm_connector *connector, bool force)
1487 {
1488         enum drm_connector_status status;
1489         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1490
1491         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1492                       connector->base.id, connector->name);
1493
1494         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1495
1496         intel_hdmi_unset_edid(connector);
1497
1498         if (intel_hdmi_set_edid(connector)) {
1499                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1500
1501                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1502                 status = connector_status_connected;
1503         } else
1504                 status = connector_status_disconnected;
1505
1506         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1507
1508         return status;
1509 }
1510
1511 static void
1512 intel_hdmi_force(struct drm_connector *connector)
1513 {
1514         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1515
1516         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1517                       connector->base.id, connector->name);
1518
1519         intel_hdmi_unset_edid(connector);
1520
1521         if (connector->status != connector_status_connected)
1522                 return;
1523
1524         intel_hdmi_set_edid(connector);
1525         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1526 }
1527
1528 static int intel_hdmi_get_modes(struct drm_connector *connector)
1529 {
1530         struct edid *edid;
1531
1532         edid = to_intel_connector(connector)->detect_edid;
1533         if (edid == NULL)
1534                 return 0;
1535
1536         return intel_connector_update_modes(connector, edid);
1537 }
1538
1539 static bool
1540 intel_hdmi_detect_audio(struct drm_connector *connector)
1541 {
1542         bool has_audio = false;
1543         struct edid *edid;
1544
1545         edid = to_intel_connector(connector)->detect_edid;
1546         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1547                 has_audio = drm_detect_monitor_audio(edid);
1548
1549         return has_audio;
1550 }
1551
1552 static int
1553 intel_hdmi_set_property(struct drm_connector *connector,
1554                         struct drm_property *property,
1555                         uint64_t val)
1556 {
1557         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1558         struct intel_digital_port *intel_dig_port =
1559                 hdmi_to_dig_port(intel_hdmi);
1560         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1561         int ret;
1562
1563         ret = drm_object_property_set_value(&connector->base, property, val);
1564         if (ret)
1565                 return ret;
1566
1567         if (property == dev_priv->force_audio_property) {
1568                 enum hdmi_force_audio i = val;
1569                 bool has_audio;
1570
1571                 if (i == intel_hdmi->force_audio)
1572                         return 0;
1573
1574                 intel_hdmi->force_audio = i;
1575
1576                 if (i == HDMI_AUDIO_AUTO)
1577                         has_audio = intel_hdmi_detect_audio(connector);
1578                 else
1579                         has_audio = (i == HDMI_AUDIO_ON);
1580
1581                 if (i == HDMI_AUDIO_OFF_DVI)
1582                         intel_hdmi->has_hdmi_sink = 0;
1583
1584                 intel_hdmi->has_audio = has_audio;
1585                 goto done;
1586         }
1587
1588         if (property == dev_priv->broadcast_rgb_property) {
1589                 bool old_auto = intel_hdmi->color_range_auto;
1590                 bool old_range = intel_hdmi->limited_color_range;
1591
1592                 switch (val) {
1593                 case INTEL_BROADCAST_RGB_AUTO:
1594                         intel_hdmi->color_range_auto = true;
1595                         break;
1596                 case INTEL_BROADCAST_RGB_FULL:
1597                         intel_hdmi->color_range_auto = false;
1598                         intel_hdmi->limited_color_range = false;
1599                         break;
1600                 case INTEL_BROADCAST_RGB_LIMITED:
1601                         intel_hdmi->color_range_auto = false;
1602                         intel_hdmi->limited_color_range = true;
1603                         break;
1604                 default:
1605                         return -EINVAL;
1606                 }
1607
1608                 if (old_auto == intel_hdmi->color_range_auto &&
1609                     old_range == intel_hdmi->limited_color_range)
1610                         return 0;
1611
1612                 goto done;
1613         }
1614
1615         if (property == connector->dev->mode_config.aspect_ratio_property) {
1616                 switch (val) {
1617                 case DRM_MODE_PICTURE_ASPECT_NONE:
1618                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1619                         break;
1620                 case DRM_MODE_PICTURE_ASPECT_4_3:
1621                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1622                         break;
1623                 case DRM_MODE_PICTURE_ASPECT_16_9:
1624                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1625                         break;
1626                 default:
1627                         return -EINVAL;
1628                 }
1629                 goto done;
1630         }
1631
1632         return -EINVAL;
1633
1634 done:
1635         if (intel_dig_port->base.base.crtc)
1636                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1637
1638         return 0;
1639 }
1640
1641 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1642                                   struct intel_crtc_state *pipe_config,
1643                                   struct drm_connector_state *conn_state)
1644 {
1645         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1646         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1647
1648         intel_hdmi_prepare(encoder);
1649
1650         intel_hdmi->set_infoframes(&encoder->base,
1651                                    pipe_config->has_hdmi_sink,
1652                                    adjusted_mode);
1653 }
1654
1655 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1656                                 struct intel_crtc_state *pipe_config,
1657                                 struct drm_connector_state *conn_state)
1658 {
1659         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1660         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1661         struct drm_device *dev = encoder->base.dev;
1662         struct drm_i915_private *dev_priv = to_i915(dev);
1663         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1664
1665         vlv_phy_pre_encoder_enable(encoder);
1666
1667         /* HDMI 1.0V-2dB */
1668         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1669                                  0x2b247878);
1670
1671         intel_hdmi->set_infoframes(&encoder->base,
1672                                    pipe_config->has_hdmi_sink,
1673                                    adjusted_mode);
1674
1675         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1676
1677         vlv_wait_port_ready(dev_priv, dport, 0x0);
1678 }
1679
1680 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1681                                     struct intel_crtc_state *pipe_config,
1682                                     struct drm_connector_state *conn_state)
1683 {
1684         intel_hdmi_prepare(encoder);
1685
1686         vlv_phy_pre_pll_enable(encoder);
1687 }
1688
1689 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1690                                     struct intel_crtc_state *pipe_config,
1691                                     struct drm_connector_state *conn_state)
1692 {
1693         intel_hdmi_prepare(encoder);
1694
1695         chv_phy_pre_pll_enable(encoder);
1696 }
1697
1698 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
1699                                       struct intel_crtc_state *old_crtc_state,
1700                                       struct drm_connector_state *old_conn_state)
1701 {
1702         chv_phy_post_pll_disable(encoder);
1703 }
1704
1705 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
1706                                   struct intel_crtc_state *old_crtc_state,
1707                                   struct drm_connector_state *old_conn_state)
1708 {
1709         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1710         vlv_phy_reset_lanes(encoder);
1711 }
1712
1713 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
1714                                   struct intel_crtc_state *old_crtc_state,
1715                                   struct drm_connector_state *old_conn_state)
1716 {
1717         struct drm_device *dev = encoder->base.dev;
1718         struct drm_i915_private *dev_priv = to_i915(dev);
1719
1720         mutex_lock(&dev_priv->sb_lock);
1721
1722         /* Assert data lane reset */
1723         chv_data_lane_soft_reset(encoder, true);
1724
1725         mutex_unlock(&dev_priv->sb_lock);
1726 }
1727
1728 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
1729                                 struct intel_crtc_state *pipe_config,
1730                                 struct drm_connector_state *conn_state)
1731 {
1732         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1733         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1734         struct drm_device *dev = encoder->base.dev;
1735         struct drm_i915_private *dev_priv = to_i915(dev);
1736         struct intel_crtc *intel_crtc =
1737                 to_intel_crtc(encoder->base.crtc);
1738         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1739
1740         chv_phy_pre_encoder_enable(encoder);
1741
1742         /* FIXME: Program the support xxx V-dB */
1743         /* Use 800mV-0dB */
1744         chv_set_phy_signal_level(encoder, 128, 102, false);
1745
1746         intel_hdmi->set_infoframes(&encoder->base,
1747                                    intel_crtc->config->has_hdmi_sink,
1748                                    adjusted_mode);
1749
1750         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1751
1752         vlv_wait_port_ready(dev_priv, dport, 0x0);
1753
1754         /* Second common lane will stay alive on its own now */
1755         chv_phy_release_cl2_override(encoder);
1756 }
1757
1758 static void intel_hdmi_destroy(struct drm_connector *connector)
1759 {
1760         kfree(to_intel_connector(connector)->detect_edid);
1761         drm_connector_cleanup(connector);
1762         kfree(connector);
1763 }
1764
1765 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1766         .dpms = drm_atomic_helper_connector_dpms,
1767         .detect = intel_hdmi_detect,
1768         .force = intel_hdmi_force,
1769         .fill_modes = drm_helper_probe_single_connector_modes,
1770         .set_property = intel_hdmi_set_property,
1771         .atomic_get_property = intel_connector_atomic_get_property,
1772         .late_register = intel_connector_register,
1773         .early_unregister = intel_connector_unregister,
1774         .destroy = intel_hdmi_destroy,
1775         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1776         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1777 };
1778
1779 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1780         .get_modes = intel_hdmi_get_modes,
1781         .mode_valid = intel_hdmi_mode_valid,
1782 };
1783
1784 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1785         .destroy = intel_encoder_destroy,
1786 };
1787
1788 static void
1789 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1790 {
1791         intel_attach_force_audio_property(connector);
1792         intel_attach_broadcast_rgb_property(connector);
1793         intel_hdmi->color_range_auto = true;
1794         intel_attach_aspect_ratio_property(connector);
1795         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1796 }
1797
1798 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
1799                              enum port port)
1800 {
1801         const struct ddi_vbt_port_info *info =
1802                 &dev_priv->vbt.ddi_port_info[port];
1803         u8 ddc_pin;
1804
1805         if (info->alternate_ddc_pin) {
1806                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
1807                               info->alternate_ddc_pin, port_name(port));
1808                 return info->alternate_ddc_pin;
1809         }
1810
1811         switch (port) {
1812         case PORT_B:
1813                 if (IS_BROXTON(dev_priv))
1814                         ddc_pin = GMBUS_PIN_1_BXT;
1815                 else
1816                         ddc_pin = GMBUS_PIN_DPB;
1817                 break;
1818         case PORT_C:
1819                 if (IS_BROXTON(dev_priv))
1820                         ddc_pin = GMBUS_PIN_2_BXT;
1821                 else
1822                         ddc_pin = GMBUS_PIN_DPC;
1823                 break;
1824         case PORT_D:
1825                 if (IS_CHERRYVIEW(dev_priv))
1826                         ddc_pin = GMBUS_PIN_DPD_CHV;
1827                 else
1828                         ddc_pin = GMBUS_PIN_DPD;
1829                 break;
1830         default:
1831                 MISSING_CASE(port);
1832                 ddc_pin = GMBUS_PIN_DPB;
1833                 break;
1834         }
1835
1836         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
1837                       ddc_pin, port_name(port));
1838
1839         return ddc_pin;
1840 }
1841
1842 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1843                                struct intel_connector *intel_connector)
1844 {
1845         struct drm_connector *connector = &intel_connector->base;
1846         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1847         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1848         struct drm_device *dev = intel_encoder->base.dev;
1849         struct drm_i915_private *dev_priv = to_i915(dev);
1850         enum port port = intel_dig_port->port;
1851
1852         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
1853                       port_name(port));
1854
1855         if (WARN(intel_dig_port->max_lanes < 4,
1856                  "Not enough lanes (%d) for HDMI on port %c\n",
1857                  intel_dig_port->max_lanes, port_name(port)))
1858                 return;
1859
1860         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1861                            DRM_MODE_CONNECTOR_HDMIA);
1862         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1863
1864         connector->interlace_allowed = 1;
1865         connector->doublescan_allowed = 0;
1866         connector->stereo_allowed = 1;
1867
1868         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
1869
1870         switch (port) {
1871         case PORT_B:
1872                 /*
1873                  * On BXT A0/A1, sw needs to activate DDIA HPD logic and
1874                  * interrupts to check the external panel connection.
1875                  */
1876                 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1877                         intel_encoder->hpd_pin = HPD_PORT_A;
1878                 else
1879                         intel_encoder->hpd_pin = HPD_PORT_B;
1880                 break;
1881         case PORT_C:
1882                 intel_encoder->hpd_pin = HPD_PORT_C;
1883                 break;
1884         case PORT_D:
1885                 intel_encoder->hpd_pin = HPD_PORT_D;
1886                 break;
1887         case PORT_E:
1888                 intel_encoder->hpd_pin = HPD_PORT_E;
1889                 break;
1890         default:
1891                 MISSING_CASE(port);
1892                 return;
1893         }
1894
1895         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1896                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1897                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1898                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1899         } else if (IS_G4X(dev_priv)) {
1900                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1901                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1902                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1903         } else if (HAS_DDI(dev_priv)) {
1904                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1905                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1906                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1907         } else if (HAS_PCH_IBX(dev_priv)) {
1908                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1909                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1910                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1911         } else {
1912                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1913                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1914                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1915         }
1916
1917         if (HAS_DDI(dev_priv))
1918                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1919         else
1920                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1921
1922         intel_hdmi_add_properties(intel_hdmi, connector);
1923
1924         intel_connector_attach_encoder(intel_connector, intel_encoder);
1925         intel_hdmi->attached_connector = intel_connector;
1926
1927         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1928          * 0xd.  Failure to do so will result in spurious interrupts being
1929          * generated on the port when a cable is not attached.
1930          */
1931         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
1932                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1933                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1934         }
1935 }
1936
1937 void intel_hdmi_init(struct drm_device *dev,
1938                      i915_reg_t hdmi_reg, enum port port)
1939 {
1940         struct drm_i915_private *dev_priv = to_i915(dev);
1941         struct intel_digital_port *intel_dig_port;
1942         struct intel_encoder *intel_encoder;
1943         struct intel_connector *intel_connector;
1944
1945         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1946         if (!intel_dig_port)
1947                 return;
1948
1949         intel_connector = intel_connector_alloc();
1950         if (!intel_connector) {
1951                 kfree(intel_dig_port);
1952                 return;
1953         }
1954
1955         intel_encoder = &intel_dig_port->base;
1956
1957         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1958                          DRM_MODE_ENCODER_TMDS, "HDMI %c", port_name(port));
1959
1960         intel_encoder->compute_config = intel_hdmi_compute_config;
1961         if (HAS_PCH_SPLIT(dev_priv)) {
1962                 intel_encoder->disable = pch_disable_hdmi;
1963                 intel_encoder->post_disable = pch_post_disable_hdmi;
1964         } else {
1965                 intel_encoder->disable = g4x_disable_hdmi;
1966         }
1967         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1968         intel_encoder->get_config = intel_hdmi_get_config;
1969         if (IS_CHERRYVIEW(dev_priv)) {
1970                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1971                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1972                 intel_encoder->enable = vlv_enable_hdmi;
1973                 intel_encoder->post_disable = chv_hdmi_post_disable;
1974                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
1975         } else if (IS_VALLEYVIEW(dev_priv)) {
1976                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1977                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1978                 intel_encoder->enable = vlv_enable_hdmi;
1979                 intel_encoder->post_disable = vlv_hdmi_post_disable;
1980         } else {
1981                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1982                 if (HAS_PCH_CPT(dev_priv))
1983                         intel_encoder->enable = cpt_enable_hdmi;
1984                 else if (HAS_PCH_IBX(dev_priv))
1985                         intel_encoder->enable = ibx_enable_hdmi;
1986                 else
1987                         intel_encoder->enable = g4x_enable_hdmi;
1988         }
1989
1990         intel_encoder->type = INTEL_OUTPUT_HDMI;
1991         intel_encoder->port = port;
1992         if (IS_CHERRYVIEW(dev_priv)) {
1993                 if (port == PORT_D)
1994                         intel_encoder->crtc_mask = 1 << 2;
1995                 else
1996                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1997         } else {
1998                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1999         }
2000         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2001         /*
2002          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2003          * to work on real hardware. And since g4x can send infoframes to
2004          * only one port anyway, nothing is lost by allowing it.
2005          */
2006         if (IS_G4X(dev_priv))
2007                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2008
2009         intel_dig_port->port = port;
2010         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2011         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2012         intel_dig_port->max_lanes = 4;
2013
2014         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2015 }