2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_scdc_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
40 #include <drm/intel_lpe_audio.h>
43 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
45 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
49 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
51 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
52 struct drm_i915_private *dev_priv = to_i915(dev);
53 uint32_t enabled_bits;
55 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
57 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
58 "HDMI port enabled, expecting disabled\n");
61 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
63 struct intel_digital_port *intel_dig_port =
64 container_of(encoder, struct intel_digital_port, base.base);
65 return &intel_dig_port->hdmi;
68 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
70 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
73 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
76 case HDMI_INFOFRAME_TYPE_AVI:
77 return VIDEO_DIP_SELECT_AVI;
78 case HDMI_INFOFRAME_TYPE_SPD:
79 return VIDEO_DIP_SELECT_SPD;
80 case HDMI_INFOFRAME_TYPE_VENDOR:
81 return VIDEO_DIP_SELECT_VENDOR;
88 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
91 case HDMI_INFOFRAME_TYPE_AVI:
92 return VIDEO_DIP_ENABLE_AVI;
93 case HDMI_INFOFRAME_TYPE_SPD:
94 return VIDEO_DIP_ENABLE_SPD;
95 case HDMI_INFOFRAME_TYPE_VENDOR:
96 return VIDEO_DIP_ENABLE_VENDOR;
103 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
106 case HDMI_INFOFRAME_TYPE_AVI:
107 return VIDEO_DIP_ENABLE_AVI_HSW;
108 case HDMI_INFOFRAME_TYPE_SPD:
109 return VIDEO_DIP_ENABLE_SPD_HSW;
110 case HDMI_INFOFRAME_TYPE_VENDOR:
111 return VIDEO_DIP_ENABLE_VS_HSW;
119 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
120 enum transcoder cpu_transcoder,
121 enum hdmi_infoframe_type type,
125 case HDMI_INFOFRAME_TYPE_AVI:
126 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
127 case HDMI_INFOFRAME_TYPE_SPD:
128 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
129 case HDMI_INFOFRAME_TYPE_VENDOR:
130 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
133 return INVALID_MMIO_REG;
137 static void g4x_write_infoframe(struct drm_encoder *encoder,
138 const struct intel_crtc_state *crtc_state,
139 enum hdmi_infoframe_type type,
140 const void *frame, ssize_t len)
142 const uint32_t *data = frame;
143 struct drm_device *dev = encoder->dev;
144 struct drm_i915_private *dev_priv = to_i915(dev);
145 u32 val = I915_READ(VIDEO_DIP_CTL);
148 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
150 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
151 val |= g4x_infoframe_index(type);
153 val &= ~g4x_infoframe_enable(type);
155 I915_WRITE(VIDEO_DIP_CTL, val);
158 for (i = 0; i < len; i += 4) {
159 I915_WRITE(VIDEO_DIP_DATA, *data);
162 /* Write every possible data byte to force correct ECC calculation. */
163 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
164 I915_WRITE(VIDEO_DIP_DATA, 0);
167 val |= g4x_infoframe_enable(type);
168 val &= ~VIDEO_DIP_FREQ_MASK;
169 val |= VIDEO_DIP_FREQ_VSYNC;
171 I915_WRITE(VIDEO_DIP_CTL, val);
172 POSTING_READ(VIDEO_DIP_CTL);
175 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
176 const struct intel_crtc_state *pipe_config)
178 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
179 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
180 u32 val = I915_READ(VIDEO_DIP_CTL);
182 if ((val & VIDEO_DIP_ENABLE) == 0)
185 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
188 return val & (VIDEO_DIP_ENABLE_AVI |
189 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
192 static void ibx_write_infoframe(struct drm_encoder *encoder,
193 const struct intel_crtc_state *crtc_state,
194 enum hdmi_infoframe_type type,
195 const void *frame, ssize_t len)
197 const uint32_t *data = frame;
198 struct drm_device *dev = encoder->dev;
199 struct drm_i915_private *dev_priv = to_i915(dev);
200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
201 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
202 u32 val = I915_READ(reg);
205 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
207 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
208 val |= g4x_infoframe_index(type);
210 val &= ~g4x_infoframe_enable(type);
212 I915_WRITE(reg, val);
215 for (i = 0; i < len; i += 4) {
216 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
219 /* Write every possible data byte to force correct ECC calculation. */
220 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
221 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
224 val |= g4x_infoframe_enable(type);
225 val &= ~VIDEO_DIP_FREQ_MASK;
226 val |= VIDEO_DIP_FREQ_VSYNC;
228 I915_WRITE(reg, val);
232 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
233 const struct intel_crtc_state *pipe_config)
235 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
236 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
237 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
238 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
239 u32 val = I915_READ(reg);
241 if ((val & VIDEO_DIP_ENABLE) == 0)
244 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
247 return val & (VIDEO_DIP_ENABLE_AVI |
248 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
249 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
252 static void cpt_write_infoframe(struct drm_encoder *encoder,
253 const struct intel_crtc_state *crtc_state,
254 enum hdmi_infoframe_type type,
255 const void *frame, ssize_t len)
257 const uint32_t *data = frame;
258 struct drm_device *dev = encoder->dev;
259 struct drm_i915_private *dev_priv = to_i915(dev);
260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
261 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
262 u32 val = I915_READ(reg);
265 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
267 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
268 val |= g4x_infoframe_index(type);
270 /* The DIP control register spec says that we need to update the AVI
271 * infoframe without clearing its enable bit */
272 if (type != HDMI_INFOFRAME_TYPE_AVI)
273 val &= ~g4x_infoframe_enable(type);
275 I915_WRITE(reg, val);
278 for (i = 0; i < len; i += 4) {
279 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
282 /* Write every possible data byte to force correct ECC calculation. */
283 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
284 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
287 val |= g4x_infoframe_enable(type);
288 val &= ~VIDEO_DIP_FREQ_MASK;
289 val |= VIDEO_DIP_FREQ_VSYNC;
291 I915_WRITE(reg, val);
295 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
296 const struct intel_crtc_state *pipe_config)
298 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
299 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
300 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
302 if ((val & VIDEO_DIP_ENABLE) == 0)
305 return val & (VIDEO_DIP_ENABLE_AVI |
306 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
307 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
310 static void vlv_write_infoframe(struct drm_encoder *encoder,
311 const struct intel_crtc_state *crtc_state,
312 enum hdmi_infoframe_type type,
313 const void *frame, ssize_t len)
315 const uint32_t *data = frame;
316 struct drm_device *dev = encoder->dev;
317 struct drm_i915_private *dev_priv = to_i915(dev);
318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
319 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
320 u32 val = I915_READ(reg);
323 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
325 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
326 val |= g4x_infoframe_index(type);
328 val &= ~g4x_infoframe_enable(type);
330 I915_WRITE(reg, val);
333 for (i = 0; i < len; i += 4) {
334 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
337 /* Write every possible data byte to force correct ECC calculation. */
338 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
339 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
342 val |= g4x_infoframe_enable(type);
343 val &= ~VIDEO_DIP_FREQ_MASK;
344 val |= VIDEO_DIP_FREQ_VSYNC;
346 I915_WRITE(reg, val);
350 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
351 const struct intel_crtc_state *pipe_config)
353 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
354 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
355 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
356 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
358 if ((val & VIDEO_DIP_ENABLE) == 0)
361 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
364 return val & (VIDEO_DIP_ENABLE_AVI |
365 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
366 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
369 static void hsw_write_infoframe(struct drm_encoder *encoder,
370 const struct intel_crtc_state *crtc_state,
371 enum hdmi_infoframe_type type,
372 const void *frame, ssize_t len)
374 const uint32_t *data = frame;
375 struct drm_device *dev = encoder->dev;
376 struct drm_i915_private *dev_priv = to_i915(dev);
377 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
378 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
381 u32 val = I915_READ(ctl_reg);
383 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
385 val &= ~hsw_infoframe_enable(type);
386 I915_WRITE(ctl_reg, val);
389 for (i = 0; i < len; i += 4) {
390 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
391 type, i >> 2), *data);
394 /* Write every possible data byte to force correct ECC calculation. */
395 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
396 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
400 val |= hsw_infoframe_enable(type);
401 I915_WRITE(ctl_reg, val);
402 POSTING_READ(ctl_reg);
405 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
406 const struct intel_crtc_state *pipe_config)
408 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
409 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
411 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
412 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
413 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
417 * The data we write to the DIP data buffer registers is 1 byte bigger than the
418 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
419 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
420 * used for both technologies.
422 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
423 * DW1: DB3 | DB2 | DB1 | DB0
424 * DW2: DB7 | DB6 | DB5 | DB4
427 * (HB is Header Byte, DB is Data Byte)
429 * The hdmi pack() functions don't know about that hardware specific hole so we
430 * trick them by giving an offset into the buffer and moving back the header
433 static void intel_write_infoframe(struct drm_encoder *encoder,
434 const struct intel_crtc_state *crtc_state,
435 union hdmi_infoframe *frame)
437 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
438 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
441 /* see comment above for the reason for this offset */
442 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
446 /* Insert the 'hole' (see big comment above) at position 3 */
447 buffer[0] = buffer[1];
448 buffer[1] = buffer[2];
449 buffer[2] = buffer[3];
453 intel_hdmi->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
456 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
457 const struct intel_crtc_state *crtc_state)
459 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
460 const struct drm_display_mode *adjusted_mode =
461 &crtc_state->base.adjusted_mode;
462 union hdmi_infoframe frame;
465 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
468 DRM_ERROR("couldn't fill AVI infoframe\n");
472 drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
473 crtc_state->limited_color_range ?
474 HDMI_QUANTIZATION_RANGE_LIMITED :
475 HDMI_QUANTIZATION_RANGE_FULL,
476 intel_hdmi->rgb_quant_range_selectable);
478 intel_write_infoframe(encoder, crtc_state, &frame);
481 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder,
482 const struct intel_crtc_state *crtc_state)
484 union hdmi_infoframe frame;
487 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
489 DRM_ERROR("couldn't fill SPD infoframe\n");
493 frame.spd.sdi = HDMI_SPD_SDI_PC;
495 intel_write_infoframe(encoder, crtc_state, &frame);
499 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
500 const struct intel_crtc_state *crtc_state)
502 union hdmi_infoframe frame;
505 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
506 &crtc_state->base.adjusted_mode);
510 intel_write_infoframe(encoder, crtc_state, &frame);
513 static void g4x_set_infoframes(struct drm_encoder *encoder,
515 const struct intel_crtc_state *crtc_state,
516 const struct drm_connector_state *conn_state)
518 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
519 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
520 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
521 i915_reg_t reg = VIDEO_DIP_CTL;
522 u32 val = I915_READ(reg);
523 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
525 assert_hdmi_port_disabled(intel_hdmi);
527 /* If the registers were not initialized yet, they might be zeroes,
528 * which means we're selecting the AVI DIP and we're setting its
529 * frequency to once. This seems to really confuse the HW and make
530 * things stop working (the register spec says the AVI always needs to
531 * be sent every VSync). So here we avoid writing to the register more
532 * than we need and also explicitly select the AVI DIP and explicitly
533 * set its frequency to every VSync. Avoiding to write it twice seems to
534 * be enough to solve the problem, but being defensive shouldn't hurt us
536 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
539 if (!(val & VIDEO_DIP_ENABLE))
541 if (port != (val & VIDEO_DIP_PORT_MASK)) {
542 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
543 (val & VIDEO_DIP_PORT_MASK) >> 29);
546 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
547 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
548 I915_WRITE(reg, val);
553 if (port != (val & VIDEO_DIP_PORT_MASK)) {
554 if (val & VIDEO_DIP_ENABLE) {
555 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
556 (val & VIDEO_DIP_PORT_MASK) >> 29);
559 val &= ~VIDEO_DIP_PORT_MASK;
563 val |= VIDEO_DIP_ENABLE;
564 val &= ~(VIDEO_DIP_ENABLE_AVI |
565 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
567 I915_WRITE(reg, val);
570 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
571 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
572 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
575 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
577 struct drm_connector *connector = conn_state->connector;
580 * HDMI cloning is only supported on g4x which doesn't
581 * support deep color or GCP infoframes anyway so no
582 * need to worry about multiple HDMI sinks here.
585 return connector->display_info.bpc > 8;
589 * Determine if default_phase=1 can be indicated in the GCP infoframe.
591 * From HDMI specification 1.4a:
592 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
593 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
594 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
595 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
598 static bool gcp_default_phase_possible(int pipe_bpp,
599 const struct drm_display_mode *mode)
601 unsigned int pixels_per_group;
605 /* 4 pixels in 5 clocks */
606 pixels_per_group = 4;
609 /* 2 pixels in 3 clocks */
610 pixels_per_group = 2;
613 /* 1 pixel in 2 clocks */
614 pixels_per_group = 1;
617 /* phase information not relevant for 8bpc */
621 return mode->crtc_hdisplay % pixels_per_group == 0 &&
622 mode->crtc_htotal % pixels_per_group == 0 &&
623 mode->crtc_hblank_start % pixels_per_group == 0 &&
624 mode->crtc_hblank_end % pixels_per_group == 0 &&
625 mode->crtc_hsync_start % pixels_per_group == 0 &&
626 mode->crtc_hsync_end % pixels_per_group == 0 &&
627 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
628 mode->crtc_htotal/2 % pixels_per_group == 0);
631 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder,
632 const struct intel_crtc_state *crtc_state,
633 const struct drm_connector_state *conn_state)
635 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
636 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
640 if (HAS_DDI(dev_priv))
641 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
642 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
643 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
644 else if (HAS_PCH_SPLIT(dev_priv))
645 reg = TVIDEO_DIP_GCP(crtc->pipe);
649 /* Indicate color depth whenever the sink supports deep color */
650 if (hdmi_sink_is_deep_color(conn_state))
651 val |= GCP_COLOR_INDICATION;
653 /* Enable default_phase whenever the display mode is suitably aligned */
654 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
655 &crtc_state->base.adjusted_mode))
656 val |= GCP_DEFAULT_PHASE_ENABLE;
658 I915_WRITE(reg, val);
663 static void ibx_set_infoframes(struct drm_encoder *encoder,
665 const struct intel_crtc_state *crtc_state,
666 const struct drm_connector_state *conn_state)
668 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
670 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
671 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
672 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
673 u32 val = I915_READ(reg);
674 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
676 assert_hdmi_port_disabled(intel_hdmi);
678 /* See the big comment in g4x_set_infoframes() */
679 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
682 if (!(val & VIDEO_DIP_ENABLE))
684 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
685 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
686 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
687 I915_WRITE(reg, val);
692 if (port != (val & VIDEO_DIP_PORT_MASK)) {
693 WARN(val & VIDEO_DIP_ENABLE,
694 "DIP already enabled on port %c\n",
695 (val & VIDEO_DIP_PORT_MASK) >> 29);
696 val &= ~VIDEO_DIP_PORT_MASK;
700 val |= VIDEO_DIP_ENABLE;
701 val &= ~(VIDEO_DIP_ENABLE_AVI |
702 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
703 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
705 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
706 val |= VIDEO_DIP_ENABLE_GCP;
708 I915_WRITE(reg, val);
711 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
712 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
713 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
716 static void cpt_set_infoframes(struct drm_encoder *encoder,
718 const struct intel_crtc_state *crtc_state,
719 const struct drm_connector_state *conn_state)
721 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
723 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
724 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
725 u32 val = I915_READ(reg);
727 assert_hdmi_port_disabled(intel_hdmi);
729 /* See the big comment in g4x_set_infoframes() */
730 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
733 if (!(val & VIDEO_DIP_ENABLE))
735 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
736 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
737 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
738 I915_WRITE(reg, val);
743 /* Set both together, unset both together: see the spec. */
744 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
745 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
746 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
748 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
749 val |= VIDEO_DIP_ENABLE_GCP;
751 I915_WRITE(reg, val);
754 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
755 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
756 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
759 static void vlv_set_infoframes(struct drm_encoder *encoder,
761 const struct intel_crtc_state *crtc_state,
762 const struct drm_connector_state *conn_state)
764 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
765 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
767 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
768 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
769 u32 val = I915_READ(reg);
770 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
772 assert_hdmi_port_disabled(intel_hdmi);
774 /* See the big comment in g4x_set_infoframes() */
775 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
778 if (!(val & VIDEO_DIP_ENABLE))
780 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
781 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
782 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
783 I915_WRITE(reg, val);
788 if (port != (val & VIDEO_DIP_PORT_MASK)) {
789 WARN(val & VIDEO_DIP_ENABLE,
790 "DIP already enabled on port %c\n",
791 (val & VIDEO_DIP_PORT_MASK) >> 29);
792 val &= ~VIDEO_DIP_PORT_MASK;
796 val |= VIDEO_DIP_ENABLE;
797 val &= ~(VIDEO_DIP_ENABLE_AVI |
798 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
799 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
801 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
802 val |= VIDEO_DIP_ENABLE_GCP;
804 I915_WRITE(reg, val);
807 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
808 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
809 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
812 static void hsw_set_infoframes(struct drm_encoder *encoder,
814 const struct intel_crtc_state *crtc_state,
815 const struct drm_connector_state *conn_state)
817 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
818 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
819 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
820 u32 val = I915_READ(reg);
822 assert_hdmi_port_disabled(intel_hdmi);
824 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
825 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
826 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
829 I915_WRITE(reg, val);
834 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
835 val |= VIDEO_DIP_ENABLE_GCP_HSW;
837 I915_WRITE(reg, val);
840 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
841 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
842 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
845 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
847 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
848 struct i2c_adapter *adapter =
849 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
851 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
854 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
855 enable ? "Enabling" : "Disabling");
857 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
861 static void intel_hdmi_prepare(struct intel_encoder *encoder,
862 const struct intel_crtc_state *crtc_state)
864 struct drm_device *dev = encoder->base.dev;
865 struct drm_i915_private *dev_priv = to_i915(dev);
866 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
867 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
868 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
871 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
873 hdmi_val = SDVO_ENCODING_HDMI;
874 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
875 hdmi_val |= HDMI_COLOR_RANGE_16_235;
876 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
877 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
878 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
879 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
881 if (crtc_state->pipe_bpp > 24)
882 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
884 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
886 if (crtc_state->has_hdmi_sink)
887 hdmi_val |= HDMI_MODE_SELECT_HDMI;
889 if (HAS_PCH_CPT(dev_priv))
890 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
891 else if (IS_CHERRYVIEW(dev_priv))
892 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
894 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
896 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
897 POSTING_READ(intel_hdmi->hdmi_reg);
900 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
903 struct drm_device *dev = encoder->base.dev;
904 struct drm_i915_private *dev_priv = to_i915(dev);
905 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
909 if (!intel_display_power_get_if_enabled(dev_priv,
910 encoder->power_domain))
915 tmp = I915_READ(intel_hdmi->hdmi_reg);
917 if (!(tmp & SDVO_ENABLE))
920 if (HAS_PCH_CPT(dev_priv))
921 *pipe = PORT_TO_PIPE_CPT(tmp);
922 else if (IS_CHERRYVIEW(dev_priv))
923 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
925 *pipe = PORT_TO_PIPE(tmp);
930 intel_display_power_put(dev_priv, encoder->power_domain);
935 static void intel_hdmi_get_config(struct intel_encoder *encoder,
936 struct intel_crtc_state *pipe_config)
938 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
939 struct drm_device *dev = encoder->base.dev;
940 struct drm_i915_private *dev_priv = to_i915(dev);
944 tmp = I915_READ(intel_hdmi->hdmi_reg);
946 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
947 flags |= DRM_MODE_FLAG_PHSYNC;
949 flags |= DRM_MODE_FLAG_NHSYNC;
951 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
952 flags |= DRM_MODE_FLAG_PVSYNC;
954 flags |= DRM_MODE_FLAG_NVSYNC;
956 if (tmp & HDMI_MODE_SELECT_HDMI)
957 pipe_config->has_hdmi_sink = true;
959 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
960 pipe_config->has_infoframe = true;
962 if (tmp & SDVO_AUDIO_ENABLE)
963 pipe_config->has_audio = true;
965 if (!HAS_PCH_SPLIT(dev_priv) &&
966 tmp & HDMI_COLOR_RANGE_16_235)
967 pipe_config->limited_color_range = true;
969 pipe_config->base.adjusted_mode.flags |= flags;
971 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
972 dotclock = pipe_config->port_clock * 2 / 3;
974 dotclock = pipe_config->port_clock;
976 if (pipe_config->pixel_multiplier)
977 dotclock /= pipe_config->pixel_multiplier;
979 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
981 pipe_config->lane_count = 4;
984 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
985 struct intel_crtc_state *pipe_config,
986 struct drm_connector_state *conn_state)
988 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
990 WARN_ON(!pipe_config->has_hdmi_sink);
991 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
992 pipe_name(crtc->pipe));
993 intel_audio_codec_enable(encoder, pipe_config, conn_state);
996 static void g4x_enable_hdmi(struct intel_encoder *encoder,
997 struct intel_crtc_state *pipe_config,
998 struct drm_connector_state *conn_state)
1000 struct drm_device *dev = encoder->base.dev;
1001 struct drm_i915_private *dev_priv = to_i915(dev);
1002 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1005 temp = I915_READ(intel_hdmi->hdmi_reg);
1007 temp |= SDVO_ENABLE;
1008 if (pipe_config->has_audio)
1009 temp |= SDVO_AUDIO_ENABLE;
1011 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1012 POSTING_READ(intel_hdmi->hdmi_reg);
1014 if (pipe_config->has_audio)
1015 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1018 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1019 struct intel_crtc_state *pipe_config,
1020 struct drm_connector_state *conn_state)
1022 struct drm_device *dev = encoder->base.dev;
1023 struct drm_i915_private *dev_priv = to_i915(dev);
1024 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1027 temp = I915_READ(intel_hdmi->hdmi_reg);
1029 temp |= SDVO_ENABLE;
1030 if (pipe_config->has_audio)
1031 temp |= SDVO_AUDIO_ENABLE;
1034 * HW workaround, need to write this twice for issue
1035 * that may result in first write getting masked.
1037 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1038 POSTING_READ(intel_hdmi->hdmi_reg);
1039 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1040 POSTING_READ(intel_hdmi->hdmi_reg);
1043 * HW workaround, need to toggle enable bit off and on
1044 * for 12bpc with pixel repeat.
1046 * FIXME: BSpec says this should be done at the end of
1047 * of the modeset sequence, so not sure if this isn't too soon.
1049 if (pipe_config->pipe_bpp > 24 &&
1050 pipe_config->pixel_multiplier > 1) {
1051 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1052 POSTING_READ(intel_hdmi->hdmi_reg);
1055 * HW workaround, need to write this twice for issue
1056 * that may result in first write getting masked.
1058 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1059 POSTING_READ(intel_hdmi->hdmi_reg);
1060 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1061 POSTING_READ(intel_hdmi->hdmi_reg);
1064 if (pipe_config->has_audio)
1065 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1068 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1069 struct intel_crtc_state *pipe_config,
1070 struct drm_connector_state *conn_state)
1072 struct drm_device *dev = encoder->base.dev;
1073 struct drm_i915_private *dev_priv = to_i915(dev);
1074 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1075 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1076 enum pipe pipe = crtc->pipe;
1079 temp = I915_READ(intel_hdmi->hdmi_reg);
1081 temp |= SDVO_ENABLE;
1082 if (pipe_config->has_audio)
1083 temp |= SDVO_AUDIO_ENABLE;
1086 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1088 * The procedure for 12bpc is as follows:
1089 * 1. disable HDMI clock gating
1090 * 2. enable HDMI with 8bpc
1091 * 3. enable HDMI with 12bpc
1092 * 4. enable HDMI clock gating
1095 if (pipe_config->pipe_bpp > 24) {
1096 I915_WRITE(TRANS_CHICKEN1(pipe),
1097 I915_READ(TRANS_CHICKEN1(pipe)) |
1098 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1100 temp &= ~SDVO_COLOR_FORMAT_MASK;
1101 temp |= SDVO_COLOR_FORMAT_8bpc;
1104 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1105 POSTING_READ(intel_hdmi->hdmi_reg);
1107 if (pipe_config->pipe_bpp > 24) {
1108 temp &= ~SDVO_COLOR_FORMAT_MASK;
1109 temp |= HDMI_COLOR_FORMAT_12bpc;
1111 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1112 POSTING_READ(intel_hdmi->hdmi_reg);
1114 I915_WRITE(TRANS_CHICKEN1(pipe),
1115 I915_READ(TRANS_CHICKEN1(pipe)) &
1116 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1119 if (pipe_config->has_audio)
1120 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1123 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1124 struct intel_crtc_state *pipe_config,
1125 struct drm_connector_state *conn_state)
1129 static void intel_disable_hdmi(struct intel_encoder *encoder,
1130 struct intel_crtc_state *old_crtc_state,
1131 struct drm_connector_state *old_conn_state)
1133 struct drm_device *dev = encoder->base.dev;
1134 struct drm_i915_private *dev_priv = to_i915(dev);
1135 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1136 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1139 temp = I915_READ(intel_hdmi->hdmi_reg);
1141 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1142 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1143 POSTING_READ(intel_hdmi->hdmi_reg);
1146 * HW workaround for IBX, we need to move the port
1147 * to transcoder A after disabling it to allow the
1148 * matching DP port to be enabled on transcoder A.
1150 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1152 * We get CPU/PCH FIFO underruns on the other pipe when
1153 * doing the workaround. Sweep them under the rug.
1155 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1156 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1158 temp &= ~SDVO_PIPE_B_SELECT;
1159 temp |= SDVO_ENABLE;
1161 * HW workaround, need to write this twice for issue
1162 * that may result in first write getting masked.
1164 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1165 POSTING_READ(intel_hdmi->hdmi_reg);
1166 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1167 POSTING_READ(intel_hdmi->hdmi_reg);
1169 temp &= ~SDVO_ENABLE;
1170 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1171 POSTING_READ(intel_hdmi->hdmi_reg);
1173 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1174 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1175 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1178 intel_hdmi->set_infoframes(&encoder->base, false, old_crtc_state, old_conn_state);
1180 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1183 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1184 struct intel_crtc_state *old_crtc_state,
1185 struct drm_connector_state *old_conn_state)
1187 if (old_crtc_state->has_audio)
1188 intel_audio_codec_disable(encoder);
1190 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1193 static void pch_disable_hdmi(struct intel_encoder *encoder,
1194 struct intel_crtc_state *old_crtc_state,
1195 struct drm_connector_state *old_conn_state)
1197 if (old_crtc_state->has_audio)
1198 intel_audio_codec_disable(encoder);
1201 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1202 struct intel_crtc_state *old_crtc_state,
1203 struct drm_connector_state *old_conn_state)
1205 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1208 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
1210 if (IS_G4X(dev_priv))
1212 else if (IS_GEMINILAKE(dev_priv))
1214 else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
1220 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1221 bool respect_downstream_limits)
1223 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1224 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
1226 if (respect_downstream_limits) {
1227 struct intel_connector *connector = hdmi->attached_connector;
1228 const struct drm_display_info *info = &connector->base.display_info;
1230 if (hdmi->dp_dual_mode.max_tmds_clock)
1231 max_tmds_clock = min(max_tmds_clock,
1232 hdmi->dp_dual_mode.max_tmds_clock);
1234 if (info->max_tmds_clock)
1235 max_tmds_clock = min(max_tmds_clock,
1236 info->max_tmds_clock);
1237 else if (!hdmi->has_hdmi_sink)
1238 max_tmds_clock = min(max_tmds_clock, 165000);
1241 return max_tmds_clock;
1244 static enum drm_mode_status
1245 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1246 int clock, bool respect_downstream_limits)
1248 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1251 return MODE_CLOCK_LOW;
1252 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits))
1253 return MODE_CLOCK_HIGH;
1255 /* BXT DPLL can't generate 223-240 MHz */
1256 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1257 return MODE_CLOCK_RANGE;
1259 /* CHV DPLL can't generate 216-240 MHz */
1260 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1261 return MODE_CLOCK_RANGE;
1266 static enum drm_mode_status
1267 intel_hdmi_mode_valid(struct drm_connector *connector,
1268 struct drm_display_mode *mode)
1270 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1271 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1272 struct drm_i915_private *dev_priv = to_i915(dev);
1273 enum drm_mode_status status;
1275 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1277 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1278 return MODE_NO_DBLESCAN;
1280 clock = mode->clock;
1282 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1285 if (clock > max_dotclk)
1286 return MODE_CLOCK_HIGH;
1288 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1291 /* check if we can do 8bpc */
1292 status = hdmi_port_clock_valid(hdmi, clock, true);
1294 /* if we can't do 8bpc we may still be able to do 12bpc */
1295 if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK)
1296 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1301 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1303 struct drm_i915_private *dev_priv =
1304 to_i915(crtc_state->base.crtc->dev);
1305 struct drm_atomic_state *state = crtc_state->base.state;
1306 struct drm_connector_state *connector_state;
1307 struct drm_connector *connector;
1310 if (HAS_GMCH_DISPLAY(dev_priv))
1314 * HDMI 12bpc affects the clocks, so it's only possible
1315 * when not cloning with other encoder types.
1317 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1320 for_each_connector_in_state(state, connector, connector_state, i) {
1321 const struct drm_display_info *info = &connector->display_info;
1323 if (connector_state->crtc != crtc_state->base.crtc)
1326 if ((info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36) == 0)
1333 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1334 struct intel_crtc_state *pipe_config,
1335 struct drm_connector_state *conn_state)
1337 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1338 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1339 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1340 struct drm_scdc *scdc = &conn_state->connector->display_info.hdmi.scdc;
1341 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1342 int clock_12bpc = clock_8bpc * 3 / 2;
1345 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1347 if (pipe_config->has_hdmi_sink)
1348 pipe_config->has_infoframe = true;
1350 if (intel_hdmi->color_range_auto) {
1351 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1352 pipe_config->limited_color_range =
1353 pipe_config->has_hdmi_sink &&
1354 drm_default_rgb_quant_range(adjusted_mode) ==
1355 HDMI_QUANTIZATION_RANGE_LIMITED;
1357 pipe_config->limited_color_range =
1358 intel_hdmi->limited_color_range;
1361 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1362 pipe_config->pixel_multiplier = 2;
1367 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1368 pipe_config->has_pch_encoder = true;
1370 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1371 pipe_config->has_audio = true;
1374 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1375 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1376 * outputs. We also need to check that the higher clock still fits
1379 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1380 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK &&
1381 hdmi_12bpc_possible(pipe_config)) {
1382 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1385 /* Need to adjust the port link by 1.5x for 12bpc. */
1386 pipe_config->port_clock = clock_12bpc;
1388 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1391 pipe_config->port_clock = clock_8bpc;
1394 if (!pipe_config->bw_constrained) {
1395 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1396 pipe_config->pipe_bpp = desired_bpp;
1399 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1400 false) != MODE_OK) {
1401 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1405 /* Set user selected PAR to incoming mode's member */
1406 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1408 pipe_config->lane_count = 4;
1410 if (scdc->scrambling.supported && IS_GEMINILAKE(dev_priv)) {
1411 if (scdc->scrambling.low_rates)
1412 pipe_config->hdmi_scrambling = true;
1414 if (pipe_config->port_clock > 340000) {
1415 pipe_config->hdmi_scrambling = true;
1416 pipe_config->hdmi_high_tmds_clock_ratio = true;
1424 intel_hdmi_unset_edid(struct drm_connector *connector)
1426 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1428 intel_hdmi->has_hdmi_sink = false;
1429 intel_hdmi->has_audio = false;
1430 intel_hdmi->rgb_quant_range_selectable = false;
1432 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1433 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1435 kfree(to_intel_connector(connector)->detect_edid);
1436 to_intel_connector(connector)->detect_edid = NULL;
1440 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1442 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1443 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1444 enum port port = hdmi_to_dig_port(hdmi)->port;
1445 struct i2c_adapter *adapter =
1446 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1447 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1450 * Type 1 DVI adaptors are not required to implement any
1451 * registers, so we can't always detect their presence.
1452 * Ideally we should be able to check the state of the
1453 * CONFIG1 pin, but no such luck on our hardware.
1455 * The only method left to us is to check the VBT to see
1456 * if the port is a dual mode capable DP port. But let's
1457 * only do that when we sucesfully read the EDID, to avoid
1458 * confusing log messages about DP dual mode adaptors when
1459 * there's nothing connected to the port.
1461 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1463 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1464 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1465 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1467 type = DRM_DP_DUAL_MODE_NONE;
1471 if (type == DRM_DP_DUAL_MODE_NONE)
1474 hdmi->dp_dual_mode.type = type;
1475 hdmi->dp_dual_mode.max_tmds_clock =
1476 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1478 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1479 drm_dp_get_dual_mode_type_name(type),
1480 hdmi->dp_dual_mode.max_tmds_clock);
1484 intel_hdmi_set_edid(struct drm_connector *connector)
1486 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1487 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1489 bool connected = false;
1491 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1493 edid = drm_get_edid(connector,
1494 intel_gmbus_get_adapter(dev_priv,
1495 intel_hdmi->ddc_bus));
1497 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1499 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1501 to_intel_connector(connector)->detect_edid = edid;
1502 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1503 intel_hdmi->rgb_quant_range_selectable =
1504 drm_rgb_quant_range_selectable(edid);
1506 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1507 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1508 intel_hdmi->has_audio =
1509 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1511 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1512 intel_hdmi->has_hdmi_sink =
1513 drm_detect_hdmi_monitor(edid);
1521 static enum drm_connector_status
1522 intel_hdmi_detect(struct drm_connector *connector, bool force)
1524 enum drm_connector_status status;
1525 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1527 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1528 connector->base.id, connector->name);
1530 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1532 intel_hdmi_unset_edid(connector);
1534 if (intel_hdmi_set_edid(connector)) {
1535 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1537 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1538 status = connector_status_connected;
1540 status = connector_status_disconnected;
1542 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1548 intel_hdmi_force(struct drm_connector *connector)
1550 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1552 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1553 connector->base.id, connector->name);
1555 intel_hdmi_unset_edid(connector);
1557 if (connector->status != connector_status_connected)
1560 intel_hdmi_set_edid(connector);
1561 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1564 static int intel_hdmi_get_modes(struct drm_connector *connector)
1568 edid = to_intel_connector(connector)->detect_edid;
1572 return intel_connector_update_modes(connector, edid);
1576 intel_hdmi_detect_audio(struct drm_connector *connector)
1578 bool has_audio = false;
1581 edid = to_intel_connector(connector)->detect_edid;
1582 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1583 has_audio = drm_detect_monitor_audio(edid);
1589 intel_hdmi_set_property(struct drm_connector *connector,
1590 struct drm_property *property,
1593 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1594 struct intel_digital_port *intel_dig_port =
1595 hdmi_to_dig_port(intel_hdmi);
1596 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1599 ret = drm_object_property_set_value(&connector->base, property, val);
1603 if (property == dev_priv->force_audio_property) {
1604 enum hdmi_force_audio i = val;
1607 if (i == intel_hdmi->force_audio)
1610 intel_hdmi->force_audio = i;
1612 if (i == HDMI_AUDIO_AUTO)
1613 has_audio = intel_hdmi_detect_audio(connector);
1615 has_audio = (i == HDMI_AUDIO_ON);
1617 if (i == HDMI_AUDIO_OFF_DVI)
1618 intel_hdmi->has_hdmi_sink = 0;
1620 intel_hdmi->has_audio = has_audio;
1624 if (property == dev_priv->broadcast_rgb_property) {
1625 bool old_auto = intel_hdmi->color_range_auto;
1626 bool old_range = intel_hdmi->limited_color_range;
1629 case INTEL_BROADCAST_RGB_AUTO:
1630 intel_hdmi->color_range_auto = true;
1632 case INTEL_BROADCAST_RGB_FULL:
1633 intel_hdmi->color_range_auto = false;
1634 intel_hdmi->limited_color_range = false;
1636 case INTEL_BROADCAST_RGB_LIMITED:
1637 intel_hdmi->color_range_auto = false;
1638 intel_hdmi->limited_color_range = true;
1644 if (old_auto == intel_hdmi->color_range_auto &&
1645 old_range == intel_hdmi->limited_color_range)
1651 if (property == connector->dev->mode_config.aspect_ratio_property) {
1653 case DRM_MODE_PICTURE_ASPECT_NONE:
1654 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1656 case DRM_MODE_PICTURE_ASPECT_4_3:
1657 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1659 case DRM_MODE_PICTURE_ASPECT_16_9:
1660 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1671 if (intel_dig_port->base.base.crtc)
1672 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1677 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1678 struct intel_crtc_state *pipe_config,
1679 struct drm_connector_state *conn_state)
1681 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1683 intel_hdmi_prepare(encoder, pipe_config);
1685 intel_hdmi->set_infoframes(&encoder->base,
1686 pipe_config->has_hdmi_sink,
1687 pipe_config, conn_state);
1690 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1691 struct intel_crtc_state *pipe_config,
1692 struct drm_connector_state *conn_state)
1694 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1695 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1696 struct drm_device *dev = encoder->base.dev;
1697 struct drm_i915_private *dev_priv = to_i915(dev);
1699 vlv_phy_pre_encoder_enable(encoder);
1702 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1705 intel_hdmi->set_infoframes(&encoder->base,
1706 pipe_config->has_hdmi_sink,
1707 pipe_config, conn_state);
1709 g4x_enable_hdmi(encoder, pipe_config, conn_state);
1711 vlv_wait_port_ready(dev_priv, dport, 0x0);
1714 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1715 struct intel_crtc_state *pipe_config,
1716 struct drm_connector_state *conn_state)
1718 intel_hdmi_prepare(encoder, pipe_config);
1720 vlv_phy_pre_pll_enable(encoder);
1723 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1724 struct intel_crtc_state *pipe_config,
1725 struct drm_connector_state *conn_state)
1727 intel_hdmi_prepare(encoder, pipe_config);
1729 chv_phy_pre_pll_enable(encoder);
1732 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
1733 struct intel_crtc_state *old_crtc_state,
1734 struct drm_connector_state *old_conn_state)
1736 chv_phy_post_pll_disable(encoder);
1739 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
1740 struct intel_crtc_state *old_crtc_state,
1741 struct drm_connector_state *old_conn_state)
1743 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1744 vlv_phy_reset_lanes(encoder);
1747 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
1748 struct intel_crtc_state *old_crtc_state,
1749 struct drm_connector_state *old_conn_state)
1751 struct drm_device *dev = encoder->base.dev;
1752 struct drm_i915_private *dev_priv = to_i915(dev);
1754 mutex_lock(&dev_priv->sb_lock);
1756 /* Assert data lane reset */
1757 chv_data_lane_soft_reset(encoder, true);
1759 mutex_unlock(&dev_priv->sb_lock);
1762 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
1763 struct intel_crtc_state *pipe_config,
1764 struct drm_connector_state *conn_state)
1766 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1767 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1768 struct drm_device *dev = encoder->base.dev;
1769 struct drm_i915_private *dev_priv = to_i915(dev);
1771 chv_phy_pre_encoder_enable(encoder);
1773 /* FIXME: Program the support xxx V-dB */
1775 chv_set_phy_signal_level(encoder, 128, 102, false);
1777 intel_hdmi->set_infoframes(&encoder->base,
1778 pipe_config->has_hdmi_sink,
1779 pipe_config, conn_state);
1781 g4x_enable_hdmi(encoder, pipe_config, conn_state);
1783 vlv_wait_port_ready(dev_priv, dport, 0x0);
1785 /* Second common lane will stay alive on its own now */
1786 chv_phy_release_cl2_override(encoder);
1789 static void intel_hdmi_destroy(struct drm_connector *connector)
1791 kfree(to_intel_connector(connector)->detect_edid);
1792 drm_connector_cleanup(connector);
1796 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1797 .dpms = drm_atomic_helper_connector_dpms,
1798 .detect = intel_hdmi_detect,
1799 .force = intel_hdmi_force,
1800 .fill_modes = drm_helper_probe_single_connector_modes,
1801 .set_property = intel_hdmi_set_property,
1802 .atomic_get_property = intel_connector_atomic_get_property,
1803 .late_register = intel_connector_register,
1804 .early_unregister = intel_connector_unregister,
1805 .destroy = intel_hdmi_destroy,
1806 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1807 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1810 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1811 .get_modes = intel_hdmi_get_modes,
1812 .mode_valid = intel_hdmi_mode_valid,
1815 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1816 .destroy = intel_encoder_destroy,
1820 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1822 intel_attach_force_audio_property(connector);
1823 intel_attach_broadcast_rgb_property(connector);
1824 intel_hdmi->color_range_auto = true;
1825 intel_attach_aspect_ratio_property(connector);
1826 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1830 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
1831 * @encoder: intel_encoder
1832 * @connector: drm_connector
1833 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
1834 * or reset the high tmds clock ratio for scrambling
1835 * @scrambling: bool to Indicate if the function needs to set or reset
1838 * This function handles scrambling on HDMI 2.0 capable sinks.
1839 * If required clock rate is > 340 Mhz && scrambling is supported by sink
1840 * it enables scrambling. This should be called before enabling the HDMI
1841 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
1842 * detect a scrambled clock within 100 ms.
1844 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1845 struct drm_connector *connector,
1846 bool high_tmds_clock_ratio,
1849 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1850 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1851 struct drm_scrambling *sink_scrambling =
1852 &connector->display_info.hdmi.scdc.scrambling;
1853 struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv,
1854 intel_hdmi->ddc_bus);
1857 if (!sink_scrambling->supported)
1860 DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n",
1861 encoder->base.name, connector->name);
1863 /* Set TMDS bit clock ratio to 1/40 or 1/10 */
1864 ret = drm_scdc_set_high_tmds_clock_ratio(adptr, high_tmds_clock_ratio);
1866 DRM_ERROR("Set TMDS ratio failed\n");
1870 /* Enable/disable sink scrambling */
1871 ret = drm_scdc_set_scrambling(adptr, scrambling);
1873 DRM_ERROR("Set sink scrambling failed\n");
1877 DRM_DEBUG_KMS("sink scrambling handled\n");
1880 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
1883 const struct ddi_vbt_port_info *info =
1884 &dev_priv->vbt.ddi_port_info[port];
1887 if (info->alternate_ddc_pin) {
1888 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
1889 info->alternate_ddc_pin, port_name(port));
1890 return info->alternate_ddc_pin;
1895 if (IS_GEN9_LP(dev_priv))
1896 ddc_pin = GMBUS_PIN_1_BXT;
1898 ddc_pin = GMBUS_PIN_DPB;
1901 if (IS_GEN9_LP(dev_priv))
1902 ddc_pin = GMBUS_PIN_2_BXT;
1904 ddc_pin = GMBUS_PIN_DPC;
1907 if (IS_CHERRYVIEW(dev_priv))
1908 ddc_pin = GMBUS_PIN_DPD_CHV;
1910 ddc_pin = GMBUS_PIN_DPD;
1914 ddc_pin = GMBUS_PIN_DPB;
1918 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
1919 ddc_pin, port_name(port));
1924 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1925 struct intel_connector *intel_connector)
1927 struct drm_connector *connector = &intel_connector->base;
1928 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1929 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1930 struct drm_device *dev = intel_encoder->base.dev;
1931 struct drm_i915_private *dev_priv = to_i915(dev);
1932 enum port port = intel_dig_port->port;
1934 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
1937 if (WARN(intel_dig_port->max_lanes < 4,
1938 "Not enough lanes (%d) for HDMI on port %c\n",
1939 intel_dig_port->max_lanes, port_name(port)))
1942 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1943 DRM_MODE_CONNECTOR_HDMIA);
1944 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1946 connector->interlace_allowed = 1;
1947 connector->doublescan_allowed = 0;
1948 connector->stereo_allowed = 1;
1950 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
1954 intel_encoder->hpd_pin = HPD_PORT_B;
1957 intel_encoder->hpd_pin = HPD_PORT_C;
1960 intel_encoder->hpd_pin = HPD_PORT_D;
1963 intel_encoder->hpd_pin = HPD_PORT_E;
1970 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1971 intel_hdmi->write_infoframe = vlv_write_infoframe;
1972 intel_hdmi->set_infoframes = vlv_set_infoframes;
1973 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1974 } else if (IS_G4X(dev_priv)) {
1975 intel_hdmi->write_infoframe = g4x_write_infoframe;
1976 intel_hdmi->set_infoframes = g4x_set_infoframes;
1977 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1978 } else if (HAS_DDI(dev_priv)) {
1979 intel_hdmi->write_infoframe = hsw_write_infoframe;
1980 intel_hdmi->set_infoframes = hsw_set_infoframes;
1981 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1982 } else if (HAS_PCH_IBX(dev_priv)) {
1983 intel_hdmi->write_infoframe = ibx_write_infoframe;
1984 intel_hdmi->set_infoframes = ibx_set_infoframes;
1985 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1987 intel_hdmi->write_infoframe = cpt_write_infoframe;
1988 intel_hdmi->set_infoframes = cpt_set_infoframes;
1989 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1992 if (HAS_DDI(dev_priv))
1993 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1995 intel_connector->get_hw_state = intel_connector_get_hw_state;
1997 intel_hdmi_add_properties(intel_hdmi, connector);
1999 intel_connector_attach_encoder(intel_connector, intel_encoder);
2000 intel_hdmi->attached_connector = intel_connector;
2002 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2003 * 0xd. Failure to do so will result in spurious interrupts being
2004 * generated on the port when a cable is not attached.
2006 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
2007 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2008 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2012 void intel_hdmi_init(struct drm_i915_private *dev_priv,
2013 i915_reg_t hdmi_reg, enum port port)
2015 struct intel_digital_port *intel_dig_port;
2016 struct intel_encoder *intel_encoder;
2017 struct intel_connector *intel_connector;
2019 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2020 if (!intel_dig_port)
2023 intel_connector = intel_connector_alloc();
2024 if (!intel_connector) {
2025 kfree(intel_dig_port);
2029 intel_encoder = &intel_dig_port->base;
2031 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2032 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2033 "HDMI %c", port_name(port));
2035 intel_encoder->compute_config = intel_hdmi_compute_config;
2036 if (HAS_PCH_SPLIT(dev_priv)) {
2037 intel_encoder->disable = pch_disable_hdmi;
2038 intel_encoder->post_disable = pch_post_disable_hdmi;
2040 intel_encoder->disable = g4x_disable_hdmi;
2042 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2043 intel_encoder->get_config = intel_hdmi_get_config;
2044 if (IS_CHERRYVIEW(dev_priv)) {
2045 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2046 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2047 intel_encoder->enable = vlv_enable_hdmi;
2048 intel_encoder->post_disable = chv_hdmi_post_disable;
2049 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2050 } else if (IS_VALLEYVIEW(dev_priv)) {
2051 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2052 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2053 intel_encoder->enable = vlv_enable_hdmi;
2054 intel_encoder->post_disable = vlv_hdmi_post_disable;
2056 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2057 if (HAS_PCH_CPT(dev_priv))
2058 intel_encoder->enable = cpt_enable_hdmi;
2059 else if (HAS_PCH_IBX(dev_priv))
2060 intel_encoder->enable = ibx_enable_hdmi;
2062 intel_encoder->enable = g4x_enable_hdmi;
2065 intel_encoder->type = INTEL_OUTPUT_HDMI;
2066 intel_encoder->power_domain = intel_port_to_power_domain(port);
2067 intel_encoder->port = port;
2068 if (IS_CHERRYVIEW(dev_priv)) {
2070 intel_encoder->crtc_mask = 1 << 2;
2072 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2074 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2076 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2078 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2079 * to work on real hardware. And since g4x can send infoframes to
2080 * only one port anyway, nothing is lost by allowing it.
2082 if (IS_G4X(dev_priv))
2083 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2085 intel_dig_port->port = port;
2086 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2087 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2088 intel_dig_port->max_lanes = 4;
2090 intel_hdmi_init_connector(intel_dig_port, intel_connector);