drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_crtc.h"
  35 #include "drm_edid.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39
  40 struct intel_hdmi {
  41         struct intel_encoder base;
  42         u32 sdvox_reg;
  43         int ddc_bus;
  44         uint32_t color_range;
  45         bool has_hdmi_sink;
  46         bool has_audio;
  47         enum hdmi_force_audio force_audio;
  48         void (*write_infoframe)(struct drm_encoder *encoder,
  49                                 struct dip_infoframe *frame);
  50 };
  51
  52 static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  53 {
  54         return container_of(encoder, struct intel_hdmi, base.base);
  55 }
  56
  57 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  58 {
  59         return container_of(intel_attached_encoder(connector),
  60                             struct intel_hdmi, base);
  61 }
  62
  63 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  64 {
  65         uint8_t *data = (uint8_t *)frame;
  66         uint8_t sum = 0;
  67         unsigned i;
  68
  69         frame->checksum = 0;
  70         frame->ecc = 0;
  71
  72         for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  73                 sum += data[i];
  74
  75         frame->checksum = 0x100 - sum;
  76 }
  77
  78 static u32 intel_infoframe_index(struct dip_infoframe *frame)
  79 {
  80         u32 flags = 0;
  81
  82         switch (frame->type) {
  83         case DIP_TYPE_AVI:
  84                 flags |= VIDEO_DIP_SELECT_AVI;
  85                 break;
  86         case DIP_TYPE_SPD:
  87                 flags |= VIDEO_DIP_SELECT_SPD;
  88                 break;
  89         default:
  90                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  91                 break;
  92         }
  93
  94         return flags;
  95 }
  96
  97 static u32 intel_infoframe_enable(struct dip_infoframe *frame)
  98 {
  99         u32 flags = 0;
 100
 101         switch (frame->type) {
 102         case DIP_TYPE_AVI:
 103                 flags |= VIDEO_DIP_ENABLE_AVI;
 104                 break;
 105         case DIP_TYPE_SPD:
 106                 flags |= VIDEO_DIP_ENABLE_SPD;
 107                 break;
 108         default:
 109                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 110                 break;
 111         }
 112
 113         return flags;
 114 }
 115
 116 static void i9xx_write_infoframe(struct drm_encoder *encoder,
 117                                  struct dip_infoframe *frame)
 118 {
 119         uint32_t *data = (uint32_t *)frame;
 120         struct drm_device *dev = encoder->dev;
 121         struct drm_i915_private *dev_priv = dev->dev_private;
 122         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 123         u32 val = I915_READ(VIDEO_DIP_CTL);
 124         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 125
 126
 127         /* XXX first guess at handling video port, is this corrent? */
 128         val &= ~VIDEO_DIP_PORT_MASK;
 129         if (intel_hdmi->sdvox_reg == SDVOB)
 130                 val |= VIDEO_DIP_PORT_B;
 131         else if (intel_hdmi->sdvox_reg == SDVOC)
 132                 val |= VIDEO_DIP_PORT_C;
 133         else
 134                 return;
 135
 136         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 137         val |= intel_infoframe_index(frame);
 138
 139         val &= ~intel_infoframe_enable(frame);
 140         val |= VIDEO_DIP_ENABLE;
 141
 142         I915_WRITE(VIDEO_DIP_CTL, val);
 143
 144         for (i = 0; i < len; i += 4) {
 145                 I915_WRITE(VIDEO_DIP_DATA, *data);
 146                 data++;
 147         }
 148
 149         val |= intel_infoframe_enable(frame);
 150         val &= ~VIDEO_DIP_FREQ_MASK;
 151         val |= VIDEO_DIP_FREQ_VSYNC;
 152
 153         I915_WRITE(VIDEO_DIP_CTL, val);
 154 }
 155
 156 static void ibx_write_infoframe(struct drm_encoder *encoder,
 157                                 struct dip_infoframe *frame)
 158 {
 159         uint32_t *data = (uint32_t *)frame;
 160         struct drm_device *dev = encoder->dev;
 161         struct drm_i915_private *dev_priv = dev->dev_private;
 162         struct drm_crtc *crtc = encoder->crtc;
 163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 164         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 165         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 166         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 167         u32 val = I915_READ(reg);
 168
 169         val &= ~VIDEO_DIP_PORT_MASK;
 170         switch (intel_hdmi->sdvox_reg) {
 171         case HDMIB:
 172                 val |= VIDEO_DIP_PORT_B;
 173                 break;
 174         case HDMIC:
 175                 val |= VIDEO_DIP_PORT_C;
 176                 break;
 177         case HDMID:
 178                 val |= VIDEO_DIP_PORT_D;
 179                 break;
 180         default:
 181                 return;
 182         }
 183
 184         intel_wait_for_vblank(dev, intel_crtc->pipe);
 185
 186         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 187         val |= intel_infoframe_index(frame);
 188
 189         val &= ~intel_infoframe_enable(frame);
 190         val |= VIDEO_DIP_ENABLE;
 191
 192         I915_WRITE(reg, val);
 193
 194         for (i = 0; i < len; i += 4) {
 195                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 196                 data++;
 197         }
 198
 199         val |= intel_infoframe_enable(frame);
 200         val &= ~VIDEO_DIP_FREQ_MASK;
 201         val |= VIDEO_DIP_FREQ_VSYNC;
 202
 203         I915_WRITE(reg, val);
 204 }
 205
 206 static void cpt_write_infoframe(struct drm_encoder *encoder,
 207                                 struct dip_infoframe *frame)
 208 {
 209         uint32_t *data = (uint32_t *)frame;
 210         struct drm_device *dev = encoder->dev;
 211         struct drm_i915_private *dev_priv = dev->dev_private;
 212         struct drm_crtc *crtc = encoder->crtc;
 213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 214         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 215         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 216         u32 val = I915_READ(reg);
 217
 218         intel_wait_for_vblank(dev, intel_crtc->pipe);
 219
 220         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 221         val |= intel_infoframe_index(frame);
 222
 223         /* The DIP control register spec says that we need to update the AVI
 224          * infoframe without clearing its enable bit */
 225         if (frame->type == DIP_TYPE_AVI)
 226                 val |= VIDEO_DIP_ENABLE_AVI;
 227         else
 228                 val &= ~intel_infoframe_enable(frame);
 229
 230         val |= VIDEO_DIP_ENABLE;
 231
 232         I915_WRITE(reg, val);
 233
 234         for (i = 0; i < len; i += 4) {
 235                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 236                 data++;
 237         }
 238
 239         val |= intel_infoframe_enable(frame);
 240         val &= ~VIDEO_DIP_FREQ_MASK;
 241         val |= VIDEO_DIP_FREQ_VSYNC;
 242
 243         I915_WRITE(reg, val);
 244 }
 245
 246 static void vlv_write_infoframe(struct drm_encoder *encoder,
 247                                      struct dip_infoframe *frame)
 248 {
 249         uint32_t *data = (uint32_t *)frame;
 250         struct drm_device *dev = encoder->dev;
 251         struct drm_i915_private *dev_priv = dev->dev_private;
 252         struct drm_crtc *crtc = encoder->crtc;
 253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 254         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 255         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 256         u32 val = I915_READ(reg);
 257
 258         intel_wait_for_vblank(dev, intel_crtc->pipe);
 259
 260         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 261         val |= intel_infoframe_index(frame);
 262
 263         val &= ~intel_infoframe_enable(frame);
 264         val |= VIDEO_DIP_ENABLE;
 265
 266         I915_WRITE(reg, val);
 267
 268         for (i = 0; i < len; i += 4) {
 269                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 270                 data++;
 271         }
 272
 273         val |= intel_infoframe_enable(frame);
 274         val &= ~VIDEO_DIP_FREQ_MASK;
 275         val |= VIDEO_DIP_FREQ_VSYNC;
 276
 277         I915_WRITE(reg, val);
 278 }
 279
 280 static void intel_set_infoframe(struct drm_encoder *encoder,
 281                                 struct dip_infoframe *frame)
 282 {
 283         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 284
 285         if (!intel_hdmi->has_hdmi_sink)
 286                 return;
 287
 288         intel_dip_infoframe_csum(frame);
 289         intel_hdmi->write_infoframe(encoder, frame);
 290 }
 291
 292 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 293                                          struct drm_display_mode *adjusted_mode)
 294 {
 295         struct dip_infoframe avi_if = {
 296                 .type = DIP_TYPE_AVI,
 297                 .ver = DIP_VERSION_AVI,
 298                 .len = DIP_LEN_AVI,
 299         };
 300
 301         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 302                 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
 303
 304         intel_set_infoframe(encoder, &avi_if);
 305 }
 306
 307 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 308 {
 309         struct dip_infoframe spd_if;
 310
 311         memset(&spd_if, 0, sizeof(spd_if));
 312         spd_if.type = DIP_TYPE_SPD;
 313         spd_if.ver = DIP_VERSION_SPD;
 314         spd_if.len = DIP_LEN_SPD;
 315         strcpy(spd_if.body.spd.vn, "Intel");
 316         strcpy(spd_if.body.spd.pd, "Integrated gfx");
 317         spd_if.body.spd.sdi = DIP_SPD_PC;
 318
 319         intel_set_infoframe(encoder, &spd_if);
 320 }
 321
 322 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
 323                                 struct drm_display_mode *mode,
 324                                 struct drm_display_mode *adjusted_mode)
 325 {
 326         struct drm_device *dev = encoder->dev;
 327         struct drm_i915_private *dev_priv = dev->dev_private;
 328         struct drm_crtc *crtc = encoder->crtc;
 329         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 330         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 331         u32 sdvox;
 332
 333         sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
 334         if (!HAS_PCH_SPLIT(dev))
 335                 sdvox |= intel_hdmi->color_range;
 336         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 337                 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
 338         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 339                 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
 340
 341         if (intel_crtc->bpp > 24)
 342                 sdvox |= COLOR_FORMAT_12bpc;
 343         else
 344                 sdvox |= COLOR_FORMAT_8bpc;
 345
 346         /* Required on CPT */
 347         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
 348                 sdvox |= HDMI_MODE_SELECT;
 349
 350         if (intel_hdmi->has_audio) {
 351                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 352                                  pipe_name(intel_crtc->pipe));
 353                 sdvox |= SDVO_AUDIO_ENABLE;
 354                 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
 355                 intel_write_eld(encoder, adjusted_mode);
 356         }
 357
 358         if (HAS_PCH_CPT(dev))
 359                 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
 360         else if (intel_crtc->pipe == 1)
 361                 sdvox |= SDVO_PIPE_B_SELECT;
 362
 363         I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
 364         POSTING_READ(intel_hdmi->sdvox_reg);
 365
 366         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 367         intel_hdmi_set_spd_infoframe(encoder);
 368 }
 369
 370 static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
 371 {
 372         struct drm_device *dev = encoder->dev;
 373         struct drm_i915_private *dev_priv = dev->dev_private;
 374         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 375         u32 temp;
 376         u32 enable_bits = SDVO_ENABLE;
 377
 378         if (intel_hdmi->has_audio)
 379                 enable_bits |= SDVO_AUDIO_ENABLE;
 380
 381         temp = I915_READ(intel_hdmi->sdvox_reg);
 382
 383         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 384          * we do this anyway which shows more stable in testing.
 385          */
 386         if (HAS_PCH_SPLIT(dev)) {
 387                 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
 388                 POSTING_READ(intel_hdmi->sdvox_reg);
 389         }
 390
 391         if (mode != DRM_MODE_DPMS_ON) {
 392                 temp &= ~enable_bits;
 393         } else {
 394                 temp |= enable_bits;
 395         }
 396
 397         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 398         POSTING_READ(intel_hdmi->sdvox_reg);
 399
 400         /* HW workaround, need to write this twice for issue that may result
 401          * in first write getting masked.
 402          */
 403         if (HAS_PCH_SPLIT(dev)) {
 404                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
 405                 POSTING_READ(intel_hdmi->sdvox_reg);
 406         }
 407 }
 408
 409 static int intel_hdmi_mode_valid(struct drm_connector *connector,
 410                                  struct drm_display_mode *mode)
 411 {
 412         if (mode->clock > 165000)
 413                 return MODE_CLOCK_HIGH;
 414         if (mode->clock < 20000)
 415                 return MODE_CLOCK_LOW;
 416
 417         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 418                 return MODE_NO_DBLESCAN;
 419
 420         return MODE_OK;
 421 }
 422
 423 static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
 424                                   struct drm_display_mode *mode,
 425                                   struct drm_display_mode *adjusted_mode)
 426 {
 427         return true;
 428 }
 429
 430 static enum drm_connector_status
 431 intel_hdmi_detect(struct drm_connector *connector, bool force)
 432 {
 433         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 434         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 435         struct edid *edid;
 436         enum drm_connector_status status = connector_status_disconnected;
 437
 438         intel_hdmi->has_hdmi_sink = false;
 439         intel_hdmi->has_audio = false;
 440         edid = drm_get_edid(connector,
 441                             intel_gmbus_get_adapter(dev_priv,
 442                                                     intel_hdmi->ddc_bus));
 443
 444         if (edid) {
 445                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 446                         status = connector_status_connected;
 447                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
 448                                 intel_hdmi->has_hdmi_sink =
 449                                                 drm_detect_hdmi_monitor(edid);
 450                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 451                 }
 452                 connector->display_info.raw_edid = NULL;
 453                 kfree(edid);
 454         }
 455
 456         if (status == connector_status_connected) {
 457                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
 458                         intel_hdmi->has_audio =
 459                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
 460         }
 461
 462         return status;
 463 }
 464
 465 static int intel_hdmi_get_modes(struct drm_connector *connector)
 466 {
 467         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 468         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 469
 470         /* We should parse the EDID data and find out if it's an HDMI sink so
 471          * we can send audio to it.
 472          */
 473
 474         return intel_ddc_get_modes(connector,
 475                                    intel_gmbus_get_adapter(dev_priv,
 476                                                            intel_hdmi->ddc_bus));
 477 }
 478
 479 static bool
 480 intel_hdmi_detect_audio(struct drm_connector *connector)
 481 {
 482         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 483         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 484         struct edid *edid;
 485         bool has_audio = false;
 486
 487         edid = drm_get_edid(connector,
 488                             intel_gmbus_get_adapter(dev_priv,
 489                                                     intel_hdmi->ddc_bus));
 490         if (edid) {
 491                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
 492                         has_audio = drm_detect_monitor_audio(edid);
 493
 494                 connector->display_info.raw_edid = NULL;
 495                 kfree(edid);
 496         }
 497
 498         return has_audio;
 499 }
 500
 501 static int
 502 intel_hdmi_set_property(struct drm_connector *connector,
 503                       struct drm_property *property,
 504                       uint64_t val)
 505 {
 506         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 507         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 508         int ret;
 509
 510         ret = drm_connector_property_set_value(connector, property, val);
 511         if (ret)
 512                 return ret;
 513
 514         if (property == dev_priv->force_audio_property) {
 515                 enum hdmi_force_audio i = val;
 516                 bool has_audio;
 517
 518                 if (i == intel_hdmi->force_audio)
 519                         return 0;
 520
 521                 intel_hdmi->force_audio = i;
 522
 523                 if (i == HDMI_AUDIO_AUTO)
 524                         has_audio = intel_hdmi_detect_audio(connector);
 525                 else
 526                         has_audio = (i == HDMI_AUDIO_ON);
 527
 528                 if (i == HDMI_AUDIO_OFF_DVI)
 529                         intel_hdmi->has_hdmi_sink = 0;
 530
 531                 intel_hdmi->has_audio = has_audio;
 532                 goto done;
 533         }
 534
 535         if (property == dev_priv->broadcast_rgb_property) {
 536                 if (val == !!intel_hdmi->color_range)
 537                         return 0;
 538
 539                 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
 540                 goto done;
 541         }
 542
 543         return -EINVAL;
 544
 545 done:
 546         if (intel_hdmi->base.base.crtc) {
 547                 struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
 548                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
 549                                          crtc->x, crtc->y,
 550                                          crtc->fb);
 551         }
 552
 553         return 0;
 554 }
 555
 556 static void intel_hdmi_destroy(struct drm_connector *connector)
 557 {
 558         drm_sysfs_connector_remove(connector);
 559         drm_connector_cleanup(connector);
 560         kfree(connector);
 561 }
 562
 563 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
 564         .dpms = intel_hdmi_dpms,
 565         .mode_fixup = intel_hdmi_mode_fixup,
 566         .prepare = intel_encoder_prepare,
 567         .mode_set = intel_hdmi_mode_set,
 568         .commit = intel_encoder_commit,
 569 };
 570
 571 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
 572         .dpms = drm_helper_connector_dpms,
 573         .detect = intel_hdmi_detect,
 574         .fill_modes = drm_helper_probe_single_connector_modes,
 575         .set_property = intel_hdmi_set_property,
 576         .destroy = intel_hdmi_destroy,
 577 };
 578
 579 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
 580         .get_modes = intel_hdmi_get_modes,
 581         .mode_valid = intel_hdmi_mode_valid,
 582         .best_encoder = intel_best_encoder,
 583 };
 584
 585 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
 586         .destroy = intel_encoder_destroy,
 587 };
 588
 589 static void
 590 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
 591 {
 592         intel_attach_force_audio_property(connector);
 593         intel_attach_broadcast_rgb_property(connector);
 594 }
 595
 596 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
 597 {
 598         struct drm_i915_private *dev_priv = dev->dev_private;
 599         struct drm_connector *connector;
 600         struct intel_encoder *intel_encoder;
 601         struct intel_connector *intel_connector;
 602         struct intel_hdmi *intel_hdmi;
 603         int i;
 604
 605         intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
 606         if (!intel_hdmi)
 607                 return;
 608
 609         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
 610         if (!intel_connector) {
 611                 kfree(intel_hdmi);
 612                 return;
 613         }
 614
 615         intel_encoder = &intel_hdmi->base;
 616         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
 617                          DRM_MODE_ENCODER_TMDS);
 618
 619         connector = &intel_connector->base;
 620         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
 621                            DRM_MODE_CONNECTOR_HDMIA);
 622         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
 623
 624         intel_encoder->type = INTEL_OUTPUT_HDMI;
 625
 626         connector->polled = DRM_CONNECTOR_POLL_HPD;
 627         connector->interlace_allowed = 1;
 628         connector->doublescan_allowed = 0;
 629         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 630
 631         /* Set up the DDC bus. */
 632         if (sdvox_reg == SDVOB) {
 633                 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
 634                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 635                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 636         } else if (sdvox_reg == SDVOC) {
 637                 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
 638                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 639                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 640         } else if (sdvox_reg == HDMIB) {
 641                 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
 642                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 643                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 644         } else if (sdvox_reg == HDMIC) {
 645                 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
 646                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 647                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 648         } else if (sdvox_reg == HDMID) {
 649                 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
 650                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
 651                 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
 652         }
 653
 654         intel_hdmi->sdvox_reg = sdvox_reg;
 655
 656         if (!HAS_PCH_SPLIT(dev)) {
 657                 intel_hdmi->write_infoframe = i9xx_write_infoframe;
 658                 I915_WRITE(VIDEO_DIP_CTL, 0);
 659         } else if (IS_VALLEYVIEW(dev)) {
 660                 intel_hdmi->write_infoframe = vlv_write_infoframe;
 661                 for_each_pipe(i)
 662                         I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
 663         } else if (HAS_PCH_IBX(dev)) {
 664                 intel_hdmi->write_infoframe = ibx_write_infoframe;
 665                 for_each_pipe(i)
 666                         I915_WRITE(TVIDEO_DIP_CTL(i), 0);
 667         } else {
 668                 intel_hdmi->write_infoframe = cpt_write_infoframe;
 669                 for_each_pipe(i)
 670                         I915_WRITE(TVIDEO_DIP_CTL(i), 0);
 671         }
 672
 673         drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
 674
 675         intel_hdmi_add_properties(intel_hdmi, connector);
 676
 677         intel_connector_attach_encoder(intel_connector, intel_encoder);
 678         drm_sysfs_connector_add(connector);
 679
 680         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
 681          * 0xd.  Failure to do so will result in spurious interrupts being
 682          * generated on the port when a cable is not attached.
 683          */
 684         if (IS_G4X(dev) && !IS_GM45(dev)) {
 685                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
 686                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
 687         }
 688 }