2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
36 #include "intel_drv.h"
41 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
43 struct drm_device *dev = intel_hdmi->base.base.dev;
44 struct drm_i915_private *dev_priv = dev->dev_private;
45 uint32_t enabled_bits;
47 enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
49 WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,
50 "HDMI port enabled, expecting disabled\n");
53 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
55 return container_of(encoder, struct intel_hdmi, base.base);
58 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
60 return container_of(intel_attached_encoder(connector),
61 struct intel_hdmi, base);
64 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
66 uint8_t *data = (uint8_t *)frame;
73 for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
76 frame->checksum = 0x100 - sum;
79 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
81 switch (frame->type) {
83 return VIDEO_DIP_SELECT_AVI;
85 return VIDEO_DIP_SELECT_SPD;
87 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
92 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
94 switch (frame->type) {
96 return VIDEO_DIP_ENABLE_AVI;
98 return VIDEO_DIP_ENABLE_SPD;
100 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
105 static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
107 switch (frame->type) {
109 return VIDEO_DIP_ENABLE_AVI_HSW;
111 return VIDEO_DIP_ENABLE_SPD_HSW;
113 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
118 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
120 switch (frame->type) {
122 return HSW_TVIDEO_DIP_AVI_DATA(pipe);
124 return HSW_TVIDEO_DIP_SPD_DATA(pipe);
126 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
131 static void g4x_write_infoframe(struct drm_encoder *encoder,
132 struct dip_infoframe *frame)
134 uint32_t *data = (uint32_t *)frame;
135 struct drm_device *dev = encoder->dev;
136 struct drm_i915_private *dev_priv = dev->dev_private;
137 u32 val = I915_READ(VIDEO_DIP_CTL);
138 unsigned i, len = DIP_HEADER_SIZE + frame->len;
140 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
142 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
143 val |= g4x_infoframe_index(frame);
145 val &= ~g4x_infoframe_enable(frame);
147 I915_WRITE(VIDEO_DIP_CTL, val);
150 for (i = 0; i < len; i += 4) {
151 I915_WRITE(VIDEO_DIP_DATA, *data);
156 val |= g4x_infoframe_enable(frame);
157 val &= ~VIDEO_DIP_FREQ_MASK;
158 val |= VIDEO_DIP_FREQ_VSYNC;
160 I915_WRITE(VIDEO_DIP_CTL, val);
161 POSTING_READ(VIDEO_DIP_CTL);
164 static void ibx_write_infoframe(struct drm_encoder *encoder,
165 struct dip_infoframe *frame)
167 uint32_t *data = (uint32_t *)frame;
168 struct drm_device *dev = encoder->dev;
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
171 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
172 unsigned i, len = DIP_HEADER_SIZE + frame->len;
173 u32 val = I915_READ(reg);
175 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
177 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
178 val |= g4x_infoframe_index(frame);
180 val &= ~g4x_infoframe_enable(frame);
182 I915_WRITE(reg, val);
185 for (i = 0; i < len; i += 4) {
186 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
191 val |= g4x_infoframe_enable(frame);
192 val &= ~VIDEO_DIP_FREQ_MASK;
193 val |= VIDEO_DIP_FREQ_VSYNC;
195 I915_WRITE(reg, val);
199 static void cpt_write_infoframe(struct drm_encoder *encoder,
200 struct dip_infoframe *frame)
202 uint32_t *data = (uint32_t *)frame;
203 struct drm_device *dev = encoder->dev;
204 struct drm_i915_private *dev_priv = dev->dev_private;
205 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
206 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
207 unsigned i, len = DIP_HEADER_SIZE + frame->len;
208 u32 val = I915_READ(reg);
210 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
212 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
213 val |= g4x_infoframe_index(frame);
215 /* The DIP control register spec says that we need to update the AVI
216 * infoframe without clearing its enable bit */
217 if (frame->type != DIP_TYPE_AVI)
218 val &= ~g4x_infoframe_enable(frame);
220 I915_WRITE(reg, val);
223 for (i = 0; i < len; i += 4) {
224 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
229 val |= g4x_infoframe_enable(frame);
230 val &= ~VIDEO_DIP_FREQ_MASK;
231 val |= VIDEO_DIP_FREQ_VSYNC;
233 I915_WRITE(reg, val);
237 static void vlv_write_infoframe(struct drm_encoder *encoder,
238 struct dip_infoframe *frame)
240 uint32_t *data = (uint32_t *)frame;
241 struct drm_device *dev = encoder->dev;
242 struct drm_i915_private *dev_priv = dev->dev_private;
243 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
244 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
245 unsigned i, len = DIP_HEADER_SIZE + frame->len;
246 u32 val = I915_READ(reg);
248 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
250 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
251 val |= g4x_infoframe_index(frame);
253 val &= ~g4x_infoframe_enable(frame);
255 I915_WRITE(reg, val);
258 for (i = 0; i < len; i += 4) {
259 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
264 val |= g4x_infoframe_enable(frame);
265 val &= ~VIDEO_DIP_FREQ_MASK;
266 val |= VIDEO_DIP_FREQ_VSYNC;
268 I915_WRITE(reg, val);
272 static void hsw_write_infoframe(struct drm_encoder *encoder,
273 struct dip_infoframe *frame)
275 uint32_t *data = (uint32_t *)frame;
276 struct drm_device *dev = encoder->dev;
277 struct drm_i915_private *dev_priv = dev->dev_private;
278 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
279 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
280 u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
281 unsigned int i, len = DIP_HEADER_SIZE + frame->len;
282 u32 val = I915_READ(ctl_reg);
287 val &= ~hsw_infoframe_enable(frame);
288 I915_WRITE(ctl_reg, val);
291 for (i = 0; i < len; i += 4) {
292 I915_WRITE(data_reg + i, *data);
297 val |= hsw_infoframe_enable(frame);
298 I915_WRITE(ctl_reg, val);
299 POSTING_READ(ctl_reg);
302 static void intel_set_infoframe(struct drm_encoder *encoder,
303 struct dip_infoframe *frame)
305 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
307 intel_dip_infoframe_csum(frame);
308 intel_hdmi->write_infoframe(encoder, frame);
311 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
312 struct drm_display_mode *adjusted_mode)
314 struct dip_infoframe avi_if = {
315 .type = DIP_TYPE_AVI,
316 .ver = DIP_VERSION_AVI,
320 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
321 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
323 intel_set_infoframe(encoder, &avi_if);
326 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
328 struct dip_infoframe spd_if;
330 memset(&spd_if, 0, sizeof(spd_if));
331 spd_if.type = DIP_TYPE_SPD;
332 spd_if.ver = DIP_VERSION_SPD;
333 spd_if.len = DIP_LEN_SPD;
334 strcpy(spd_if.body.spd.vn, "Intel");
335 strcpy(spd_if.body.spd.pd, "Integrated gfx");
336 spd_if.body.spd.sdi = DIP_SPD_PC;
338 intel_set_infoframe(encoder, &spd_if);
341 static void g4x_set_infoframes(struct drm_encoder *encoder,
342 struct drm_display_mode *adjusted_mode)
344 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
345 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
346 u32 reg = VIDEO_DIP_CTL;
347 u32 val = I915_READ(reg);
350 assert_hdmi_port_disabled(intel_hdmi);
352 /* If the registers were not initialized yet, they might be zeroes,
353 * which means we're selecting the AVI DIP and we're setting its
354 * frequency to once. This seems to really confuse the HW and make
355 * things stop working (the register spec says the AVI always needs to
356 * be sent every VSync). So here we avoid writing to the register more
357 * than we need and also explicitly select the AVI DIP and explicitly
358 * set its frequency to every VSync. Avoiding to write it twice seems to
359 * be enough to solve the problem, but being defensive shouldn't hurt us
361 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
363 if (!intel_hdmi->has_hdmi_sink) {
364 if (!(val & VIDEO_DIP_ENABLE))
366 val &= ~VIDEO_DIP_ENABLE;
367 I915_WRITE(reg, val);
372 switch (intel_hdmi->sdvox_reg) {
374 port = VIDEO_DIP_PORT_B;
377 port = VIDEO_DIP_PORT_C;
383 if (port != (val & VIDEO_DIP_PORT_MASK)) {
384 if (val & VIDEO_DIP_ENABLE) {
385 val &= ~VIDEO_DIP_ENABLE;
386 I915_WRITE(reg, val);
389 val &= ~VIDEO_DIP_PORT_MASK;
393 val |= VIDEO_DIP_ENABLE;
394 val &= ~VIDEO_DIP_ENABLE_VENDOR;
396 I915_WRITE(reg, val);
399 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
400 intel_hdmi_set_spd_infoframe(encoder);
403 static void ibx_set_infoframes(struct drm_encoder *encoder,
404 struct drm_display_mode *adjusted_mode)
406 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
407 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
408 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
409 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
410 u32 val = I915_READ(reg);
413 assert_hdmi_port_disabled(intel_hdmi);
415 /* See the big comment in g4x_set_infoframes() */
416 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
418 if (!intel_hdmi->has_hdmi_sink) {
419 if (!(val & VIDEO_DIP_ENABLE))
421 val &= ~VIDEO_DIP_ENABLE;
422 I915_WRITE(reg, val);
427 switch (intel_hdmi->sdvox_reg) {
429 port = VIDEO_DIP_PORT_B;
432 port = VIDEO_DIP_PORT_C;
435 port = VIDEO_DIP_PORT_D;
441 if (port != (val & VIDEO_DIP_PORT_MASK)) {
442 if (val & VIDEO_DIP_ENABLE) {
443 val &= ~VIDEO_DIP_ENABLE;
444 I915_WRITE(reg, val);
447 val &= ~VIDEO_DIP_PORT_MASK;
451 val |= VIDEO_DIP_ENABLE;
452 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
453 VIDEO_DIP_ENABLE_GCP);
455 I915_WRITE(reg, val);
458 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
459 intel_hdmi_set_spd_infoframe(encoder);
462 static void cpt_set_infoframes(struct drm_encoder *encoder,
463 struct drm_display_mode *adjusted_mode)
465 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
466 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
467 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
468 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
469 u32 val = I915_READ(reg);
471 assert_hdmi_port_disabled(intel_hdmi);
473 /* See the big comment in g4x_set_infoframes() */
474 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
476 if (!intel_hdmi->has_hdmi_sink) {
477 if (!(val & VIDEO_DIP_ENABLE))
479 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
480 I915_WRITE(reg, val);
485 /* Set both together, unset both together: see the spec. */
486 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
487 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
488 VIDEO_DIP_ENABLE_GCP);
490 I915_WRITE(reg, val);
493 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
494 intel_hdmi_set_spd_infoframe(encoder);
497 static void vlv_set_infoframes(struct drm_encoder *encoder,
498 struct drm_display_mode *adjusted_mode)
500 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
501 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
502 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
503 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
504 u32 val = I915_READ(reg);
506 assert_hdmi_port_disabled(intel_hdmi);
508 /* See the big comment in g4x_set_infoframes() */
509 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
511 if (!intel_hdmi->has_hdmi_sink) {
512 if (!(val & VIDEO_DIP_ENABLE))
514 val &= ~VIDEO_DIP_ENABLE;
515 I915_WRITE(reg, val);
520 val |= VIDEO_DIP_ENABLE;
521 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
522 VIDEO_DIP_ENABLE_GCP);
524 I915_WRITE(reg, val);
527 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
528 intel_hdmi_set_spd_infoframe(encoder);
531 static void hsw_set_infoframes(struct drm_encoder *encoder,
532 struct drm_display_mode *adjusted_mode)
534 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
535 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
536 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
537 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
538 u32 val = I915_READ(reg);
540 assert_hdmi_port_disabled(intel_hdmi);
542 if (!intel_hdmi->has_hdmi_sink) {
548 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
549 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
551 I915_WRITE(reg, val);
554 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
555 intel_hdmi_set_spd_infoframe(encoder);
558 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
559 struct drm_display_mode *mode,
560 struct drm_display_mode *adjusted_mode)
562 struct drm_device *dev = encoder->dev;
563 struct drm_i915_private *dev_priv = dev->dev_private;
564 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
565 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
568 sdvox = SDVO_ENCODING_HDMI;
569 if (!HAS_PCH_SPLIT(dev))
570 sdvox |= intel_hdmi->color_range;
571 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
572 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
573 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
574 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
576 if (intel_crtc->bpp > 24)
577 sdvox |= COLOR_FORMAT_12bpc;
579 sdvox |= COLOR_FORMAT_8bpc;
581 /* Required on CPT */
582 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
583 sdvox |= HDMI_MODE_SELECT;
585 if (intel_hdmi->has_audio) {
586 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
587 pipe_name(intel_crtc->pipe));
588 sdvox |= SDVO_AUDIO_ENABLE;
589 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
590 intel_write_eld(encoder, adjusted_mode);
593 if (HAS_PCH_CPT(dev))
594 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
595 else if (intel_crtc->pipe == PIPE_B)
596 sdvox |= SDVO_PIPE_B_SELECT;
598 I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
599 POSTING_READ(intel_hdmi->sdvox_reg);
601 intel_hdmi->set_infoframes(encoder, adjusted_mode);
604 static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
606 struct drm_device *dev = encoder->dev;
607 struct drm_i915_private *dev_priv = dev->dev_private;
608 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
610 u32 enable_bits = SDVO_ENABLE;
612 if (intel_hdmi->has_audio)
613 enable_bits |= SDVO_AUDIO_ENABLE;
615 temp = I915_READ(intel_hdmi->sdvox_reg);
617 /* HW workaround for IBX, we need to move the port to transcoder A
618 * before disabling it. */
619 if (HAS_PCH_IBX(dev)) {
620 struct drm_crtc *crtc = encoder->crtc;
621 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
623 if (mode != DRM_MODE_DPMS_ON) {
624 if (temp & SDVO_PIPE_B_SELECT) {
625 temp &= ~SDVO_PIPE_B_SELECT;
626 I915_WRITE(intel_hdmi->sdvox_reg, temp);
627 POSTING_READ(intel_hdmi->sdvox_reg);
629 /* Again we need to write this twice. */
630 I915_WRITE(intel_hdmi->sdvox_reg, temp);
631 POSTING_READ(intel_hdmi->sdvox_reg);
633 /* Transcoder selection bits only update
634 * effectively on vblank. */
636 intel_wait_for_vblank(dev, pipe);
641 /* Restore the transcoder select bit. */
643 enable_bits |= SDVO_PIPE_B_SELECT;
647 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
648 * we do this anyway which shows more stable in testing.
650 if (HAS_PCH_SPLIT(dev)) {
651 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
652 POSTING_READ(intel_hdmi->sdvox_reg);
655 if (mode != DRM_MODE_DPMS_ON) {
656 temp &= ~enable_bits;
661 I915_WRITE(intel_hdmi->sdvox_reg, temp);
662 POSTING_READ(intel_hdmi->sdvox_reg);
664 /* HW workaround, need to write this twice for issue that may result
665 * in first write getting masked.
667 if (HAS_PCH_SPLIT(dev)) {
668 I915_WRITE(intel_hdmi->sdvox_reg, temp);
669 POSTING_READ(intel_hdmi->sdvox_reg);
673 static int intel_hdmi_mode_valid(struct drm_connector *connector,
674 struct drm_display_mode *mode)
676 if (mode->clock > 165000)
677 return MODE_CLOCK_HIGH;
678 if (mode->clock < 20000)
679 return MODE_CLOCK_LOW;
681 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
682 return MODE_NO_DBLESCAN;
687 static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
688 const struct drm_display_mode *mode,
689 struct drm_display_mode *adjusted_mode)
694 static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
696 struct drm_device *dev = intel_hdmi->base.base.dev;
697 struct drm_i915_private *dev_priv = dev->dev_private;
700 switch (intel_hdmi->sdvox_reg) {
702 bit = HDMIB_HOTPLUG_LIVE_STATUS;
705 bit = HDMIC_HOTPLUG_LIVE_STATUS;
712 return I915_READ(PORT_HOTPLUG_STAT) & bit;
715 static enum drm_connector_status
716 intel_hdmi_detect(struct drm_connector *connector, bool force)
718 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
719 struct drm_i915_private *dev_priv = connector->dev->dev_private;
721 enum drm_connector_status status = connector_status_disconnected;
723 if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
726 intel_hdmi->has_hdmi_sink = false;
727 intel_hdmi->has_audio = false;
728 edid = drm_get_edid(connector,
729 intel_gmbus_get_adapter(dev_priv,
730 intel_hdmi->ddc_bus));
733 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
734 status = connector_status_connected;
735 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
736 intel_hdmi->has_hdmi_sink =
737 drm_detect_hdmi_monitor(edid);
738 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
740 connector->display_info.raw_edid = NULL;
744 if (status == connector_status_connected) {
745 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
746 intel_hdmi->has_audio =
747 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
753 static int intel_hdmi_get_modes(struct drm_connector *connector)
755 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
756 struct drm_i915_private *dev_priv = connector->dev->dev_private;
758 /* We should parse the EDID data and find out if it's an HDMI sink so
759 * we can send audio to it.
762 return intel_ddc_get_modes(connector,
763 intel_gmbus_get_adapter(dev_priv,
764 intel_hdmi->ddc_bus));
768 intel_hdmi_detect_audio(struct drm_connector *connector)
770 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
771 struct drm_i915_private *dev_priv = connector->dev->dev_private;
773 bool has_audio = false;
775 edid = drm_get_edid(connector,
776 intel_gmbus_get_adapter(dev_priv,
777 intel_hdmi->ddc_bus));
779 if (edid->input & DRM_EDID_INPUT_DIGITAL)
780 has_audio = drm_detect_monitor_audio(edid);
782 connector->display_info.raw_edid = NULL;
790 intel_hdmi_set_property(struct drm_connector *connector,
791 struct drm_property *property,
794 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
795 struct drm_i915_private *dev_priv = connector->dev->dev_private;
798 ret = drm_connector_property_set_value(connector, property, val);
802 if (property == dev_priv->force_audio_property) {
803 enum hdmi_force_audio i = val;
806 if (i == intel_hdmi->force_audio)
809 intel_hdmi->force_audio = i;
811 if (i == HDMI_AUDIO_AUTO)
812 has_audio = intel_hdmi_detect_audio(connector);
814 has_audio = (i == HDMI_AUDIO_ON);
816 if (i == HDMI_AUDIO_OFF_DVI)
817 intel_hdmi->has_hdmi_sink = 0;
819 intel_hdmi->has_audio = has_audio;
823 if (property == dev_priv->broadcast_rgb_property) {
824 if (val == !!intel_hdmi->color_range)
827 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
834 if (intel_hdmi->base.base.crtc) {
835 struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
836 drm_crtc_helper_set_mode(crtc, &crtc->mode,
844 static void intel_hdmi_destroy(struct drm_connector *connector)
846 drm_sysfs_connector_remove(connector);
847 drm_connector_cleanup(connector);
851 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
852 .dpms = intel_ddi_dpms,
853 .mode_fixup = intel_hdmi_mode_fixup,
854 .prepare = intel_encoder_prepare,
855 .mode_set = intel_ddi_mode_set,
856 .commit = intel_encoder_commit,
859 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
860 .dpms = intel_hdmi_dpms,
861 .mode_fixup = intel_hdmi_mode_fixup,
862 .prepare = intel_encoder_prepare,
863 .mode_set = intel_hdmi_mode_set,
864 .commit = intel_encoder_commit,
867 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
868 .dpms = drm_helper_connector_dpms,
869 .detect = intel_hdmi_detect,
870 .fill_modes = drm_helper_probe_single_connector_modes,
871 .set_property = intel_hdmi_set_property,
872 .destroy = intel_hdmi_destroy,
875 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
876 .get_modes = intel_hdmi_get_modes,
877 .mode_valid = intel_hdmi_mode_valid,
878 .best_encoder = intel_best_encoder,
881 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
882 .destroy = intel_encoder_destroy,
886 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
888 intel_attach_force_audio_property(connector);
889 intel_attach_broadcast_rgb_property(connector);
892 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
894 struct drm_i915_private *dev_priv = dev->dev_private;
895 struct drm_connector *connector;
896 struct intel_encoder *intel_encoder;
897 struct intel_connector *intel_connector;
898 struct intel_hdmi *intel_hdmi;
900 intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
904 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
905 if (!intel_connector) {
910 intel_encoder = &intel_hdmi->base;
911 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
912 DRM_MODE_ENCODER_TMDS);
914 connector = &intel_connector->base;
915 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
916 DRM_MODE_CONNECTOR_HDMIA);
917 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
919 intel_encoder->type = INTEL_OUTPUT_HDMI;
921 connector->polled = DRM_CONNECTOR_POLL_HPD;
922 connector->interlace_allowed = 1;
923 connector->doublescan_allowed = 0;
924 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
926 /* Set up the DDC bus. */
927 if (sdvox_reg == SDVOB) {
928 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
929 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
930 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
931 } else if (sdvox_reg == SDVOC) {
932 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
933 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
934 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
935 } else if (sdvox_reg == HDMIB) {
936 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
937 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
938 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
939 } else if (sdvox_reg == HDMIC) {
940 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
941 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
942 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
943 } else if (sdvox_reg == HDMID) {
944 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
945 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
946 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
947 } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) {
948 DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n");
949 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
950 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
951 intel_hdmi->ddi_port = PORT_B;
952 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
953 } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) {
954 DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n");
955 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
956 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
957 intel_hdmi->ddi_port = PORT_C;
958 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
959 } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) {
960 DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n");
961 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
962 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
963 intel_hdmi->ddi_port = PORT_D;
964 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
966 /* If we got an unknown sdvox_reg, things are pretty much broken
967 * in a way that we should let the kernel know about it */
971 intel_hdmi->sdvox_reg = sdvox_reg;
973 if (!HAS_PCH_SPLIT(dev)) {
974 intel_hdmi->write_infoframe = g4x_write_infoframe;
975 intel_hdmi->set_infoframes = g4x_set_infoframes;
976 } else if (IS_VALLEYVIEW(dev)) {
977 intel_hdmi->write_infoframe = vlv_write_infoframe;
978 intel_hdmi->set_infoframes = vlv_set_infoframes;
979 } else if (IS_HASWELL(dev)) {
980 intel_hdmi->write_infoframe = hsw_write_infoframe;
981 intel_hdmi->set_infoframes = hsw_set_infoframes;
982 } else if (HAS_PCH_IBX(dev)) {
983 intel_hdmi->write_infoframe = ibx_write_infoframe;
984 intel_hdmi->set_infoframes = ibx_set_infoframes;
986 intel_hdmi->write_infoframe = cpt_write_infoframe;
987 intel_hdmi->set_infoframes = cpt_set_infoframes;
991 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw);
993 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
995 intel_hdmi_add_properties(intel_hdmi, connector);
997 intel_connector_attach_encoder(intel_connector, intel_encoder);
998 drm_sysfs_connector_add(connector);
1000 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1001 * 0xd. Failure to do so will result in spurious interrupts being
1002 * generated on the port when a cable is not attached.
1004 if (IS_G4X(dev) && !IS_GM45(dev)) {
1005 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1006 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);