drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40
  41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  42 {
  43         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  44 }
  45
  46 static void
  47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  48 {
  49         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  50         struct drm_i915_private *dev_priv = dev->dev_private;
  51         uint32_t enabled_bits;
  52
  53         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  54
  55         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  56              "HDMI port enabled, expecting disabled\n");
  57 }
  58
  59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  60 {
  61         struct intel_digital_port *intel_dig_port =
  62                 container_of(encoder, struct intel_digital_port, base.base);
  63         return &intel_dig_port->hdmi;
  64 }
  65
  66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  67 {
  68         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  69 }
  70
  71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  72 {
  73         switch (type) {
  74         case HDMI_INFOFRAME_TYPE_AVI:
  75                 return VIDEO_DIP_SELECT_AVI;
  76         case HDMI_INFOFRAME_TYPE_SPD:
  77                 return VIDEO_DIP_SELECT_SPD;
  78         case HDMI_INFOFRAME_TYPE_VENDOR:
  79                 return VIDEO_DIP_SELECT_VENDOR;
  80         default:
  81                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  82                 return 0;
  83         }
  84 }
  85
  86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  87 {
  88         switch (type) {
  89         case HDMI_INFOFRAME_TYPE_AVI:
  90                 return VIDEO_DIP_ENABLE_AVI;
  91         case HDMI_INFOFRAME_TYPE_SPD:
  92                 return VIDEO_DIP_ENABLE_SPD;
  93         case HDMI_INFOFRAME_TYPE_VENDOR:
  94                 return VIDEO_DIP_ENABLE_VENDOR;
  95         default:
  96                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  97                 return 0;
  98         }
  99 }
 100
 101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 102 {
 103         switch (type) {
 104         case HDMI_INFOFRAME_TYPE_AVI:
 105                 return VIDEO_DIP_ENABLE_AVI_HSW;
 106         case HDMI_INFOFRAME_TYPE_SPD:
 107                 return VIDEO_DIP_ENABLE_SPD_HSW;
 108         case HDMI_INFOFRAME_TYPE_VENDOR:
 109                 return VIDEO_DIP_ENABLE_VS_HSW;
 110         default:
 111                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 112                 return 0;
 113         }
 114 }
 115
 116 static i915_reg_t
 117 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 118                  enum transcoder cpu_transcoder,
 119                  enum hdmi_infoframe_type type,
 120                  int i)
 121 {
 122         switch (type) {
 123         case HDMI_INFOFRAME_TYPE_AVI:
 124                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 125         case HDMI_INFOFRAME_TYPE_SPD:
 126                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 127         case HDMI_INFOFRAME_TYPE_VENDOR:
 128                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 129         default:
 130                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 131                 return INVALID_MMIO_REG;
 132         }
 133 }
 134
 135 static void g4x_write_infoframe(struct drm_encoder *encoder,
 136                                 enum hdmi_infoframe_type type,
 137                                 const void *frame, ssize_t len)
 138 {
 139         const uint32_t *data = frame;
 140         struct drm_device *dev = encoder->dev;
 141         struct drm_i915_private *dev_priv = dev->dev_private;
 142         u32 val = I915_READ(VIDEO_DIP_CTL);
 143         int i;
 144
 145         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 146
 147         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 148         val |= g4x_infoframe_index(type);
 149
 150         val &= ~g4x_infoframe_enable(type);
 151
 152         I915_WRITE(VIDEO_DIP_CTL, val);
 153
 154         mmiowb();
 155         for (i = 0; i < len; i += 4) {
 156                 I915_WRITE(VIDEO_DIP_DATA, *data);
 157                 data++;
 158         }
 159         /* Write every possible data byte to force correct ECC calculation. */
 160         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 161                 I915_WRITE(VIDEO_DIP_DATA, 0);
 162         mmiowb();
 163
 164         val |= g4x_infoframe_enable(type);
 165         val &= ~VIDEO_DIP_FREQ_MASK;
 166         val |= VIDEO_DIP_FREQ_VSYNC;
 167
 168         I915_WRITE(VIDEO_DIP_CTL, val);
 169         POSTING_READ(VIDEO_DIP_CTL);
 170 }
 171
 172 static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
 173 {
 174         struct drm_device *dev = encoder->dev;
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 177         u32 val = I915_READ(VIDEO_DIP_CTL);
 178
 179         if ((val & VIDEO_DIP_ENABLE) == 0)
 180                 return false;
 181
 182         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 183                 return false;
 184
 185         return val & (VIDEO_DIP_ENABLE_AVI |
 186                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 187 }
 188
 189 static void ibx_write_infoframe(struct drm_encoder *encoder,
 190                                 enum hdmi_infoframe_type type,
 191                                 const void *frame, ssize_t len)
 192 {
 193         const uint32_t *data = frame;
 194         struct drm_device *dev = encoder->dev;
 195         struct drm_i915_private *dev_priv = dev->dev_private;
 196         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 197         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 198         u32 val = I915_READ(reg);
 199         int i;
 200
 201         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 202
 203         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 204         val |= g4x_infoframe_index(type);
 205
 206         val &= ~g4x_infoframe_enable(type);
 207
 208         I915_WRITE(reg, val);
 209
 210         mmiowb();
 211         for (i = 0; i < len; i += 4) {
 212                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 213                 data++;
 214         }
 215         /* Write every possible data byte to force correct ECC calculation. */
 216         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 217                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 218         mmiowb();
 219
 220         val |= g4x_infoframe_enable(type);
 221         val &= ~VIDEO_DIP_FREQ_MASK;
 222         val |= VIDEO_DIP_FREQ_VSYNC;
 223
 224         I915_WRITE(reg, val);
 225         POSTING_READ(reg);
 226 }
 227
 228 static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
 229 {
 230         struct drm_device *dev = encoder->dev;
 231         struct drm_i915_private *dev_priv = dev->dev_private;
 232         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 233         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 234         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 235         u32 val = I915_READ(reg);
 236
 237         if ((val & VIDEO_DIP_ENABLE) == 0)
 238                 return false;
 239
 240         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 241                 return false;
 242
 243         return val & (VIDEO_DIP_ENABLE_AVI |
 244                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 245                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 246 }
 247
 248 static void cpt_write_infoframe(struct drm_encoder *encoder,
 249                                 enum hdmi_infoframe_type type,
 250                                 const void *frame, ssize_t len)
 251 {
 252         const uint32_t *data = frame;
 253         struct drm_device *dev = encoder->dev;
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 256         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 257         u32 val = I915_READ(reg);
 258         int i;
 259
 260         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 261
 262         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 263         val |= g4x_infoframe_index(type);
 264
 265         /* The DIP control register spec says that we need to update the AVI
 266          * infoframe without clearing its enable bit */
 267         if (type != HDMI_INFOFRAME_TYPE_AVI)
 268                 val &= ~g4x_infoframe_enable(type);
 269
 270         I915_WRITE(reg, val);
 271
 272         mmiowb();
 273         for (i = 0; i < len; i += 4) {
 274                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 275                 data++;
 276         }
 277         /* Write every possible data byte to force correct ECC calculation. */
 278         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 279                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 280         mmiowb();
 281
 282         val |= g4x_infoframe_enable(type);
 283         val &= ~VIDEO_DIP_FREQ_MASK;
 284         val |= VIDEO_DIP_FREQ_VSYNC;
 285
 286         I915_WRITE(reg, val);
 287         POSTING_READ(reg);
 288 }
 289
 290 static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
 291 {
 292         struct drm_device *dev = encoder->dev;
 293         struct drm_i915_private *dev_priv = dev->dev_private;
 294         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 295         u32 val = I915_READ(TVIDEO_DIP_CTL(intel_crtc->pipe));
 296
 297         if ((val & VIDEO_DIP_ENABLE) == 0)
 298                 return false;
 299
 300         return val & (VIDEO_DIP_ENABLE_AVI |
 301                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 302                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 303 }
 304
 305 static void vlv_write_infoframe(struct drm_encoder *encoder,
 306                                 enum hdmi_infoframe_type type,
 307                                 const void *frame, ssize_t len)
 308 {
 309         const uint32_t *data = frame;
 310         struct drm_device *dev = encoder->dev;
 311         struct drm_i915_private *dev_priv = dev->dev_private;
 312         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 313         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 314         u32 val = I915_READ(reg);
 315         int i;
 316
 317         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 318
 319         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 320         val |= g4x_infoframe_index(type);
 321
 322         val &= ~g4x_infoframe_enable(type);
 323
 324         I915_WRITE(reg, val);
 325
 326         mmiowb();
 327         for (i = 0; i < len; i += 4) {
 328                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 329                 data++;
 330         }
 331         /* Write every possible data byte to force correct ECC calculation. */
 332         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 333                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 334         mmiowb();
 335
 336         val |= g4x_infoframe_enable(type);
 337         val &= ~VIDEO_DIP_FREQ_MASK;
 338         val |= VIDEO_DIP_FREQ_VSYNC;
 339
 340         I915_WRITE(reg, val);
 341         POSTING_READ(reg);
 342 }
 343
 344 static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
 345 {
 346         struct drm_device *dev = encoder->dev;
 347         struct drm_i915_private *dev_priv = dev->dev_private;
 348         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 349         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 350         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(intel_crtc->pipe));
 351
 352         if ((val & VIDEO_DIP_ENABLE) == 0)
 353                 return false;
 354
 355         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 356                 return false;
 357
 358         return val & (VIDEO_DIP_ENABLE_AVI |
 359                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 360                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 361 }
 362
 363 static void hsw_write_infoframe(struct drm_encoder *encoder,
 364                                 enum hdmi_infoframe_type type,
 365                                 const void *frame, ssize_t len)
 366 {
 367         const uint32_t *data = frame;
 368         struct drm_device *dev = encoder->dev;
 369         struct drm_i915_private *dev_priv = dev->dev_private;
 370         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 371         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
 372         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 373         i915_reg_t data_reg;
 374         int i;
 375         u32 val = I915_READ(ctl_reg);
 376
 377         data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
 378         if (i915_mmio_reg_valid(data_reg))
 379                 return;
 380
 381         val &= ~hsw_infoframe_enable(type);
 382         I915_WRITE(ctl_reg, val);
 383
 384         mmiowb();
 385         for (i = 0; i < len; i += 4) {
 386                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 387                                             type, i >> 2), *data);
 388                 data++;
 389         }
 390         /* Write every possible data byte to force correct ECC calculation. */
 391         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 392                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 393                                             type, i >> 2), 0);
 394         mmiowb();
 395
 396         val |= hsw_infoframe_enable(type);
 397         I915_WRITE(ctl_reg, val);
 398         POSTING_READ(ctl_reg);
 399 }
 400
 401 static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
 402 {
 403         struct drm_device *dev = encoder->dev;
 404         struct drm_i915_private *dev_priv = dev->dev_private;
 405         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 406         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder));
 407
 408         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 409                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 410                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 411 }
 412
 413 /*
 414  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 415  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 416  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 417  * used for both technologies.
 418  *
 419  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 420  * DW1:       DB3       | DB2 | DB1 | DB0
 421  * DW2:       DB7       | DB6 | DB5 | DB4
 422  * DW3: ...
 423  *
 424  * (HB is Header Byte, DB is Data Byte)
 425  *
 426  * The hdmi pack() functions don't know about that hardware specific hole so we
 427  * trick them by giving an offset into the buffer and moving back the header
 428  * bytes by one.
 429  */
 430 static void intel_write_infoframe(struct drm_encoder *encoder,
 431                                   union hdmi_infoframe *frame)
 432 {
 433         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 434         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 435         ssize_t len;
 436
 437         /* see comment above for the reason for this offset */
 438         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 439         if (len < 0)
 440                 return;
 441
 442         /* Insert the 'hole' (see big comment above) at position 3 */
 443         buffer[0] = buffer[1];
 444         buffer[1] = buffer[2];
 445         buffer[2] = buffer[3];
 446         buffer[3] = 0;
 447         len++;
 448
 449         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 450 }
 451
 452 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 453                                          const struct drm_display_mode *adjusted_mode)
 454 {
 455         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 456         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 457         union hdmi_infoframe frame;
 458         int ret;
 459
 460         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 461                                                        adjusted_mode);
 462         if (ret < 0) {
 463                 DRM_ERROR("couldn't fill AVI infoframe\n");
 464                 return;
 465         }
 466
 467         if (intel_hdmi->rgb_quant_range_selectable) {
 468                 if (intel_crtc->config->limited_color_range)
 469                         frame.avi.quantization_range =
 470                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 471                 else
 472                         frame.avi.quantization_range =
 473                                 HDMI_QUANTIZATION_RANGE_FULL;
 474         }
 475
 476         intel_write_infoframe(encoder, &frame);
 477 }
 478
 479 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 480 {
 481         union hdmi_infoframe frame;
 482         int ret;
 483
 484         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 485         if (ret < 0) {
 486                 DRM_ERROR("couldn't fill SPD infoframe\n");
 487                 return;
 488         }
 489
 490         frame.spd.sdi = HDMI_SPD_SDI_PC;
 491
 492         intel_write_infoframe(encoder, &frame);
 493 }
 494
 495 static void
 496 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 497                               const struct drm_display_mode *adjusted_mode)
 498 {
 499         union hdmi_infoframe frame;
 500         int ret;
 501
 502         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 503                                                           adjusted_mode);
 504         if (ret < 0)
 505                 return;
 506
 507         intel_write_infoframe(encoder, &frame);
 508 }
 509
 510 static void g4x_set_infoframes(struct drm_encoder *encoder,
 511                                bool enable,
 512                                const struct drm_display_mode *adjusted_mode)
 513 {
 514         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 515         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 516         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 517         i915_reg_t reg = VIDEO_DIP_CTL;
 518         u32 val = I915_READ(reg);
 519         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 520
 521         assert_hdmi_port_disabled(intel_hdmi);
 522
 523         /* If the registers were not initialized yet, they might be zeroes,
 524          * which means we're selecting the AVI DIP and we're setting its
 525          * frequency to once. This seems to really confuse the HW and make
 526          * things stop working (the register spec says the AVI always needs to
 527          * be sent every VSync). So here we avoid writing to the register more
 528          * than we need and also explicitly select the AVI DIP and explicitly
 529          * set its frequency to every VSync. Avoiding to write it twice seems to
 530          * be enough to solve the problem, but being defensive shouldn't hurt us
 531          * either. */
 532         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 533
 534         if (!enable) {
 535                 if (!(val & VIDEO_DIP_ENABLE))
 536                         return;
 537                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 538                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 539                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 540                         return;
 541                 }
 542                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 543                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 544                 I915_WRITE(reg, val);
 545                 POSTING_READ(reg);
 546                 return;
 547         }
 548
 549         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 550                 if (val & VIDEO_DIP_ENABLE) {
 551                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 552                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 553                         return;
 554                 }
 555                 val &= ~VIDEO_DIP_PORT_MASK;
 556                 val |= port;
 557         }
 558
 559         val |= VIDEO_DIP_ENABLE;
 560         val &= ~(VIDEO_DIP_ENABLE_AVI |
 561                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 562
 563         I915_WRITE(reg, val);
 564         POSTING_READ(reg);
 565
 566         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 567         intel_hdmi_set_spd_infoframe(encoder);
 568         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 569 }
 570
 571 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
 572 {
 573         struct drm_device *dev = encoder->dev;
 574         struct drm_connector *connector;
 575
 576         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 577
 578         /*
 579          * HDMI cloning is only supported on g4x which doesn't
 580          * support deep color or GCP infoframes anyway so no
 581          * need to worry about multiple HDMI sinks here.
 582          */
 583         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 584                 if (connector->encoder == encoder)
 585                         return connector->display_info.bpc > 8;
 586
 587         return false;
 588 }
 589
 590 /*
 591  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 592  *
 593  * From HDMI specification 1.4a:
 594  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 595  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 596  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 597  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 598  *   phase of 0
 599  */
 600 static bool gcp_default_phase_possible(int pipe_bpp,
 601                                        const struct drm_display_mode *mode)
 602 {
 603         unsigned int pixels_per_group;
 604
 605         switch (pipe_bpp) {
 606         case 30:
 607                 /* 4 pixels in 5 clocks */
 608                 pixels_per_group = 4;
 609                 break;
 610         case 36:
 611                 /* 2 pixels in 3 clocks */
 612                 pixels_per_group = 2;
 613                 break;
 614         case 48:
 615                 /* 1 pixel in 2 clocks */
 616                 pixels_per_group = 1;
 617                 break;
 618         default:
 619                 /* phase information not relevant for 8bpc */
 620                 return false;
 621         }
 622
 623         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 624                 mode->crtc_htotal % pixels_per_group == 0 &&
 625                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 626                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 627                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 628                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 629                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 630                  mode->crtc_htotal/2 % pixels_per_group == 0);
 631 }
 632
 633 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
 634 {
 635         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 636         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 637         i915_reg_t reg;
 638         u32 val = 0;
 639
 640         if (HAS_DDI(dev_priv))
 641                 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
 642         else if (IS_VALLEYVIEW(dev_priv))
 643                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 644         else if (HAS_PCH_SPLIT(dev_priv->dev))
 645                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 646         else
 647                 return false;
 648
 649         /* Indicate color depth whenever the sink supports deep color */
 650         if (hdmi_sink_is_deep_color(encoder))
 651                 val |= GCP_COLOR_INDICATION;
 652
 653         /* Enable default_phase whenever the display mode is suitably aligned */
 654         if (gcp_default_phase_possible(crtc->config->pipe_bpp,
 655                                        &crtc->config->base.adjusted_mode))
 656                 val |= GCP_DEFAULT_PHASE_ENABLE;
 657
 658         I915_WRITE(reg, val);
 659
 660         return val != 0;
 661 }
 662
 663 static void ibx_set_infoframes(struct drm_encoder *encoder,
 664                                bool enable,
 665                                const struct drm_display_mode *adjusted_mode)
 666 {
 667         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 668         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 669         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 670         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 671         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 672         u32 val = I915_READ(reg);
 673         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 674
 675         assert_hdmi_port_disabled(intel_hdmi);
 676
 677         /* See the big comment in g4x_set_infoframes() */
 678         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 679
 680         if (!enable) {
 681                 if (!(val & VIDEO_DIP_ENABLE))
 682                         return;
 683                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 684                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 685                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 686                 I915_WRITE(reg, val);
 687                 POSTING_READ(reg);
 688                 return;
 689         }
 690
 691         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 692                 WARN(val & VIDEO_DIP_ENABLE,
 693                      "DIP already enabled on port %c\n",
 694                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 695                 val &= ~VIDEO_DIP_PORT_MASK;
 696                 val |= port;
 697         }
 698
 699         val |= VIDEO_DIP_ENABLE;
 700         val &= ~(VIDEO_DIP_ENABLE_AVI |
 701                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 702                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 703
 704         if (intel_hdmi_set_gcp_infoframe(encoder))
 705                 val |= VIDEO_DIP_ENABLE_GCP;
 706
 707         I915_WRITE(reg, val);
 708         POSTING_READ(reg);
 709
 710         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 711         intel_hdmi_set_spd_infoframe(encoder);
 712         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 713 }
 714
 715 static void cpt_set_infoframes(struct drm_encoder *encoder,
 716                                bool enable,
 717                                const struct drm_display_mode *adjusted_mode)
 718 {
 719         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 720         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 721         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 722         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 723         u32 val = I915_READ(reg);
 724
 725         assert_hdmi_port_disabled(intel_hdmi);
 726
 727         /* See the big comment in g4x_set_infoframes() */
 728         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 729
 730         if (!enable) {
 731                 if (!(val & VIDEO_DIP_ENABLE))
 732                         return;
 733                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 734                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 735                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 736                 I915_WRITE(reg, val);
 737                 POSTING_READ(reg);
 738                 return;
 739         }
 740
 741         /* Set both together, unset both together: see the spec. */
 742         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 743         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 744                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 745
 746         if (intel_hdmi_set_gcp_infoframe(encoder))
 747                 val |= VIDEO_DIP_ENABLE_GCP;
 748
 749         I915_WRITE(reg, val);
 750         POSTING_READ(reg);
 751
 752         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 753         intel_hdmi_set_spd_infoframe(encoder);
 754         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 755 }
 756
 757 static void vlv_set_infoframes(struct drm_encoder *encoder,
 758                                bool enable,
 759                                const struct drm_display_mode *adjusted_mode)
 760 {
 761         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 762         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 763         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 764         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 765         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 766         u32 val = I915_READ(reg);
 767         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 768
 769         assert_hdmi_port_disabled(intel_hdmi);
 770
 771         /* See the big comment in g4x_set_infoframes() */
 772         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 773
 774         if (!enable) {
 775                 if (!(val & VIDEO_DIP_ENABLE))
 776                         return;
 777                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 778                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 779                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 780                 I915_WRITE(reg, val);
 781                 POSTING_READ(reg);
 782                 return;
 783         }
 784
 785         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 786                 WARN(val & VIDEO_DIP_ENABLE,
 787                      "DIP already enabled on port %c\n",
 788                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 789                 val &= ~VIDEO_DIP_PORT_MASK;
 790                 val |= port;
 791         }
 792
 793         val |= VIDEO_DIP_ENABLE;
 794         val &= ~(VIDEO_DIP_ENABLE_AVI |
 795                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 796                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 797
 798         if (intel_hdmi_set_gcp_infoframe(encoder))
 799                 val |= VIDEO_DIP_ENABLE_GCP;
 800
 801         I915_WRITE(reg, val);
 802         POSTING_READ(reg);
 803
 804         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 805         intel_hdmi_set_spd_infoframe(encoder);
 806         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 807 }
 808
 809 static void hsw_set_infoframes(struct drm_encoder *encoder,
 810                                bool enable,
 811                                const struct drm_display_mode *adjusted_mode)
 812 {
 813         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 814         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 815         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 816         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 817         u32 val = I915_READ(reg);
 818
 819         assert_hdmi_port_disabled(intel_hdmi);
 820
 821         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 822                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 823                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 824
 825         if (!enable) {
 826                 I915_WRITE(reg, val);
 827                 POSTING_READ(reg);
 828                 return;
 829         }
 830
 831         if (intel_hdmi_set_gcp_infoframe(encoder))
 832                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
 833
 834         I915_WRITE(reg, val);
 835         POSTING_READ(reg);
 836
 837         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 838         intel_hdmi_set_spd_infoframe(encoder);
 839         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 840 }
 841
 842 static void intel_hdmi_prepare(struct intel_encoder *encoder)
 843 {
 844         struct drm_device *dev = encoder->base.dev;
 845         struct drm_i915_private *dev_priv = dev->dev_private;
 846         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 847         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 848         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 849         u32 hdmi_val;
 850
 851         hdmi_val = SDVO_ENCODING_HDMI;
 852         if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
 853                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
 854         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 855                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 856         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 857                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 858
 859         if (crtc->config->pipe_bpp > 24)
 860                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 861         else
 862                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 863
 864         if (crtc->config->has_hdmi_sink)
 865                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 866
 867         if (HAS_PCH_CPT(dev))
 868                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 869         else if (IS_CHERRYVIEW(dev))
 870                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 871         else
 872                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 873
 874         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 875         POSTING_READ(intel_hdmi->hdmi_reg);
 876 }
 877
 878 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 879                                     enum pipe *pipe)
 880 {
 881         struct drm_device *dev = encoder->base.dev;
 882         struct drm_i915_private *dev_priv = dev->dev_private;
 883         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 884         enum intel_display_power_domain power_domain;
 885         u32 tmp;
 886
 887         power_domain = intel_display_port_power_domain(encoder);
 888         if (!intel_display_power_is_enabled(dev_priv, power_domain))
 889                 return false;
 890
 891         tmp = I915_READ(intel_hdmi->hdmi_reg);
 892
 893         if (!(tmp & SDVO_ENABLE))
 894                 return false;
 895
 896         if (HAS_PCH_CPT(dev))
 897                 *pipe = PORT_TO_PIPE_CPT(tmp);
 898         else if (IS_CHERRYVIEW(dev))
 899                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 900         else
 901                 *pipe = PORT_TO_PIPE(tmp);
 902
 903         return true;
 904 }
 905
 906 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 907                                   struct intel_crtc_state *pipe_config)
 908 {
 909         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 910         struct drm_device *dev = encoder->base.dev;
 911         struct drm_i915_private *dev_priv = dev->dev_private;
 912         u32 tmp, flags = 0;
 913         int dotclock;
 914
 915         tmp = I915_READ(intel_hdmi->hdmi_reg);
 916
 917         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 918                 flags |= DRM_MODE_FLAG_PHSYNC;
 919         else
 920                 flags |= DRM_MODE_FLAG_NHSYNC;
 921
 922         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 923                 flags |= DRM_MODE_FLAG_PVSYNC;
 924         else
 925                 flags |= DRM_MODE_FLAG_NVSYNC;
 926
 927         if (tmp & HDMI_MODE_SELECT_HDMI)
 928                 pipe_config->has_hdmi_sink = true;
 929
 930         if (intel_hdmi->infoframe_enabled(&encoder->base))
 931                 pipe_config->has_infoframe = true;
 932
 933         if (tmp & SDVO_AUDIO_ENABLE)
 934                 pipe_config->has_audio = true;
 935
 936         if (!HAS_PCH_SPLIT(dev) &&
 937             tmp & HDMI_COLOR_RANGE_16_235)
 938                 pipe_config->limited_color_range = true;
 939
 940         pipe_config->base.adjusted_mode.flags |= flags;
 941
 942         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 943                 dotclock = pipe_config->port_clock * 2 / 3;
 944         else
 945                 dotclock = pipe_config->port_clock;
 946
 947         if (pipe_config->pixel_multiplier)
 948                 dotclock /= pipe_config->pixel_multiplier;
 949
 950         if (HAS_PCH_SPLIT(dev_priv->dev))
 951                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 952
 953         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 954 }
 955
 956 static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
 957 {
 958         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 959
 960         WARN_ON(!crtc->config->has_hdmi_sink);
 961         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 962                          pipe_name(crtc->pipe));
 963         intel_audio_codec_enable(encoder);
 964 }
 965
 966 static void g4x_enable_hdmi(struct intel_encoder *encoder)
 967 {
 968         struct drm_device *dev = encoder->base.dev;
 969         struct drm_i915_private *dev_priv = dev->dev_private;
 970         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 971         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 972         u32 temp;
 973
 974         temp = I915_READ(intel_hdmi->hdmi_reg);
 975
 976         temp |= SDVO_ENABLE;
 977         if (crtc->config->has_audio)
 978                 temp |= SDVO_AUDIO_ENABLE;
 979
 980         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 981         POSTING_READ(intel_hdmi->hdmi_reg);
 982
 983         if (crtc->config->has_audio)
 984                 intel_enable_hdmi_audio(encoder);
 985 }
 986
 987 static void ibx_enable_hdmi(struct intel_encoder *encoder)
 988 {
 989         struct drm_device *dev = encoder->base.dev;
 990         struct drm_i915_private *dev_priv = dev->dev_private;
 991         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 992         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 993         u32 temp;
 994
 995         temp = I915_READ(intel_hdmi->hdmi_reg);
 996
 997         temp |= SDVO_ENABLE;
 998         if (crtc->config->has_audio)
 999                 temp |= SDVO_AUDIO_ENABLE;
1000
1001         /*
1002          * HW workaround, need to write this twice for issue
1003          * that may result in first write getting masked.
1004          */
1005         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1006         POSTING_READ(intel_hdmi->hdmi_reg);
1007         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1008         POSTING_READ(intel_hdmi->hdmi_reg);
1009
1010         /*
1011          * HW workaround, need to toggle enable bit off and on
1012          * for 12bpc with pixel repeat.
1013          *
1014          * FIXME: BSpec says this should be done at the end of
1015          * of the modeset sequence, so not sure if this isn't too soon.
1016          */
1017         if (crtc->config->pipe_bpp > 24 &&
1018             crtc->config->pixel_multiplier > 1) {
1019                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1020                 POSTING_READ(intel_hdmi->hdmi_reg);
1021
1022                 /*
1023                  * HW workaround, need to write this twice for issue
1024                  * that may result in first write getting masked.
1025                  */
1026                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1027                 POSTING_READ(intel_hdmi->hdmi_reg);
1028                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1029                 POSTING_READ(intel_hdmi->hdmi_reg);
1030         }
1031
1032         if (crtc->config->has_audio)
1033                 intel_enable_hdmi_audio(encoder);
1034 }
1035
1036 static void cpt_enable_hdmi(struct intel_encoder *encoder)
1037 {
1038         struct drm_device *dev = encoder->base.dev;
1039         struct drm_i915_private *dev_priv = dev->dev_private;
1040         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1041         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1042         enum pipe pipe = crtc->pipe;
1043         u32 temp;
1044
1045         temp = I915_READ(intel_hdmi->hdmi_reg);
1046
1047         temp |= SDVO_ENABLE;
1048         if (crtc->config->has_audio)
1049                 temp |= SDVO_AUDIO_ENABLE;
1050
1051         /*
1052          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1053          *
1054          * The procedure for 12bpc is as follows:
1055          * 1. disable HDMI clock gating
1056          * 2. enable HDMI with 8bpc
1057          * 3. enable HDMI with 12bpc
1058          * 4. enable HDMI clock gating
1059          */
1060
1061         if (crtc->config->pipe_bpp > 24) {
1062                 I915_WRITE(TRANS_CHICKEN1(pipe),
1063                            I915_READ(TRANS_CHICKEN1(pipe)) |
1064                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1065
1066                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1067                 temp |= SDVO_COLOR_FORMAT_8bpc;
1068         }
1069
1070         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1071         POSTING_READ(intel_hdmi->hdmi_reg);
1072
1073         if (crtc->config->pipe_bpp > 24) {
1074                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1075                 temp |= HDMI_COLOR_FORMAT_12bpc;
1076
1077                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1078                 POSTING_READ(intel_hdmi->hdmi_reg);
1079
1080                 I915_WRITE(TRANS_CHICKEN1(pipe),
1081                            I915_READ(TRANS_CHICKEN1(pipe)) &
1082                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1083         }
1084
1085         if (crtc->config->has_audio)
1086                 intel_enable_hdmi_audio(encoder);
1087 }
1088
1089 static void vlv_enable_hdmi(struct intel_encoder *encoder)
1090 {
1091 }
1092
1093 static void intel_disable_hdmi(struct intel_encoder *encoder)
1094 {
1095         struct drm_device *dev = encoder->base.dev;
1096         struct drm_i915_private *dev_priv = dev->dev_private;
1097         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1098         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1099         u32 temp;
1100
1101         temp = I915_READ(intel_hdmi->hdmi_reg);
1102
1103         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1104         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1105         POSTING_READ(intel_hdmi->hdmi_reg);
1106
1107         /*
1108          * HW workaround for IBX, we need to move the port
1109          * to transcoder A after disabling it to allow the
1110          * matching DP port to be enabled on transcoder A.
1111          */
1112         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
1113                 /*
1114                  * We get CPU/PCH FIFO underruns on the other pipe when
1115                  * doing the workaround. Sweep them under the rug.
1116                  */
1117                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1118                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1119
1120                 temp &= ~SDVO_PIPE_B_SELECT;
1121                 temp |= SDVO_ENABLE;
1122                 /*
1123                  * HW workaround, need to write this twice for issue
1124                  * that may result in first write getting masked.
1125                  */
1126                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1127                 POSTING_READ(intel_hdmi->hdmi_reg);
1128                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1129                 POSTING_READ(intel_hdmi->hdmi_reg);
1130
1131                 temp &= ~SDVO_ENABLE;
1132                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1133                 POSTING_READ(intel_hdmi->hdmi_reg);
1134
1135                 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
1136                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1137                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1138         }
1139
1140         intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1141 }
1142
1143 static void g4x_disable_hdmi(struct intel_encoder *encoder)
1144 {
1145         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1146
1147         if (crtc->config->has_audio)
1148                 intel_audio_codec_disable(encoder);
1149
1150         intel_disable_hdmi(encoder);
1151 }
1152
1153 static void pch_disable_hdmi(struct intel_encoder *encoder)
1154 {
1155         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1156
1157         if (crtc->config->has_audio)
1158                 intel_audio_codec_disable(encoder);
1159 }
1160
1161 static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1162 {
1163         intel_disable_hdmi(encoder);
1164 }
1165
1166 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
1167 {
1168         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1169
1170         if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
1171                 return 165000;
1172         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
1173                 return 300000;
1174         else
1175                 return 225000;
1176 }
1177
1178 static enum drm_mode_status
1179 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1180                       int clock, bool respect_dvi_limit)
1181 {
1182         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1183
1184         if (clock < 25000)
1185                 return MODE_CLOCK_LOW;
1186         if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
1187                 return MODE_CLOCK_HIGH;
1188
1189         /* BXT DPLL can't generate 223-240 MHz */
1190         if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
1191                 return MODE_CLOCK_RANGE;
1192
1193         /* CHV DPLL can't generate 216-240 MHz */
1194         if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
1195                 return MODE_CLOCK_RANGE;
1196
1197         return MODE_OK;
1198 }
1199
1200 static enum drm_mode_status
1201 intel_hdmi_mode_valid(struct drm_connector *connector,
1202                       struct drm_display_mode *mode)
1203 {
1204         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1205         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1206         enum drm_mode_status status;
1207         int clock;
1208
1209         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1210                 return MODE_NO_DBLESCAN;
1211
1212         clock = mode->clock;
1213         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1214                 clock *= 2;
1215
1216         /* check if we can do 8bpc */
1217         status = hdmi_port_clock_valid(hdmi, clock, true);
1218
1219         /* if we can't do 8bpc we may still be able to do 12bpc */
1220         if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1221                 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1222
1223         return status;
1224 }
1225
1226 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1227 {
1228         struct drm_device *dev = crtc_state->base.crtc->dev;
1229         struct drm_atomic_state *state;
1230         struct intel_encoder *encoder;
1231         struct drm_connector *connector;
1232         struct drm_connector_state *connector_state;
1233         int count = 0, count_hdmi = 0;
1234         int i;
1235
1236         if (HAS_GMCH_DISPLAY(dev))
1237                 return false;
1238
1239         state = crtc_state->base.state;
1240
1241         for_each_connector_in_state(state, connector, connector_state, i) {
1242                 if (connector_state->crtc != crtc_state->base.crtc)
1243                         continue;
1244
1245                 encoder = to_intel_encoder(connector_state->best_encoder);
1246
1247                 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
1248                 count++;
1249         }
1250
1251         /*
1252          * HDMI 12bpc affects the clocks, so it's only possible
1253          * when not cloning with other encoder types.
1254          */
1255         return count_hdmi > 0 && count_hdmi == count;
1256 }
1257
1258 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1259                                struct intel_crtc_state *pipe_config)
1260 {
1261         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1262         struct drm_device *dev = encoder->base.dev;
1263         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1264         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1265         int clock_12bpc = clock_8bpc * 3 / 2;
1266         int desired_bpp;
1267
1268         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1269
1270         if (pipe_config->has_hdmi_sink)
1271                 pipe_config->has_infoframe = true;
1272
1273         if (intel_hdmi->color_range_auto) {
1274                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1275                 pipe_config->limited_color_range =
1276                         pipe_config->has_hdmi_sink &&
1277                         drm_match_cea_mode(adjusted_mode) > 1;
1278         } else {
1279                 pipe_config->limited_color_range =
1280                         intel_hdmi->limited_color_range;
1281         }
1282
1283         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1284                 pipe_config->pixel_multiplier = 2;
1285                 clock_8bpc *= 2;
1286                 clock_12bpc *= 2;
1287         }
1288
1289         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1290                 pipe_config->has_pch_encoder = true;
1291
1292         if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1293                 pipe_config->has_audio = true;
1294
1295         /*
1296          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1297          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1298          * outputs. We also need to check that the higher clock still fits
1299          * within limits.
1300          */
1301         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1302             hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK &&
1303             hdmi_12bpc_possible(pipe_config)) {
1304                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1305                 desired_bpp = 12*3;
1306
1307                 /* Need to adjust the port link by 1.5x for 12bpc. */
1308                 pipe_config->port_clock = clock_12bpc;
1309         } else {
1310                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1311                 desired_bpp = 8*3;
1312
1313                 pipe_config->port_clock = clock_8bpc;
1314         }
1315
1316         if (!pipe_config->bw_constrained) {
1317                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1318                 pipe_config->pipe_bpp = desired_bpp;
1319         }
1320
1321         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1322                                   false) != MODE_OK) {
1323                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1324                 return false;
1325         }
1326
1327         /* Set user selected PAR to incoming mode's member */
1328         adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1329
1330         return true;
1331 }
1332
1333 static void
1334 intel_hdmi_unset_edid(struct drm_connector *connector)
1335 {
1336         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1337
1338         intel_hdmi->has_hdmi_sink = false;
1339         intel_hdmi->has_audio = false;
1340         intel_hdmi->rgb_quant_range_selectable = false;
1341
1342         kfree(to_intel_connector(connector)->detect_edid);
1343         to_intel_connector(connector)->detect_edid = NULL;
1344 }
1345
1346 static bool
1347 intel_hdmi_set_edid(struct drm_connector *connector, bool force)
1348 {
1349         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1350         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1351         struct edid *edid = NULL;
1352         bool connected = false;
1353
1354         if (force) {
1355                 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1356
1357                 edid = drm_get_edid(connector,
1358                                     intel_gmbus_get_adapter(dev_priv,
1359                                     intel_hdmi->ddc_bus));
1360
1361                 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1362         }
1363
1364         to_intel_connector(connector)->detect_edid = edid;
1365         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1366                 intel_hdmi->rgb_quant_range_selectable =
1367                         drm_rgb_quant_range_selectable(edid);
1368
1369                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1370                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1371                         intel_hdmi->has_audio =
1372                                 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1373
1374                 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1375                         intel_hdmi->has_hdmi_sink =
1376                                 drm_detect_hdmi_monitor(edid);
1377
1378                 connected = true;
1379         }
1380
1381         return connected;
1382 }
1383
1384 static enum drm_connector_status
1385 intel_hdmi_detect(struct drm_connector *connector, bool force)
1386 {
1387         enum drm_connector_status status;
1388         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1389         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1390         bool live_status = false;
1391         unsigned int retry = 3;
1392
1393         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1394                       connector->base.id, connector->name);
1395
1396         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1397
1398         while (!live_status && --retry) {
1399                 live_status = intel_digital_port_connected(dev_priv,
1400                                 hdmi_to_dig_port(intel_hdmi));
1401                 mdelay(10);
1402         }
1403
1404         if (!live_status)
1405                 DRM_DEBUG_KMS("Live status not up!");
1406
1407         intel_hdmi_unset_edid(connector);
1408
1409         if (intel_hdmi_set_edid(connector, live_status)) {
1410                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1411
1412                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1413                 status = connector_status_connected;
1414         } else
1415                 status = connector_status_disconnected;
1416
1417         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1418
1419         return status;
1420 }
1421
1422 static void
1423 intel_hdmi_force(struct drm_connector *connector)
1424 {
1425         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1426
1427         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1428                       connector->base.id, connector->name);
1429
1430         intel_hdmi_unset_edid(connector);
1431
1432         if (connector->status != connector_status_connected)
1433                 return;
1434
1435         intel_hdmi_set_edid(connector, true);
1436         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1437 }
1438
1439 static int intel_hdmi_get_modes(struct drm_connector *connector)
1440 {
1441         struct edid *edid;
1442
1443         edid = to_intel_connector(connector)->detect_edid;
1444         if (edid == NULL)
1445                 return 0;
1446
1447         return intel_connector_update_modes(connector, edid);
1448 }
1449
1450 static bool
1451 intel_hdmi_detect_audio(struct drm_connector *connector)
1452 {
1453         bool has_audio = false;
1454         struct edid *edid;
1455
1456         edid = to_intel_connector(connector)->detect_edid;
1457         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1458                 has_audio = drm_detect_monitor_audio(edid);
1459
1460         return has_audio;
1461 }
1462
1463 static int
1464 intel_hdmi_set_property(struct drm_connector *connector,
1465                         struct drm_property *property,
1466                         uint64_t val)
1467 {
1468         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1469         struct intel_digital_port *intel_dig_port =
1470                 hdmi_to_dig_port(intel_hdmi);
1471         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1472         int ret;
1473
1474         ret = drm_object_property_set_value(&connector->base, property, val);
1475         if (ret)
1476                 return ret;
1477
1478         if (property == dev_priv->force_audio_property) {
1479                 enum hdmi_force_audio i = val;
1480                 bool has_audio;
1481
1482                 if (i == intel_hdmi->force_audio)
1483                         return 0;
1484
1485                 intel_hdmi->force_audio = i;
1486
1487                 if (i == HDMI_AUDIO_AUTO)
1488                         has_audio = intel_hdmi_detect_audio(connector);
1489                 else
1490                         has_audio = (i == HDMI_AUDIO_ON);
1491
1492                 if (i == HDMI_AUDIO_OFF_DVI)
1493                         intel_hdmi->has_hdmi_sink = 0;
1494
1495                 intel_hdmi->has_audio = has_audio;
1496                 goto done;
1497         }
1498
1499         if (property == dev_priv->broadcast_rgb_property) {
1500                 bool old_auto = intel_hdmi->color_range_auto;
1501                 bool old_range = intel_hdmi->limited_color_range;
1502
1503                 switch (val) {
1504                 case INTEL_BROADCAST_RGB_AUTO:
1505                         intel_hdmi->color_range_auto = true;
1506                         break;
1507                 case INTEL_BROADCAST_RGB_FULL:
1508                         intel_hdmi->color_range_auto = false;
1509                         intel_hdmi->limited_color_range = false;
1510                         break;
1511                 case INTEL_BROADCAST_RGB_LIMITED:
1512                         intel_hdmi->color_range_auto = false;
1513                         intel_hdmi->limited_color_range = true;
1514                         break;
1515                 default:
1516                         return -EINVAL;
1517                 }
1518
1519                 if (old_auto == intel_hdmi->color_range_auto &&
1520                     old_range == intel_hdmi->limited_color_range)
1521                         return 0;
1522
1523                 goto done;
1524         }
1525
1526         if (property == connector->dev->mode_config.aspect_ratio_property) {
1527                 switch (val) {
1528                 case DRM_MODE_PICTURE_ASPECT_NONE:
1529                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1530                         break;
1531                 case DRM_MODE_PICTURE_ASPECT_4_3:
1532                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1533                         break;
1534                 case DRM_MODE_PICTURE_ASPECT_16_9:
1535                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1536                         break;
1537                 default:
1538                         return -EINVAL;
1539                 }
1540                 goto done;
1541         }
1542
1543         return -EINVAL;
1544
1545 done:
1546         if (intel_dig_port->base.base.crtc)
1547                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1548
1549         return 0;
1550 }
1551
1552 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1553 {
1554         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1555         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1556         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1557
1558         intel_hdmi_prepare(encoder);
1559
1560         intel_hdmi->set_infoframes(&encoder->base,
1561                                    intel_crtc->config->has_hdmi_sink,
1562                                    adjusted_mode);
1563 }
1564
1565 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1566 {
1567         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1568         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1569         struct drm_device *dev = encoder->base.dev;
1570         struct drm_i915_private *dev_priv = dev->dev_private;
1571         struct intel_crtc *intel_crtc =
1572                 to_intel_crtc(encoder->base.crtc);
1573         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1574         enum dpio_channel port = vlv_dport_to_channel(dport);
1575         int pipe = intel_crtc->pipe;
1576         u32 val;
1577
1578         /* Enable clock channels for this port */
1579         mutex_lock(&dev_priv->sb_lock);
1580         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1581         val = 0;
1582         if (pipe)
1583                 val |= (1<<21);
1584         else
1585                 val &= ~(1<<21);
1586         val |= 0x001000c4;
1587         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1588
1589         /* HDMI 1.0V-2dB */
1590         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1591         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1592         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1593         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1594         vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1595         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1596         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1597         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1598
1599         /* Program lane clock */
1600         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1601         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1602         mutex_unlock(&dev_priv->sb_lock);
1603
1604         intel_hdmi->set_infoframes(&encoder->base,
1605                                    intel_crtc->config->has_hdmi_sink,
1606                                    adjusted_mode);
1607
1608         g4x_enable_hdmi(encoder);
1609
1610         vlv_wait_port_ready(dev_priv, dport, 0x0);
1611 }
1612
1613 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1614 {
1615         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1616         struct drm_device *dev = encoder->base.dev;
1617         struct drm_i915_private *dev_priv = dev->dev_private;
1618         struct intel_crtc *intel_crtc =
1619                 to_intel_crtc(encoder->base.crtc);
1620         enum dpio_channel port = vlv_dport_to_channel(dport);
1621         int pipe = intel_crtc->pipe;
1622
1623         intel_hdmi_prepare(encoder);
1624
1625         /* Program Tx lane resets to default */
1626         mutex_lock(&dev_priv->sb_lock);
1627         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1628                          DPIO_PCS_TX_LANE2_RESET |
1629                          DPIO_PCS_TX_LANE1_RESET);
1630         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1631                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1632                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1633                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1634                          DPIO_PCS_CLK_SOFT_RESET);
1635
1636         /* Fix up inter-pair skew failure */
1637         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1638         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1639         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1640
1641         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1642         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1643         mutex_unlock(&dev_priv->sb_lock);
1644 }
1645
1646 static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
1647                                      bool reset)
1648 {
1649         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1650         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1651         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1652         enum pipe pipe = crtc->pipe;
1653         uint32_t val;
1654
1655         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1656         if (reset)
1657                 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1658         else
1659                 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1660         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1661
1662         if (crtc->config->lane_count > 2) {
1663                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1664                 if (reset)
1665                         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1666                 else
1667                         val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1668                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1669         }
1670
1671         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1672         val |= CHV_PCS_REQ_SOFTRESET_EN;
1673         if (reset)
1674                 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1675         else
1676                 val |= DPIO_PCS_CLK_SOFT_RESET;
1677         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1678
1679         if (crtc->config->lane_count > 2) {
1680                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1681                 val |= CHV_PCS_REQ_SOFTRESET_EN;
1682                 if (reset)
1683                         val &= ~DPIO_PCS_CLK_SOFT_RESET;
1684                 else
1685                         val |= DPIO_PCS_CLK_SOFT_RESET;
1686                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1687         }
1688 }
1689
1690 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1691 {
1692         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1693         struct drm_device *dev = encoder->base.dev;
1694         struct drm_i915_private *dev_priv = dev->dev_private;
1695         struct intel_crtc *intel_crtc =
1696                 to_intel_crtc(encoder->base.crtc);
1697         enum dpio_channel ch = vlv_dport_to_channel(dport);
1698         enum pipe pipe = intel_crtc->pipe;
1699         u32 val;
1700
1701         intel_hdmi_prepare(encoder);
1702
1703         /*
1704          * Must trick the second common lane into life.
1705          * Otherwise we can't even access the PLL.
1706          */
1707         if (ch == DPIO_CH0 && pipe == PIPE_B)
1708                 dport->release_cl2_override =
1709                         !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
1710
1711         chv_phy_powergate_lanes(encoder, true, 0x0);
1712
1713         mutex_lock(&dev_priv->sb_lock);
1714
1715         /* Assert data lane reset */
1716         chv_data_lane_soft_reset(encoder, true);
1717
1718         /* program left/right clock distribution */
1719         if (pipe != PIPE_B) {
1720                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1721                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1722                 if (ch == DPIO_CH0)
1723                         val |= CHV_BUFLEFTENA1_FORCE;
1724                 if (ch == DPIO_CH1)
1725                         val |= CHV_BUFRIGHTENA1_FORCE;
1726                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1727         } else {
1728                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1729                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1730                 if (ch == DPIO_CH0)
1731                         val |= CHV_BUFLEFTENA2_FORCE;
1732                 if (ch == DPIO_CH1)
1733                         val |= CHV_BUFRIGHTENA2_FORCE;
1734                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1735         }
1736
1737         /* program clock channel usage */
1738         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1739         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1740         if (pipe != PIPE_B)
1741                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1742         else
1743                 val |= CHV_PCS_USEDCLKCHANNEL;
1744         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1745
1746         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1747         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1748         if (pipe != PIPE_B)
1749                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1750         else
1751                 val |= CHV_PCS_USEDCLKCHANNEL;
1752         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1753
1754         /*
1755          * This a a bit weird since generally CL
1756          * matches the pipe, but here we need to
1757          * pick the CL based on the port.
1758          */
1759         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1760         if (pipe != PIPE_B)
1761                 val &= ~CHV_CMN_USEDCLKCHANNEL;
1762         else
1763                 val |= CHV_CMN_USEDCLKCHANNEL;
1764         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1765
1766         mutex_unlock(&dev_priv->sb_lock);
1767 }
1768
1769 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
1770 {
1771         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1772         enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
1773         u32 val;
1774
1775         mutex_lock(&dev_priv->sb_lock);
1776
1777         /* disable left/right clock distribution */
1778         if (pipe != PIPE_B) {
1779                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1780                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1781                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1782         } else {
1783                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1784                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1785                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1786         }
1787
1788         mutex_unlock(&dev_priv->sb_lock);
1789
1790         /*
1791          * Leave the power down bit cleared for at least one
1792          * lane so that chv_powergate_phy_ch() will power
1793          * on something when the channel is otherwise unused.
1794          * When the port is off and the override is removed
1795          * the lanes power down anyway, so otherwise it doesn't
1796          * really matter what the state of power down bits is
1797          * after this.
1798          */
1799         chv_phy_powergate_lanes(encoder, false, 0x0);
1800 }
1801
1802 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1803 {
1804         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1805         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1806         struct intel_crtc *intel_crtc =
1807                 to_intel_crtc(encoder->base.crtc);
1808         enum dpio_channel port = vlv_dport_to_channel(dport);
1809         int pipe = intel_crtc->pipe;
1810
1811         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1812         mutex_lock(&dev_priv->sb_lock);
1813         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1814         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1815         mutex_unlock(&dev_priv->sb_lock);
1816 }
1817
1818 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1819 {
1820         struct drm_device *dev = encoder->base.dev;
1821         struct drm_i915_private *dev_priv = dev->dev_private;
1822
1823         mutex_lock(&dev_priv->sb_lock);
1824
1825         /* Assert data lane reset */
1826         chv_data_lane_soft_reset(encoder, true);
1827
1828         mutex_unlock(&dev_priv->sb_lock);
1829 }
1830
1831 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1832 {
1833         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1834         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1835         struct drm_device *dev = encoder->base.dev;
1836         struct drm_i915_private *dev_priv = dev->dev_private;
1837         struct intel_crtc *intel_crtc =
1838                 to_intel_crtc(encoder->base.crtc);
1839         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1840         enum dpio_channel ch = vlv_dport_to_channel(dport);
1841         int pipe = intel_crtc->pipe;
1842         int data, i, stagger;
1843         u32 val;
1844
1845         mutex_lock(&dev_priv->sb_lock);
1846
1847         /* allow hardware to manage TX FIFO reset source */
1848         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1849         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1850         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1851
1852         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1853         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1854         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1855
1856         /* Program Tx latency optimal setting */
1857         for (i = 0; i < 4; i++) {
1858                 /* Set the upar bit */
1859                 data = (i == 1) ? 0x0 : 0x1;
1860                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1861                                 data << DPIO_UPAR_SHIFT);
1862         }
1863
1864         /* Data lane stagger programming */
1865         if (intel_crtc->config->port_clock > 270000)
1866                 stagger = 0x18;
1867         else if (intel_crtc->config->port_clock > 135000)
1868                 stagger = 0xd;
1869         else if (intel_crtc->config->port_clock > 67500)
1870                 stagger = 0x7;
1871         else if (intel_crtc->config->port_clock > 33750)
1872                 stagger = 0x4;
1873         else
1874                 stagger = 0x2;
1875
1876         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1877         val |= DPIO_TX2_STAGGER_MASK(0x1f);
1878         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1879
1880         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1881         val |= DPIO_TX2_STAGGER_MASK(0x1f);
1882         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1883
1884         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1885                        DPIO_LANESTAGGER_STRAP(stagger) |
1886                        DPIO_LANESTAGGER_STRAP_OVRD |
1887                        DPIO_TX1_STAGGER_MASK(0x1f) |
1888                        DPIO_TX1_STAGGER_MULT(6) |
1889                        DPIO_TX2_STAGGER_MULT(0));
1890
1891         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1892                        DPIO_LANESTAGGER_STRAP(stagger) |
1893                        DPIO_LANESTAGGER_STRAP_OVRD |
1894                        DPIO_TX1_STAGGER_MASK(0x1f) |
1895                        DPIO_TX1_STAGGER_MULT(7) |
1896                        DPIO_TX2_STAGGER_MULT(5));
1897
1898         /* Deassert data lane reset */
1899         chv_data_lane_soft_reset(encoder, false);
1900
1901         /* Clear calc init */
1902         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1903         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1904         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1905         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1906         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1907
1908         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1909         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1910         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1911         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1912         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1913
1914         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1915         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1916         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1917         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1918
1919         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1920         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1921         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1922         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1923
1924         /* FIXME: Program the support xxx V-dB */
1925         /* Use 800mV-0dB */
1926         for (i = 0; i < 4; i++) {
1927                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1928                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1929                 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1930                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1931         }
1932
1933         for (i = 0; i < 4; i++) {
1934                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1935
1936                 val &= ~DPIO_SWING_MARGIN000_MASK;
1937                 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1938
1939                 /*
1940                  * Supposedly this value shouldn't matter when unique transition
1941                  * scale is disabled, but in fact it does matter. Let's just
1942                  * always program the same value and hope it's OK.
1943                  */
1944                 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
1945                 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
1946
1947                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1948         }
1949
1950         /*
1951          * The document said it needs to set bit 27 for ch0 and bit 26
1952          * for ch1. Might be a typo in the doc.
1953          * For now, for this unique transition scale selection, set bit
1954          * 27 for ch0 and ch1.
1955          */
1956         for (i = 0; i < 4; i++) {
1957                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1958                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1959                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1960         }
1961
1962         /* Start swing calculation */
1963         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1964         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1965         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1966
1967         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1968         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1969         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1970
1971         mutex_unlock(&dev_priv->sb_lock);
1972
1973         intel_hdmi->set_infoframes(&encoder->base,
1974                                    intel_crtc->config->has_hdmi_sink,
1975                                    adjusted_mode);
1976
1977         g4x_enable_hdmi(encoder);
1978
1979         vlv_wait_port_ready(dev_priv, dport, 0x0);
1980
1981         /* Second common lane will stay alive on its own now */
1982         if (dport->release_cl2_override) {
1983                 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
1984                 dport->release_cl2_override = false;
1985         }
1986 }
1987
1988 static void intel_hdmi_destroy(struct drm_connector *connector)
1989 {
1990         kfree(to_intel_connector(connector)->detect_edid);
1991         drm_connector_cleanup(connector);
1992         kfree(connector);
1993 }
1994
1995 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1996         .dpms = drm_atomic_helper_connector_dpms,
1997         .detect = intel_hdmi_detect,
1998         .force = intel_hdmi_force,
1999         .fill_modes = drm_helper_probe_single_connector_modes,
2000         .set_property = intel_hdmi_set_property,
2001         .atomic_get_property = intel_connector_atomic_get_property,
2002         .destroy = intel_hdmi_destroy,
2003         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2004         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2005 };
2006
2007 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2008         .get_modes = intel_hdmi_get_modes,
2009         .mode_valid = intel_hdmi_mode_valid,
2010         .best_encoder = intel_best_encoder,
2011 };
2012
2013 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2014         .destroy = intel_encoder_destroy,
2015 };
2016
2017 static void
2018 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2019 {
2020         intel_attach_force_audio_property(connector);
2021         intel_attach_broadcast_rgb_property(connector);
2022         intel_hdmi->color_range_auto = true;
2023         intel_attach_aspect_ratio_property(connector);
2024         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2025 }
2026
2027 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2028                                struct intel_connector *intel_connector)
2029 {
2030         struct drm_connector *connector = &intel_connector->base;
2031         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2032         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2033         struct drm_device *dev = intel_encoder->base.dev;
2034         struct drm_i915_private *dev_priv = dev->dev_private;
2035         enum port port = intel_dig_port->port;
2036         uint8_t alternate_ddc_pin;
2037
2038         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2039                            DRM_MODE_CONNECTOR_HDMIA);
2040         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2041
2042         connector->interlace_allowed = 1;
2043         connector->doublescan_allowed = 0;
2044         connector->stereo_allowed = 1;
2045
2046         switch (port) {
2047         case PORT_B:
2048                 if (IS_BROXTON(dev_priv))
2049                         intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
2050                 else
2051                         intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2052                 /*
2053                  * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2054                  * interrupts to check the external panel connection.
2055                  */
2056                 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
2057                         intel_encoder->hpd_pin = HPD_PORT_A;
2058                 else
2059                         intel_encoder->hpd_pin = HPD_PORT_B;
2060                 break;
2061         case PORT_C:
2062                 if (IS_BROXTON(dev_priv))
2063                         intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
2064                 else
2065                         intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2066                 intel_encoder->hpd_pin = HPD_PORT_C;
2067                 break;
2068         case PORT_D:
2069                 if (WARN_ON(IS_BROXTON(dev_priv)))
2070                         intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
2071                 else if (IS_CHERRYVIEW(dev_priv))
2072                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
2073                 else
2074                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2075                 intel_encoder->hpd_pin = HPD_PORT_D;
2076                 break;
2077         case PORT_E:
2078                 /* On SKL PORT E doesn't have seperate GMBUS pin
2079                  *  We rely on VBT to set a proper alternate GMBUS pin. */
2080                 alternate_ddc_pin =
2081                         dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
2082                 switch (alternate_ddc_pin) {
2083                 case DDC_PIN_B:
2084                         intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2085                         break;
2086                 case DDC_PIN_C:
2087                         intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2088                         break;
2089                 case DDC_PIN_D:
2090                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2091                         break;
2092                 default:
2093                         MISSING_CASE(alternate_ddc_pin);
2094                 }
2095                 intel_encoder->hpd_pin = HPD_PORT_E;
2096                 break;
2097         case PORT_A:
2098                 intel_encoder->hpd_pin = HPD_PORT_A;
2099                 /* Internal port only for eDP. */
2100         default:
2101                 BUG();
2102         }
2103
2104         if (IS_VALLEYVIEW(dev)) {
2105                 intel_hdmi->write_infoframe = vlv_write_infoframe;
2106                 intel_hdmi->set_infoframes = vlv_set_infoframes;
2107                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
2108         } else if (IS_G4X(dev)) {
2109                 intel_hdmi->write_infoframe = g4x_write_infoframe;
2110                 intel_hdmi->set_infoframes = g4x_set_infoframes;
2111                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
2112         } else if (HAS_DDI(dev)) {
2113                 intel_hdmi->write_infoframe = hsw_write_infoframe;
2114                 intel_hdmi->set_infoframes = hsw_set_infoframes;
2115                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
2116         } else if (HAS_PCH_IBX(dev)) {
2117                 intel_hdmi->write_infoframe = ibx_write_infoframe;
2118                 intel_hdmi->set_infoframes = ibx_set_infoframes;
2119                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2120         } else {
2121                 intel_hdmi->write_infoframe = cpt_write_infoframe;
2122                 intel_hdmi->set_infoframes = cpt_set_infoframes;
2123                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2124         }
2125
2126         if (HAS_DDI(dev))
2127                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2128         else
2129                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2130         intel_connector->unregister = intel_connector_unregister;
2131
2132         intel_hdmi_add_properties(intel_hdmi, connector);
2133
2134         intel_connector_attach_encoder(intel_connector, intel_encoder);
2135         drm_connector_register(connector);
2136         intel_hdmi->attached_connector = intel_connector;
2137
2138         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2139          * 0xd.  Failure to do so will result in spurious interrupts being
2140          * generated on the port when a cable is not attached.
2141          */
2142         if (IS_G4X(dev) && !IS_GM45(dev)) {
2143                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2144                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2145         }
2146 }
2147
2148 void intel_hdmi_init(struct drm_device *dev,
2149                      i915_reg_t hdmi_reg, enum port port)
2150 {
2151         struct intel_digital_port *intel_dig_port;
2152         struct intel_encoder *intel_encoder;
2153         struct intel_connector *intel_connector;
2154
2155         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2156         if (!intel_dig_port)
2157                 return;
2158
2159         intel_connector = intel_connector_alloc();
2160         if (!intel_connector) {
2161                 kfree(intel_dig_port);
2162                 return;
2163         }
2164
2165         intel_encoder = &intel_dig_port->base;
2166
2167         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
2168                          DRM_MODE_ENCODER_TMDS);
2169
2170         intel_encoder->compute_config = intel_hdmi_compute_config;
2171         if (HAS_PCH_SPLIT(dev)) {
2172                 intel_encoder->disable = pch_disable_hdmi;
2173                 intel_encoder->post_disable = pch_post_disable_hdmi;
2174         } else {
2175                 intel_encoder->disable = g4x_disable_hdmi;
2176         }
2177         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2178         intel_encoder->get_config = intel_hdmi_get_config;
2179         if (IS_CHERRYVIEW(dev)) {
2180                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2181                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2182                 intel_encoder->enable = vlv_enable_hdmi;
2183                 intel_encoder->post_disable = chv_hdmi_post_disable;
2184                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2185         } else if (IS_VALLEYVIEW(dev)) {
2186                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2187                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2188                 intel_encoder->enable = vlv_enable_hdmi;
2189                 intel_encoder->post_disable = vlv_hdmi_post_disable;
2190         } else {
2191                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2192                 if (HAS_PCH_CPT(dev))
2193                         intel_encoder->enable = cpt_enable_hdmi;
2194                 else if (HAS_PCH_IBX(dev))
2195                         intel_encoder->enable = ibx_enable_hdmi;
2196                 else
2197                         intel_encoder->enable = g4x_enable_hdmi;
2198         }
2199
2200         intel_encoder->type = INTEL_OUTPUT_HDMI;
2201         if (IS_CHERRYVIEW(dev)) {
2202                 if (port == PORT_D)
2203                         intel_encoder->crtc_mask = 1 << 2;
2204                 else
2205                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2206         } else {
2207                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2208         }
2209         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2210         /*
2211          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2212          * to work on real hardware. And since g4x can send infoframes to
2213          * only one port anyway, nothing is lost by allowing it.
2214          */
2215         if (IS_G4X(dev))
2216                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2217
2218         intel_dig_port->port = port;
2219         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2220         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2221
2222         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2223 }