2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
39 #include <drm/intel_lpe_audio.h>
42 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
44 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
48 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
50 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
51 struct drm_i915_private *dev_priv = to_i915(dev);
52 uint32_t enabled_bits;
54 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
56 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
57 "HDMI port enabled, expecting disabled\n");
60 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
62 struct intel_digital_port *intel_dig_port =
63 container_of(encoder, struct intel_digital_port, base.base);
64 return &intel_dig_port->hdmi;
67 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
69 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
72 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
75 case HDMI_INFOFRAME_TYPE_AVI:
76 return VIDEO_DIP_SELECT_AVI;
77 case HDMI_INFOFRAME_TYPE_SPD:
78 return VIDEO_DIP_SELECT_SPD;
79 case HDMI_INFOFRAME_TYPE_VENDOR:
80 return VIDEO_DIP_SELECT_VENDOR;
87 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
90 case HDMI_INFOFRAME_TYPE_AVI:
91 return VIDEO_DIP_ENABLE_AVI;
92 case HDMI_INFOFRAME_TYPE_SPD:
93 return VIDEO_DIP_ENABLE_SPD;
94 case HDMI_INFOFRAME_TYPE_VENDOR:
95 return VIDEO_DIP_ENABLE_VENDOR;
102 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
105 case HDMI_INFOFRAME_TYPE_AVI:
106 return VIDEO_DIP_ENABLE_AVI_HSW;
107 case HDMI_INFOFRAME_TYPE_SPD:
108 return VIDEO_DIP_ENABLE_SPD_HSW;
109 case HDMI_INFOFRAME_TYPE_VENDOR:
110 return VIDEO_DIP_ENABLE_VS_HSW;
118 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
119 enum transcoder cpu_transcoder,
120 enum hdmi_infoframe_type type,
124 case HDMI_INFOFRAME_TYPE_AVI:
125 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
126 case HDMI_INFOFRAME_TYPE_SPD:
127 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
128 case HDMI_INFOFRAME_TYPE_VENDOR:
129 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
132 return INVALID_MMIO_REG;
136 static void g4x_write_infoframe(struct drm_encoder *encoder,
137 const struct intel_crtc_state *crtc_state,
138 enum hdmi_infoframe_type type,
139 const void *frame, ssize_t len)
141 const uint32_t *data = frame;
142 struct drm_device *dev = encoder->dev;
143 struct drm_i915_private *dev_priv = to_i915(dev);
144 u32 val = I915_READ(VIDEO_DIP_CTL);
147 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
149 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
150 val |= g4x_infoframe_index(type);
152 val &= ~g4x_infoframe_enable(type);
154 I915_WRITE(VIDEO_DIP_CTL, val);
157 for (i = 0; i < len; i += 4) {
158 I915_WRITE(VIDEO_DIP_DATA, *data);
161 /* Write every possible data byte to force correct ECC calculation. */
162 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
163 I915_WRITE(VIDEO_DIP_DATA, 0);
166 val |= g4x_infoframe_enable(type);
167 val &= ~VIDEO_DIP_FREQ_MASK;
168 val |= VIDEO_DIP_FREQ_VSYNC;
170 I915_WRITE(VIDEO_DIP_CTL, val);
171 POSTING_READ(VIDEO_DIP_CTL);
174 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
175 const struct intel_crtc_state *pipe_config)
177 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
178 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
179 u32 val = I915_READ(VIDEO_DIP_CTL);
181 if ((val & VIDEO_DIP_ENABLE) == 0)
184 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
187 return val & (VIDEO_DIP_ENABLE_AVI |
188 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
191 static void ibx_write_infoframe(struct drm_encoder *encoder,
192 const struct intel_crtc_state *crtc_state,
193 enum hdmi_infoframe_type type,
194 const void *frame, ssize_t len)
196 const uint32_t *data = frame;
197 struct drm_device *dev = encoder->dev;
198 struct drm_i915_private *dev_priv = to_i915(dev);
199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
200 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
201 u32 val = I915_READ(reg);
204 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
206 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
207 val |= g4x_infoframe_index(type);
209 val &= ~g4x_infoframe_enable(type);
211 I915_WRITE(reg, val);
214 for (i = 0; i < len; i += 4) {
215 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
218 /* Write every possible data byte to force correct ECC calculation. */
219 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
220 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
223 val |= g4x_infoframe_enable(type);
224 val &= ~VIDEO_DIP_FREQ_MASK;
225 val |= VIDEO_DIP_FREQ_VSYNC;
227 I915_WRITE(reg, val);
231 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
232 const struct intel_crtc_state *pipe_config)
234 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
235 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
236 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
237 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
238 u32 val = I915_READ(reg);
240 if ((val & VIDEO_DIP_ENABLE) == 0)
243 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
246 return val & (VIDEO_DIP_ENABLE_AVI |
247 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
248 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
251 static void cpt_write_infoframe(struct drm_encoder *encoder,
252 const struct intel_crtc_state *crtc_state,
253 enum hdmi_infoframe_type type,
254 const void *frame, ssize_t len)
256 const uint32_t *data = frame;
257 struct drm_device *dev = encoder->dev;
258 struct drm_i915_private *dev_priv = to_i915(dev);
259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
260 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
261 u32 val = I915_READ(reg);
264 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
266 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
267 val |= g4x_infoframe_index(type);
269 /* The DIP control register spec says that we need to update the AVI
270 * infoframe without clearing its enable bit */
271 if (type != HDMI_INFOFRAME_TYPE_AVI)
272 val &= ~g4x_infoframe_enable(type);
274 I915_WRITE(reg, val);
277 for (i = 0; i < len; i += 4) {
278 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
281 /* Write every possible data byte to force correct ECC calculation. */
282 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
283 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
286 val |= g4x_infoframe_enable(type);
287 val &= ~VIDEO_DIP_FREQ_MASK;
288 val |= VIDEO_DIP_FREQ_VSYNC;
290 I915_WRITE(reg, val);
294 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
295 const struct intel_crtc_state *pipe_config)
297 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
298 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
299 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
301 if ((val & VIDEO_DIP_ENABLE) == 0)
304 return val & (VIDEO_DIP_ENABLE_AVI |
305 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
306 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
309 static void vlv_write_infoframe(struct drm_encoder *encoder,
310 const struct intel_crtc_state *crtc_state,
311 enum hdmi_infoframe_type type,
312 const void *frame, ssize_t len)
314 const uint32_t *data = frame;
315 struct drm_device *dev = encoder->dev;
316 struct drm_i915_private *dev_priv = to_i915(dev);
317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
318 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
319 u32 val = I915_READ(reg);
322 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
324 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
325 val |= g4x_infoframe_index(type);
327 val &= ~g4x_infoframe_enable(type);
329 I915_WRITE(reg, val);
332 for (i = 0; i < len; i += 4) {
333 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
336 /* Write every possible data byte to force correct ECC calculation. */
337 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
338 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
341 val |= g4x_infoframe_enable(type);
342 val &= ~VIDEO_DIP_FREQ_MASK;
343 val |= VIDEO_DIP_FREQ_VSYNC;
345 I915_WRITE(reg, val);
349 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
350 const struct intel_crtc_state *pipe_config)
352 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
353 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
354 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
355 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
357 if ((val & VIDEO_DIP_ENABLE) == 0)
360 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
363 return val & (VIDEO_DIP_ENABLE_AVI |
364 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
365 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
368 static void hsw_write_infoframe(struct drm_encoder *encoder,
369 const struct intel_crtc_state *crtc_state,
370 enum hdmi_infoframe_type type,
371 const void *frame, ssize_t len)
373 const uint32_t *data = frame;
374 struct drm_device *dev = encoder->dev;
375 struct drm_i915_private *dev_priv = to_i915(dev);
376 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
377 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
380 u32 val = I915_READ(ctl_reg);
382 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
384 val &= ~hsw_infoframe_enable(type);
385 I915_WRITE(ctl_reg, val);
388 for (i = 0; i < len; i += 4) {
389 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
390 type, i >> 2), *data);
393 /* Write every possible data byte to force correct ECC calculation. */
394 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
395 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
399 val |= hsw_infoframe_enable(type);
400 I915_WRITE(ctl_reg, val);
401 POSTING_READ(ctl_reg);
404 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
405 const struct intel_crtc_state *pipe_config)
407 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
408 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
410 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
411 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
412 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
416 * The data we write to the DIP data buffer registers is 1 byte bigger than the
417 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
418 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
419 * used for both technologies.
421 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
422 * DW1: DB3 | DB2 | DB1 | DB0
423 * DW2: DB7 | DB6 | DB5 | DB4
426 * (HB is Header Byte, DB is Data Byte)
428 * The hdmi pack() functions don't know about that hardware specific hole so we
429 * trick them by giving an offset into the buffer and moving back the header
432 static void intel_write_infoframe(struct drm_encoder *encoder,
433 const struct intel_crtc_state *crtc_state,
434 union hdmi_infoframe *frame)
436 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
437 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
440 /* see comment above for the reason for this offset */
441 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
445 /* Insert the 'hole' (see big comment above) at position 3 */
446 buffer[0] = buffer[1];
447 buffer[1] = buffer[2];
448 buffer[2] = buffer[3];
452 intel_hdmi->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
455 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
456 const struct intel_crtc_state *crtc_state)
458 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
459 const struct drm_display_mode *adjusted_mode =
460 &crtc_state->base.adjusted_mode;
461 union hdmi_infoframe frame;
464 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
467 DRM_ERROR("couldn't fill AVI infoframe\n");
471 drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
472 crtc_state->limited_color_range ?
473 HDMI_QUANTIZATION_RANGE_LIMITED :
474 HDMI_QUANTIZATION_RANGE_FULL,
475 intel_hdmi->rgb_quant_range_selectable);
477 intel_write_infoframe(encoder, crtc_state, &frame);
480 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder,
481 const struct intel_crtc_state *crtc_state)
483 union hdmi_infoframe frame;
486 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
488 DRM_ERROR("couldn't fill SPD infoframe\n");
492 frame.spd.sdi = HDMI_SPD_SDI_PC;
494 intel_write_infoframe(encoder, crtc_state, &frame);
498 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
499 const struct intel_crtc_state *crtc_state)
501 union hdmi_infoframe frame;
504 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
505 &crtc_state->base.adjusted_mode);
509 intel_write_infoframe(encoder, crtc_state, &frame);
512 static void g4x_set_infoframes(struct drm_encoder *encoder,
514 const struct intel_crtc_state *crtc_state,
515 const struct drm_connector_state *conn_state)
517 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
518 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
519 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
520 i915_reg_t reg = VIDEO_DIP_CTL;
521 u32 val = I915_READ(reg);
522 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
524 assert_hdmi_port_disabled(intel_hdmi);
526 /* If the registers were not initialized yet, they might be zeroes,
527 * which means we're selecting the AVI DIP and we're setting its
528 * frequency to once. This seems to really confuse the HW and make
529 * things stop working (the register spec says the AVI always needs to
530 * be sent every VSync). So here we avoid writing to the register more
531 * than we need and also explicitly select the AVI DIP and explicitly
532 * set its frequency to every VSync. Avoiding to write it twice seems to
533 * be enough to solve the problem, but being defensive shouldn't hurt us
535 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
538 if (!(val & VIDEO_DIP_ENABLE))
540 if (port != (val & VIDEO_DIP_PORT_MASK)) {
541 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
542 (val & VIDEO_DIP_PORT_MASK) >> 29);
545 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
546 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
547 I915_WRITE(reg, val);
552 if (port != (val & VIDEO_DIP_PORT_MASK)) {
553 if (val & VIDEO_DIP_ENABLE) {
554 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
555 (val & VIDEO_DIP_PORT_MASK) >> 29);
558 val &= ~VIDEO_DIP_PORT_MASK;
562 val |= VIDEO_DIP_ENABLE;
563 val &= ~(VIDEO_DIP_ENABLE_AVI |
564 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
566 I915_WRITE(reg, val);
569 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
570 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
571 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
574 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
576 struct drm_connector *connector = conn_state->connector;
579 * HDMI cloning is only supported on g4x which doesn't
580 * support deep color or GCP infoframes anyway so no
581 * need to worry about multiple HDMI sinks here.
584 return connector->display_info.bpc > 8;
588 * Determine if default_phase=1 can be indicated in the GCP infoframe.
590 * From HDMI specification 1.4a:
591 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
592 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
593 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
594 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
597 static bool gcp_default_phase_possible(int pipe_bpp,
598 const struct drm_display_mode *mode)
600 unsigned int pixels_per_group;
604 /* 4 pixels in 5 clocks */
605 pixels_per_group = 4;
608 /* 2 pixels in 3 clocks */
609 pixels_per_group = 2;
612 /* 1 pixel in 2 clocks */
613 pixels_per_group = 1;
616 /* phase information not relevant for 8bpc */
620 return mode->crtc_hdisplay % pixels_per_group == 0 &&
621 mode->crtc_htotal % pixels_per_group == 0 &&
622 mode->crtc_hblank_start % pixels_per_group == 0 &&
623 mode->crtc_hblank_end % pixels_per_group == 0 &&
624 mode->crtc_hsync_start % pixels_per_group == 0 &&
625 mode->crtc_hsync_end % pixels_per_group == 0 &&
626 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
627 mode->crtc_htotal/2 % pixels_per_group == 0);
630 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder,
631 const struct intel_crtc_state *crtc_state,
632 const struct drm_connector_state *conn_state)
634 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
635 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
639 if (HAS_DDI(dev_priv))
640 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
641 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
642 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
643 else if (HAS_PCH_SPLIT(dev_priv))
644 reg = TVIDEO_DIP_GCP(crtc->pipe);
648 /* Indicate color depth whenever the sink supports deep color */
649 if (hdmi_sink_is_deep_color(conn_state))
650 val |= GCP_COLOR_INDICATION;
652 /* Enable default_phase whenever the display mode is suitably aligned */
653 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
654 &crtc_state->base.adjusted_mode))
655 val |= GCP_DEFAULT_PHASE_ENABLE;
657 I915_WRITE(reg, val);
662 static void ibx_set_infoframes(struct drm_encoder *encoder,
664 const struct intel_crtc_state *crtc_state,
665 const struct drm_connector_state *conn_state)
667 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
669 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
670 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
671 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
672 u32 val = I915_READ(reg);
673 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
675 assert_hdmi_port_disabled(intel_hdmi);
677 /* See the big comment in g4x_set_infoframes() */
678 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
681 if (!(val & VIDEO_DIP_ENABLE))
683 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
684 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
685 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
686 I915_WRITE(reg, val);
691 if (port != (val & VIDEO_DIP_PORT_MASK)) {
692 WARN(val & VIDEO_DIP_ENABLE,
693 "DIP already enabled on port %c\n",
694 (val & VIDEO_DIP_PORT_MASK) >> 29);
695 val &= ~VIDEO_DIP_PORT_MASK;
699 val |= VIDEO_DIP_ENABLE;
700 val &= ~(VIDEO_DIP_ENABLE_AVI |
701 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
702 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
704 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
705 val |= VIDEO_DIP_ENABLE_GCP;
707 I915_WRITE(reg, val);
710 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
711 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
712 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
715 static void cpt_set_infoframes(struct drm_encoder *encoder,
717 const struct intel_crtc_state *crtc_state,
718 const struct drm_connector_state *conn_state)
720 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
722 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
723 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
724 u32 val = I915_READ(reg);
726 assert_hdmi_port_disabled(intel_hdmi);
728 /* See the big comment in g4x_set_infoframes() */
729 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
732 if (!(val & VIDEO_DIP_ENABLE))
734 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
735 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
736 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
737 I915_WRITE(reg, val);
742 /* Set both together, unset both together: see the spec. */
743 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
744 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
745 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
747 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
748 val |= VIDEO_DIP_ENABLE_GCP;
750 I915_WRITE(reg, val);
753 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
754 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
755 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
758 static void vlv_set_infoframes(struct drm_encoder *encoder,
760 const struct intel_crtc_state *crtc_state,
761 const struct drm_connector_state *conn_state)
763 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
764 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
766 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
767 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
768 u32 val = I915_READ(reg);
769 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
771 assert_hdmi_port_disabled(intel_hdmi);
773 /* See the big comment in g4x_set_infoframes() */
774 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
777 if (!(val & VIDEO_DIP_ENABLE))
779 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
780 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
781 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
782 I915_WRITE(reg, val);
787 if (port != (val & VIDEO_DIP_PORT_MASK)) {
788 WARN(val & VIDEO_DIP_ENABLE,
789 "DIP already enabled on port %c\n",
790 (val & VIDEO_DIP_PORT_MASK) >> 29);
791 val &= ~VIDEO_DIP_PORT_MASK;
795 val |= VIDEO_DIP_ENABLE;
796 val &= ~(VIDEO_DIP_ENABLE_AVI |
797 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
798 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
800 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
801 val |= VIDEO_DIP_ENABLE_GCP;
803 I915_WRITE(reg, val);
806 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
807 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
808 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
811 static void hsw_set_infoframes(struct drm_encoder *encoder,
813 const struct intel_crtc_state *crtc_state,
814 const struct drm_connector_state *conn_state)
816 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
817 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
818 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
819 u32 val = I915_READ(reg);
821 assert_hdmi_port_disabled(intel_hdmi);
823 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
824 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
825 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
828 I915_WRITE(reg, val);
833 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
834 val |= VIDEO_DIP_ENABLE_GCP_HSW;
836 I915_WRITE(reg, val);
839 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
840 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
841 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
844 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
846 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
847 struct i2c_adapter *adapter =
848 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
850 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
853 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
854 enable ? "Enabling" : "Disabling");
856 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
860 static void intel_hdmi_prepare(struct intel_encoder *encoder,
861 const struct intel_crtc_state *crtc_state)
863 struct drm_device *dev = encoder->base.dev;
864 struct drm_i915_private *dev_priv = to_i915(dev);
865 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
866 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
867 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
870 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
872 hdmi_val = SDVO_ENCODING_HDMI;
873 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
874 hdmi_val |= HDMI_COLOR_RANGE_16_235;
875 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
876 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
877 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
878 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
880 if (crtc_state->pipe_bpp > 24)
881 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
883 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
885 if (crtc_state->has_hdmi_sink)
886 hdmi_val |= HDMI_MODE_SELECT_HDMI;
888 if (HAS_PCH_CPT(dev_priv))
889 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
890 else if (IS_CHERRYVIEW(dev_priv))
891 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
893 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
895 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
896 POSTING_READ(intel_hdmi->hdmi_reg);
899 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
902 struct drm_device *dev = encoder->base.dev;
903 struct drm_i915_private *dev_priv = to_i915(dev);
904 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
905 enum intel_display_power_domain power_domain;
909 power_domain = intel_display_port_power_domain(encoder);
910 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
915 tmp = I915_READ(intel_hdmi->hdmi_reg);
917 if (!(tmp & SDVO_ENABLE))
920 if (HAS_PCH_CPT(dev_priv))
921 *pipe = PORT_TO_PIPE_CPT(tmp);
922 else if (IS_CHERRYVIEW(dev_priv))
923 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
925 *pipe = PORT_TO_PIPE(tmp);
930 intel_display_power_put(dev_priv, power_domain);
935 static void intel_hdmi_get_config(struct intel_encoder *encoder,
936 struct intel_crtc_state *pipe_config)
938 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
939 struct drm_device *dev = encoder->base.dev;
940 struct drm_i915_private *dev_priv = to_i915(dev);
944 tmp = I915_READ(intel_hdmi->hdmi_reg);
946 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
947 flags |= DRM_MODE_FLAG_PHSYNC;
949 flags |= DRM_MODE_FLAG_NHSYNC;
951 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
952 flags |= DRM_MODE_FLAG_PVSYNC;
954 flags |= DRM_MODE_FLAG_NVSYNC;
956 if (tmp & HDMI_MODE_SELECT_HDMI)
957 pipe_config->has_hdmi_sink = true;
959 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
960 pipe_config->has_infoframe = true;
962 if (tmp & SDVO_AUDIO_ENABLE)
963 pipe_config->has_audio = true;
965 if (!HAS_PCH_SPLIT(dev_priv) &&
966 tmp & HDMI_COLOR_RANGE_16_235)
967 pipe_config->limited_color_range = true;
969 pipe_config->base.adjusted_mode.flags |= flags;
971 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
972 dotclock = pipe_config->port_clock * 2 / 3;
974 dotclock = pipe_config->port_clock;
976 if (pipe_config->pixel_multiplier)
977 dotclock /= pipe_config->pixel_multiplier;
979 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
981 pipe_config->lane_count = 4;
984 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
985 struct intel_crtc_state *pipe_config,
986 struct drm_connector_state *conn_state)
988 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
990 WARN_ON(!pipe_config->has_hdmi_sink);
991 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
992 pipe_name(crtc->pipe));
993 intel_audio_codec_enable(encoder, pipe_config, conn_state);
996 static void g4x_enable_hdmi(struct intel_encoder *encoder,
997 struct intel_crtc_state *pipe_config,
998 struct drm_connector_state *conn_state)
1000 struct drm_device *dev = encoder->base.dev;
1001 struct drm_i915_private *dev_priv = to_i915(dev);
1002 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1005 temp = I915_READ(intel_hdmi->hdmi_reg);
1007 temp |= SDVO_ENABLE;
1008 if (pipe_config->has_audio)
1009 temp |= SDVO_AUDIO_ENABLE;
1011 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1012 POSTING_READ(intel_hdmi->hdmi_reg);
1014 if (pipe_config->has_audio)
1015 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1018 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1019 struct intel_crtc_state *pipe_config,
1020 struct drm_connector_state *conn_state)
1022 struct drm_device *dev = encoder->base.dev;
1023 struct drm_i915_private *dev_priv = to_i915(dev);
1024 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1027 temp = I915_READ(intel_hdmi->hdmi_reg);
1029 temp |= SDVO_ENABLE;
1030 if (pipe_config->has_audio)
1031 temp |= SDVO_AUDIO_ENABLE;
1034 * HW workaround, need to write this twice for issue
1035 * that may result in first write getting masked.
1037 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1038 POSTING_READ(intel_hdmi->hdmi_reg);
1039 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1040 POSTING_READ(intel_hdmi->hdmi_reg);
1043 * HW workaround, need to toggle enable bit off and on
1044 * for 12bpc with pixel repeat.
1046 * FIXME: BSpec says this should be done at the end of
1047 * of the modeset sequence, so not sure if this isn't too soon.
1049 if (pipe_config->pipe_bpp > 24 &&
1050 pipe_config->pixel_multiplier > 1) {
1051 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1052 POSTING_READ(intel_hdmi->hdmi_reg);
1055 * HW workaround, need to write this twice for issue
1056 * that may result in first write getting masked.
1058 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1059 POSTING_READ(intel_hdmi->hdmi_reg);
1060 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1061 POSTING_READ(intel_hdmi->hdmi_reg);
1064 if (pipe_config->has_audio)
1065 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1068 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1069 struct intel_crtc_state *pipe_config,
1070 struct drm_connector_state *conn_state)
1072 struct drm_device *dev = encoder->base.dev;
1073 struct drm_i915_private *dev_priv = to_i915(dev);
1074 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1075 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1076 enum pipe pipe = crtc->pipe;
1079 temp = I915_READ(intel_hdmi->hdmi_reg);
1081 temp |= SDVO_ENABLE;
1082 if (pipe_config->has_audio)
1083 temp |= SDVO_AUDIO_ENABLE;
1086 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1088 * The procedure for 12bpc is as follows:
1089 * 1. disable HDMI clock gating
1090 * 2. enable HDMI with 8bpc
1091 * 3. enable HDMI with 12bpc
1092 * 4. enable HDMI clock gating
1095 if (pipe_config->pipe_bpp > 24) {
1096 I915_WRITE(TRANS_CHICKEN1(pipe),
1097 I915_READ(TRANS_CHICKEN1(pipe)) |
1098 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1100 temp &= ~SDVO_COLOR_FORMAT_MASK;
1101 temp |= SDVO_COLOR_FORMAT_8bpc;
1104 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1105 POSTING_READ(intel_hdmi->hdmi_reg);
1107 if (pipe_config->pipe_bpp > 24) {
1108 temp &= ~SDVO_COLOR_FORMAT_MASK;
1109 temp |= HDMI_COLOR_FORMAT_12bpc;
1111 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1112 POSTING_READ(intel_hdmi->hdmi_reg);
1114 I915_WRITE(TRANS_CHICKEN1(pipe),
1115 I915_READ(TRANS_CHICKEN1(pipe)) &
1116 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1119 if (pipe_config->has_audio)
1120 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1123 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1124 struct intel_crtc_state *pipe_config,
1125 struct drm_connector_state *conn_state)
1129 static void intel_disable_hdmi(struct intel_encoder *encoder,
1130 struct intel_crtc_state *old_crtc_state,
1131 struct drm_connector_state *old_conn_state)
1133 struct drm_device *dev = encoder->base.dev;
1134 struct drm_i915_private *dev_priv = to_i915(dev);
1135 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1136 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1139 temp = I915_READ(intel_hdmi->hdmi_reg);
1141 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1142 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1143 POSTING_READ(intel_hdmi->hdmi_reg);
1146 * HW workaround for IBX, we need to move the port
1147 * to transcoder A after disabling it to allow the
1148 * matching DP port to be enabled on transcoder A.
1150 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1152 * We get CPU/PCH FIFO underruns on the other pipe when
1153 * doing the workaround. Sweep them under the rug.
1155 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1156 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1158 temp &= ~SDVO_PIPE_B_SELECT;
1159 temp |= SDVO_ENABLE;
1161 * HW workaround, need to write this twice for issue
1162 * that may result in first write getting masked.
1164 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1165 POSTING_READ(intel_hdmi->hdmi_reg);
1166 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1167 POSTING_READ(intel_hdmi->hdmi_reg);
1169 temp &= ~SDVO_ENABLE;
1170 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1171 POSTING_READ(intel_hdmi->hdmi_reg);
1173 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1174 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1175 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1178 intel_hdmi->set_infoframes(&encoder->base, false, old_crtc_state, old_conn_state);
1180 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1183 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1184 struct intel_crtc_state *old_crtc_state,
1185 struct drm_connector_state *old_conn_state)
1187 if (old_crtc_state->has_audio)
1188 intel_audio_codec_disable(encoder);
1190 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1193 static void pch_disable_hdmi(struct intel_encoder *encoder,
1194 struct intel_crtc_state *old_crtc_state,
1195 struct drm_connector_state *old_conn_state)
1197 if (old_crtc_state->has_audio)
1198 intel_audio_codec_disable(encoder);
1201 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1202 struct intel_crtc_state *old_crtc_state,
1203 struct drm_connector_state *old_conn_state)
1205 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1208 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
1210 if (IS_G4X(dev_priv))
1212 else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
1218 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1219 bool respect_downstream_limits)
1221 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1222 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
1224 if (respect_downstream_limits) {
1225 struct intel_connector *connector = hdmi->attached_connector;
1226 const struct drm_display_info *info = &connector->base.display_info;
1228 if (hdmi->dp_dual_mode.max_tmds_clock)
1229 max_tmds_clock = min(max_tmds_clock,
1230 hdmi->dp_dual_mode.max_tmds_clock);
1232 if (info->max_tmds_clock)
1233 max_tmds_clock = min(max_tmds_clock,
1234 info->max_tmds_clock);
1235 else if (!hdmi->has_hdmi_sink)
1236 max_tmds_clock = min(max_tmds_clock, 165000);
1239 return max_tmds_clock;
1242 static enum drm_mode_status
1243 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1244 int clock, bool respect_downstream_limits)
1246 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1249 return MODE_CLOCK_LOW;
1250 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits))
1251 return MODE_CLOCK_HIGH;
1253 /* BXT DPLL can't generate 223-240 MHz */
1254 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1255 return MODE_CLOCK_RANGE;
1257 /* CHV DPLL can't generate 216-240 MHz */
1258 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1259 return MODE_CLOCK_RANGE;
1264 static enum drm_mode_status
1265 intel_hdmi_mode_valid(struct drm_connector *connector,
1266 struct drm_display_mode *mode)
1268 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1269 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1270 struct drm_i915_private *dev_priv = to_i915(dev);
1271 enum drm_mode_status status;
1273 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1275 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1276 return MODE_NO_DBLESCAN;
1278 clock = mode->clock;
1280 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1283 if (clock > max_dotclk)
1284 return MODE_CLOCK_HIGH;
1286 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1289 /* check if we can do 8bpc */
1290 status = hdmi_port_clock_valid(hdmi, clock, true);
1292 /* if we can't do 8bpc we may still be able to do 12bpc */
1293 if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK)
1294 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1299 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1301 struct drm_device *dev = crtc_state->base.crtc->dev;
1303 if (HAS_GMCH_DISPLAY(to_i915(dev)))
1307 * HDMI 12bpc affects the clocks, so it's only possible
1308 * when not cloning with other encoder types.
1310 return crtc_state->output_types == 1 << INTEL_OUTPUT_HDMI;
1313 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1314 struct intel_crtc_state *pipe_config,
1315 struct drm_connector_state *conn_state)
1317 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1318 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1319 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1320 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1321 int clock_12bpc = clock_8bpc * 3 / 2;
1324 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1326 if (pipe_config->has_hdmi_sink)
1327 pipe_config->has_infoframe = true;
1329 if (intel_hdmi->color_range_auto) {
1330 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1331 pipe_config->limited_color_range =
1332 pipe_config->has_hdmi_sink &&
1333 drm_default_rgb_quant_range(adjusted_mode) ==
1334 HDMI_QUANTIZATION_RANGE_LIMITED;
1336 pipe_config->limited_color_range =
1337 intel_hdmi->limited_color_range;
1340 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1341 pipe_config->pixel_multiplier = 2;
1346 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1347 pipe_config->has_pch_encoder = true;
1349 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1350 pipe_config->has_audio = true;
1353 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1354 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1355 * outputs. We also need to check that the higher clock still fits
1358 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1359 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK &&
1360 hdmi_12bpc_possible(pipe_config)) {
1361 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1364 /* Need to adjust the port link by 1.5x for 12bpc. */
1365 pipe_config->port_clock = clock_12bpc;
1367 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1370 pipe_config->port_clock = clock_8bpc;
1373 if (!pipe_config->bw_constrained) {
1374 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1375 pipe_config->pipe_bpp = desired_bpp;
1378 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1379 false) != MODE_OK) {
1380 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1384 /* Set user selected PAR to incoming mode's member */
1385 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1387 pipe_config->lane_count = 4;
1393 intel_hdmi_unset_edid(struct drm_connector *connector)
1395 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1397 intel_hdmi->has_hdmi_sink = false;
1398 intel_hdmi->has_audio = false;
1399 intel_hdmi->rgb_quant_range_selectable = false;
1401 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1402 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1404 kfree(to_intel_connector(connector)->detect_edid);
1405 to_intel_connector(connector)->detect_edid = NULL;
1409 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1411 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1412 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1413 enum port port = hdmi_to_dig_port(hdmi)->port;
1414 struct i2c_adapter *adapter =
1415 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1416 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1419 * Type 1 DVI adaptors are not required to implement any
1420 * registers, so we can't always detect their presence.
1421 * Ideally we should be able to check the state of the
1422 * CONFIG1 pin, but no such luck on our hardware.
1424 * The only method left to us is to check the VBT to see
1425 * if the port is a dual mode capable DP port. But let's
1426 * only do that when we sucesfully read the EDID, to avoid
1427 * confusing log messages about DP dual mode adaptors when
1428 * there's nothing connected to the port.
1430 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1432 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1433 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1434 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1436 type = DRM_DP_DUAL_MODE_NONE;
1440 if (type == DRM_DP_DUAL_MODE_NONE)
1443 hdmi->dp_dual_mode.type = type;
1444 hdmi->dp_dual_mode.max_tmds_clock =
1445 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1447 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1448 drm_dp_get_dual_mode_type_name(type),
1449 hdmi->dp_dual_mode.max_tmds_clock);
1453 intel_hdmi_set_edid(struct drm_connector *connector)
1455 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1456 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1458 bool connected = false;
1460 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1462 edid = drm_get_edid(connector,
1463 intel_gmbus_get_adapter(dev_priv,
1464 intel_hdmi->ddc_bus));
1466 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1468 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1470 to_intel_connector(connector)->detect_edid = edid;
1471 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1472 intel_hdmi->rgb_quant_range_selectable =
1473 drm_rgb_quant_range_selectable(edid);
1475 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1476 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1477 intel_hdmi->has_audio =
1478 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1480 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1481 intel_hdmi->has_hdmi_sink =
1482 drm_detect_hdmi_monitor(edid);
1490 static enum drm_connector_status
1491 intel_hdmi_detect(struct drm_connector *connector, bool force)
1493 enum drm_connector_status status;
1494 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1496 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1497 connector->base.id, connector->name);
1499 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1501 intel_hdmi_unset_edid(connector);
1503 if (intel_hdmi_set_edid(connector)) {
1504 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1506 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1507 status = connector_status_connected;
1509 status = connector_status_disconnected;
1511 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1517 intel_hdmi_force(struct drm_connector *connector)
1519 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1521 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1522 connector->base.id, connector->name);
1524 intel_hdmi_unset_edid(connector);
1526 if (connector->status != connector_status_connected)
1529 intel_hdmi_set_edid(connector);
1530 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1533 static int intel_hdmi_get_modes(struct drm_connector *connector)
1537 edid = to_intel_connector(connector)->detect_edid;
1541 return intel_connector_update_modes(connector, edid);
1545 intel_hdmi_detect_audio(struct drm_connector *connector)
1547 bool has_audio = false;
1550 edid = to_intel_connector(connector)->detect_edid;
1551 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1552 has_audio = drm_detect_monitor_audio(edid);
1558 intel_hdmi_set_property(struct drm_connector *connector,
1559 struct drm_property *property,
1562 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1563 struct intel_digital_port *intel_dig_port =
1564 hdmi_to_dig_port(intel_hdmi);
1565 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1568 ret = drm_object_property_set_value(&connector->base, property, val);
1572 if (property == dev_priv->force_audio_property) {
1573 enum hdmi_force_audio i = val;
1576 if (i == intel_hdmi->force_audio)
1579 intel_hdmi->force_audio = i;
1581 if (i == HDMI_AUDIO_AUTO)
1582 has_audio = intel_hdmi_detect_audio(connector);
1584 has_audio = (i == HDMI_AUDIO_ON);
1586 if (i == HDMI_AUDIO_OFF_DVI)
1587 intel_hdmi->has_hdmi_sink = 0;
1589 intel_hdmi->has_audio = has_audio;
1593 if (property == dev_priv->broadcast_rgb_property) {
1594 bool old_auto = intel_hdmi->color_range_auto;
1595 bool old_range = intel_hdmi->limited_color_range;
1598 case INTEL_BROADCAST_RGB_AUTO:
1599 intel_hdmi->color_range_auto = true;
1601 case INTEL_BROADCAST_RGB_FULL:
1602 intel_hdmi->color_range_auto = false;
1603 intel_hdmi->limited_color_range = false;
1605 case INTEL_BROADCAST_RGB_LIMITED:
1606 intel_hdmi->color_range_auto = false;
1607 intel_hdmi->limited_color_range = true;
1613 if (old_auto == intel_hdmi->color_range_auto &&
1614 old_range == intel_hdmi->limited_color_range)
1620 if (property == connector->dev->mode_config.aspect_ratio_property) {
1622 case DRM_MODE_PICTURE_ASPECT_NONE:
1623 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1625 case DRM_MODE_PICTURE_ASPECT_4_3:
1626 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1628 case DRM_MODE_PICTURE_ASPECT_16_9:
1629 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1640 if (intel_dig_port->base.base.crtc)
1641 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1646 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1647 struct intel_crtc_state *pipe_config,
1648 struct drm_connector_state *conn_state)
1650 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1652 intel_hdmi_prepare(encoder, pipe_config);
1654 intel_hdmi->set_infoframes(&encoder->base,
1655 pipe_config->has_hdmi_sink,
1656 pipe_config, conn_state);
1659 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1660 struct intel_crtc_state *pipe_config,
1661 struct drm_connector_state *conn_state)
1663 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1664 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1665 struct drm_device *dev = encoder->base.dev;
1666 struct drm_i915_private *dev_priv = to_i915(dev);
1668 vlv_phy_pre_encoder_enable(encoder);
1671 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1674 intel_hdmi->set_infoframes(&encoder->base,
1675 pipe_config->has_hdmi_sink,
1676 pipe_config, conn_state);
1678 g4x_enable_hdmi(encoder, pipe_config, conn_state);
1680 vlv_wait_port_ready(dev_priv, dport, 0x0);
1683 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1684 struct intel_crtc_state *pipe_config,
1685 struct drm_connector_state *conn_state)
1687 intel_hdmi_prepare(encoder, pipe_config);
1689 vlv_phy_pre_pll_enable(encoder);
1692 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1693 struct intel_crtc_state *pipe_config,
1694 struct drm_connector_state *conn_state)
1696 intel_hdmi_prepare(encoder, pipe_config);
1698 chv_phy_pre_pll_enable(encoder);
1701 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
1702 struct intel_crtc_state *old_crtc_state,
1703 struct drm_connector_state *old_conn_state)
1705 chv_phy_post_pll_disable(encoder);
1708 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
1709 struct intel_crtc_state *old_crtc_state,
1710 struct drm_connector_state *old_conn_state)
1712 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1713 vlv_phy_reset_lanes(encoder);
1716 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
1717 struct intel_crtc_state *old_crtc_state,
1718 struct drm_connector_state *old_conn_state)
1720 struct drm_device *dev = encoder->base.dev;
1721 struct drm_i915_private *dev_priv = to_i915(dev);
1723 mutex_lock(&dev_priv->sb_lock);
1725 /* Assert data lane reset */
1726 chv_data_lane_soft_reset(encoder, true);
1728 mutex_unlock(&dev_priv->sb_lock);
1731 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
1732 struct intel_crtc_state *pipe_config,
1733 struct drm_connector_state *conn_state)
1735 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1736 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1737 struct drm_device *dev = encoder->base.dev;
1738 struct drm_i915_private *dev_priv = to_i915(dev);
1740 chv_phy_pre_encoder_enable(encoder);
1742 /* FIXME: Program the support xxx V-dB */
1744 chv_set_phy_signal_level(encoder, 128, 102, false);
1746 intel_hdmi->set_infoframes(&encoder->base,
1747 pipe_config->has_hdmi_sink,
1748 pipe_config, conn_state);
1750 g4x_enable_hdmi(encoder, pipe_config, conn_state);
1752 vlv_wait_port_ready(dev_priv, dport, 0x0);
1754 /* Second common lane will stay alive on its own now */
1755 chv_phy_release_cl2_override(encoder);
1758 static void intel_hdmi_destroy(struct drm_connector *connector)
1760 kfree(to_intel_connector(connector)->detect_edid);
1761 drm_connector_cleanup(connector);
1765 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1766 .dpms = drm_atomic_helper_connector_dpms,
1767 .detect = intel_hdmi_detect,
1768 .force = intel_hdmi_force,
1769 .fill_modes = drm_helper_probe_single_connector_modes,
1770 .set_property = intel_hdmi_set_property,
1771 .atomic_get_property = intel_connector_atomic_get_property,
1772 .late_register = intel_connector_register,
1773 .early_unregister = intel_connector_unregister,
1774 .destroy = intel_hdmi_destroy,
1775 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1776 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1779 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1780 .get_modes = intel_hdmi_get_modes,
1781 .mode_valid = intel_hdmi_mode_valid,
1784 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1785 .destroy = intel_encoder_destroy,
1789 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1791 intel_attach_force_audio_property(connector);
1792 intel_attach_broadcast_rgb_property(connector);
1793 intel_hdmi->color_range_auto = true;
1794 intel_attach_aspect_ratio_property(connector);
1795 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1798 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
1801 const struct ddi_vbt_port_info *info =
1802 &dev_priv->vbt.ddi_port_info[port];
1805 if (info->alternate_ddc_pin) {
1806 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
1807 info->alternate_ddc_pin, port_name(port));
1808 return info->alternate_ddc_pin;
1813 if (IS_GEN9_LP(dev_priv))
1814 ddc_pin = GMBUS_PIN_1_BXT;
1816 ddc_pin = GMBUS_PIN_DPB;
1819 if (IS_GEN9_LP(dev_priv))
1820 ddc_pin = GMBUS_PIN_2_BXT;
1822 ddc_pin = GMBUS_PIN_DPC;
1825 if (IS_CHERRYVIEW(dev_priv))
1826 ddc_pin = GMBUS_PIN_DPD_CHV;
1828 ddc_pin = GMBUS_PIN_DPD;
1832 ddc_pin = GMBUS_PIN_DPB;
1836 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
1837 ddc_pin, port_name(port));
1842 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1843 struct intel_connector *intel_connector)
1845 struct drm_connector *connector = &intel_connector->base;
1846 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1847 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1848 struct drm_device *dev = intel_encoder->base.dev;
1849 struct drm_i915_private *dev_priv = to_i915(dev);
1850 enum port port = intel_dig_port->port;
1852 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
1855 if (WARN(intel_dig_port->max_lanes < 4,
1856 "Not enough lanes (%d) for HDMI on port %c\n",
1857 intel_dig_port->max_lanes, port_name(port)))
1860 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1861 DRM_MODE_CONNECTOR_HDMIA);
1862 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1864 connector->interlace_allowed = 1;
1865 connector->doublescan_allowed = 0;
1866 connector->stereo_allowed = 1;
1868 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
1873 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
1874 * interrupts to check the external panel connection.
1876 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1877 intel_encoder->hpd_pin = HPD_PORT_A;
1879 intel_encoder->hpd_pin = HPD_PORT_B;
1882 intel_encoder->hpd_pin = HPD_PORT_C;
1885 intel_encoder->hpd_pin = HPD_PORT_D;
1888 intel_encoder->hpd_pin = HPD_PORT_E;
1895 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1896 intel_hdmi->write_infoframe = vlv_write_infoframe;
1897 intel_hdmi->set_infoframes = vlv_set_infoframes;
1898 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1899 } else if (IS_G4X(dev_priv)) {
1900 intel_hdmi->write_infoframe = g4x_write_infoframe;
1901 intel_hdmi->set_infoframes = g4x_set_infoframes;
1902 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1903 } else if (HAS_DDI(dev_priv)) {
1904 intel_hdmi->write_infoframe = hsw_write_infoframe;
1905 intel_hdmi->set_infoframes = hsw_set_infoframes;
1906 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1907 } else if (HAS_PCH_IBX(dev_priv)) {
1908 intel_hdmi->write_infoframe = ibx_write_infoframe;
1909 intel_hdmi->set_infoframes = ibx_set_infoframes;
1910 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1912 intel_hdmi->write_infoframe = cpt_write_infoframe;
1913 intel_hdmi->set_infoframes = cpt_set_infoframes;
1914 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1917 if (HAS_DDI(dev_priv))
1918 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1920 intel_connector->get_hw_state = intel_connector_get_hw_state;
1922 intel_hdmi_add_properties(intel_hdmi, connector);
1924 intel_connector_attach_encoder(intel_connector, intel_encoder);
1925 intel_hdmi->attached_connector = intel_connector;
1927 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1928 * 0xd. Failure to do so will result in spurious interrupts being
1929 * generated on the port when a cable is not attached.
1931 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
1932 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1933 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1937 void intel_hdmi_init(struct drm_i915_private *dev_priv,
1938 i915_reg_t hdmi_reg, enum port port)
1940 struct intel_digital_port *intel_dig_port;
1941 struct intel_encoder *intel_encoder;
1942 struct intel_connector *intel_connector;
1944 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1945 if (!intel_dig_port)
1948 intel_connector = intel_connector_alloc();
1949 if (!intel_connector) {
1950 kfree(intel_dig_port);
1954 intel_encoder = &intel_dig_port->base;
1956 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
1957 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
1958 "HDMI %c", port_name(port));
1960 intel_encoder->compute_config = intel_hdmi_compute_config;
1961 if (HAS_PCH_SPLIT(dev_priv)) {
1962 intel_encoder->disable = pch_disable_hdmi;
1963 intel_encoder->post_disable = pch_post_disable_hdmi;
1965 intel_encoder->disable = g4x_disable_hdmi;
1967 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1968 intel_encoder->get_config = intel_hdmi_get_config;
1969 if (IS_CHERRYVIEW(dev_priv)) {
1970 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1971 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1972 intel_encoder->enable = vlv_enable_hdmi;
1973 intel_encoder->post_disable = chv_hdmi_post_disable;
1974 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
1975 } else if (IS_VALLEYVIEW(dev_priv)) {
1976 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1977 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1978 intel_encoder->enable = vlv_enable_hdmi;
1979 intel_encoder->post_disable = vlv_hdmi_post_disable;
1981 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1982 if (HAS_PCH_CPT(dev_priv))
1983 intel_encoder->enable = cpt_enable_hdmi;
1984 else if (HAS_PCH_IBX(dev_priv))
1985 intel_encoder->enable = ibx_enable_hdmi;
1987 intel_encoder->enable = g4x_enable_hdmi;
1990 intel_encoder->type = INTEL_OUTPUT_HDMI;
1991 intel_encoder->port = port;
1992 if (IS_CHERRYVIEW(dev_priv)) {
1994 intel_encoder->crtc_mask = 1 << 2;
1996 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1998 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2000 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2002 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2003 * to work on real hardware. And since g4x can send infoframes to
2004 * only one port anyway, nothing is lost by allowing it.
2006 if (IS_G4X(dev_priv))
2007 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2009 intel_dig_port->port = port;
2010 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2011 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2012 intel_dig_port->max_lanes = 4;
2014 intel_hdmi_init_connector(intel_dig_port, intel_connector);