2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_mocs.h"
140 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
194 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
195 (reg_state)[(pos)+1] = (val); \
198 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
199 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
200 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
201 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
204 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
205 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
206 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
210 ADVANCED_CONTEXT = 0,
215 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
216 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
217 LEGACY_64B_CONTEXT :\
221 FAULT_AND_HALT, /* Debug only */
223 FAULT_AND_CONTINUE /* Unsupported */
225 #define GEN8_CTX_ID_SHIFT 32
226 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
227 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
229 static int intel_lr_context_pin(struct intel_context *ctx,
230 struct intel_engine_cs *engine);
231 static void lrc_setup_hardware_status_page(struct intel_engine_cs *engine,
232 struct drm_i915_gem_object *default_ctx_obj);
236 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
238 * @enable_execlists: value of i915.enable_execlists module parameter.
240 * Only certain platforms support Execlists (the prerequisites being
241 * support for Logical Ring Contexts and Aliasing PPGTT or better).
243 * Return: 1 if Execlists is supported and has to be enabled.
245 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
247 WARN_ON(i915.enable_ppgtt == -1);
249 /* On platforms with execlist available, vGPU will only
250 * support execlist mode, no ring buffer mode.
252 if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
255 if (INTEL_INFO(dev)->gen >= 9)
258 if (enable_execlists == 0)
261 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
262 i915.use_mmio_flip >= 0)
269 logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
271 struct drm_device *dev = engine->dev;
273 if (IS_GEN8(dev) || IS_GEN9(dev))
274 engine->idle_lite_restore_wa = ~0;
276 engine->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
277 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
278 (engine->id == VCS || engine->id == VCS2);
280 engine->ctx_desc_template = GEN8_CTX_VALID;
281 engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) <<
282 GEN8_CTX_ADDRESSING_MODE_SHIFT;
284 engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
285 engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
287 /* TODO: WaDisableLiteRestore when we start using semaphore
288 * signalling between Command Streamers */
289 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
291 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
292 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
293 if (engine->disable_lite_restore_wa)
294 engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
298 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
299 * descriptor for a pinned context
301 * @ctx: Context to work on
302 * @ring: Engine the descriptor will be used with
304 * The context descriptor encodes various attributes of a context,
305 * including its GTT address and some flags. Because it's fairly
306 * expensive to calculate, we'll just do it once and cache the result,
307 * which remains valid until the context is unpinned.
309 * This is what a descriptor looks like, from LSB to MSB:
310 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
311 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
312 * bits 32-51: ctx ID, a globally unique tag (the LRCA again!)
313 * bits 52-63: reserved, may encode the engine ID (for GuC)
316 intel_lr_context_descriptor_update(struct intel_context *ctx,
317 struct intel_engine_cs *engine)
321 lrca = ctx->engine[engine->id].lrc_vma->node.start +
322 LRC_PPHWSP_PN * PAGE_SIZE;
324 desc = engine->ctx_desc_template; /* bits 0-11 */
325 desc |= lrca; /* bits 12-31 */
326 desc |= (lrca >> PAGE_SHIFT) << GEN8_CTX_ID_SHIFT; /* bits 32-51 */
328 ctx->engine[engine->id].lrc_desc = desc;
331 uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
332 struct intel_engine_cs *engine)
334 return ctx->engine[engine->id].lrc_desc;
338 * intel_execlists_ctx_id() - get the Execlists Context ID
339 * @ctx: Context to get the ID for
340 * @ring: Engine to get the ID for
342 * Do not confuse with ctx->id! Unfortunately we have a name overload
343 * here: the old context ID we pass to userspace as a handler so that
344 * they can refer to a context, and the new context ID we pass to the
345 * ELSP so that the GPU can inform us of the context status via
348 * The context ID is a portion of the context descriptor, so we can
349 * just extract the required part from the cached descriptor.
351 * Return: 20-bits globally unique context ID.
353 u32 intel_execlists_ctx_id(struct intel_context *ctx,
354 struct intel_engine_cs *engine)
356 return intel_lr_context_descriptor(ctx, engine) >> GEN8_CTX_ID_SHIFT;
359 static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
360 struct drm_i915_gem_request *rq1)
363 struct intel_engine_cs *engine = rq0->engine;
364 struct drm_device *dev = engine->dev;
365 struct drm_i915_private *dev_priv = dev->dev_private;
369 desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine);
370 rq1->elsp_submitted++;
375 desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine);
376 rq0->elsp_submitted++;
378 /* You must always write both descriptors in the order below. */
379 I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1]));
380 I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1]));
382 I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0]));
383 /* The context is automatically loaded after the following */
384 I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0]));
386 /* ELSP is a wo register, use another nearby reg for posting */
387 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine));
391 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
393 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
394 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
395 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
396 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
399 static void execlists_update_context(struct drm_i915_gem_request *rq)
401 struct intel_engine_cs *engine = rq->engine;
402 struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
403 uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state;
405 reg_state[CTX_RING_TAIL+1] = rq->tail;
407 /* True 32b PPGTT with dynamic page allocation: update PDP
408 * registers and point the unallocated PDPs to scratch page.
409 * PML4 is allocated during ppgtt init, so this is not needed
412 if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
413 execlists_update_context_pdps(ppgtt, reg_state);
416 static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
417 struct drm_i915_gem_request *rq1)
419 struct drm_i915_private *dev_priv = rq0->i915;
421 /* BUG_ON(!irqs_disabled()); */
423 execlists_update_context(rq0);
426 execlists_update_context(rq1);
428 spin_lock(&dev_priv->uncore.lock);
429 intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
431 execlists_elsp_write(rq0, rq1);
433 intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
434 spin_unlock(&dev_priv->uncore.lock);
437 static void execlists_context_unqueue(struct intel_engine_cs *engine)
439 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
440 struct drm_i915_gem_request *cursor, *tmp;
442 assert_spin_locked(&engine->execlist_lock);
445 * If irqs are not active generate a warning as batches that finish
446 * without the irqs may get lost and a GPU Hang may occur.
448 WARN_ON(!intel_irqs_enabled(engine->dev->dev_private));
450 /* Try to read in pairs */
451 list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue,
455 } else if (req0->ctx == cursor->ctx) {
456 /* Same ctx: ignore first request, as second request
457 * will update tail past first request's workload */
458 cursor->elsp_submitted = req0->elsp_submitted;
459 list_move_tail(&req0->execlist_link,
460 &engine->execlist_retired_req_list);
464 WARN_ON(req1->elsp_submitted);
472 if (req0->elsp_submitted & engine->idle_lite_restore_wa) {
474 * WaIdleLiteRestore: make sure we never cause a lite restore
477 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
478 * resubmit the request. See gen8_emit_request() for where we
479 * prepare the padding after the end of the request.
481 struct intel_ringbuffer *ringbuf;
483 ringbuf = req0->ctx->engine[engine->id].ringbuf;
485 req0->tail &= ringbuf->size - 1;
488 execlists_submit_requests(req0, req1);
492 execlists_check_remove_request(struct intel_engine_cs *engine, u32 request_id)
494 struct drm_i915_gem_request *head_req;
496 assert_spin_locked(&engine->execlist_lock);
498 head_req = list_first_entry_or_null(&engine->execlist_queue,
499 struct drm_i915_gem_request,
505 if (unlikely(intel_execlists_ctx_id(head_req->ctx, engine) != request_id))
508 WARN(head_req->elsp_submitted == 0, "Never submitted head request\n");
510 if (--head_req->elsp_submitted > 0)
513 list_move_tail(&head_req->execlist_link,
514 &engine->execlist_retired_req_list);
520 get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
523 struct drm_i915_private *dev_priv = engine->dev->dev_private;
526 read_pointer %= GEN8_CSB_ENTRIES;
528 status = I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine, read_pointer));
530 if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
533 *context_id = I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine,
540 * intel_lrc_irq_handler() - handle Context Switch interrupts
541 * @ring: Engine Command Streamer to handle.
543 * Check the unread Context Status Buffers and manage the submission of new
544 * contexts to the ELSP accordingly.
546 void intel_lrc_irq_handler(struct intel_engine_cs *engine)
548 struct drm_i915_private *dev_priv = engine->dev->dev_private;
550 unsigned int read_pointer, write_pointer;
551 u32 csb[GEN8_CSB_ENTRIES][2];
552 unsigned int csb_read = 0, i;
553 unsigned int submit_contexts = 0;
555 spin_lock(&dev_priv->uncore.lock);
556 intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
558 status_pointer = I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine));
560 read_pointer = engine->next_context_status_buffer;
561 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
562 if (read_pointer > write_pointer)
563 write_pointer += GEN8_CSB_ENTRIES;
565 while (read_pointer < write_pointer) {
566 if (WARN_ON_ONCE(csb_read == GEN8_CSB_ENTRIES))
568 csb[csb_read][0] = get_context_status(engine, ++read_pointer,
573 engine->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES;
575 /* Update the read pointer to the old write pointer. Manual ringbuffer
576 * management ftw </sarcasm> */
577 I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine),
578 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
579 engine->next_context_status_buffer << 8));
581 intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
582 spin_unlock(&dev_priv->uncore.lock);
584 spin_lock(&engine->execlist_lock);
586 for (i = 0; i < csb_read; i++) {
587 if (unlikely(csb[i][0] & GEN8_CTX_STATUS_PREEMPTED)) {
588 if (csb[i][0] & GEN8_CTX_STATUS_LITE_RESTORE) {
589 if (execlists_check_remove_request(engine, csb[i][1]))
590 WARN(1, "Lite Restored request removed from queue\n");
592 WARN(1, "Preemption without Lite Restore\n");
595 if (csb[i][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE |
596 GEN8_CTX_STATUS_ELEMENT_SWITCH))
598 execlists_check_remove_request(engine, csb[i][1]);
601 if (submit_contexts) {
602 if (!engine->disable_lite_restore_wa ||
603 (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE))
604 execlists_context_unqueue(engine);
607 spin_unlock(&engine->execlist_lock);
609 if (unlikely(submit_contexts > 2))
610 DRM_ERROR("More than two context complete events?\n");
613 static void execlists_context_queue(struct drm_i915_gem_request *request)
615 struct intel_engine_cs *engine = request->engine;
616 struct drm_i915_gem_request *cursor;
617 int num_elements = 0;
619 if (request->ctx != request->i915->kernel_context)
620 intel_lr_context_pin(request->ctx, engine);
622 i915_gem_request_reference(request);
624 spin_lock_irq(&engine->execlist_lock);
626 list_for_each_entry(cursor, &engine->execlist_queue, execlist_link)
627 if (++num_elements > 2)
630 if (num_elements > 2) {
631 struct drm_i915_gem_request *tail_req;
633 tail_req = list_last_entry(&engine->execlist_queue,
634 struct drm_i915_gem_request,
637 if (request->ctx == tail_req->ctx) {
638 WARN(tail_req->elsp_submitted != 0,
639 "More than 2 already-submitted reqs queued\n");
640 list_move_tail(&tail_req->execlist_link,
641 &engine->execlist_retired_req_list);
645 list_add_tail(&request->execlist_link, &engine->execlist_queue);
646 if (num_elements == 0)
647 execlists_context_unqueue(engine);
649 spin_unlock_irq(&engine->execlist_lock);
652 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
654 struct intel_engine_cs *engine = req->engine;
655 uint32_t flush_domains;
659 if (engine->gpu_caches_dirty)
660 flush_domains = I915_GEM_GPU_DOMAINS;
662 ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
666 engine->gpu_caches_dirty = false;
670 static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
671 struct list_head *vmas)
673 const unsigned other_rings = ~intel_engine_flag(req->engine);
674 struct i915_vma *vma;
675 uint32_t flush_domains = 0;
676 bool flush_chipset = false;
679 list_for_each_entry(vma, vmas, exec_list) {
680 struct drm_i915_gem_object *obj = vma->obj;
682 if (obj->active & other_rings) {
683 ret = i915_gem_object_sync(obj, req->engine, &req);
688 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
689 flush_chipset |= i915_gem_clflush_object(obj, false);
691 flush_domains |= obj->base.write_domain;
694 if (flush_domains & I915_GEM_DOMAIN_GTT)
697 /* Unconditionally invalidate gpu caches and ensure that we do flush
698 * any residual writes from the previous batch.
700 return logical_ring_invalidate_all_caches(req);
703 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
707 request->ringbuf = request->ctx->engine[request->engine->id].ringbuf;
709 if (i915.enable_guc_submission) {
711 * Check that the GuC has space for the request before
712 * going any further, as the i915_add_request() call
713 * later on mustn't fail ...
715 struct intel_guc *guc = &request->i915->guc;
717 ret = i915_guc_wq_check_space(guc->execbuf_client);
722 if (request->ctx != request->i915->kernel_context)
723 ret = intel_lr_context_pin(request->ctx, request->engine);
728 static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
731 struct intel_ringbuffer *ringbuf = req->ringbuf;
732 struct intel_engine_cs *engine = req->engine;
733 struct drm_i915_gem_request *target;
737 if (intel_ring_space(ringbuf) >= bytes)
740 /* The whole point of reserving space is to not wait! */
741 WARN_ON(ringbuf->reserved_in_use);
743 list_for_each_entry(target, &engine->request_list, list) {
745 * The request queue is per-engine, so can contain requests
746 * from multiple ringbuffers. Here, we must ignore any that
747 * aren't from the ringbuffer we're considering.
749 if (target->ringbuf != ringbuf)
752 /* Would completion of this request free enough space? */
753 space = __intel_ring_space(target->postfix, ringbuf->tail,
759 if (WARN_ON(&target->list == &engine->request_list))
762 ret = i915_wait_request(target);
766 ringbuf->space = space;
771 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
772 * @request: Request to advance the logical ringbuffer of.
774 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
775 * really happens during submission is that the context and current tail will be placed
776 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
777 * point, the tail *inside* the context is updated and the ELSP written to.
780 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
782 struct intel_ringbuffer *ringbuf = request->ringbuf;
783 struct drm_i915_private *dev_priv = request->i915;
784 struct intel_engine_cs *engine = request->engine;
786 intel_logical_ring_advance(ringbuf);
787 request->tail = ringbuf->tail;
790 * Here we add two extra NOOPs as padding to avoid
791 * lite restore of a context with HEAD==TAIL.
793 * Caller must reserve WA_TAIL_DWORDS for us!
795 intel_logical_ring_emit(ringbuf, MI_NOOP);
796 intel_logical_ring_emit(ringbuf, MI_NOOP);
797 intel_logical_ring_advance(ringbuf);
799 if (intel_engine_stopped(engine))
802 if (engine->last_context != request->ctx) {
803 if (engine->last_context)
804 intel_lr_context_unpin(engine->last_context, engine);
805 if (request->ctx != request->i915->kernel_context) {
806 intel_lr_context_pin(request->ctx, engine);
807 engine->last_context = request->ctx;
809 engine->last_context = NULL;
813 if (dev_priv->guc.execbuf_client)
814 i915_guc_submit(dev_priv->guc.execbuf_client, request);
816 execlists_context_queue(request);
821 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
823 uint32_t __iomem *virt;
824 int rem = ringbuf->size - ringbuf->tail;
826 virt = ringbuf->virtual_start + ringbuf->tail;
829 iowrite32(MI_NOOP, virt++);
832 intel_ring_update_space(ringbuf);
835 static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
837 struct intel_ringbuffer *ringbuf = req->ringbuf;
838 int remain_usable = ringbuf->effective_size - ringbuf->tail;
839 int remain_actual = ringbuf->size - ringbuf->tail;
840 int ret, total_bytes, wait_bytes = 0;
841 bool need_wrap = false;
843 if (ringbuf->reserved_in_use)
846 total_bytes = bytes + ringbuf->reserved_size;
848 if (unlikely(bytes > remain_usable)) {
850 * Not enough space for the basic request. So need to flush
851 * out the remainder and then wait for base + reserved.
853 wait_bytes = remain_actual + total_bytes;
856 if (unlikely(total_bytes > remain_usable)) {
858 * The base request will fit but the reserved space
859 * falls off the end. So only need to to wait for the
860 * reserved size after flushing out the remainder.
862 wait_bytes = remain_actual + ringbuf->reserved_size;
864 } else if (total_bytes > ringbuf->space) {
865 /* No wrapping required, just waiting. */
866 wait_bytes = total_bytes;
871 ret = logical_ring_wait_for_space(req, wait_bytes);
876 __wrap_ring_buffer(ringbuf);
883 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
885 * @req: The request to start some new work for
886 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
888 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
889 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
890 * and also preallocates a request (every workload submission is still mediated through
891 * requests, same as it did with legacy ringbuffer submission).
893 * Return: non-zero if the ringbuffer is not ready to be written to.
895 int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
897 struct drm_i915_private *dev_priv;
900 WARN_ON(req == NULL);
901 dev_priv = req->i915;
903 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
904 dev_priv->mm.interruptible);
908 ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t));
912 req->ringbuf->space -= num_dwords * sizeof(uint32_t);
916 int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
919 * The first call merely notes the reserve request and is common for
920 * all back ends. The subsequent localised _begin() call actually
921 * ensures that the reservation is available. Without the begin, if
922 * the request creator immediately submitted the request without
923 * adding any commands to it then there might not actually be
924 * sufficient room for the submission commands.
926 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
928 return intel_logical_ring_begin(request, 0);
932 * execlists_submission() - submit a batchbuffer for execution, Execlists style
935 * @ring: Engine Command Streamer to submit to.
936 * @ctx: Context to employ for this submission.
937 * @args: execbuffer call arguments.
938 * @vmas: list of vmas.
939 * @batch_obj: the batchbuffer to submit.
940 * @exec_start: batchbuffer start virtual address pointer.
941 * @dispatch_flags: translated execbuffer call flags.
943 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
944 * away the submission details of the execbuffer ioctl call.
946 * Return: non-zero if the submission fails.
948 int intel_execlists_submission(struct i915_execbuffer_params *params,
949 struct drm_i915_gem_execbuffer2 *args,
950 struct list_head *vmas)
952 struct drm_device *dev = params->dev;
953 struct intel_engine_cs *engine = params->engine;
954 struct drm_i915_private *dev_priv = dev->dev_private;
955 struct intel_ringbuffer *ringbuf = params->ctx->engine[engine->id].ringbuf;
961 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
962 instp_mask = I915_EXEC_CONSTANTS_MASK;
963 switch (instp_mode) {
964 case I915_EXEC_CONSTANTS_REL_GENERAL:
965 case I915_EXEC_CONSTANTS_ABSOLUTE:
966 case I915_EXEC_CONSTANTS_REL_SURFACE:
967 if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) {
968 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
972 if (instp_mode != dev_priv->relative_constants_mode) {
973 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
974 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
978 /* The HW changed the meaning on this bit on gen6 */
979 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
983 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
987 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
988 DRM_DEBUG("sol reset is gen7 only\n");
992 ret = execlists_move_to_gpu(params->request, vmas);
996 if (engine == &dev_priv->engine[RCS] &&
997 instp_mode != dev_priv->relative_constants_mode) {
998 ret = intel_logical_ring_begin(params->request, 4);
1002 intel_logical_ring_emit(ringbuf, MI_NOOP);
1003 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
1004 intel_logical_ring_emit_reg(ringbuf, INSTPM);
1005 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
1006 intel_logical_ring_advance(ringbuf);
1008 dev_priv->relative_constants_mode = instp_mode;
1011 exec_start = params->batch_obj_vm_offset +
1012 args->batch_start_offset;
1014 ret = engine->emit_bb_start(params->request, exec_start, params->dispatch_flags);
1018 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
1020 i915_gem_execbuffer_move_to_active(vmas, params->request);
1021 i915_gem_execbuffer_retire_commands(params);
1026 void intel_execlists_retire_requests(struct intel_engine_cs *engine)
1028 struct drm_i915_gem_request *req, *tmp;
1029 struct list_head retired_list;
1031 WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex));
1032 if (list_empty(&engine->execlist_retired_req_list))
1035 INIT_LIST_HEAD(&retired_list);
1036 spin_lock_irq(&engine->execlist_lock);
1037 list_replace_init(&engine->execlist_retired_req_list, &retired_list);
1038 spin_unlock_irq(&engine->execlist_lock);
1040 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
1041 struct intel_context *ctx = req->ctx;
1042 struct drm_i915_gem_object *ctx_obj =
1043 ctx->engine[engine->id].state;
1045 if (ctx_obj && (ctx != req->i915->kernel_context))
1046 intel_lr_context_unpin(ctx, engine);
1048 list_del(&req->execlist_link);
1049 i915_gem_request_unreference(req);
1053 void intel_logical_ring_stop(struct intel_engine_cs *engine)
1055 struct drm_i915_private *dev_priv = engine->dev->dev_private;
1058 if (!intel_engine_initialized(engine))
1061 ret = intel_engine_idle(engine);
1062 if (ret && !i915_reset_in_progress(&to_i915(engine->dev)->gpu_error))
1063 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1066 /* TODO: Is this correct with Execlists enabled? */
1067 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
1068 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
1069 DRM_ERROR("%s :timed out trying to stop ring\n", engine->name);
1072 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
1075 int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
1077 struct intel_engine_cs *engine = req->engine;
1080 if (!engine->gpu_caches_dirty)
1083 ret = engine->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
1087 engine->gpu_caches_dirty = false;
1091 static int intel_lr_context_do_pin(struct intel_context *ctx,
1092 struct intel_engine_cs *engine)
1094 struct drm_device *dev = engine->dev;
1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
1097 struct intel_ringbuffer *ringbuf = ctx->engine[engine->id].ringbuf;
1098 struct page *lrc_state_page;
1099 uint32_t *lrc_reg_state;
1102 WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex));
1104 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN,
1105 PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
1109 lrc_state_page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
1110 if (WARN_ON(!lrc_state_page)) {
1115 ret = intel_pin_and_map_ringbuffer_obj(engine->dev, ringbuf);
1119 ctx->engine[engine->id].lrc_vma = i915_gem_obj_to_ggtt(ctx_obj);
1120 intel_lr_context_descriptor_update(ctx, engine);
1121 lrc_reg_state = kmap(lrc_state_page);
1122 lrc_reg_state[CTX_RING_BUFFER_START+1] = ringbuf->vma->node.start;
1123 ctx->engine[engine->id].lrc_reg_state = lrc_reg_state;
1124 ctx_obj->dirty = true;
1126 /* Invalidate GuC TLB. */
1127 if (i915.enable_guc_submission)
1128 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
1133 i915_gem_object_ggtt_unpin(ctx_obj);
1138 static int intel_lr_context_pin(struct intel_context *ctx,
1139 struct intel_engine_cs *engine)
1143 if (ctx->engine[engine->id].pin_count++ == 0) {
1144 ret = intel_lr_context_do_pin(ctx, engine);
1146 goto reset_pin_count;
1148 i915_gem_context_reference(ctx);
1153 ctx->engine[engine->id].pin_count = 0;
1157 void intel_lr_context_unpin(struct intel_context *ctx,
1158 struct intel_engine_cs *engine)
1160 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
1162 WARN_ON(!mutex_is_locked(&ctx->i915->dev->struct_mutex));
1163 if (--ctx->engine[engine->id].pin_count == 0) {
1164 kunmap(kmap_to_page(ctx->engine[engine->id].lrc_reg_state));
1165 intel_unpin_ringbuffer_obj(ctx->engine[engine->id].ringbuf);
1166 i915_gem_object_ggtt_unpin(ctx_obj);
1167 ctx->engine[engine->id].lrc_vma = NULL;
1168 ctx->engine[engine->id].lrc_desc = 0;
1169 ctx->engine[engine->id].lrc_reg_state = NULL;
1171 i915_gem_context_unreference(ctx);
1175 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
1178 struct intel_engine_cs *engine = req->engine;
1179 struct intel_ringbuffer *ringbuf = req->ringbuf;
1180 struct drm_device *dev = engine->dev;
1181 struct drm_i915_private *dev_priv = dev->dev_private;
1182 struct i915_workarounds *w = &dev_priv->workarounds;
1187 engine->gpu_caches_dirty = true;
1188 ret = logical_ring_flush_all_caches(req);
1192 ret = intel_logical_ring_begin(req, w->count * 2 + 2);
1196 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1197 for (i = 0; i < w->count; i++) {
1198 intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr);
1199 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1201 intel_logical_ring_emit(ringbuf, MI_NOOP);
1203 intel_logical_ring_advance(ringbuf);
1205 engine->gpu_caches_dirty = true;
1206 ret = logical_ring_flush_all_caches(req);
1213 #define wa_ctx_emit(batch, index, cmd) \
1215 int __index = (index)++; \
1216 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1219 batch[__index] = (cmd); \
1222 #define wa_ctx_emit_reg(batch, index, reg) \
1223 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1226 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1227 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1228 * but there is a slight complication as this is applied in WA batch where the
1229 * values are only initialized once so we cannot take register value at the
1230 * beginning and reuse it further; hence we save its value to memory, upload a
1231 * constant value with bit21 set and then we restore it back with the saved value.
1232 * To simplify the WA, a constant value is formed by using the default value
1233 * of this register. This shouldn't be a problem because we are only modifying
1234 * it for a short period and this batch in non-premptible. We can ofcourse
1235 * use additional instructions that read the actual value of the register
1236 * at that time and set our bit of interest but it makes the WA complicated.
1238 * This WA is also required for Gen9 so extracting as a function avoids
1241 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
1242 uint32_t *const batch,
1245 uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
1248 * WaDisableLSQCROPERFforOCL:skl
1249 * This WA is implemented in skl_init_clock_gating() but since
1250 * this batch updates GEN8_L3SQCREG4 with default value we need to
1251 * set this bit here to retain the WA during flush.
1253 if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0))
1254 l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
1256 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
1257 MI_SRM_LRM_GLOBAL_GTT));
1258 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1259 wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
1260 wa_ctx_emit(batch, index, 0);
1262 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1263 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1264 wa_ctx_emit(batch, index, l3sqc4_flush);
1266 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1267 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
1268 PIPE_CONTROL_DC_FLUSH_ENABLE));
1269 wa_ctx_emit(batch, index, 0);
1270 wa_ctx_emit(batch, index, 0);
1271 wa_ctx_emit(batch, index, 0);
1272 wa_ctx_emit(batch, index, 0);
1274 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
1275 MI_SRM_LRM_GLOBAL_GTT));
1276 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1277 wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
1278 wa_ctx_emit(batch, index, 0);
1283 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
1285 uint32_t start_alignment)
1287 return wa_ctx->offset = ALIGN(offset, start_alignment);
1290 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
1292 uint32_t size_alignment)
1294 wa_ctx->size = offset - wa_ctx->offset;
1296 WARN(wa_ctx->size % size_alignment,
1297 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1298 wa_ctx->size, size_alignment);
1303 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1305 * @ring: only applicable for RCS
1306 * @wa_ctx: structure representing wa_ctx
1307 * offset: specifies start of the batch, should be cache-aligned. This is updated
1308 * with the offset value received as input.
1309 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1310 * @batch: page in which WA are loaded
1311 * @offset: This field specifies the start of the batch, it should be
1312 * cache-aligned otherwise it is adjusted accordingly.
1313 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1314 * initialized at the beginning and shared across all contexts but this field
1315 * helps us to have multiple batches at different offsets and select them based
1316 * on a criteria. At the moment this batch always start at the beginning of the page
1317 * and at this point we don't have multiple wa_ctx batch buffers.
1319 * The number of WA applied are not known at the beginning; we use this field
1320 * to return the no of DWORDS written.
1322 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1323 * so it adds NOOPs as padding to make it cacheline aligned.
1324 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1325 * makes a complete batch buffer.
1327 * Return: non-zero if we exceed the PAGE_SIZE limit.
1330 static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
1331 struct i915_wa_ctx_bb *wa_ctx,
1332 uint32_t *const batch,
1335 uint32_t scratch_addr;
1336 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1338 /* WaDisableCtxRestoreArbitration:bdw,chv */
1339 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1341 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1342 if (IS_BROADWELL(engine->dev)) {
1343 int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1349 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1350 /* Actual scratch location is at 128 bytes offset */
1351 scratch_addr = engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
1353 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1354 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1355 PIPE_CONTROL_GLOBAL_GTT_IVB |
1356 PIPE_CONTROL_CS_STALL |
1357 PIPE_CONTROL_QW_WRITE));
1358 wa_ctx_emit(batch, index, scratch_addr);
1359 wa_ctx_emit(batch, index, 0);
1360 wa_ctx_emit(batch, index, 0);
1361 wa_ctx_emit(batch, index, 0);
1363 /* Pad to end of cacheline */
1364 while (index % CACHELINE_DWORDS)
1365 wa_ctx_emit(batch, index, MI_NOOP);
1368 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1369 * execution depends on the length specified in terms of cache lines
1370 * in the register CTX_RCS_INDIRECT_CTX
1373 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1377 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1379 * @ring: only applicable for RCS
1380 * @wa_ctx: structure representing wa_ctx
1381 * offset: specifies start of the batch, should be cache-aligned.
1382 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1383 * @batch: page in which WA are loaded
1384 * @offset: This field specifies the start of this batch.
1385 * This batch is started immediately after indirect_ctx batch. Since we ensure
1386 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1388 * The number of DWORDS written are returned using this field.
1390 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1391 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1393 static int gen8_init_perctx_bb(struct intel_engine_cs *engine,
1394 struct i915_wa_ctx_bb *wa_ctx,
1395 uint32_t *const batch,
1398 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1400 /* WaDisableCtxRestoreArbitration:bdw,chv */
1401 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1403 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1405 return wa_ctx_end(wa_ctx, *offset = index, 1);
1408 static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
1409 struct i915_wa_ctx_bb *wa_ctx,
1410 uint32_t *const batch,
1414 struct drm_device *dev = engine->dev;
1415 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1417 /* WaDisableCtxRestoreArbitration:skl,bxt */
1418 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
1419 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1420 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1422 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1423 ret = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1428 /* Pad to end of cacheline */
1429 while (index % CACHELINE_DWORDS)
1430 wa_ctx_emit(batch, index, MI_NOOP);
1432 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1435 static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
1436 struct i915_wa_ctx_bb *wa_ctx,
1437 uint32_t *const batch,
1440 struct drm_device *dev = engine->dev;
1441 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1443 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1444 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
1445 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1446 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1447 wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1448 wa_ctx_emit(batch, index,
1449 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
1450 wa_ctx_emit(batch, index, MI_NOOP);
1453 /* WaDisableCtxRestoreArbitration:skl,bxt */
1454 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
1455 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1456 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1458 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1460 return wa_ctx_end(wa_ctx, *offset = index, 1);
1463 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
1467 engine->wa_ctx.obj = i915_gem_alloc_object(engine->dev,
1469 if (!engine->wa_ctx.obj) {
1470 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1474 ret = i915_gem_obj_ggtt_pin(engine->wa_ctx.obj, PAGE_SIZE, 0);
1476 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1478 drm_gem_object_unreference(&engine->wa_ctx.obj->base);
1485 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine)
1487 if (engine->wa_ctx.obj) {
1488 i915_gem_object_ggtt_unpin(engine->wa_ctx.obj);
1489 drm_gem_object_unreference(&engine->wa_ctx.obj->base);
1490 engine->wa_ctx.obj = NULL;
1494 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1500 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1502 WARN_ON(engine->id != RCS);
1504 /* update this when WA for higher Gen are added */
1505 if (INTEL_INFO(engine->dev)->gen > 9) {
1506 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1507 INTEL_INFO(engine->dev)->gen);
1511 /* some WA perform writes to scratch page, ensure it is valid */
1512 if (engine->scratch.obj == NULL) {
1513 DRM_ERROR("scratch page not allocated for %s\n", engine->name);
1517 ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE);
1519 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1523 page = i915_gem_object_get_dirty_page(wa_ctx->obj, 0);
1524 batch = kmap_atomic(page);
1527 if (INTEL_INFO(engine->dev)->gen == 8) {
1528 ret = gen8_init_indirectctx_bb(engine,
1529 &wa_ctx->indirect_ctx,
1535 ret = gen8_init_perctx_bb(engine,
1541 } else if (INTEL_INFO(engine->dev)->gen == 9) {
1542 ret = gen9_init_indirectctx_bb(engine,
1543 &wa_ctx->indirect_ctx,
1549 ret = gen9_init_perctx_bb(engine,
1558 kunmap_atomic(batch);
1560 lrc_destroy_wa_ctx_obj(engine);
1565 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1567 struct drm_device *dev = engine->dev;
1568 struct drm_i915_private *dev_priv = dev->dev_private;
1569 unsigned int next_context_status_buffer_hw;
1571 lrc_setup_hardware_status_page(engine,
1572 dev_priv->kernel_context->engine[engine->id].state);
1574 I915_WRITE_IMR(engine,
1575 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1576 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1578 I915_WRITE(RING_MODE_GEN7(engine),
1579 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1580 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1581 POSTING_READ(RING_MODE_GEN7(engine));
1584 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1585 * zero, we need to read the write pointer from hardware and use its
1586 * value because "this register is power context save restored".
1587 * Effectively, these states have been observed:
1589 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1590 * BDW | CSB regs not reset | CSB regs reset |
1591 * CHT | CSB regs not reset | CSB regs not reset |
1595 next_context_status_buffer_hw =
1596 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine)));
1599 * When the CSB registers are reset (also after power-up / gpu reset),
1600 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1601 * this special case, so the first element read is CSB[0].
1603 if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK)
1604 next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1);
1606 engine->next_context_status_buffer = next_context_status_buffer_hw;
1607 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1609 intel_engine_init_hangcheck(engine);
1614 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1616 struct drm_device *dev = engine->dev;
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1620 ret = gen8_init_common_ring(engine);
1624 /* We need to disable the AsyncFlip performance optimisations in order
1625 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1626 * programmed to '1' on all products.
1628 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1630 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1632 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1634 return init_workarounds_ring(engine);
1637 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1641 ret = gen8_init_common_ring(engine);
1645 return init_workarounds_ring(engine);
1648 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1650 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1651 struct intel_engine_cs *engine = req->engine;
1652 struct intel_ringbuffer *ringbuf = req->ringbuf;
1653 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1656 ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2);
1660 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1661 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1662 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1664 intel_logical_ring_emit_reg(ringbuf,
1665 GEN8_RING_PDP_UDW(engine, i));
1666 intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
1667 intel_logical_ring_emit_reg(ringbuf,
1668 GEN8_RING_PDP_LDW(engine, i));
1669 intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
1672 intel_logical_ring_emit(ringbuf, MI_NOOP);
1673 intel_logical_ring_advance(ringbuf);
1678 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1679 u64 offset, unsigned dispatch_flags)
1681 struct intel_ringbuffer *ringbuf = req->ringbuf;
1682 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1685 /* Don't rely in hw updating PDPs, specially in lite-restore.
1686 * Ideally, we should set Force PD Restore in ctx descriptor,
1687 * but we can't. Force Restore would be a second option, but
1688 * it is unsafe in case of lite-restore (because the ctx is
1689 * not idle). PML4 is allocated during ppgtt init so this is
1690 * not needed in 48-bit.*/
1691 if (req->ctx->ppgtt &&
1692 (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
1693 if (!USES_FULL_48BIT_PPGTT(req->i915) &&
1694 !intel_vgpu_active(req->i915->dev)) {
1695 ret = intel_logical_ring_emit_pdps(req);
1700 req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1703 ret = intel_logical_ring_begin(req, 4);
1707 /* FIXME(BDW): Address space and security selectors. */
1708 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
1710 (dispatch_flags & I915_DISPATCH_RS ?
1711 MI_BATCH_RESOURCE_STREAMER : 0));
1712 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1713 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1714 intel_logical_ring_emit(ringbuf, MI_NOOP);
1715 intel_logical_ring_advance(ringbuf);
1720 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
1722 struct drm_device *dev = engine->dev;
1723 struct drm_i915_private *dev_priv = dev->dev_private;
1724 unsigned long flags;
1726 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1729 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1730 if (engine->irq_refcount++ == 0) {
1731 I915_WRITE_IMR(engine,
1732 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1733 POSTING_READ(RING_IMR(engine->mmio_base));
1735 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1740 static void gen8_logical_ring_put_irq(struct intel_engine_cs *engine)
1742 struct drm_device *dev = engine->dev;
1743 struct drm_i915_private *dev_priv = dev->dev_private;
1744 unsigned long flags;
1746 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1747 if (--engine->irq_refcount == 0) {
1748 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1749 POSTING_READ(RING_IMR(engine->mmio_base));
1751 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1754 static int gen8_emit_flush(struct drm_i915_gem_request *request,
1755 u32 invalidate_domains,
1758 struct intel_ringbuffer *ringbuf = request->ringbuf;
1759 struct intel_engine_cs *engine = ringbuf->engine;
1760 struct drm_device *dev = engine->dev;
1761 struct drm_i915_private *dev_priv = dev->dev_private;
1765 ret = intel_logical_ring_begin(request, 4);
1769 cmd = MI_FLUSH_DW + 1;
1771 /* We always require a command barrier so that subsequent
1772 * commands, such as breadcrumb interrupts, are strictly ordered
1773 * wrt the contents of the write cache being flushed to memory
1774 * (and thus being coherent from the CPU).
1776 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1778 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1779 cmd |= MI_INVALIDATE_TLB;
1780 if (engine == &dev_priv->engine[VCS])
1781 cmd |= MI_INVALIDATE_BSD;
1784 intel_logical_ring_emit(ringbuf, cmd);
1785 intel_logical_ring_emit(ringbuf,
1786 I915_GEM_HWS_SCRATCH_ADDR |
1787 MI_FLUSH_DW_USE_GTT);
1788 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1789 intel_logical_ring_emit(ringbuf, 0); /* value */
1790 intel_logical_ring_advance(ringbuf);
1795 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1796 u32 invalidate_domains,
1799 struct intel_ringbuffer *ringbuf = request->ringbuf;
1800 struct intel_engine_cs *engine = ringbuf->engine;
1801 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1802 bool vf_flush_wa = false;
1806 flags |= PIPE_CONTROL_CS_STALL;
1808 if (flush_domains) {
1809 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1810 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1811 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1812 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1815 if (invalidate_domains) {
1816 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1817 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1818 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1819 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1820 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1821 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1822 flags |= PIPE_CONTROL_QW_WRITE;
1823 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1826 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1829 if (IS_GEN9(engine->dev))
1833 ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
1838 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1839 intel_logical_ring_emit(ringbuf, 0);
1840 intel_logical_ring_emit(ringbuf, 0);
1841 intel_logical_ring_emit(ringbuf, 0);
1842 intel_logical_ring_emit(ringbuf, 0);
1843 intel_logical_ring_emit(ringbuf, 0);
1846 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1847 intel_logical_ring_emit(ringbuf, flags);
1848 intel_logical_ring_emit(ringbuf, scratch_addr);
1849 intel_logical_ring_emit(ringbuf, 0);
1850 intel_logical_ring_emit(ringbuf, 0);
1851 intel_logical_ring_emit(ringbuf, 0);
1852 intel_logical_ring_advance(ringbuf);
1857 static u32 gen8_get_seqno(struct intel_engine_cs *engine, bool lazy_coherency)
1859 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1862 static void gen8_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1864 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1867 static u32 bxt_a_get_seqno(struct intel_engine_cs *engine,
1868 bool lazy_coherency)
1872 * On BXT A steppings there is a HW coherency issue whereby the
1873 * MI_STORE_DATA_IMM storing the completed request's seqno
1874 * occasionally doesn't invalidate the CPU cache. Work around this by
1875 * clflushing the corresponding cacheline whenever the caller wants
1876 * the coherency to be guaranteed. Note that this cacheline is known
1877 * to be clean at this point, since we only write it in
1878 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1879 * this clflush in practice becomes an invalidate operation.
1882 if (!lazy_coherency)
1883 intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1885 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1888 static void bxt_a_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1890 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1892 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1893 intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1897 * Reserve space for 2 NOOPs at the end of each request to be
1898 * used as a workaround for not being allowed to do lite
1899 * restore with HEAD==TAIL (WaIdleLiteRestore).
1901 #define WA_TAIL_DWORDS 2
1903 static inline u32 hws_seqno_address(struct intel_engine_cs *engine)
1905 return engine->status_page.gfx_addr + I915_GEM_HWS_INDEX_ADDR;
1908 static int gen8_emit_request(struct drm_i915_gem_request *request)
1910 struct intel_ringbuffer *ringbuf = request->ringbuf;
1913 ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS);
1917 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1918 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1920 intel_logical_ring_emit(ringbuf,
1921 (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
1922 intel_logical_ring_emit(ringbuf,
1923 hws_seqno_address(request->engine) |
1924 MI_FLUSH_DW_USE_GTT);
1925 intel_logical_ring_emit(ringbuf, 0);
1926 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1927 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1928 intel_logical_ring_emit(ringbuf, MI_NOOP);
1929 return intel_logical_ring_advance_and_submit(request);
1932 static int gen8_emit_request_render(struct drm_i915_gem_request *request)
1934 struct intel_ringbuffer *ringbuf = request->ringbuf;
1937 ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS);
1941 /* w/a for post sync ops following a GPGPU operation we
1942 * need a prior CS_STALL, which is emitted by the flush
1943 * following the batch.
1945 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5));
1946 intel_logical_ring_emit(ringbuf,
1947 (PIPE_CONTROL_GLOBAL_GTT_IVB |
1948 PIPE_CONTROL_CS_STALL |
1949 PIPE_CONTROL_QW_WRITE));
1950 intel_logical_ring_emit(ringbuf, hws_seqno_address(request->engine));
1951 intel_logical_ring_emit(ringbuf, 0);
1952 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1953 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1954 return intel_logical_ring_advance_and_submit(request);
1957 static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
1959 struct render_state so;
1962 ret = i915_gem_render_state_prepare(req->engine, &so);
1966 if (so.rodata == NULL)
1969 ret = req->engine->emit_bb_start(req, so.ggtt_offset,
1970 I915_DISPATCH_SECURE);
1974 ret = req->engine->emit_bb_start(req,
1975 (so.ggtt_offset + so.aux_batch_offset),
1976 I915_DISPATCH_SECURE);
1980 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
1983 i915_gem_render_state_fini(&so);
1987 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1991 ret = intel_logical_ring_workarounds_emit(req);
1995 ret = intel_rcs_context_init_mocs(req);
1997 * Failing to program the MOCS is non-fatal.The system will not
1998 * run at peak performance. So generate an error and carry on.
2001 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
2003 return intel_lr_context_render_state_init(req);
2007 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
2009 * @ring: Engine Command Streamer.
2012 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
2014 struct drm_i915_private *dev_priv;
2016 if (!intel_engine_initialized(engine))
2019 dev_priv = engine->dev->dev_private;
2021 if (engine->buffer) {
2022 intel_logical_ring_stop(engine);
2023 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
2026 if (engine->cleanup)
2027 engine->cleanup(engine);
2029 i915_cmd_parser_fini_ring(engine);
2030 i915_gem_batch_pool_fini(&engine->batch_pool);
2032 if (engine->status_page.obj) {
2033 kunmap(sg_page(engine->status_page.obj->pages->sgl));
2034 engine->status_page.obj = NULL;
2037 engine->idle_lite_restore_wa = 0;
2038 engine->disable_lite_restore_wa = false;
2039 engine->ctx_desc_template = 0;
2041 lrc_destroy_wa_ctx_obj(engine);
2046 logical_ring_default_vfuncs(struct drm_device *dev,
2047 struct intel_engine_cs *engine)
2049 /* Default vfuncs which can be overriden by each engine. */
2050 engine->init_hw = gen8_init_common_ring;
2051 engine->emit_request = gen8_emit_request;
2052 engine->emit_flush = gen8_emit_flush;
2053 engine->irq_get = gen8_logical_ring_get_irq;
2054 engine->irq_put = gen8_logical_ring_put_irq;
2055 engine->emit_bb_start = gen8_emit_bb_start;
2056 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
2057 engine->get_seqno = bxt_a_get_seqno;
2058 engine->set_seqno = bxt_a_set_seqno;
2060 engine->get_seqno = gen8_get_seqno;
2061 engine->set_seqno = gen8_set_seqno;
2066 logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift)
2068 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
2069 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
2073 logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine)
2075 struct intel_context *dctx = to_i915(dev)->kernel_context;
2078 /* Intentionally left blank. */
2079 engine->buffer = NULL;
2082 INIT_LIST_HEAD(&engine->active_list);
2083 INIT_LIST_HEAD(&engine->request_list);
2084 i915_gem_batch_pool_init(dev, &engine->batch_pool);
2085 init_waitqueue_head(&engine->irq_queue);
2087 INIT_LIST_HEAD(&engine->buffers);
2088 INIT_LIST_HEAD(&engine->execlist_queue);
2089 INIT_LIST_HEAD(&engine->execlist_retired_req_list);
2090 spin_lock_init(&engine->execlist_lock);
2092 logical_ring_init_platform_invariants(engine);
2094 ret = i915_cmd_parser_init_ring(engine);
2098 ret = intel_lr_context_deferred_alloc(dctx, engine);
2102 /* As this is the default context, always pin it */
2103 ret = intel_lr_context_do_pin(dctx, engine);
2106 "Failed to pin and map ringbuffer %s: %d\n",
2114 intel_logical_ring_cleanup(engine);
2118 static int logical_render_ring_init(struct drm_device *dev)
2120 struct drm_i915_private *dev_priv = dev->dev_private;
2121 struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2124 engine->name = "render ring";
2126 engine->exec_id = I915_EXEC_RENDER;
2127 engine->guc_id = GUC_RENDER_ENGINE;
2128 engine->mmio_base = RENDER_RING_BASE;
2130 logical_ring_default_irqs(engine, GEN8_RCS_IRQ_SHIFT);
2131 if (HAS_L3_DPF(dev))
2132 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2134 logical_ring_default_vfuncs(dev, engine);
2136 /* Override some for render ring. */
2137 if (INTEL_INFO(dev)->gen >= 9)
2138 engine->init_hw = gen9_init_render_ring;
2140 engine->init_hw = gen8_init_render_ring;
2141 engine->init_context = gen8_init_rcs_context;
2142 engine->cleanup = intel_fini_pipe_control;
2143 engine->emit_flush = gen8_emit_flush_render;
2144 engine->emit_request = gen8_emit_request_render;
2148 ret = intel_init_pipe_control(engine);
2152 ret = intel_init_workaround_bb(engine);
2155 * We continue even if we fail to initialize WA batch
2156 * because we only expect rare glitches but nothing
2157 * critical to prevent us from using GPU
2159 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2163 ret = logical_ring_init(dev, engine);
2165 lrc_destroy_wa_ctx_obj(engine);
2171 static int logical_bsd_ring_init(struct drm_device *dev)
2173 struct drm_i915_private *dev_priv = dev->dev_private;
2174 struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2176 engine->name = "bsd ring";
2178 engine->exec_id = I915_EXEC_BSD;
2179 engine->guc_id = GUC_VIDEO_ENGINE;
2180 engine->mmio_base = GEN6_BSD_RING_BASE;
2182 logical_ring_default_irqs(engine, GEN8_VCS1_IRQ_SHIFT);
2183 logical_ring_default_vfuncs(dev, engine);
2185 return logical_ring_init(dev, engine);
2188 static int logical_bsd2_ring_init(struct drm_device *dev)
2190 struct drm_i915_private *dev_priv = dev->dev_private;
2191 struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
2193 engine->name = "bsd2 ring";
2195 engine->exec_id = I915_EXEC_BSD;
2196 engine->guc_id = GUC_VIDEO_ENGINE2;
2197 engine->mmio_base = GEN8_BSD2_RING_BASE;
2199 logical_ring_default_irqs(engine, GEN8_VCS2_IRQ_SHIFT);
2200 logical_ring_default_vfuncs(dev, engine);
2202 return logical_ring_init(dev, engine);
2205 static int logical_blt_ring_init(struct drm_device *dev)
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct intel_engine_cs *engine = &dev_priv->engine[BCS];
2210 engine->name = "blitter ring";
2212 engine->exec_id = I915_EXEC_BLT;
2213 engine->guc_id = GUC_BLITTER_ENGINE;
2214 engine->mmio_base = BLT_RING_BASE;
2216 logical_ring_default_irqs(engine, GEN8_BCS_IRQ_SHIFT);
2217 logical_ring_default_vfuncs(dev, engine);
2219 return logical_ring_init(dev, engine);
2222 static int logical_vebox_ring_init(struct drm_device *dev)
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 struct intel_engine_cs *engine = &dev_priv->engine[VECS];
2227 engine->name = "video enhancement ring";
2229 engine->exec_id = I915_EXEC_VEBOX;
2230 engine->guc_id = GUC_VIDEOENHANCE_ENGINE;
2231 engine->mmio_base = VEBOX_RING_BASE;
2233 logical_ring_default_irqs(engine, GEN8_VECS_IRQ_SHIFT);
2234 logical_ring_default_vfuncs(dev, engine);
2236 return logical_ring_init(dev, engine);
2240 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2243 * This function inits the engines for an Execlists submission style (the equivalent in the
2244 * legacy ringbuffer submission world would be i915_gem_init_engines). It does it only for
2245 * those engines that are present in the hardware.
2247 * Return: non-zero if the initialization failed.
2249 int intel_logical_rings_init(struct drm_device *dev)
2251 struct drm_i915_private *dev_priv = dev->dev_private;
2254 ret = logical_render_ring_init(dev);
2259 ret = logical_bsd_ring_init(dev);
2261 goto cleanup_render_ring;
2265 ret = logical_blt_ring_init(dev);
2267 goto cleanup_bsd_ring;
2270 if (HAS_VEBOX(dev)) {
2271 ret = logical_vebox_ring_init(dev);
2273 goto cleanup_blt_ring;
2276 if (HAS_BSD2(dev)) {
2277 ret = logical_bsd2_ring_init(dev);
2279 goto cleanup_vebox_ring;
2285 intel_logical_ring_cleanup(&dev_priv->engine[VECS]);
2287 intel_logical_ring_cleanup(&dev_priv->engine[BCS]);
2289 intel_logical_ring_cleanup(&dev_priv->engine[VCS]);
2290 cleanup_render_ring:
2291 intel_logical_ring_cleanup(&dev_priv->engine[RCS]);
2297 make_rpcs(struct drm_device *dev)
2302 * No explicit RPCS request is needed to ensure full
2303 * slice/subslice/EU enablement prior to Gen9.
2305 if (INTEL_INFO(dev)->gen < 9)
2309 * Starting in Gen9, render power gating can leave
2310 * slice/subslice/EU in a partially enabled state. We
2311 * must make an explicit request through RPCS for full
2314 if (INTEL_INFO(dev)->has_slice_pg) {
2315 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2316 rpcs |= INTEL_INFO(dev)->slice_total <<
2317 GEN8_RPCS_S_CNT_SHIFT;
2318 rpcs |= GEN8_RPCS_ENABLE;
2321 if (INTEL_INFO(dev)->has_subslice_pg) {
2322 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2323 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
2324 GEN8_RPCS_SS_CNT_SHIFT;
2325 rpcs |= GEN8_RPCS_ENABLE;
2328 if (INTEL_INFO(dev)->has_eu_pg) {
2329 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2330 GEN8_RPCS_EU_MIN_SHIFT;
2331 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2332 GEN8_RPCS_EU_MAX_SHIFT;
2333 rpcs |= GEN8_RPCS_ENABLE;
2339 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2341 u32 indirect_ctx_offset;
2343 switch (INTEL_INFO(engine->dev)->gen) {
2345 MISSING_CASE(INTEL_INFO(engine->dev)->gen);
2348 indirect_ctx_offset =
2349 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2352 indirect_ctx_offset =
2353 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2357 return indirect_ctx_offset;
2361 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
2362 struct intel_engine_cs *engine,
2363 struct intel_ringbuffer *ringbuf)
2365 struct drm_device *dev = engine->dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2369 uint32_t *reg_state;
2373 ppgtt = dev_priv->mm.aliasing_ppgtt;
2375 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2377 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2381 ret = i915_gem_object_get_pages(ctx_obj);
2383 DRM_DEBUG_DRIVER("Could not get object pages\n");
2387 i915_gem_object_pin_pages(ctx_obj);
2389 /* The second page of the context object contains some fields which must
2390 * be set up prior to the first execution. */
2391 page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
2392 reg_state = kmap_atomic(page);
2394 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2395 * commands followed by (reg, value) pairs. The values we are setting here are
2396 * only for the first context restore: on a subsequent save, the GPU will
2397 * recreate this batchbuffer with new values (including all the missing
2398 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2399 reg_state[CTX_LRI_HEADER_0] =
2400 MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
2401 ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL,
2402 RING_CONTEXT_CONTROL(engine),
2403 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2404 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2405 (HAS_RESOURCE_STREAMER(dev) ?
2406 CTX_CTRL_RS_CTX_ENABLE : 0)));
2407 ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
2409 ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base),
2411 /* Ring buffer start address is not known until the buffer is pinned.
2412 * It is written to the context image in execlists_update_context()
2414 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START,
2415 RING_START(engine->mmio_base), 0);
2416 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
2417 RING_CTL(engine->mmio_base),
2418 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
2419 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
2420 RING_BBADDR_UDW(engine->mmio_base), 0);
2421 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
2422 RING_BBADDR(engine->mmio_base), 0);
2423 ASSIGN_CTX_REG(reg_state, CTX_BB_STATE,
2424 RING_BBSTATE(engine->mmio_base),
2426 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U,
2427 RING_SBBADDR_UDW(engine->mmio_base), 0);
2428 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L,
2429 RING_SBBADDR(engine->mmio_base), 0);
2430 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE,
2431 RING_SBBSTATE(engine->mmio_base), 0);
2432 if (engine->id == RCS) {
2433 ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR,
2434 RING_BB_PER_CTX_PTR(engine->mmio_base), 0);
2435 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX,
2436 RING_INDIRECT_CTX(engine->mmio_base), 0);
2437 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET,
2438 RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0);
2439 if (engine->wa_ctx.obj) {
2440 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2441 uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
2443 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2444 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2445 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2447 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2448 intel_lr_indirect_ctx_offset(engine) << 6;
2450 reg_state[CTX_BB_PER_CTX_PTR+1] =
2451 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2455 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2456 ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP,
2457 RING_CTX_TIMESTAMP(engine->mmio_base), 0);
2458 /* PDP values well be assigned later if needed */
2459 ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3),
2461 ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3),
2463 ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2),
2465 ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2),
2467 ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1),
2469 ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1),
2471 ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
2473 ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
2476 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
2477 /* 64b PPGTT (48bit canonical)
2478 * PDP0_DESCRIPTOR contains the base address to PML4 and
2479 * other PDP Descriptors are ignored.
2481 ASSIGN_CTX_PML4(ppgtt, reg_state);
2484 * PDP*_DESCRIPTOR contains the base address of space supported.
2485 * With dynamic page allocation, PDPs may not be allocated at
2486 * this point. Point the unallocated PDPs to the scratch page
2488 execlists_update_context_pdps(ppgtt, reg_state);
2491 if (engine->id == RCS) {
2492 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2493 ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2497 kunmap_atomic(reg_state);
2498 i915_gem_object_unpin_pages(ctx_obj);
2504 * intel_lr_context_free() - free the LRC specific bits of a context
2505 * @ctx: the LR context to free.
2507 * The real context freeing is done in i915_gem_context_free: this only
2508 * takes care of the bits that are LRC related: the per-engine backing
2509 * objects and the logical ringbuffer.
2511 void intel_lr_context_free(struct intel_context *ctx)
2515 for (i = I915_NUM_ENGINES; --i >= 0; ) {
2516 struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
2517 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
2522 if (ctx == ctx->i915->kernel_context) {
2523 intel_unpin_ringbuffer_obj(ringbuf);
2524 i915_gem_object_ggtt_unpin(ctx_obj);
2527 WARN_ON(ctx->engine[i].pin_count);
2528 intel_ringbuffer_free(ringbuf);
2529 drm_gem_object_unreference(&ctx_obj->base);
2534 * intel_lr_context_size() - return the size of the context for an engine
2535 * @ring: which engine to find the context size for
2537 * Each engine may require a different amount of space for a context image,
2538 * so when allocating (or copying) an image, this function can be used to
2539 * find the right size for the specific engine.
2541 * Return: size (in bytes) of an engine-specific context image
2543 * Note: this size includes the HWSP, which is part of the context image
2544 * in LRC mode, but does not include the "shared data page" used with
2545 * GuC submission. The caller should account for this if using the GuC.
2547 uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
2551 WARN_ON(INTEL_INFO(engine->dev)->gen < 8);
2553 switch (engine->id) {
2555 if (INTEL_INFO(engine->dev)->gen >= 9)
2556 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2558 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2564 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2571 static void lrc_setup_hardware_status_page(struct intel_engine_cs *engine,
2572 struct drm_i915_gem_object *default_ctx_obj)
2574 struct drm_i915_private *dev_priv = engine->dev->dev_private;
2577 /* The HWSP is part of the default context object in LRC mode. */
2578 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj)
2579 + LRC_PPHWSP_PN * PAGE_SIZE;
2580 page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN);
2581 engine->status_page.page_addr = kmap(page);
2582 engine->status_page.obj = default_ctx_obj;
2584 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
2585 (u32)engine->status_page.gfx_addr);
2586 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
2590 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2591 * @ctx: LR context to create.
2592 * @ring: engine to be used with the context.
2594 * This function can be called more than once, with different engines, if we plan
2595 * to use the context with them. The context backing objects and the ringbuffers
2596 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2597 * the creation is a deferred call: it's better to make sure first that we need to use
2598 * a given ring with the context.
2600 * Return: non-zero on error.
2603 int intel_lr_context_deferred_alloc(struct intel_context *ctx,
2604 struct intel_engine_cs *engine)
2606 struct drm_device *dev = engine->dev;
2607 struct drm_i915_gem_object *ctx_obj;
2608 uint32_t context_size;
2609 struct intel_ringbuffer *ringbuf;
2612 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
2613 WARN_ON(ctx->engine[engine->id].state);
2615 context_size = round_up(intel_lr_context_size(engine), 4096);
2617 /* One extra page as the sharing data between driver and GuC */
2618 context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2620 ctx_obj = i915_gem_alloc_object(dev, context_size);
2622 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2626 ringbuf = intel_engine_create_ringbuffer(engine, 4 * PAGE_SIZE);
2627 if (IS_ERR(ringbuf)) {
2628 ret = PTR_ERR(ringbuf);
2629 goto error_deref_obj;
2632 ret = populate_lr_context(ctx, ctx_obj, engine, ringbuf);
2634 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2638 ctx->engine[engine->id].ringbuf = ringbuf;
2639 ctx->engine[engine->id].state = ctx_obj;
2641 if (ctx != ctx->i915->kernel_context && engine->init_context) {
2642 struct drm_i915_gem_request *req;
2644 req = i915_gem_request_alloc(engine, ctx);
2647 DRM_ERROR("ring create req: %d\n", ret);
2651 ret = engine->init_context(req);
2653 DRM_ERROR("ring init context: %d\n",
2655 i915_gem_request_cancel(req);
2658 i915_add_request_no_flush(req);
2663 intel_ringbuffer_free(ringbuf);
2665 drm_gem_object_unreference(&ctx_obj->base);
2666 ctx->engine[engine->id].ringbuf = NULL;
2667 ctx->engine[engine->id].state = NULL;
2671 void intel_lr_context_reset(struct drm_device *dev,
2672 struct intel_context *ctx)
2674 struct drm_i915_private *dev_priv = dev->dev_private;
2675 struct intel_engine_cs *engine;
2677 for_each_engine(engine, dev_priv) {
2678 struct drm_i915_gem_object *ctx_obj =
2679 ctx->engine[engine->id].state;
2680 struct intel_ringbuffer *ringbuf =
2681 ctx->engine[engine->id].ringbuf;
2682 uint32_t *reg_state;
2688 if (i915_gem_object_get_pages(ctx_obj)) {
2689 WARN(1, "Failed get_pages for context obj\n");
2692 page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
2693 reg_state = kmap_atomic(page);
2695 reg_state[CTX_RING_HEAD+1] = 0;
2696 reg_state[CTX_RING_TAIL+1] = 0;
2698 kunmap_atomic(reg_state);